commit f902fe37f00cc015a1f0c0fd5b4989e8280506e8
Author: Imbis <destruct82@gmail.com>
Date:   Wed May 8 22:31:03 2024 +0900

    Init Commit

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diff --git a/Project/A31G12x_Co2_Sensor_Logger.uvoptx b/Project/A31G12x_Co2_Sensor_Logger.uvoptx
new file mode 100644
index 0000000..702c91f
--- /dev/null
+++ b/Project/A31G12x_Co2_Sensor_Logger.uvoptx
@@ -0,0 +1,916 @@
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+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>53</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Application\FATFS\App\fatfs.c</PathWithFileName>
+      <FilenameWithoutPath>fatfs.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>54</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Application\FATFS\Target\user_diskio.c</PathWithFileName>
+      <FilenameWithoutPath>user_diskio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>55</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Application\FATFS\Target\user_diskio_spi.c</PathWithFileName>
+      <FilenameWithoutPath>user_diskio_spi.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>56</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Application\Middlewares\Third_Party\FatFs\src\diskio.c</PathWithFileName>
+      <FilenameWithoutPath>diskio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>57</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Application\Middlewares\Third_Party\FatFs\src\ff.c</PathWithFileName>
+      <FilenameWithoutPath>ff.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>58</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Application\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c</PathWithFileName>
+      <FilenameWithoutPath>ff_gen_drv.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/Project/A31G12x_Co2_Sensor_Logger.uvprojx b/Project/A31G12x_Co2_Sensor_Logger.uvprojx
new file mode 100644
index 0000000..88eb2a4
--- /dev/null
+++ b/Project/A31G12x_Co2_Sensor_Logger.uvprojx
@@ -0,0 +1,722 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>S_Co2_Sensor_Logger</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>A31G123</Device>
+          <Vendor>ABOV Semiconductor</Vendor>
+          <PackID>ABOV.CM0_DFP.1.0.4</PackID>
+          <PackURL>http://www.abov.co.kr/data/mds/PACK/</PackURL>
+          <Cpu>IRAM(0x20000000,0x1800) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0A31G12x_series_FLASH -FS00 -FL010000 -FF1A31G12x_series_CFG -FS11FFFF200 -FL1600 -FP0($$Device:A31G123$A31G12x\Flashloader\A31G12x_series_FLASH.FLM) -FP1($$Device:A31G123$A31G12x\Flashloader\A31G12x_series_CFG.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:A31G123$A31G12x\Core\include\A31G12x_series.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>.\SDK_V2_5_0\Debugging_Info\SFR\A31G12x.SFR</SFDFile>
+          <bCustSvd>1</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>S_DustSensorView</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x1800</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x10000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x1800</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>1</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>1</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\Application;.\SDK_V2_5_0\Device\Startup;.\SDK_V2_5_0\Drivers\Include;.\SDK_V2_5_0\Drivers\Source;.\SDK_V2_5_0\FlashLoader;.\SDK_V2_5_0\Option;.\SDK_V2_5_0\INI;.\SDK_V2_5_0\Core;.\Application\FATFS\App;.\Application\FATFS\Target;.\Application\Middlewares\Third_Party\FatFs\src;.\Application\Middlewares\Third_Party\FatFs\src\option</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>1</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Application</GroupName>
+          <Files>
+            <File>
+              <FileName>A31G12x_Interrupt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\A31G12x_Interrupt.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_Interrupt.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Application\A31G12x_Interrupt.h</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_SystemClock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\A31G12x_SystemClock.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_SystemClock.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Application\A31G12x_SystemClock.h</FilePath>
+            </File>
+            <File>
+              <FileName>board_config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Application\board_config.h</FilePath>
+            </File>
+            <File>
+              <FileName>define.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Application\define.h</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>dbg_printf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\dbg_printf.c</FilePath>
+            </File>
+            <File>
+              <FileName>sw_timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\sw_timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>systick_timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\systick_timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>ring_buffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\ring_buffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio_state_led.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\gpio_state_led.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio_switch.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\gpio_switch.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart1.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\uart1.c</FilePath>
+            </File>
+            <File>
+              <FileName>segment_74hc595d.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\segment_74hc595d.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer12.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\timer12.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\gpio_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi10.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\spi10.c</FilePath>
+            </File>
+            <File>
+              <FileName>save_file.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\save_file.c</FilePath>
+            </File>
+            <File>
+              <FileName>driver_ds3231.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\driver_ds3231.c</FilePath>
+            </File>
+            <File>
+              <FileName>driver_ds3231_basic.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\driver_ds3231_basic.c</FilePath>
+            </File>
+            <File>
+              <FileName>driver_ds3231_interface_template.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\driver_ds3231_interface_template.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtc_process.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\rtc_process.c</FilePath>
+            </File>
+            <File>
+              <FileName>action_process.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\action_process.c</FilePath>
+            </File>
+            <File>
+              <FileName>eeprom.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\eeprom.c</FilePath>
+            </File>
+            <File>
+              <FileName>buzzer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\buzzer.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio_sensor.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\gpio_sensor.c</FilePath>
+            </File>
+            <File>
+              <FileName>segment.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\segment.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart_packet.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\uart_packet.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Driver</GroupName>
+          <Files>
+            <File>
+              <FileName>A31G12x_hal_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_debug_frmwrk.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_debug_frmwrk.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_fmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_fmc.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_i2cn.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_i2cn.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_intc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_intc.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_lcd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_lcd.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_pcu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_pcu.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_scu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_scu.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_sculv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_sculv.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_timer1n.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_timer1n.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_timer2n.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_timer2n.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_timer3n.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_timer3n.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_uartn.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_uartn.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_usart1n.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_usart1n.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_wdt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_wdt.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x_hal_wt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_wt.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Startup</GroupName>
+          <Files>
+            <File>
+              <FileName>startup_A31G12x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\SDK_V2_5_0\Device\Startup\startup_A31G12x.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Device</GroupName>
+          <Files>
+            <File>
+              <FileName>system_A31G12x.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\SDK_V2_5_0\Device\Startup\system_A31G12x.h</FilePath>
+            </File>
+            <File>
+              <FileName>system_A31G12x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\SDK_V2_5_0\Device\Startup\system_A31G12x.c</FilePath>
+            </File>
+            <File>
+              <FileName>A31G12x.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\SDK_V2_5_0\Device\Startup\A31G12x.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Option</GroupName>
+          <Files>
+            <File>
+              <FileName>option_A31G12x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\SDK_V2_5_0\Option\option_A31G12x.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FATFS</GroupName>
+          <Files>
+            <File>
+              <FileName>fatfs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\FATFS\App\fatfs.c</FilePath>
+            </File>
+            <File>
+              <FileName>user_diskio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\FATFS\Target\user_diskio.c</FilePath>
+            </File>
+            <File>
+              <FileName>user_diskio_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\FATFS\Target\user_diskio_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>diskio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\Middlewares\Third_Party\FatFs\src\diskio.c</FilePath>
+            </File>
+            <File>
+              <FileName>ff.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\Middlewares\Third_Party\FatFs\src\ff.c</FilePath>
+            </File>
+            <File>
+              <FileName>ff_gen_drv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Application\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>A31G12x_Project</LayName>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>
diff --git a/Project/Application/A31G12x_Interrupt.c b/Project/Application/A31G12x_Interrupt.c
new file mode 100644
index 0000000..4c98fe6
--- /dev/null
+++ b/Project/Application/A31G12x_Interrupt.c
@@ -0,0 +1,89 @@
+/***************************************************************************//**
+* @file     A31G12x_it.c
+* @brief    Contains all functions support for Exception & Interrupt Handler on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+*//****************************************************************************/
+
+#include "A31G12x_Interrupt.h"
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private define ----------------------------------------------------------- */
+/* Private function prototypes ---------------------------------------------- */
+/* Private variables -------------------------------------------------------- */
+
+
+
+
+/******************************************************************************/
+/*            Cortex M0+ Processor Exceptions Handlers                        */
+/******************************************************************************/
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         This function handles NMI exception.
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void NMI_Handler( void )
+{
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         This function handles Hard Fault exception.
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void HardFault_Handler( void )
+{
+   /* Go to infinite loop when Hard Fault exception occurs */
+   while( 1 )
+   {
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         This function handles SVCall exception
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void SVC_Handler( void )
+{
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         This function handles PendSVC exception
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void PendSV_Handler( void )
+{
+}
+
+
+/******************************************************************************/
+/*                 A31G12x Peripherals Interrupt Handlers                     */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_A31G12x.s).                                                 */
+/******************************************************************************/
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Project/Application/A31G12x_Interrupt.h b/Project/Application/A31G12x_Interrupt.h
new file mode 100644
index 0000000..6ba7e56
--- /dev/null
+++ b/Project/Application/A31G12x_Interrupt.h
@@ -0,0 +1,52 @@
+/** \file A31G12x_Interrupt.h */ 
+
+/***************************************************************************//**
+* @file     A31G12x_it.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for Exception & Interrupt Handler on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+*//****************************************************************************/
+
+/* Define to prevent recursive inclusion ------------------------------------ */
+#if !defined(A31G12X_INTERRUPT_H__8AA39883_A129_473E_A344_853E2B3D652F__INCLUDED_)
+#define A31G12X_INTERRUPT_H__8AA39883_A129_473E_A344_853E2B3D652F__INCLUDED_
+
+/* Includes ----------------------------------------------------------------- */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ----------------------------------------------------------- */
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+
+
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler( void );
+void HardFault_Handler( void );
+void MemManage_Handler( void );
+void BusFault_Handler( void );
+void UsageFault_Handler( void );
+void SVC_Handler( void );
+void DebugMon_Handler( void );
+void PendSV_Handler( void );
+void SysTick_Handler( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* __A31G12x_IT_H */
+
+
+
diff --git a/Project/Application/A31G12x_SystemClock.c b/Project/Application/A31G12x_SystemClock.c
new file mode 100644
index 0000000..d58a6de
--- /dev/null
+++ b/Project/Application/A31G12x_SystemClock.c
@@ -0,0 +1,126 @@
+
+
+/***************************************************************************//**
+* @file     A31G12x_SystemClock.c
+* @brief    Contains all functions support for Example Code on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+*//****************************************************************************/
+/*******************************************************************************
+ *                          A31G12x Device
+ *------------------------------------------------------------------------
+ *    System Clock source       | High Speend Internal oscillator
+ *------------------------------------------------------------------------
+ *    SYSCLK(MHz)               | 40MHz
+ *------------------------------------------------------------------------
+ *    HCLK(MHz) - Core Clock    | 40MHz
+ *------------------------------------------------------------------------
+ *    PCLK(MHz) - Peri Clock    | 40MHz
+ *------------------------------------------------------------------------
+ ******************************************************************************/
+
+#include "A31G12x_SystemClock.h"
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+
+
+/* Private define ----------------------------------------------------------- */
+
+// Main Clock Selection: Select only one of the following.
+#define USED_HIRC       /*  HIRC  :  40000000uL */
+//#define USED_WDTRC      /*  WDTRC :  40000uL */
+//#define USED_XMOSC      /*  XMOSC :  16000000uL */
+//#define USED_XSOSC      /*  XSOSC :  32768uL */
+
+/* Clock Out Selection ( Monitoring ) */
+/*#define USED_CLKO*/
+
+
+/* Private function prototypes ---------------------------------------------- */
+
+void SystemClock_Config( void );
+
+
+/* Private variables -------------------------------------------------------- */
+
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize default clock for A31G12x Board
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void System_Clock_Initialization( void )
+{
+    uint32_t    i;
+
+    // enable clock source
+    HAL_SCU_ClockSource_Enable( CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN | CLKSRCR_WDTRCEN, HIRCSEL_HIRC1 );
+    for( i = 0; i < 1000; i++ );  // Clock Stable Time
+
+    // select system clock
+#ifdef USED_WDTRC
+    HAL_SCU_SystemClockDivider( WLDIV_MCLK64 | HDIV_MCLK1, SYSTDIV_HCLK1 | PDIV_HCLK1 );  // WT/LCD | HCLK, SysTick | PCLK
+    HAL_SCU_SystemClockChange( MCLKSEL_WDTRC );
+
+    SystemCoreClock = 40000uL;    // HCLK
+    SystemPeriClock = 40000uL;    // PCLK
+#endif
+
+#ifdef USED_XSOSC
+    HAL_SCU_SystemClockDivider( WLDIV_MCLK64 | HDIV_MCLK1, SYSTDIV_HCLK1 | PDIV_HCLK1 );  // WT/LCD | HCLK, SysTick | PCLK
+    HAL_SCU_SystemClockChange( MCLKSEL_XSOSC );
+
+    SystemCoreClock = 32768uL;    // HCLK
+    SystemPeriClock = 32768uL;    // PCLK
+#endif
+
+#ifdef USED_XMOSC
+    HAL_SCU_SystemClockChange( MCLKSEL_XMOSC );
+    HAL_SCU_SystemClockDivider( WLDIV_MCLK64 | HDIV_MCLK1, SYSTDIV_HCLK1 | PDIV_HCLK1 );  // WT/LCD | HCLK, SysTick | PCLK
+
+    SystemCoreClock = 16000000uL;    // HCLK
+    SystemPeriClock = 16000000uL;    // PCLK
+#endif
+
+#ifdef USED_HIRC
+    HAL_SCU_SystemClockChange( MCLKSEL_HIRC );
+    HAL_SCU_SystemClockDivider( WLDIV_MCLK64 | HDIV_MCLK1, SYSTDIV_HCLK1 | PDIV_HCLK1 );  // WT/LCD | HCLK, SysTick | PCLK
+
+    SystemCoreClock = 40000000uL;    // HCLK
+    SystemPeriClock = 40000000uL;    // PCLK
+#endif
+
+    // disable unused clock source
+    //HAL_SCU_ClockSource_Disable( CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN );
+
+    // enable clock monitoring
+    HAL_SCU_ClockMonitoring( MACTS_SysClkChg, MONCS_MCLK );
+
+    // enable clock output
+#ifdef USED_CLKO
+    HAL_SCU_CLKO_PinConfig();
+    HAL_SCU_ClockOutput( CLKOS_MCLK, POLSEL_Low, CLKODIV_SelectedClock1 );
+#endif
+    HAL_SCU_Peripheral_ClockConfig(0x00003FuL, 0x000000L);	// Enable All Ports,
+}
+
+void Systick_Initialization(uint32_t SysticTime)
+{
+    if(SysticTime > 1000)
+    {
+        SysticTime = 1000;
+    }
+    SysTick_Config( SystemCoreClock / (1000 / SysticTime) );
+}
+
diff --git a/Project/Application/A31G12x_SystemClock.h b/Project/Application/A31G12x_SystemClock.h
new file mode 100644
index 0000000..32d7a42
--- /dev/null
+++ b/Project/Application/A31G12x_SystemClock.h
@@ -0,0 +1,11 @@
+/** \file A31G12x_SystemClock.h */ 
+#if !defined(A31G12X_SYSTEMCLOCK_H__CC394B1C_0861_4187_A351_DE0A4FCEDED0__INCLUDED_)
+#define A31G12X_SYSTEMCLOCK_H__CC394B1C_0861_4187_A351_DE0A4FCEDED0__INCLUDED_
+
+#include "define.h"
+
+
+void System_Clock_Initialization( void );
+void Systick_Initialization(uint32_t SysticTime);
+
+#endif
diff --git a/Project/Application/FATFS/App/fatfs.c b/Project/Application/FATFS/App/fatfs.c
new file mode 100644
index 0000000..6185cc2
--- /dev/null
+++ b/Project/Application/FATFS/App/fatfs.c
@@ -0,0 +1,56 @@
+/**
+  ******************************************************************************
+  * @file   fatfs.c
+  * @brief  Code for fatfs applications
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+#include "fatfs.h"
+
+uint8_t retUSER;    /* Return value for USER */
+char USERPath[4];   /* USER logical drive path */
+FATFS USERFatFS;    /* File system object for USER logical drive */
+FIL USERFile;       /* File object for USER */
+
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+void MX_FATFS_Init(void)
+{
+  /*## FatFS: Link the USER driver ###########################*/
+  retUSER = FATFS_LinkDriver(&USER_Driver, USERPath);
+
+  /* USER CODE BEGIN Init */
+  /* additional user code for init */
+  /* USER CODE END Init */
+}
+
+/**
+  * @brief  Gets Time from RTC
+  * @param  None
+  * @retval Time in DWORD
+  */
+DWORD get_fattime(void)
+{
+  /* USER CODE BEGIN get_fattime */
+  return 0;
+  /* USER CODE END get_fattime */
+}
+
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Project/Application/FATFS/App/fatfs.h b/Project/Application/FATFS/App/fatfs.h
new file mode 100644
index 0000000..6f5c0a7
--- /dev/null
+++ b/Project/Application/FATFS/App/fatfs.h
@@ -0,0 +1,49 @@
+/**
+  ******************************************************************************
+  * @file   fatfs.h
+  * @brief  Header for fatfs applications
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __fatfs_H
+#define __fatfs_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ff.h"
+#include "ff_gen_drv.h"
+#include "user_diskio.h" /* defines USER_Driver as external */
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern uint8_t retUSER; /* Return value for USER */
+extern char USERPath[4]; /* USER logical drive path */
+extern FATFS USERFatFS; /* File system object for USER logical drive */
+extern FIL USERFile; /* File object for USER */
+
+void MX_FATFS_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+#ifdef __cplusplus
+}
+#endif
+#endif /*__fatfs_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Project/Application/FATFS/Target/ffconf.h b/Project/Application/FATFS/Target/ffconf.h
new file mode 100644
index 0000000..f7fdd3d
--- /dev/null
+++ b/Project/Application/FATFS/Target/ffconf.h
@@ -0,0 +1,275 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  *  FatFs - FAT file system module configuration file  R0.11 (C)ChaN, 2015
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+#ifndef _FFCONF
+#define _FFCONF 32020	/* Revision ID */
+
+/*-----------------------------------------------------------------------------/
+/ Additional user header to be used
+/-----------------------------------------------------------------------------*/
+#include "main.h"
+
+
+/*-----------------------------------------------------------------------------/
+/ Functions and Buffer Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _FS_TINY             0      /* 0:Normal or 1:Tiny */
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of the file object (FIL) is reduced _MAX_SS
+/  bytes. Instead of private sector buffer eliminated from the file object,
+/  common sector buffer in the file system object (FATFS) is used for the file
+/  data transfer. */
+
+#define _FS_READONLY         0      /* 0:Read/Write or 1:Read only */
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+#define _FS_MINIMIZE         0      /* 0 to 3 */
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: All basic functions are enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(),
+/      f_truncate() and f_rename() function are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+#define _USE_STRFUNC         2      /* 0:Disable or 1-2:Enable */
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/  0: Disable string functions.
+/  1: Enable without LF-CRLF conversion.
+/  2: Enable with LF-CRLF conversion. */
+
+#define _USE_FIND            0
+/* This option switches filtered directory read feature and related functions,
+/  f_findfirst() and f_findnext(). (0:Disable or 1:Enable) */
+
+#define _USE_MKFS            1
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+#define _USE_FASTSEEK        1
+/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+
+#define _USE_LABEL           0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+#define _USE_FORWARD         0
+/* This option switches f_forward() function. (0:Disable or 1:Enable)
+/  To enable it, also _FS_TINY need to be set to 1. */
+
+/*-----------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE         850
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect setting of the code page can cause a file open failure.
+/
+/   932  - Japanese Shift_JIS (DBCS, OEM, Windows)
+/   936  - Simplified Chinese GBK (DBCS, OEM, Windows)
+/   949  - Korean (DBCS, OEM, Windows)
+/   950  - Traditional Chinese Big5 (DBCS, OEM, Windows)
+/   1250 - Central Europe (Windows)
+/   1251 - Cyrillic (Windows)
+/   1252 - Latin 1 (Windows)
+/   1253 - Greek (Windows)
+/   1254 - Turkish (Windows)
+/   1255 - Hebrew (Windows)
+/   1256 - Arabic (Windows)
+/   1257 - Baltic (Windows)
+/   1258 - Vietnam (OEM, Windows)
+/   437  - U.S. (OEM)
+/   720  - Arabic (OEM)
+/   737  - Greek (OEM)
+/   775  - Baltic (OEM)
+/   850  - Multilingual Latin 1 (OEM)
+/   858  - Multilingual Latin 1 + Euro (OEM)
+/   852  - Latin 2 (OEM)
+/   855  - Cyrillic (OEM)
+/   866  - Russian (OEM)
+/   857  - Turkish (OEM)
+/   862  - Hebrew (OEM)
+/   874  - Thai (OEM, Windows)
+/   1    - ASCII (No extended character. Valid for only non-LFN configuration.) */
+
+#define _USE_LFN     0    /* 0 to 3 */
+#define _MAX_LFN     255    /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN option switches the LFN feature.
+/
+/   0: Disable LFN feature. _MAX_LFN has no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  When enable the LFN feature, Unicode handling functions (option/unicode.c) must
+/  be added to the project. The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree(), must be added to the project. */
+
+#define _LFN_UNICODE    0 /* 0:ANSI/OEM or 1:Unicode */
+/* This option switches character encoding on the API. (0:ANSI/OEM or 1:Unicode)
+/  To use Unicode string for the path name, enable LFN feature and set _LFN_UNICODE
+/  to 1. This option also affects behavior of string I/O functions. */
+
+#define _STRF_ENCODE    3
+/* When _LFN_UNICODE is 1, this option selects the character encoding on the file to
+/  be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+/
+/  0: ANSI/OEM
+/  1: UTF-16LE
+/  2: UTF-16BE
+/  3: UTF-8
+/
+/  When _LFN_UNICODE is 0, this option has no effect. */
+
+#define _FS_RPATH       0 /* 0 to 2 */
+/* This option configures relative path feature.
+/
+/   0: Disable relative path feature and remove related functions.
+/   1: Enable relative path feature. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+/
+/  Note that directory items read via f_readdir() are affected by this option. */
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES    1
+/* Number of volumes (logical drives) to be used. */
+
+/* USER CODE BEGIN Volumes */
+#define _STR_VOLUME_ID          0	/* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
+#define _VOLUME_STRS            "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* _STR_VOLUME_ID option switches string volume ID feature.
+/  When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/  number in the path name. _VOLUME_STRS defines the drive ID strings for each
+/  logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+/  the drive ID strings are: A-Z and 0-9. */
+/* USER CODE END Volumes */
+
+#define _MULTI_PARTITION     0 /* 0:Single partition, 1:Multiple partition */
+/* This option switches multi-partition feature. By default (0), each logical drive
+/  number is bound to the same physical drive number and only an FAT volume found on
+/  the physical drive will be mounted. When multi-partition feature is enabled (1),
+/  each logical drive number is bound to arbitrary physical drive and partition
+/  listed in the VolToPart[]. Also f_fdisk() funciton will be available. */
+
+#define _MIN_SS    512  /* 512, 1024, 2048 or 4096 */
+#define _MAX_SS    512  /* 512, 1024, 2048 or 4096 */
+/* These options configure the range of sector size to be supported. (512, 1024,
+/  2048 or 4096) Always set both 512 for most systems, all type of memory cards and
+/  harddisk. But a larger value may be required for on-board flash memory and some
+/  type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/  to variable sector size and GET_SECTOR_SIZE command must be implemented to the
+/  disk_ioctl() function. */
+
+#define	_USE_TRIM      0
+/* This option switches ATA-TRIM feature. (0:Disable or 1:Enable)
+/  To enable Trim feature, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+#define _FS_NOFSINFO    0 /* 0,1,2 or 3 */
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_NORTC	0
+#define _NORTC_MON	6
+#define _NORTC_MDAY	4
+#define _NORTC_YEAR	2015
+/* The _FS_NORTC option switches timestamp feature. If the system does not have
+/  an RTC function or valid timestamp is not needed, set _FS_NORTC to 1 to disable
+/  the timestamp feature. All objects modified by FatFs will have a fixed timestamp
+/  defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR.
+/  When timestamp feature is enabled (_FS_NORTC	== 0), get_fattime() function need
+/  to be added to the project to read current time form RTC. _NORTC_MON,
+/  _NORTC_MDAY and _NORTC_YEAR have no effect.
+/  These options have no effect at read-only configuration (_FS_READONLY == 1). */
+
+#define _FS_LOCK    2     /* 0:Disable or >=1:Enable */
+/* The _FS_LOCK option switches file lock feature to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock feature. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock feature. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock feature is independent of re-entrancy. */
+
+#define _FS_REENTRANT    0  /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT      1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t          NULL
+/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this feature.
+/
+/   0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/      function, must be added to the project. Samples are available in
+/      option/syscall.c.
+/
+/  The _FS_TIMEOUT defines timeout period in unit of time tick.
+/  The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  SemaphoreHandle_t and etc.. */
+
+#define _WORD_ACCESS    0 /* 0 or 1 */
+/* The _WORD_ACCESS option is an only platform dependent option. It defines
+/  which access method is used to the word data on the FAT volume.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless under both the following conditions.
+/
+/  * Address misaligned memory access is always allowed to ALL instructions.
+/  * Byte order on the memory is little-endian.
+/
+/  If it is the case, _WORD_ACCESS can also be set to 1 to reduce code size.
+/  Following table shows allowable settings of some processor types.
+/
+/   ARM7TDMI    0           ColdFire    0           V850E       0
+/   Cortex-M3   0           Z80         0/1         V850ES      0/1
+/   Cortex-M0   0           x86         0/1         TLCS-870    0/1
+/   AVR         0/1         RX600(LE)   0/1         TLCS-900    0/1
+/   AVR32       0           RL78        0           R32C        0
+/   PIC18       0/1         SH-2        0           M16C        0/1
+/   PIC24       0           H8S         0           MSP430      0
+/   PIC32       0           H8/300H     0           8051        0/1
+*/
+
+#endif /* _FFCONF */
diff --git a/Project/Application/FATFS/Target/user_diskio.c b/Project/Application/FATFS/Target/user_diskio.c
new file mode 100644
index 0000000..66c058a
--- /dev/null
+++ b/Project/Application/FATFS/Target/user_diskio.c
@@ -0,0 +1,167 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * @file    user_diskio.c
+  * @brief   This file includes a diskio driver skeleton to be completed by the user.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+ /* USER CODE END Header */
+
+#ifdef USE_OBSOLETE_USER_CODE_SECTION_0
+/*
+ * Warning: the user section 0 is no more in use (starting from CubeMx version 4.16.0)
+ * To be suppressed in the future.
+ * Kept to ensure backward compatibility with previous CubeMx versions when
+ * migrating projects.
+ * User code previously added there should be copied in the new user sections before
+ * the section contents can be deleted.
+ */
+/* USER CODE BEGIN 0 */
+/* USER CODE END 0 */
+#endif
+
+/* USER CODE BEGIN DECL */
+
+/* Includes ------------------------------------------------------------------*/
+#include <string.h>
+#include "ff_gen_drv.h"
+#include "user_diskio_spi.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Private variables ---------------------------------------------------------*/
+/* Disk status */
+static volatile DSTATUS Stat = STA_NOINIT;
+
+/* USER CODE END DECL */
+
+/* Private function prototypes -----------------------------------------------*/
+DSTATUS USER_initialize (BYTE pdrv);
+DSTATUS USER_status (BYTE pdrv);
+DRESULT USER_read (BYTE pdrv, BYTE *buff, DWORD sector, UINT count);
+#if _USE_WRITE == 1
+  DRESULT USER_write (BYTE pdrv, const BYTE *buff, DWORD sector, UINT count);
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+  DRESULT USER_ioctl (BYTE pdrv, BYTE cmd, void *buff);
+#endif /* _USE_IOCTL == 1 */
+
+Diskio_drvTypeDef  USER_Driver =
+{
+  USER_initialize,
+  USER_status,
+  USER_read,
+#if  _USE_WRITE
+  USER_write,
+#endif  /* _USE_WRITE == 1 */
+#if  _USE_IOCTL == 1
+  USER_ioctl,
+#endif /* _USE_IOCTL == 1 */
+};
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Initializes a Drive
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS USER_initialize (
+	BYTE pdrv           /* Physical drive nmuber to identify the drive */
+)
+{
+  /* USER CODE BEGIN INIT */
+	return USER_SPI_initialize(pdrv);
+  /* USER CODE END INIT */
+}
+
+/**
+  * @brief  Gets Disk Status
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS USER_status (
+	BYTE pdrv       /* Physical drive number to identify the drive */
+)
+{
+  /* USER CODE BEGIN STATUS */
+	return USER_SPI_status(pdrv);
+  /* USER CODE END STATUS */
+}
+
+/**
+  * @brief  Reads Sector(s)
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+DRESULT USER_read (
+	BYTE pdrv,      /* Physical drive nmuber to identify the drive */
+	BYTE *buff,     /* Data buffer to store read data */
+	DWORD sector,   /* Sector address in LBA */
+	UINT count      /* Number of sectors to read */
+)
+{
+  /* USER CODE BEGIN READ */
+	return USER_SPI_read(pdrv, buff, sector, count);
+  /* USER CODE END READ */
+}
+
+/**
+  * @brief  Writes Sector(s)
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+DRESULT USER_write (
+	BYTE pdrv,          /* Physical drive nmuber to identify the drive */
+	const BYTE *buff,   /* Data to be written */
+	DWORD sector,       /* Sector address in LBA */
+	UINT count          /* Number of sectors to write */
+)
+{
+  /* USER CODE BEGIN WRITE */
+  /* USER CODE HERE */
+	return USER_SPI_write(pdrv, buff, sector, count);
+  /* USER CODE END WRITE */
+}
+#endif /* _USE_WRITE == 1 */
+
+/**
+  * @brief  I/O control operation
+  * @param  pdrv: Physical drive number (0..)
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT USER_ioctl (
+	BYTE pdrv,      /* Physical drive nmuber (0..) */
+	BYTE cmd,       /* Control code */
+	void *buff      /* Buffer to send/receive control data */
+)
+{
+  /* USER CODE BEGIN IOCTL */
+	return USER_SPI_ioctl(pdrv, cmd, buff);
+  /* USER CODE END IOCTL */
+}
+#endif /* _USE_IOCTL == 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Project/Application/FATFS/Target/user_diskio.h b/Project/Application/FATFS/Target/user_diskio.h
new file mode 100644
index 0000000..d4cb322
--- /dev/null
+++ b/Project/Application/FATFS/Target/user_diskio.h
@@ -0,0 +1,47 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * @file    user_diskio.h
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the user_diskio driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+ /* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USER_DISKIO_H
+#define __USER_DISKIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* USER CODE BEGIN 0 */
+
+/* Includes ------------------------------------------------------------------*/
+#include "user_diskio_spi.h"
+ /* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+extern Diskio_drvTypeDef  USER_Driver;
+
+/* USER CODE END 0 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USER_DISKIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Project/Application/FATFS/Target/user_diskio_spi.c b/Project/Application/FATFS/Target/user_diskio_spi.c
new file mode 100644
index 0000000..b93b284
--- /dev/null
+++ b/Project/Application/FATFS/Target/user_diskio_spi.c
@@ -0,0 +1,551 @@
+/**
+ ******************************************************************************
+  * @file    user_diskio_spi.c
+  * @brief   This file contains the implementation of the user_diskio_spi FatFs
+  *          driver.
+  ******************************************************************************
+  * Portions copyright (C) 2014, ChaN, all rights reserved.
+  * Portions copyright (C) 2017, kiwih, all rights reserved.
+  *
+  * This software is a free software and there is NO WARRANTY.
+  * No restriction on use. You can use, modify and redistribute it for
+  * personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+  * Redistributions of source code must retain the above copyright notice.
+  *
+  ******************************************************************************
+  */
+
+//This code was ported by kiwih from a copywrited (C) library written by ChaN
+//available at http://elm-chan.org/fsw/ff/ffsample.zip
+//(text at http://elm-chan.org/fsw/ff/00index_e.html)
+
+//This file provides the FatFs driver functions and SPI code required to manage
+//an SPI-connected MMC or compatible SD card with FAT
+
+//It is designed to be wrapped by a cubemx generated user_diskio.c file.
+
+
+#include "user_diskio_spi.h"
+#include "spi10.h"
+
+
+//Make sure you set #define SD_SPI_HANDLE as some hspix in main.h
+//Make sure you set #define SD_CS_GPIO_Port as some GPIO port in main.h
+//Make sure you set #define SD_CS_Pin as some GPIO pin in main.h
+
+
+/* Function prototypes */
+
+//(Note that the _256 is used as a mask to clear the prescalar bits as it provides binary 111 in the correct position)
+#define FCLK_SLOW() { SPI10_Initialization(250000, SPI10_MODE0, false); }	/* Set SCLK = slow, approx 280 KBits/s*/
+#define FCLK_FAST() { SPI10_Initialization(4500000, SPI10_MODE0, false); }	/* Set SCLK = fast, approx 4.5 MBits/s */
+
+#define CS_HIGH()	{SPI10_CS_HIGH;}
+#define CS_LOW()	{SPI10_CS_LOW;}
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+/* MMC/SD command */
+#define CMD0	(0)			/* GO_IDLE_STATE */
+#define CMD1	(1)			/* SEND_OP_COND (MMC) */
+#define	ACMD41	(0x80+41)	/* SEND_OP_COND (SDC) */
+#define CMD8	(8)			/* SEND_IF_COND */
+#define CMD9	(9)			/* SEND_CSD */
+#define CMD10	(10)		/* SEND_CID */
+#define CMD12	(12)		/* STOP_TRANSMISSION */
+#define ACMD13	(0x80+13)	/* SD_STATUS (SDC) */
+#define CMD16	(16)		/* SET_BLOCKLEN */
+#define CMD17	(17)		/* READ_SINGLE_BLOCK */
+#define CMD18	(18)		/* READ_MULTIPLE_BLOCK */
+#define CMD23	(23)		/* SET_BLOCK_COUNT (MMC) */
+#define	ACMD23	(0x80+23)	/* SET_WR_BLK_ERASE_COUNT (SDC) */
+#define CMD24	(24)		/* WRITE_BLOCK */
+#define CMD25	(25)		/* WRITE_MULTIPLE_BLOCK */
+#define CMD32	(32)		/* ERASE_ER_BLK_START */
+#define CMD33	(33)		/* ERASE_ER_BLK_END */
+#define CMD38	(38)		/* ERASE */
+#define CMD55	(55)		/* APP_CMD */
+#define CMD58	(58)		/* READ_OCR */
+
+/* MMC card type flags (MMC_GET_TYPE) */
+#define CT_MMC		0x01		/* MMC ver 3 */
+#define CT_SD1		0x02		/* SD ver 1 */
+#define CT_SD2		0x04		/* SD ver 2 */
+#define CT_SDC		(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK	0x08		/* Block addressing */
+
+static volatile
+DSTATUS Stat = STA_NOINIT;	/* Physical drive status */
+
+
+static
+BYTE CardType;			/* Card type flags */
+
+uint32_t spiTimerTickStart;
+uint32_t spiTimerTickDelay;
+
+void SPI_Timer_On(uint32_t waitTicks) {
+    spiTimerTickStart = millis();
+    spiTimerTickDelay = waitTicks;
+}
+
+uint8_t SPI_Timer_Status() {
+    return ((millis() - spiTimerTickStart) < spiTimerTickDelay);
+}
+
+/*-----------------------------------------------------------------------*/
+/* SPI controls (Platform dependent)                                     */
+/*-----------------------------------------------------------------------*/
+
+/* Exchange a byte */
+static
+BYTE xchg_spi (
+	BYTE dat	/* Data to send */
+)
+{
+	BYTE rxDat;
+    rxDat = SPI10_SendReceiveByte(dat);
+    return rxDat;
+}
+
+
+/* Receive multiple byte */
+static
+void rcvr_spi_multi (
+	BYTE *buff,		/* Pointer to data buffer */
+	UINT btr		/* Number of bytes to receive (even number) */
+)
+{
+	for(UINT i=0; i<btr; i++) {
+		*(buff+i) = xchg_spi(0xFF);
+	}
+}
+
+
+#if _USE_WRITE
+/* Send multiple byte */
+static
+void xmit_spi_multi (
+	const BYTE *buff,	/* Pointer to the data */
+	UINT btx			/* Number of bytes to send (even number) */
+)
+{
+	//HAL_SPI_Transmit(&SD_SPI_HANDLE, buff, btx, HAL_MAX_DELAY);
+	SPI10_Transmit((uint8_t *)buff, btx);
+}
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/* Wait for card ready                                                   */
+/*-----------------------------------------------------------------------*/
+
+static
+int wait_ready (	/* 1:Ready, 0:Timeout */
+	UINT wt			/* Timeout [ms] */
+)
+{
+	BYTE d;
+	//wait_ready needs its own timer, unfortunately, so it can't use the
+	//spi_timer functions
+	uint32_t waitSpiTimerTickStart;
+	uint32_t waitSpiTimerTickDelay;
+
+	waitSpiTimerTickStart = millis();
+	waitSpiTimerTickDelay = (uint32_t)wt;
+	do {
+		d = xchg_spi(0xFF);
+		/* This loop takes a time. Insert rot_rdq() here for multitask envilonment. */
+	} while (d != 0xFF && ((millis() - waitSpiTimerTickStart) < waitSpiTimerTickDelay));	/* Wait for card goes ready or timeout */
+
+	return (d == 0xFF) ? 1 : 0;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Despiselect card and release SPI                                         */
+/*-----------------------------------------------------------------------*/
+
+static
+void despiselect (void)
+{
+	CS_HIGH();		/* Set CS# high */
+	xchg_spi(0xFF);	/* Dummy clock (force DO hi-z for multiple slave SPI) */
+
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Select card and wait for ready                                        */
+/*-----------------------------------------------------------------------*/
+
+static
+int spiselect (void)	/* 1:OK, 0:Timeout */
+{
+	CS_LOW();		/* Set CS# low */
+	xchg_spi(0xFF);	/* Dummy clock (force DO enabled) */
+	if (wait_ready(500)) return 1;	/* Wait for card ready */
+
+	despiselect();
+	return 0;	/* Timeout */
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Receive a data packet from the MMC                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+int rcvr_datablock (	/* 1:OK, 0:Error */
+	BYTE *buff,			/* Data buffer */
+	UINT btr			/* Data block length (byte) */
+)
+{
+	BYTE token;
+
+
+	SPI_Timer_On(200);
+	do {							/* Wait for DataStart token in timeout of 200ms */
+		token = xchg_spi(0xFF);
+		/* This loop will take a time. Insert rot_rdq() here for multitask envilonment. */
+	} while ((token == 0xFF) && SPI_Timer_Status());
+	if(token != 0xFE) return 0;		/* Function fails if invalid DataStart token or timeout */
+
+	rcvr_spi_multi(buff, btr);		/* Store trailing data to the buffer */
+	xchg_spi(0xFF); xchg_spi(0xFF);			/* Discard CRC */
+
+	return 1;						/* Function succeeded */
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Send a data packet to the MMC                                         */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_WRITE
+static
+int xmit_datablock (	/* 1:OK, 0:Failed */
+	const BYTE *buff,	/* Ponter to 512 byte data to be sent */
+	BYTE token			/* Token */
+)
+{
+	BYTE resp;
+
+
+	if (!wait_ready(500)) return 0;		/* Wait for card ready */
+
+	xchg_spi(token);					/* Send token */
+	if (token != 0xFD) {				/* Send data if token is other than StopTran */
+		xmit_spi_multi(buff, 512);		/* Data */
+		xchg_spi(0xFF); xchg_spi(0xFF);	/* Dummy CRC */
+
+		resp = xchg_spi(0xFF);				/* Receive data resp */
+		if ((resp & 0x1F) != 0x05) return 0;	/* Function fails if the data packet was not accepted */
+	}
+	return 1;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/* Send a command packet to the MMC                                      */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE send_cmd (		/* Return value: R1 resp (bit7==1:Failed to send) */
+	BYTE cmd,		/* Command index */
+	DWORD arg		/* Argument */
+)
+{
+	BYTE n, res;
+
+
+	if (cmd & 0x80) {	/* Send a CMD55 prior to ACMD<n> */
+		cmd &= 0x7F;
+		res = send_cmd(CMD55, 0);
+		if (res > 1) return res;
+	}
+
+	/* Select the card and wait for ready except to stop multiple block read */
+	if (cmd != CMD12) {
+		despiselect();
+		if (!spiselect()) return 0xFF;
+	}
+
+	/* Send command packet */
+	xchg_spi(0x40 | cmd);				/* Start + command index */
+	xchg_spi((BYTE)(arg >> 24));		/* Argument[31..24] */
+	xchg_spi((BYTE)(arg >> 16));		/* Argument[23..16] */
+	xchg_spi((BYTE)(arg >> 8));			/* Argument[15..8] */
+	xchg_spi((BYTE)arg);				/* Argument[7..0] */
+	n = 0x01;							/* Dummy CRC + Stop */
+	if (cmd == CMD0) n = 0x95;			/* Valid CRC for CMD0(0) */
+	if (cmd == CMD8) n = 0x87;			/* Valid CRC for CMD8(0x1AA) */
+	xchg_spi(n);
+
+	/* Receive command resp */
+	if (cmd == CMD12) xchg_spi(0xFF);	/* Diacard following one byte when CMD12 */
+	n = 10;								/* Wait for response (10 bytes max) */
+	do {
+		res = xchg_spi(0xFF);
+	} while ((res & 0x80) && --n);
+
+	return res;							/* Return received response */
+}
+
+
+/*--------------------------------------------------------------------------
+
+   Public FatFs Functions (wrapped in user_diskio.c)
+
+---------------------------------------------------------------------------*/
+
+//The following functions are defined as inline because they aren't the functions that
+//are passed to FatFs - they are wrapped by autogenerated (non-inline) cubemx template
+//code.
+//If you do not wish to use cubemx, remove the "inline" from these functions here
+//and in the associated .h
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize disk drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+inline DSTATUS USER_SPI_initialize (
+	BYTE drv		/* Physical drive number (0) */
+)
+{
+	BYTE n, cmd, ty, ocr[4];
+
+	if (drv != 0) return STA_NOINIT;		/* Supports only drive 0 */
+	//assume SPI already init init_spi();	/* Initialize SPI */
+
+	if (Stat & STA_NODISK) return Stat;	/* Is card existing in the soket? */
+
+	FCLK_SLOW();
+	for (n = 10; n; n--) xchg_spi(0xFF);	/* Send 80 dummy clocks */
+
+	ty = 0;
+	if (send_cmd(CMD0, 0) == 1) {			/* Put the card SPI/Idle state */
+		SPI_Timer_On(1000);					/* Initialization timeout = 1 sec */
+		if (send_cmd(CMD8, 0x1AA) == 1) {	/* SDv2? */
+			for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF);	/* Get 32 bit return value of R7 resp */
+			if (ocr[2] == 0x01 && ocr[3] == 0xAA) {				/* Is the card supports vcc of 2.7-3.6V? */
+				while (SPI_Timer_Status() && send_cmd(ACMD41, 1UL << 30)) ;	/* Wait for end of initialization with ACMD41(HCS) */
+				if (SPI_Timer_Status() && send_cmd(CMD58, 0) == 0) {		/* Check CCS bit in the OCR */
+					for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF);
+					ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2;	/* Card id SDv2 */
+				}
+			}
+		} else {	/* Not SDv2 card */
+			if (send_cmd(ACMD41, 0) <= 1) 	{	/* SDv1 or MMC? */
+				ty = CT_SD1; cmd = ACMD41;	/* SDv1 (ACMD41(0)) */
+			} else {
+				ty = CT_MMC; cmd = CMD1;	/* MMCv3 (CMD1(0)) */
+			}
+			while (SPI_Timer_Status() && send_cmd(cmd, 0)) ;		/* Wait for end of initialization */
+			if (!SPI_Timer_Status() || send_cmd(CMD16, 512) != 0)	/* Set block length: 512 */
+				ty = 0;
+		}
+	}
+	CardType = ty;	/* Card type */
+	despiselect();
+
+	if (ty) {			/* OK */
+		FCLK_FAST();			/* Set fast clock */
+		Stat &= ~STA_NOINIT;	/* Clear STA_NOINIT flag */
+	} else {			/* Failed */
+		Stat = STA_NOINIT;
+	}
+
+	return Stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get disk status                                                       */
+/*-----------------------------------------------------------------------*/
+
+inline DSTATUS USER_SPI_status (
+	BYTE drv		/* Physical drive number (0) */
+)
+{
+	if (drv) return STA_NOINIT;		/* Supports only drive 0 */
+
+	return Stat;	/* Return disk status */
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read sector(s)                                                        */
+/*-----------------------------------------------------------------------*/
+
+inline DRESULT USER_SPI_read (
+	BYTE drv,		/* Physical drive number (0) */
+	BYTE *buff,		/* Pointer to the data buffer to store read data */
+	DWORD sector,	/* Start sector number (LBA) */
+	UINT count		/* Number of sectors to read (1..128) */
+)
+{
+	if (drv || !count) return RES_PARERR;		/* Check parameter */
+	if (Stat & STA_NOINIT) return RES_NOTRDY;	/* Check if drive is ready */
+
+	if (!(CardType & CT_BLOCK)) sector *= 512;	/* LBA ot BA conversion (byte addressing cards) */
+
+	if (count == 1) {	/* Single sector read */
+		if ((send_cmd(CMD17, sector) == 0)	/* READ_SINGLE_BLOCK */
+			&& rcvr_datablock(buff, 512)) {
+			count = 0;
+		}
+	}
+	else {				/* Multiple sector read */
+		if (send_cmd(CMD18, sector) == 0) {	/* READ_MULTIPLE_BLOCK */
+			do {
+				if (!rcvr_datablock(buff, 512)) break;
+				buff += 512;
+			} while (--count);
+			send_cmd(CMD12, 0);				/* STOP_TRANSMISSION */
+		}
+	}
+	despiselect();
+
+	return count ? RES_ERROR : RES_OK;	/* Return result */
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write sector(s)                                                       */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_WRITE
+inline DRESULT USER_SPI_write (
+	BYTE drv,			/* Physical drive number (0) */
+	const BYTE *buff,	/* Ponter to the data to write */
+	DWORD sector,		/* Start sector number (LBA) */
+	UINT count			/* Number of sectors to write (1..128) */
+)
+{
+	if (drv || !count) return RES_PARERR;		/* Check parameter */
+	if (Stat & STA_NOINIT) return RES_NOTRDY;	/* Check drive status */
+	if (Stat & STA_PROTECT) return RES_WRPRT;	/* Check write protect */
+
+	if (!(CardType & CT_BLOCK)) sector *= 512;	/* LBA ==> BA conversion (byte addressing cards) */
+
+	if (count == 1) {	/* Single sector write */
+		if ((send_cmd(CMD24, sector) == 0)	/* WRITE_BLOCK */
+			&& xmit_datablock(buff, 0xFE)) {
+			count = 0;
+		}
+	}
+	else {				/* Multiple sector write */
+		if (CardType & CT_SDC) send_cmd(ACMD23, count);	/* Predefine number of sectors */
+		if (send_cmd(CMD25, sector) == 0) {	/* WRITE_MULTIPLE_BLOCK */
+			do {
+				if (!xmit_datablock(buff, 0xFC)) break;
+				buff += 512;
+			} while (--count);
+			if (!xmit_datablock(0, 0xFD)) count = 1;	/* STOP_TRAN token */
+		}
+	}
+	despiselect();
+
+	return count ? RES_ERROR : RES_OK;	/* Return result */
+}
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous drive controls other than data read/write               */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_IOCTL
+inline DRESULT USER_SPI_ioctl (
+	BYTE drv,		/* Physical drive number (0) */
+	BYTE cmd,		/* Control command code */
+	void *buff		/* Pointer to the conrtol data */
+)
+{
+	DRESULT res;
+	BYTE n, csd[16];
+	DWORD *dp, st, ed, csize;
+
+
+	if (drv) return RES_PARERR;					/* Check parameter */
+	if (Stat & STA_NOINIT) return RES_NOTRDY;	/* Check if drive is ready */
+
+	res = RES_ERROR;
+
+	switch (cmd) {
+	case CTRL_SYNC :		/* Wait for end of internal write process of the drive */
+		if (spiselect()) res = RES_OK;
+		break;
+
+	case GET_SECTOR_COUNT :	/* Get drive capacity in unit of sector (DWORD) */
+		if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) {
+			if ((csd[0] >> 6) == 1) {	/* SDC ver 2.00 */
+				csize = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1;
+				*(DWORD*)buff = csize << 10;
+			} else {					/* SDC ver 1.XX or MMC ver 3 */
+				n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
+				csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1;
+				*(DWORD*)buff = csize << (n - 9);
+			}
+			res = RES_OK;
+		}
+		break;
+
+	case GET_BLOCK_SIZE :	/* Get erase block size in unit of sector (DWORD) */
+		if (CardType & CT_SD2) {	/* SDC ver 2.00 */
+			if (send_cmd(ACMD13, 0) == 0) {	/* Read SD status */
+				xchg_spi(0xFF);
+				if (rcvr_datablock(csd, 16)) {				/* Read partial block */
+					for (n = 64 - 16; n; n--) xchg_spi(0xFF);	/* Purge trailing data */
+					*(DWORD*)buff = 16UL << (csd[10] >> 4);
+					res = RES_OK;
+				}
+			}
+		} else {					/* SDC ver 1.XX or MMC */
+			if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) {	/* Read CSD */
+				if (CardType & CT_SD1) {	/* SDC ver 1.XX */
+					*(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1);
+				} else {					/* MMC */
+					*(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1);
+				}
+				res = RES_OK;
+			}
+		}
+		break;
+
+	case CTRL_TRIM :	/* Erase a block of sectors (used when _USE_ERASE == 1) */
+		if (!(CardType & CT_SDC)) break;				/* Check if the card is SDC */
+		if (USER_SPI_ioctl(drv, MMC_GET_CSD, csd)) break;	/* Get CSD */
+		if (!(csd[0] >> 6) && !(csd[10] & 0x40)) break;	/* Check if sector erase can be applied to the card */
+		dp = buff; st = dp[0]; ed = dp[1];				/* Load sector block */
+		if (!(CardType & CT_BLOCK)) {
+			st *= 512; ed *= 512;
+		}
+		if (send_cmd(CMD32, st) == 0 && send_cmd(CMD33, ed) == 0 && send_cmd(CMD38, 0) == 0 && wait_ready(30000)) {	/* Erase sector block */
+			res = RES_OK;	/* FatFs does not check result of this command */
+		}
+		break;
+
+	default:
+		res = RES_PARERR;
+	}
+
+	despiselect();
+
+	return res;
+}
+#endif
diff --git a/Project/Application/FATFS/Target/user_diskio_spi.h b/Project/Application/FATFS/Target/user_diskio_spi.h
new file mode 100644
index 0000000..0a95e56
--- /dev/null
+++ b/Project/Application/FATFS/Target/user_diskio_spi.h
@@ -0,0 +1,38 @@
+/**
+ ******************************************************************************
+  * @file    user_diskio_spi.h
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the user_diskio_spi driver implementation
+  ******************************************************************************
+  * Portions copyright (C) 2014, ChaN, all rights reserved.
+  * Portions copyright (C) 2017, kiwih, all rights reserved.
+  *
+  * This software is a free software and there is NO WARRANTY.
+  * No restriction on use. You can use, modify and redistribute it for
+  * personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+  * Redistributions of source code must retain the above copyright notice.
+  *
+  ******************************************************************************
+  */
+
+#ifndef _USER_DISKIO_SPI_H
+#define _USER_DISKIO_SPI_H
+
+#include "integer.h" //from FatFs middleware library
+#include "diskio.h" //from FatFs middleware library
+#include "ff_gen_drv.h" //from FatFs middleware library
+
+//we define these as inline because we don't want them to be actual function calls (they get "called" from the cubemx autogenerated user_diskio file)
+//we define them as extern because they are defined in a separate .c file to user_diskio.c (which #includes this .h file)
+
+extern DSTATUS USER_SPI_initialize (BYTE pdrv);
+extern DSTATUS USER_SPI_status (BYTE pdrv);
+extern DRESULT USER_SPI_read (BYTE pdrv, BYTE *buff, DWORD sector, UINT count);
+#if _USE_WRITE == 1
+  extern DRESULT USER_SPI_write (BYTE pdrv, const BYTE *buff, DWORD sector, UINT count);
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+  extern DRESULT USER_SPI_ioctl (BYTE pdrv, BYTE cmd, void *buff);
+#endif /* _USE_IOCTL == 1 */
+
+#endif
diff --git a/Project/Application/Middlewares/Third_Party/FatFs/src/diskio.c b/Project/Application/Middlewares/Third_Party/FatFs/src/diskio.c
new file mode 100644
index 0000000..2a4a02c
--- /dev/null
+++ b/Project/Application/Middlewares/Third_Party/FatFs/src/diskio.c
@@ -0,0 +1,160 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2014        */
+/*                                                                       */
+/*   Portions COPYRIGHT 2015 STMicroelectronics                          */
+/*   Portions Copyright (C) 2014, ChaN, all right reserved               */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be        */
+/* attached to the FatFs via a glue function rather than modifying it.   */
+/* This is an example of glue functions to attach various exsisting      */
+/* storage control modules to the FatFs module with a defined API.       */
+/*-----------------------------------------------------------------------*/
+
+/**
+  ******************************************************************************
+  * @file    diskio.c 
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    08-May-2015
+  * @brief   FatFs low level disk I/O module.
+  ******************************************************************************
+  * @attention
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "diskio.h"
+#include "ff_gen_drv.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern Disk_drvTypeDef  disk;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Gets Disk Status 
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS disk_status (
+	BYTE pdrv		/* Physical drive nmuber to identify the drive */
+)
+{
+  DSTATUS stat;
+  
+  stat = disk.drv[pdrv]->disk_status(disk.lun[pdrv]);
+  return stat;
+}
+
+/**
+  * @brief  Initializes a Drive
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS disk_initialize (
+	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+)
+{
+  DSTATUS stat = RES_OK;
+  
+  if(disk.is_initialized[pdrv] == 0)
+  { 
+    disk.is_initialized[pdrv] = 1;
+    stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]);
+  }
+  return stat;
+}
+
+/**
+  * @brief  Reads Sector(s) 
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+DRESULT disk_read (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	BYTE *buff,		/* Data buffer to store read data */
+	DWORD sector,	        /* Sector address in LBA */
+	UINT count		/* Number of sectors to read */
+)
+{
+  DRESULT res;
+ 
+  res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count);
+  return res;
+}
+
+/**
+  * @brief  Writes Sector(s)  
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+DRESULT disk_write (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	const BYTE *buff,	/* Data to be written */
+	DWORD sector,		/* Sector address in LBA */
+	UINT count        	/* Number of sectors to write */
+)
+{
+  DRESULT res;
+  
+  res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count);
+  return res;
+}
+#endif /* _USE_WRITE == 1 */
+
+/**
+  * @brief  I/O control operation  
+  * @param  pdrv: Physical drive number (0..)
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT disk_ioctl (
+	BYTE pdrv,		/* Physical drive nmuber (0..) */
+	BYTE cmd,		/* Control code */
+	void *buff		/* Buffer to send/receive control data */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff);
+  return res;
+}
+#endif /* _USE_IOCTL == 1 */
+
+/**
+  * @brief  Gets Time from RTC 
+  * @param  None
+  * @retval Time in DWORD
+  */
+__weak DWORD get_fattime (void)
+{
+  return 0;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Project/Application/Middlewares/Third_Party/FatFs/src/diskio.h b/Project/Application/Middlewares/Third_Party/FatFs/src/diskio.h
new file mode 100644
index 0000000..6af958a
--- /dev/null
+++ b/Project/Application/Middlewares/Third_Party/FatFs/src/diskio.h
@@ -0,0 +1,80 @@
+/*-----------------------------------------------------------------------/
+/  Low level disk interface modlue include file   (C)ChaN, 2014          /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _USE_WRITE	1	/* 1: Enable disk_write function */
+#define _USE_IOCTL	1	/* 1: Enable disk_ioctl fucntion */
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Successful */
+	RES_ERROR,		/* 1: R/W Error */
+	RES_WRPRT,		/* 2: Write Protected */
+	RES_NOTRDY,		/* 3: Not Ready */
+	RES_PARERR		/* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+DWORD get_fattime (void);
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+#define STA_PROTECT		0x04	/* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC		0	/* Complete pending write process (needed at _FS_READONLY == 0) */
+#define GET_SECTOR_COUNT	1	/* Get media size (needed at _USE_MKFS == 1) */
+#define GET_SECTOR_SIZE		2	/* Get sector size (needed at _MAX_SS != _MIN_SS) */
+#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at _USE_MKFS == 1) */
+#define CTRL_TRIM		4	/* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
+
+/* Generic command (Not used by FatFs) */
+#define CTRL_POWER			5	/* Get/Set power status */
+#define CTRL_LOCK			6	/* Lock/Unlock media removal */
+#define CTRL_EJECT			7	/* Eject media */
+#define CTRL_FORMAT			8	/* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE		10	/* Get card type */
+#define MMC_GET_CSD			11	/* Get CSD */
+#define MMC_GET_CID			12	/* Get CID */
+#define MMC_GET_OCR			13	/* Get OCR */
+#define MMC_GET_SDSTAT		14	/* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV			20	/* Get F/W revision */
+#define ATA_GET_MODEL		21	/* Get model name */
+#define ATA_GET_SN			22	/* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Project/Application/Middlewares/Third_Party/FatFs/src/ff.c b/Project/Application/Middlewares/Third_Party/FatFs/src/ff.c
new file mode 100644
index 0000000..5766d55
--- /dev/null
+++ b/Project/Application/Middlewares/Third_Party/FatFs/src/ff.c
@@ -0,0 +1,4752 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - FAT file system module  R0.11                 (C)ChaN, 2015
+/-----------------------------------------------------------------------------/
+/ FatFs module is a free software that opened under license policy of
+/ following conditions.
+/
+/ Copyright (C) 2015, ChaN, all right reserved.
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/-----------------------------------------------------------------------------/
+/ Feb 26,'06 R0.00  Prototype.
+/
+/ Apr 29,'06 R0.01  First stable version.
+/
+/ Jun 01,'06 R0.02  Added FAT12 support.
+/                   Removed unbuffered mode.
+/                   Fixed a problem on small (<32M) partition.
+/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM).
+/
+/ Sep 22,'06 R0.03  Added f_rename().
+/                   Changed option _FS_MINIMUM to _FS_MINIMIZE.
+/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast.
+/                   Fixed f_mkdir() creates incorrect directory on FAT32.
+/
+/ Feb 04,'07 R0.04  Supported multiple drive system.
+/                   Changed some interfaces for multiple drive system.
+/                   Changed f_mountdrv() to f_mount().
+/                   Added f_mkfs().
+/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive.
+/                   Added a capability of extending file size to f_lseek().
+/                   Added minimization level 3.
+/                   Fixed an endian sensitive code in f_mkfs().
+/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG.
+/                   Added FSINFO support.
+/                   Fixed DBCS name can result FR_INVALID_NAME.
+/                   Fixed short seek (<= csize) collapses the file object.
+/
+/ Aug 25,'07 R0.05  Changed arguments of f_read(), f_write() and f_mkfs().
+/                   Fixed f_mkfs() on FAT32 creates incorrect FSINFO.
+/                   Fixed f_mkdir() on FAT32 creates incorrect directory.
+/ Feb 03,'08 R0.05a Added f_truncate() and f_utime().
+/                   Fixed off by one error at FAT sub-type determination.
+/                   Fixed btr in f_read() can be mistruncated.
+/                   Fixed cached sector is not flushed when create and close without write.
+/
+/ Apr 01,'08 R0.06  Added fputc(), fputs(), fprintf() and fgets().
+/                   Improved performance of f_lseek() on moving to the same or following cluster.
+/
+/ Apr 01,'09 R0.07  Merged Tiny-FatFs as a configuration option. (_FS_TINY)
+/                   Added long file name feature.
+/                   Added multiple code page feature.
+/                   Added re-entrancy for multitask operation.
+/                   Added auto cluster size selection to f_mkfs().
+/                   Added rewind option to f_readdir().
+/                   Changed result code of critical errors.
+/                   Renamed string functions to avoid name collision.
+/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg.
+/                   Added multiple sector size feature.
+/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error.
+/                   Fixed wrong cache control in f_lseek().
+/                   Added relative path feature.
+/                   Added f_chdir() and f_chdrive().
+/                   Added proper case conversion to extended character.
+/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h.
+/                   Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH.
+/                   Fixed name matching error on the 13 character boundary.
+/                   Added a configuration option, _LFN_UNICODE.
+/                   Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
+/
+/ May 15,'10 R0.08  Added a memory configuration option. (_USE_LFN = 3)
+/                   Added file lock feature. (_FS_SHARE)
+/                   Added fast seek feature. (_USE_FASTSEEK)
+/                   Changed some types on the API, XCHAR->TCHAR.
+/                   Changed .fname in the FILINFO structure on Unicode cfg.
+/                   String functions support UTF-8 encoding files on Unicode cfg.
+/ Aug 16,'10 R0.08a Added f_getcwd().
+/                   Added sector erase feature. (_USE_ERASE)
+/                   Moved file lock semaphore table from fs object to the bss.
+/                   Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
+/                   Fixed f_mkfs() creates wrong FAT32 volume.
+/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write().
+/                   f_lseek() reports required table size on creating CLMP.
+/                   Extended format syntax of f_printf().
+/                   Ignores duplicated directory separators in given path name.
+/
+/ Sep 06,'11 R0.09  f_mkfs() supports multiple partition to complete the multiple partition feature.
+/                   Added f_fdisk().
+/ Aug 27,'12 R0.09a Changed f_open() and f_opendir() reject null object pointer to avoid crash.
+/                   Changed option name _FS_SHARE to _FS_LOCK.
+/                   Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
+/ Jan 24,'13 R0.09b Added f_setlabel() and f_getlabel().
+/
+/ Oct 02,'13 R0.10  Added selection of character encoding on the file. (_STRF_ENCODE)
+/                   Added f_closedir().
+/                   Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO)
+/                   Added forced mount feature with changes of f_mount().
+/                   Improved behavior of volume auto detection.
+/                   Improved write throughput of f_puts() and f_printf().
+/                   Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write().
+/                   Fixed f_write() can be truncated when the file size is close to 4GB.
+/                   Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect error code.
+/ Jan 15,'14 R0.10a Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID)
+/                   Added a configuration option of minimum sector size. (_MIN_SS)
+/                   2nd argument of f_rename() can have a drive number and it will be ignored.
+/                   Fixed f_mount() with forced mount fails when drive number is >= 1.
+/                   Fixed f_close() invalidates the file object without volume lock.
+/                   Fixed f_closedir() returns but the volume lock is left acquired.
+/                   Fixed creation of an entry with LFN fails on too many SFN collisions.
+/ May 19,'14 R0.10b Fixed a hard error in the disk I/O layer can collapse the directory entry.
+/                   Fixed LFN entry is not deleted on delete/rename an object with lossy converted SFN.
+/ Nov  9,'14 R0.10c Added a configuration option for the platforms without RTC. (_FS_NORTC)
+/                   Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b)
+/                   Fixed a potential problem of FAT access that can appear on disk error.
+/                   Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)
+/ Feb 02,'15 R0.11  Added f_findfirst() and f_findnext(). (_USE_FIND)
+/                   Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c)
+/                   Fixed _FS_NORTC option does not work properly. (appeared at R0.10c)
+/---------------------------------------------------------------------------*/
+
+#include "ff.h"			/* Declarations of FatFs API */
+#include "diskio.h"		/* Declarations of disk I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 32020	/* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area cannot be used at thread-safe configuration
+#endif
+#define	ENTER_FF(fs)		{ if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define	LEAVE_FF(fs, res)	{ unlock_fs(fs, res); return res; }
+#else
+#define	ENTER_FF(fs)
+#define LEAVE_FF(fs, res)	return res
+#endif
+
+#define	ABORT(fs, res)		{ fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+
+
+/* Definitions of sector size */
+#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096)
+#error Wrong sector size configuration
+#endif
+#if _MAX_SS == _MIN_SS
+#define	SS(fs)	((UINT)_MAX_SS)	/* Fixed sector size */
+#else
+#define	SS(fs)	((fs)->ssize)	/* Variable sector size */
+#endif
+
+
+/* Timestamp feature */
+#if _FS_NORTC == 1
+#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31
+#error Invalid _FS_NORTC settings
+#endif
+#define GET_FATTIME()	((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16)
+#else
+#define GET_FATTIME()	get_fattime()
+#endif
+
+
+/* File access control feature */
+#if _FS_LOCK
+#if _FS_READONLY
+#error _FS_LOCK must be 0 at read-only configuration
+#endif
+typedef struct {
+	FATFS *fs;		/* Object ID 1, volume (NULL:blank entry) */
+	DWORD clu;		/* Object ID 2, directory (0:root) */
+	WORD idx;		/* Object ID 3, directory index */
+	WORD ctr;		/* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+
+/* DBCS code ranges and SBCS extend character conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#if _USE_LFN
+#error Cannot use LFN feature without valid code page.
+#endif
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+/* Character code support macros */
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+#define IsDigit(c)	(((c)>='0')&&((c)<='9'))
+
+#if _DF1S		/* Code page is DBCS */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* Code page is SBCS */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* Name status flags */
+#define NSFLAG		11		/* Index of name status byte in fn[] */
+#define NS_LOSS		0x01	/* Out of 8.3 format */
+#define NS_LFN		0x02	/* Force to create LFN entry */
+#define NS_LAST		0x04	/* Last segment */
+#define NS_BODY		0x08	/* Lower case flag (body) */
+#define NS_EXT		0x10	/* Lower case flag (ext) */
+#define NS_DOT		0x20	/* Dot entry */
+
+
+/* FAT sub-type boundaries (Differ from specs but correct for real DOS/Windows) */
+#define MIN_FAT16	4086U	/* Minimum number of clusters as FAT16 */
+#define	MIN_FAT32	65526U	/* Minimum number of clusters as FAT32 */
+
+
+/* FatFs refers the members in the FAT structures as byte array instead of
+/ structure member because the structure is not binary compatible between
+/ different platforms */
+
+#define BS_jmpBoot			0		/* x86 jump instruction (3) */
+#define BS_OEMName			3		/* OEM name (8) */
+#define BPB_BytsPerSec		11		/* Sector size [byte] (2) */
+#define BPB_SecPerClus		13		/* Cluster size [sector] (1) */
+#define BPB_RsvdSecCnt		14		/* Size of reserved area [sector] (2) */
+#define BPB_NumFATs			16		/* Number of FAT copies (1) */
+#define BPB_RootEntCnt		17		/* Number of root directory entries for FAT12/16 (2) */
+#define BPB_TotSec16		19		/* Volume size [sector] (2) */
+#define BPB_Media			21		/* Media descriptor (1) */
+#define BPB_FATSz16			22		/* FAT size [sector] (2) */
+#define BPB_SecPerTrk		24		/* Track size [sector] (2) */
+#define BPB_NumHeads		26		/* Number of heads (2) */
+#define BPB_HiddSec			28		/* Number of special hidden sectors (4) */
+#define BPB_TotSec32		32		/* Volume size [sector] (4) */
+#define BS_DrvNum			36		/* Physical drive number (2) */
+#define BS_BootSig			38		/* Extended boot signature (1) */
+#define BS_VolID			39		/* Volume serial number (4) */
+#define BS_VolLab			43		/* Volume label (8) */
+#define BS_FilSysType		54		/* File system type (1) */
+#define BPB_FATSz32			36		/* FAT size [sector] (4) */
+#define BPB_ExtFlags		40		/* Extended flags (2) */
+#define BPB_FSVer			42		/* File system version (2) */
+#define BPB_RootClus		44		/* Root directory first cluster (4) */
+#define BPB_FSInfo			48		/* Offset of FSINFO sector (2) */
+#define BPB_BkBootSec		50		/* Offset of backup boot sector (2) */
+#define BS_DrvNum32			64		/* Physical drive number (2) */
+#define BS_BootSig32		66		/* Extended boot signature (1) */
+#define BS_VolID32			67		/* Volume serial number (4) */
+#define BS_VolLab32			71		/* Volume label (8) */
+#define BS_FilSysType32		82		/* File system type (1) */
+#define	FSI_LeadSig			0		/* FSI: Leading signature (4) */
+#define	FSI_StrucSig		484		/* FSI: Structure signature (4) */
+#define	FSI_Free_Count		488		/* FSI: Number of free clusters (4) */
+#define	FSI_Nxt_Free		492		/* FSI: Last allocated cluster (4) */
+#define MBR_Table			446		/* MBR: Partition table offset (2) */
+#define	SZ_PTE				16		/* MBR: Size of a partition table entry */
+#define BS_55AA				510		/* Signature word (2) */
+
+#define	DIR_Name			0		/* Short file name (11) */
+#define	DIR_Attr			11		/* Attribute (1) */
+#define	DIR_NTres			12		/* Lower case flag (1) */
+#define DIR_CrtTimeTenth	13		/* Created time sub-second (1) */
+#define	DIR_CrtTime			14		/* Created time (2) */
+#define	DIR_CrtDate			16		/* Created date (2) */
+#define DIR_LstAccDate		18		/* Last accessed date (2) */
+#define	DIR_FstClusHI		20		/* Higher 16-bit of first cluster (2) */
+#define	DIR_WrtTime			22		/* Modified time (2) */
+#define	DIR_WrtDate			24		/* Modified date (2) */
+#define	DIR_FstClusLO		26		/* Lower 16-bit of first cluster (2) */
+#define	DIR_FileSize		28		/* File size (4) */
+#define	LDIR_Ord			0		/* LFN entry order and LLE flag (1) */
+#define	LDIR_Attr			11		/* LFN attribute (1) */
+#define	LDIR_Type			12		/* LFN type (1) */
+#define	LDIR_Chksum			13		/* Sum of corresponding SFN entry */
+#define	LDIR_FstClusLO		26		/* Must be zero (0) */
+#define	SZ_DIRE				32		/* Size of a directory entry */
+#define	LLEF				0x40	/* Last long entry flag in LDIR_Ord */
+#define	DDEM				0xE5	/* Deleted directory entry mark at DIR_Name[0] */
+#define	RDDEM				0x05	/* Replacement of the character collides with DDEM */
+
+
+
+
+/*------------------------------------------------------------*/
+/* Module private work area                                   */
+/*------------------------------------------------------------*/
+/* Remark: Uninitialized variables with static duration are
+/  guaranteed zero/null at start-up. If not, either the linker
+/  or start-up routine being used is out of ANSI-C standard.
+*/
+
+#if _VOLUMES < 1 || _VOLUMES > 9
+#error Wrong _VOLUMES setting
+#endif
+static FATFS *FatFs[_VOLUMES];	/* Pointer to the file system objects (logical drives) */
+static WORD Fsid;				/* File system mount ID */
+
+#if _FS_RPATH && _VOLUMES >= 2
+static BYTE CurrVol;			/* Current drive */
+#endif
+
+#if _FS_LOCK
+static FILESEM Files[_FS_LOCK];	/* Open object lock semaphores */
+#endif
+
+#if _USE_LFN == 0			/* Non LFN feature */
+#define	DEFINE_NAMEBUF		BYTE sfn[12]
+#define INIT_BUF(dobj)		(dobj).fn = sfn
+#define	FREE_BUF()
+#else
+#if _MAX_LFN < 12 || _MAX_LFN > 255
+#error Wrong _MAX_LFN setting
+#endif
+#if _USE_LFN == 1			/* LFN feature with static working buffer */
+static WCHAR LfnBuf[_MAX_LFN + 1];
+#define	DEFINE_NAMEBUF		BYTE sfn[12]
+#define INIT_BUF(dobj)		{ (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
+#define	FREE_BUF()
+#elif _USE_LFN == 2 		/* LFN feature with dynamic working buffer on the stack */
+#define	DEFINE_NAMEBUF		BYTE sfn[12]; WCHAR lbuf[_MAX_LFN + 1]
+#define INIT_BUF(dobj)		{ (dobj).fn = sfn; (dobj).lfn = lbuf; }
+#define	FREE_BUF()
+#elif _USE_LFN == 3 		/* LFN feature with dynamic working buffer on the heap */
+#define	DEFINE_NAMEBUF		BYTE sfn[12]; WCHAR *lfn
+#define INIT_BUF(dobj)		{ lfn = ff_memalloc((_MAX_LFN + 1) * 2); if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); (dobj).lfn = lfn; (dobj).fn = sfn; }
+#define	FREE_BUF()			ff_memfree(lfn)
+#else
+#error Wrong _USE_LFN setting
+#endif
+#endif
+
+#ifdef _EXCVT
+static const BYTE ExCvt[] = _EXCVT;	/* Upper conversion table for extended characters */
+#endif
+
+
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+DWORD clust2sect (FATFS* fs, DWORD clst);
+DWORD get_fat (FATFS* fs,	DWORD clst);
+
+#if !_FS_READONLY
+FRESULT put_fat (FATFS* fs,	DWORD clst,	DWORD val);
+#endif /* !_FS_READONLY */
+
+#if _USE_LFN
+static void gen_numname (BYTE* dst, const BYTE* src, const WCHAR* lfn, UINT seq);
+#endif /* !_USE_LFN */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions                                                      */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+	const BYTE *s = (const BYTE*)src;
+
+#if _WORD_ACCESS == 1
+	while (cnt >= sizeof (int)) {
+		*(int*)d = *(int*)s;
+		d += sizeof (int); s += sizeof (int);
+		cnt -= sizeof (int);
+	}
+#endif
+	while (cnt--)
+		*d++ = *s++;
+}
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+
+	while (cnt--)
+		*d++ = (BYTE)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt) {
+	const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+	int r = 0;
+
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr) {
+	while (*str && *str != chr) str++;
+	return *str;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume                            */
+/*-----------------------------------------------------------------------*/
+#if _FS_REENTRANT
+static
+int lock_fs (
+	FATFS* fs		/* File system object */
+)
+{
+	return ff_req_grant(fs->sobj);
+}
+
+
+static
+void unlock_fs (
+	FATFS* fs,		/* File system object */
+	FRESULT res		/* Result code to be returned */
+)
+{
+	if (fs &&
+		res != FR_NOT_ENABLED &&
+		res != FR_INVALID_DRIVE &&
+		res != FR_INVALID_OBJECT &&
+		res != FR_TIMEOUT) {
+		ff_rel_grant(fs->sobj);
+	}
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* File lock control functions                                           */
+/*-----------------------------------------------------------------------*/
+#if _FS_LOCK
+
+static
+FRESULT chk_lock (	/* Check if the file can be accessed */
+	DIR* dp,		/* Directory object pointing the file to be checked */
+	int acc			/* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i, be;
+
+	/* Search file semaphore table */
+	for (i = be = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs) {	/* Existing entry */
+			if (Files[i].fs == dp->fs &&	 	/* Check if the object matched with an open object */
+				Files[i].clu == dp->sclust &&
+				Files[i].idx == dp->index) break;
+		} else {			/* Blank entry */
+			be = 1;
+		}
+	}
+	if (i == _FS_LOCK)	/* The object is not opened */
+		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new object? */
+
+	/* The object has been opened. Reject any open against writing file and all write mode open */
+	return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static
+int enq_lock (void)	/* Check if an entry is available for a new object */
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+	return (i == _FS_LOCK) ? 0 : 1;
+}
+
+
+static
+UINT inc_lock (	/* Increment object open counter and returns its index (0:Internal error) */
+	DIR* dp,	/* Directory object pointing the file to register or increment */
+	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i;
+
+
+	for (i = 0; i < _FS_LOCK; i++) {	/* Find the object */
+		if (Files[i].fs == dp->fs &&
+			Files[i].clu == dp->sclust &&
+			Files[i].idx == dp->index) break;
+	}
+
+	if (i == _FS_LOCK) {				/* Not opened. Register it as new. */
+		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+		if (i == _FS_LOCK) return 0;	/* No free entry to register (int err) */
+		Files[i].fs = dp->fs;
+		Files[i].clu = dp->sclust;
+		Files[i].idx = dp->index;
+		Files[i].ctr = 0;
+	}
+
+	if (acc && Files[i].ctr) return 0;	/* Access violation (int err) */
+
+	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
+
+	return i + 1;
+}
+
+
+static
+FRESULT dec_lock (	/* Decrement object open counter */
+	UINT i			/* Semaphore index (1..) */
+)
+{
+	WORD n;
+	FRESULT res;
+
+
+	if (--i < _FS_LOCK) {	/* Shift index number origin from 0 */
+		n = Files[i].ctr;
+		if (n == 0x100) n = 0;		/* If write mode open, delete the entry */
+		if (n) n--;					/* Decrement read mode open count */
+		Files[i].ctr = n;
+		if (!n) Files[i].fs = 0;	/* Delete the entry if open count gets zero */
+		res = FR_OK;
+	} else {
+		res = FR_INT_ERR;			/* Invalid index nunber */
+	}
+	return res;
+}
+
+
+static
+void clear_lock (	/* Clear lock entries of the volume */
+	FATFS *fs
+)
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs == fs) Files[i].fs = 0;
+	}
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Move/Flush disk access window in the file system object               */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync_window (
+	FATFS* fs		/* File system object */
+)
+{
+	DWORD wsect;
+	UINT nf;
+	FRESULT res = FR_OK;
+
+
+	if (fs->wflag) {	/* Write back the sector if it is dirty */
+		wsect = fs->winsect;	/* Current sector number */
+		if (disk_write(fs->drv, fs->win.d8, wsect, 1) != RES_OK) {
+			res = FR_DISK_ERR;
+		} else {
+			fs->wflag = 0;
+			if (wsect - fs->fatbase < fs->fsize) {		/* Is it in the FAT area? */
+				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+					wsect += fs->fsize;
+					disk_write(fs->drv, fs->win.d8, wsect, 1);
+				}
+			}
+		}
+	}
+	return res;
+}
+#endif
+
+
+static
+FRESULT move_window (
+	FATFS* fs,		/* File system object */
+	DWORD sector	/* Sector number to make appearance in the fs->win[].d8 */
+)
+{
+	FRESULT res = FR_OK;
+
+
+	if (sector != fs->winsect) {	/* Window offset changed? */
+#if !_FS_READONLY
+		res = sync_window(fs);		/* Write-back changes */
+#endif
+		if (res == FR_OK) {			/* Fill sector window with new data */
+			if (disk_read(fs->drv, fs->win.d8, sector, 1) != RES_OK) {
+				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+				res = FR_DISK_ERR;
+			}
+			fs->winsect = sector;
+		}
+	}
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize file system and strage device                             */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync_fs (	/* FR_OK: successful, FR_DISK_ERR: failed */
+	FATFS* fs		/* File system object */
+)
+{
+	FRESULT res;
+
+
+	res = sync_window(fs);
+	if (res == FR_OK) {
+		/* Update FSINFO sector if needed */
+		if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {
+			/* Create FSINFO structure */
+			mem_set(fs->win.d8, 0, SS(fs));
+			ST_WORD(fs->win.d8 + BS_55AA, 0xAA55);
+			ST_DWORD(fs->win.d8 + FSI_LeadSig, 0x41615252);
+			ST_DWORD(fs->win.d8 + FSI_StrucSig, 0x61417272);
+			ST_DWORD(fs->win.d8 + FSI_Free_Count, fs->free_clust);
+			ST_DWORD(fs->win.d8 + FSI_Nxt_Free, fs->last_clust);
+			/* Write it into the FSINFO sector */
+			fs->winsect = fs->volbase + 1;
+			disk_write(fs->drv, fs->win.d8, fs->winsect, 1);
+			fs->fsi_flag = 0;
+		}
+		/* Make sure that no pending write process in the physical drive */
+		if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK)
+			res = FR_DISK_ERR;
+	}
+
+	return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+/* Hidden API for hacks and disk tools */
+
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	FATFS* fs,		/* File system object */
+	DWORD clst		/* Cluster# to be converted */
+)
+{
+	clst -= 2;
+	if (clst >= fs->n_fatent - 2) return 0;		/* Invalid cluster# */
+	return clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+/* Hidden API for hacks and disk tools */
+
+DWORD get_fat (	/* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x0FFFFFFF:Cluster status */
+	FATFS* fs,	/* File system object */
+	DWORD clst	/* FAT index number (cluster number) to get the value */
+)
+{
+	UINT wc, bc;
+	BYTE *p;
+	DWORD val;
+
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check range */
+		val = 1;	/* Internal error */
+
+	} else {
+		val = 0xFFFFFFFF;	/* Default value falls on disk error */
+
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc = fs->win.d8[bc++ % SS(fs)];
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc |= fs->win.d8[bc % SS(fs)] << 8;
+			val = clst & 1 ? wc >> 4 : (wc & 0xFFF);
+			break;
+
+		case FS_FAT16 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+			p = &fs->win.d8[clst * 2 % SS(fs)];
+			val = LD_WORD(p);
+			break;
+
+		case FS_FAT32 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+			p = &fs->win.d8[clst * 4 % SS(fs)];
+			val = LD_DWORD(p) & 0x0FFFFFFF;
+			break;
+
+		default:
+			val = 1;	/* Internal error */
+		}
+	}
+
+	return val;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry                              */
+/*-----------------------------------------------------------------------*/
+/* Hidden API for hacks and disk tools */
+
+#if !_FS_READONLY
+FRESULT put_fat (
+	FATFS* fs,	/* File system object */
+	DWORD clst,	/* FAT index number (cluster number) to be changed */
+	DWORD val	/* New value to be set to the entry */
+)
+{
+	UINT bc;
+	BYTE *p;
+	FRESULT res;
+
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check range */
+		res = FR_INT_ERR;
+
+	} else {
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = &fs->win.d8[bc++ % SS(fs)];
+			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+			fs->wflag = 1;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = &fs->win.d8[bc % SS(fs)];
+			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT16 :
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+			if (res != FR_OK) break;
+			p = &fs->win.d8[clst * 2 % SS(fs)];
+			ST_WORD(p, (WORD)val);
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT32 :
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+			if (res != FR_OK) break;
+			p = &fs->win.d8[clst * 4 % SS(fs)];
+			val |= LD_DWORD(p) & 0xF0000000;
+			ST_DWORD(p, val);
+			fs->wflag = 1;
+			break;
+
+		default :
+			res = FR_INT_ERR;
+		}
+	}
+
+	return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain                                 */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT remove_chain (
+	FATFS* fs,			/* File system object */
+	DWORD clst			/* Cluster# to remove a chain from */
+)
+{
+	FRESULT res;
+	DWORD nxt;
+#if _USE_TRIM
+	DWORD scl = clst, ecl = clst, rt[2];
+#endif
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check range */
+		res = FR_INT_ERR;
+
+	} else {
+		res = FR_OK;
+		while (clst < fs->n_fatent) {			/* Not a last link? */
+			nxt = get_fat(fs, clst);			/* Get cluster status */
+			if (nxt == 0) break;				/* Empty cluster? */
+			if (nxt == 1) { res = FR_INT_ERR; break; }	/* Internal error? */
+			if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }	/* Disk error? */
+			res = put_fat(fs, clst, 0);			/* Mark the cluster "empty" */
+			if (res != FR_OK) break;
+			if (fs->free_clust != 0xFFFFFFFF) {	/* Update FSINFO */
+				fs->free_clust++;
+				fs->fsi_flag |= 1;
+			}
+#if _USE_TRIM
+			if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
+				ecl = nxt;
+			} else {				/* End of contiguous clusters */ 
+				rt[0] = clust2sect(fs, scl);					/* Start sector */
+				rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
+				disk_ioctl(fs->drv, CTRL_TRIM, rt);				/* Erase the block */
+				scl = ecl = nxt;
+			}
+#endif
+			clst = nxt;	/* Next cluster */
+		}
+	}
+
+	return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch or Create a cluster chain                      */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+	FATFS* fs,			/* File system object */
+	DWORD clst			/* Cluster# to stretch. 0 means create a new chain. */
+)
+{
+	DWORD cs, ncl, scl;
+	FRESULT res;
+
+
+	if (clst == 0) {		/* Create a new chain */
+		scl = fs->last_clust;			/* Get suggested start point */
+		if (!scl || scl >= fs->n_fatent) scl = 1;
+	}
+	else {					/* Stretch the current chain */
+		cs = get_fat(fs, clst);			/* Check the cluster status */
+		if (cs < 2) return 1;			/* Invalid value */
+		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+		scl = clst;
+	}
+
+	ncl = scl;				/* Start cluster */
+	for (;;) {
+		ncl++;							/* Next cluster */
+		if (ncl >= fs->n_fatent) {		/* Check wrap around */
+			ncl = 2;
+			if (ncl > scl) return 0;	/* No free cluster */
+		}
+		cs = get_fat(fs, ncl);			/* Get the cluster status */
+		if (cs == 0) break;				/* Found a free cluster */
+		if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
+			return cs;
+		if (ncl == scl) return 0;		/* No free cluster */
+	}
+
+	res = put_fat(fs, ncl, 0x0FFFFFFF);	/* Mark the new cluster "last link" */
+	if (res == FR_OK && clst != 0) {
+		res = put_fat(fs, clst, ncl);	/* Link it to the previous one if needed */
+	}
+	if (res == FR_OK) {
+		fs->last_clust = ncl;			/* Update FSINFO */
+		if (fs->free_clust != 0xFFFFFFFF) {
+			fs->free_clust--;
+			fs->fsi_flag |= 1;
+		}
+	} else {
+		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
+	}
+
+	return ncl;		/* Return new cluster number or error code */
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table        */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_FASTSEEK
+static
+DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
+	FIL* fp,		/* Pointer to the file object */
+	DWORD ofs		/* File offset to be converted to cluster# */
+)
+{
+	DWORD cl, ncl, *tbl;
+
+
+	tbl = fp->cltbl + 1;	/* Top of CLMT */
+	cl = ofs / SS(fp->fs) / fp->fs->csize;	/* Cluster order from top of the file */
+	for (;;) {
+		ncl = *tbl++;			/* Number of cluters in the fragment */
+		if (!ncl) return 0;		/* End of table? (error) */
+		if (cl < ncl) break;	/* In this fragment? */
+		cl -= ncl; tbl++;		/* Next fragment */
+	}
+	return cl + *tbl;	/* Return the cluster number */
+}
+#endif	/* _USE_FASTSEEK */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (
+	DIR* dp,		/* Pointer to directory object */
+	UINT idx		/* Index of directory table */
+)
+{
+	DWORD clst, sect;
+	UINT ic;
+
+
+	dp->index = (WORD)idx;	/* Current index */
+	clst = dp->sclust;		/* Table start cluster (0:root) */
+	if (clst == 1 || clst >= dp->fs->n_fatent)	/* Check start cluster range */
+		return FR_INT_ERR;
+	if (!clst && dp->fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = dp->fs->dirbase;
+
+	if (clst == 0) {	/* Static table (root-directory in FAT12/16) */
+		if (idx >= dp->fs->n_rootdir)	/* Is index out of range? */
+			return FR_INT_ERR;
+		sect = dp->fs->dirbase;
+	}
+	else {				/* Dynamic table (root-directory in FAT32 or sub-directory) */
+		ic = SS(dp->fs) / SZ_DIRE * dp->fs->csize;	/* Entries per cluster */
+		while (idx >= ic) {	/* Follow cluster chain */
+			clst = get_fat(dp->fs, clst);				/* Get next cluster */
+			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+			if (clst < 2 || clst >= dp->fs->n_fatent)	/* Reached to end of table or internal error */
+				return FR_INT_ERR;
+			idx -= ic;
+		}
+		sect = clust2sect(dp->fs, clst);
+	}
+	dp->clust = clst;	/* Current cluster# */
+	if (!sect) return FR_INT_ERR;
+	dp->sect = sect + idx / (SS(dp->fs) / SZ_DIRE);					/* Sector# of the directory entry */
+	dp->dir = dp->fs->win.d8 + (idx % (SS(dp->fs) / SZ_DIRE)) * SZ_DIRE;	/* Ptr to the entry in the sector */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+	DIR* dp,		/* Pointer to the directory object */
+	int stretch		/* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+	DWORD clst;
+	UINT i;
+#if !_FS_READONLY
+	UINT c;
+#endif
+
+
+	i = dp->index + 1;
+	if (!(i & 0xFFFF) || !dp->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % (SS(dp->fs) / SZ_DIRE))) {	/* Sector changed? */
+		dp->sect++;					/* Next sector */
+
+		if (!dp->clust) {		/* Static table */
+			if (i >= dp->fs->n_rootdir)	/* Report EOT if it reached end of static table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / (SS(dp->fs) / SZ_DIRE)) & (dp->fs->csize - 1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dp->fs, dp->clust);				/* Get next cluster */
+				if (clst <= 1) return FR_INT_ERR;
+				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+				if (clst >= dp->fs->n_fatent) {					/* If it reached end of dynamic table, */
+#if !_FS_READONLY
+					if (!stretch) return FR_NO_FILE;			/* If do not stretch, report EOT */
+					clst = create_chain(dp->fs, dp->clust);		/* Stretch cluster chain */
+					if (clst == 0) return FR_DENIED;			/* No free cluster */
+					if (clst == 1) return FR_INT_ERR;
+					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+					/* Clean-up stretched table */
+					if (sync_window(dp->fs)) return FR_DISK_ERR;/* Flush disk access window */
+					mem_set(dp->fs->win.d8, 0, SS(dp->fs));		/* Clear window buffer */
+					dp->fs->winsect = clust2sect(dp->fs, clst);	/* Cluster start sector */
+					for (c = 0; c < dp->fs->csize; c++) {		/* Fill the new cluster with 0 */
+						dp->fs->wflag = 1;
+						if (sync_window(dp->fs)) return FR_DISK_ERR;
+						dp->fs->winsect++;
+					}
+					dp->fs->winsect -= c;						/* Rewind window offset */
+#else
+					if (!stretch) return FR_NO_FILE;			/* If do not stretch, report EOT (this is to suppress warning) */
+					return FR_NO_FILE;							/* Report EOT */
+#endif
+				}
+				dp->clust = clst;				/* Initialize data for new cluster */
+				dp->sect = clust2sect(dp->fs, clst);
+			}
+		}
+	}
+
+	dp->index = (WORD)i;	/* Current index */
+	dp->dir = dp->fs->win.d8 + (i % (SS(dp->fs) / SZ_DIRE)) * SZ_DIRE;	/* Current entry in the window */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Reserve directory entry                          */
+/*-----------------------------------------------------------------------*/
+
+#if !_FS_READONLY
+static
+FRESULT dir_alloc (
+	DIR* dp,	/* Pointer to the directory object */
+	UINT nent	/* Number of contiguous entries to allocate (1-21) */
+)
+{
+	FRESULT res;
+	UINT n;
+
+
+	res = dir_sdi(dp, 0);
+	if (res == FR_OK) {
+		n = 0;
+		do {
+			res = move_window(dp->fs, dp->sect);
+			if (res != FR_OK) break;
+			if (dp->dir[0] == DDEM || dp->dir[0] == 0) {	/* Is it a free entry? */
+				if (++n == nent) break;	/* A block of contiguous free entries is found */
+			} else {
+				n = 0;					/* Not a blank entry. Restart to search */
+			}
+			res = dir_next(dp, 1);		/* Next entry with table stretch enabled */
+		} while (res == FR_OK);
+	}
+	if (res == FR_NO_FILE) res = FR_DENIED;	/* No directory entry to allocate */
+	return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Load/Store start cluster number                  */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD ld_clust (
+	FATFS* fs,	/* Pointer to the fs object */
+	BYTE* dir	/* Pointer to the directory entry */
+)
+{
+	DWORD cl;
+
+	cl = LD_WORD(dir + DIR_FstClusLO);
+	if (fs->fs_type == FS_FAT32)
+		cl |= (DWORD)LD_WORD(dir + DIR_FstClusHI) << 16;
+
+	return cl;
+}
+
+
+#if !_FS_READONLY
+static
+void st_clust (
+	BYTE* dir,	/* Pointer to the directory entry */
+	DWORD cl	/* Value to be set */
+)
+{
+	ST_WORD(dir + DIR_FstClusLO, cl);
+	ST_WORD(dir + DIR_FstClusHI, cl >> 16);
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry   */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* Offset of LFN characters in the directory entry */
+
+
+static
+int cmp_lfn (			/* 1:Matched, 0:Not matched */
+	WCHAR* lfnbuf,		/* Pointer to the LFN to be compared */
+	BYTE* dir			/* Pointer to the directory entry containing a part of LFN */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13;	/* Get offset in the LFN buffer */
+	s = 0; wc = 1;
+	do {
+		uc = LD_WORD(dir + LfnOfs[s]);	/* Pick an LFN character from the entry */
+		if (wc) {	/* Last character has not been processed */
+			wc = ff_wtoupper(uc);		/* Convert it to upper case */
+			if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++]))	/* Compare it */
+				return 0;				/* Not matched */
+		} else {
+			if (uc != 0xFFFF) return 0;	/* Check filler */
+		}
+	} while (++s < 13);				/* Repeat until all characters in the entry are checked */
+
+	if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i])	/* Last segment matched but different length */
+		return 0;
+
+	return 1;						/* The part of LFN matched */
+}
+
+
+
+static
+int pick_lfn (			/* 1:Succeeded, 0:Buffer overflow */
+	WCHAR* lfnbuf,		/* Pointer to the Unicode-LFN buffer */
+	BYTE* dir			/* Pointer to the directory entry */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+
+	s = 0; wc = 1;
+	do {
+		uc = LD_WORD(dir + LfnOfs[s]);		/* Pick an LFN character from the entry */
+		if (wc) {	/* Last character has not been processed */
+			if (i >= _MAX_LFN) return 0;	/* Buffer overflow? */
+			lfnbuf[i++] = wc = uc;			/* Store it */
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	} while (++s < 13);						/* Read all character in the entry */
+
+	if (dir[LDIR_Ord] & LLEF) {				/* Put terminator if it is the last LFN part */
+		if (i >= _MAX_LFN) return 0;		/* Buffer overflow? */
+		lfnbuf[i] = 0;
+	}
+
+	return 1;
+}
+
+
+#if !_FS_READONLY
+static
+void fit_lfn (
+	const WCHAR* lfnbuf,	/* Pointer to the LFN buffer */
+	BYTE* dir,				/* Pointer to the directory entry */
+	BYTE ord,				/* LFN order (1-20) */
+	BYTE sum				/* SFN sum */
+)
+{
+	UINT i, s;
+	WCHAR wc;
+
+
+	dir[LDIR_Chksum] = sum;			/* Set check sum */
+	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
+	dir[LDIR_Type] = 0;
+	ST_WORD(dir + LDIR_FstClusLO, 0);
+
+	i = (ord - 1) * 13;				/* Get offset in the LFN buffer */
+	s = wc = 0;
+	do {
+		if (wc != 0xFFFF) wc = lfnbuf[i++];	/* Get an effective character */
+		ST_WORD(dir+LfnOfs[s], wc);	/* Put it */
+		if (!wc) wc = 0xFFFF;		/* Padding characters following last character */
+	} while (++s < 13);
+	if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLEF;	/* Bottom LFN part is the start of LFN sequence */
+	dir[LDIR_Ord] = ord;			/* Set the LFN order */
+}
+
+#endif
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create numbered name                                                  */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+void gen_numname (
+	BYTE* dst,			/* Pointer to the buffer to store numbered SFN */
+	const BYTE* src,	/* Pointer to SFN */
+	const WCHAR* lfn,	/* Pointer to LFN */
+	UINT seq			/* Sequence number */
+)
+{
+	BYTE ns[8], c;
+	UINT i, j;
+	WCHAR wc;
+	DWORD sr;
+
+
+	mem_cpy(dst, src, 11);
+
+	if (seq > 5) {	/* On many collisions, generate a hash number instead of sequential number */
+		sr = seq;
+		while (*lfn) {	/* Create a CRC */
+			wc = *lfn++;
+			for (i = 0; i < 16; i++) {
+				sr = (sr << 1) + (wc & 1);
+				wc >>= 1;
+				if (sr & 0x10000) sr ^= 0x11021;
+			}
+		}
+		seq = (UINT)sr;
+	}
+
+	/* itoa (hexdecimal) */
+	i = 7;
+	do {
+		c = (seq % 16) + '0';
+		if (c > '9') c += 7;
+		ns[i--] = c;
+		seq /= 16;
+	} while (seq);
+	ns[i] = '~';
+
+	/* Append the number */
+	for (j = 0; j < i && dst[j] != ' '; j++) {
+		if (IsDBCS1(dst[j])) {
+			if (j == i - 1) break;
+			j++;
+		}
+	}
+	do {
+		dst[j++] = (i < 8) ? ns[i++] : ' ';
+	} while (j < 8);
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Calculate sum of an SFN                                               */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+BYTE sum_sfn (
+	const BYTE* dir		/* Pointer to the SFN entry */
+)
+{
+	BYTE sum = 0;
+	UINT n = 11;
+
+	do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n);
+	return sum;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR* dp			/* Pointer to the directory object linked to the file name */
+)
+{
+	FRESULT res;
+	BYTE c, *dir;
+#if _USE_LFN
+	BYTE a, ord, sum;
+#endif
+
+	res = dir_sdi(dp, 0);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+#if _USE_LFN
+	ord = sum = 0xFF; dp->lfn_idx = 0xFFFF;	/* Reset LFN sequence */
+#endif
+	do {
+		res = move_window(dp->fs, dp->sect);
+		if (res != FR_OK) break;
+		dir = dp->dir;					/* Ptr to the directory entry of current index */
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+#if _USE_LFN	/* LFN configuration */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
+			ord = 0xFF; dp->lfn_idx = 0xFFFF;	/* Reset LFN sequence */
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (dp->lfn) {
+					if (c & LLEF) {		/* Is it start of LFN sequence? */
+						sum = dir[LDIR_Chksum];
+						c &= ~LLEF; ord = c;	/* LFN start order */
+						dp->lfn_idx = dp->index;	/* Start index of LFN */
+					}
+					/* Check validity of the LFN entry and compare it with given name */
+					ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF;
+				}
+			} else {					/* An SFN entry is found */
+				if (!ord && sum == sum_sfn(dir)) break;	/* LFN matched? */
+				if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dir, dp->fn, 11)) break;	/* SFN matched? */
+				ord = 0xFF; dp->lfn_idx = 0xFFFF;	/* Reset LFN sequence */
+			}
+		}
+#else		/* Non LFN configuration */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dp->fn, 11)) /* Is it a valid entry? */
+			break;
+#endif
+		res = dir_next(dp, 0);		/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2
+static
+FRESULT dir_read (
+	DIR* dp,		/* Pointer to the directory object */
+	int vol			/* Filtered by 0:file/directory or 1:volume label */
+)
+{
+	FRESULT res;
+	BYTE a, c, *dir;
+#if _USE_LFN
+	BYTE ord = 0xFF, sum = 0xFF;
+#endif
+
+	res = FR_NO_FILE;
+	while (dp->sect) {
+		res = move_window(dp->fs, dp->sect);
+		if (res != FR_OK) break;
+		dir = dp->dir;					/* Ptr to the directory entry of current index */
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+#if _USE_LFN	/* LFN configuration */
+		if (c == DDEM || (!_FS_RPATH && c == '.') || (int)((a & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
+			ord = 0xFF;
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (c & LLEF) {			/* Is it start of LFN sequence? */
+					sum = dir[LDIR_Chksum];
+					c &= ~LLEF; ord = c;
+					dp->lfn_idx = dp->index;
+				}
+				/* Check LFN validity and capture it */
+				ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF;
+			} else {					/* An SFN entry is found */
+				if (ord || sum != sum_sfn(dir))	/* Is there a valid LFN? */
+					dp->lfn_idx = 0xFFFF;		/* It has no LFN. */
+				break;
+			}
+		}
+#else		/* Non LFN configuration */
+		if (c != DDEM && (_FS_RPATH || c != '.') && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol)	/* Is it a valid entry? */
+			break;
+#endif
+		res = dir_next(dp, 0);				/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dp->sect = 0;
+
+	return res;
+}
+#endif	/* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory                                   */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT dir_register (	/* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */
+	DIR* dp				/* Target directory with object name to be created */
+)
+{
+	FRESULT res;
+#if _USE_LFN	/* LFN configuration */
+	UINT n, nent;
+	BYTE sn[12], *fn, sum;
+	WCHAR *lfn;
+
+
+	fn = dp->fn; lfn = dp->lfn;
+	mem_cpy(sn, fn, 12);
+
+	if (_FS_RPATH && (sn[NSFLAG] & NS_DOT))		/* Cannot create dot entry */
+		return FR_INVALID_NAME;
+
+	if (sn[NSFLAG] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
+		fn[NSFLAG] = 0; dp->lfn = 0;			/* Find only SFN */
+		for (n = 1; n < 100; n++) {
+			gen_numname(fn, sn, lfn, n);	/* Generate a numbered name */
+			res = dir_find(dp);				/* Check if the name collides with existing SFN */
+			if (res != FR_OK) break;
+		}
+		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
+		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
+		fn[NSFLAG] = sn[NSFLAG]; dp->lfn = lfn;
+	}
+
+	if (sn[NSFLAG] & NS_LFN) {			/* When LFN is to be created, allocate entries for an SFN + LFNs. */
+		for (n = 0; lfn[n]; n++) ;
+		nent = (n + 25) / 13;
+	} else {						/* Otherwise allocate an entry for an SFN  */
+		nent = 1;
+	}
+	res = dir_alloc(dp, nent);		/* Allocate entries */
+
+	if (res == FR_OK && --nent) {	/* Set LFN entry if needed */
+		res = dir_sdi(dp, dp->index - nent);
+		if (res == FR_OK) {
+			sum = sum_sfn(dp->fn);	/* Sum value of the SFN tied to the LFN */
+			do {					/* Store LFN entries in bottom first */
+				res = move_window(dp->fs, dp->sect);
+				if (res != FR_OK) break;
+				fit_lfn(dp->lfn, dp->dir, (BYTE)nent, sum);
+				dp->fs->wflag = 1;
+				res = dir_next(dp, 0);	/* Next entry */
+			} while (res == FR_OK && --nent);
+		}
+	}
+#else	/* Non LFN configuration */
+	res = dir_alloc(dp, 1);		/* Allocate an entry for SFN */
+#endif
+
+	if (res == FR_OK) {				/* Set SFN entry */
+		res = move_window(dp->fs, dp->sect);
+		if (res == FR_OK) {
+			mem_set(dp->dir, 0, SZ_DIRE);	/* Clean the entry */
+			mem_cpy(dp->dir, dp->fn, 11);	/* Put SFN */
+#if _USE_LFN
+			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
+#endif
+			dp->fs->wflag = 1;
+		}
+	}
+
+	return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory                                   */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY && !_FS_MINIMIZE
+static
+FRESULT dir_remove (	/* FR_OK: Successful, FR_DISK_ERR: A disk error */
+	DIR* dp				/* Directory object pointing the entry to be removed */
+)
+{
+	FRESULT res;
+#if _USE_LFN	/* LFN configuration */
+	UINT i;
+
+	i = dp->index;	/* SFN index */
+	res = dir_sdi(dp, (dp->lfn_idx == 0xFFFF) ? i : dp->lfn_idx);	/* Goto the SFN or top of the LFN entries */
+	if (res == FR_OK) {
+		do {
+			res = move_window(dp->fs, dp->sect);
+			if (res != FR_OK) break;
+			mem_set(dp->dir, 0, SZ_DIRE);	/* Clear and mark the entry "deleted" */
+			*dp->dir = DDEM;
+			dp->fs->wflag = 1;
+			if (dp->index >= i) break;	/* When reached SFN, all entries of the object has been deleted. */
+			res = dir_next(dp, 0);		/* Next entry */
+		} while (res == FR_OK);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;
+	}
+
+#else			/* Non LFN configuration */
+	res = dir_sdi(dp, dp->index);
+	if (res == FR_OK) {
+		res = move_window(dp->fs, dp->sect);
+		if (res == FR_OK) {
+			mem_set(dp->dir, 0, SZ_DIRE);	/* Clear and mark the entry "deleted" */
+			*dp->dir = DDEM;
+			dp->fs->wflag = 1;
+		}
+	}
+#endif
+
+	return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+static
+void get_fileinfo (		/* No return code */
+	DIR* dp,			/* Pointer to the directory object */
+	FILINFO* fno	 	/* Pointer to the file information to be filled */
+)
+{
+	UINT i;
+	TCHAR *p, c;
+	BYTE *dir;
+#if _USE_LFN
+	WCHAR w, *lfn;
+#endif
+
+	p = fno->fname;
+	if (dp->sect) {		/* Get SFN */
+		dir = dp->dir;
+		i = 0;
+		while (i < 11) {		/* Copy name body and extension */
+			c = (TCHAR)dir[i++];
+			if (c == ' ') continue;				/* Skip padding spaces */
+			if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+			if (i == 9) *p++ = '.';				/* Insert a . if extension is exist */
+#if _USE_LFN
+			if (IsUpper(c) && (dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY)))
+				c += 0x20;			/* To lower */
+#if _LFN_UNICODE
+			if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dir[i]))
+				c = c << 8 | dir[i++];
+			c = ff_convert(c, 1);	/* OEM -> Unicode */
+			if (!c) c = '?';
+#endif
+#endif
+			*p++ = c;
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir + DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir + DIR_WrtDate);	/* Date */
+		fno->ftime = LD_WORD(dir + DIR_WrtTime);	/* Time */
+	}
+	*p = 0;		/* Terminate SFN string by a \0 */
+
+#if _USE_LFN
+	if (fno->lfname) {
+		i = 0; p = fno->lfname;
+		if (dp->sect && fno->lfsize && dp->lfn_idx != 0xFFFF) {	/* Get LFN if available */
+			lfn = dp->lfn;
+			while ((w = *lfn++) != 0) {		/* Get an LFN character */
+#if !_LFN_UNICODE
+				w = ff_convert(w, 0);		/* Unicode -> OEM */
+				if (!w) { i = 0; break; }	/* No LFN if it could not be converted */
+				if (_DF1S && w >= 0x100)	/* Put 1st byte if it is a DBC (always false on SBCS cfg) */
+					p[i++] = (TCHAR)(w >> 8);
+#endif
+				if (i >= fno->lfsize - 1) { i = 0; break; }	/* No LFN if buffer overflow */
+				p[i++] = (TCHAR)w;
+			}
+		}
+		p[i] = 0;	/* Terminate LFN string by a \0 */
+	}
+#endif
+}
+#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pattern matching                                                      */
+/*-----------------------------------------------------------------------*/
+#if _USE_FIND && _FS_MINIMIZE <= 1
+static
+WCHAR get_achar (		/* Get a character and advances ptr 1 or 2 */
+	const TCHAR** ptr	/* Pointer to pointer to the SBCS/DBCS/Unicode string */
+)
+{
+	WCHAR chr;
+
+#if !_LFN_UNICODE
+	chr = (BYTE)*(*ptr)++;					/* Get a byte */
+	if (IsLower(chr)) chr -= 0x20;			/* To upper ASCII char */
+	if (IsDBCS1(chr) && IsDBCS2(**ptr))		/* Get DBC 2nd byte if needed */
+		chr = chr << 8 | (BYTE)*(*ptr)++;
+#ifdef _EXCVT
+	if (chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#endif
+#else
+	chr = ff_wtoupper(*(*ptr)++);			/* Get a word and to upper */
+#endif
+	return chr;
+}
+
+
+static
+int pattern_matching (	/* Return value: 0:mismatched, 1:matched */
+	const TCHAR* pat,	/* Matching pattern */
+	const TCHAR* nam,	/* String to be tested */
+	int skip,			/* Number of pre-skip chars (number of ?s) */
+	int inf				/* Infinite search (* specified) */
+)
+{
+	const TCHAR *pp, *np;
+	WCHAR pc, nc;
+	int nm, nx;
+
+
+	while (skip--) {				/* Pre-skip name chars */
+		if (!get_achar(&nam)) return 0;	/* Branch mismatched if less name chars */
+	}
+	if (!*pat && inf) return 1;		/* (short circuit) */
+
+	do {
+		pp = pat; np = nam;			/* Top of pattern and name to match */
+		for (;;) {
+			if (*pp == '?' || *pp == '*') {	/* Wildcard? */
+				nm = nx = 0;
+				do {				/* Analyze the wildcard chars */
+					if (*pp++ == '?') nm++; else nx = 1;
+				} while (*pp == '?' || *pp == '*');
+				if (pattern_matching(pp, np, nm, nx)) return 1;	/* Test new branch (recurs upto number of wildcard blocks in the pattern) */
+				nc = *np; break;	/* Branch mismatched */
+			}
+			pc = get_achar(&pp);	/* Get a pattern char */
+			nc = get_achar(&np);	/* Get a name char */
+			if (pc != nc) break;	/* Branch mismatched? */
+			if (!pc) return 1;		/* Branch matched? (matched at end of both strings) */
+		}
+		get_achar(&nam);			/* nam++ */
+	} while (inf && nc);			/* Retry until end of name if infinite search is specified */
+
+	return 0;
+}
+#endif /* _USE_FIND && _FS_MINIMIZE <= 1 */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (
+	DIR* dp,			/* Pointer to the directory object */
+	const TCHAR** path	/* Pointer to pointer to the segment in the path string */
+)
+{
+#if _USE_LFN	/* LFN configuration */
+	BYTE b, cf;
+	WCHAR w, *lfn;
+	UINT i, ni, si, di;
+	const TCHAR *p;
+
+	/* Create LFN in Unicode */
+	for (p = *path; *p == '/' || *p == '\\'; p++) ;	/* Strip duplicated separator */
+	lfn = dp->lfn;
+	si = di = 0;
+	for (;;) {
+		w = p[si++];					/* Get a character */
+		if (w < ' ' || w == '/' || w == '\\') break;	/* Break on end of segment */
+		if (di >= _MAX_LFN)				/* Reject too long name */
+			return FR_INVALID_NAME;
+#if !_LFN_UNICODE
+		w &= 0xFF;
+		if (IsDBCS1(w)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+#if _DF1S
+			b = (BYTE)p[si++];			/* Get 2nd byte */
+			w = (w << 8) + b;			/* Create a DBC */
+			if (!IsDBCS2(b))
+				return FR_INVALID_NAME;	/* Reject invalid sequence */
+#endif
+		}
+		w = ff_convert(w, 1);			/* Convert ANSI/OEM to Unicode */
+		if (!w) return FR_INVALID_NAME;	/* Reject invalid code */
+#endif
+		if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal characters for LFN */
+			return FR_INVALID_NAME;
+		lfn[di++] = w;					/* Store the Unicode character */
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	cf = (w < ' ') ? NS_LAST : 0;		/* Set last segment flag if end of path */
+#if _FS_RPATH
+	if ((di == 1 && lfn[di - 1] == '.') || /* Is this a dot entry? */
+		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {
+		lfn[di] = 0;
+		for (i = 0; i < 11; i++)
+			dp->fn[i] = (i < di) ? '.' : ' ';
+		dp->fn[i] = cf | NS_DOT;		/* This is a dot entry */
+		return FR_OK;
+	}
+#endif
+	while (di) {						/* Strip trailing spaces and dots */
+		w = lfn[di - 1];
+		if (w != ' ' && w != '.') break;
+		di--;
+	}
+	if (!di) return FR_INVALID_NAME;	/* Reject nul string */
+
+	lfn[di] = 0;						/* LFN is created */
+
+	/* Create SFN in directory form */
+	mem_set(dp->fn, ' ', 11);
+	for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ;	/* Strip leading spaces and dots */
+	if (si) cf |= NS_LOSS | NS_LFN;
+	while (di && lfn[di - 1] != '.') di--;	/* Find extension (di<=si: no extension) */
+
+	b = i = 0; ni = 8;
+	for (;;) {
+		w = lfn[si++];					/* Get an LFN character */
+		if (!w) break;					/* Break on end of the LFN */
+		if (w == ' ' || (w == '.' && si != di)) {	/* Remove spaces and dots */
+			cf |= NS_LOSS | NS_LFN; continue;
+		}
+
+		if (i >= ni || si == di) {		/* Extension or end of SFN */
+			if (ni == 11) {				/* Long extension */
+				cf |= NS_LOSS | NS_LFN; break;
+			}
+			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Out of 8.3 format */
+			if (si > di) break;			/* No extension */
+			si = di; i = 8; ni = 11;	/* Enter extension section */
+			b <<= 2; continue;
+		}
+
+		if (w >= 0x80) {				/* Non ASCII character */
+#ifdef _EXCVT
+			w = ff_convert(w, 0);		/* Unicode -> OEM code */
+			if (w) w = ExCvt[w - 0x80];	/* Convert extended character to upper (SBCS) */
+#else
+			w = ff_convert(ff_wtoupper(w), 0);	/* Upper converted Unicode -> OEM code */
+#endif
+			cf |= NS_LFN;				/* Force create LFN entry */
+		}
+
+		if (_DF1S && w >= 0x100) {		/* DBC (always false at SBCS cfg) */
+			if (i >= ni - 1) {
+				cf |= NS_LOSS | NS_LFN; i = ni; continue;
+			}
+			dp->fn[i++] = (BYTE)(w >> 8);
+		} else {						/* SBC */
+			if (!w || chk_chr("+,;=[]", w)) {	/* Replace illegal characters for SFN */
+				w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+			} else {
+				if (IsUpper(w)) {		/* ASCII large capital */
+					b |= 2;
+				} else {
+					if (IsLower(w)) {	/* ASCII small capital */
+						b |= 1; w -= 0x20;
+					}
+				}
+			}
+		}
+		dp->fn[i++] = (BYTE)w;
+	}
+
+	if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM;	/* If the first character collides with deleted mark, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;
+	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03)	/* Create LFN entry when there are composite capitals */
+		cf |= NS_LFN;
+	if (!(cf & NS_LFN)) {						/* When LFN is in 8.3 format without extended character, NT flags are created */
+		if ((b & 0x03) == 0x01) cf |= NS_EXT;	/* NT flag (Extension has only small capital) */
+		if ((b & 0x0C) == 0x04) cf |= NS_BODY;	/* NT flag (Filename has only small capital) */
+	}
+
+	dp->fn[NSFLAG] = cf;	/* SFN is created */
+
+	return FR_OK;
+
+
+#else	/* Non-LFN configuration */
+	BYTE b, c, d, *sfn;
+	UINT ni, si, i;
+	const char *p;
+
+	/* Create file name in directory form */
+	for (p = *path; *p == '/' || *p == '\\'; p++) ;	/* Strip duplicated separator */
+	sfn = dp->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = b = 0; ni = 8;
+#if _FS_RPATH
+	if (p[si] == '.') { /* Is this a dot entry? */
+		for (;;) {
+			c = (BYTE)p[si++];
+			if (c != '.' || si >= 3) break;
+			sfn[i++] = c;
+		}
+		if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+		*path = &p[si];									/* Return pointer to the next segment */
+		sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of path */
+		return FR_OK;
+	}
+#endif
+	for (;;) {
+		c = (BYTE)p[si++];
+		if (c <= ' ' || c == '/' || c == '\\') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') return FR_INVALID_NAME;
+			i = 8; ni = 11;
+			b <<= 2; continue;
+		}
+		if (c >= 0x80) {				/* Extended character? */
+			b |= 3;						/* Eliminate NT flag */
+#ifdef _EXCVT
+			c = ExCvt[c - 0x80];		/* To upper extended characters (SBCS cfg) */
+#else
+#if !_DF1S
+			return FR_INVALID_NAME;		/* Reject extended characters (ASCII cfg) */
+#endif
+#endif
+		}
+		if (IsDBCS1(c)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+			d = (BYTE)p[si++];			/* Get 2nd byte */
+			if (!IsDBCS2(d) || i >= ni - 1)	/* Reject invalid DBC */
+				return FR_INVALID_NAME;
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* SBC */
+			if (chk_chr("\"*+,:;<=>\?[]|\x7F", c))	/* Reject illegal chrs for SFN */
+				return FR_INVALID_NAME;
+			if (IsUpper(c)) {			/* ASCII large capital? */
+				b |= 2;
+			} else {
+				if (IsLower(c)) {		/* ASCII small capital? */
+					b |= 1; c -= 0x20;
+				}
+			}
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	c = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of path */
+
+	if (!i) return FR_INVALID_NAME;		/* Reject nul string */
+	if (sfn[0] == DDEM) sfn[0] = RDDEM;	/* When first character collides with DDEM, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;
+	if ((b & 0x03) == 0x01) c |= NS_EXT;	/* NT flag (Name extension has only small capital) */
+	if ((b & 0x0C) == 0x04) c |= NS_BODY;	/* NT flag (Name body has only small capital) */
+
+	sfn[NSFLAG] = c;		/* Store NT flag, File name is created */
+
+	return FR_OK;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR* dp,			/* Directory object to return last directory and found object */
+	const TCHAR* path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+	BYTE *dir, ns;
+
+
+#if _FS_RPATH
+	if (*path == '/' || *path == '\\') {	/* There is a heading separator */
+		path++;	dp->sclust = 0;				/* Strip it and start from the root directory */
+	} else {								/* No heading separator */
+		dp->sclust = dp->fs->cdir;			/* Start from the current directory */
+	}
+#else
+	if (*path == '/' || *path == '\\')		/* Strip heading separator if exist */
+		path++;
+	dp->sclust = 0;							/* Always start from the root directory */
+#endif
+
+	if ((UINT)*path < ' ') {				/* Null path name is the origin directory itself */
+		res = dir_sdi(dp, 0);
+		dp->dir = 0;
+	} else {								/* Follow path */
+		for (;;) {
+			res = create_name(dp, &path);	/* Get a segment name of the path */
+			if (res != FR_OK) break;
+			res = dir_find(dp);				/* Find an object with the sagment name */
+			ns = dp->fn[NSFLAG];
+			if (res != FR_OK) {				/* Failed to find the object */
+				if (res == FR_NO_FILE) {	/* Object is not found */
+					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, */
+						dp->sclust = 0; dp->dir = 0;	/* it is the root directory and stay there */
+						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+						res = FR_OK;					/* Ended at the root directroy. Function completed. */
+					} else {							/* Could not find the object */
+						if (!(ns & NS_LAST)) res = FR_NO_PATH;	/* Adjust error code if not last segment */
+					}
+				}
+				break;
+			}
+			if (ns & NS_LAST) break;			/* Last segment matched. Function completed. */
+			dir = dp->dir;						/* Follow the sub-directory */
+			if (!(dir[DIR_Attr] & AM_DIR)) {	/* It is not a sub-directory and cannot follow */
+				res = FR_NO_PATH; break;
+			}
+			dp->sclust = ld_clust(dp->fs, dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get logical drive number from path name                               */
+/*-----------------------------------------------------------------------*/
+
+static
+int get_ldnumber (		/* Returns logical drive number (-1:invalid drive) */
+	const TCHAR** path	/* Pointer to pointer to the path name */
+)
+{
+	const TCHAR *tp, *tt;
+	UINT i;
+	int vol = -1;
+#if _STR_VOLUME_ID		/* Find string drive id */
+	static const char* const str[] = {_VOLUME_STRS};
+	const char *sp;
+	char c;
+	TCHAR tc;
+#endif
+
+
+	if (*path) {	/* If the pointer is not a null */
+		for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ;	/* Find ':' in the path */
+		if (*tt == ':') {	/* If a ':' is exist in the path name */
+			tp = *path;
+			i = *tp++ - '0'; 
+			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = ++tt;
+				}
+			}
+#if _STR_VOLUME_ID
+			 else {	/* No numeric drive number, find string drive id */
+				i = 0; tt++;
+				do {
+					sp = str[i]; tp = *path;
+					do {	/* Compare a string drive id with path name */
+						c = *sp++; tc = *tp++;
+						if (IsLower(tc)) tc -= 0x20;
+					} while (c && (TCHAR)c == tc);
+				} while ((c || tp != tt) && ++i < _VOLUMES);	/* Repeat for each id until pattern match */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = tt;
+				}
+			}
+#endif
+			return vol;
+		}
+#if _FS_RPATH && _VOLUMES >= 2
+		vol = CurrVol;	/* Current drive */
+#else
+		vol = 0;		/* Drive 0 */
+#endif
+	}
+	return vol;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT boot sector                   */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:FAT boor sector, 1:Valid boor sector but not FAT, 2:Not a boot sector, 3:Disk error */
+	FATFS* fs,	/* File system object */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	fs->wflag = 0; fs->winsect = 0xFFFFFFFF;	/* Invaidate window */
+	if (move_window(fs, sect) != FR_OK)			/* Load boot record */
+		return 3;
+
+	if (LD_WORD(&fs->win.d8[BS_55AA]) != 0xAA55)	/* Check boot record signature (always placed at offset 510 even if the sector size is >512) */
+		return 2;
+
+	if ((LD_DWORD(&fs->win.d8[BS_FilSysType]) & 0xFFFFFF) == 0x544146)		/* Check "FAT" string */
+		return 0;
+	if ((LD_DWORD(&fs->win.d8[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)	/* Check "FAT" string */
+		return 0;
+
+	return 1;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find logical drive and check if the volume is mounted                 */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
+	FATFS** rfs,		/* Pointer to pointer to the found file system object */
+	const TCHAR** path,	/* Pointer to pointer to the path name (drive number) */
+	BYTE wmode			/* !=0: Check write protection for write access */
+)
+{
+	BYTE fmt, *pt;
+	int vol;
+	DSTATUS stat;
+	DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
+	WORD nrsv;
+	FATFS *fs;
+	UINT i;
+
+
+	/* Get logical drive number from the path name */
+	*rfs = 0;
+	vol = get_ldnumber(path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	/* Check if the file system object is valid or not */
+	fs = FatFs[vol];					/* Get pointer to the file system object */
+	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
+
+	ENTER_FF(fs);						/* Lock the volume */
+	*rfs = fs;							/* Return pointer to the file system object */
+
+	if (fs->fs_type) {					/* If the volume has been mounted */
+		stat = disk_status(fs->drv);
+		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+			if (!_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check write protection if needed */
+				return FR_WRITE_PROTECTED;
+			return FR_OK;				/* The file system object is valid */
+		}
+	}
+
+	/* The file system object is not valid. */
+	/* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+
+	fs->fs_type = 0;					/* Clear the file system object */
+	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
+	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+	if (stat & STA_NOINIT)				/* Check if the initialization succeeded */
+		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+	if (!_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check disk write protection if needed */
+		return FR_WRITE_PROTECTED;
+#if _MAX_SS != _MIN_SS						/* Get sector size (multiple sector size cfg only) */
+	if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK
+		|| SS(fs) < _MIN_SS || SS(fs) > _MAX_SS) return FR_DISK_ERR;
+#endif
+	/* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */
+	bsect = 0;
+	fmt = check_fs(fs, bsect);					/* Load sector 0 and check if it is an FAT boot sector as SFD */
+	if (fmt == 1 || (!fmt && (LD2PT(vol)))) {	/* Not an FAT boot sector or forced partition number */
+		for (i = 0; i < 4; i++) {			/* Get partition offset */
+			pt = fs->win.d8 + MBR_Table + i * SZ_PTE;
+			br[i] = pt[4] ? LD_DWORD(&pt[8]) : 0;
+		}
+		i = LD2PT(vol);						/* Partition number: 0:auto, 1-4:forced */
+		if (i) i--;
+		do {								/* Find an FAT volume */
+			bsect = br[i];
+			fmt = bsect ? check_fs(fs, bsect) : 2;	/* Check the partition */
+		} while (!LD2PT(vol) && fmt && ++i < 4);
+	}
+	if (fmt == 3) return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
+	if (fmt) return FR_NO_FILESYSTEM;		/* No FAT volume is found */
+
+	/* An FAT volume is found. Following code initializes the file system object */
+
+	if (LD_WORD(fs->win.d8 + BPB_BytsPerSec) != SS(fs))	/* (BPB_BytsPerSec must be equal to the physical sector size) */
+		return FR_NO_FILESYSTEM;
+
+	fasize = LD_WORD(fs->win.d8 + BPB_FATSz16);			/* Number of sectors per FAT */
+	if (!fasize) fasize = LD_DWORD(fs->win.d8 + BPB_FATSz32);
+	fs->fsize = fasize;
+
+	fs->n_fats = fs->win.d8[BPB_NumFATs];					/* Number of FAT copies */
+	if (fs->n_fats != 1 && fs->n_fats != 2)				/* (Must be 1 or 2) */
+		return FR_NO_FILESYSTEM;
+	fasize *= fs->n_fats;								/* Number of sectors for FAT area */
+
+	fs->csize = fs->win.d8[BPB_SecPerClus];				/* Number of sectors per cluster */
+	if (!fs->csize || (fs->csize & (fs->csize - 1)))	/* (Must be power of 2) */
+		return FR_NO_FILESYSTEM;
+
+	fs->n_rootdir = LD_WORD(fs->win.d8 + BPB_RootEntCnt);	/* Number of root directory entries */
+	if (fs->n_rootdir % (SS(fs) / SZ_DIRE))				/* (Must be sector aligned) */
+		return FR_NO_FILESYSTEM;
+
+	tsect = LD_WORD(fs->win.d8 + BPB_TotSec16);			/* Number of sectors on the volume */
+	if (!tsect) tsect = LD_DWORD(fs->win.d8 + BPB_TotSec32);
+
+	nrsv = LD_WORD(fs->win.d8 + BPB_RsvdSecCnt);			/* Number of reserved sectors */
+	if (!nrsv) return FR_NO_FILESYSTEM;					/* (Must not be 0) */
+
+	/* Determine the FAT sub type */
+	sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIRE);	/* RSV + FAT + DIR */
+	if (tsect < sysect) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+	nclst = (tsect - sysect) / fs->csize;				/* Number of clusters */
+	if (!nclst) return FR_NO_FILESYSTEM;				/* (Invalid volume size) */
+	fmt = FS_FAT12;
+	if (nclst >= MIN_FAT16) fmt = FS_FAT16;
+	if (nclst >= MIN_FAT32) fmt = FS_FAT32;
+
+	/* Boundaries and Limits */
+	fs->n_fatent = nclst + 2;							/* Number of FAT entries */
+	fs->volbase = bsect;								/* Volume start sector */
+	fs->fatbase = bsect + nrsv; 						/* FAT start sector */
+	fs->database = bsect + sysect;						/* Data start sector */
+	if (fmt == FS_FAT32) {
+		if (fs->n_rootdir) return FR_NO_FILESYSTEM;		/* (BPB_RootEntCnt must be 0) */
+		fs->dirbase = LD_DWORD(fs->win.d8 + BPB_RootClus);	/* Root directory start cluster */
+		szbfat = fs->n_fatent * 4;						/* (Needed FAT size) */
+	} else {
+		if (!fs->n_rootdir)	return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must not be 0) */
+		fs->dirbase = fs->fatbase + fasize;				/* Root directory start sector */
+		szbfat = (fmt == FS_FAT16) ?					/* (Needed FAT size) */
+			fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+	}
+	if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs))	/* (BPB_FATSz must not be less than the size needed) */
+		return FR_NO_FILESYSTEM;
+
+#if !_FS_READONLY
+	/* Initialize cluster allocation information */
+	fs->last_clust = fs->free_clust = 0xFFFFFFFF;
+
+	/* Get fsinfo if available */
+	fs->fsi_flag = 0x80;
+#if (_FS_NOFSINFO & 3) != 3
+	if (fmt == FS_FAT32				/* Enable FSINFO only if FAT32 and BPB_FSInfo is 1 */
+		&& LD_WORD(fs->win.d8 + BPB_FSInfo) == 1
+		&& move_window(fs, bsect + 1) == FR_OK)
+	{
+		fs->fsi_flag = 0;
+		if (LD_WORD(fs->win.d8 + BS_55AA) == 0xAA55	/* Load FSINFO data if available */
+			&& LD_DWORD(fs->win.d8 + FSI_LeadSig) == 0x41615252
+			&& LD_DWORD(fs->win.d8 + FSI_StrucSig) == 0x61417272)
+		{
+#if (_FS_NOFSINFO & 1) == 0
+			fs->free_clust = LD_DWORD(fs->win.d8 + FSI_Free_Count);
+#endif
+#if (_FS_NOFSINFO & 2) == 0
+			fs->last_clust = LD_DWORD(fs->win.d8 + FSI_Nxt_Free);
+#endif
+		}
+	}
+#endif
+#endif
+	fs->fs_type = fmt;	/* FAT sub-type */
+	fs->id = ++Fsid;	/* File system mount ID */
+#if _FS_RPATH
+	fs->cdir = 0;		/* Set current directory to root */
+#endif
+#if _FS_LOCK			/* Clear file lock semaphores */
+	clear_lock(fs);
+#endif
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/directory object is valid or not                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate (	/* FR_OK(0): The object is valid, !=0: Invalid */
+	void* obj		/* Pointer to the object FIL/DIR to check validity */
+)
+{
+	FIL *fil = (FIL*)obj;	/* Assuming offset of .fs and .id in the FIL/DIR structure is identical */
+
+
+	if (!fil || !fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id || (disk_status(fil->fs->drv) & STA_NOINIT))
+		return FR_INVALID_OBJECT;
+
+	ENTER_FF(fil->fs);		/* Lock file system */
+
+	return FR_OK;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+	FATFS* fs,			/* Pointer to the file system object (NULL:unmount)*/
+	const TCHAR* path,	/* Logical drive number to be mounted/unmounted */
+	BYTE opt			/* 0:Do not mount (delayed mount), 1:Mount immediately */
+)
+{
+	FATFS *cfs;
+	int vol;
+	FRESULT res;
+	const TCHAR *rp = path;
+
+
+	vol = get_ldnumber(&rp);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	cfs = FatFs[vol];					/* Pointer to fs object */
+
+	if (cfs) {
+#if _FS_LOCK
+		clear_lock(cfs);
+#endif
+#if _FS_REENTRANT						/* Discard sync object of the current volume */
+		if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
+#endif
+		cfs->fs_type = 0;				/* Clear old fs object */
+	}
+
+	if (fs) {
+		fs->fs_type = 0;				/* Clear new fs object */
+#if _FS_REENTRANT						/* Create sync object for the new volume */
+		if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+	}
+	FatFs[vol] = fs;					/* Register new fs object */
+
+	if (!fs || opt != 1) return FR_OK;	/* Do not mount now, it will be mounted later */
+
+	res = find_volume(&fs, &path, 0);	/* Force mounted the volume */
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+	FIL* fp,			/* Pointer to the blank file object */
+	const TCHAR* path,	/* Pointer to the file name */
+	BYTE mode			/* Access mode and file open mode flags */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE *dir;
+	DEFINE_NAMEBUF;
+#if !_FS_READONLY
+	DWORD dw, cl;
+#endif
+
+
+	if (!fp) return FR_INVALID_OBJECT;
+	fp->fs = 0;			/* Clear file object */
+
+	/* Get logical drive number */
+#if !_FS_READONLY
+	mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
+	res = find_volume(&dj.fs, &path, (BYTE)(mode & ~FA_READ));
+#else
+	mode &= FA_READ;
+	res = find_volume(&dj.fs, &path, 0);
+#endif
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		dir = dj.dir;
+#if !_FS_READONLY	/* R/W configuration */
+		if (res == FR_OK) {
+			if (!dir)	/* Default directory itself */
+				res = FR_INVALID_NAME;
+#if _FS_LOCK
+			else
+				res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+#endif
+		}
+		/* Create or Open a file */
+		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+			if (res != FR_OK) {					/* No file, create new */
+				if (res == FR_NO_FILE)			/* There is no file to open, create a new entry */
+#if _FS_LOCK
+					res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+					res = dir_register(&dj);
+#endif
+				mode |= FA_CREATE_ALWAYS;		/* File is created */
+				dir = dj.dir;					/* New entry */
+			}
+			else {								/* Any object is already existing */
+				if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+					res = FR_DENIED;
+				} else {
+					if (mode & FA_CREATE_NEW)	/* Cannot create as new file */
+						res = FR_EXIST;
+				}
+			}
+			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate it if overwrite mode */
+				dw = GET_FATTIME();				/* Created time */
+				ST_DWORD(dir + DIR_CrtTime, dw);
+				dir[DIR_Attr] = 0;				/* Reset attribute */
+				ST_DWORD(dir + DIR_FileSize, 0);/* size = 0 */
+				cl = ld_clust(dj.fs, dir);		/* Get start cluster */
+				st_clust(dir, 0);				/* cluster = 0 */
+				dj.fs->wflag = 1;
+				if (cl) {						/* Remove the cluster chain if exist */
+					dw = dj.fs->winsect;
+					res = remove_chain(dj.fs, cl);
+					if (res == FR_OK) {
+						dj.fs->last_clust = cl - 1;	/* Reuse the cluster hole */
+						res = move_window(dj.fs, dw);
+					}
+				}
+			}
+		}
+		else {	/* Open an existing file */
+			if (res == FR_OK) {					/* Follow succeeded */
+				if (dir[DIR_Attr] & AM_DIR) {	/* It is a directory */
+					res = FR_NO_FILE;
+				} else {
+					if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
+						res = FR_DENIED;
+				}
+			}
+		}
+		if (res == FR_OK) {
+			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
+				mode |= FA__WRITTEN;
+			fp->dir_sect = dj.fs->winsect;		/* Pointer to the directory entry */
+			fp->dir_ptr = dir;
+#if _FS_LOCK
+			fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+			if (!fp->lockid) res = FR_INT_ERR;
+#endif
+		}
+
+#else				/* R/O configuration */
+		if (res == FR_OK) {					/* Follow succeeded */
+			dir = dj.dir;
+			if (!dir) {						/* Current directory itself */
+				res = FR_INVALID_NAME;
+			} else {
+				if (dir[DIR_Attr] & AM_DIR)	/* It is a directory */
+					res = FR_NO_FILE;
+			}
+		}
+#endif
+		FREE_BUF();
+
+		if (res == FR_OK) {
+			fp->flag = mode;					/* File access mode */
+			fp->err = 0;						/* Clear error flag */
+			fp->sclust = ld_clust(dj.fs, dir);	/* File start cluster */
+			fp->fsize = LD_DWORD(dir + DIR_FileSize);	/* File size */
+			fp->fptr = 0;						/* File pointer */
+			fp->dsect = 0;
+#if _USE_FASTSEEK
+			fp->cltbl = 0;						/* Normal seek mode */
+#endif
+			fp->fs = dj.fs;	 					/* Validate file object */
+			fp->id = fp->fs->id;
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+	FIL* fp, 		/* Pointer to the file object */
+	void* buff,		/* Pointer to data buffer */
+	UINT btr,		/* Number of bytes to read */
+	UINT* br		/* Pointer to number of bytes read */
+)
+{
+	FRESULT res;
+	DWORD clst, sect, remain;
+	UINT rcnt, cc;
+	BYTE csect, *rbuff = (BYTE*)buff;
+
+
+	*br = 0;	/* Clear read byte counter */
+
+	res = validate(fp);							/* Check validity */
+	if (res != FR_OK) LEAVE_FF(fp->fs, res);
+	if (fp->err)								/* Check error */
+		LEAVE_FF(fp->fs, (FRESULT)fp->err);
+	if (!(fp->flag & FA_READ)) 					/* Check access mode */
+		LEAVE_FF(fp->fs, FR_DENIED);
+	remain = fp->fsize - fp->fptr;
+	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+
+	for ( ;  btr;								/* Repeat until all data read */
+		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+		if ((fp->fptr % SS(fp->fs)) == 0) {		/* On the sector boundary? */
+			csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
+			if (!csect) {						/* On the cluster boundary? */
+				if (fp->fptr == 0) {			/* On the top of the file? */
+					clst = fp->sclust;			/* Follow from the origin */
+				} else {						/* Middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl)
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					else
+#endif
+						clst = get_fat(fp->fs, fp->clust);	/* Follow cluster chain on the FAT */
+				}
+				if (clst < 2) ABORT(fp->fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+				fp->clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fp->fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fp->fs, FR_INT_ERR);
+			sect += csect;
+			cc = btr / SS(fp->fs);				/* When remaining bytes >= sector size, */
+			if (cc) {							/* Read maximum contiguous sectors directly */
+				if (csect + cc > fp->fs->csize)	/* Clip at cluster boundary */
+					cc = fp->fs->csize - csect;
+				if (disk_read(fp->fs->drv, rbuff, sect, cc) != RES_OK)
+					ABORT(fp->fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+				if (fp->fs->wflag && fp->fs->winsect - sect < cc)
+					mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win.d8, SS(fp->fs));
+#else
+				if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
+					mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf.d8, SS(fp->fs));
+#endif
+#endif
+				rcnt = SS(fp->fs) * cc;			/* Number of bytes transferred */
+				continue;
+			}
+#if !_FS_TINY
+			if (fp->dsect != sect) {			/* Load data sector if not in cache */
+#if !_FS_READONLY
+				if (fp->flag & FA__DIRTY) {		/* Write-back dirty sector cache */
+					if (disk_write(fp->fs->drv, fp->buf.d8, fp->dsect, 1) != RES_OK)
+						ABORT(fp->fs, FR_DISK_ERR);
+					fp->flag &= ~FA__DIRTY;
+				}
+#endif
+				if (disk_read(fp->fs->drv, fp->buf.d8, sect, 1) != RES_OK)	/* Fill sector cache */
+					ABORT(fp->fs, FR_DISK_ERR);
+			}
+#endif
+			fp->dsect = sect;
+		}
+		rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));	/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+#if _FS_TINY
+		if (move_window(fp->fs, fp->dsect) != FR_OK)		/* Move sector window */
+			ABORT(fp->fs, FR_DISK_ERR);
+		mem_cpy(rbuff, &fp->fs->win.d8[fp->fptr % SS(fp->fs)], rcnt);	/* Pick partial sector */
+#else
+		mem_cpy(rbuff, &fp->buf.d8[fp->fptr % SS(fp->fs)], rcnt);	/* Pick partial sector */
+#endif
+	}
+
+	LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+	FIL* fp,			/* Pointer to the file object */
+	const void *buff,	/* Pointer to the data to be written */
+	UINT btw,			/* Number of bytes to write */
+	UINT* bw			/* Pointer to number of bytes written */
+)
+{
+	FRESULT res;
+	DWORD clst, sect;
+	UINT wcnt, cc;
+	const BYTE *wbuff = (const BYTE*)buff;
+	BYTE csect;
+
+
+	*bw = 0;	/* Clear write byte counter */
+
+	res = validate(fp);						/* Check validity */
+	if (res != FR_OK) LEAVE_FF(fp->fs, res);
+	if (fp->err)							/* Check error */
+		LEAVE_FF(fp->fs, (FRESULT)fp->err);
+	if (!(fp->flag & FA_WRITE))				/* Check access mode */
+		LEAVE_FF(fp->fs, FR_DENIED);
+	if (fp->fptr + btw < fp->fptr) btw = 0;	/* File size cannot reach 4GB */
+
+	for ( ;  btw;							/* Repeat until all data written */
+		wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
+		if ((fp->fptr % SS(fp->fs)) == 0) {	/* On the sector boundary? */
+			csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
+			if (!csect) {					/* On the cluster boundary? */
+				if (fp->fptr == 0) {		/* On the top of the file? */
+					clst = fp->sclust;		/* Follow from the origin */
+					if (clst == 0)			/* When no cluster is allocated, */
+						clst = create_chain(fp->fs, 0);	/* Create a new cluster chain */
+				} else {					/* Middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl)
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					else
+#endif
+						clst = create_chain(fp->fs, fp->clust);	/* Follow or stretch cluster chain on the FAT */
+				}
+				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
+				if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+				fp->clust = clst;			/* Update current cluster */
+				if (fp->sclust == 0) fp->sclust = clst;	/* Set start cluster if the first write */
+			}
+#if _FS_TINY
+			if (fp->fs->winsect == fp->dsect && sync_window(fp->fs))	/* Write-back sector cache */
+				ABORT(fp->fs, FR_DISK_ERR);
+#else
+			if (fp->flag & FA__DIRTY) {		/* Write-back sector cache */
+				if (disk_write(fp->fs->drv, fp->buf.d8, fp->dsect, 1) != RES_OK)
+					ABORT(fp->fs, FR_DISK_ERR);
+				fp->flag &= ~FA__DIRTY;
+			}
+#endif
+			sect = clust2sect(fp->fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fp->fs, FR_INT_ERR);
+			sect += csect;
+			cc = btw / SS(fp->fs);			/* When remaining bytes >= sector size, */
+			if (cc) {						/* Write maximum contiguous sectors directly */
+				if (csect + cc > fp->fs->csize)	/* Clip at cluster boundary */
+					cc = fp->fs->csize - csect;
+				if (disk_write(fp->fs->drv, wbuff, sect, cc) != RES_OK)
+					ABORT(fp->fs, FR_DISK_ERR);
+#if _FS_MINIMIZE <= 2
+#if _FS_TINY
+				if (fp->fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fp->fs->win.d8, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
+					fp->fs->wflag = 0;
+				}
+#else
+				if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fp->buf.d8, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
+					fp->flag &= ~FA__DIRTY;
+				}
+#endif
+#endif
+				wcnt = SS(fp->fs) * cc;		/* Number of bytes transferred */
+				continue;
+			}
+#if _FS_TINY
+			if (fp->fptr >= fp->fsize) {	/* Avoid silly cache filling at growing edge */
+				if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR);
+				fp->fs->winsect = sect;
+			}
+#else
+			if (fp->dsect != sect) {		/* Fill sector cache with file data */
+				if (fp->fptr < fp->fsize &&
+					disk_read(fp->fs->drv, fp->buf.d8, sect, 1) != RES_OK)
+						ABORT(fp->fs, FR_DISK_ERR);
+			}
+#endif
+			fp->dsect = sect;
+		}
+		wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
+		if (wcnt > btw) wcnt = btw;
+#if _FS_TINY
+		if (move_window(fp->fs, fp->dsect) != FR_OK)	/* Move sector window */
+			ABORT(fp->fs, FR_DISK_ERR);
+		mem_cpy(&fp->fs->win.d8[fp->fptr % SS(fp->fs)], wbuff, wcnt);	/* Fit partial sector */
+		fp->fs->wflag = 1;
+#else
+		mem_cpy(&fp->buf.d8[fp->fptr % SS(fp->fs)], wbuff, wcnt);	/* Fit partial sector */
+		fp->flag |= FA__DIRTY;
+#endif
+	}
+
+	if (fp->fptr > fp->fsize) fp->fsize = fp->fptr;	/* Update file size if needed */
+	fp->flag |= FA__WRITTEN;						/* Set file change flag */
+
+	LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File                                                  */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	DWORD tm;
+	BYTE *dir;
+
+
+	res = validate(fp);					/* Check validity of the object */
+	if (res == FR_OK) {
+		if (fp->flag & FA__WRITTEN) {	/* Has the file been written? */
+			/* Write-back dirty buffer */
+#if !_FS_TINY
+			if (fp->flag & FA__DIRTY) {
+				if (disk_write(fp->fs->drv, fp->buf.d8, fp->dsect, 1) != RES_OK)
+					LEAVE_FF(fp->fs, FR_DISK_ERR);
+				fp->flag &= ~FA__DIRTY;
+			}
+#endif
+			/* Update the directory entry */
+			res = move_window(fp->fs, fp->dir_sect);
+			if (res == FR_OK) {
+				dir = fp->dir_ptr;
+				dir[DIR_Attr] |= AM_ARC;					/* Set archive bit */
+				ST_DWORD(dir + DIR_FileSize, fp->fsize);	/* Update file size */
+				st_clust(dir, fp->sclust);					/* Update start cluster */
+				tm = GET_FATTIME();							/* Update updated time */
+				ST_DWORD(dir + DIR_WrtTime, tm);
+				ST_WORD(dir + DIR_LstAccDate, 0);
+				fp->flag &= ~FA__WRITTEN;
+				fp->fs->wflag = 1;
+				res = sync_fs(fp->fs);
+			}
+		}
+	}
+
+	LEAVE_FF(fp->fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+	FIL *fp		/* Pointer to the file object to be closed */
+)
+{
+	FRESULT res;
+
+
+#if !_FS_READONLY
+	res = f_sync(fp);					/* Flush cached data */
+	if (res == FR_OK)
+#endif
+	{
+		res = validate(fp);				/* Lock volume */
+		if (res == FR_OK) {
+#if _FS_REENTRANT
+			FATFS *fs = fp->fs;
+#endif
+#if _FS_LOCK
+			res = dec_lock(fp->lockid);	/* Decrement file open counter */
+			if (res == FR_OK)
+#endif
+				fp->fs = 0;				/* Invalidate file object */
+#if _FS_REENTRANT
+			unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+		}
+	}
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Current Directory or Current Drive, Get Current Directory      */
+/*-----------------------------------------------------------------------*/
+
+#if _FS_RPATH >= 1
+#if _VOLUMES >= 2
+FRESULT f_chdrive (
+	const TCHAR* path		/* Drive number */
+)
+{
+	int vol;
+
+
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	CurrVol = (BYTE)vol;
+
+	return FR_OK;
+}
+#endif
+
+
+FRESULT f_chdir (
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEFINE_NAMEBUF;
+
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 0);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);		/* Follow the path */
+		FREE_BUF();
+		if (res == FR_OK) {					/* Follow completed */
+			if (!dj.dir) {
+				dj.fs->cdir = dj.sclust;	/* Start directory itself */
+			} else {
+				if (dj.dir[DIR_Attr] & AM_DIR)	/* Reached to the directory */
+					dj.fs->cdir = ld_clust(dj.fs, dj.dir);
+				else
+					res = FR_NO_PATH;		/* Reached but a file */
+			}
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+	TCHAR* buff,	/* Pointer to the directory path */
+	UINT len		/* Size of path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	UINT i, n;
+	DWORD ccl;
+	TCHAR *tp;
+	FILINFO fno;
+	DEFINE_NAMEBUF;
+
+
+	*buff = 0;
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, (const TCHAR**)&buff, 0);	/* Get current volume */
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		i = len;			/* Bottom of buffer (directory stack base) */
+		dj.sclust = dj.fs->cdir;			/* Start to follow upper directory from current directory */
+		while ((ccl = dj.sclust) != 0) {	/* Repeat while current directory is a sub-directory */
+			res = dir_sdi(&dj, 1);			/* Get parent directory */
+			if (res != FR_OK) break;
+			res = dir_read(&dj, 0);
+			if (res != FR_OK) break;
+			dj.sclust = ld_clust(dj.fs, dj.dir);	/* Goto parent directory */
+			res = dir_sdi(&dj, 0);
+			if (res != FR_OK) break;
+			do {							/* Find the entry links to the child directory */
+				res = dir_read(&dj, 0);
+				if (res != FR_OK) break;
+				if (ccl == ld_clust(dj.fs, dj.dir)) break;	/* Found the entry */
+				res = dir_next(&dj, 0);	
+			} while (res == FR_OK);
+			if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+			if (res != FR_OK) break;
+#if _USE_LFN
+			fno.lfname = buff;
+			fno.lfsize = i;
+#endif
+			get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
+			tp = fno.fname;
+#if _USE_LFN
+			if (*buff) tp = buff;
+#endif
+			for (n = 0; tp[n]; n++) ;
+			if (i < n + 3) {
+				res = FR_NOT_ENOUGH_CORE; break;
+			}
+			while (n) buff[--i] = tp[--n];
+			buff[--i] = '/';
+		}
+		tp = buff;
+		if (res == FR_OK) {
+#if _VOLUMES >= 2
+			*tp++ = '0' + CurrVol;			/* Put drive number */
+			*tp++ = ':';
+#endif
+			if (i == len) {					/* Root-directory */
+				*tp++ = '/';
+			} else {						/* Sub-directroy */
+				do		/* Add stacked path str */
+					*tp++ = buff[i++];
+				while (i < len);
+			}
+		}
+		*tp = 0;
+		FREE_BUF();
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+	FIL* fp,		/* Pointer to the file object */
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	FRESULT res;
+	DWORD clst, bcs, nsect, ifptr;
+#if _USE_FASTSEEK
+	DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+#endif
+
+
+	res = validate(fp);					/* Check validity of the object */
+	if (res != FR_OK) LEAVE_FF(fp->fs, res);
+	if (fp->err)						/* Check error */
+		LEAVE_FF(fp->fs, (FRESULT)fp->err);
+
+#if _USE_FASTSEEK
+	if (fp->cltbl) {	/* Fast seek */
+		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+			tbl = fp->cltbl;
+			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+			cl = fp->sclust;			/* Top of the chain */
+			if (cl) {
+				do {
+					/* Get a fragment */
+					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
+					do {
+						pcl = cl; ncl++;
+						cl = get_fat(fp->fs, cl);
+						if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
+						if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+					} while (cl == pcl + 1);
+					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+						*tbl++ = ncl; *tbl++ = tcl;
+					}
+				} while (cl < fp->fs->n_fatent);	/* Repeat until end of chain */
+			}
+			*fp->cltbl = ulen;	/* Number of items used */
+			if (ulen <= tlen)
+				*tbl = 0;		/* Terminate table */
+			else
+				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
+
+		} else {						/* Fast seek */
+			if (ofs > fp->fsize)		/* Clip offset at the file size */
+				ofs = fp->fsize;
+			fp->fptr = ofs;				/* Set file pointer */
+			if (ofs) {
+				fp->clust = clmt_clust(fp, ofs - 1);
+				dsc = clust2sect(fp->fs, fp->clust);
+				if (!dsc) ABORT(fp->fs, FR_INT_ERR);
+				dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1);
+				if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) {	/* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+					if (fp->flag & FA__DIRTY) {		/* Write-back dirty sector cache */
+						if (disk_write(fp->fs->drv, fp->buf.d8, fp->dsect, 1) != RES_OK)
+							ABORT(fp->fs, FR_DISK_ERR);
+						fp->flag &= ~FA__DIRTY;
+					}
+#endif
+					if (disk_read(fp->fs->drv, fp->buf.d8, dsc, 1) != RES_OK)	/* Load current sector */
+						ABORT(fp->fs, FR_DISK_ERR);
+#endif
+					fp->dsect = dsc;
+				}
+			}
+		}
+	} else
+#endif
+
+	/* Normal Seek */
+	{
+		if (ofs > fp->fsize					/* In read-only mode, clip offset with the file size */
+#if !_FS_READONLY
+			 && !(fp->flag & FA_WRITE)
+#endif
+			) ofs = fp->fsize;
+
+		ifptr = fp->fptr;
+		fp->fptr = nsect = 0;
+		if (ofs) {
+			bcs = (DWORD)fp->fs->csize * SS(fp->fs);	/* Cluster size (byte) */
+			if (ifptr > 0 &&
+				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+				fp->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+				ofs -= fp->fptr;
+				clst = fp->clust;
+			} else {									/* When seek to back cluster, */
+				clst = fp->sclust;						/* start from the first cluster */
+#if !_FS_READONLY
+				if (clst == 0) {						/* If no cluster chain, create a new chain */
+					clst = create_chain(fp->fs, 0);
+					if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+					if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+					fp->sclust = clst;
+				}
+#endif
+				fp->clust = clst;
+			}
+			if (clst != 0) {
+				while (ofs > bcs) {						/* Cluster following loop */
+#if !_FS_READONLY
+					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
+						clst = create_chain(fp->fs, clst);	/* Force stretch if in write mode */
+						if (clst == 0) {				/* When disk gets full, clip file size */
+							ofs = bcs; break;
+						}
+					} else
+#endif
+						clst = get_fat(fp->fs, clst);	/* Follow cluster chain if not in write mode */
+					if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+					if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
+					fp->clust = clst;
+					fp->fptr += bcs;
+					ofs -= bcs;
+				}
+				fp->fptr += ofs;
+				if (ofs % SS(fp->fs)) {
+					nsect = clust2sect(fp->fs, clst);	/* Current sector */
+					if (!nsect) ABORT(fp->fs, FR_INT_ERR);
+					nsect += ofs / SS(fp->fs);
+				}
+			}
+		}
+		if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) {	/* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+			if (fp->flag & FA__DIRTY) {			/* Write-back dirty sector cache */
+				if (disk_write(fp->fs->drv, fp->buf.d8, fp->dsect, 1) != RES_OK)
+					ABORT(fp->fs, FR_DISK_ERR);
+				fp->flag &= ~FA__DIRTY;
+			}
+#endif
+			if (disk_read(fp->fs->drv, fp->buf.d8, nsect, 1) != RES_OK)	/* Fill sector cache */
+				ABORT(fp->fs, FR_DISK_ERR);
+#endif
+			fp->dsect = nsect;
+		}
+#if !_FS_READONLY
+		if (fp->fptr > fp->fsize) {			/* Set file change flag if the file size is extended */
+			fp->fsize = fp->fptr;
+			fp->flag |= FA__WRITTEN;
+		}
+#endif
+	}
+
+	LEAVE_FF(fp->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+	DIR* dp,			/* Pointer to directory object to create */
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS* fs;
+	DEFINE_NAMEBUF;
+
+
+	if (!dp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive number */
+	res = find_volume(&fs, &path, 0);
+	if (res == FR_OK) {
+		dp->fs = fs;
+		INIT_BUF(*dp);
+		res = follow_path(dp, path);			/* Follow the path to the directory */
+		FREE_BUF();
+		if (res == FR_OK) {						/* Follow completed */
+			if (dp->dir) {						/* It is not the origin directory itself */
+				if (dp->dir[DIR_Attr] & AM_DIR)	/* The object is a sub directory */
+					dp->sclust = ld_clust(fs, dp->dir);
+				else							/* The object is a file */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK) {
+				dp->id = fs->id;
+				res = dir_sdi(dp, 0);			/* Rewind directory */
+#if _FS_LOCK
+				if (res == FR_OK) {
+					if (dp->sclust) {
+						dp->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+						if (!dp->lockid)
+							res = FR_TOO_MANY_OPEN_FILES;
+					} else {
+						dp->lockid = 0;	/* Root directory need not to be locked */
+					}
+				}
+#endif
+			}
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+	if (res != FR_OK) dp->fs = 0;		/* Invalidate the directory object if function faild */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close Directory                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_closedir (
+	DIR *dp		/* Pointer to the directory object to be closed */
+)
+{
+	FRESULT res;
+
+
+	res = validate(dp);
+	if (res == FR_OK) {
+#if _FS_REENTRANT
+		FATFS *fs = dp->fs;
+#endif
+#if _FS_LOCK
+		if (dp->lockid)				/* Decrement sub-directory open counter */
+			res = dec_lock(dp->lockid);
+		if (res == FR_OK)
+#endif
+			dp->fs = 0;				/* Invalidate directory object */
+#if _FS_REENTRANT
+		unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+	}
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entries in Sequence                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+	DIR* dp,			/* Pointer to the open directory object */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DEFINE_NAMEBUF;
+
+
+	res = validate(dp);						/* Check validity of the object */
+	if (res == FR_OK) {
+		if (!fno) {
+			res = dir_sdi(dp, 0);			/* Rewind the directory object */
+		} else {
+			INIT_BUF(*dp);
+			res = dir_read(dp, 0);			/* Read an item */
+			if (res == FR_NO_FILE) {		/* Reached end of directory */
+				dp->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dp, fno);		/* Get the object information */
+				res = dir_next(dp, 0);		/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dp->sect = 0;
+					res = FR_OK;
+				}
+			}
+			FREE_BUF();
+		}
+	}
+
+	LEAVE_FF(dp->fs, res);
+}
+
+
+
+#if _USE_FIND
+/*-----------------------------------------------------------------------*/
+/* Find next file                                                        */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findnext (
+	DIR* dp,		/* Pointer to the open directory object */
+	FILINFO* fno	/* Pointer to the file information structure */
+)
+{
+	FRESULT res;
+
+
+	for (;;) {
+		res = f_readdir(dp, fno);		/* Get a directory item */
+		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory */
+#if _USE_LFN
+		if (fno->lfname && pattern_matching(dp->pat, fno->lfname, 0, 0)) break;	/* Test for LFN if exist */
+#endif
+		if (pattern_matching(dp->pat, fno->fname, 0, 0)) break;	/* Test for SFN */
+	}
+	return res;
+
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find first file                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findfirst (
+	DIR* dp,				/* Pointer to the blank directory object */
+	FILINFO* fno,			/* Pointer to the file information structure */
+	const TCHAR* path,		/* Pointer to the directory to open */
+	const TCHAR* pattern	/* Pointer to the matching pattern */
+)
+{
+	FRESULT res;
+
+
+	dp->pat = pattern;		/* Save pointer to pattern string */
+	res = f_opendir(dp, path);		/* Open the target directory */
+	if (res == FR_OK)
+		res = f_findnext(dp, fno);	/* Find the first item */
+	return res;
+}
+
+#endif	/* _USE_FIND */
+
+
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+	const TCHAR* path,	/* Pointer to the file path */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEFINE_NAMEBUF;
+
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 0);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK) {				/* Follow completed */
+			if (dj.dir) {		/* Found an object */
+				if (fno) get_fileinfo(&dj, fno);
+			} else {			/* It is root directory */
+				res = FR_INVALID_NAME;
+			}
+		}
+		FREE_BUF();
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	DWORD* nclst,		/* Pointer to a variable to return number of free clusters */
+	FATFS** fatfs		/* Pointer to return pointer to corresponding file system object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD n, clst, sect, stat;
+	UINT i;
+	BYTE fat, *p;
+
+
+	/* Get logical drive number */
+	res = find_volume(fatfs, &path, 0);
+	fs = *fatfs;
+	if (res == FR_OK) {
+		/* If free_clust is valid, return it without full cluster scan */
+		if (fs->free_clust <= fs->n_fatent - 2) {
+			*nclst = fs->free_clust;
+		} else {
+			/* Get number of free clusters */
+			fat = fs->fs_type;
+			n = 0;
+			if (fat == FS_FAT12) {
+				clst = 2;
+				do {
+					stat = get_fat(fs, clst);
+					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+					if (stat == 1) { res = FR_INT_ERR; break; }
+					if (stat == 0) n++;
+				} while (++clst < fs->n_fatent);
+			} else {
+				clst = fs->n_fatent;
+				sect = fs->fatbase;
+				i = 0; p = 0;
+				do {
+					if (!i) {
+						res = move_window(fs, sect++);
+						if (res != FR_OK) break;
+						p = fs->win.d8;
+						i = SS(fs);
+					}
+					if (fat == FS_FAT16) {
+						if (LD_WORD(p) == 0) n++;
+						p += 2; i -= 2;
+					} else {
+						if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++;
+						p += 4; i -= 4;
+					}
+				} while (--clst);
+			}
+			fs->free_clust = n;
+			fs->fsi_flag |= 1;
+			*nclst = n;
+		}
+	}
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File                                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	DWORD ncl;
+
+
+	res = validate(fp);						/* Check validity of the object */
+	if (res == FR_OK) {
+		if (fp->err) {						/* Check error */
+			res = (FRESULT)fp->err;
+		} else {
+			if (!(fp->flag & FA_WRITE))		/* Check access mode */
+				res = FR_DENIED;
+		}
+	}
+	if (res == FR_OK) {
+		if (fp->fsize > fp->fptr) {
+			fp->fsize = fp->fptr;	/* Set file size to current R/W point */
+			fp->flag |= FA__WRITTEN;
+			if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+				res = remove_chain(fp->fs, fp->sclust);
+				fp->sclust = 0;
+			} else {				/* When truncate a part of the file, remove remaining clusters */
+				ncl = get_fat(fp->fs, fp->clust);
+				res = FR_OK;
+				if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+				if (ncl == 1) res = FR_INT_ERR;
+				if (res == FR_OK && ncl < fp->fs->n_fatent) {
+					res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF);
+					if (res == FR_OK) res = remove_chain(fp->fs, ncl);
+				}
+			}
+#if !_FS_TINY
+			if (res == FR_OK && (fp->flag & FA__DIRTY)) {
+				if (disk_write(fp->fs->drv, fp->buf.d8, fp->dsect, 1) != RES_OK)
+					res = FR_DISK_ERR;
+				else
+					fp->flag &= ~FA__DIRTY;
+			}
+#endif
+		}
+		if (res != FR_OK) fp->err = (FRESULT)res;
+	}
+
+	LEAVE_FF(fp->fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File or Directory                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+	const TCHAR* path		/* Pointer to the file or directory path */
+)
+{
+	FRESULT res;
+	DIR dj, sdj;
+	BYTE *dir;
+	DWORD dclst = 0;
+	DEFINE_NAMEBUF;
+
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 1);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+#if _FS_LOCK
+		if (res == FR_OK) res = chk_lock(&dj, 2);	/* Cannot remove open object */
+#endif
+		if (res == FR_OK) {					/* The object is accessible */
+			dir = dj.dir;
+			if (!dir) {
+				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+			} else {
+				if (dir[DIR_Attr] & AM_RDO)
+					res = FR_DENIED;		/* Cannot remove R/O object */
+			}
+			if (res == FR_OK) {
+				dclst = ld_clust(dj.fs, dir);
+				if (dclst && (dir[DIR_Attr] & AM_DIR)) {	/* Is it a sub-directory ? */
+#if _FS_RPATH
+					if (dclst == dj.fs->cdir) {		 		/* Is it the current directory? */
+						res = FR_DENIED;
+					} else
+#endif
+					{
+						mem_cpy(&sdj, &dj, sizeof (DIR));	/* Open the sub-directory */
+						sdj.sclust = dclst;
+						res = dir_sdi(&sdj, 2);
+						if (res == FR_OK) {
+							res = dir_read(&sdj, 0);			/* Read an item (excluding dot entries) */
+							if (res == FR_OK) res = FR_DENIED;	/* Not empty? (cannot remove) */
+							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? (can remove) */
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&dj);		/* Remove the directory entry */
+				if (res == FR_OK && dclst)	/* Remove the cluster chain if exist */
+					res = remove_chain(dj.fs, dclst);
+				if (res == FR_OK) res = sync_fs(dj.fs);
+			}
+		}
+		FREE_BUF();
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory                                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+	const TCHAR* path		/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE *dir, n;
+	DWORD dsc, dcl, pcl, tm = GET_FATTIME();
+	DEFINE_NAMEBUF;
+
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 1);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);			/* Follow the file path */
+		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;
+		if (res == FR_NO_FILE) {				/* Can create a new directory */
+			dcl = create_chain(dj.fs, 0);		/* Allocate a cluster for the new directory table */
+			res = FR_OK;
+			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster */
+			if (dcl == 1) res = FR_INT_ERR;
+			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (res == FR_OK)					/* Flush FAT */
+				res = sync_window(dj.fs);
+			if (res == FR_OK) {					/* Initialize the new directory table */
+				dsc = clust2sect(dj.fs, dcl);
+				dir = dj.fs->win.d8;
+				mem_set(dir, 0, SS(dj.fs));
+				mem_set(dir + DIR_Name, ' ', 11);	/* Create "." entry */
+				dir[DIR_Name] = '.';
+				dir[DIR_Attr] = AM_DIR;
+				ST_DWORD(dir + DIR_WrtTime, tm);
+				st_clust(dir, dcl);
+				mem_cpy(dir + SZ_DIRE, dir, SZ_DIRE); 	/* Create ".." entry */
+				dir[SZ_DIRE + 1] = '.'; pcl = dj.sclust;
+				if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
+					pcl = 0;
+				st_clust(dir + SZ_DIRE, pcl);
+				for (n = dj.fs->csize; n; n--) {	/* Write dot entries and clear following sectors */
+					dj.fs->winsect = dsc++;
+					dj.fs->wflag = 1;
+					res = sync_window(dj.fs);
+					if (res != FR_OK) break;
+					mem_set(dir, 0, SS(dj.fs));
+				}
+			}
+			if (res == FR_OK) res = dir_register(&dj);	/* Register the object to the directoy */
+			if (res != FR_OK) {
+				remove_chain(dj.fs, dcl);			/* Could not register, remove cluster chain */
+			} else {
+				dir = dj.dir;
+				dir[DIR_Attr] = AM_DIR;				/* Attribute */
+				ST_DWORD(dir + DIR_WrtTime, tm);	/* Created time */
+				st_clust(dir, dcl);					/* Table start cluster */
+				dj.fs->wflag = 1;
+				res = sync_fs(dj.fs);
+			}
+		}
+		FREE_BUF();
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Attribute                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+	const TCHAR* path,	/* Pointer to the file path */
+	BYTE attr,			/* Attribute bits */
+	BYTE mask			/* Attribute mask to change */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE *dir;
+	DEFINE_NAMEBUF;
+
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 1);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		FREE_BUF();
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;
+		if (res == FR_OK) {
+			dir = dj.dir;
+			if (!dir) {						/* Is it a root directory? */
+				res = FR_INVALID_NAME;
+			} else {						/* File or sub directory */
+				mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
+				dir[DIR_Attr] = (attr & mask) | (dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				dj.fs->wflag = 1;
+				res = sync_fs(dj.fs);
+			}
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename File/Directory                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+	const TCHAR* path_old,	/* Pointer to the object to be renamed */
+	const TCHAR* path_new	/* Pointer to the new name */
+)
+{
+	FRESULT res;
+	DIR djo, djn;
+	BYTE buf[21], *dir;
+	DWORD dw;
+	DEFINE_NAMEBUF;
+
+
+	/* Get logical drive number of the source object */
+	res = find_volume(&djo.fs, &path_old, 1);
+	if (res == FR_OK) {
+		djn.fs = djo.fs;
+		INIT_BUF(djo);
+		res = follow_path(&djo, path_old);		/* Check old object */
+		if (_FS_RPATH && res == FR_OK && (djo.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;
+#if _FS_LOCK
+		if (res == FR_OK) res = chk_lock(&djo, 2);
+#endif
+		if (res == FR_OK) {						/* Old object is found */
+			if (!djo.dir) {						/* Is root dir? */
+				res = FR_NO_FILE;
+			} else {
+				mem_cpy(buf, djo.dir + DIR_Attr, 21);	/* Save information about object except name */
+				mem_cpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+				if (get_ldnumber(&path_new) >= 0)		/* Snip drive number off and ignore it */
+					res = follow_path(&djn, path_new);	/* and make sure if new object name is not conflicting */
+				else
+					res = FR_INVALID_DRIVE;
+				if (res == FR_OK) res = FR_EXIST;		/* The new object name is already existing */
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+/* Start of critical section where any interruption can cause a cross-link */
+						dir = djn.dir;					/* Copy information about object except name */
+						mem_cpy(dir + 13, buf + 2, 19);
+						dir[DIR_Attr] = buf[0] | AM_ARC;
+						djo.fs->wflag = 1;
+						if ((dir[DIR_Attr] & AM_DIR) && djo.sclust != djn.sclust) {	/* Update .. entry in the sub-directory if needed */
+							dw = clust2sect(djo.fs, ld_clust(djo.fs, dir));
+							if (!dw) {
+								res = FR_INT_ERR;
+							} else {
+								res = move_window(djo.fs, dw);
+								dir = djo.fs->win.d8 + SZ_DIRE * 1;	/* Ptr to .. entry */
+								if (res == FR_OK && dir[1] == '.') {
+									st_clust(dir, djn.sclust);
+									djo.fs->wflag = 1;
+								}
+							}
+						}
+						if (res == FR_OK) {
+							res = dir_remove(&djo);		/* Remove old entry */
+							if (res == FR_OK)
+								res = sync_fs(djo.fs);
+						}
+/* End of critical section */
+					}
+				}
+			}
+		}
+		FREE_BUF();
+	}
+
+	LEAVE_FF(djo.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+	const TCHAR* path,	/* Pointer to the file/directory name */
+	const FILINFO* fno	/* Pointer to the time stamp to be set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE *dir;
+	DEFINE_NAMEBUF;
+
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 1);
+	if (res == FR_OK) {
+		INIT_BUF(dj);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		FREE_BUF();
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+			res = FR_INVALID_NAME;
+		if (res == FR_OK) {
+			dir = dj.dir;
+			if (!dir) {					/* Root directory */
+				res = FR_INVALID_NAME;
+			} else {					/* File or sub-directory */
+				ST_WORD(dir + DIR_WrtTime, fno->ftime);
+				ST_WORD(dir + DIR_WrtDate, fno->fdate);
+				dj.fs->wflag = 1;
+				res = sync_fs(dj.fs);
+			}
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+
+
+
+#if _USE_LABEL
+/*-----------------------------------------------------------------------*/
+/* Get volume label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getlabel (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	TCHAR* label,		/* Pointer to a buffer to return the volume label */
+	DWORD* vsn			/* Pointer to a variable to return the volume serial number */
+)
+{
+	FRESULT res;
+	DIR dj;
+	UINT i, j;
+#if _USE_LFN && _LFN_UNICODE
+	WCHAR w;
+#endif
+
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &path, 0);
+
+	/* Get volume label */
+	if (res == FR_OK && label) {
+		dj.sclust = 0;					/* Open root directory */
+		res = dir_sdi(&dj, 0);
+		if (res == FR_OK) {
+			res = dir_read(&dj, 1);		/* Get an entry with AM_VOL */
+			if (res == FR_OK) {			/* A volume label is exist */
+#if _USE_LFN && _LFN_UNICODE
+				i = j = 0;
+				do {
+					w = (i < 11) ? dj.dir[i++] : ' ';
+					if (IsDBCS1(w) && i < 11 && IsDBCS2(dj.dir[i]))
+						w = w << 8 | dj.dir[i++];
+					label[j++] = ff_convert(w, 1);	/* OEM -> Unicode */
+				} while (j < 11);
+#else
+				mem_cpy(label, dj.dir, 11);
+#endif
+				j = 11;
+				do {
+					label[j] = 0;
+					if (!j) break;
+				} while (label[--j] == ' ');
+			}
+			if (res == FR_NO_FILE) {	/* No label, return nul string */
+				label[0] = 0;
+				res = FR_OK;
+			}
+		}
+	}
+
+	/* Get volume serial number */
+	if (res == FR_OK && vsn) {
+		res = move_window(dj.fs, dj.fs->volbase);
+		if (res == FR_OK) {
+			i = dj.fs->fs_type == FS_FAT32 ? BS_VolID32 : BS_VolID;
+			*vsn = LD_DWORD(&dj.fs->win.d8[i]);
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Set volume label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setlabel (
+	const TCHAR* label	/* Pointer to the volume label to set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE vn[11];
+	UINT i, j, sl;
+	WCHAR w;
+	DWORD tm;
+
+
+	/* Get logical drive number */
+	res = find_volume(&dj.fs, &label, 1);
+	if (res) LEAVE_FF(dj.fs, res);
+
+	/* Create a volume label in directory form */
+	vn[0] = 0;
+	for (sl = 0; label[sl]; sl++) ;				/* Get name length */
+	for ( ; sl && label[sl - 1] == ' '; sl--) ;	/* Remove trailing spaces */
+	if (sl) {	/* Create volume label in directory form */
+		i = j = 0;
+		do {
+#if _USE_LFN && _LFN_UNICODE
+			w = ff_convert(ff_wtoupper(label[i++]), 0);
+#else
+			w = (BYTE)label[i++];
+			if (IsDBCS1(w))
+				w = (j < 10 && i < sl && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+#if _USE_LFN
+			w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0);
+#else
+			if (IsLower(w)) w -= 0x20;			/* To upper ASCII characters */
+#ifdef _EXCVT
+			if (w >= 0x80) w = ExCvt[w - 0x80];	/* To upper extended characters (SBCS cfg) */
+#else
+			if (!_DF1S && w >= 0x80) w = 0;		/* Reject extended characters (ASCII cfg) */
+#endif
+#endif
+#endif
+			if (!w || chk_chr("\"*+,.:;<=>\?[]|\x7F", w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) /* Reject invalid characters for volume label */
+				LEAVE_FF(dj.fs, FR_INVALID_NAME);
+			if (w >= 0x100) vn[j++] = (BYTE)(w >> 8);
+			vn[j++] = (BYTE)w;
+		} while (i < sl);
+		while (j < 11) vn[j++] = ' ';	/* Fill remaining name field */
+		if (vn[0] == DDEM) LEAVE_FF(dj.fs, FR_INVALID_NAME);	/* Reject illegal name (heading DDEM) */
+	}
+
+	/* Set volume label */
+	dj.sclust = 0;					/* Open root directory */
+	res = dir_sdi(&dj, 0);
+	if (res == FR_OK) {
+		res = dir_read(&dj, 1);		/* Get an entry with AM_VOL */
+		if (res == FR_OK) {			/* A volume label is found */
+			if (vn[0]) {
+				mem_cpy(dj.dir, vn, 11);	/* Change the volume label name */
+				tm = GET_FATTIME();
+				ST_DWORD(dj.dir + DIR_WrtTime, tm);
+			} else {
+				dj.dir[0] = DDEM;			/* Remove the volume label */
+			}
+			dj.fs->wflag = 1;
+			res = sync_fs(dj.fs);
+		} else {					/* No volume label is found or error */
+			if (res == FR_NO_FILE) {
+				res = FR_OK;
+				if (vn[0]) {				/* Create volume label as new */
+					res = dir_alloc(&dj, 1);	/* Allocate an entry for volume label */
+					if (res == FR_OK) {
+						mem_set(dj.dir, 0, SZ_DIRE);	/* Set volume label */
+						mem_cpy(dj.dir, vn, 11);
+						dj.dir[DIR_Attr] = AM_VOL;
+						tm = GET_FATTIME();
+						ST_DWORD(dj.dir + DIR_WrtTime, tm);
+						dj.fs->wflag = 1;
+						res = sync_fs(dj.fs);
+					}
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(dj.fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_LABEL */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly (available on only tiny cfg)      */
+/*-----------------------------------------------------------------------*/
+#if _USE_FORWARD && _FS_TINY
+
+FRESULT f_forward (
+	FIL* fp, 						/* Pointer to the file object */
+	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
+	UINT btf,						/* Number of bytes to forward */
+	UINT* bf						/* Pointer to number of bytes forwarded */
+)
+{
+	FRESULT res;
+	DWORD remain, clst, sect;
+	UINT rcnt;
+	BYTE csect;
+
+
+	*bf = 0;	/* Clear transfer byte counter */
+
+	res = validate(fp);								/* Check validity of the object */
+	if (res != FR_OK) LEAVE_FF(fp->fs, res);
+	if (fp->err)									/* Check error */
+		LEAVE_FF(fp->fs, (FRESULT)fp->err);
+	if (!(fp->flag & FA_READ))						/* Check access mode */
+		LEAVE_FF(fp->fs, FR_DENIED);
+
+	remain = fp->fsize - fp->fptr;
+	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
+
+	for ( ;  btf && (*func)(0, 0);					/* Repeat until all data transferred or stream becomes busy */
+		fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
+		csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
+		if ((fp->fptr % SS(fp->fs)) == 0) {			/* On the sector boundary? */
+			if (!csect) {							/* On the cluster boundary? */
+				clst = (fp->fptr == 0) ?			/* On the top of the file? */
+					fp->sclust : get_fat(fp->fs, fp->clust);
+				if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+				fp->clust = clst;					/* Update current cluster */
+			}
+		}
+		sect = clust2sect(fp->fs, fp->clust);		/* Get current data sector */
+		if (!sect) ABORT(fp->fs, FR_INT_ERR);
+		sect += csect;
+		if (move_window(fp->fs, sect) != FR_OK)		/* Move sector window */
+			ABORT(fp->fs, FR_DISK_ERR);
+		fp->dsect = sect;
+		rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs));	/* Forward data from sector window */
+		if (rcnt > btf) rcnt = btf;
+		rcnt = (*func)(&fp->fs->win.d8[(WORD)fp->fptr % SS(fp->fs)], rcnt);
+		if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
+	}
+
+	LEAVE_FF(fp->fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create file system on the logical drive                               */
+/*-----------------------------------------------------------------------*/
+#define N_ROOTDIR	512		/* Number of root directory entries for FAT12/16 */
+#define N_FATS		1		/* Number of FATs (1 or 2) */
+
+
+FRESULT f_mkfs (
+	const TCHAR* path,	/* Logical drive number */
+	BYTE sfd,			/* Partitioning rule 0:FDISK, 1:SFD */
+	UINT au				/* Size of allocation unit in unit of byte or sector */
+)
+{
+	static const WORD vst[] = { 1024,   512,  256,  128,   64,    32,   16,    8,    4,    2,   0};
+	static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
+	int vol;
+	BYTE fmt, md, sys, *tbl, pdrv, part;
+	DWORD n_clst, vs, n, wsect;
+	UINT i;
+	DWORD b_vol, b_fat, b_dir, b_data;	/* LBA */
+	DWORD n_vol, n_rsv, n_fat, n_dir;	/* Size */
+	FATFS *fs;
+	DSTATUS stat;
+#if _USE_TRIM
+	DWORD eb[2];
+#endif
+
+
+	/* Check mounted drive and clear work area */
+	if (sfd > 1) return FR_INVALID_PARAMETER;
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	fs = FatFs[vol];
+	if (!fs) return FR_NOT_ENABLED;
+	fs->fs_type = 0;
+	pdrv = LD2PD(vol);	/* Physical drive */
+	part = LD2PT(vol);	/* Partition (0:auto detect, 1-4:get from partition table)*/
+
+	/* Get disk statics */
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+#if _MAX_SS != _MIN_SS		/* Get disk sector size */
+	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS || SS(fs) < _MIN_SS)
+		return FR_DISK_ERR;
+#endif
+	if (_MULTI_PARTITION && part) {
+		/* Get partition information from partition table in the MBR */
+		if (disk_read(pdrv, fs->win.d8, 0, 1) != RES_OK) return FR_DISK_ERR;
+		if (LD_WORD(fs->win.d8 + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;
+		tbl = &fs->win.d8[MBR_Table + (part - 1) * SZ_PTE];
+		if (!tbl[4]) return FR_MKFS_ABORTED;	/* No partition? */
+		b_vol = LD_DWORD(tbl + 8);	/* Volume start sector */
+		n_vol = LD_DWORD(tbl + 12);	/* Volume size */
+	} else {
+		/* Create a partition in this function */
+		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
+			return FR_DISK_ERR;
+		b_vol = (sfd) ? 0 : 63;		/* Volume start sector */
+		n_vol -= b_vol;				/* Volume size */
+	}
+
+	if (au & (au - 1)) au = 0;
+	if (!au) {						/* AU auto selection */
+		vs = n_vol / (2000 / (SS(fs) / 512));
+		for (i = 0; vs < vst[i]; i++) ;
+		au = cst[i];
+	}
+	if (au >= _MIN_SS) au /= SS(fs);	/* Number of sectors per cluster */
+	if (!au) au = 1;
+	if (au > 128) au = 128;
+
+	/* Pre-compute number of clusters and FAT sub-type */
+	n_clst = n_vol / au;
+	fmt = FS_FAT12;
+	if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
+	if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
+
+	/* Determine offset and size of FAT structure */
+	if (fmt == FS_FAT32) {
+		n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
+		n_rsv = 32;
+		n_dir = 0;
+	} else {
+		n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
+		n_fat = (n_fat + SS(fs) - 1) / SS(fs);
+		n_rsv = 1;
+		n_dir = (DWORD)N_ROOTDIR * SZ_DIRE / SS(fs);
+	}
+	b_fat = b_vol + n_rsv;				/* FAT area start sector */
+	b_dir = b_fat + n_fat * N_FATS;		/* Directory area start sector */
+	b_data = b_dir + n_dir;				/* Data area start sector */
+	if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED;	/* Too small volume */
+
+	/* Align data start sector to erase block boundary (for flash memory media) */
+	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
+	n = (b_data + n - 1) & ~(n - 1);	/* Next nearest erase block from current data start */
+	n = (n - b_data) / N_FATS;
+	if (fmt == FS_FAT32) {		/* FAT32: Move FAT offset */
+		n_rsv += n;
+		b_fat += n;
+	} else {					/* FAT12/16: Expand FAT size */
+		n_fat += n;
+	}
+
+	/* Determine number of clusters and final check of validity of the FAT sub-type */
+	n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
+	if (   (fmt == FS_FAT16 && n_clst < MIN_FAT16)
+		|| (fmt == FS_FAT32 && n_clst < MIN_FAT32))
+		return FR_MKFS_ABORTED;
+
+	/* Determine system ID in the partition table */
+	if (fmt == FS_FAT32) {
+		sys = 0x0C;		/* FAT32X */
+	} else {
+		if (fmt == FS_FAT12 && n_vol < 0x10000) {
+			sys = 0x01;	/* FAT12(<65536) */
+		} else {
+			sys = (n_vol < 0x10000) ? 0x04 : 0x06;	/* FAT16(<65536) : FAT12/16(>=65536) */
+		}
+	}
+
+	if (_MULTI_PARTITION && part) {
+		/* Update system ID in the partition table */
+		tbl = &fs->win.d8[MBR_Table + (part - 1) * SZ_PTE];
+		tbl[4] = sys;
+		if (disk_write(pdrv, fs->win.d8, 0, 1) != RES_OK)	/* Write it to teh MBR */
+			return FR_DISK_ERR;
+		md = 0xF8;
+	} else {
+		if (sfd) {	/* No partition table (SFD) */
+			md = 0xF0;
+		} else {	/* Create partition table (FDISK) */
+			mem_set(fs->win.d8, 0, SS(fs));
+			tbl = fs->win.d8 + MBR_Table;	/* Create partition table for single partition in the drive */
+			tbl[1] = 1;						/* Partition start head */
+			tbl[2] = 1;						/* Partition start sector */
+			tbl[3] = 0;						/* Partition start cylinder */
+			tbl[4] = sys;					/* System type */
+			tbl[5] = 254;					/* Partition end head */
+			n = (b_vol + n_vol) / 63 / 255;
+			tbl[6] = (BYTE)(n >> 2 | 63);	/* Partition end sector */
+			tbl[7] = (BYTE)n;				/* End cylinder */
+			ST_DWORD(tbl + 8, 63);			/* Partition start in LBA */
+			ST_DWORD(tbl + 12, n_vol);		/* Partition size in LBA */
+			ST_WORD(fs->win.d8 + BS_55AA, 0xAA55);	/* MBR signature */
+			if (disk_write(pdrv, fs->win.d8, 0, 1) != RES_OK)	/* Write it to the MBR */
+				return FR_DISK_ERR;
+			md = 0xF8;
+		}
+	}
+
+	/* Create BPB in the VBR */
+	tbl = fs->win.d8;							/* Clear sector */
+	mem_set(tbl, 0, SS(fs));
+	mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */
+	i = SS(fs);								/* Sector size */
+	ST_WORD(tbl + BPB_BytsPerSec, i);
+	tbl[BPB_SecPerClus] = (BYTE)au;			/* Sectors per cluster */
+	ST_WORD(tbl + BPB_RsvdSecCnt, n_rsv);	/* Reserved sectors */
+	tbl[BPB_NumFATs] = N_FATS;				/* Number of FATs */
+	i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR;	/* Number of root directory entries */
+	ST_WORD(tbl + BPB_RootEntCnt, i);
+	if (n_vol < 0x10000) {					/* Number of total sectors */
+		ST_WORD(tbl + BPB_TotSec16, n_vol);
+	} else {
+		ST_DWORD(tbl + BPB_TotSec32, n_vol);
+	}
+	tbl[BPB_Media] = md;					/* Media descriptor */
+	ST_WORD(tbl + BPB_SecPerTrk, 63);		/* Number of sectors per track */
+	ST_WORD(tbl + BPB_NumHeads, 255);		/* Number of heads */
+	ST_DWORD(tbl + BPB_HiddSec, b_vol);		/* Hidden sectors */
+	n = GET_FATTIME();						/* Use current time as VSN */
+	if (fmt == FS_FAT32) {
+		ST_DWORD(tbl + BS_VolID32, n);		/* VSN */
+		ST_DWORD(tbl + BPB_FATSz32, n_fat);	/* Number of sectors per FAT */
+		ST_DWORD(tbl + BPB_RootClus, 2);	/* Root directory start cluster (2) */
+		ST_WORD(tbl + BPB_FSInfo, 1);		/* FSINFO record offset (VBR + 1) */
+		ST_WORD(tbl + BPB_BkBootSec, 6);	/* Backup boot record offset (VBR + 6) */
+		tbl[BS_DrvNum32] = 0x80;			/* Drive number */
+		tbl[BS_BootSig32] = 0x29;			/* Extended boot signature */
+		mem_cpy(tbl + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+	} else {
+		ST_DWORD(tbl + BS_VolID, n);		/* VSN */
+		ST_WORD(tbl + BPB_FATSz16, n_fat);	/* Number of sectors per FAT */
+		tbl[BS_DrvNum] = 0x80;				/* Drive number */
+		tbl[BS_BootSig] = 0x29;				/* Extended boot signature */
+		mem_cpy(tbl + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+	}
+	ST_WORD(tbl + BS_55AA, 0xAA55);			/* Signature (Offset is fixed here regardless of sector size) */
+	if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK)	/* Write it to the VBR sector */
+		return FR_DISK_ERR;
+	if (fmt == FS_FAT32)					/* Write backup VBR if needed (VBR + 6) */
+		disk_write(pdrv, tbl, b_vol + 6, 1);
+
+	/* Initialize FAT area */
+	wsect = b_fat;
+	for (i = 0; i < N_FATS; i++) {		/* Initialize each FAT copy */
+		mem_set(tbl, 0, SS(fs));			/* 1st sector of the FAT  */
+		n = md;								/* Media descriptor byte */
+		if (fmt != FS_FAT32) {
+			n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
+			ST_DWORD(tbl + 0, n);			/* Reserve cluster #0-1 (FAT12/16) */
+		} else {
+			n |= 0xFFFFFF00;
+			ST_DWORD(tbl + 0, n);			/* Reserve cluster #0-1 (FAT32) */
+			ST_DWORD(tbl + 4, 0xFFFFFFFF);
+			ST_DWORD(tbl + 8, 0x0FFFFFFF);	/* Reserve cluster #2 for root directory */
+		}
+		if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+			return FR_DISK_ERR;
+		mem_set(tbl, 0, SS(fs));			/* Fill following FAT entries with zero */
+		for (n = 1; n < n_fat; n++) {		/* This loop may take a time on FAT32 volume due to many single sector writes */
+			if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+				return FR_DISK_ERR;
+		}
+	}
+
+	/* Initialize root directory */
+	i = (fmt == FS_FAT32) ? au : (UINT)n_dir;
+	do {
+		if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+			return FR_DISK_ERR;
+	} while (--i);
+
+#if _USE_TRIM	/* Erase data area if needed */
+	{
+		eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
+		disk_ioctl(pdrv, CTRL_TRIM, eb);
+	}
+#endif
+
+	/* Create FSINFO if needed */
+	if (fmt == FS_FAT32) {
+		ST_DWORD(tbl + FSI_LeadSig, 0x41615252);
+		ST_DWORD(tbl + FSI_StrucSig, 0x61417272);
+		ST_DWORD(tbl + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+		ST_DWORD(tbl + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+		ST_WORD(tbl + BS_55AA, 0xAA55);
+		disk_write(pdrv, tbl, b_vol + 1, 1);	/* Write original (VBR + 1) */
+		disk_write(pdrv, tbl, b_vol + 7, 1);	/* Write backup (VBR + 7) */
+	}
+
+	return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR;
+}
+
+
+
+#if _MULTI_PARTITION
+/*-----------------------------------------------------------------------*/
+/* Create partition table on the physical drive                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+	BYTE pdrv,			/* Physical drive number */
+	const DWORD szt[],	/* Pointer to the size table for each partitions */
+	void* work			/* Pointer to the working buffer */
+)
+{
+	UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+	BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+	DSTATUS stat;
+	DWORD sz_disk, sz_part, s_part;
+
+
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+	if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+	/* Determine CHS in the table regardless of the drive geometry */
+	for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+	if (n == 256) n--;
+	e_hd = n - 1;
+	sz_cyl = 63 * n;
+	tot_cyl = sz_disk / sz_cyl;
+
+	/* Create partition table */
+	mem_set(buf, 0, _MAX_SS);
+	p = buf + MBR_Table; b_cyl = 0;
+	for (i = 0; i < 4; i++, p += SZ_PTE) {
+		p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;
+		if (!p_cyl) continue;
+		s_part = (DWORD)sz_cyl * b_cyl;
+		sz_part = (DWORD)sz_cyl * p_cyl;
+		if (i == 0) {	/* Exclude first track of cylinder 0 */
+			s_hd = 1;
+			s_part += 63; sz_part -= 63;
+		} else {
+			s_hd = 0;
+		}
+		e_cyl = b_cyl + p_cyl - 1;
+		if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+
+		/* Set partition table */
+		p[1] = s_hd;						/* Start head */
+		p[2] = (BYTE)((b_cyl >> 2) + 1);	/* Start sector */
+		p[3] = (BYTE)b_cyl;					/* Start cylinder */
+		p[4] = 0x06;						/* System type (temporary setting) */
+		p[5] = e_hd;						/* End head */
+		p[6] = (BYTE)((e_cyl >> 2) + 63);	/* End sector */
+		p[7] = (BYTE)e_cyl;					/* End cylinder */
+		ST_DWORD(p + 8, s_part);			/* Start sector in LBA */
+		ST_DWORD(p + 12, sz_part);			/* Partition size */
+
+		/* Next partition */
+		b_cyl += p_cyl;
+	}
+	ST_WORD(p, 0xAA55);
+
+	/* Write it to the MBR */
+	return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DISK_ERR : FR_OK;
+}
+
+
+#endif /* _MULTI_PARTITION */
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+
+
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file                                            */
+/*-----------------------------------------------------------------------*/
+
+TCHAR* f_gets (
+	TCHAR* buff,	/* Pointer to the string buffer to read */
+	int len,		/* Size of string buffer (characters) */
+	FIL* fp			/* Pointer to the file object */
+)
+{
+	int n = 0;
+	TCHAR c, *p = buff;
+	BYTE s[2];
+	UINT rc;
+
+
+	while (n < len - 1) {	/* Read characters until buffer gets filled */
+#if _USE_LFN && _LFN_UNICODE
+#if _STRF_ENCODE == 3		/* Read a character in UTF-8 */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (c >= 0x80) {
+			if (c < 0xC0) continue;	/* Skip stray trailer */
+			if (c < 0xE0) {			/* Two-byte sequence */
+				f_read(fp, s, 1, &rc);
+				if (rc != 1) break;
+				c = (c & 0x1F) << 6 | (s[0] & 0x3F);
+				if (c < 0x80) c = '?';
+			} else {
+				if (c < 0xF0) {		/* Three-byte sequence */
+					f_read(fp, s, 2, &rc);
+					if (rc != 2) break;
+					c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F);
+					if (c < 0x800) c = '?';
+				} else {			/* Reject four-byte sequence */
+					c = '?';
+				}
+			}
+		}
+#elif _STRF_ENCODE == 2		/* Read a character in UTF-16BE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[1] + (s[0] << 8);
+#elif _STRF_ENCODE == 1		/* Read a character in UTF-16LE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[0] + (s[1] << 8);
+#else						/* Read a character in ANSI/OEM */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (IsDBCS1(c)) {
+			f_read(fp, s, 1, &rc);
+			if (rc != 1) break;
+			c = (c << 8) + s[0];
+		}
+		c = ff_convert(c, 1);	/* OEM -> Unicode */
+		if (!c) c = '?';
+#endif
+#else						/* Read a character without conversion */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+#endif
+		if (_USE_STRFUNC == 2 && c == '\r') continue;	/* Strip '\r' */
+		*p++ = c;
+		n++;
+		if (c == '\n') break;		/* Break on EOL */
+	}
+	*p = 0;
+	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
+}
+
+
+
+
+#if !_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file                                           */
+/*-----------------------------------------------------------------------*/
+
+typedef struct {
+	FIL* fp;
+	int idx, nchr;
+	BYTE buf[64];
+} putbuff;
+
+
+static
+void putc_bfd (
+	putbuff* pb,
+	TCHAR c
+)
+{
+	UINT bw;
+	int i;
+
+
+	if (_USE_STRFUNC == 2 && c == '\n')	 /* LF -> CRLF conversion */
+		putc_bfd(pb, '\r');
+
+	i = pb->idx;	/* Buffer write index (-1:error) */
+	if (i < 0) return;
+
+#if _USE_LFN && _LFN_UNICODE
+#if _STRF_ENCODE == 3			/* Write a character in UTF-8 */
+	if (c < 0x80) {				/* 7-bit */
+		pb->buf[i++] = (BYTE)c;
+	} else {
+		if (c < 0x800) {		/* 11-bit */
+			pb->buf[i++] = (BYTE)(0xC0 | c >> 6);
+		} else {				/* 16-bit */
+			pb->buf[i++] = (BYTE)(0xE0 | c >> 12);
+			pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F));
+		}
+		pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F));
+	}
+#elif _STRF_ENCODE == 2			/* Write a character in UTF-16BE */
+	pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#elif _STRF_ENCODE == 1			/* Write a character in UTF-16LE */
+	pb->buf[i++] = (BYTE)c;
+	pb->buf[i++] = (BYTE)(c >> 8);
+#else							/* Write a character in ANSI/OEM */
+	c = ff_convert(c, 0);	/* Unicode -> OEM */
+	if (!c) c = '?';
+	if (c >= 0x100)
+		pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#endif
+#else							/* Write a character without conversion */
+	pb->buf[i++] = (BYTE)c;
+#endif
+
+	if (i >= (int)(sizeof pb->buf) - 3) {	/* Write buffered characters to the file */
+		f_write(pb->fp, pb->buf, (UINT)i, &bw);
+		i = (bw == (UINT)i) ? 0 : -1;
+	}
+	pb->idx = i;
+	pb->nchr++;
+}
+
+
+
+int f_putc (
+	TCHAR c,	/* A character to be output */
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	putbuff pb;
+	UINT nw;
+
+
+	pb.fp = fp;			/* Initialize output buffer */
+	pb.nchr = pb.idx = 0;
+
+	putc_bfd(&pb, c);	/* Put a character */
+
+	if (   pb.idx >= 0	/* Flush buffered characters to the file */
+		&& f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK
+		&& (UINT)pb.idx == nw) return pb.nchr;
+	return EOF;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file                                              */
+/*-----------------------------------------------------------------------*/
+
+int f_puts (
+	const TCHAR* str,	/* Pointer to the string to be output */
+	FIL* fp				/* Pointer to the file object */
+)
+{
+	putbuff pb;
+	UINT nw;
+
+
+	pb.fp = fp;				/* Initialize output buffer */
+	pb.nchr = pb.idx = 0;
+
+	while (*str)			/* Put the string */
+		putc_bfd(&pb, *str++);
+
+	if (   pb.idx >= 0		/* Flush buffered characters to the file */
+		&& f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK
+		&& (UINT)pb.idx == nw) return pb.nchr;
+	return EOF;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file                                    */
+/*-----------------------------------------------------------------------*/
+
+int f_printf (
+	FIL* fp,			/* Pointer to the file object */
+	const TCHAR* fmt,	/* Pointer to the format string */
+	...					/* Optional arguments... */
+)
+{
+	va_list arp;
+	BYTE f, r;
+	UINT nw, i, j, w;
+	DWORD v;
+	TCHAR c, d, s[16], *p;
+	putbuff pb;
+
+
+	pb.fp = fp;				/* Initialize output buffer */
+	pb.nchr = pb.idx = 0;
+
+	va_start(arp, fmt);
+
+	for (;;) {
+		c = *fmt++;
+		if (c == 0) break;			/* End of string */
+		if (c != '%') {				/* Non escape character */
+			putc_bfd(&pb, c);
+			continue;
+		}
+		w = f = 0;
+		c = *fmt++;
+		if (c == '0') {				/* Flag: '0' padding */
+			f = 1; c = *fmt++;
+		} else {
+			if (c == '-') {			/* Flag: left justified */
+				f = 2; c = *fmt++;
+			}
+		}
+		while (IsDigit(c)) {		/* Precision */
+			w = w * 10 + c - '0';
+			c = *fmt++;
+		}
+		if (c == 'l' || c == 'L') {	/* Prefix: Size is long int */
+			f |= 4; c = *fmt++;
+		}
+		if (!c) break;
+		d = c;
+		if (IsLower(d)) d -= 0x20;
+		switch (d) {				/* Type is... */
+		case 'S' :					/* String */
+			p = va_arg(arp, TCHAR*);
+			for (j = 0; p[j]; j++) ;
+			if (!(f & 2)) {
+				while (j++ < w) putc_bfd(&pb, ' ');
+			}
+			while (*p) putc_bfd(&pb, *p++);
+			while (j++ < w) putc_bfd(&pb, ' ');
+			continue;
+		case 'C' :					/* Character */
+			putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
+		case 'B' :					/* Binary */
+			r = 2; break;
+		case 'O' :					/* Octal */
+			r = 8; break;
+		case 'D' :					/* Signed decimal */
+		case 'U' :					/* Unsigned decimal */
+			r = 10; break;
+		case 'X' :					/* Hexdecimal */
+			r = 16; break;
+		default:					/* Unknown type (pass-through) */
+			putc_bfd(&pb, c); continue;
+		}
+
+		/* Get an argument and put it in numeral */
+		v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int));
+		if (d == 'D' && (v & 0x80000000)) {
+			v = 0 - v;
+			f |= 8;
+		}
+		i = 0;
+		do {
+			d = (TCHAR)(v % r); v /= r;
+			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+			s[i++] = d + '0';
+		} while (v && i < sizeof s / sizeof s[0]);
+		if (f & 8) s[i++] = '-';
+		j = i; d = (f & 1) ? '0' : ' ';
+		while (!(f & 2) && j++ < w) putc_bfd(&pb, d);
+		do putc_bfd(&pb, s[--i]); while (i);
+		while (j++ < w) putc_bfd(&pb, d);
+	}
+
+	va_end(arp);
+
+	if (   pb.idx >= 0		/* Flush buffered characters to the file */
+		&& f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK
+		&& (UINT)pb.idx == nw) return pb.nchr;
+	return EOF;
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
diff --git a/Project/Application/Middlewares/Third_Party/FatFs/src/ff.h b/Project/Application/Middlewares/Third_Party/FatFs/src/ff.h
new file mode 100644
index 0000000..6d18b12
--- /dev/null
+++ b/Project/Application/Middlewares/Third_Party/FatFs/src/ff.h
@@ -0,0 +1,364 @@
+/*---------------------------------------------------------------------------/
+/  FatFs - FAT file system module include R0.11     (C)ChaN, 2015
+/----------------------------------------------------------------------------/
+/ FatFs module is a free software that opened under license policy of
+/ following conditions.
+/
+/ Copyright (C) 2015, ChaN, all right reserved.
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/---------------------------------------------------------------------------*/
+
+
+#ifndef _FATFS
+#define _FATFS	32020	/* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "integer.h"	/* Basic integer types */
+#include "ffconf.h"		/* FatFs configuration options */
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION		/* Multiple partition configuration */
+typedef struct {
+	BYTE pd;	/* Physical drive number */
+	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[];	/* Volume - Partition resolution table */
+#define LD2PD(vol) (VolToPart[vol].pd)	/* Get physical drive number */
+#define LD2PT(vol) (VolToPart[vol].pt)	/* Get partition index */
+
+#else							/* Single partition configuration */
+#define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0			/* Find first valid partition or in SFD */
+
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE			/* Unicode string */
+#if !_USE_LFN
+#error _LFN_UNICODE must be 0 at non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+
+#else						/* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+  union{
+	UINT	d32[_MAX_SS/4]; /* Force 32bits alignement */     
+	BYTE	d8[_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */  
+  }win;
+	BYTE	fs_type;		/* FAT sub-type (0:Not mounted) */
+	BYTE	drv;			/* Physical drive number */
+	BYTE	csize;			/* Sectors per cluster (1,2,4...128) */
+	BYTE	n_fats;			/* Number of FAT copies (1 or 2) */
+	BYTE	wflag;			/* win[] flag (b0:dirty) */
+	BYTE	fsi_flag;		/* FSINFO flags (b7:disabled, b0:dirty) */
+	WORD	id;				/* File system mount ID */
+	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
+#if _MAX_SS != _MIN_SS
+	WORD	ssize;			/* Bytes per sector (512, 1024, 2048 or 4096) */
+#endif
+#if _FS_REENTRANT
+	_SYNC_t	sobj;			/* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+	DWORD	last_clust;		/* Last allocated cluster */
+	DWORD	free_clust;		/* Number of free clusters */
+#endif
+#if _FS_RPATH
+	DWORD	cdir;			/* Current directory start cluster (0:root) */
+#endif
+	DWORD	n_fatent;		/* Number of FAT entries, = number of clusters + 2 */
+	DWORD	fsize;			/* Sectors per FAT */
+	DWORD	volbase;		/* Volume start sector */
+	DWORD	fatbase;		/* FAT start sector */
+	DWORD	dirbase;		/* Root directory start sector (FAT32:Cluster#) */
+	DWORD	database;		/* Data start sector */
+	DWORD	winsect;		/* Current sector appearing in the win[] */
+	
+} FATFS;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+#if !_FS_TINY
+  union{  
+	UINT	d32[_MAX_SS/4]; /* Force 32bits alignement */     
+	BYTE	d8[_MAX_SS];	/* File data read/write buffer */
+  }buf;
+#endif
+	FATFS*	fs;				/* Pointer to the related file system object (**do not change order**) */
+	WORD	id;				/* Owner file system mount ID (**do not change order**) */
+	BYTE	flag;			/* Status flags */
+	BYTE	err;			/* Abort flag (error code) */
+	DWORD	fptr;			/* File read/write pointer (Zeroed on file open) */
+	DWORD	fsize;			/* File size */
+	DWORD	sclust;			/* File start cluster (0:no cluster chain, always 0 when fsize is 0) */
+	DWORD	clust;			/* Current cluster of fpter (not valid when fprt is 0) */
+	DWORD	dsect;			/* Sector number appearing in buf[] (0:invalid) */
+#if !_FS_READONLY
+	DWORD	dir_sect;		/* Sector number containing the directory entry */
+	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] */
+#endif
+#if _USE_FASTSEEK
+	DWORD*	cltbl;			/* Pointer to the cluster link map table (Nulled on file open) */
+#endif
+#if _FS_LOCK
+	UINT	lockid;			/* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+#if !_FS_TINY
+  union{  
+            UINT     d32[_MAX_SS/4];  /* Force 32bits alignement */  
+            BYTE   d8[_MAX_SS];  /* File data read/write buffer */
+  }buf;
+#endif   
+	FATFS*	fs;				/* Pointer to the owner file system object (**do not change order**) */
+	WORD	id;				/* Owner file system mount ID (**do not change order**) */
+	WORD	index;			/* Current read/write index number */
+	DWORD	sclust;			/* Table start cluster (0:Root dir) */
+	DWORD	clust;			/* Current cluster */
+	DWORD	sect;			/* Current sector */
+	BYTE*	dir;			/* Pointer to the current SFN entry in the win[] */
+	BYTE*	fn;				/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _FS_LOCK
+	UINT	lockid;			/* File lock ID (index of file semaphore table Files[]) */
+#endif
+#if _USE_LFN
+	WCHAR*	lfn;			/* Pointer to the LFN working buffer */
+	WORD	lfn_idx;		/* Last matched LFN index number (0xFFFF:No LFN) */
+#endif
+#if _USE_FIND
+	const TCHAR*	pat;	/* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+	DWORD	fsize;			/* File size */
+	WORD	fdate;			/* Last modified date */
+	WORD	ftime;			/* Last modified time */
+	BYTE	fattrib;		/* Attribute */
+	TCHAR	fname[13];		/* Short file name (8.3 format) */
+#if _USE_LFN
+	TCHAR*	lfname;			/* Pointer to the LFN buffer */
+	UINT 	lfsize;			/* Size of LFN buffer in TCHAR */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,				/* (0) Succeeded */
+	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
+	FR_INT_ERR,				/* (2) Assertion failed */
+	FR_NOT_READY,			/* (3) The physical drive cannot work */
+	FR_NO_FILE,				/* (4) Could not find the file */
+	FR_NO_PATH,				/* (5) Could not find the path */
+	FR_INVALID_NAME,		/* (6) The path name format is invalid */
+	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
+	FR_EXIST,				/* (8) Access denied due to prohibited access */
+	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
+	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
+	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
+	FR_NOT_ENABLED,			/* (12) The volume has no work area */
+	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
+	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any parameter error */
+	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
+	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
+	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
+	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > _FS_SHARE */
+	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface                           */
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
+FRESULT f_close (FIL* fp);											/* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from a file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to a file */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
+FRESULT f_lseek (FIL* fp, DWORD ofs);								/* Move file pointer of a file object */
+FRESULT f_truncate (FIL* fp);										/* Truncate file */
+FRESULT f_sync (FIL* fp);											/* Flush cached data of a writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path);						/* Open a directory */
+FRESULT f_closedir (DIR* dp);										/* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno);							/* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno);							/* Find next file */
+FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask);			/* Change attribute of the file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change times-tamp of the file/dir */
+FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
+FRESULT f_chdrive (const TCHAR* path);								/* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
+FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, BYTE sfd, UINT au);				/* Create a file system on the volume */
+FRESULT f_fdisk (BYTE pdrv, const DWORD szt[], void* work);			/* Divide a physical drive into some partitions */
+int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->fsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->fsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions                            */
+
+/* RTC function */
+#if !_FS_READONLY && !_FS_NORTC
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN							/* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR chr, UINT dir);	/* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR chr);			/* Unicode upper-case conversion */
+#if _USE_LFN == 3						/* Memory functions */
+void* ff_memalloc (UINT msize);			/* Allocate memory block */
+void ff_memfree (void* mblock);			/* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj);	/* Create a sync object */
+int ff_req_grant (_SYNC_t sobj);				/* Lock sync object */
+void ff_rel_grant (_SYNC_t sobj);				/* Unlock sync object */
+int ff_del_syncobj (_SYNC_t sobj);				/* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+
+/* File access control and file status flags (FIL.flag) */
+
+#define	FA_READ				0x01
+#define	FA_OPEN_EXISTING	0x00
+
+#if !_FS_READONLY
+#define	FA_WRITE			0x02
+#define	FA_CREATE_NEW		0x04
+#define	FA_CREATE_ALWAYS	0x08
+#define	FA_OPEN_ALWAYS		0x10
+#define FA__WRITTEN			0x20
+#define FA__DIRTY			0x40
+#endif
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/* Fast seek feature */
+#define CREATE_LINKMAP	0xFFFFFFFF
+
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
diff --git a/Project/Application/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c b/Project/Application/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
new file mode 100644
index 0000000..984e9eb
--- /dev/null
+++ b/Project/Application/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
@@ -0,0 +1,132 @@
+/**
+  ******************************************************************************
+  * @file    ff_gen_drv.c 
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    08-May-2015
+  * @brief   FatFs generic low level driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "ff_gen_drv.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+Disk_drvTypeDef disk = {{0},{0},{0},0};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Links a compatible diskio driver/lun id and increments the number of active
+  *         linked drivers.
+  * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits.
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path 
+  * @param  lun : only used for USB Key Disk to add multi-lun management
+            else the paramter must be equal to 0
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriverEx(Diskio_drvTypeDef *drv, char *path, uint8_t lun)
+{
+  uint8_t ret = 1;
+  uint8_t DiskNum = 0;
+  
+  if(disk.nbr <= _VOLUMES)
+  {
+    disk.is_initialized[disk.nbr] = 0;
+    disk.drv[disk.nbr] = drv;  
+    disk.lun[disk.nbr] = lun;  
+    DiskNum = disk.nbr++;
+    path[0] = DiskNum + '0';
+    path[1] = ':';
+    path[2] = '/';
+    path[3] = 0;
+    ret = 0;
+  }
+  
+  return ret;
+}
+
+/**
+  * @brief  Links a compatible diskio driver and increments the number of active
+  *         linked drivers.          
+  * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path 
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriver(Diskio_drvTypeDef *drv, char *path)
+{
+  return FATFS_LinkDriverEx(drv, path, 0);
+}
+
+/**
+  * @brief  Unlinks a diskio driver and decrements the number of active linked
+  *         drivers.
+  * @param  path: pointer to the logical drive path  
+  * @param  lun : not used   
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_UnLinkDriverEx(char *path, uint8_t lun)
+{ 
+  uint8_t DiskNum = 0;
+  uint8_t ret = 1;
+  
+  if(disk.nbr >= 1)
+  {    
+    DiskNum = path[0] - '0';
+    if(disk.drv[DiskNum] != 0)
+    {
+      disk.drv[DiskNum] = 0;
+      disk.lun[DiskNum] = 0;
+      disk.nbr--;
+      ret = 0;
+    }
+  }
+  
+  return ret;
+}
+
+/**
+  * @brief  Unlinks a diskio driver and decrements the number of active linked
+  *         drivers.
+  * @param  path: pointer to the logical drive path  
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_UnLinkDriver(char *path)
+{ 
+  return FATFS_UnLinkDriverEx(path, 0);
+}
+
+/**
+  * @brief  Gets number of linked drivers to the FatFs module.
+  * @param  None
+  * @retval Number of attached drivers.
+  */
+uint8_t FATFS_GetAttachedDriversNbr(void)
+{
+  return disk.nbr;
+}
+ 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Project/Application/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h b/Project/Application/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h
new file mode 100644
index 0000000..d1c7a08
--- /dev/null
+++ b/Project/Application/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h
@@ -0,0 +1,88 @@
+/**
+  ******************************************************************************
+  * @file    ff_gen_drv.h 
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    08-May-2015
+  * @brief   Header for ff_gen_drv.c module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FF_GEN_DRV_H
+#define __FF_GEN_DRV_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+#include "diskio.h"
+#include "ff.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  Disk IO Driver structure definition  
+  */ 
+typedef struct
+{
+  DSTATUS (*disk_initialize) (BYTE);                     /*!< Initialize Disk Drive                     */
+  DSTATUS (*disk_status)     (BYTE);                     /*!< Get Disk Status                           */
+  DRESULT (*disk_read)       (BYTE, BYTE*, DWORD, UINT);       /*!< Read Sector(s)                            */
+#if _USE_WRITE == 1 
+  DRESULT (*disk_write)      (BYTE, const BYTE*, DWORD, UINT); /*!< Write Sector(s) when _USE_WRITE = 0       */
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1  
+  DRESULT (*disk_ioctl)      (BYTE, BYTE, void*);              /*!< I/O control operation when _USE_IOCTL = 1 */
+#endif /* _USE_IOCTL == 1 */
+
+}Diskio_drvTypeDef;
+
+/** 
+  * @brief  Global Disk IO Drivers structure definition  
+  */ 
+typedef struct
+{ 
+  uint8_t                 is_initialized[_VOLUMES];
+  Diskio_drvTypeDef       *drv[_VOLUMES];
+  uint8_t                 lun[_VOLUMES];
+  __IO uint8_t            nbr;
+
+}Disk_drvTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+uint8_t FATFS_LinkDriverEx(Diskio_drvTypeDef *drv, char *path, uint8_t lun);
+uint8_t FATFS_LinkDriver(Diskio_drvTypeDef *drv, char *path);
+uint8_t FATFS_UnLinkDriver(char *path);
+uint8_t FATFS_LinkDriverEx(Diskio_drvTypeDef *drv, char *path, BYTE lun);
+uint8_t FATFS_UnLinkDriverEx(char *path, BYTE lun);
+uint8_t FATFS_GetAttachedDriversNbr(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FF_GEN_DRV_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Project/Application/Middlewares/Third_Party/FatFs/src/integer.h b/Project/Application/Middlewares/Third_Party/FatFs/src/integer.h
new file mode 100644
index 0000000..f254b2a
--- /dev/null
+++ b/Project/Application/Middlewares/Third_Party/FatFs/src/integer.h
@@ -0,0 +1,33 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _FF_INTEGER
+#define _FF_INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* This type MUST be 8 bit */
+typedef unsigned char	BYTE;
+
+/* These types MUST be 16 bit */
+typedef short			SHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types MUST be 16 bit or 32 bit */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types MUST be 32 bit */
+typedef long			LONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
diff --git a/Project/Application/Middlewares/Third_Party/FatFs/src/option/syscall.c b/Project/Application/Middlewares/Third_Party/FatFs/src/option/syscall.c
new file mode 100644
index 0000000..bf1870f
--- /dev/null
+++ b/Project/Application/Middlewares/Third_Party/FatFs/src/option/syscall.c
@@ -0,0 +1,119 @@
+/*------------------------------------------------------------------------*/
+/* Sample code of OS dependent controls for FatFs                         */
+/* (C)ChaN, 2014                                                          */
+/*------------------------------------------------------------------------*/
+
+#include <stdlib.h>		/* ANSI memory controls */
+#include "../ff.h"
+
+#if _FS_REENTRANT
+/*-----------------------------------------------------------------------
+ Create a Synchronization Object
+------------------------------------------------------------------------
+ This function is called in f_mount function to create a new
+ synchronization object, such as semaphore and mutex. When a zero is
+ returned, the f_mount function fails with FR_INT_ERR.
+*/
+
+int ff_cre_syncobj (	/* TRUE:Function succeeded, FALSE:Could not create due to any error */
+	BYTE vol,			/* Corresponding logical drive being processed */
+	_SYNC_t *sobj		/* Pointer to return the created sync object */
+)
+{
+  int ret;
+  
+  osSemaphoreDef(SEM);
+  *sobj = osSemaphoreCreate(osSemaphore(SEM), 1);		
+  ret = (*sobj != NULL);
+  
+  return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount function to delete a synchronization
+/  object that created with ff_cre_syncobj function. When a zero is
+/  returned, the f_mount function fails with FR_INT_ERR.
+*/
+
+int ff_del_syncobj (	/* TRUE:Function succeeded, FALSE:Could not delete due to any error */
+	_SYNC_t sobj		/* Sync object tied to the logical drive to be deleted */
+)
+{
+  osSemaphoreDelete (sobj);
+  return 1;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Request Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on entering file functions to lock the volume.
+/  When a zero is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_req_grant (	/* TRUE:Got a grant to access the volume, FALSE:Could not get a grant */
+	_SYNC_t sobj	/* Sync object to wait */
+)
+{
+  int ret = 0;
+  
+  if(osSemaphoreWait(sobj, _FS_TIMEOUT) == osOK)
+  {
+    ret = 1;
+  }
+  
+  return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Release Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on leaving file functions to unlock the volume.
+*/
+
+void ff_rel_grant (
+	_SYNC_t sobj	/* Sync object to be signaled */
+)
+{
+  osSemaphoreRelease(sobj);
+}
+
+#endif
+
+
+
+
+#if _USE_LFN == 3	/* LFN with a working buffer on the heap */
+/*------------------------------------------------------------------------*/
+/* Allocate a memory block                                                */
+/*------------------------------------------------------------------------*/
+/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE.
+*/
+
+void* ff_memalloc (	/* Returns pointer to the allocated memory block */
+	UINT msize		/* Number of bytes to allocate */
+)
+{
+	return malloc(msize);	/* Allocate a new memory block with POSIX API */
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Free a memory block                                                    */
+/*------------------------------------------------------------------------*/
+
+void ff_memfree (
+	void* mblock	/* Pointer to the memory block to free */
+)
+{
+	free(mblock);	/* Discard the memory block with POSIX API */
+}
+
+#endif
diff --git a/Project/Application/action_process.c b/Project/Application/action_process.c
new file mode 100644
index 0000000..ad690e6
--- /dev/null
+++ b/Project/Application/action_process.c
@@ -0,0 +1,50 @@
+#include "action_process.h"
+#include "sw_timer.h"
+#include "gpio_switch.h"
+#include "gpio_state_led.h"
+#include "gpio_sensor.h"
+#include "eeprom.h"
+#include "buzzer.h"
+#include "segment.h"
+#include "rtc_process.h"
+#include "save_file.h"
+
+typedef struct _control_info
+{
+    bool        isActionRun;
+    uint32_t    Co2_MaxValue;
+    uint32_t    Co2_MinValue;
+}CONTROL_INFO;
+
+
+static CONTROL_INFO Control_Info;
+
+
+
+
+
+static void Action_Process(void);
+
+static void Action_PowerKey_Push(void);
+static void Action_PowerKey_LongPush(void);
+static void Action_Sensor_Read_Process(void);
+
+void Action_Initialization(void)
+{
+
+    SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1, Action_Process);
+}
+
+
+static void Action_Process(void)
+{
+    
+}
+
+
+
+
+
+
+
+
diff --git a/Project/Application/action_process.h b/Project/Application/action_process.h
new file mode 100644
index 0000000..cbc9f38
--- /dev/null
+++ b/Project/Application/action_process.h
@@ -0,0 +1,17 @@
+/** \file action_process.h */ 
+#if !defined(ACTION_PROCESS_H__793AF4F0_9732_4285_BF6C_F708ACCE969B__INCLUDED_)
+#define ACTION_PROCESS_H__793AF4F0_9732_4285_BF6C_F708ACCE969B__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+
+
+
+
+void Action_Initialization(void);
+
+
+
+
+#endif
diff --git a/Project/Application/board_config.h b/Project/Application/board_config.h
new file mode 100644
index 0000000..39b5d7c
--- /dev/null
+++ b/Project/Application/board_config.h
@@ -0,0 +1,70 @@
+/** \file board_config.h */ 
+#if !defined(BOARD_CONFIG_H__8269C71E_6C81_429B_B9F6_2CA6AC082DCC__INCLUDED_)
+#define BOARD_CONFIG_H__8269C71E_6C81_429B_B9F6_2CA6AC082DCC__INCLUDED_
+
+#include "define.h"
+
+#define FW_VERSION_MAJOR    0
+#define FW_VERSION_MINOR    1
+
+
+
+//////////////////////////////////////////////////////////////
+#define FALSE   0
+#define TRUE    (!FALSE)
+
+
+
+//////////////////////////////////////////////////////////////
+// dbg_print Config
+//////////////////////////////////////////////////////////////
+#define DEBUG_PRINT
+
+#if defined(DEBUG_PRINT)    
+    #define dbg_printf(fmt,args...)     printf( fmt, ## args )                
+#if 0    
+    #define SW_TIMER_DBG_PRINT
+#endif    
+
+#else
+    #define dbg_printf(fmt,args...)         
+#endif
+
+
+
+
+
+#if 0
+//////////////////////////////////////////////////////////////
+// MODBUS Config
+//////////////////////////////////////////////////////////////
+#define MODBUS_BAUDRATE                             9600
+#define MODBUS_DATA_BIT                             UARTn_DATA_BIT_8
+#define MODBUS_STOP_BIT                             UARTn_STOP_BIT_1
+#define MODBUS_PARITY_BIT                           UARTn_PARITY_BIT_EVEN
+#define MODBUS_RX_TIMEOUT                           100                             
+#define MODBUS_DEFAULT_ADDRESS                      0x01
+#define MODBUS_START_REG_ADDRESS                    0x0000
+#define MODBUS_GET_REG_COUNT                        0x0029
+#define MODBUS_POLLING_INTERVAL_TIME                1000                            //??? ?? ??
+#define MODBUS_DATA_INDEX_OUTPUT_COUNT              100                             //??? ??? ?? ??? ??
+#define MODBUS_DATA_UPDATE_CHECK_INTERVAL_TIME      (MODBUS_POLLING_INTERVAL_TIME/2)
+#define MODBUS_TX_ERROR_COUNT                       10                              //?? ?? ?? ?? ???? ??, ??? ???
+
+
+
+//////////////////////////////////////////////////////////////
+// DATA OUT Uart Config
+//////////////////////////////////////////////////////////////
+#define DATAOUT_BAUDRATE            115200
+#define DATAOUT_DATA_BIT            USART1n_DATA_BIT_8
+#define DATAOUT_STOP_BIT            USART1n_STOP_BIT_1
+#define DATAOUT_PARITY_BIT          USART1n_PARITY_BIT_NONE
+#define DATAOUT_INTERFACE_INIT      Usart11_Initialization
+#define DATAOUT_TRANSMIT            Usart11_Transmit
+
+#endif
+
+
+
+#endif
diff --git a/Project/Application/buzzer.c b/Project/Application/buzzer.c
new file mode 100644
index 0000000..ce02d80
--- /dev/null
+++ b/Project/Application/buzzer.c
@@ -0,0 +1,47 @@
+#include "buzzer.h"
+#include "sw_timer.h"
+
+
+static bool isBuzzerOn;
+static uint32_t BuzzerStartTick;
+static uint32_t BuzzerOnTimeCount;
+
+static void Buzzer_Output_Process(void);
+
+void Buzzer_Initialization(void)
+{
+    HAL_GPIO_ConfigOutput(GPIO_BUZZER_PORT, GPIO_BUZZER_PIN_NUM, PUSH_PULL_OUTPUT);    
+    HAL_GPIO_ConfigPullup(GPIO_BUZZER_PORT, GPIO_BUZZER_PIN_NUM, PUPDx_EnablePU);
+
+    SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1, Buzzer_Output_Process);
+}
+
+void Buzzer_On(uint32_t BuzzerOnTime)
+{
+    isBuzzerOn = true;
+    BuzzerStartTick = millis();
+    BuzzerOnTimeCount = BuzzerOnTime;
+}
+
+
+
+static void Buzzer_Output_Process(void)
+{
+    if(isBuzzerOn == true)
+    {
+        if((millis() - BuzzerStartTick) <= BuzzerOnTimeCount)
+        {
+            GPIO_BUZZER_ON;
+        }
+        else
+        {
+            isBuzzerOn = false;
+            GPIO_BUZZER_OFF;
+        }
+    }
+    else
+    {
+        GPIO_BUZZER_OFF;;
+    }
+}
+
diff --git a/Project/Application/buzzer.h b/Project/Application/buzzer.h
new file mode 100644
index 0000000..7498056
--- /dev/null
+++ b/Project/Application/buzzer.h
@@ -0,0 +1,26 @@
+/** \file buzzer.h */ 
+#if !defined(BUZZER_H__4676A357_207F_4D31_A901_C2B23A663560__INCLUDED_)
+#define BUZZER_H__4676A357_207F_4D31_A901_C2B23A663560__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+
+#define GPIO_BUZZER_PORT         (Pn_Type*)PD
+#define GPIO_BUZZER_PIN_NUM      7
+#define GPIO_BUZZER_ON           HAL_GPIO_SetPin(GPIO_BUZZER_PORT, _BIT(GPIO_BUZZER_PIN_NUM))
+#define GPIO_BUZZER_OFF          HAL_GPIO_ClearPin(GPIO_BUZZER_PORT, _BIT(GPIO_BUZZER_PIN_NUM))
+#define GPIO_BUZZER_T            HAL_GPIO_TogglePin(GPIO_BUZZER_PORT, _BIT(GPIO_BUZZER_PIN_NUM))
+
+
+
+
+
+void Buzzer_Initialization(void);
+void Buzzer_On(uint32_t BuzzerOnTime);
+
+
+
+
+
+#endif
diff --git a/Project/Application/dbg_printf.c b/Project/Application/dbg_printf.c
new file mode 100644
index 0000000..b8dc653
--- /dev/null
+++ b/Project/Application/dbg_printf.c
@@ -0,0 +1,25 @@
+#include "dbg_printf.h"
+
+#include "uart1.h"
+
+
+
+
+
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a character to file
+ * @param[in]     ch
+ *                   Character to put
+ * @param[in]     f
+ *                   Pointer to file
+ * @return        character
+ * @note          if you use IAR EWARM, select Full as Options/General Options/Library Configuration/Library.
+ *//*-------------------------------------------------------------------------*/
+int fputc( int ch, FILE* f )
+{
+    Uart1_Transmit(ch);
+    return( ch );
+}
+
+
diff --git a/Project/Application/dbg_printf.h b/Project/Application/dbg_printf.h
new file mode 100644
index 0000000..c118f94
--- /dev/null
+++ b/Project/Application/dbg_printf.h
@@ -0,0 +1,9 @@
+/** \file dbg_printf.h */ 
+#if !defined(DBG_PRINTF_H__3735CB34_D9A0_43AC_B22D_005B5B83B450__INCLUDED_)
+#define DBG_PRINTF_H__3735CB34_D9A0_43AC_B22D_005B5B83B450__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+
+#endif
diff --git a/Project/Application/define.h b/Project/Application/define.h
new file mode 100644
index 0000000..3a26b6e
--- /dev/null
+++ b/Project/Application/define.h
@@ -0,0 +1,95 @@
+/** \file define.h */ 
+#if !defined(DEFINE_H__8F668E66_FF75_45CB_850C_2513B033D139__INCLUDED_)
+#define DEFINE_H__8F668E66_FF75_45CB_850C_2513B033D139__INCLUDED_
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdbool.h>
+#include <math.h>
+
+
+
+
+
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+#include "A31G12x_hal_adc.h"
+#include "A31G12x_hal_crc.h"
+#include "A31G12x_hal_debug_frmwrk.h"
+#include "A31G12x_hal_fmc.h"
+#include "A31G12x_hal_i2cn.h"
+#include "A31G12x_hal_intc.h"
+#include "A31G12x_hal_lcd.h"
+#include "A31G12x_hal_libcfg.h"
+#include "A31G12x_hal_pcu.h"
+#include "A31G12x_hal_pwr.h"
+#include "A31G12x_hal_scu.h"
+#include "A31G12x_hal_sculv.h"
+#include "A31G12x_hal_timer1n.h"
+#include "A31G12x_hal_timer2n.h"
+#include "A31G12x_hal_timer3n.h"
+#include "A31G12x_hal_uartn.h"
+#include "A31G12x_hal_usart1n.h"
+#include "A31G12x_hal_wdt.h"
+#include "A31G12x_hal_wt.h"
+#include "A31G12x_hal_wtidky.h"
+
+
+
+
+#include "A31G12x_SystemClock.h"
+
+#include "systick_timer.h"
+
+
+
+#define SETBIT(ADDRESS,BIT)		(ADDRESS |= (1<<BIT))
+#define CLEARBIT(ADDRESS,BIT)	(ADDRESS &= ~(1<<BIT))
+#define TESTBIT(ADDRESS,BIT)	((ADDRESS & (1<<BIT)) ? 1 : 0)
+#define TOGGLEBIT(ADDRESS, BIT) (ADDRESS ^= (1<<BIT))
+
+
+
+
+
+
+#define VERSION_MAJOR   0   // max 9
+#define VERSION_MINOR   0   // max 9
+#define VERSION_PATCH   1   // max 99
+
+
+
+#define SEGMENT_CHECK_WAIT_TIME     300 // 
+#define SEGMENT_VERSION_WAIT_TIME   1000
+
+
+#define DEFAULT_KEY_PUSH_COUNT          50
+#define DEFAULT_LONGKEY_PUSH_COUNT      1000
+
+
+#define DUST_SENSOR_POWER_ON_WAIT_TIME_COUNT    100
+#define DUST_SENSOR_POWER_OFF_WAIT_TIME_COUNT   100
+
+
+#define DUST_SENSOR_PM4P0_VIEW_TIME             5       // sec
+#define DUST_SENSOR_PM1P0_VIEW_TIME             5       // sec
+#define DUST_SENSOR_MODE_1_TIME                 1000
+#define DUST_SENSOR_MODE_2_TIME                 2000
+#define DUST_SENSOR_MODE_3_TIME                 3000
+#define DUST_SENSOR_MODE_4_TIME                 4000
+#define DUST_SENSOR_MODE_5_TIME                 5000
+
+#define DUST_SENSOR_PM40_SELECT_1               SEGMENT_OUTPUT_F3C1
+#define DUST_SENSOR_PM40_SELECT_2               SEGMENT_OUTPUT_F3C2
+
+
+#define SEGMENT_TOGGLE_TIME                     250
+
+
+
+#endif
+
diff --git a/Project/Application/driver_ds3231.c b/Project/Application/driver_ds3231.c
new file mode 100644
index 0000000..2a207f2
--- /dev/null
+++ b/Project/Application/driver_ds3231.c
@@ -0,0 +1,1809 @@
+/**
+ * Copyright (c) 2015 - present LibDriver All rights reserved
+ * 
+ * The MIT License (MIT)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE. 
+ *
+ * @file      driver_ds3231.c
+ * @brief     driver ds3231 source file
+ * @version   2.0.0
+ * @author    Shifeng Li
+ * @date      2021-03-15
+ *
+ * <h3>history</h3>
+ * <table>
+ * <tr><th>Date        <th>Version  <th>Author      <th>Description
+ * <tr><td>2021/03/15  <td>2.0      <td>Shifeng Li  <td>format the code
+ * <tr><td>2020/11/30  <td>1.0      <td>Shifeng Li  <td>first upload
+ * </table>
+ */
+
+#include "driver_ds3231.h"
+
+/**
+ * @brief chip information definition
+ */
+#define CHIP_NAME                 "Maxim Integrated DS3231"        /**< chip name */
+#define MANUFACTURER_NAME         "Maxim Integrated"               /**< manufacturer name */
+#define SUPPLY_VOLTAGE_MIN        2.3f                             /**< chip min supply voltage */
+#define SUPPLY_VOLTAGE_MAX        5.5f                             /**< chip max supply voltage */
+#define MAX_CURRENT               0.65f                            /**< chip max current */
+#define TEMPERATURE_MIN           -40.0f                           /**< chip min operating temperature */
+#define TEMPERATURE_MAX           85.0f                            /**< chip max operating temperature */
+#define DRIVER_VERSION            2000                             /**< driver version */
+
+/**
+ * @brief chip register definition
+ */
+#define DS3231_REG_SECOND               0x00        /**< second register */
+#define DS3231_REG_MINUTE               0x01        /**< minute register */
+#define DS3231_REG_HOUR                 0x02        /**< hour register */
+#define DS3231_REG_WEEK                 0x03        /**< week register */
+#define DS3231_REG_DATE                 0x04        /**< date register */
+#define DS3231_REG_MONTH                0x05        /**< month register */
+#define DS3231_REG_YEAR                 0x06        /**< year register */
+#define DS3231_REG_ALARM1_SECOND        0x07        /**< alarm1 second register */
+#define DS3231_REG_ALARM1_MINUTE        0x08        /**< alarm1 minute register */
+#define DS3231_REG_ALARM1_HOUR          0x09        /**< alarm1 hour register */
+#define DS3231_REG_ALARM1_WEEK          0x0A        /**< alarm1 week register */
+#define DS3231_REG_ALARM2_MINUTE        0x0B        /**< alarm2 minute register */
+#define DS3231_REG_ALARM2_HOUR          0x0C        /**< alarm2 hour register */
+#define DS3231_REG_ALARM2_WEEK          0x0D        /**< alarm2 week register */
+#define DS3231_REG_CONTROL              0x0E        /**< control register */
+#define DS3231_REG_STATUS               0x0F        /**< status register */
+#define DS3231_REG_XTAL                 0x10        /**< xtal register */
+#define DS3231_REG_TEMPERATUREH         0x11        /**< temperature high register */
+#define DS3231_REG_TEMPERATUREL         0x12        /**< temperature low register */
+
+/**
+ * @brief chip address definition
+ */
+#define DS3231_ADDRESS        0x68        /**< iic device address */ 
+
+/**
+ * @brief     write one byte
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] reg is the iic register address
+ * @param[in] data is the write data
+ * @return    status code
+ *            - 0 success
+ *            - 1 write failed
+ * @note      none
+ */
+static uint8_t a_ds3231_iic_write(ds3231_handle_t *handle, uint8_t reg, uint8_t data)
+{
+    if (handle->iic_write(DS3231_ADDRESS, reg, &data, 1) != 0)        /* write data */
+    {
+        return 1;                                                     /* return error */
+    }
+    else
+    {
+        return 0;                                                     /* success return 0 */
+    }
+}
+
+/**
+ * @brief      read multiple bytes
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  reg is the iic register address
+ * @param[out] *buf points to a data buffer
+ * @param[in]  len is the data buffer length
+ * @return     status code
+ *             - 0 success
+ *             - 1 read failed
+ * @note       none
+ */
+static uint8_t a_ds3231_iic_multiple_read(ds3231_handle_t *handle, uint8_t reg, uint8_t *buf, uint8_t len)
+{
+    if (handle->iic_read(DS3231_ADDRESS, reg, buf, len) != 0)        /* read data */
+    {
+        return 1;                                                    /* return error */
+    }
+    else
+    {                                                                /* success return 0 */
+        return 0;
+    }
+}
+
+/**
+ * @brief     hex to bcd
+ * @param[in] val is the hex data
+ * @return    bcd data
+ * @note      none
+ */
+static uint8_t a_ds3231_hex2bcd(uint8_t val)
+{
+    uint8_t i, j, k;
+    
+    i = val / 10;            /* get tens place */
+    j = val % 10;            /* get ones place */
+    k = j + (i << 4);        /* set bcd */
+    
+    return k;                /* return bcd */
+}
+
+/**
+ * @brief     bcd to hex
+ * @param[in] val is the bcd data
+ * @return    hex data
+ * @note      none
+ */
+static uint8_t a_ds3231_bcd2hex(uint8_t val)
+{
+    uint8_t temp;
+    
+    temp = val & 0x0F;              /* get ones place */
+    val = (val >> 4) & 0x0F;        /* get tens place */
+    val = val * 10;                 /* set tens place */
+    temp = temp + val;              /* get hex */
+    
+    return temp;                    /* return hex */
+}
+
+/**
+ * @brief     set the current time
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] *t points to a time structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 set time failed
+ *            - 2 handle or time is NULL
+ *            - 3 handle is not initialized
+ *            - 4 time is invalid
+ * @note      none
+ */
+uint8_t ds3231_set_time(ds3231_handle_t *handle, ds3231_time_t *t)
+{
+    uint8_t res;
+    uint8_t reg;
+    uint8_t century;
+    uint16_t year;
+    
+    if (handle == NULL)                                                                                      /* check handle */
+    {
+        return 2;                                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                                 /* check handle initialization */
+    {
+        return 3;                                                                                            /* return error */
+    }
+    if (t == NULL)                                                                                           /* check time */
+    {
+        handle->debug_print("ds3231: time is null.\n");                                                      /* time is null */
+        
+        return 2;                                                                                            /* return error */
+    }
+    if (t->format == DS3231_FORMAT_12H)                                                                      /* if 12H */
+    {
+        if ((t->year < 1990) || (t->year > 2190))                                                            /* check year */
+        {
+            handle->debug_print("ds3231: year can't be over 2190 or less than 1990.\n");                     /* year can't be over 2190 or less than 1990 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if ((t->month == 0) || (t->month > 12))                                                              /* check month */
+        {
+            handle->debug_print("ds3231: month can't be zero or over than 12.\n");                           /* month can't be zero or over than 12 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if ((t->week == 0) || (t->week > 7))                                                                 /* check week */
+        {
+            handle->debug_print("ds3231: week can't be zero or over than 7.\n");                             /* week can't be zero or over than 7 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if ((t->date == 0) || (t->date > 31))                                                                /* check data */
+        {
+            handle->debug_print("ds3231: date can't be zero or over than 31.\n");                            /* date can't be zero or over than 31 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if ((t->hour < 1) || (t->hour > 12))                                                                 /* check hour */
+        {
+            handle->debug_print("ds3231: hour can't be over than 12 or less 1.\n");                          /* hour can't be over than 12 or less 1 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if (t->minute > 59)                                                                                  /* check minute */
+        {
+            handle->debug_print("ds3231: minute can't be over than 59.\n");                                  /* minute can't be over than 59 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if (t->second > 59)                                                                                  /* check second */
+        {
+            handle->debug_print("ds3231: second can't be over than 59.\n");                                  /* second can't be over than 59 */
+            
+            return 4;                                                                                        /* return error */
+        }
+    }
+    else if (t->format == DS3231_FORMAT_24H)                                                                 /* if 24H */
+    {
+        if ((t->year < 1990) || (t->year > 2190))                                                            /* check year */
+        {
+            handle->debug_print("ds3231: year can't be over 2190 or less than 1990.\n");                     /* year can't be over 2190 or less than 1990 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if ((t->month == 0) || (t->month > 12))                                                              /* check month */
+        {
+            handle->debug_print("ds3231: month can't be zero or over than 12.\n");                           /* month can't be zero or over than 12 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if ((t->week == 0) || (t->week > 7))                                                                 /* check week */
+        {
+            handle->debug_print("ds3231: week can't be zero or over than 7.\n");                             /* week can't be zero or over than 7 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if ((t->date == 0) || (t->date > 31))                                                                /* check data */
+        {
+            handle->debug_print("ds3231: date can't be zero or over than 31.\n");                            /* date can't be zero or over than 31 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if (t->hour > 23)                                                                                    /* check hour */
+        {
+            handle->debug_print("ds3231: hour can't be over than 23.\n");                                    /* hour can't be over than 23 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if (t->minute > 59)                                                                                  /* check minute */
+        {
+            handle->debug_print("ds3231: minute can't be over than 59.\n");                                  /* minute can't be over than 59 */
+            
+            return 4;                                                                                        /* return error */
+        }
+        if (t->second > 59)                                                                                  /* check second */
+        {
+            handle->debug_print("ds3231: second can't be over than 59.\n");                                  /* second can't be over than 59 */
+            
+            return 4;                                                                                        /* return error */
+        }
+    }
+    else
+    {
+        handle->debug_print("ds3231: format is invalid.\n");                                                 /* format is invalid */
+        
+        return 4;                                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_write(handle, DS3231_REG_SECOND, a_ds3231_hex2bcd(t->second));                        /* write second */
+    if (res != 0)                                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write second failed.\n");                                               /* write second failed */
+        
+        return 1;                                                                                            /* return error */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_MINUTE, a_ds3231_hex2bcd(t->minute));                        /* write minute */
+    if (res != 0)                                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write minute failed.\n");                                               /* write minute failed */
+        
+        return 1;                                                                                            /* return error */
+    }
+    if (t->format == DS3231_FORMAT_12H)                                                                      /* if 12H */
+    {
+        reg = (uint8_t)((1 << 6) | (t->am_pm << 5) | a_ds3231_hex2bcd(t->hour));                             /* set hour in 12H */
+    }
+    else                                                                                                     /* if 24H */
+    {
+        reg = (0 << 6) | a_ds3231_hex2bcd(t->hour);                                                          /* set hour in 24H */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_HOUR, reg);                                                  /* write hour */
+    if (res != 0)                                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write hour failed.\n");                                                 /* write hour failed */
+        
+        return 1;                                                                                            /* return error */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_WEEK, a_ds3231_hex2bcd(t->week));                            /* write week */
+    if (res != 0)                                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write week failed.\n");                                                 /* write week failed */
+        
+        return 1;                                                                                            /* return error */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_DATE, a_ds3231_hex2bcd(t->date));                            /* write data */
+    if (res != 0)                                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write date failed.\n");                                                 /* write date failed */
+        
+        return 1;                                                                                            /* return error */
+    }
+    year = t->year - 1990;                                                                                   /* year -1990 */
+    if (year >= 100)                                                                                         /* check year */
+    {
+        century = 1;                                                                                         /* set century */
+        year -= 100;                                                                                         /* year -= 100 */
+    }
+    else
+    {
+        century = 0;                                                                                         /* set century 0 */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_MONTH, a_ds3231_hex2bcd(t->month) | (century << 7));         /* write month and century */
+    if (res != 0)                                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write century and month failed.\n");                                    /* write century and month failed */
+        
+        return 1;                                                                                            /* return error */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_YEAR, a_ds3231_hex2bcd((uint8_t)year));                      /* write year */
+    if (res != 0)                                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write year failed.\n");                                                 /* write year failed */
+        
+        return 1;                                                                                            /* return error */
+    }
+    
+    return 0;                                                                                                /* success return 0 */
+}
+
+/**
+ * @brief      get the current time
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *t points to a time structure
+ * @return     status code
+ *             - 0 success
+ *             - 1 get time failed
+ *             - 2 handle or time is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_time(ds3231_handle_t *handle, ds3231_time_t *t)
+{
+    uint8_t res;
+    uint8_t buf[7];
+    
+    if (handle == NULL)                                                                   /* check handle */
+    {
+        return 2;                                                                         /* return error */
+    }
+    if (handle->inited != 1)                                                              /* check handle initialization */
+    {
+        return 3;                                                                         /* return error */
+    }
+    if (t == NULL)                                                                        /* check time */
+    {
+        handle->debug_print("ds3231: time is null.\n");                                   /* time is null */
+        
+        return 2;                                                                         /* return error */
+    }
+    
+    memset(buf, 0, sizeof(uint8_t) * 7);                                                  /* clear the buffer */
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_SECOND, (uint8_t *)buf, 7);       /* multiple_read */
+    if (res != 0)                                                                         /* check result */
+    {
+        handle->debug_print("ds3231: multiple read failed.\n");                           /* multiple read failed */
+        
+        return 1;                                                                         /* return error */
+    }
+    t->year = a_ds3231_bcd2hex(buf[6]) + 1990 + ((buf[5] >> 7) & 0x01) * 100;             /* get year */
+    t->month = a_ds3231_bcd2hex(buf[5]&0x1F);                                             /* get month */
+    t->week = a_ds3231_bcd2hex(buf[3]);                                                   /* get week */
+    t->date = a_ds3231_bcd2hex(buf[4]);                                                   /* get date */
+    t->am_pm = (ds3231_am_pm_t)((buf[2] >> 5) & 0x01);                                    /* get am pm */
+    t->format = (ds3231_format_t)((buf[2] >> 6) & 0x01);                                  /* get format */
+    if (t->format == DS3231_FORMAT_12H)                                                   /* if 12H */
+    {
+        t->hour = a_ds3231_bcd2hex(buf[2] & 0x1F);                                        /* get hour */
+    }
+    else
+    {
+        t->hour = a_ds3231_bcd2hex(buf[2] & 0x3F);                                        /* get hour */
+    }
+    t->minute = a_ds3231_bcd2hex(buf[1]);                                                 /* get minute */
+    t->second = a_ds3231_bcd2hex(buf[0]);                                                 /* get second */
+    
+    return 0;                                                                             /* success return 0 */
+}
+
+/**
+ * @brief     set the alarm1 time
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] *t points to a time structure
+ * @param[in] mode is the alarm1 interrupt mode
+ * @return    status code
+ *            - 0 success
+ *            - 1 set alarm1 failed
+ *            - 2 handle or time is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_alarm1(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm1_mode_t mode)
+{
+    uint8_t res;
+    uint8_t reg;
+    
+    if (handle == NULL)                                                                                                            /* check handle */
+    {
+        return 2;                                                                                                                  /* return error */
+    }
+    if (handle->inited != 1)                                                                                                       /* check handle initialization */
+    {
+        return 3;                                                                                                                  /* return error */
+    }
+    if (t == NULL)                                                                                                                 /* check time */
+    {
+        handle->debug_print("ds3231: time is null.\n");                                                                            /* time is null */
+        
+        return 2;                                                                                                                  /* return error */
+    }
+    if (t->format == DS3231_FORMAT_12H)                                                                                            /* if 12H */
+    {
+        if ((t->week == 0) || (t->week > 7))                                                                                       /* check week */
+        {
+            handle->debug_print("ds3231: week can't be zero or over than 7.\n");                                                   /* week can't be zero or over than 7 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if ((t->date == 0) || (t->date > 31))                                                                                      /* check data */
+        {
+            handle->debug_print("ds3231: date can't be zero or over than 31.\n");                                                  /* date can't be zero or over than 31 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if ((t->hour < 1) || (t->hour > 12))                                                                                       /* check hour */
+        {
+            handle->debug_print("ds3231: hour can't be over than 12 or less 1.\n");                                                /* hour can't be over than 12 or less 1 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if (t->minute > 59)                                                                                                        /* check minute */
+        {
+            handle->debug_print("ds3231: minute can't be over than 59.\n");                                                        /* minute can't be over than 59 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if (t->second > 59)                                                                                                        /* check second  */
+        {
+            handle->debug_print("ds3231: second can't be over than 59.\n");                                                        /* second can't be over than 59 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+    }
+    else if (t->format == DS3231_FORMAT_24H)                                                                                       /* if 24H */
+    {
+        if ((t->week == 0) || (t->week > 7))                                                                                       /* check week */
+        {
+            handle->debug_print("ds3231: week can't be zero or over than 7.\n");                                                   /* week can't be zero or over than 7 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if ((t->date == 0) || (t->date > 31))                                                                                      /* check data */
+        {
+            handle->debug_print("ds3231: date can't be zero or over than 31.\n");                                                  /* date can't be zero or over than 31 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if (t->hour > 23)                                                                                                          /* check hour */
+        {
+            handle->debug_print("ds3231: hour can't be over than 23.\n");                                                          /* hour can't be over than 23 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if (t->minute > 59)                                                                                                        /* check minute */
+        {
+            handle->debug_print("ds3231: minute can't be over than 59.\n");                                                        /* minute can't be over than 59 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if (t->second > 59)                                                                                                        /* check second */
+        {
+            handle->debug_print("ds3231: second can't be over than 59.\n");                                                        /* second can't be over than 59 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+    }
+    else
+    {
+        handle->debug_print("ds3231: format is invalid.\n");                                                                       /* format is invalid */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    
+    res = a_ds3231_iic_write(handle, DS3231_REG_ALARM1_SECOND, a_ds3231_hex2bcd(t->second) | ((mode & 0x01) << 7));                /* write second */
+    if (res != 0)                                                                                                                  /* check result */
+    {
+        handle->debug_print("ds3231: write alarm1 second failed.\n");                                                              /* write alarm1 second failed */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_ALARM1_MINUTE, a_ds3231_hex2bcd(t->minute) | (((mode >> 1) & 0x01) << 7));         /* write minute */
+    if (res != 0)                                                                                                                  /* check result */
+    {
+        handle->debug_print("ds3231: write alarm1 minute failed.\n");                                                              /* write alarm1 minute failed */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    if (t->format == DS3231_FORMAT_12H)                                                                                            /* if 12H */
+    {
+        reg = (uint8_t)((((mode >> 2) & 0x01) << 7) | (1 << 6) | (t->am_pm << 5) | a_ds3231_hex2bcd(t->hour));                     /* set hour in 12H */
+    }
+    else                                                                                                                           /* if 24H */
+    {
+        reg = (((mode >> 2) & 0x01) << 7) | a_ds3231_hex2bcd(t->hour);                                                             /* set hour in 24H */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_ALARM1_HOUR, reg);                                                                 /* write hour */
+    if (res != 0)                                                                                                                  /* check result */
+    {
+        handle->debug_print("ds3231: write alarm1 hour failed.\n");                                                                /* write alarm1 hour failed */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    if (mode >= DS3231_ALARM1_MODE_WEEK_HOUR_MINUTE_SECOND_MATCH)                                                                  /* if week */
+    {
+        reg = (((mode >> 3) & 0x01) << 7) | (1 << 6) | a_ds3231_hex2bcd(t->week);                                                  /* set data in week */
+    }
+    else                                                                                                                           /* if day */
+    {
+        reg = (((mode >> 3) & 0x01) << 7) | a_ds3231_hex2bcd(t->date);                                                             /* set data in date */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_ALARM1_WEEK, reg);                                                                 /* write week */
+    if (res != 0)                                                                                                                  /* check result */
+    {
+        handle->debug_print("ds3231: write alarm1 week failed.\n");                                                                /* write alarm1 week failed */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    
+    return 0;                                                                                                                      /* success return 0 */
+}
+
+/**
+ * @brief      get the alarm1 time
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *t points to a time structure
+ * @param[out] *mode points to an alarm1 interrupt mode buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get alarm1 failed
+ *             - 2 handle or time is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_alarm1(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm1_mode_t *mode)
+{
+    uint8_t res;
+    uint8_t buf[4];
+    
+    if (handle == NULL)                                                                                                                   /* check handle */
+    {
+        return 2;                                                                                                                         /* return error */
+    }
+    if (handle->inited != 1)                                                                                                              /* check handle initialization */
+    {
+        return 3;                                                                                                                         /* return error */
+    }
+    if (t == NULL)                                                                                                                        /* check time */
+    {
+        handle->debug_print("ds3231: time is null.\n");                                                                                   /* time is null */
+        
+        return 2;                                                                                                                         /* return error */
+    }
+    
+    memset(buf, 0, sizeof(uint8_t) * 4);                                                                                                  /* clear the buffer */
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_ALARM1_SECOND, (uint8_t *)buf, 4);                                                /* multiple_read */
+    if (res != 0)                                                                                                                         /* check result */
+    {
+        handle->debug_print("ds3231: multiple read failed.\n");                                                                           /* multiple read failed */
+        
+        return 1;                                                                                                                         /* return error */
+    }
+    t->year = 0;                                                                                                                          /* get year */
+    t->month = 0;                                                                                                                         /* get month */
+    if (((buf[3] >> 6) & 0x01) != 0)                                                                                                      /* if week */
+    {
+        t->week = a_ds3231_bcd2hex(buf[3] & 0x0F);                                                                                        /* get week */
+        t->date = 0;                                                                                                                      /* get data */
+    }
+    else                                                                                                                                  /* if data */
+    {
+        t->week = 0;                                                                                                                      /* get week */
+        t->date = a_ds3231_bcd2hex(buf[3] & 0x3F);                                                                                        /* get data */
+    }
+    t->am_pm = (ds3231_am_pm_t)((buf[2] >> 5) & 0x01);                                                                                    /* get am pm */
+    t->format = (ds3231_format_t)((buf[2] >> 6) & 0x01);                                                                                  /* get format */
+    if (t->format == DS3231_FORMAT_12H)                                                                                                   /* if 12H */
+    {
+        t->hour = a_ds3231_bcd2hex(buf[2]&0x1F);                                                                                          /* get hour */
+    }
+    else                                                                                                                                  /* if 24H */
+    {
+        t->hour = a_ds3231_bcd2hex(buf[2]&0x3F);                                                                                          /* get hour */
+    }
+    t->minute = a_ds3231_bcd2hex(buf[1] & 0x7F);                                                                                          /* get minute */
+    t->second = a_ds3231_bcd2hex(buf[0] & 0x7F);                                                                                          /* get second */
+    *mode = (ds3231_alarm1_mode_t)(((buf[0]>>7)&0x01)<<0 | ((buf[1]>>7)&0x01)<<1 | ((buf[2]>>7)&0x01)<<2 | ((buf[3]>>7)&0x01)<<3 |
+                                   ((buf[3] >> 6)&0x01)<<4
+                                  );                                                                                                      /* get mode */
+    
+    return 0;                                                                                                                             /* success return 0 */
+}
+
+/**
+ * @brief     set the alarm2 time
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] *t points to a time structure
+ * @param[in] mode is the alarm2 interrupt mode
+ * @return    status code
+ *            - 0 success
+ *            - 1 set alarm2 failed
+ *            - 2 handle or time is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_alarm2(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm2_mode_t mode)
+{
+    uint8_t res;
+    uint8_t reg;
+    
+    if (handle == NULL)                                                                                                            /* check handle */
+    {
+        return 2;                                                                                                                  /* return error */
+    }
+    if (handle->inited != 1)                                                                                                       /* check handle initialization */
+    {
+        return 3;                                                                                                                  /* return error */
+    }
+    if (t == NULL)                                                                                                                 /* check time */
+    {
+        handle->debug_print("ds3231: time is null.\n");                                                                            /* time is null */
+        
+        return 2;                                                                                                                  /* return error */
+    }
+    if (t->format == DS3231_FORMAT_12H)                                                                                            /* if 12H */
+    {
+        if ((t->week == 0) || (t->week > 7))                                                                                       /* check week */
+        {
+            handle->debug_print("ds3231: week can't be zero or over than 7.\n");                                                   /* week can't be zero or over than 7 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if ((t->date == 0) || (t->date > 31))                                                                                      /* check data */
+        {
+            handle->debug_print("ds3231: date can't be zero or over than 31.\n");                                                  /* date can't be zero or over than 31 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if ((t->hour < 1) || (t->hour > 12))                                                                                       /* check hour */
+        {
+            handle->debug_print("ds3231: hour can't be over than 12 or less 1.\n");                                                /* hour can't be over than 12 or less 1 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if (t->minute > 59)                                                                                                        /* check minute */
+        {
+            handle->debug_print("ds3231: minute can't be over than 59.\n");                                                        /* minute can't be over than 59 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+    }
+    else if (t->format == DS3231_FORMAT_24H)                                                                                       /* if 24H */
+    {
+        if ((t->week == 0) || (t->week > 7))                                                                                       /* check week */
+        {
+            handle->debug_print("ds3231: week can't be zero or over than 7.\n");                                                   /* week can't be zero or over than 7 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if ((t->date == 0) || (t->date > 31))                                                                                      /* check data */
+        {
+            handle->debug_print("ds3231: date can't be zero or over than 31.\n");                                                  /* date can't be zero or over than 31 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if (t->hour > 23)                                                                                                          /* check hour */
+        {
+            handle->debug_print("ds3231: hour can't be over than 23.\n");                                                          /* hour can't be over than 23 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+        if (t->minute > 59)                                                                                                        /* check minute */
+        {
+            handle->debug_print("ds3231: minute can't be over than 59.\n");                                                        /* minute can't be over than 59 */
+            
+            return 1;                                                                                                              /* return error */
+        }
+    }
+    else
+    {
+        handle->debug_print("ds3231: format is invalid.\n");                                                                       /* format is invalid */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    
+    res = a_ds3231_iic_write(handle, DS3231_REG_ALARM2_MINUTE, a_ds3231_hex2bcd(t->minute) | (((mode >> 0) & 0x01) << 7));         /* write minute */
+    if (res != 0)                                                                                                                  /* check result */
+    {
+        handle->debug_print("ds3231: write alarm2 minute failed.\n");                                                              /* write alarm2 minute failed */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    if (t->format == DS3231_FORMAT_12H)                                                                                            /* if 12H */
+    {
+        reg = (uint8_t)((((mode >> 1) & 0x01) << 7) | (1 << 6) | (t->am_pm << 5) | a_ds3231_hex2bcd(t->hour));                     /* set hour in 12H */
+    }
+    else                                                                                                                           /* if 24H */
+    {
+        reg = (((mode >> 1) & 0x01) << 7) | a_ds3231_hex2bcd(t->hour);                                                             /* set hour in 24H */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_ALARM2_HOUR, reg);                                                                 /* write hour */
+    if (res != 0)                                                                                                                  /* check result */
+    {
+        handle->debug_print("ds3231: write alarm2 hour failed.\n");                                                                /* write alarm2 hour failed */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    if (mode >= (uint8_t)DS3231_ALARM1_MODE_WEEK_HOUR_MINUTE_SECOND_MATCH)                                                         /* if week */
+    {
+        reg = (((mode >> 2) & 0x01) << 7) | (1 << 6) | a_ds3231_hex2bcd(t->week);                                                  /* set data in week */
+    }
+    else                                                                                                                           /* if day */
+    {
+        reg = (((mode >> 2) & 0x01) << 7) | a_ds3231_hex2bcd(t->date);                                                             /* set data in date */
+    }
+    res = a_ds3231_iic_write(handle, DS3231_REG_ALARM2_WEEK, reg);                                                                 /* write week */
+    if (res != 0)                                                                                                                  /* check result */
+    {
+        handle->debug_print("ds3231: write alarm2 week failed.\n");                                                                /* write alarm2 week failed */
+        
+        return 1;                                                                                                                  /* return error */
+    }
+    
+    return 0;                                                                                                                      /* success return 0 */
+}
+
+/**
+ * @brief      get the alarm2 time
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *t points to a time structure
+ * @param[out] *mode points to an alarm2 interrupt mode buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get alarm2 failed
+ *             - 2 handle or time is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_alarm2(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm2_mode_t *mode)
+{
+    uint8_t res;
+    uint8_t buf[3];
+    
+    if (handle == NULL)                                                                                                                   /* check handle */
+    {
+        return 2;                                                                                                                         /* return error */
+    }
+    if (handle->inited != 1)                                                                                                              /* check handle initialization */
+    {
+        return 3;                                                                                                                         /* return error */
+    }
+    if (t == NULL)                                                                                                                        /* check time */
+    {
+        handle->debug_print("ds3231: time is null.\n");                                                                                   /* time is null */
+        
+        return 2;                                                                                                                         /* return error */
+    }
+    
+    memset(buf, 0, sizeof(uint8_t) * 3);                                                                                                  /* clear the buffer */
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_ALARM2_MINUTE, (uint8_t *)buf, 3);                                                /* multiple read */
+    if (res != 0)                                                                                                                         /* check result */
+    {
+        handle->debug_print("ds3231: multiple read failed.\n");                                                                           /* multiple read failed */
+        
+        return 1;                                                                                                                         /* return error */
+    }
+    t->year = 0;                                                                                                                          /* get year */
+    t->month = 0;                                                                                                                         /* get month */
+    if (((buf[2] >> 6) & 0x01) != 0)                                                                                                      /* if week */
+    {
+        t->week = a_ds3231_bcd2hex(buf[2] & 0x0F);                                                                                        /* get week */
+        t->date = 0;                                                                                                                      /* get data */
+    }
+    else                                                                                                                                  /* if data */
+    {
+        t->week = 0;                                                                                                                      /* get week */
+        t->date = a_ds3231_bcd2hex(buf[2] & 0x3F);                                                                                        /* get data */
+    }
+    t->am_pm = (ds3231_am_pm_t)((buf[1] >> 5) & 0x01);                                                                                    /* get am pm */
+    t->format = (ds3231_format_t)((buf[1] >> 6) & 0x01);                                                                                  /* get format */
+    if (t->format == DS3231_FORMAT_12H)                                                                                                   /* if 12H */
+    {
+        t->hour = a_ds3231_bcd2hex(buf[1]&0x1F);                                                                                          /* get hour */
+    }
+    else                                                                                                                                  /* if 24H */
+    {
+        t->hour = a_ds3231_bcd2hex(buf[1]&0x3F);                                                                                          /* get hour */
+    }
+    t->minute = a_ds3231_bcd2hex(buf[0] & 0x7F);                                                                                          /* get minute */
+    t->second = 0;                                                                                                                        /* get second */
+    *mode = (ds3231_alarm2_mode_t)(((buf[0]>>7)&0x01)<<0 | ((buf[1]>>7)&0x01)<<1 | ((buf[2]>>7)&0x01)<<2 | ((buf[2]>>6)&0x01)<<4);        /* get mode */
+    
+    return 0;                                                                                                                             /* success return 0 */
+}
+
+/**
+ * @brief     enable or disable the oscillator
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] enable is a bool value
+ * @return    status code
+ *            - 0 success
+ *            - 1 set oscillator failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_oscillator(ds3231_handle_t *handle, ds3231_bool_t enable)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);       /* multiple read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                               /* read control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    prev &= ~ (1 << 7);                                                                      /* clear config */
+    prev |= (!enable) << 7;                                                                  /* set enable */
+    res = a_ds3231_iic_write(handle, DS3231_REG_CONTROL, prev);                              /* write control */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write control failed.\n");                              /* write control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief      get the chip oscillator status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *enable points to a bool value buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get oscillator failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_oscillator(ds3231_handle_t *handle, ds3231_bool_t *enable)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);       /* multiple read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                               /* read control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    *enable = (ds3231_bool_t)(!((prev >> 7) & 0x01));                                        /* get enable */
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief     enable or disable the alarm interrupt
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] alarm is the alarm number
+ * @param[in] enable is a bool value
+ * @return    status code
+ *            - 0 success
+ *            - 1 set alarm interrupt failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_alarm_interrupt(ds3231_handle_t *handle, ds3231_alarm_t alarm, ds3231_bool_t enable)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);       /* multiple_read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                               /* read control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    prev &= ~(1 << alarm);                                                                   /* clear config */
+    prev |= enable << alarm;                                                                 /* set enable */
+    res = a_ds3231_iic_write(handle, DS3231_REG_CONTROL, prev);                              /* write control */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write control failed.\n");                              /* write control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief      get the alarm interrupt status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  alarm is the alarm number
+ * @param[out] *enable points to a bool value buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get alarm interrupt failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_alarm_interrupt(ds3231_handle_t *handle, ds3231_alarm_t alarm, ds3231_bool_t *enable)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);       /* multiple_read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                               /* read control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    *enable = (ds3231_bool_t)((prev >> alarm) & 0x01);                                       /* get enable */
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief     set the chip pin function
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] pin is the pin's function
+ * @return    status code
+ *            - 0 success
+ *            - 1 set pin failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_pin(ds3231_handle_t *handle, ds3231_pin_t pin)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);       /* multiple_read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                               /* read control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    prev &= ~(1 << 2);                                                                       /* clear config */
+    prev |= pin << 2;                                                                        /* set pin */
+    res = a_ds3231_iic_write(handle, DS3231_REG_CONTROL, prev);                              /* write control */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write control failed.\n");                              /* write control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief      get the chip pin function
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *pin points to a pin's function buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get pin failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_pin(ds3231_handle_t *handle, ds3231_pin_t *pin)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);       /* multiple_read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                               /* read control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    *pin = (ds3231_pin_t)((prev >> 2) & 0x01);                                               /* get pin */
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief     enable or disable the square wave output
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] enable is a bool value
+ * @return    status code
+ *            - 0 success
+ *            - 1 set square wave failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_square_wave(ds3231_handle_t *handle, ds3231_bool_t enable)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);       /* multiple_read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                               /* read control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    prev &= ~(1 << 6);                                                                       /* clear config */
+    prev |= enable << 6;                                                                     /* set enable */
+    res = a_ds3231_iic_write(handle, DS3231_REG_CONTROL, prev);                              /* write control */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write control failed.\n");                              /* write control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief      get the square wave output status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *enable points to a bool value buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get square wave failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_square_wave(ds3231_handle_t *handle, ds3231_bool_t *enable)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);       /* multiple_read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                               /* read control failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    *enable = (ds3231_bool_t)((prev >> 6) & 0x01);                                           /* get enable */
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief      get the chip temperature
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *raw points to a raw temperature buffer
+ * @param[out] *s points to a converted temperature buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get temperature failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_temperature(ds3231_handle_t *handle, int16_t *raw, float *s)
+{
+    uint8_t res;
+    uint8_t prev;
+    uint32_t times;
+    uint8_t buf[2];
+    
+    if (handle == NULL)                                                                         /* check handle */
+    {
+        return 2;                                                                               /* return error */
+    }
+    if (handle->inited != 1)                                                                    /* check handle initialization */
+    {
+        return 3;                                                                               /* return error */
+    }
+    
+    memset(buf, 0, sizeof(uint8_t) * 2);                                                        /* clear the buffer */
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_CONTROL, (uint8_t *)&prev, 1);          /* multiple read */
+    if (res != 0)                                                                               /* check result */
+    {
+        handle->debug_print("ds3231: read control failed.\n");                                  /* read control failed */
+        
+        return 1;                                                                               /* return error */
+    }
+    prev &= ~(1 << 5);                                                                          /* clear config */
+    prev |= 1 << 5;                                                                             /* set enable */
+    res = a_ds3231_iic_write(handle, DS3231_REG_CONTROL, prev);                                 /* write control */
+    if (res != 0)                                                                               /* check result */
+    {
+        handle->debug_print("ds3231: write control failed.\n");                                 /* write control failed */
+        
+        return 1;                                                                               /* return error */
+    }
+    times = 500;                                                                                /* set 5s */
+    while (times != 0)                                                                          /* check times */
+    {
+        handle->delay_ms(10);                                                                   /* delay 10 ms */
+        res = a_ds3231_iic_multiple_read(handle, DS3231_REG_STATUS, (uint8_t *)&prev, 1);       /* read status */
+        if (res != 0)                                                                           /* check result */
+        {
+            handle->debug_print("ds3231: read status failed.\n");                               /* read status failed */
+            
+            return 1;                                                                           /* return error */
+        }
+        if (((prev >> 2) & 0x01) == 0)                                                          /* check result */
+        {
+            break;                                                                              /* break */
+        }
+        times--;                                                                                /* times-- */
+    }
+    if (times == 0)                                                                             /* if zero */
+    {
+        handle->debug_print("ds3231: read timeout.\n");                                         /* read timeout */
+        
+        return 1;                                                                               /* return error */
+    }
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_TEMPERATUREH, (uint8_t *)buf, 2);       /* read temperature */
+    if (res != 0)                                                                               /* check result */
+    {
+        handle->debug_print("ds3231: read temperature failed.\n");                              /* read temperature failed */
+        
+        return 1;                                                                               /* return error */
+    }
+    *raw = (int16_t)(((uint16_t)buf[0]) << 8) | buf[1];                                         /* set raw temperature */
+    *raw = (*raw) >> 6;                                                                         /* right shift */
+    if (((*raw) & 0x0200) != 0)                                                                 /* set negative value */
+    {
+        *raw = (*raw) | 0xFC00U;                                                                /* set negative part */
+    }
+    *s = (float)(*raw) * 0.25f;                                                                 /* set converted temperature */
+    
+    return 0;                                                                                   /* success return 0 */
+}
+
+/**
+ * @brief      get the chip status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *status points to a chip status buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get status failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_status(ds3231_handle_t *handle, uint8_t *status)
+{
+    uint8_t res;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_STATUS, (uint8_t *)status, 1);       /* multiple read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read status failed.\n");                                /* read status failed */
+        
+        return 1;                                                                            /* return error */
+    }
+
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief     set the chip aging offset
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] offset is time aging offset
+ * @return    status code
+ *            - 0 success
+ *            - 1 set aging offset failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_aging_offset(ds3231_handle_t *handle, int8_t offset)
+{
+    uint8_t res;
+    
+    if (handle == NULL)                                               /* check handle */
+    {
+        return 2;                                                     /* return error */
+    }
+    if (handle->inited != 1)                                          /* check handle initialization */
+    {
+        return 3;                                                     /* return error */
+    }
+
+    res = a_ds3231_iic_write(handle, DS3231_REG_XTAL, offset);        /* write offset */
+    if (res != 0)                                                     /* check result */
+    {
+        handle->debug_print("ds3231: write offset failed.\n");        /* write offset failed */
+        
+        return 1;                                                     /* return error */
+    }
+    
+    return 0;                                                         /* success return 0 */
+}
+
+/**
+ * @brief      get the chip aging offset
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *offset points to a time aging offset buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get aging offset failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_aging_offset(ds3231_handle_t *handle, int8_t *offset)
+{
+    uint8_t res;
+    
+    if (handle == NULL)                                                                    /* check handle */
+    {
+        return 2;                                                                          /* return error */
+    }
+    if (handle->inited != 1)                                                               /* check handle initialization */
+    {
+        return 3;                                                                          /* return error */
+    }
+
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_XTAL, (uint8_t *)offset, 1);       /* read offset */
+    if (res != 0)                                                                          /* check result */
+    {
+        handle->debug_print("ds3231: read offset failed.\n");                              /* read offset failed */
+        
+        return 1;                                                                          /* return error */
+    }
+    
+    return 0;                                                                              /* success return 0 */
+}
+
+/**
+ * @brief      convert a aging offset value to a register raw data
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  offset is a converted aging offset value
+ * @param[out] *reg points to a register raw buffer
+ * @return     status code
+ *             - 0 success
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_aging_offset_convert_to_register(ds3231_handle_t *handle, float offset, int8_t *reg)
+{
+    if (handle == NULL)                     /* check handle */
+    {
+        return 2;                           /* return error */
+    }
+    if (handle->inited != 1)                /* check handle initialization */
+    {
+        return 3;                           /* return error */
+    }
+    
+    *reg = (int8_t)(offset / 0.12f);        /* convert real data to register data */
+    
+    return 0;                               /* success return 0 */
+}
+
+/**
+ * @brief      convert a register raw data to a converted aging offset data
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  reg is the register raw data
+ * @param[out] *offset points to a converted aging offset buffer
+ * @return     status code
+ *             - 0 success
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_aging_offset_convert_to_data(ds3231_handle_t *handle, int8_t reg, float *offset)
+{
+    if (handle == NULL)                    /* check handle */
+    {
+        return 2;                          /* return error */
+    }
+    if (handle->inited != 1)               /* check handle initialization */
+    {
+        return 3;                          /* return error */
+    }
+    
+    *offset = (float)(reg) * 0.12f;        /* convert raw data to real data */
+    
+    return 0;                              /* success return 0 */
+}
+
+/**
+ * @brief     irq handler
+ * @param[in] *handle points to a ds3231 handle structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 run failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_irq_handler(ds3231_handle_t *handle)
+{
+    uint8_t res, prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_STATUS, (uint8_t *)&prev, 1);        /* multiple read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read status failed.\n");                                /* read status failed */
+        
+        return 1;                                                                            /* return error */
+    }                                                                                        /* if oscillator stop */
+    if ((prev & DS3231_STATUS_ALARM_2) != 0)                                                 /* if alarm 2 */
+    {
+        if (handle->receive_callback != NULL)                                                /* if receive callback */
+        {
+            handle->receive_callback(DS3231_STATUS_ALARM_2);                                 /* run callback */
+        }
+    }
+    if ((prev & DS3231_STATUS_ALARM_1) != 0)                                                 /* if alarm 1 */
+    {
+        if (handle->receive_callback != NULL)                                                /* if receive callback */
+        {
+            handle->receive_callback(DS3231_STATUS_ALARM_1);                                 /* run callback */
+        }
+    }
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief     initialize the chip
+ * @param[in] *handle points to a ds3231 handle structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 iic initialization failed
+ *            - 2 handle is NULL
+ *            - 3 linked functions is NULL
+ * @note      none
+ */
+uint8_t ds3231_init(ds3231_handle_t *handle)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->debug_print == NULL)                                                         /* check debug_print */
+    {
+        return 3;                                                                            /* return error */
+    }
+    if (handle->iic_init == NULL)                                                            /* check iic_init */
+    {
+        handle->debug_print("ds3231: iic_init is null.\n");                                  /* iic_init is null */
+       
+        return 3;                                                                            /* return error */
+    }
+    if (handle->iic_deinit == NULL)                                                          /* check iic_deinit */
+    {
+        handle->debug_print("ds3231: iic_deinit is null.\n");                                /* iic_deinit is null */
+       
+        return 3;                                                                            /* return error */
+    }
+    if (handle->iic_write == NULL)                                                           /* check iic_write */
+    {
+        handle->debug_print("ds3231: iic_write is null.\n");                                 /* iic_write is null */
+       
+        return 3;                                                                            /* return error */
+    }
+    if (handle->iic_read == NULL)                                                            /* check iic_read */
+    {
+        handle->debug_print("ds3231: iic_read is null.\n");                                  /* iic_read is null */
+       
+        return 3;                                                                            /* return error */
+    }
+    if (handle->delay_ms == NULL)                                                            /* check delay_ms */
+    {
+        handle->debug_print("ds3231: delay_ms is null.\n");                                  /* delay_ms is null */
+       
+        return 3;                                                                            /* return error */
+    }
+    if (handle->receive_callback == NULL)                                                    /* check receive_callback */
+    {
+        handle->debug_print("ds3231: receive_callback is null.\n");                          /* receive_callback is null */
+       
+        return 3;                                                                            /* return error */
+    }
+    
+    if (handle->iic_init() != 0)                                                             /* iic init */
+    {
+        handle->debug_print("ds3231: iic init failed.\n");                                   /* iic init failed */
+       
+        return 1;                                                                            /* return error */
+    }
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_STATUS, (uint8_t *)&prev, 1);        /* multiple_read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read status failed.\n");                                /* read status failed */
+        (void)handle->iic_deinit();                                                          /* iic deinit */
+        
+        return 1;                                                                            /* return error */
+    }
+    prev &= ~(1 << 7);                                                                       /* clear config */
+    res = a_ds3231_iic_write(handle, DS3231_REG_STATUS, prev);                               /* write status */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write status failed.\n");                               /* write status failed */
+        (void)handle->iic_deinit();                                                          /* iic deinit */
+        
+        return 1;                                                                            /* return error */
+    }
+    handle->inited = 1;                                                                      /* flag finish initialization */
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief     close the chip
+ * @param[in] *handle points to a ds3231 handle structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 iic deinit failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_deinit(ds3231_handle_t *handle)
+{
+    if (handle == NULL)                                             /* check handle */
+    {
+        return 2;                                                   /* return error */
+    }
+    if (handle->inited != 1)                                        /* check handle initialization */
+    {
+        return 3;                                                   /* return error */
+    }
+    
+    if (handle->iic_deinit() != 0)                                  /* iic deinit */
+    {
+        handle->debug_print("ds3231: iic deinit failed.\n");        /* iic deinit failed */
+       
+        return 1;                                                   /* return error */
+    }
+    handle->inited = 0;                                             /* flag close */
+    
+    return 0;                                                       /* success return 0 */
+}
+
+/**
+ * @brief     clear the alarm flag
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] alarm is the alarm number
+ * @return    status code
+ *            - 0 success
+ *            - 1 alarm clear failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_alarm_clear(ds3231_handle_t *handle, ds3231_alarm_t alarm)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_STATUS, (uint8_t *)&prev, 1);        /* multiple_read  */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read status failed.\n");                                /* read status failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    prev &= ~(1 << alarm);                                                                   /* clear config */
+    res = a_ds3231_iic_write(handle, DS3231_REG_STATUS, prev);                               /* write status */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write status failed.\n");                               /* write status failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief     enable or disable the 32KHz output
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] enable is a bool value
+ * @return    status code
+ *            - 0 success
+ *            - 1 set 32khz output failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_32khz_output(ds3231_handle_t *handle, ds3231_bool_t enable)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_STATUS, (uint8_t *)&prev, 1);        /* multiple read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read status failed.\n");                                /* read status failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    prev &= ~(1 << 3);                                                                       /* clear config */
+    prev |= enable << 3;                                                                     /* set enable */
+    res = a_ds3231_iic_write(handle, DS3231_REG_STATUS, prev);                               /* write status */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: write status failed.\n");                               /* write status failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief      get the 32KHz output status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *enable points to a bool value buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get 32khz output failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_32khz_output(ds3231_handle_t *handle, ds3231_bool_t *enable)
+{
+    uint8_t res;
+    uint8_t prev;
+    
+    if (handle == NULL)                                                                      /* check handle */
+    {
+        return 2;                                                                            /* return error */
+    }
+    if (handle->inited != 1)                                                                 /* check handle initialization */
+    {
+        return 3;                                                                            /* return error */
+    }
+    
+    res = a_ds3231_iic_multiple_read(handle, DS3231_REG_STATUS, (uint8_t *)&prev, 1);        /* multiple read */
+    if (res != 0)                                                                            /* check result */
+    {
+        handle->debug_print("ds3231: read status failed.\n");                                /* read status failed */
+        
+        return 1;                                                                            /* return error */
+    }
+    *enable = (ds3231_bool_t)((prev >> 3) & 0x01);                                           /* get enable */
+    
+    return 0;                                                                                /* success return 0 */
+}
+
+/**
+ * @brief     set the chip register
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] reg is the iic register address
+ * @param[in] *buf points to a data buffer
+ * @param[in] len is the data buffer length
+ * @return    status code
+ *            - 0 success
+ *            - 1 write failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_reg(ds3231_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
+{
+    if (handle == NULL)                                               /* check handle */
+    {
+        return 2;                                                     /* return error */
+    }
+    if (handle->inited != 1)                                          /* check handle initialization */
+    {
+        return 3;                                                     /* return error */
+    }
+    
+    if (handle->iic_write(DS3231_ADDRESS, reg, buf, len) != 0)        /* write data */
+    {
+        return 1;                                                     /* return error */
+    }
+    else
+    {
+        return 0;                                                     /* success return 0 */
+    }
+}
+
+/**
+ * @brief      get the chip register
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  reg is the iic register address
+ * @param[out] *buf points to a data buffer
+ * @param[in]  len is the data buffer length
+ * @return     status code
+ *             - 0 success
+ *             - 1 read failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_reg(ds3231_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
+{
+    if (handle == NULL)                                              /* check handle */
+    {
+        return 2;                                                    /* return error */
+    }
+    if (handle->inited != 1)                                         /* check handle initialization */
+    {
+        return 3;                                                    /* return error */
+    }
+    
+    if (handle->iic_read(DS3231_ADDRESS, reg, buf, len) != 0)        /* read data */
+    {
+        return 1;                                                    /* return error */
+    }
+    else
+    {
+        return 0;                                                    /* success return 0 */
+    }
+}
+
+/**
+ * @brief      get chip's information
+ * @param[out] *info points to a ds3231 info structure
+ * @return     status code
+ *             - 0 success
+ *             - 2 handle is NULL
+ * @note       none
+ */
+uint8_t ds3231_info(ds3231_info_t *info)
+{
+    if (info == NULL)                                               /* check handle */
+    {
+        return 2;                                                   /* return error */
+    }
+    
+    memset(info, 0, sizeof(ds3231_info_t));                         /* initialize ds3231 info structure */
+    strncpy(info->chip_name, CHIP_NAME, 32);                        /* copy chip name */
+    strncpy(info->manufacturer_name, MANUFACTURER_NAME, 32);        /* copy manufacturer name */
+    strncpy(info->interface, "IIC", 8);                             /* copy interface name */
+    info->supply_voltage_min_v = SUPPLY_VOLTAGE_MIN;                /* set minimal supply voltage */
+    info->supply_voltage_max_v = SUPPLY_VOLTAGE_MAX;                /* set maximum supply voltage */
+    info->max_current_ma = MAX_CURRENT;                             /* set maximum current */
+    info->temperature_max = TEMPERATURE_MAX;                        /* set minimal temperature */
+    info->temperature_min = TEMPERATURE_MIN;                        /* set maximum temperature */
+    info->driver_version = DRIVER_VERSION;                          /* set driver version */
+    
+    return 0;                                                       /* success return 0 */
+}
diff --git a/Project/Application/driver_ds3231.h b/Project/Application/driver_ds3231.h
new file mode 100644
index 0000000..1b888e4
--- /dev/null
+++ b/Project/Application/driver_ds3231.h
@@ -0,0 +1,718 @@
+/**
+ * Copyright (c) 2015 - present LibDriver All rights reserved
+ * 
+ * The MIT License (MIT)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE. 
+ *
+ * @file      driver_ds3231.h
+ * @brief     driver ds3231 header file
+ * @version   2.0.0
+ * @author    Shifeng Li
+ * @date      2021-03-15
+ *
+ * <h3>history</h3>
+ * <table>
+ * <tr><th>Date        <th>Version  <th>Author      <th>Description
+ * <tr><td>2021/03/15  <td>2.0      <td>Shifeng Li  <td>format the code
+ * <tr><td>2020/11/30  <td>1.0      <td>Shifeng Li  <td>first upload
+ * </table>
+ */
+
+#ifndef DRIVER_DS3231_H
+#define DRIVER_DS3231_H
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/**
+ * @defgroup ds3231_driver ds3231 driver function
+ * @brief    ds3231 driver modules
+ * @{
+ */
+
+/**
+ * @addtogroup ds3231_base_driver
+ * @{
+ */
+
+/**
+ * @brief ds3231 bool enumeration definition
+ */
+typedef enum
+{
+    DS3231_BOOL_FALSE = 0x00,        /**< disable function */
+    DS3231_BOOL_TRUE  = 0x01,        /**< enable function */
+} ds3231_bool_t;
+
+/**
+ * @brief ds3231 alarm enumeration definition
+ */
+typedef enum
+{
+    DS3231_ALARM_1 = 0x00,        /**< alarm 1 */
+    DS3231_ALARM_2 = 0x01,        /**< alarm 2 */
+} ds3231_alarm_t;
+
+/**
+ * @brief ds3231 am pm enumeration definition
+ */
+typedef enum
+{
+    DS3231_AM = 0x00,        /**< am */
+    DS3231_PM = 0x01,        /**< pm */
+} ds3231_am_pm_t;
+
+/**
+ * @brief ds3231 pin enumeration definition
+ */
+typedef enum
+{
+    DS3231_PIN_SQUARE_WAVE = 0x00,        /**< square wave pin */
+    DS3231_PIN_INTERRUPT   = 0x01,        /**< interrupt pin */
+} ds3231_pin_t;
+
+/**
+ * @brief ds3231 format enumeration definition
+ */
+typedef enum
+{
+    DS3231_FORMAT_12H = 0x01,        /**< 12h format */
+    DS3231_FORMAT_24H = 0x00,        /**< 24h format */
+} ds3231_format_t;
+
+/**
+ * @brief ds3231 alarm1 enumeration definition
+ */
+typedef enum
+{
+    DS3231_STATUS_ALARM_2 = (1 << 1),        /**< alarm 2 status */
+    DS3231_STATUS_ALARM_1 = (1 << 0),        /**< alarm 1 status */
+} ds3231_status_t;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup ds3231_alarm_driver
+ * @{
+ */
+
+/**
+ * @brief ds3231 alarm1 enumeration definition
+ */
+typedef enum
+{
+    DS3231_ALARM1_MODE_ONCE_A_SECOND                 = 0x0F,        /**< interrupt once a second */
+    DS3231_ALARM1_MODE_SECOND_MATCH                  = 0x0E,        /**< interrupt second match */
+    DS3231_ALARM1_MODE_MINUTE_SECOND_MATCH           = 0x0C,        /**< interrupt minute second match */
+    DS3231_ALARM1_MODE_HOUR_MINUTE_SECOND_MATCH      = 0x08,        /**< interrupt hour minute second match */
+    DS3231_ALARM1_MODE_DATE_HOUR_MINUTE_SECOND_MATCH = 0x00,        /**< interrupt date hour minute second match */
+    DS3231_ALARM1_MODE_WEEK_HOUR_MINUTE_SECOND_MATCH = 0x10,        /**< interrupt week hour minute second match */
+} ds3231_alarm1_mode_t;
+
+/**
+ * @brief ds3231 alarm2 enumeration definition
+ */
+typedef enum
+{
+    DS3231_ALARM2_MODE_ONCE_A_MINUTE          = 0x07,        /**< interrupt once a minute */
+    DS3231_ALARM2_MODE_MINUTE_MATCH           = 0x06,        /**< interrupt minute match */
+    DS3231_ALARM2_MODE_HOUR_MINUTE_MATCH      = 0x04,        /**< interrupt hour minute match */
+    DS3231_ALARM2_MODE_DATE_HOUR_MINUTE_MATCH = 0x00,        /**< interrupt data hour minute match */
+    DS3231_ALARM2_MODE_WEEK_HOUR_MINUTE_MATCH = 0x10,        /**< interrupt week hour minute match */
+} ds3231_alarm2_mode_t;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup ds3231_base_driver
+ * @{
+ */
+
+/**
+ * @brief ds3231 time structure definition
+ */
+typedef struct ds3231_time_s
+{
+    uint16_t year;                 /**< year */
+    uint8_t month;                 /**< month */
+    uint8_t week;                  /**< week */
+    uint8_t date;                  /**< date */
+    uint8_t hour;                  /**< hour */
+    uint8_t minute;                /**< minute */
+    uint8_t second;                /**< second */
+    ds3231_format_t format;        /**< data format */
+    ds3231_am_pm_t am_pm;          /**< am pm */
+} ds3231_time_t;
+
+/**
+ * @brief ds3231 handle structure definition
+ */
+typedef struct ds3231_handle_s
+{
+    uint8_t (*iic_init)(void);                                                          /**< point to an iic_init function address */
+    uint8_t (*iic_deinit)(void);                                                        /**< point to an iic_deinit function address */
+    uint8_t (*iic_write)(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len);        /**< point to an iic_write function address */
+    uint8_t (*iic_read)(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len);         /**< point to an iic_read function address */
+    void (*debug_print)(const char *const fmt, ...);                                    /**< point to a debug_print function address */
+    void (*receive_callback)(uint8_t type);                                             /**< point to a receive_callback function address */
+    void (*delay_ms)(uint32_t ms);                                                      /**< point to a delay_ms function address */
+    uint8_t inited;                                                                     /**< inited flag */
+} ds3231_handle_t;
+
+/**
+ * @brief ds3231 information structure definition
+ */
+typedef struct ds3231_info_s
+{
+    char chip_name[32];                /**< chip name */
+    char manufacturer_name[32];        /**< manufacturer name */
+    char interface[8];                 /**< chip interface name */
+    float supply_voltage_min_v;        /**< chip min supply voltage */
+    float supply_voltage_max_v;        /**< chip max supply voltage */
+    float max_current_ma;              /**< chip max current */
+    float temperature_min;             /**< chip min operating temperature */
+    float temperature_max;             /**< chip max operating temperature */
+    uint32_t driver_version;           /**< driver version */
+} ds3231_info_t;
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ds3231_link_driver ds3231 link driver function
+ * @brief    ds3231 link driver modules
+ * @ingroup  ds3231_driver
+ * @{
+ */
+
+/**
+ * @brief     initialize ds3231_handle_t structure
+ * @param[in] HANDLE points to a ds3231 handle structure
+ * @param[in] STRUCTURE is ds3231_handle_t
+ * @note      none
+ */
+#define DRIVER_DS3231_LINK_INIT(HANDLE, STRUCTURE)         memset(HANDLE, 0, sizeof(STRUCTURE))
+
+/**
+ * @brief     link iic_init function
+ * @param[in] HANDLE points to a ds3231 handle structure
+ * @param[in] FUC points to an iic_init function address
+ * @note      none
+ */
+#define DRIVER_DS3231_LINK_IIC_INIT(HANDLE, FUC)          (HANDLE)->iic_init = FUC
+
+/**
+ * @brief     link iic_deinit function
+ * @param[in] HANDLE points to a ds3231 handle structure
+ * @param[in] FUC points to an iic_deinit function address
+ * @note      none
+ */
+#define DRIVER_DS3231_LINK_IIC_DEINIT(HANDLE, FUC)        (HANDLE)->iic_deinit = FUC
+
+/**
+ * @brief     link iic_read function
+ * @param[in] HANDLE points to a ds3231 handle structure
+ * @param[in] FUC points to an iic_read function address
+ * @note      none
+ */
+#define DRIVER_DS3231_LINK_IIC_READ(HANDLE, FUC)          (HANDLE)->iic_read = FUC
+
+/**
+ * @brief     link iic_write function
+ * @param[in] HANDLE points to a ds3231 handle structure
+ * @param[in] FUC points to an iic_write function address
+ * @note      none
+ */
+#define DRIVER_DS3231_LINK_IIC_WRITE(HANDLE, FUC)         (HANDLE)->iic_write = FUC
+
+/**
+ * @brief     link delay_ms function
+ * @param[in] HANDLE points to a ds3231 handle structure
+ * @param[in] FUC points to a delay_ms function address
+ * @note      none
+ */
+#define DRIVER_DS3231_LINK_DELAY_MS(HANDLE, FUC)          (HANDLE)->delay_ms = FUC
+
+/**
+ * @brief     link debug_print function
+ * @param[in] HANDLE points to a ds3231 handle structure
+ * @param[in] FUC points to a debug_print function address
+ * @note      none
+ */
+#define DRIVER_DS3231_LINK_DEBUG_PRINT(HANDLE, FUC)       (HANDLE)->debug_print = FUC
+
+/**
+ * @brief     link receive_callback function
+ * @param[in] HANDLE points to a ds3231 handle structure
+ * @param[in] FUC points to a receive_callback function address
+ * @note      none
+ */
+#define DRIVER_DS3231_LINK_RECEIVE_CALLBACK(HANDLE, FUC)  (HANDLE)->receive_callback = FUC
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ds3231_base_driver ds3231 base driver function
+ * @brief    ds3231 base driver modules
+ * @ingroup  ds3231_driver
+ * @{
+ */
+
+/**
+ * @brief      get chip's information
+ * @param[out] *info points to a ds3231 info structure
+ * @return     status code
+ *             - 0 success
+ *             - 2 handle is NULL
+ * @note       none
+ */
+uint8_t ds3231_info(ds3231_info_t *info);
+
+/**
+ * @brief     initialize the chip
+ * @param[in] *handle points to a ds3231 handle structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 iic initialization failed
+ *            - 2 handle is NULL
+ *            - 3 linked functions is NULL
+ * @note      none
+ */
+uint8_t ds3231_init(ds3231_handle_t *handle);
+
+/**
+ * @brief     close the chip
+ * @param[in] *handle points to a ds3231 handle structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 iic deinit failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_deinit(ds3231_handle_t *handle);
+
+/**
+ * @brief     irq handler
+ * @param[in] *handle points to a ds3231 handle structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 run failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_irq_handler(ds3231_handle_t *handle);
+
+/**
+ * @brief     set the current time
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] *t points to a time structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 set time failed
+ *            - 2 handle or time is NULL
+ *            - 3 handle is not initialized
+ *            - 4 time is invalid
+ * @note      none
+ */
+uint8_t ds3231_set_time(ds3231_handle_t *handle, ds3231_time_t *t);
+
+/**
+ * @brief      get the current time
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *t points to a time structure
+ * @return     status code
+ *             - 0 success
+ *             - 1 get time failed
+ *             - 2 handle or time is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_time(ds3231_handle_t *handle, ds3231_time_t *t);
+
+/**
+ * @brief     enable or disable the oscillator
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] enable is a bool value
+ * @return    status code
+ *            - 0 success
+ *            - 1 set oscillator failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_oscillator(ds3231_handle_t *handle, ds3231_bool_t enable);
+
+/**
+ * @brief      get the chip oscillator status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *enable points to a bool value buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get oscillator failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_oscillator(ds3231_handle_t *handle, ds3231_bool_t *enable);
+
+/**
+ * @brief      get the chip status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *status points to a chip status buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get status failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_status(ds3231_handle_t *handle, uint8_t *status);
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ds3231_advance_driver ds3231 advance driver function
+ * @brief    ds3231 advance driver modules
+ * @ingroup  ds3231_driver
+ * @{
+ */
+
+/**
+ * @brief     set the chip pin function
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] pin is the pin's function
+ * @return    status code
+ *            - 0 success
+ *            - 1 set pin failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_pin(ds3231_handle_t *handle, ds3231_pin_t pin);
+
+/**
+ * @brief      get the chip pin function
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *pin points to a pin's function buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get pin failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_pin(ds3231_handle_t *handle, ds3231_pin_t *pin);
+
+/**
+ * @brief     enable or disable the square wave output
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] enable is a bool value
+ * @return    status code
+ *            - 0 success
+ *            - 1 set square wave failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_square_wave(ds3231_handle_t *handle, ds3231_bool_t enable);
+
+/**
+ * @brief      get the square wave output status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *enable points to a bool value buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get square wave failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_square_wave(ds3231_handle_t *handle, ds3231_bool_t *enable);
+
+/**
+ * @brief     enable or disable the 32KHz output
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] enable is a bool value
+ * @return    status code
+ *            - 0 success
+ *            - 1 set 32khz output failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_32khz_output(ds3231_handle_t *handle, ds3231_bool_t enable);
+
+/**
+ * @brief      get the 32KHz output status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *enable points to a bool value buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get 32khz output failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_32khz_output(ds3231_handle_t *handle, ds3231_bool_t *enable);
+
+/**
+ * @brief      get the chip temperature
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *raw points to a raw temperature buffer
+ * @param[out] *s points to a converted temperature buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get temperature failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_temperature(ds3231_handle_t *handle, int16_t *raw, float *s);
+
+/**
+ * @brief     set the chip aging offset
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] offset is time aging offset
+ * @return    status code
+ *            - 0 success
+ *            - 1 set aging offset failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_aging_offset(ds3231_handle_t *handle, int8_t offset);
+
+/**
+ * @brief      get the chip aging offset
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *offset points to a time aging offset buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get aging offset failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_aging_offset(ds3231_handle_t *handle, int8_t *offset);
+
+/**
+ * @brief      convert a aging offset value to a register raw data
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  offset is a converted aging offset value
+ * @param[out] *reg points to a register raw buffer
+ * @return     status code
+ *             - 0 success
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_aging_offset_convert_to_register(ds3231_handle_t *handle, float offset, int8_t *reg);
+
+/**
+ * @brief      convert a register raw data to a converted aging offset data
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  reg is the register raw data
+ * @param[out] *offset points to a converted aging offset buffer
+ * @return     status code
+ *             - 0 success
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_aging_offset_convert_to_data(ds3231_handle_t *handle, int8_t reg, float *offset);
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ds3231_alarm_driver ds3231 alarm driver function
+ * @brief    ds3231 alarm driver modules
+ * @ingroup  ds3231_driver
+ * @{
+ */
+
+/**
+ * @brief     enable or disable the alarm interrupt
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] alarm is the alarm number
+ * @param[in] enable is a bool value
+ * @return    status code
+ *            - 0 success
+ *            - 1 set alarm interrupt failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_alarm_interrupt(ds3231_handle_t *handle, ds3231_alarm_t alarm, ds3231_bool_t enable);
+
+/**
+ * @brief      get the alarm interrupt status
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  alarm is the alarm number
+ * @param[out] *enable points to a bool value buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get alarm interrupt failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_alarm_interrupt(ds3231_handle_t *handle, ds3231_alarm_t alarm, ds3231_bool_t *enable);
+
+/**
+ * @brief     set the alarm1 time
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] *t points to a time structure
+ * @param[in] mode is the alarm1 interrupt mode
+ * @return    status code
+ *            - 0 success
+ *            - 1 set alarm1 failed
+ *            - 2 handle or time is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_alarm1(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm1_mode_t mode);
+
+/**
+ * @brief      get the alarm1 time
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *t points to a time structure
+ * @param[out] *mode points to an alarm1 interrupt mode buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get alarm1 failed
+ *             - 2 handle or time is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_alarm1(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm1_mode_t *mode);
+
+/**
+ * @brief     set the alarm2 time
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] *t points to a time structure
+ * @param[in] mode is the alarm2 interrupt mode
+ * @return    status code
+ *            - 0 success
+ *            - 1 set alarm2 failed
+ *            - 2 handle or time is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_alarm2(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm2_mode_t mode);
+
+/**
+ * @brief      get the alarm2 time
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[out] *t points to a time structure
+ * @param[out] *mode points to an alarm2 interrupt mode buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get alarm2 failed
+ *             - 2 handle or time is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_alarm2(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm2_mode_t *mode);
+
+/**
+ * @brief     clear the alarm flag
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] alarm is the alarm number
+ * @return    status code
+ *            - 0 success
+ *            - 1 alarm clear failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_alarm_clear(ds3231_handle_t *handle, ds3231_alarm_t alarm);
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ds3231_extern_driver ds3231 extern driver function
+ * @brief    ds3231 extern driver modules
+ * @ingroup  ds3231_driver
+ * @{
+ */
+
+/**
+ * @brief     set the chip register
+ * @param[in] *handle points to a ds3231 handle structure
+ * @param[in] reg is the iic register address
+ * @param[in] *buf points to a data buffer
+ * @param[in] len is the data buffer length
+ * @return    status code
+ *            - 0 success
+ *            - 1 write failed
+ *            - 2 handle is NULL
+ *            - 3 handle is not initialized
+ * @note      none
+ */
+uint8_t ds3231_set_reg(ds3231_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len);
+
+/**
+ * @brief      get the chip register
+ * @param[in]  *handle points to a ds3231 handle structure
+ * @param[in]  reg is the iic register address
+ * @param[out] *buf points to a data buffer
+ * @param[in]  len is the data buffer length
+ * @return     status code
+ *             - 0 success
+ *             - 1 read failed
+ *             - 2 handle is NULL
+ *             - 3 handle is not initialized
+ * @note       none
+ */
+uint8_t ds3231_get_reg(ds3231_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Project/Application/driver_ds3231_basic.c b/Project/Application/driver_ds3231_basic.c
new file mode 100644
index 0000000..9912dac
--- /dev/null
+++ b/Project/Application/driver_ds3231_basic.c
@@ -0,0 +1,383 @@
+/**
+ * Copyright (c) 2015 - present LibDriver All rights reserved
+ * 
+ * The MIT License (MIT)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE. 
+ *
+ * @file      driver_ds3231_basic.c
+ * @brief     driver ds3231 basic source file
+ * @version   2.0.0
+ * @author    Shifeng Li
+ * @date      2021-03-15
+ *
+ * <h3>history</h3>
+ * <table>
+ * <tr><th>Date        <th>Version  <th>Author      <th>Description
+ * <tr><td>2021/03/15  <td>2.0      <td>Shifeng Li  <td>format the code
+ * <tr><td>2020/11/30  <td>1.0      <td>Shifeng Li  <td>first upload
+ * </table>
+ */
+
+#include "driver_ds3231_basic.h"
+
+
+static ds3231_handle_t gs_handle;        /**< ds3231 handle */
+static int8_t gs_time_zone = 0;          /**< local zone */
+
+/**
+ * @brief  basic example init
+ * @return status code
+ *         - 0 success
+ *         - 1 init failed
+ * @note   none
+ */
+uint8_t ds3231_basic_init(void)
+{
+    uint8_t res;
+    int8_t reg;
+    
+    /* link functions */
+    DRIVER_DS3231_LINK_INIT(&gs_handle, ds3231_handle_t);
+    DRIVER_DS3231_LINK_IIC_INIT(&gs_handle, ds3231_interface_iic_init);
+    DRIVER_DS3231_LINK_IIC_DEINIT(&gs_handle, ds3231_interface_iic_deinit);
+    DRIVER_DS3231_LINK_IIC_READ(&gs_handle, ds3231_interface_iic_read);
+    DRIVER_DS3231_LINK_IIC_WRITE(&gs_handle, ds3231_interface_iic_write);
+    DRIVER_DS3231_LINK_DELAY_MS(&gs_handle, ds3231_interface_delay_ms);
+    DRIVER_DS3231_LINK_DEBUG_PRINT(&gs_handle, ds3231_interface_debug_print);
+    DRIVER_DS3231_LINK_RECEIVE_CALLBACK(&gs_handle, ds3231_interface_receive_callback);
+
+    /* init ds3231 */
+    res = ds3231_init(&gs_handle);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: init failed.\n");
+        
+        return 1;
+    }
+    
+    /* set oscillator */
+    res = ds3231_set_oscillator(&gs_handle, DS3231_BOOL_TRUE);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: set oscillator failed.\n");
+        (void)ds3231_deinit(&gs_handle);
+        
+        return 1;
+    }
+    
+    /* disable alarm1 */
+    res = ds3231_set_alarm_interrupt(&gs_handle, DS3231_ALARM_1, DS3231_BOOL_FALSE);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: set alarm1 interrupt failed.\n");
+        (void)ds3231_deinit(&gs_handle);
+        
+        return 1;
+    }
+    
+    /* disable alarm2 */
+    res = ds3231_set_alarm_interrupt(&gs_handle, DS3231_ALARM_2, DS3231_BOOL_FALSE);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: set alarm2 interrupt failed.\n");
+        (void)ds3231_deinit(&gs_handle);
+        
+        return 1;
+    }
+    
+    /* set square wave */
+    res = ds3231_set_pin(&gs_handle, DS3231_PIN_SQUARE_WAVE);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: set pin failed.\n");
+        (void)ds3231_deinit(&gs_handle);
+        
+        return 1;
+    }
+    
+    /* disable square wave */
+    res = ds3231_set_square_wave(&gs_handle, DS3231_BOOL_FALSE);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: set square wave failed.\n");
+        (void)ds3231_deinit(&gs_handle);
+        
+        return 1;
+    }
+    
+    /* disable 32khz output */
+    res = ds3231_set_32khz_output(&gs_handle, DS3231_BOOL_FALSE);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: set 32khz output failed.\n");
+        (void)ds3231_deinit(&gs_handle);
+        
+        return 1;
+    }
+    
+    /* convert to register */
+    res = ds3231_aging_offset_convert_to_register(&gs_handle, DS3231_BASIC_DEFAULT_AGING_OFFSET, (int8_t *)&reg);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: convert to register failed.\n");
+        (void)ds3231_deinit(&gs_handle);
+        
+        return 1;
+    }
+    
+    /* set aging offset */
+    res = ds3231_set_aging_offset(&gs_handle, reg);
+    if (res != 0)
+    {
+        ds3231_interface_debug_print("ds3231: set aging offset failed.\n");
+        (void)ds3231_deinit(&gs_handle);
+        
+        return 1;
+    }
+    
+    return 0;
+}
+
+/**
+ * @brief  basic example deinit
+ * @return status code
+ *         - 0 success
+ *         - 1 deinit failed
+ * @note   none
+ */
+uint8_t ds3231_basic_deinit(void)
+{
+    if (ds3231_deinit(&gs_handle) != 0)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+/**
+ * @brief     basic example set the time
+ * @param[in] *t points to a time structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 set time failed
+ * @note      none
+ */
+uint8_t ds3231_basic_set_time(ds3231_time_t *t)
+{
+    /* set time */
+    if (ds3231_set_time(&gs_handle, t) != 0)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+/**
+ * @brief     basic example set the time by a unix timestamp
+ * @param[in] timestamp is a unix timestamp
+ * @return    status code
+ *            - 0 success
+ *            - 1 set timestamp failed
+ * @note      none
+ */
+uint8_t ds3231_basic_set_timestamp(time_t timestamp)
+{
+    ds3231_time_t t;
+    struct tm *timeptr;
+    
+    /* convert times */
+    timestamp += (time_t)(gs_time_zone * 3600);
+    timeptr = localtime(&timestamp);
+    t.am_pm = DS3231_AM;
+    t.date = (uint8_t)timeptr->tm_mday;
+    t.format = DS3231_FORMAT_24H;
+    t.hour = (uint8_t)timeptr->tm_hour;
+    t.minute = (uint8_t)timeptr->tm_min;
+    t.month = (uint8_t)timeptr->tm_mon + 1;
+    t.second = (uint8_t)timeptr->tm_sec;
+    if (timeptr->tm_wday == 0)
+    {
+        t.week  = 7;
+    }
+    else
+    {
+        t.week = (uint8_t)timeptr->tm_wday;
+    }
+    t.year = (uint16_t)(timeptr->tm_year + 1900);
+    
+    /* set time */
+    if (ds3231_set_time(&gs_handle, &t) != 0)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+/**
+ * @brief     basic example set the local time zone
+ * @param[in] zone is the local time zone
+ * @return    status code
+ *            - 0 success
+ * @note      none
+ */
+uint8_t ds3231_basic_set_timestamp_time_zone(int8_t zone)
+{
+    gs_time_zone = zone;
+    
+    return 0;
+}
+
+/**
+ * @brief      basic example get the time
+ * @param[out] *t points to a time structure
+ * @return     status code
+ *             - 0 success
+ *             - 1 get time failed
+ * @note       none
+ */
+uint8_t ds3231_basic_get_time(ds3231_time_t *t)
+{
+    /* get time */
+    if (ds3231_get_time(&gs_handle, t) != 0)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+/**
+ * @brief      basic example get the time in a unix timestamp
+ * @param[out] *timestamp points to a unix timestamp buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get timestamp failed
+ * @note       none
+ */
+uint8_t ds3231_basic_get_timestamp(time_t *timestamp)
+{
+    ds3231_time_t t;
+    struct tm timeptr;
+    
+    /* get time */
+    if (ds3231_get_time(&gs_handle, &t) != 0)
+    {
+        return 1;
+    }
+    timeptr.tm_year = t.year - 1900;
+    timeptr.tm_mon = t.month - 1;
+    timeptr.tm_wday = t.week; 
+    timeptr.tm_mday = t.date;
+    if (t.format == DS3231_FORMAT_24H)
+    {
+        timeptr.tm_hour = t.hour;
+    }
+    else
+    {
+        timeptr.tm_hour = t.hour % 12 + t.am_pm * 12;
+    }
+    timeptr.tm_min = t.minute;
+    timeptr.tm_sec = t.second;
+    
+    /* make time */
+    *timestamp = mktime(&timeptr) - gs_time_zone * 3600;
+    
+    return 0;
+}
+
+/**
+ * @brief      basic example get the local time zone
+ * @param[out] *zone points to a local time zone buffer
+ * @return     status code
+ *             - 0 success
+ * @note       none
+ */
+uint8_t ds3231_basic_get_timestamp_time_zone(int8_t *zone)
+{
+    *zone = gs_time_zone;
+    
+    return 0;
+}
+
+/**
+ * @brief      basic example get the current temperature
+ * @param[out] *raw points to a raw temperature buffer
+ * @param[out] *s points to a converted temperature buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 read temperature failed
+ * @note       none
+ */
+uint8_t ds3231_basic_get_temperature(int16_t *raw, float *s)
+{
+    /* get temperature */
+    if (ds3231_get_temperature(&gs_handle, raw, s) != 0)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+/**
+ * @brief      basic example get the ascii time
+ * @param[out] *buf points to an ascii buffer
+ * @param[in]  len is the data length
+ * @return     status code
+ *             - 0 success
+ *             - 1 read failed
+ * @note       none
+ */
+uint8_t ds3231_basic_get_ascii_time(char *buf, uint8_t len)
+{
+    ds3231_time_t t;
+    
+    /* get time */
+    if (ds3231_get_time(&gs_handle, &t) != 0)
+    {
+        return 1;
+    }
+    
+    if (t.format == DS3231_FORMAT_24H)
+    {
+        (void)snprintf(buf, len, "%04d-%02d-%02d %02d:%02d:%02d %d.\n", t.year, t.month, t.date, t.hour, t.minute, t.second, t.week);
+    }
+    else
+    {
+        (void)snprintf(buf, len, "%04d-%02d-%02d %s %02d:%02d:%02d %d.\n", t.year, t.month, t.date, (t.am_pm == DS3231_AM) ? "AM" : "PM",
+                       t.hour, t.minute, t.second, t.week
+                      );
+    }
+    
+    return 0;
+}
diff --git a/Project/Application/driver_ds3231_basic.h b/Project/Application/driver_ds3231_basic.h
new file mode 100644
index 0000000..d781508
--- /dev/null
+++ b/Project/Application/driver_ds3231_basic.h
@@ -0,0 +1,166 @@
+/**
+ * Copyright (c) 2015 - present LibDriver All rights reserved
+ * 
+ * The MIT License (MIT)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE. 
+ *
+ * @file      driver_ds3231_basic.h
+ * @brief     driver ds3231 basic header file
+ * @version   2.0.0
+ * @author    Shifeng Li
+ * @date      2021-03-15
+ *
+ * <h3>history</h3>
+ * <table>
+ * <tr><th>Date        <th>Version  <th>Author      <th>Description
+ * <tr><td>2021/03/15  <td>2.0      <td>Shifeng Li  <td>format the code
+ * <tr><td>2020/11/30  <td>1.0      <td>Shifeng Li  <td>first upload
+ * </table>
+ */
+  
+#ifndef DRIVER_DS3231_BASIC_H
+#define DRIVER_DS3231_BASIC_H
+
+#include "driver_ds3231_interface.h"
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/**
+ * @defgroup ds3231_example_driver ds3231 example driver function
+ * @brief    ds3231 example driver modules
+ * @ingroup  ds3231_driver
+ * @{
+ */
+
+/**
+ * @brief ds3231 basic example default definition
+ */
+#define DS3231_BASIC_DEFAULT_AGING_OFFSET        0        /**< 0 offset */
+
+/**
+ * @brief  basic example init
+ * @return status code
+ *         - 0 success
+ *         - 1 init failed
+ * @note   none
+ */
+uint8_t ds3231_basic_init(void);
+
+/**
+ * @brief  basic example deinit
+ * @return status code
+ *         - 0 success
+ *         - 1 deinit failed
+ * @note   none
+ */
+uint8_t ds3231_basic_deinit(void);
+
+/**
+ * @brief     basic example set the time
+ * @param[in] *t points to a time structure
+ * @return    status code
+ *            - 0 success
+ *            - 1 set time failed
+ * @note      none
+ */
+uint8_t ds3231_basic_set_time(ds3231_time_t *t);
+
+/**
+ * @brief      basic example get the time
+ * @param[out] *t points to a time structure
+ * @return     status code
+ *             - 0 success
+ *             - 1 get time failed
+ * @note       none
+ */
+uint8_t ds3231_basic_get_time(ds3231_time_t *t);
+
+/**
+ * @brief     basic example set the time by a unix timestamp
+ * @param[in] timestamp is a unix timestamp
+ * @return    status code
+ *            - 0 success
+ *            - 1 set timestamp failed
+ * @note      none
+ */
+uint8_t ds3231_basic_set_timestamp(time_t timestamp);
+
+/**
+ * @brief      basic example get the time in a unix timestamp
+ * @param[out] *timestamp points to a unix timestamp buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 get timestamp failed
+ * @note       none
+ */
+uint8_t ds3231_basic_get_timestamp(time_t *timestamp);
+
+/**
+ * @brief     basic example set the local time zone
+ * @param[in] zone is the local time zone
+ * @return    status code
+ *            - 0 success
+ * @note      none
+ */
+uint8_t ds3231_basic_set_timestamp_time_zone(int8_t zone);
+
+/**
+ * @brief      basic example get the local time zone
+ * @param[out] *zone points to a local time zone buffer
+ * @return     status code
+ *             - 0 success
+ * @note       none
+ */
+uint8_t ds3231_basic_get_timestamp_time_zone(int8_t *zone);
+
+/**
+ * @brief      basic example get the current temperature
+ * @param[out] *raw points to a raw temperature buffer
+ * @param[out] *s points to a converted temperature buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 read temperature failed
+ * @note       none
+ */
+uint8_t ds3231_basic_get_temperature(int16_t *raw, float *s);
+
+/**
+ * @brief      basic example get the ascii time
+ * @param[out] *buf points to an ascii buffer
+ * @param[in]  len is the data length
+ * @return     status code
+ *             - 0 success
+ *             - 1 read failed
+ * @note       none
+ */
+uint8_t ds3231_basic_get_ascii_time(char *buf, uint8_t len);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Project/Application/driver_ds3231_interface.h b/Project/Application/driver_ds3231_interface.h
new file mode 100644
index 0000000..743e202
--- /dev/null
+++ b/Project/Application/driver_ds3231_interface.h
@@ -0,0 +1,127 @@
+/**
+ * Copyright (c) 2015 - present LibDriver All rights reserved
+ * 
+ * The MIT License (MIT)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE. 
+ *
+ * @file      driver_ds3231_interface.h
+ * @brief     driver ds3231 interface header file
+ * @version   2.0.0
+ * @author    Shifeng Li
+ * @date      2021-03-15
+ *
+ * <h3>history</h3>
+ * <table>
+ * <tr><th>Date        <th>Version  <th>Author      <th>Description
+ * <tr><td>2021/03/15  <td>2.0      <td>Shifeng Li  <td>format the code
+ * <tr><td>2020/11/30  <td>1.0      <td>Shifeng Li  <td>first upload
+ * </table>
+ */
+
+#ifndef DRIVER_DS3231_INTERFACE_H
+#define DRIVER_DS3231_INTERFACE_H
+
+#include "driver_ds3231.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/**
+ * @defgroup ds3231_interface_driver ds3231 interface driver function
+ * @brief    ds3231 interface driver modules
+ * @ingroup  ds3231_driver
+ * @{
+ */
+
+/**
+ * @brief  interface iic bus init
+ * @return status code
+ *         - 0 success
+ *         - 1 iic init failed
+ * @note   none
+ */
+uint8_t ds3231_interface_iic_init(void);
+
+/**
+ * @brief  interface iic bus deinit
+ * @return status code
+ *         - 0 success
+ *         - 1 iic deinit failed
+ * @note   none
+ */
+uint8_t ds3231_interface_iic_deinit(void);
+
+/**
+ * @brief      interface iic bus read
+ * @param[in]  addr is the iic device write address
+ * @param[in]  reg is the iic register address
+ * @param[out] *buf points to a data buffer
+ * @param[in]  len is the length of the data buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 read failed
+ * @note       none
+ */
+uint8_t ds3231_interface_iic_read(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len);
+
+/**
+ * @brief     interface iic bus write
+ * @param[in] addr is the iic device write address
+ * @param[in] reg is the iic register address
+ * @param[in] *buf points to a data buffer
+ * @param[in] len is the length of the data buffer
+ * @return    status code
+ *            - 0 success
+ *            - 1 write failed
+ * @note      none
+ */
+uint8_t ds3231_interface_iic_write(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len);
+
+/**
+ * @brief     interface delay ms
+ * @param[in] ms
+ * @note      none
+ */
+void ds3231_interface_delay_ms(uint32_t ms);
+
+/**
+ * @brief     interface print format data
+ * @param[in] fmt is the format data
+ * @note      none
+ */
+void ds3231_interface_debug_print(const char *const fmt, ...);
+
+/**
+ * @brief     interface receive callback
+ * @param[in] type is the interrupt type
+ * @note      none
+ */
+void ds3231_interface_receive_callback(uint8_t type);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Project/Application/driver_ds3231_interface_template.c b/Project/Application/driver_ds3231_interface_template.c
new file mode 100644
index 0000000..efe8b29
--- /dev/null
+++ b/Project/Application/driver_ds3231_interface_template.c
@@ -0,0 +1,162 @@
+/**
+ * Copyright (c) 2015 - present LibDriver All rights reserved
+ * 
+ * The MIT License (MIT)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE. 
+ *
+ * @file      driver_ds3231_interface_template.c
+ * @brief     driver ds3231 interface template source file
+ * @version   2.0.0
+ * @author    Shifeng Li
+ * @date      2021-03-15
+ *
+ * <h3>history</h3>
+ * <table>
+ * <tr><th>Date        <th>Version  <th>Author      <th>Description
+ * <tr><td>2021/03/15  <td>2.0      <td>Shifeng Li  <td>format the code
+ * <tr><td>2020/11/30  <td>1.0      <td>Shifeng Li  <td>first upload
+ * </table>
+ */
+
+#include "driver_ds3231_interface.h"
+#include "gpio_i2c.h"
+#include "stdarg.h"
+
+/**
+ * @brief  interface iic bus init
+ * @return status code
+ *         - 0 success
+ *         - 1 iic init failed
+ * @note   none
+ */
+uint8_t ds3231_interface_iic_init(void)
+{
+    return 0;
+}
+
+/**
+ * @brief  interface iic bus deinit
+ * @return status code
+ *         - 0 success
+ *         - 1 iic deinit failed
+ * @note   none
+ */
+uint8_t ds3231_interface_iic_deinit(void)
+{
+    return 0;
+}
+
+/**
+ * @brief      interface iic bus read
+ * @param[in]  addr is the iic device write address
+ * @param[in]  reg is the iic register address
+ * @param[out] *buf points to a data buffer
+ * @param[in]  len is the length of the data buffer
+ * @return     status code
+ *             - 0 success
+ *             - 1 read failed
+ * @note       none
+ */
+uint8_t ds3231_interface_iic_read(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len)
+{
+    I2C2_Write(addr, &reg, 1);
+    I2C2_Read(addr, buf, len);
+    return 0;
+}
+
+/**
+ * @brief     interface iic bus write
+ * @param[in] addr is the iic device write address
+ * @param[in] reg is the iic register address
+ * @param[in] *buf points to a data buffer
+ * @param[in] len is the length of the data buffer
+ * @return    status code
+ *            - 0 success
+ *            - 1 write failed
+ * @note      none
+ */
+uint8_t ds3231_interface_iic_write(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len)
+{
+    uint8_t WriteData[20];
+    WriteData[0] = reg;
+    memcpy(&WriteData[1], buf, len);
+    len += 1;
+    I2C2_Write(addr, &WriteData[0], len);
+    return 0;
+}
+
+/**
+ * @brief     interface delay ms
+ * @param[in] ms
+ * @note      none
+ */
+void ds3231_interface_delay_ms(uint32_t ms)
+{
+    Delay_ms(ms);
+}
+
+/**
+ * @brief     interface print format data
+ * @param[in] fmt is the format data
+ * @note      none
+ */
+void ds3231_interface_debug_print(const char *const fmt, ...)
+{
+    char str[256];
+    uint16_t len;
+    va_list args;
+    return;
+    
+    memset((char *)str, 0, sizeof(char) * 256); 
+    va_start(args, fmt);
+    vsnprintf((char *)str, 255, (char const *)fmt, args);
+    va_end(args);
+    
+    len = strlen((char *)str);
+    //(void)Uart1_TransmitData((uint8_t *)str, len);
+}
+
+/**
+ * @brief     interface receive callback
+ * @param[in] type is the interrupt type
+ * @note      none
+ */
+void ds3231_interface_receive_callback(uint8_t type)
+{
+    switch (type)
+    {
+        case DS3231_STATUS_ALARM_2 :
+        {
+            ds3231_interface_debug_print("ds3231: irq alarm2.\n");
+            
+            break;
+        }
+        case DS3231_STATUS_ALARM_1 :
+        {
+            ds3231_interface_debug_print("ds3231: irq alarm1.\n");
+            
+            break;
+        }
+        default :
+        {
+            break;
+        }
+    }
+}
diff --git a/Project/Application/eeprom.c b/Project/Application/eeprom.c
new file mode 100644
index 0000000..76e37c3
--- /dev/null
+++ b/Project/Application/eeprom.c
@@ -0,0 +1,206 @@
+#include "eeprom.h"
+
+
+
+
+
+typedef union _eeprom_info
+{    
+    struct 
+    {
+        uint8_t isSave;
+        uint8_t Mode;
+        uint8_t Reserved[SECTOR_SIZE_BYTE - 3];
+        uint8_t CheckSum;
+    }eeprom_data;
+    uint8_t eeprom_buffer[SECTOR_SIZE_BYTE];
+}EEPROM_INFO;
+
+
+static EEPROM_INFO eeprom_info;
+
+
+
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         FlashMem_Do_PageWt
+ * @param[in]     tPageAddr
+ * @param[in]     tBuf
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void FlashMem_Do_PageWt( uint32_t tPageAddr, uint32_t* tBuf )
+{
+   uint32_t    UserID_Buf;
+
+   UserID_Buf = 0x4F17DC86;
+   HAL_FMC_PageWrite( UserID_Buf, tPageAddr, tBuf );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         FlashMem_Do_PageEr
+ * @param[in]     tPageAddr
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void FlashMem_Do_PageEr( uint32_t tPageAddr )
+{
+   uint32_t    UserID_Buf;
+
+   UserID_Buf = 0xA901358F;
+   HAL_FMC_PageErase( UserID_Buf, tPageAddr );
+}
+
+void FlashMEM_Clock_Initialization(void)
+{
+    // enable peripheral clock
+    HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_FMCLKE, PPxCLKE_Enable );    
+    // init crc
+    HAL_CRC_Init();
+}
+
+
+
+bool EEPROM_Read_Mode(uint8_t* pMode)
+{
+    uint8_t i;
+    uint16_t checksum_init = 0x5AA5;
+    uint16_t checksum_result;
+
+    __disable_irq();
+    memcpy(&eeprom_info.eeprom_buffer[0], (uint32_t *)CONFIG_ADDRESS, SECTOR_SIZE_BYTE);
+    __enable_irq();
+
+    if(eeprom_info.eeprom_data.isSave != true)
+    {
+        return false;
+    }
+
+    // CRC Block Calculation
+    CRC->INIT = checksum_init;
+    CRC->CR = 0
+            | MODS_UserMode  // Set User Mode
+            | CRC_RLTCLR     // Initialize CRC_RLT Register With CRC_INIT
+            | CRC_16           // Polynomial Selection bit : CRC-16
+            | CRC_NOINC      // Address Not Auto Increment
+            ;
+    
+    CRCRun();
+    for(i = 0 ; i < (SECTOR_SIZE_BYTE-1) ; i++)
+    {
+        CRC->IN = eeprom_info.eeprom_buffer[i];
+    }
+    CRCStop();
+    checksum_result = CRC->RLT;
+
+    if((checksum_result & 0xFF) == eeprom_info.eeprom_data.CheckSum)
+    {
+        *pMode = eeprom_info.eeprom_data.Mode;
+        return true;
+    }
+    return false;
+}
+
+
+bool EEPROM_Write_Mode(uint8_t Mode)
+{
+    uint8_t i;
+    uint16_t checksum_init = 0x5AA5;
+    uint16_t checksum_result;
+
+    if(eeprom_info.eeprom_data.isSave == true)
+    {
+        if(eeprom_info.eeprom_data.Mode == Mode)
+            return true;
+    }    
+
+    memset(&eeprom_info.eeprom_buffer[0], 0, SECTOR_SIZE_BYTE);
+    eeprom_info.eeprom_data.isSave = true;
+    eeprom_info.eeprom_data.Mode = Mode;
+
+    // CRC Block Calculation
+    CRC->INIT = checksum_init;
+    CRC->CR = 0
+            | MODS_UserMode  // Set User Mode
+            | CRC_RLTCLR     // Initialize CRC_RLT Register With CRC_INIT
+            | CRC_16           // Polynomial Selection bit : CRC-16
+            | CRC_NOINC      // Address Not Auto Increment
+            ;
+    
+    CRCRun();
+    for(i = 0 ; i < (SECTOR_SIZE_BYTE-1) ; i++)
+    {
+        CRC->IN = eeprom_info.eeprom_buffer[i];
+    }
+    CRCStop();
+    checksum_result = CRC->RLT;
+
+
+
+    eeprom_info.eeprom_data.CheckSum = checksum_result & 0xFF;
+
+
+    __disable_irq();
+    FlashMem_Do_PageEr(CONFIG_ADDRESS);
+    FlashMem_Do_PageWt(CONFIG_ADDRESS, (uint32_t *)&eeprom_info.eeprom_buffer[0]);
+    __enable_irq();
+
+    return true;
+}
+
+
+
+#if 0
+
+
+void EEPROM_Read_Setting_Data(void)
+{     
+    #if 0
+    __disable_irq();
+    memcpy(&Save_control_Info, (uint32_t *)CONFIG_ADDRESS, SECTOR_SIZE_BYTE);
+    __enable_irq();
+    
+    if(Save_control_Info.SaveFlag != EEPROM_SAVE_CHECK_FLAG_DATA)
+    {
+        Save_control_Info.SaveFlag              = EEPROM_SAVE_CHECK_FLAG_DATA;          // 1
+        Save_control_Info.SaveActionMode        = ACTION_MODE_ACTION_AUTO_1;            // 2    
+        Save_control_Info.isPowerOnReservation  = FALSE;                                // 3
+        Save_control_Info.isPowerOnSaturDay     = FALSE;                                // 4        
+        Save_control_Info.PowerOn_Hour          = 0;                                    // 5
+        Save_control_Info.PowerOn_Min           = 0;                                    // 6
+
+        Save_control_Info.isPowerOffReservation = FALSE;                                // 7
+        Save_control_Info.PowerOff_Hour         = 0;                                    // 8
+        Save_control_Info.PowerOff_Min          = 0;                                    // 9
+        Save_control_Info.FanActionTime_1       = 0;                                    // 10
+        Save_control_Info.FanActionTime_2       = 0;                                    // 11
+    }
+#endif    
+    
+}
+
+void EEPROM_Write_Seting_Data(void)
+{
+#if 0    
+    if(Control_Info.isEepromSave == TRUE)
+    {
+        Control_Info.isEepromSave = FALSE;
+        __disable_irq();
+        FlashMem_Do_PageEr(CONFIG_ADDRESS);
+        FlashMem_Do_PageWt(CONFIG_ADDRESS, (uint32_t *)&Save_control_Info);
+        __enable_irq();
+    }
+#endif    
+}
+
+
+#endif
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Project/Application/eeprom.h b/Project/Application/eeprom.h
new file mode 100644
index 0000000..e99ac8d
--- /dev/null
+++ b/Project/Application/eeprom.h
@@ -0,0 +1,17 @@
+/** \file eeprom.h */ 
+#if !defined(EEPROM_H__702B16C6_4AC7_410F_BD32_D5794BFC24E8__INCLUDED_)
+#define EEPROM_H__702B16C6_4AC7_410F_BD32_D5794BFC24E8__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+#define CONFIG_ADDRESS      0x1FFFF400
+
+
+void FlashMEM_Clock_Initialization(void);
+
+bool EEPROM_Read_Mode(uint8_t* pMode);
+bool EEPROM_Write_Mode(uint8_t Mode);
+
+
+#endif
diff --git a/Project/Application/gpio_i2c.c b/Project/Application/gpio_i2c.c
new file mode 100644
index 0000000..32dc8b6
--- /dev/null
+++ b/Project/Application/gpio_i2c.c
@@ -0,0 +1,436 @@
+#include "gpio_i2c.h"
+
+
+
+void Delay_I2C_Delay(uint32_t nDelay)
+{
+    uint32_t i;
+    for(i = 0 ; i < nDelay ; i++)
+    {
+        asm("NOP");
+    }
+    
+}
+
+
+void GPIO_I2C0_Initialization(void)
+{
+    // configure I2C1 SDA as a Output Mode
+    HAL_GPIO_ConfigOutput((Pn_Type*)I2C0_SDA_PORT, I2C0_SDA_PIN, PUSH_PULL_OUTPUT );
+    HAL_GPIO_ConfigPullup((Pn_Type*)I2C0_SDA_PORT, I2C0_SDA_PIN, PUPDx_EnablePU );
+    
+    // configure I2C1 SCL as a Output Mode
+    HAL_GPIO_ConfigOutput((Pn_Type*)I2C0_SCL_PORT, I2C0_SCL_PIN, PUSH_PULL_OUTPUT );
+    HAL_GPIO_ConfigPullup((Pn_Type*)I2C0_SCL_PORT, I2C0_SCL_PIN, PUPDx_EnablePU );
+
+	I2C0_SDA_HIGH;
+	I2C0_SCL_HIGH;
+}
+
+void GPIO_I2C0_Start(void)
+{
+    I2C0_SDA_OUTPUT;	    	
+	Delay_I2C_Delay(I2C0_DELAY);
+	I2C0_SDA_HIGH;
+	I2C0_SCL_HIGH;
+	Delay_I2C_Delay(I2C0_DELAY);
+	I2C0_SDA_LOW;
+	Delay_I2C_Delay(I2C0_DELAY);
+	I2C0_SCL_LOW;
+	Delay_I2C_Delay(I2C0_DELAY);
+}
+
+void GPIO_I2C0_Stop(void)
+{
+    I2C0_SDA_LOW;
+	I2C0_SDA_OUTPUT;
+	I2C0_SDA_LOW;
+	Delay_I2C_Delay(I2C0_DELAY);
+	I2C0_SCL_HIGH;
+	Delay_I2C_Delay(I2C0_DELAY);
+	I2C0_SDA_HIGH;	
+}
+
+uint8_t GPIO_I2C0_Write(uint8_t data)
+{
+    uint8_t Ret;
+    
+    unsigned char i;
+	I2C0_SDA_OUTPUT;
+
+	for(i = 0 ; i < 8 ; i++)
+	{
+		if((data & 0x80)==0x80)
+		{
+			I2C0_SDA_HIGH;
+		}
+		else
+		{
+			I2C0_SDA_LOW;
+		}
+		data<<=1;
+		Delay_I2C_Delay(I2C0_DELAY);
+		I2C0_SCL_HIGH;
+		Delay_I2C_Delay(I2C0_DELAY);
+		I2C0_SCL_LOW;		
+		Delay_I2C_Delay(I2C0_DELAY);
+	}
+	I2C0_SDA_INPUTS;	
+	I2C0_SCL_HIGH;
+	Delay_I2C_Delay(I2C0_DELAY);
+    Ret = I2C0_SDA_READ;
+	Delay_I2C_Delay(I2C0_DELAY);
+	I2C0_SCL_LOW;	
+
+    return Ret;
+}
+
+uint8_t GPIO_I2C0_Read(uint8_t rs)
+{
+    uint8_t i;
+    uint8_t Ret = 0x00;       
+    
+	I2C0_SDA_INPUTS;	
+
+	for(i = 0 ; i < 8 ; i++)
+    {
+		I2C0_SCL_HIGH;  
+		Delay_I2C_Delay(I2C0_DELAY);      
+		Ret <<= 1;        
+		if(I2C0_SDA_READ != 0)
+		{
+			Ret |= 0x01;
+		}
+		I2C0_SCL_LOW;        
+		Delay_I2C_Delay(I2C0_DELAY);
+	}
+
+	I2C0_SDA_OUTPUT;
+
+	if(rs == I2C_ACK)
+ 	{
+		I2C0_SDA_LOW;
+ 	}
+	else
+	{
+		I2C0_SDA_HIGH;
+	}
+
+	I2C0_SCL_HIGH;
+	Delay_I2C_Delay(I2C0_DELAY);
+	I2C0_SCL_LOW;
+	Delay_I2C_Delay(I2C0_DELAY);
+    return Ret;
+}
+
+
+uint8_t I2C0_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize)
+{
+	uint16_t i;	
+	GPIO_I2C0_Start();
+	GPIO_I2C0_Write(Address << 1);
+	for(i = 0 ; i < WriteDataSize ; i++)
+	{
+		GPIO_I2C0_Write(pWriteData[i]);
+	}
+	GPIO_I2C0_Stop(); 
+	return 0;
+}
+
+uint8_t I2C0_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize)
+{
+	uint16_t i;
+	GPIO_I2C0_Start();
+	GPIO_I2C0_Write((Address << 1) | 1);
+	for(i = 0 ; i < ReadDataSize-1 ; i++)
+	{		
+		pReadData[i] = GPIO_I2C0_Read(I2C_ACK);
+	}
+	pReadData[i] = GPIO_I2C0_Read(I2C_NACK);
+	GPIO_I2C0_Stop(); 
+	return 0;
+}
+
+
+/////////////////////////////////////////////////////////////////////////////
+
+
+void GPIO_I2C1_Initialization(void)
+{
+    // configure I2C1 SDA as a Output Mode
+    HAL_GPIO_ConfigOutput((Pn_Type*)I2C1_SDA_PORT, I2C1_SDA_PIN, PUSH_PULL_OUTPUT );
+    HAL_GPIO_ConfigPullup((Pn_Type*)I2C1_SDA_PORT, I2C1_SDA_PIN, PUPDx_EnablePU );
+    
+    // configure I2C1 SCL as a Output Mode
+    HAL_GPIO_ConfigOutput((Pn_Type*)I2C1_SCL_PORT, I2C1_SCL_PIN, PUSH_PULL_OUTPUT );
+    HAL_GPIO_ConfigPullup((Pn_Type*)I2C1_SCL_PORT, I2C1_SCL_PIN, PUPDx_EnablePU );
+
+	I2C1_SDA_HIGH;
+	I2C1_SCL_HIGH;
+}
+
+void GPIO_I2C1_Start(void)
+{
+    I2C1_SDA_OUTPUT;	    	
+	Delay_I2C_Delay(I2C1_DELAY);
+	I2C1_SDA_HIGH;
+	I2C1_SCL_HIGH;
+	Delay_I2C_Delay(I2C1_DELAY);
+	I2C1_SDA_LOW;
+	Delay_I2C_Delay(I2C1_DELAY);
+	I2C1_SCL_LOW;
+	Delay_I2C_Delay(I2C1_DELAY);
+}
+
+void GPIO_I2C1_Stop(void)
+{
+    I2C1_SDA_LOW;
+	I2C1_SDA_OUTPUT;
+	I2C1_SDA_LOW;
+	Delay_I2C_Delay(I2C1_DELAY);
+	I2C1_SCL_HIGH;
+	Delay_I2C_Delay(I2C1_DELAY);
+	I2C1_SDA_HIGH;	
+}
+
+uint8_t GPIO_I2C1_Write(uint8_t data)
+{
+    uint8_t Ret;
+    
+    unsigned char i;
+	I2C1_SDA_OUTPUT;
+
+	for(i = 0 ; i < 8 ; i++)
+	{
+		if((data & 0x80)==0x80)
+		{
+			I2C1_SDA_HIGH;
+		}
+		else
+		{
+			I2C1_SDA_LOW;
+		}
+		data<<=1;
+		Delay_I2C_Delay(I2C1_DELAY);
+		I2C1_SCL_HIGH;
+		Delay_I2C_Delay(I2C1_DELAY);
+		I2C1_SCL_LOW;		
+		Delay_I2C_Delay(I2C1_DELAY);
+	}
+	I2C1_SDA_INPUTS;	
+	I2C1_SCL_HIGH;
+	Delay_I2C_Delay(I2C1_DELAY);
+    Ret = I2C1_SDA_READ;
+	Delay_I2C_Delay(I2C1_DELAY);
+	I2C1_SCL_LOW;	
+
+    return Ret;
+}
+
+uint8_t GPIO_I2C1_Read(uint8_t rs)
+{
+    uint8_t i;
+    uint8_t Ret = 0x00;       
+    
+	I2C1_SDA_INPUTS;	
+
+	for(i = 0 ; i < 8 ; i++)
+    {
+		I2C1_SCL_HIGH;  
+		Delay_I2C_Delay(I2C1_DELAY);      
+		Ret <<= 1;        
+		if(I2C1_SDA_READ != 0)
+		{
+			Ret |= 0x01;
+		}
+		I2C1_SCL_LOW;        
+		Delay_I2C_Delay(I2C1_DELAY);
+	}
+
+	I2C1_SDA_OUTPUT;
+
+	if(rs == I2C_ACK)
+ 	{
+		I2C1_SDA_LOW;
+ 	}
+	else
+	{
+		I2C1_SDA_HIGH;
+	}
+
+	I2C1_SCL_HIGH;
+	Delay_I2C_Delay(I2C1_DELAY);
+	I2C1_SCL_LOW;
+	Delay_I2C_Delay(I2C1_DELAY);
+    return Ret;
+}
+
+
+uint8_t I2C1_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize)
+{
+	uint16_t i;	
+	GPIO_I2C1_Start();
+	GPIO_I2C1_Write(Address << 1);
+	for(i = 0 ; i < WriteDataSize ; i++)
+	{
+		GPIO_I2C1_Write(pWriteData[i]);
+	}
+	GPIO_I2C1_Stop(); 
+	return 0;
+}
+
+uint8_t I2C1_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize)
+{
+	uint16_t i;
+	GPIO_I2C1_Start();
+	GPIO_I2C1_Write((Address << 1) | 1);
+	for(i = 0 ; i < ReadDataSize-1 ; i++)
+	{		
+		pReadData[i] = GPIO_I2C1_Read(I2C_ACK);
+	}
+	pReadData[i] = GPIO_I2C1_Read(I2C_NACK);
+	GPIO_I2C1_Stop(); 
+	return 0;
+}
+
+
+/////////////////////////////////////////////////////////////////////////////
+
+
+void GPIO_I2C2_Initialization(void)
+{
+    // configure I2C1 SDA as a Output Mode
+    HAL_GPIO_ConfigOutput((Pn_Type*)I2C2_SDA_PORT, I2C2_SDA_PIN, PUSH_PULL_OUTPUT );
+    HAL_GPIO_ConfigPullup((Pn_Type*)I2C2_SDA_PORT, I2C2_SDA_PIN, PUPDx_EnablePU );
+    
+    // configure I2C2 SCL as a Output Mode
+    HAL_GPIO_ConfigOutput((Pn_Type*)I2C2_SCL_PORT, I2C2_SCL_PIN, PUSH_PULL_OUTPUT );
+    HAL_GPIO_ConfigPullup((Pn_Type*)I2C2_SCL_PORT, I2C2_SCL_PIN, PUPDx_EnablePU );
+
+	I2C2_SDA_HIGH;
+	I2C2_SCL_HIGH;
+}
+
+void GPIO_I2C2_Start(void)
+{
+    I2C2_SDA_OUTPUT;	    	
+	Delay_I2C_Delay(I2C2_DELAY);
+	I2C2_SDA_HIGH;
+	I2C2_SCL_HIGH;
+	Delay_I2C_Delay(I2C2_DELAY);
+	I2C2_SDA_LOW;
+	Delay_I2C_Delay(I2C2_DELAY);
+	I2C2_SCL_LOW;
+	Delay_I2C_Delay(I2C2_DELAY);
+}
+
+void GPIO_I2C2_Stop(void)
+{
+    I2C2_SDA_LOW;
+	I2C2_SDA_OUTPUT;
+	I2C2_SDA_LOW;
+	Delay_I2C_Delay(I2C2_DELAY);
+	I2C2_SCL_HIGH;
+	Delay_I2C_Delay(I2C2_DELAY);
+	I2C2_SDA_HIGH;	
+}
+
+uint8_t GPIO_I2C2_Write(uint8_t data)
+{
+    uint8_t Ret;
+    
+    unsigned char i;
+	I2C2_SDA_OUTPUT;
+
+	for(i = 0 ; i < 8 ; i++)
+	{
+		if((data & 0x80)==0x80)
+		{
+			I2C2_SDA_HIGH;
+		}
+		else
+		{
+			I2C2_SDA_LOW;
+		}
+		data<<=1;
+		Delay_I2C_Delay(I2C2_DELAY);
+		I2C2_SCL_HIGH;
+		Delay_I2C_Delay(I2C2_DELAY);
+		I2C2_SCL_LOW;		
+		Delay_I2C_Delay(I2C2_DELAY);
+	}
+	I2C2_SDA_INPUTS;	
+	I2C2_SCL_HIGH;
+	Delay_I2C_Delay(I2C2_DELAY);
+    Ret = I2C2_SDA_READ;
+	Delay_I2C_Delay(I2C2_DELAY);
+	I2C2_SCL_LOW;	
+
+    return Ret;
+}
+
+uint8_t GPIO_I2C2_Read(uint8_t rs)
+{
+    uint8_t i;
+    uint8_t Ret = 0x00;       
+    
+	I2C2_SDA_INPUTS;	
+
+	for(i = 0 ; i < 8 ; i++)
+    {
+		I2C2_SCL_HIGH;  
+		Delay_I2C_Delay(I2C2_DELAY);      
+		Ret <<= 1;        
+		if(I2C2_SDA_READ != 0)
+		{
+			Ret |= 0x01;
+		}
+		I2C2_SCL_LOW;        
+		Delay_I2C_Delay(I2C2_DELAY);
+	}
+
+	I2C2_SDA_OUTPUT;
+
+	if(rs == I2C_ACK)
+ 	{
+		I2C2_SDA_LOW;
+ 	}
+	else
+	{
+		I2C2_SDA_HIGH;
+	}
+
+	I2C2_SCL_HIGH;
+	Delay_I2C_Delay(I2C2_DELAY);
+	I2C2_SCL_LOW;
+	Delay_I2C_Delay(I2C2_DELAY);
+    return Ret;
+}
+
+
+uint8_t I2C2_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize)
+{
+	uint16_t i;
+	GPIO_I2C2_Start();
+	GPIO_I2C2_Write(Address << 1);
+	for(i = 0 ; i < WriteDataSize ; i++)
+	{
+		GPIO_I2C2_Write(pWriteData[i]);
+	}
+	GPIO_I2C2_Stop(); 
+	return 0;
+}
+
+uint8_t I2C2_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize)
+{
+	uint16_t i;	
+	GPIO_I2C2_Start();
+	GPIO_I2C2_Write((Address << 1) | 1);
+	for(i = 0 ; i < ReadDataSize-1 ; i++)
+	{		
+		pReadData[i] = GPIO_I2C2_Read(I2C_ACK);
+	}
+	pReadData[i] = GPIO_I2C2_Read(I2C_NACK);
+	GPIO_I2C2_Stop(); 
+	return 0;
+}
diff --git a/Project/Application/gpio_i2c.h b/Project/Application/gpio_i2c.h
new file mode 100644
index 0000000..c8ae165
--- /dev/null
+++ b/Project/Application/gpio_i2c.h
@@ -0,0 +1,134 @@
+/** \file gpio_i2c.h */ 
+#if !defined(GPIO_I2C_H__817813DF_FB6D_4121_912A_DD8A262A2476__INCLUDED_)
+#define GPIO_I2C_H__817813DF_FB6D_4121_912A_DD8A262A2476__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+
+#define	I2C_ACK	        0
+#define	I2C_NACK	    1
+
+#define I2C0_SDA_PORT	    PD
+#define I2C0_SCL_PORT	    PD
+
+#define I2C0_SDA_PIN		1
+#define I2C0_SCL_PIN		0
+#define I2C0_DELAY          30
+
+
+#define I2C0_SCL_HIGH		HAL_GPIO_SetPin((Pn_Type*)I2C0_SCL_PORT,_BIT(I2C0_SCL_PIN))
+#define I2C0_SCL_LOW		HAL_GPIO_ClearPin((Pn_Type*)I2C0_SCL_PORT,_BIT(I2C0_SCL_PIN))
+
+#define I2C0_SDA_HIGH		HAL_GPIO_SetPin((Pn_Type*)I2C0_SDA_PORT,_BIT(I2C0_SDA_PIN))
+#define I2C0_SDA_LOW		HAL_GPIO_ClearPin((Pn_Type*)I2C0_SDA_PORT,_BIT(I2C0_SDA_PIN))
+
+#define I2C0_SDA_OUTPUT		HAL_GPIO_ConfigOutput((Pn_Type*)I2C0_SDA_PORT, I2C0_SDA_PIN, PUSH_PULL_OUTPUT)
+#define I2C0_SDA_INPUTS		HAL_GPIO_ConfigOutput((Pn_Type*)I2C0_SDA_PORT, I2C0_SDA_PIN, INPUT)
+
+#define I2C0_ACK_READ	    TESTBIT(I2C0_SDA_PORT->INDR, I2C0_SDA_PIN)
+#define I2C0_SDA_READ	    TESTBIT(I2C0_SDA_PORT->INDR, I2C0_SDA_PIN)
+
+
+
+
+
+
+#define I2C1_SDA_PORT	    PF
+#define I2C1_SCL_PORT	    PF
+
+#define I2C1_SDA_PIN		1
+#define I2C1_SCL_PIN		0
+#define I2C1_DELAY          30
+
+
+#define I2C1_SCL_HIGH		HAL_GPIO_SetPin((Pn_Type*)I2C1_SCL_PORT,_BIT(I2C1_SCL_PIN))
+#define I2C1_SCL_LOW		HAL_GPIO_ClearPin((Pn_Type*)I2C1_SCL_PORT,_BIT(I2C1_SCL_PIN))
+
+#define I2C1_SDA_HIGH		HAL_GPIO_SetPin((Pn_Type*)I2C1_SDA_PORT,_BIT(I2C1_SDA_PIN))
+#define I2C1_SDA_LOW		HAL_GPIO_ClearPin((Pn_Type*)I2C1_SDA_PORT,_BIT(I2C1_SDA_PIN))
+
+#define I2C1_SDA_OUTPUT		HAL_GPIO_ConfigOutput((Pn_Type*)I2C1_SDA_PORT, I2C1_SDA_PIN, PUSH_PULL_OUTPUT)
+#define I2C1_SDA_INPUTS		HAL_GPIO_ConfigOutput((Pn_Type*)I2C1_SDA_PORT, I2C1_SDA_PIN, INPUT)
+
+#define I2C1_ACK_READ	    TESTBIT(I2C1_SDA_PORT->INDR, I2C1_SDA_PIN)
+#define I2C1_SDA_READ	    TESTBIT(I2C1_SDA_PORT->INDR, I2C1_SDA_PIN)
+
+
+
+#define I2C2_SDA_PORT	    PC
+#define I2C2_SCL_PORT	    PC
+
+#define I2C2_SDA_PIN		5
+#define I2C2_SCL_PIN		6
+#define I2C2_DELAY          30
+
+
+#define I2C2_SCL_HIGH		HAL_GPIO_SetPin((Pn_Type*)I2C2_SCL_PORT,_BIT(I2C2_SCL_PIN))
+#define I2C2_SCL_LOW		HAL_GPIO_ClearPin((Pn_Type*)I2C2_SCL_PORT,_BIT(I2C2_SCL_PIN))
+
+#define I2C2_SDA_HIGH		HAL_GPIO_SetPin((Pn_Type*)I2C2_SDA_PORT,_BIT(I2C2_SDA_PIN))
+#define I2C2_SDA_LOW		HAL_GPIO_ClearPin((Pn_Type*)I2C2_SDA_PORT,_BIT(I2C2_SDA_PIN))
+
+#define I2C2_SDA_OUTPUT		HAL_GPIO_ConfigOutput((Pn_Type*)I2C2_SDA_PORT, I2C2_SDA_PIN, PUSH_PULL_OUTPUT)
+#define I2C2_SDA_INPUTS		HAL_GPIO_ConfigOutput((Pn_Type*)I2C2_SDA_PORT, I2C2_SDA_PIN, INPUT)
+
+#define I2C2_ACK_READ	    TESTBIT(I2C2_SDA_PORT->INDR, I2C2_SDA_PIN)
+#define I2C2_SDA_READ	    TESTBIT(I2C2_SDA_PORT->INDR, I2C2_SDA_PIN)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+void GPIO_I2C0_Initialization(void);
+void GPIO_I2C0_Start(void);
+void GPIO_I2C0_Stop(void);
+uint8_t GPIO_I2C0_Write(uint8_t data);
+uint8_t GPIO_I2C0_Read(uint8_t rs);
+uint8_t I2C0_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize);
+uint8_t I2C0_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize);
+
+
+
+void GPIO_I2C1_Initialization(void);
+void GPIO_I2C1_Start(void);
+void GPIO_I2C1_Stop(void);
+uint8_t GPIO_I2C1_Write(uint8_t data);
+uint8_t GPIO_I2C1_Read(uint8_t rs);
+uint8_t I2C1_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize);
+uint8_t I2C1_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize);
+
+
+
+
+void GPIO_I2C2_Initialization(void);
+void GPIO_I2C2_Start(void);
+void GPIO_I2C2_Stop(void);
+uint8_t GPIO_I2C2_Write(uint8_t data);
+uint8_t GPIO_I2C2_Read(uint8_t rs);
+uint8_t I2C2_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize);
+uint8_t I2C2_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#endif
diff --git a/Project/Application/gpio_sensor.c b/Project/Application/gpio_sensor.c
new file mode 100644
index 0000000..88f55e6
--- /dev/null
+++ b/Project/Application/gpio_sensor.c
@@ -0,0 +1,10 @@
+#include "gpio_sensor.h"
+
+
+void Gpio_Sensor_PWR_Initialization(void)
+{
+    HAL_GPIO_ConfigOutput(GPIO_SENSOR_PWR_PORT, GPIO_SENSOR_PWR_PIN_NUM, PUSH_PULL_OUTPUT);    
+    HAL_GPIO_ConfigPullup(GPIO_SENSOR_PWR_PORT, GPIO_SENSOR_PWR_PIN_NUM, PUPDx_EnablePU);
+    GPIO_SENSOR_PWR_OFF;
+}
+
diff --git a/Project/Application/gpio_sensor.h b/Project/Application/gpio_sensor.h
new file mode 100644
index 0000000..36e5974
--- /dev/null
+++ b/Project/Application/gpio_sensor.h
@@ -0,0 +1,18 @@
+/** \file gpio_sensor.h */ 
+#if !defined(GPIO_SENSOR_H__8553E44F_09AC_401C_9FD1_67C4131DD471__INCLUDED_)
+#define GPIO_SENSOR_H__8553E44F_09AC_401C_9FD1_67C4131DD471__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+#define GPIO_SENSOR_PWR_PORT         (Pn_Type*)PD
+#define GPIO_SENSOR_PWR_PIN_NUM      6
+#define GPIO_SENSOR_PWR_ON           HAL_GPIO_SetPin(GPIO_SENSOR_PWR_PORT, _BIT(GPIO_SENSOR_PWR_PIN_NUM))
+#define GPIO_SENSOR_PWR_OFF          HAL_GPIO_ClearPin(GPIO_SENSOR_PWR_PORT, _BIT(GPIO_SENSOR_PWR_PIN_NUM))
+#define GPIO_SENSOR_PWR_T            HAL_GPIO_TogglePin(GPIO_SENSOR_PWR_PORT, _BIT(GPIO_SENSOR_PWR_PIN_NUM))
+
+void Gpio_Sensor_PWR_Initialization(void);
+
+
+
+#endif
diff --git a/Project/Application/gpio_state_led.c b/Project/Application/gpio_state_led.c
new file mode 100644
index 0000000..402c553
--- /dev/null
+++ b/Project/Application/gpio_state_led.c
@@ -0,0 +1,83 @@
+#include "gpio_state_led.h"
+#include "sw_timer.h"
+
+
+static void State_Led_Output_Process(void);
+
+
+static STATE_LED_MODE       StateLedMode = STATE_LED_MODE_UNKNOW;
+static STATE_LED_STEP       StateLedStep = STATE_LED_STEP_INIT;
+static STATE_LED_ONOFF_TIME StateLedTime;
+static uint32_t             StateLedCheckTime;
+static STATE_LED_ONOFF_TIME StateLedOnOffTime[STATE_LED_MODE_MAX] = 
+{
+    {100, 900},     //STATE_LED_MODE_OFF,
+    {500, 500},     //STATE_LED_MODE_1,
+    {1000, 1000},   //STATE_LED_MODE_2,
+    {1500, 1500},   //STATE_LED_MODE_3,
+    {2000, 2000},   //STATE_LED_MODE_4,
+    {2500, 2500},   //STATE_LED_MODE_5,    
+};
+
+
+
+
+void Gpio_StateLed_Initialization(void)
+{
+    HAL_GPIO_ConfigOutput(GPIO_STATE_LED_PORT, GPIO_STATE_LED_PIN_NUM, PUSH_PULL_OUTPUT);    
+    HAL_GPIO_ConfigPullup(GPIO_STATE_LED_PORT, GPIO_STATE_LED_PIN_NUM, PUPDx_EnablePU);
+    Gpio_StateLed_Set_Mode(STATE_LED_MODE_OFF);
+    
+    SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1, State_Led_Output_Process);
+}
+
+
+void Gpio_StateLed_Set_Mode(STATE_LED_MODE mode)
+{
+    if(StateLedMode == mode)
+        return;
+    StateLedMode = mode;
+    StateLedStep = STATE_LED_STEP_INIT;    
+    StateLedTime = StateLedOnOffTime[mode];    
+}
+
+STATE_LED_MODE Gpio_StateLed_Get_Mode(void)
+{
+    return StateLedMode;
+}
+
+
+static void State_Led_Output_Process(void)
+{
+    switch(StateLedStep)
+    {
+        case STATE_LED_STEP_INIT:
+            StateLedCheckTime = millis();
+            StateLedStep = STATE_LED_STEP_ON_TIME;
+        break;
+        case STATE_LED_STEP_ON_TIME:
+            if((millis() - StateLedCheckTime) <= StateLedTime.onTime)
+            {
+                GPIO_STATE_LED_ON;
+            }
+            else
+            {
+                StateLedCheckTime = millis();
+                StateLedStep = STATE_LED_STEP_OFF_TIME;
+            }
+        break;
+        case STATE_LED_STEP_OFF_TIME:
+            if((millis() - StateLedCheckTime) <= StateLedTime.OffTime)
+            {
+                GPIO_STATE_LED_OFF;
+            }
+            else
+            {
+                StateLedCheckTime = millis();
+                StateLedStep = STATE_LED_STEP_ON_TIME;
+            }
+        break;
+    }
+}
+
+
diff --git a/Project/Application/gpio_state_led.h b/Project/Application/gpio_state_led.h
new file mode 100644
index 0000000..b1df84e
--- /dev/null
+++ b/Project/Application/gpio_state_led.h
@@ -0,0 +1,45 @@
+/** \file gpio_state_led.h */ 
+#if !defined(GPIO_STATE_LED_H__E29D0861_1041_4928_8D5B_AAD6D1FAD6EB__INCLUDED_)
+#define GPIO_STATE_LED_H__E29D0861_1041_4928_8D5B_AAD6D1FAD6EB__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+#define GPIO_STATE_LED_PORT         (Pn_Type*)PF
+#define GPIO_STATE_LED_PIN_NUM      4
+#define GPIO_STATE_LED_ON           HAL_GPIO_ClearPin(GPIO_STATE_LED_PORT, _BIT(GPIO_STATE_LED_PIN_NUM))
+#define GPIO_STATE_LED_OFF          HAL_GPIO_SetPin(GPIO_STATE_LED_PORT, _BIT(GPIO_STATE_LED_PIN_NUM))
+#define GPIO_STATE_LED_T            HAL_GPIO_TogglePin(GPIO_STATE_LED_PORT, _BIT(GPIO_STATE_LED_PIN_NUM))
+
+
+typedef enum _state_led_mode
+{
+    STATE_LED_MODE_OFF,
+    STATE_LED_MODE_1,
+    STATE_LED_MODE_2,
+    STATE_LED_MODE_3,
+    STATE_LED_MODE_4,
+    STATE_LED_MODE_5,    
+    STATE_LED_MODE_MAX,
+    STATE_LED_MODE_UNKNOW,
+}STATE_LED_MODE;
+
+typedef enum _state_led_step
+{
+    STATE_LED_STEP_INIT,
+    STATE_LED_STEP_ON_TIME,
+    STATE_LED_STEP_OFF_TIME,
+}STATE_LED_STEP;
+
+
+typedef struct _state_led_onoff_time
+{
+    uint32_t onTime;
+    uint32_t OffTime;
+}STATE_LED_ONOFF_TIME;
+
+void Gpio_StateLed_Initialization(void);
+void Gpio_StateLed_Set_Mode(STATE_LED_MODE mode);
+STATE_LED_MODE Gpio_StateLed_Get_Mode(void);
+
+#endif
diff --git a/Project/Application/gpio_switch.c b/Project/Application/gpio_switch.c
new file mode 100644
index 0000000..49f225e
--- /dev/null
+++ b/Project/Application/gpio_switch.c
@@ -0,0 +1,127 @@
+#include "gpio_switch.h"
+#include "sw_timer.h"
+#include "gpio_state_led.h"
+
+
+
+#if 1
+#define GPIO_PUSH_SW1_PORT              (Pn_Type*)PB
+#define GPIO_PUSH_SW1_PIN_NUM           8
+#else
+#define GPIO_PUSH_SW1_PORT              (Pn_Type*)PF
+#define GPIO_PUSH_SW1_PIN_NUM           6
+#endif
+
+typedef struct 
+{
+    Pn_Type*            Port;
+    uint8_t             Pin;
+    uint32_t            nPushCount;
+    uint32_t            nLongPushCount;
+
+    GPIO_SW_CALLBACK_FN Push_Callback;
+    GPIO_SW_CALLBACK_FN LongPush_Callback;
+    GPIO_SW_CALLBACK_FN Release_Callback;
+
+    //////////////////////////////////////////////////////////
+    bool isPush;
+    bool isLongKeyPush;    
+    uint32_t nCheckCount;        
+}KEY_CHECK;
+
+static KEY_CHECK    KeyCheckInfo[KEY_PUSH_SW_MAX] = 
+{
+    {GPIO_PUSH_SW1_PORT, GPIO_PUSH_SW1_PIN_NUM, DEFAULT_KEY_PUSH_COUNT, DEFAULT_LONGKEY_PUSH_COUNT, NULL, NULL, NULL, false, false, 0},
+};
+
+
+static void Gpio_Switch_Check_Process(void);
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+void Gpio_Switch_Port_Initialization(void)
+{    
+    HAL_GPIO_ConfigOutput((Pn_Type*)GPIO_PUSH_SW1_PORT, GPIO_PUSH_SW1_PIN_NUM, INPUT);
+    HAL_GPIO_ConfigPullup((Pn_Type*)GPIO_PUSH_SW1_PORT, GPIO_PUSH_SW1_PIN_NUM, PUPDx_EnablePU);
+    HAL_GPIO_SetDebouncePin((Pn_Type*)GPIO_PUSH_SW1_PORT, GPIO_PUSH_SW1_PIN_NUM, DBCLK_HCLK64);
+    
+    SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1, Gpio_Switch_Check_Process);
+
+}
+
+void Gpio_Swtich_Set_PushCount(KEY_LIST key, uint32_t Push_Count, uint32_t LongPush_Count)
+{
+    if(key < KEY_PUSH_SW_MAX)
+    {
+        KeyCheckInfo[key].nPushCount     = Push_Count;
+        KeyCheckInfo[key].nLongPushCount = LongPush_Count;
+    }
+}
+
+void Gpio_Swtich_Set_Callback(KEY_LIST key, GPIO_SW_CALLBACK_FN Push_Callback, GPIO_SW_CALLBACK_FN LongPush_Callback, GPIO_SW_CALLBACK_FN Release_Callback)
+{
+    if(key < KEY_PUSH_SW_MAX)
+    {
+        KeyCheckInfo[key].Push_Callback     = Push_Callback;
+        KeyCheckInfo[key].LongPush_Callback = LongPush_Callback;
+        KeyCheckInfo[key].Release_Callback  = Release_Callback;
+    }
+}
+
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////
+static void Gpio_Switch_Check_Process(void)
+{   
+    uint8_t i;
+    for(i = 0 ; i < KEY_PUSH_SW_MAX ; i++)
+    {
+        if(TESTBIT(HAL_GPIO_ReadPin(KeyCheckInfo[i].Port), KeyCheckInfo[i].Pin) == 0)
+        {
+            
+            if(KeyCheckInfo[i].isPush != true)
+            {
+                KeyCheckInfo[i].isPush = true;
+                KeyCheckInfo[i].isLongKeyPush = false;
+                KeyCheckInfo[i].nCheckCount = 0;
+            }
+            else
+            {
+                KeyCheckInfo[i].nCheckCount++;
+                if((KeyCheckInfo[i].nCheckCount >= KeyCheckInfo[i].nLongPushCount) && (KeyCheckInfo[i].isLongKeyPush == false))
+                {
+                    KeyCheckInfo[i].isLongKeyPush = true;
+                    if(KeyCheckInfo[i].LongPush_Callback != NULL)
+                    {
+                        KeyCheckInfo[i].LongPush_Callback();
+                    }
+                }
+            }
+        }
+        else
+        {            
+            if(KeyCheckInfo[i].isLongKeyPush == false)
+            {
+                if(KeyCheckInfo[i].nCheckCount >= KeyCheckInfo[i].nPushCount)
+                {
+                    if(KeyCheckInfo[i].Push_Callback != NULL)
+                    {
+                        KeyCheckInfo[i].Push_Callback();
+                    }
+                }
+            }
+
+            if(KeyCheckInfo[i].Release_Callback != NULL)
+            {
+                KeyCheckInfo[i].Release_Callback();
+            }
+            KeyCheckInfo[i].isPush = false;
+            KeyCheckInfo[i].isLongKeyPush = false;
+            KeyCheckInfo[i].nCheckCount = 0;
+        }
+    }
+} 
+
+
diff --git a/Project/Application/gpio_switch.h b/Project/Application/gpio_switch.h
new file mode 100644
index 0000000..c61fdb2
--- /dev/null
+++ b/Project/Application/gpio_switch.h
@@ -0,0 +1,25 @@
+/** \file gpio_switch.h */ 
+#if !defined(GPIO_SWITCH_H__7A08A6AB_4529_4D95_A81A_08ECA85DC521__INCLUDED_)
+#define GPIO_SWITCH_H__7A08A6AB_4529_4D95_A81A_08ECA85DC521__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+typedef enum
+{
+    KEY_PUSH_SW1,
+    KEY_PUSH_SW_MAX
+}KEY_LIST;
+
+typedef void (*GPIO_SW_CALLBACK_FN) (void);
+
+
+
+void Gpio_Switch_Port_Initialization(void);
+void Gpio_Swtich_Set_PushCount(KEY_LIST key, uint32_t Push_Count, uint32_t LongPush_Count);
+void Gpio_Swtich_Set_Callback(KEY_LIST key, GPIO_SW_CALLBACK_FN Push_Callback, GPIO_SW_CALLBACK_FN LongPush_Callback, GPIO_SW_CALLBACK_FN Release_Callback);
+
+
+
+
+#endif
diff --git a/Project/Application/main.c b/Project/Application/main.c
new file mode 100644
index 0000000..3fe76e1
--- /dev/null
+++ b/Project/Application/main.c
@@ -0,0 +1,74 @@
+#include "main.h"
+#include "sw_timer.h"
+#include "gpio_state_led.h"
+#include "gpio_switch.h"
+#include "uart1.h"
+#include "spi10.h"
+#include "spi13.h"
+#include "timer12.h"
+#include "segment_74hc595d.h"
+#include "segment.h"
+#include "save_file.h"
+#include "driver_ds3231_basic.h"
+#include "gpio_i2c.h"
+#include "rtc_process.h"
+#include "action_process.h"
+#include "eeprom.h"
+#include "buzzer.h"
+#include "uart_packet.h"
+
+void timer_test(void)
+{
+   
+
+    //Buzzer_On(50);
+    //Segment_In_Set_Humidity(12);
+
+}
+
+
+
+int main(void)
+{    
+    System_Clock_Initialization();
+    Systick_Initialization(1);       
+    FlashMEM_Clock_Initialization();
+
+    Timer12_Initialization();
+
+    Uart1_Initialization(115200, UARTn_DATA_BIT_8, UARTn_PARITY_BIT_NONE, UARTn_STOP_BIT_1);
+    SPI10_Initialization(1000000, SPI10_MODE0, false);
+    
+
+
+
+    Gpio_StateLed_Initialization();
+    Gpio_Switch_Port_Initialization();
+    Gpio_Sensor_PWR_Initialization();
+    GPIO_I2C0_Initialization();
+    GPIO_I2C1_Initialization();
+    GPIO_I2C2_Initialization();       
+    Segment_Initialization();
+    
+    __enable_irq();
+    
+    
+    RTC_Process_Initialization();
+    Buzzer_Initialization();
+    Action_Initialization();
+    Uart_Packet_Initialization();
+
+    
+    
+    
+    
+    //Sensor_Save_SDCard_Process();
+    SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 500, timer_test);
+    //Timer12_Set_Match_Interrupt_Callback(timer_test);
+
+    while(true)
+    {
+        SW_Timer_Callback_Process();
+    }
+}
+
diff --git a/Project/Application/main.h b/Project/Application/main.h
new file mode 100644
index 0000000..1588817
--- /dev/null
+++ b/Project/Application/main.h
@@ -0,0 +1,9 @@
+/** \file main.h */ 
+#if !defined(MAIN_H__5D109DF7_736B_42BD_A8C5_FB39935994BC__INCLUDED_)
+#define MAIN_H__5D109DF7_736B_42BD_A8C5_FB39935994BC__INCLUDED_
+
+#include "define.h"
+
+
+
+#endif
diff --git a/Project/Application/ring_buffer.c b/Project/Application/ring_buffer.c
new file mode 100644
index 0000000..844b591
--- /dev/null
+++ b/Project/Application/ring_buffer.c
@@ -0,0 +1,114 @@
+#include "ring_buffer.h"
+
+// 큐 초기화
+bool RingBuffer_Initialization(RING_BUFFER* pRingbuffer, bool isOverWrite, uint32_t buffer_size, uint8_t* pBuffer)
+{
+    if(buffer_size == 0 || pRingbuffer == NULL || pBuffer == NULL)
+        return false;
+    pRingbuffer->pBuffer = pBuffer;
+    pRingbuffer->BufferSize = buffer_size;
+    pRingbuffer->isOverWrite = isOverWrite;
+    pRingbuffer->front = -1;
+    pRingbuffer->rear = -1;
+    return true;
+}
+
+bool RingBuffer_Clear(RING_BUFFER* pRingbuffer)
+{
+    if(pRingbuffer == NULL || pRingbuffer->BufferSize == 0 || pRingbuffer->pBuffer == NULL)
+        return false;
+    
+    pRingbuffer->front = -1;
+    pRingbuffer->rear = -1;
+    return true;
+}
+
+bool RingBuffer_isEmpty(RING_BUFFER* pRingbuffer)
+{
+    return (pRingbuffer->front == -1);        
+}
+
+bool RingBuffer_isFull(RING_BUFFER* pRingbuffer)
+{
+    return ((pRingbuffer->front == 0 && pRingbuffer->rear == (pRingbuffer->BufferSize - 1)) || (pRingbuffer->front == (pRingbuffer->rear + 1)));
+}
+// 큐에 요소를 추가 (enqueue)
+bool RingBuffer_Enqueue(RING_BUFFER* pRingbuffer, uint8_t value) 
+{
+    uint8_t temp;
+    if (RingBuffer_isFull(pRingbuffer)) 
+    {
+        if(pRingbuffer->isOverWrite == false)
+            return false;
+        else
+            RingBuffer_Dequeue(pRingbuffer, &temp);
+    }
+    
+    if (pRingbuffer->front == -1) 
+    {
+        pRingbuffer->front = 0;
+    }
+    pRingbuffer->rear = (pRingbuffer->rear + 1) % pRingbuffer->BufferSize;
+    pRingbuffer->pBuffer[pRingbuffer->rear] = value;
+    return true;
+    
+}
+
+// 큐에서 요소를 제거하고 반환 (dequeue)
+bool RingBuffer_Dequeue(RING_BUFFER* pRingbuffer, uint8_t* pRetValue)  
+{    
+    if (RingBuffer_isEmpty(pRingbuffer)) 
+    {        
+        return false;        
+    } 
+    else 
+    {
+        *pRetValue = pRingbuffer->pBuffer[pRingbuffer->front];
+        if (pRingbuffer->front == pRingbuffer->rear) 
+        {
+            pRingbuffer->front = -1;
+            pRingbuffer->rear = -1;
+        } 
+        else 
+        {
+            pRingbuffer->front = (pRingbuffer->front + 1) % pRingbuffer->BufferSize;
+        }
+        return true;
+    }
+}
+
+bool RingBuffer_GetData(RING_BUFFER* pRingbuffer, uint8_t* pRetValue)  
+{
+    *pRetValue = pRingbuffer->pBuffer[pRingbuffer->front];
+    return true;
+}
+
+bool RingBuffer_PopData(RING_BUFFER* pRingbuffer)  
+{
+    if (pRingbuffer->front == pRingbuffer->rear) 
+    {
+        pRingbuffer->front = -1;
+        pRingbuffer->rear = -1;
+    } 
+    else 
+    {
+        pRingbuffer->front = (pRingbuffer->front + 1) % pRingbuffer->BufferSize;
+    }
+    return true;
+}
+
+uint32_t RingBuffer_Get_DataSize(RING_BUFFER* pRingbuffer) 
+{
+    if (RingBuffer_isEmpty(pRingbuffer)) 
+    {
+        return 0;
+    } 
+    else if (pRingbuffer->front <= pRingbuffer->rear) 
+    {
+        return (pRingbuffer->rear - pRingbuffer->front + 1);
+    } 
+    else 
+    {
+        return (pRingbuffer->BufferSize - pRingbuffer->front + pRingbuffer->rear + 1);
+    }
+}
diff --git a/Project/Application/ring_buffer.h b/Project/Application/ring_buffer.h
new file mode 100644
index 0000000..b3652cb
--- /dev/null
+++ b/Project/Application/ring_buffer.h
@@ -0,0 +1,28 @@
+/** \file ring_buffer.h */ 
+#if !defined(RING_BUFFER_H__002F3B3E_9C40_4947_A8EE_139D5ADFF045__INCLUDED_)
+#define RING_BUFFER_H__002F3B3E_9C40_4947_A8EE_139D5ADFF045__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+
+typedef struct ring_buffer 
+{
+    uint8_t*    pBuffer;
+    uint32_t    BufferSize;    
+    bool        isOverWrite;
+    int32_t     front, rear;
+}RING_BUFFER;
+
+bool RingBuffer_Initialization(RING_BUFFER* pRingbuffer, bool isOverWrite, uint32_t buffer_size, uint8_t* pBuffer);
+bool RingBuffer_Clear(RING_BUFFER* pRingbuffer);
+bool RingBuffer_isEmpty(RING_BUFFER* pRingbuffer);
+bool RingBuffer_isFull(RING_BUFFER* pRingbuffer);
+bool RingBuffer_Enqueue(RING_BUFFER* pRingbuffer, uint8_t value) ;
+bool RingBuffer_Dequeue(RING_BUFFER* pRingbuffer, uint8_t* pRetValue);
+bool RingBuffer_GetData(RING_BUFFER* pRingbuffer, uint8_t* pRetValue);
+bool RingBuffer_PopData(RING_BUFFER* pRingbuffer);
+uint32_t RingBuffer_Get_DataSize(RING_BUFFER* pRingbuffer);
+
+
+#endif
diff --git a/Project/Application/rtc_process.c b/Project/Application/rtc_process.c
new file mode 100644
index 0000000..4d6a275
--- /dev/null
+++ b/Project/Application/rtc_process.c
@@ -0,0 +1,44 @@
+#include "rtc_process.h"
+#include "sw_timer.h"
+#include "driver_ds3231_basic.h"
+#include "save_file.h"
+
+
+static RTC_TIME rtc_Time;
+
+static void RTC_Get_IC_Time_Process(void);
+
+
+void RTC_Process_Initialization(void)
+{
+    ds3231_basic_init();
+    SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1000, RTC_Get_IC_Time_Process);
+}
+
+
+static void RTC_Get_IC_Time_Process(void)
+{
+    ds3231_time_t t;       
+    ds3231_basic_get_time(&t);    
+    
+    rtc_Time.rtc_Year = t.year;
+    rtc_Time.rtc_Month = t.month;
+    rtc_Time.rtc_Date = t.date;
+    if(t.format == DS3231_FORMAT_24H)
+        rtc_Time.rtc_Hour = t.hour;
+    else
+        rtc_Time.rtc_Hour = t.hour % 12 + t.am_pm * 12;
+    rtc_Time.rtc_Min = t.minute;
+    rtc_Time.rtc_Sec = t.second;
+   
+
+   
+}
+
+
+RTC_TIME RTC_Get_Time(void)
+{
+    return rtc_Time;
+}
+
+
diff --git a/Project/Application/rtc_process.h b/Project/Application/rtc_process.h
new file mode 100644
index 0000000..1089315
--- /dev/null
+++ b/Project/Application/rtc_process.h
@@ -0,0 +1,21 @@
+/** \file rtc_process.h */ 
+#if !defined(RTC_PROCESS_H__D0EA5D23_A0C1_480D_9C2A_A1F6D5C1D9CC__INCLUDED_)
+#define RTC_PROCESS_H__D0EA5D23_A0C1_480D_9C2A_A1F6D5C1D9CC__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+typedef struct _rtc_time
+{
+    uint16_t rtc_Year;
+    uint8_t  rtc_Month;
+    uint8_t  rtc_Date;
+    uint8_t  rtc_Hour;
+    uint8_t  rtc_Min;
+    uint8_t  rtc_Sec;
+}RTC_TIME;
+
+void RTC_Process_Initialization(void);
+RTC_TIME RTC_Get_Time(void);
+
+#endif
diff --git a/Project/Application/save_file.c b/Project/Application/save_file.c
new file mode 100644
index 0000000..3f0f6e1
--- /dev/null
+++ b/Project/Application/save_file.c
@@ -0,0 +1,190 @@
+#include "save_file.h"
+#include "fatfs.h"
+#include "spi10.h"
+#include "rtc_process.h"
+
+#include "action_process.h"
+
+
+
+
+typedef enum
+{
+    SAVE_STEP_INIT,
+    SAVE_STEP_POWER_ON_WAIT,
+    SAVE_STEP_SAVE_TIME_CHECK,
+    SAVE_STEP_SAVE_MOUNT,
+    SAVE_STEP_SAVE_FILE_OPEN,
+    SAVE_STEP_SAVE_FILE_LSEEK,
+    SAVE_STEP_SAVE_FILE_WRITE,
+    SAVE_STEP_SAVE_FILE_CLOSE,
+    SAVE_STEP_SAVE_ERROR,    
+}SAVE_STEP;
+
+
+static SAVE_STEP    SaveStep = SAVE_STEP_INIT;
+static uint32_t     SaveFileTickCount;
+static uint8_t      SaveMin;
+static FATFS FatFs; 	//Fatfs handle
+static FIL fil; 		//File handle
+static FRESULT fres; //Result after operations
+uint8_t FileBuffer[512];
+
+
+
+uint32_t WriteDataSize;
+
+static bool         isGuidePrint;
+static bool         isPowerOn;
+
+
+bool Save_SensorData_SDCard(void)
+{
+#if 0    
+    RTC_TIME rtc_time;
+    SENSOR_SAVE_DATA SaveSensorData;
+    uint32_t writeByte;
+    rtc_time = RTC_Get_Time();       
+
+    MX_FATFS_Init();
+    fres = f_mount(&FatFs, "", 1); //1=mount now                    
+    if(fres == FR_DISK_ERR)
+    {
+        FATFS_UnLinkDriver("0:/");
+        MX_FATFS_Init();
+        fres = f_mount(&FatFs, "", 1); //1=mount now                    
+    }
+
+    if(fres != FR_OK)
+    {                   
+        return false;
+    }
+    
+
+    sprintf((char *)FileBuffer, "%d_%d_%d.csv", rtc_time.rtc_Year, rtc_time.rtc_Month, rtc_time.rtc_Date);
+    if(f_open(&fil, FileBuffer, FA_WRITE | FA_READ) != FR_OK)
+    {
+        if (f_open(&fil, FileBuffer, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK)
+        {
+            return false;
+        }
+        else
+        {
+            isGuidePrint = true;
+        }
+    }
+    else
+    {
+        isGuidePrint = false;                    
+    }
+
+    
+
+    fres = f_lseek(&fil, f_size(&fil));
+    if(fres != FR_OK)
+    {
+        f_close(&fil);
+        return false;
+    }
+    if(isGuidePrint == true)
+    {
+        sprintf((char *)FileBuffer, "Time,In_PM10.0,In_PM4.0,In_PM2.5,In_PM1.0,In_Humidity,In_Temp,In_Voc,Out_PM10.0,Out_PM4.0,Out_PM2.5,Out_PM1.0,Out_Humidity,Out_Temp,Out_Voc\r\n");
+        fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
+        if(fres != FR_OK)
+        {
+            f_close(&fil);
+            return false;
+        }
+    }
+
+    while(Sensor_RingBuffer_Get_DataSize(&Sensor_RingBuffer_Info) != 0)
+    {
+        if(Sensor_RingBuffer_Dequeue(&Sensor_RingBuffer_Info, &SaveSensorData) == true)
+        {
+            sprintf((char *)FileBuffer, "%d:%d:%d,", SaveSensorData.rtc_time.rtc_Hour, SaveSensorData.rtc_time.rtc_Min, SaveSensorData.rtc_time.rtc_Sec);
+            fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
+            if(fres != FR_OK)
+            {
+                f_close(&fil);
+                return false;
+            }
+
+            if(SaveSensorData.dust_sensor_In_info.isSensorMount == true)
+            {
+                sprintf((char *)FileBuffer, "%d,%d,%d,%d,%d,%d,%d,", SaveSensorData.dust_sensor_In_info.Dust_PM10p0, 
+                                                                           SaveSensorData.dust_sensor_In_info.Dust_PM4p0, 
+                                                                           SaveSensorData.dust_sensor_In_info.Dust_PM2p5,
+                                                                           SaveSensorData.dust_sensor_In_info.Dust_PM1p0,
+                                                                           SaveSensorData.dust_sensor_In_info.Dust_Humidity,
+                                                                           SaveSensorData.dust_sensor_In_info.Dust_Temperature, 
+                                                                           SaveSensorData.dust_sensor_In_info.Dust_VOC_Index);
+                fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
+                if(fres != FR_OK)
+                {
+                    f_close(&fil);
+                    return false;
+                }
+
+                #if 0
+                printf("In, 
+                #endif                                                                 
+            }
+            else
+            {
+                sprintf((char *)FileBuffer, "-,-,-,-,-,-,-,");
+                fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
+                if(fres != FR_OK)
+                {
+                    f_close(&fil);
+                    return false;
+                }
+            }
+
+            if(SaveSensorData.dust_sensor_Out_info.isSensorMount == true)
+            {
+                sprintf((char *)FileBuffer, "%d,%d,%d,%d,%d,%d,%d\r\n", SaveSensorData.dust_sensor_Out_info.Dust_PM10p0, 
+                                                                           SaveSensorData.dust_sensor_Out_info.Dust_PM4p0, 
+                                                                           SaveSensorData.dust_sensor_Out_info.Dust_PM2p5,
+                                                                           SaveSensorData.dust_sensor_Out_info.Dust_PM1p0,
+                                                                           SaveSensorData.dust_sensor_Out_info.Dust_Humidity,
+                                                                           SaveSensorData.dust_sensor_Out_info.Dust_Temperature, 
+                                                                           SaveSensorData.dust_sensor_Out_info.Dust_VOC_Index);
+                fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);        
+                if(fres != FR_OK)
+                {
+                    f_close(&fil);
+                    return false;
+                }        
+            }
+            else
+            {
+                sprintf((char *)FileBuffer, "-,-,-,-,-,-,-\r\n");
+                fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
+                if(fres != FR_OK)
+                {
+                    f_close(&fil);                    
+                    return false;
+                }
+            }
+
+        }
+    }
+
+
+
+    
+    
+
+
+
+
+    f_close(&fil);
+#endif    
+    return true;
+
+}
+
+
+
+
+
diff --git a/Project/Application/save_file.h b/Project/Application/save_file.h
new file mode 100644
index 0000000..bb67749
--- /dev/null
+++ b/Project/Application/save_file.h
@@ -0,0 +1,10 @@
+/** \file save_file.h */ 
+#if !defined(SAVE_FILE_H__13EABF11_DA2C_4D03_AFD4_9CD0FD384825__INCLUDED_)
+#define SAVE_FILE_H__13EABF11_DA2C_4D03_AFD4_9CD0FD384825__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+bool Save_SensorData_SDCard(void);
+
+#endif
diff --git a/Project/Application/segment.c b/Project/Application/segment.c
new file mode 100644
index 0000000..dcb36a2
--- /dev/null
+++ b/Project/Application/segment.c
@@ -0,0 +1,583 @@
+#include "segment.h"
+#include "segment_74hc595d.h"
+
+const uint8_t SegmentData[SEG_INDEX_MAX] = 
+{
+    0x3F, //SEGMENT_0
+    0x06, //SEGMENT_1
+    0x5B, //SEGMENT_2
+    0x4F, //SEGMENT_3
+    0x66, //SEGMENT_4
+    0x6D, //SEGMENT_5
+    0x7D, //SEGMENT_6
+    0x07, //SEGMENT_7
+    0x7F, //SEGMENT_8
+    0x67, //SEGMENT_9
+    0x00, //SEGMENT_CLEAR
+    0x5F, //SEGMENT_A,
+    0x7C, //SEGMENT_B,
+    0x58, //SEGMENT_C,
+    0x5E, //SEGMENT_D,
+    0x79, //SEGMENT_E,
+    0x71, //SEGMENT_F,
+    0x3D, //SEGMENT_G,
+    0x74, //SEGMENT_H,
+    0x11, //SEGMENT_I,
+    0x0D, //SEGMENT_J,
+    0x75, //SEGMENT_K,
+    0x38, //SEGMENT_L,
+    0x55, //SEGMENT_M,
+    0x54, //SEGMENT_N,
+    0x5C, //SEGMENT_O,
+    0x73, //SEGMENT_P,
+    0x67, //SEGMENT_Q,
+    0x50, //SEGMENT_R,
+    0x2D, //SEGMENT_S,
+    0x78, //SEGMENT_T,
+    0x1C, //SEGMENT_U,
+    0x2A, //SEGMENT_V,
+    0x6A, //SEGMENT_W,
+    0x14, //SEGMENT_X,
+    0x6E, //SEGMENT_Y,
+    0x1B, //SEGMENT_Z,    
+    0x40, //SEGMENT_MINUS
+};
+
+
+
+
+
+uint8_t Segment_OutputBuff[SEGMENT_SELECT_MAX_INDEX][SEGMENT_MAX_DATA_INDEX];
+
+
+void Segment_In_Set_PM_1p0(uint32_t OutputData)
+{
+    Segment_Toggle_In = false;
+    if(OutputData >= 9999)
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= 1000)
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[OutputData/1000];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 100)
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 10)
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+}
+
+void Segment_In_Set_PM_2p5(uint32_t OutputData)
+{
+    if(OutputData >= 9999)
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= 1000)
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[OutputData/1000];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 100)
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 10)
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+}
+
+void Segment_In_Set_PM_4p0(uint32_t OutputData)
+{
+    Segment_Toggle_In = true;
+    if(OutputData >= 9999)
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[SEG_9];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= 1000)
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[OutputData/1000];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 100)
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 10)
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+}
+
+void Segment_In_Set_PM_10(uint32_t OutputData)
+{
+    
+    if(OutputData >= 9999)
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= 1000)
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[OutputData/1000];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 100)
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 10)
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
+    }
+}
+
+void Segment_In_Set_Humidity(uint32_t OutputData)
+{
+    if(OutputData >= 99)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_1] = SegmentData[SEG_9];
+    }
+    else if(OutputData <= 9)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_1] = SegmentData[OutputData%10];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_1] = SegmentData[OutputData / 10];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_1] = SegmentData[OutputData % 10];  
+    } 
+}
+
+void Segment_In_Set_Temperature(int32_t OutputData)
+{
+    if(OutputData >= 99)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
+    }
+    else if(OutputData <= -10)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= -9 && OutputData <= -1)
+    {
+        int32_t temp = OutputData * -1;
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[temp%10];
+    }
+    else if(OutputData <= 9 && OutputData >= 0)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[OutputData%10];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[OutputData / 10];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[OutputData % 10];  
+    } 
+}
+
+void Segment_Out_Set_PM_1p0(uint32_t OutputData)
+{
+    Segment_Toggle_Out = false;
+    if(OutputData >= 9999)
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= 1000)
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[OutputData/1000];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 100)
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 10)
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+}
+
+void Segment_Out_Set_PM_2p5(uint32_t OutputData)
+{
+    if(OutputData >= 9999)
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= 1000)
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[OutputData/1000];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 100)
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 10)
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+}
+
+void Segment_Out_Set_PM_4p0(uint32_t OutputData)
+{
+    Segment_Toggle_Out = true;
+    if(OutputData >= 9999)
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[SEG_9];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= 1000)
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[OutputData/1000];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 100)
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 10)
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else
+    {
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+}
+
+void Segment_Out_Set_PM_10(uint32_t OutputData)
+{
+    
+    if(OutputData >= 9999)
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= 1000)
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[OutputData/1000];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 100)
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else if(OutputData >= 10)
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
+    }
+}
+
+void Segment_Out_Set_Humidity(uint32_t OutputData)
+{
+    if(OutputData >= 99)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_3] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_3] = SegmentData[SEG_9];
+    }
+    else if(OutputData <= 9)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_3] = SegmentData[OutputData%10];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_3] = SegmentData[OutputData / 10];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_3] = SegmentData[OutputData % 10];  
+    } 
+}
+
+void Segment_Out_Set_Temperature(int32_t OutputData)
+{
+    if(OutputData >= 99)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_9];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
+    }
+    else if(OutputData <= -10)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
+    }
+    else if(OutputData >= -9 && OutputData <= -1)
+    {
+        int32_t temp = OutputData * -1;
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[temp%10];
+    }
+    else if(OutputData <= 9 && OutputData >= 0)
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[OutputData%10];
+    }
+    else
+    {
+        Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[OutputData / 10];
+        Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[OutputData % 10];  
+    } 
+}
+
+
+void Segment_All_Set_Data(uint8_t SegmentData)
+{
+    uint8_t i;    
+    for(i = SEGMENT_F1C1 ; i < SEGMENT_SELECT_MAX_INDEX ; i++)
+    {
+        Segment_OutputBuff[i][SEGMENT_DATA_1] = SegmentData;
+        Segment_OutputBuff[i][SEGMENT_DATA_2] = SegmentData;
+        Segment_OutputBuff[i][SEGMENT_DATA_3] = SegmentData;
+        Segment_OutputBuff[i][SEGMENT_DATA_4] = SegmentData;
+    }
+
+}
+
+
+void Segment_Show_Version(void)
+{
+    uint8_t i;    
+    uint16_t temp;
+    for(i = SEGMENT_F1C1 ; i < SEGMENT_SELECT_MAX_INDEX ; i++)
+    {
+        Segment_OutputBuff[i][SEGMENT_DATA_1] = 0x00;
+        Segment_OutputBuff[i][SEGMENT_DATA_2] = 0x00;
+        Segment_OutputBuff[i][SEGMENT_DATA_3] = 0x00;
+        Segment_OutputBuff[i][SEGMENT_DATA_4] = 0x00;
+    }
+
+    //Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_V];
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_E];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[SEG_R];
+
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[VERSION_MAJOR] | 0x80;
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[VERSION_MINOR] | 0x80;
+    temp = VERSION_PATCH;
+    if(temp >= 99)
+    {
+        temp = 99;
+    }
+
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[temp/10];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[temp%10];
+}
+
+
+
+void Segment_Show_Mode(uint8_t Mode)
+{
+    uint8_t i;    
+    uint16_t temp;
+    for(i = SEGMENT_F1C1 ; i < SEGMENT_SELECT_MAX_INDEX ; i++)
+    {
+        Segment_OutputBuff[i][SEGMENT_DATA_1] = 0x00;
+        Segment_OutputBuff[i][SEGMENT_DATA_2] = 0x00;
+        Segment_OutputBuff[i][SEGMENT_DATA_3] = 0x00;
+        Segment_OutputBuff[i][SEGMENT_DATA_4] = 0x00;
+    }
+
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_M];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_O];
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_D];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[SEG_E];
+
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[Mode];
+
+}
+
+void Segment_In_Sensor_Error(void)
+{
+    Segment_Toggle_In = false;
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+
+    Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+
+    Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+
+    Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];    
+}
+
+
+void Segment_Out_Sensor_Error(void)
+{
+    Segment_Toggle_Out = false;
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+
+    Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+
+    Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+
+    Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
+    Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];    
+}
diff --git a/Project/Application/segment.h b/Project/Application/segment.h
new file mode 100644
index 0000000..edbd59f
--- /dev/null
+++ b/Project/Application/segment.h
@@ -0,0 +1,97 @@
+/** \file segment.h */ 
+#if !defined(SEGMENT_H__CECA83FE_5707_4492_A247_CC6270C87910__INCLUDED_)
+#define SEGMENT_H__CECA83FE_5707_4492_A247_CC6270C87910__INCLUDED_
+
+#include "board_config.h"
+
+typedef enum
+{
+    SEG_0,
+    SEG_1,
+    SEG_2,
+    SEG_3,
+    SEG_4,
+    SEG_5,
+    SEG_6,
+    SEG_7,
+    SEG_8,
+    SEG_9,
+    SEG_CLEAR,
+    SEG_A,
+    SEG_B,
+    SEG_C,
+    SEG_D,
+    SEG_E,
+    SEG_F,
+    SEG_G,
+    SEG_H,
+    SEG_I,
+    SEG_J,
+    SEG_K,
+    SEG_L,
+    SEG_M,
+    SEG_N,
+    SEG_O,
+    SEG_P,
+    SEG_Q,
+    SEG_R,
+    SEG_S,
+    SEG_T,
+    SEG_U,
+    SEG_V,
+    SEG_W,
+    SEG_X,
+    SEG_Y,
+    SEG_Z,    
+    SEG_MINUS,
+    SEG_INDEX_MAX,
+}SEGMENT_INDEX;
+
+typedef enum
+{
+    SEGMENT_F1C1,
+    SEGMENT_F1C2,
+    SEGMENT_F2C1,
+    SEGMENT_F2C2,
+    SEGMENT_F3C1,
+    SEGMENT_F3C2,
+    SEGMENT_F4C1,
+    SEGMENT_F4C2,
+    SEGMENT_SELECT_MAX_INDEX,
+}SEGMENT_SELECT_INDEX;
+
+typedef enum
+{
+    SEGMENT_DATA_1,
+    SEGMENT_DATA_2,
+    SEGMENT_DATA_3,
+    SEGMENT_DATA_4,
+    SEGMENT_MAX_DATA_INDEX,
+}SEGMENT_DATA_INDEX;
+
+
+extern uint8_t Segment_OutputBuff[SEGMENT_SELECT_MAX_INDEX][SEGMENT_MAX_DATA_INDEX];
+extern const uint8_t SegmentData[SEG_INDEX_MAX];
+
+
+void Segment_In_Set_PM_1p0(uint32_t OutputData);
+void Segment_In_Set_PM_2p5(uint32_t OutputData);
+void Segment_In_Set_PM_4p0(uint32_t OutputData);
+void Segment_In_Set_PM_10(uint32_t OutputData);
+void Segment_In_Set_Humidity(uint32_t OutputData);
+void Segment_In_Set_Temperature(int32_t OutputData);
+void Segment_In_Sensor_Error(void);
+
+void Segment_Out_Set_PM_1p0(uint32_t OutputData);
+void Segment_Out_Set_PM_2p5(uint32_t OutputData);
+void Segment_Out_Set_PM_4p0(uint32_t OutputData);
+void Segment_Out_Set_PM_10(uint32_t OutputData);
+void Segment_Out_Set_Humidity(uint32_t OutputData);
+void Segment_Out_Set_Temperature(int32_t OutputData);
+void Segment_Out_Sensor_Error(void);
+
+void Segment_All_Set_Data(uint8_t SegmentData);
+void Segment_Show_Version(void);
+void Segment_Show_Mode(uint8_t Mode);
+
+#endif
diff --git a/Project/Application/segment_74hc595d.c b/Project/Application/segment_74hc595d.c
new file mode 100644
index 0000000..51624bc
--- /dev/null
+++ b/Project/Application/segment_74hc595d.c
@@ -0,0 +1,220 @@
+#include "segment_74hc595d.h"
+#include "segment.h"
+#include "timer12.h"
+#include "spi13.h"
+#include "systick_timer.h"
+
+
+typedef enum
+{
+    LSB_FIRST,
+    MSB_FIRST,
+}LSB_MSB_MODE;
+
+
+
+#define SEGMENT_74HC595D_SDATA_PORT         (Pn_Type*)PE
+#define SEGMENT_74HC595D_SDATA_PIN          8
+#define SEGMENT_74HC595D_SDATA_HIGH		    HAL_GPIO_SetPin(SEGMENT_74HC595D_SDATA_PORT,_BIT(SEGMENT_74HC595D_SDATA_PIN))
+#define SEGMENT_74HC595D_SDATA_LOW		    HAL_GPIO_ClearPin(SEGMENT_74HC595D_SDATA_PORT,_BIT(SEGMENT_74HC595D_SDATA_PIN))
+
+#define SEGMENT_74HC595D_SCK_PORT           (Pn_Type*)PE
+#define SEGMENT_74HC595D_SCK_PIN            9
+#define SEGMENT_74HC595D_SCK_HIGH		    HAL_GPIO_SetPin(SEGMENT_74HC595D_SCK_PORT,_BIT(SEGMENT_74HC595D_SCK_PIN))
+#define SEGMENT_74HC595D_SCK_LOW		    HAL_GPIO_ClearPin(SEGMENT_74HC595D_SCK_PORT,_BIT(SEGMENT_74HC595D_SCK_PIN))
+
+#define SEGMENT_74HC595D_LATCH_PORT         (Pn_Type*)PE
+#define SEGMENT_74HC595D_LATCH_PIN_NUM      10
+#define SEGMENT_74HC595D_LATCH_H            HAL_GPIO_SetPin(SEGMENT_74HC595D_LATCH_PORT, _BIT(SEGMENT_74HC595D_LATCH_PIN_NUM))
+#define SEGMENT_74HC595D_LATCH_L            HAL_GPIO_ClearPin(SEGMENT_74HC595D_LATCH_PORT, _BIT(SEGMENT_74HC595D_LATCH_PIN_NUM))
+#define SEGMENT_74HC595D_LATCH_T            HAL_GPIO_TogglePin(SEGMENT_74HC595D_LATCH_PORT, _BIT(SEGMENT_74HC595D_LATCH_PIN_NUM))
+
+
+typedef union 
+{
+    struct 
+    {
+        uint8_t HC595_4;
+        uint8_t HC595_3;
+        
+        uint8_t HC595_5_F1C1  : 1;
+        uint8_t HC595_5_F1C2  : 1;
+        uint8_t HC595_5_F2C1  : 1;        
+        uint8_t HC595_5_F2C2  : 1;
+        uint8_t HC595_5_F3C1  : 1;
+        uint8_t HC595_5_F3C2  : 1;        
+        uint8_t HC595_5_F4C1  : 1;
+        uint8_t HC595_5_F4C2  : 1;                       
+
+        uint8_t HC595_2;
+        uint8_t HC595_1;
+    }HC595_Data;
+    uint8_t HC595_TxBuff[SEGMENT_74HC595D_IC_TOTAL_NUM];
+}HC595_OUTPUT_DATA;
+
+
+
+static SEGMENT_OUTPUT_STEP  SegmentOutputStep;
+static HC595_OUTPUT_DATA    HC595_OutputData;
+static LSB_MSB_MODE         HC595_OutputMode = MSB_FIRST;
+static uint32_t ToggleTickCount;
+static bool isToggle = false;
+
+uint8_t Segment_Buff[SEGMENT_OUTPUT_MAX][SEGMENT_74HC595D_IC_DATA_NUM];
+bool    Segment_Toggle_In;
+bool    Segment_Toggle_Out;
+
+
+static void Segemet_Output_Process(void);
+static void Segment_Output_Data(uint8_t* pTxData, uint8_t TxSize);
+
+void Segment_Initialization(void)
+{
+    HAL_GPIO_ConfigOutput(SEGMENT_74HC595D_SDATA_PORT, SEGMENT_74HC595D_SDATA_PIN, PUSH_PULL_OUTPUT);    
+    HAL_GPIO_ConfigPullup(SEGMENT_74HC595D_SDATA_PORT, SEGMENT_74HC595D_SDATA_PIN, PUPDx_EnablePU);
+    
+    HAL_GPIO_ConfigOutput(SEGMENT_74HC595D_SCK_PORT, SEGMENT_74HC595D_SCK_PIN, PUSH_PULL_OUTPUT);    
+    HAL_GPIO_ConfigPullup(SEGMENT_74HC595D_SCK_PORT, SEGMENT_74HC595D_SCK_PIN, PUPDx_EnablePU);
+    
+    HAL_GPIO_ConfigOutput(SEGMENT_74HC595D_LATCH_PORT, SEGMENT_74HC595D_LATCH_PIN_NUM, PUSH_PULL_OUTPUT);    
+    HAL_GPIO_ConfigPullup(SEGMENT_74HC595D_LATCH_PORT, SEGMENT_74HC595D_LATCH_PIN_NUM, PUPDx_EnablePU);
+
+
+    SEGMENT_74HC595D_LATCH_H;
+    SEGMENT_74HC595D_SCK_LOW;
+    SEGMENT_74HC595D_SDATA_HIGH;
+
+    //Segmet_Output_Process();
+    ToggleTickCount = millis();
+    isToggle = false;
+    Timer12_Set_Match_Interrupt_Callback(Segemet_Output_Process);
+}
+
+static void Segemet_Output_Process(void)
+{
+    static uint8_t temp = 0;
+    
+    memset(HC595_OutputData.HC595_TxBuff, 0, SEGMENT_74HC595D_IC_TOTAL_NUM);
+
+    if((millis() - ToggleTickCount) >= SEGMENT_TOGGLE_TIME)
+    {
+        ToggleTickCount = millis();
+        isToggle = !isToggle;
+    }
+    
+    
+    switch(SegmentOutputStep)
+    {
+        case SEGMENT_OUTPUT_F1C1:                        
+            HC595_OutputData.HC595_Data.HC595_5_F1C1 = true;
+        break;
+        case SEGMENT_OUTPUT_F1C2:
+            HC595_OutputData.HC595_Data.HC595_5_F1C2 = true;
+        break;        
+        case SEGMENT_OUTPUT_F2C1:
+            HC595_OutputData.HC595_Data.HC595_5_F2C1 = true;
+        break;
+        case SEGMENT_OUTPUT_F2C2:
+            HC595_OutputData.HC595_Data.HC595_5_F2C2 = true;
+        break;
+        case SEGMENT_OUTPUT_F3C1:
+            HC595_OutputData.HC595_Data.HC595_5_F3C1 = true;
+        break;
+        case SEGMENT_OUTPUT_F3C2:            
+            HC595_OutputData.HC595_Data.HC595_5_F3C2 = true;
+        break;
+        case SEGMENT_OUTPUT_F4C1:            
+            HC595_OutputData.HC595_Data.HC595_5_F4C1 = true;
+        break;
+        case SEGMENT_OUTPUT_F4C2:
+            HC595_OutputData.HC595_Data.HC595_5_F4C2 = true;
+        break;
+    }
+
+    HC595_OutputData.HC595_Data.HC595_1 = Segment_OutputBuff[SegmentOutputStep][0];
+    HC595_OutputData.HC595_Data.HC595_2 = Segment_OutputBuff[SegmentOutputStep][1];
+    HC595_OutputData.HC595_Data.HC595_3 = Segment_OutputBuff[SegmentOutputStep][2];
+    HC595_OutputData.HC595_Data.HC595_4 = Segment_OutputBuff[SegmentOutputStep][3];
+
+    if(Segment_Toggle_In == true && isToggle == true)
+    {
+        if(SegmentOutputStep == DUST_SENSOR_PM40_SELECT_1 || SegmentOutputStep == DUST_SENSOR_PM40_SELECT_2)
+        {
+            HC595_OutputData.HC595_Data.HC595_1 = 0x00;
+            HC595_OutputData.HC595_Data.HC595_2 = 0x00;
+        }
+    }
+
+    if(Segment_Toggle_Out == true && isToggle == true)
+    {
+        if(SegmentOutputStep == DUST_SENSOR_PM40_SELECT_1 || SegmentOutputStep == DUST_SENSOR_PM40_SELECT_2)
+        {
+            HC595_OutputData.HC595_Data.HC595_3 = 0x00;
+            HC595_OutputData.HC595_Data.HC595_4 = 0x00;
+        }
+    }
+    
+    SEGMENT_74HC595D_LATCH_L;
+    Segment_Output_Data(HC595_OutputData.HC595_TxBuff, SEGMENT_74HC595D_IC_TOTAL_NUM);
+    SEGMENT_74HC595D_LATCH_H;
+
+    SegmentOutputStep++;
+    if(SegmentOutputStep >= SEGMENT_OUTPUT_MAX)
+    {
+        SegmentOutputStep = SEGMENT_OUTPUT_F1C1;
+    }
+}
+
+
+static void Segment_Output_Data(uint8_t* pTxData, uint8_t TxSize)
+{
+    uint8_t Temp;
+    uint8_t i, j;
+
+    if(HC595_OutputMode == LSB_FIRST)
+    {
+        for(i = 0 ; i < TxSize ; i++)
+        {
+            Temp = pTxData[i];
+            for(j = 0 ; j < 8 ; j++)
+            {
+                if((Temp & 0x01))                
+                {
+                    SEGMENT_74HC595D_SDATA_HIGH;
+                }
+                else
+                {
+                    SEGMENT_74HC595D_SDATA_LOW;
+                }
+
+                SEGMENT_74HC595D_SCK_HIGH;
+                SEGMENT_74HC595D_SCK_LOW;
+                Temp = Temp >> 1;
+            }
+        }
+    }
+    else
+    {
+        for(i = 0 ; i < TxSize ; i++)
+        {
+            Temp = pTxData[i];
+            for(j = 0 ; j < 8 ; j++)
+            {
+                if((Temp & 0x80))                
+                {
+                    SEGMENT_74HC595D_SDATA_HIGH;
+                }
+                else
+                {
+                    SEGMENT_74HC595D_SDATA_LOW;
+                }
+
+                SEGMENT_74HC595D_SCK_HIGH;
+                SEGMENT_74HC595D_SCK_LOW;
+                Temp = Temp << 1;
+            }
+        }
+    }
+    SEGMENT_74HC595D_SDATA_HIGH;
+}
+
diff --git a/Project/Application/segment_74hc595d.h b/Project/Application/segment_74hc595d.h
new file mode 100644
index 0000000..959be90
--- /dev/null
+++ b/Project/Application/segment_74hc595d.h
@@ -0,0 +1,46 @@
+/** \file segment_74hc595d.h */ 
+#if !defined(SEGMENT_74HC595D_H__80B128A2_DCE6_4A8C_812C_0CCA0173ECA2__INCLUDED_)
+#define SEGMENT_74HC595D_H__80B128A2_DCE6_4A8C_812C_0CCA0173ECA2__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+
+#define SEGMENT_74HC595D_IC_DATA_NUM        4
+#define SEGMENT_74HC595D_IC_SELECT_NUM      1
+#define SEGMENT_74HC595D_IC_TOTAL_NUM       (SEGMENT_74HC595D_IC_DATA_NUM + SEGMENT_74HC595D_IC_SELECT_NUM)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+typedef enum
+{
+    SEGMENT_OUTPUT_F1C1,
+    SEGMENT_OUTPUT_F1C2,
+    SEGMENT_OUTPUT_F2C1,
+    SEGMENT_OUTPUT_F2C2,
+    SEGMENT_OUTPUT_F3C1,
+    SEGMENT_OUTPUT_F3C2,
+    SEGMENT_OUTPUT_F4C1,
+    SEGMENT_OUTPUT_F4C2,
+    SEGMENT_OUTPUT_MAX,
+}SEGMENT_OUTPUT_STEP;
+
+
+
+void Segment_Initialization(void);
+
+extern uint8_t Segment_Buff[SEGMENT_OUTPUT_MAX][SEGMENT_74HC595D_IC_DATA_NUM];
+extern bool    Segment_Toggle_In;
+extern bool    Segment_Toggle_Out;
+#endif
diff --git a/Project/Application/spi10.c b/Project/Application/spi10.c
new file mode 100644
index 0000000..bd0a934
--- /dev/null
+++ b/Project/Application/spi10.c
@@ -0,0 +1,114 @@
+#include "spi10.h"
+
+
+void SPI10_Initialization(uint32_t speed, SPI10_MODE mode, bool lsbFirst)
+{
+    USART1n_CFG_Type     USART1n_Config;
+   /*
+   * Initialize USART10
+   */
+    HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 0, ALTERN_FUNC );
+    HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 0, AFSRx_AF2 );
+
+    HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 1, ALTERN_FUNC );
+    HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 1, AFSRx_AF2 );
+
+    HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 2, ALTERN_FUNC );
+    HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 2, AFSRx_AF2 );    
+
+
+    
+
+    HAL_GPIO_ConfigOutput((Pn_Type*)SPI10_CS_PORT, SPI10_CS_PIN, PUSH_PULL_OUTPUT );
+    HAL_GPIO_ConfigPullup((Pn_Type*)SPI10_CS_PORT, SPI10_CS_PIN, PUPDx_EnablePU );
+    
+    SPI10_CS_HIGH;
+
+
+
+    // default: 38400-8-N-1
+    HAL_USART_SPI_Mode_Config( &USART1n_Config );
+
+    USART1n_Config.Mode = USART1n_SPI_MODE;
+    USART1n_Config.Baudrate = speed;
+    USART1n_Config.Databits = USART1n_DATA_BIT_8;
+    USART1n_Config.Parity = USART1n_PARITY_BIT_NONE;
+    USART1n_Config.Stopbits = USART1n_STOP_BIT_1;  
+
+    if(lsbFirst == true)
+        USART1n_Config.Order = USART1n_SPI_LSB; 
+    else
+        USART1n_Config.Order = USART1n_SPI_MSB;        
+    
+    switch(mode)
+    {
+        case SPI10_MODE0:
+            USART1n_Config.ACK = USART1n_SPI_TX_RISING;
+            USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
+        break;
+        case SPI10_MODE1:
+            USART1n_Config.ACK = USART1n_SPI_TX_RISING;
+            USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
+        break;
+        case SPI10_MODE2:
+            USART1n_Config.ACK = USART1n_SPI_TX_FALLING;
+            USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
+        break;
+        case SPI10_MODE3:
+            USART1n_Config.ACK = USART1n_SPI_TX_FALLING;
+            USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
+        break;
+    }
+
+   HAL_USART_Init( ( USART1n_Type* )USART10, &USART1n_Config );
+
+   // SPI Master
+   HAL_USART_DataControlConfig( ( USART1n_Type* )USART10, USART1n_CONTROL_MASTER, ENABLE );   
+
+   // ENABLE
+   HAL_USART_Enable( ( USART1n_Type* )USART10, ENABLE );
+}
+
+
+
+
+void SPI10_Transmit(uint8_t* pTxData, uint32_t Tx_Len)
+{
+    
+    uint32_t i;
+        
+    for(i = 0 ; i < Tx_Len ; i++)
+    {
+        USART10->DR = pTxData[i];
+        while((USART10->ST & 0x40)==0x00){} // transmit complete flag wait
+        while((USART10->ST & 0x20)==0x00){} // receive complete flag wait            
+        uint8_t temp = USART10->DR;
+    }   
+}
+
+void SPI10_SendRecv(uint8_t* pTxByte, uint8_t* pRxByte, uint32_t TRx_Len)
+{
+    uint32_t i;
+
+    for(i = 0 ; i < TRx_Len ; i++)
+    {
+        USART10->DR = pTxByte[i];
+        while((USART10->ST & 0x40)==0x00){} // transmit complete flag wait
+        while((USART10->ST & 0x20)==0x00){} // receive complete flag wait    
+        pRxByte[i] = USART10->DR;
+    }   
+}
+
+uint8_t SPI10_SendReceiveByte(uint8_t SendByte)
+{
+    uint8_t recvByte;
+
+    USART10->DR = SendByte;
+    while((USART10->ST & 0x40)==0x00){} // transmit complete flag wait
+    while((USART10->ST & 0x20)==0x00){} // receive complete flag wait    
+
+    recvByte = USART10->DR;
+
+    return recvByte;
+}
+
diff --git a/Project/Application/spi10.h b/Project/Application/spi10.h
new file mode 100644
index 0000000..730e13d
--- /dev/null
+++ b/Project/Application/spi10.h
@@ -0,0 +1,35 @@
+/** \file spi11.h */ 
+#if !defined(SPI10_H__30436C8B_DA45_4E91_95E0_C40C4C083867__INCLUDED_)
+#define SPI10_H__30436C8B_DA45_4E91_95E0_C40C4C083867__INCLUDED_
+
+
+#include "define.h"
+#include "board_config.h"
+
+
+typedef enum
+{
+    SPI10_MODE0, 
+    SPI10_MODE1, 
+    SPI10_MODE2, 
+    SPI10_MODE3, 
+}SPI10_MODE;
+
+
+
+#define SPI10_CS_PORT               PA
+#define SPI10_CS_PIN                7
+#define SPI10_CS_LOW                HAL_GPIO_ClearPin((Pn_Type*)SPI10_CS_PORT, _BIT(SPI10_CS_PIN))
+#define SPI10_CS_HIGH               HAL_GPIO_SetPin((Pn_Type*)SPI10_CS_PORT, _BIT(SPI10_CS_PIN))
+
+
+
+void SPI10_Initialization(uint32_t speed, SPI10_MODE mode, bool lsbFirst);
+void SPI10_Transmit(uint8_t* pTxData, uint32_t Tx_Len);
+void SPI10_SendRecv(uint8_t* pTxByte, uint8_t* pRxByte, uint32_t TRx_Len);
+uint8_t SPI10_SendReceiveByte(uint8_t SendByte);
+
+
+
+
+#endif
diff --git a/Project/Application/spi13.c b/Project/Application/spi13.c
new file mode 100644
index 0000000..3dbdec0
--- /dev/null
+++ b/Project/Application/spi13.c
@@ -0,0 +1,107 @@
+#include "spi13.h"
+
+
+void SPI13_Initialization(uint32_t speed, SPI13_MODE mode, bool lsbFirst)
+{
+    USART1n_CFG_Type     USART1n_Config;
+   /*
+   * Initialize USART13
+   */
+    // MOSI
+    HAL_GPIO_ConfigOutput( ( Pn_Type* )PE, 8, ALTERN_FUNC );
+    HAL_GPIO_ConfigFunction( ( Pn_Type* )PE, 8, AFSRx_AF2 );
+
+    // MISO
+    //HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 1, ALTERN_FUNC );
+    //HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 1, AFSRx_AF2 );
+
+    // SCK
+    HAL_GPIO_ConfigOutput( ( Pn_Type* )PE, 10, ALTERN_FUNC );
+    HAL_GPIO_ConfigFunction( ( Pn_Type* )PE, 10, AFSRx_AF2 );    
+
+    // default: 38400-8-N-1
+    HAL_USART_SPI_Mode_Config( &USART1n_Config );
+
+    USART1n_Config.Mode = USART1n_SPI_MODE;
+    USART1n_Config.Baudrate = speed;
+    USART1n_Config.Databits = USART1n_DATA_BIT_8;
+    USART1n_Config.Parity = USART1n_PARITY_BIT_NONE;
+    USART1n_Config.Stopbits = USART1n_STOP_BIT_1;  
+
+    if(lsbFirst == true)
+        USART1n_Config.Order = USART1n_SPI_LSB; 
+    else
+        USART1n_Config.Order = USART1n_SPI_MSB;        
+    
+    switch(mode)
+    {
+        case SPI13_MODE0:
+            USART1n_Config.ACK = USART1n_SPI_TX_RISING;
+            USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
+        break;
+        case SPI13_MODE1:
+            USART1n_Config.ACK = USART1n_SPI_TX_RISING;
+            USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
+        break;
+        case SPI13_MODE2:
+            USART1n_Config.ACK = USART1n_SPI_TX_FALLING;
+            USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
+        break;
+        case SPI13_MODE3:
+            USART1n_Config.ACK = USART1n_SPI_TX_FALLING;
+            USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
+        break;
+    }
+
+   HAL_USART_Init( ( USART1n_Type* )USART13, &USART1n_Config );
+
+   // SPI Master
+   HAL_USART_DataControlConfig( ( USART1n_Type* )USART13, USART1n_CONTROL_MASTER, ENABLE );   
+
+   // ENABLE
+   HAL_USART_Enable( ( USART1n_Type* )USART13, ENABLE );
+}
+
+
+
+
+void SPI13_Transmit(uint8_t* pTxData, uint32_t Tx_Len)
+{
+    
+    uint32_t i;
+        
+    for(i = 0 ; i < Tx_Len ; i++)
+    {
+        USART13->DR = pTxData[i];
+        while((USART13->ST & 0x40)==0x00){} // transmit complete flag wait
+        while((USART13->ST & 0x20)==0x00){} // receive complete flag wait            
+        uint8_t temp = USART13->DR;
+    }   
+}
+
+void SPI13_SendRecv(uint8_t* pTxByte, uint8_t* pRxByte, uint32_t TRx_Len)
+{
+    uint32_t i;
+
+    for(i = 0 ; i < TRx_Len ; i++)
+    {
+        USART13->DR = pTxByte[i];
+        while((USART13->ST & 0x40)==0x00){} // transmit complete flag wait
+        while((USART13->ST & 0x20)==0x00){} // receive complete flag wait    
+        pRxByte[i] = USART13->DR;
+    }   
+}
+
+uint8_t SPI13_SendReceiveByte(uint8_t SendByte)
+{
+    uint8_t recvByte;
+
+    USART13->DR = SendByte;
+    while((USART13->ST & 0x40)==0x00){} // transmit complete flag wait
+    while((USART13->ST & 0x20)==0x00){} // receive complete flag wait    
+
+    recvByte = USART13->DR;
+
+    return recvByte;
+}
+
diff --git a/Project/Application/spi13.h b/Project/Application/spi13.h
new file mode 100644
index 0000000..462ab96
--- /dev/null
+++ b/Project/Application/spi13.h
@@ -0,0 +1,26 @@
+/** \file spi13.h */ 
+#if !defined(SPI13_H__30436C8B_DA45_4E91_95E0_C40C4C083867__INCLUDED_)
+#define SPI10_H__30436C8B_DA45_4E91_95E0_C40C4C083867__INCLUDED_
+
+
+#include "define.h"
+#include "board_config.h"
+
+
+typedef enum
+{
+    SPI13_MODE0, 
+    SPI13_MODE1, 
+    SPI13_MODE2, 
+    SPI13_MODE3, 
+}SPI13_MODE;
+
+void SPI13_Initialization(uint32_t speed, SPI13_MODE mode, bool lsbFirst);
+void SPI13_Transmit(uint8_t* pTxData, uint32_t Tx_Len);
+void SPI13_SendRecv(uint8_t* pTxByte, uint8_t* pRxByte, uint32_t TRx_Len);
+uint8_t SPI13_SendReceiveByte(uint8_t SendByte);
+
+
+
+
+#endif
diff --git a/Project/Application/sw_timer.c b/Project/Application/sw_timer.c
new file mode 100644
index 0000000..46fd0db
--- /dev/null
+++ b/Project/Application/sw_timer.c
@@ -0,0 +1,84 @@
+#include "sw_timer.h"
+#include "systick_timer.h"
+
+
+
+typedef struct _timer_callback_info
+{
+    SW_TIMER_CALLBACK_TYPE  SW_Callback_Type;
+    uint32_t                SW_Timer_StartTick;
+    uint32_t                SW_Timer_PeriodCount;
+    SW_TIMER_CALLBACK_FN    SW_Timer_CallbackFunction;
+}SW_TIMER_INFO;
+
+
+static SW_TIMER_INFO    SW_Timer_Info[MAX_SW_TIMER_REGISTER_COUNT];
+
+
+
+bool SW_Timer_Callback_Register(SW_TIMER_CALLBACK_TYPE type, uint32_t PeriodTime, SW_TIMER_CALLBACK_FN pTimerCallback)
+{
+    uint8_t i;
+    bool ret = false;   
+    
+    for(i = 0 ; i < MAX_SW_TIMER_REGISTER_COUNT ; i++)
+    {
+        if(SW_Timer_Info[i].SW_Timer_CallbackFunction == NULL)
+        {
+            SW_Timer_Info[i].SW_Callback_Type = type;
+            SW_Timer_Info[i].SW_Timer_StartTick = millis();
+            SW_Timer_Info[i].SW_Timer_PeriodCount = PeriodTime;
+            SW_Timer_Info[i].SW_Timer_CallbackFunction = pTimerCallback;
+            ret = true;
+            break;
+        }
+    }
+   
+    return ret;
+}
+
+bool SW_Timer_Callback_UnRegister(SW_TIMER_CALLBACK_FN pSwTimerCallbackFunc)
+{
+    uint8_t i;
+    bool ret = false;
+
+    for(i = 0 ; i < MAX_SW_TIMER_REGISTER_COUNT ; i++)
+    {
+        if(SW_Timer_Info[i].SW_Timer_CallbackFunction == pSwTimerCallbackFunc)
+        {            
+            SW_Timer_Info[i].SW_Callback_Type = SW_TIMER_RUN_NONE;
+            SW_Timer_Info[i].SW_Timer_CallbackFunction = NULL;
+            ret = true;            
+        }
+    }
+    return ret;
+}
+
+void SW_Timer_Callback_Process(void)
+{
+    uint8_t i;
+    uint32_t nowTickCount = millis();
+    for(i = 0 ; i < MAX_SW_TIMER_REGISTER_COUNT ; i++)
+    {
+        if(SW_Timer_Info[i].SW_Timer_CallbackFunction != NULL && 
+           SW_Timer_Info[i].SW_Callback_Type != SW_TIMER_RUN_NONE)
+        {
+            if((nowTickCount - SW_Timer_Info[i].SW_Timer_StartTick) >= SW_Timer_Info[i].SW_Timer_PeriodCount)
+            {
+                if(SW_Timer_Info[i].SW_Callback_Type == SW_TIMER_RUN_ONNY_ONCE)
+                {					
+					SW_Timer_Info[i].SW_Timer_StartTick = 0xFFFFFFFF;
+                    SW_Timer_Info[i].SW_Callback_Type = SW_TIMER_RUN_NONE;
+					SW_Timer_Info[i].SW_Timer_CallbackFunction();
+                    SW_Timer_Info[i].SW_Timer_CallbackFunction = NULL;					
+                }
+				else
+				{
+					SW_Timer_Info[i].SW_Timer_CallbackFunction();
+					SW_Timer_Info[i].SW_Timer_StartTick = nowTickCount;
+				}
+            }
+        }
+    }
+}
+
diff --git a/Project/Application/sw_timer.h b/Project/Application/sw_timer.h
new file mode 100644
index 0000000..64221fd
--- /dev/null
+++ b/Project/Application/sw_timer.h
@@ -0,0 +1,25 @@
+/** \file sw_timer.h */ 
+#if !defined(SW_TIMER_H__8AF06FDD_AC0A_4693_88C3_8ACCF1AB4372__INCLUDED_)
+#define SW_TIMER_H__8AF06FDD_AC0A_4693_88C3_8ACCF1AB4372__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+
+#define MAX_SW_TIMER_REGISTER_COUNT     10
+
+typedef enum
+{
+    SW_TIMER_RUN_NONE,
+    SW_TIMER_RUN_ONNY_ONCE,
+    SW_TIMER_RUN_CONTINUE,    
+}SW_TIMER_CALLBACK_TYPE;
+
+typedef void (*SW_TIMER_CALLBACK_FN) (void);
+
+
+bool SW_Timer_Callback_Register(SW_TIMER_CALLBACK_TYPE type, uint32_t PeriodTime, SW_TIMER_CALLBACK_FN pTimerCallback);
+bool SW_Timer_Callback_UnRegister(SW_TIMER_CALLBACK_FN pSwTimerCallbackFunc);
+void SW_Timer_Callback_Process(void);
+
+#endif
diff --git a/Project/Application/systick_timer.c b/Project/Application/systick_timer.c
new file mode 100644
index 0000000..bded962
--- /dev/null
+++ b/Project/Application/systick_timer.c
@@ -0,0 +1,31 @@
+#include "systick_timer.h"
+
+
+static uint32_t tick_count;
+volatile uint32_t nDelayCount;
+/*-------------------------------------------------------------------------*//**
+ * @brief         This function handles SysTick Handler.
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void SysTick_Handler( void )
+{
+    tick_count++;    
+    if(nDelayCount != 0)
+    {
+        nDelayCount--;
+    }
+}
+
+
+uint32_t millis(void)
+{
+    return tick_count;
+}
+
+
+void Delay_ms(uint32_t nDelay)
+{
+    nDelayCount = nDelay;
+    while(nDelayCount != 0);
+}
diff --git a/Project/Application/systick_timer.h b/Project/Application/systick_timer.h
new file mode 100644
index 0000000..946712b
--- /dev/null
+++ b/Project/Application/systick_timer.h
@@ -0,0 +1,10 @@
+/** \file systick_timer.h */ 
+#if !defined(SYSTICK_TIMER_H__5F17ECEC_79B1_4DE4_9B38_A54E0782477E__INCLUDED_)
+#define SYSTICK_TIMER_H__5F17ECEC_79B1_4DE4_9B38_A54E0782477E__INCLUDED_
+
+#include "define.h"
+
+uint32_t millis(void);
+void Delay_ms(uint32_t nDelay);
+
+#endif
diff --git a/Project/Application/timer12.c b/Project/Application/timer12.c
new file mode 100644
index 0000000..03065e0
--- /dev/null
+++ b/Project/Application/timer12.c
@@ -0,0 +1,66 @@
+#include "timer12.h"
+#include "gpio_state_led.h"
+
+#define TIMER1n_PERIPHERAL               TIMER12
+#define TIMER1n_IRQ_TYPE                 TIMER12_IRQn
+#define TIMER1n_INTERRUPT_MASK           MSK_TIMER12
+
+
+static TIMER_CALLBACK Timer12_Match_Callback = NULL;
+
+
+
+
+
+void Timer12_Initialization(void)
+{
+    TIMER1n_PERIODICCFG_Type TIMER1n_Config;
+	
+	TIMER1n_Config.CkSel = TIMER1n_PCLK;               // PCLK = 40MHz
+    TIMER1n_Config.Prescaler = 40;                     // fTIMER = PCLK / 40 = 1MHz
+    TIMER1n_Config.ADR = ( 1000 );                     // Period  = ADR / fTIMER = 1000us
+    TIMER1n_Config.StartLevel = TIMER1n_START_LOW;
+    TIMER1n_Config.BDR = 0;                            // Duty(B) = BDR / fTIMER =    0us  // dummy parameter
+    TIMER1n_Config.ECE = TIMER1n_FALLING_EGDE;         // dummy parameter
+
+	HAL_TIMER1n_Init((TIMER1n_Type*)TIMER1n_PERIPHERAL, TIMER1n_PERIODIC_MODE, &TIMER1n_Config);
+    HAL_TIMER1n_ConfigInterrupt((TIMER1n_Type*)TIMER1n_PERIPHERAL, TIMER1n_INTCFG_MIE, ENABLE);
+
+   NVIC_SetPriority(TIMER1n_IRQ_TYPE, 3);
+   NVIC_EnableIRQ(TIMER1n_IRQ_TYPE);
+   HAL_INT_EInt_MaskDisable(TIMER1n_INTERRUPT_MASK);
+
+   HAL_TIMER1n_Cmd((TIMER1n_Type*)TIMER1n_PERIPHERAL, ENABLE );   // timer start & clear
+}
+
+   
+void Timer12_Set_Match_Interrupt_Callback(TIMER_CALLBACK Callback)
+{
+    Timer12_Match_Callback = Callback;
+}
+   
+
+
+
+
+
+
+/*----------------- INTERRUPT SERVICE ROUTINES --------------------------*/
+/*********************************************************************//**
+ * @brief		Timer12 interrupt handler sub-routine
+ * @param[in]	None
+ * @return 		None
+ **********************************************************************/
+void TIMER12_Handler(void)
+{
+	// TODO : Type your code here    
+    uint32_t status;	
+    status = T1nMaInt_GetFg(TIMER1n_PERIPHERAL);    
+	if (status == 1)
+    {
+        T1nMaInt_ClrFg(TIMER1n_PERIPHERAL);                
+        if(Timer12_Match_Callback != NULL)
+            Timer12_Match_Callback();        
+	}         
+}
+
diff --git a/Project/Application/timer12.h b/Project/Application/timer12.h
new file mode 100644
index 0000000..38f00df
--- /dev/null
+++ b/Project/Application/timer12.h
@@ -0,0 +1,13 @@
+/** \file timer12.h */ 
+#if !defined(TIMER12_H__2923006F_3CBC_45ED_8A7D_C04AC01E9281__INCLUDED_)
+#define TIMER12_H__2923006F_3CBC_45ED_8A7D_C04AC01E9281__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+typedef void (*TIMER_CALLBACK)(void);
+
+void Timer12_Initialization(void);
+void Timer12_Set_Match_Interrupt_Callback(TIMER_CALLBACK Callback);
+
+#endif
diff --git a/Project/Application/uart.h b/Project/Application/uart.h
new file mode 100644
index 0000000..e792ce6
--- /dev/null
+++ b/Project/Application/uart.h
@@ -0,0 +1,36 @@
+/** \file uart.h */ 
+#if !defined(UART_H__06447B60_D695_412E_90C8_93147FA649B9__INCLUDED_)
+#define UART_H__06447B60_D695_412E_90C8_93147FA649B9__INCLUDED_
+
+#include "define.h"
+#include "struct.h"
+#include "ringbuffer.h"
+
+void Uart1_Initialization(uint32_t Baudrate);
+void Uart1_Receive_Process(void);
+void Uart1_Transmit(uint8_t TxData);
+
+
+void Usart10_Initialization(uint32_t Baudrate);
+void Usart10_Receive_Process(void);
+void Usart10_Transmit(uint8_t TxData);
+
+void Usart10_Transmit_Process(void);
+void Usart10_Transmit_DataPush(uint8_t TxData);
+void Usart10_Recv_Complete_TimeCheck_Process(void);
+void Usart10_Transmit_Check_Process(void);
+
+void Usart11_Initialization(uint32_t Baudrate);
+void Usart11_Receive_Process(void);
+void Usart11_Transmit(uint8_t TxData);
+
+
+void Usart13_Initialization(uint32_t Baudrate);
+void Usart13_Receive_Process(void);
+void Usart13_Transmit(uint8_t TxData);
+
+
+
+
+
+#endif
diff --git a/Project/Application/uart1.c b/Project/Application/uart1.c
new file mode 100644
index 0000000..d157d9b
--- /dev/null
+++ b/Project/Application/uart1.c
@@ -0,0 +1,261 @@
+#include "uart1.h"
+#include "sw_timer.h"
+#include "ring_buffer.h"
+
+
+#define UARTn_TX_INTERRUTP_ENABLE       FALSE
+
+
+#define UARTn_PERIPHERAL                UART1
+#define UARTn_INTERRUPT_HANDLER         UART1_IRQn
+#define UARTn_INTERRUPT_MASK            MSK_UART1
+#define UARTn_INTERRUPT_PRIORITY        3
+#define UARTn_TX_PORT                   PB
+#define UARTn_TX_PIN_NUM                6      
+#define UARTn_RX_PORT                   PB
+#define UARTn_RX_PIN_NUM                7
+
+#define UARTn_TX_BUFFER_SIZE            200
+#define UARTn_RX_BUFFER_SIZE            100
+
+
+
+static uint8_t Tx_Buffer[UARTn_TX_BUFFER_SIZE];
+static uint8_t Rx_Buffer[UARTn_RX_BUFFER_SIZE];
+static RING_BUFFER RingBuffer_Tx;
+static RING_BUFFER RingBuffer_Rx;
+
+
+#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
+    static volatile uint8_t Uartn_TxIntEnable = FALSE;
+    static void Uart1_Init_TransmitSet(void);
+#else
+    static void Uart1_Transmit_Process(void);
+#endif
+
+
+
+static void Uart1_Receive_Handler(void);
+
+
+void Uart1_Initialization(uint32_t Baudrate, UARTn_DATA_BIT_Type Databit, UARTn_PARITY_BIT_Type Paritybit, UARTn_STOP_BIT_Type Stopbit)
+{
+    UARTn_CFG_Type    UARTn_Config;
+
+   /*
+    * Initialize UART0 pin connect
+    */
+    HAL_GPIO_ConfigOutput((Pn_Type*)UARTn_RX_PORT,   UARTn_RX_PIN_NUM, ALTERN_FUNC );
+    HAL_GPIO_ConfigFunction((Pn_Type*)UARTn_RX_PORT, UARTn_RX_PIN_NUM, AFSRx_AF1 );
+    HAL_GPIO_ConfigPullup((Pn_Type*)UARTn_RX_PORT,   UARTn_RX_PIN_NUM, PUPDx_EnablePU );
+
+    HAL_GPIO_ConfigOutput((Pn_Type*)UARTn_TX_PORT,   UARTn_TX_PIN_NUM, ALTERN_FUNC );
+    HAL_GPIO_ConfigFunction((Pn_Type*)UARTn_TX_PORT, UARTn_TX_PIN_NUM, AFSRx_AF1 );
+
+    // default: 38400-8-N-1
+    HAL_UART_ConfigStructInit(&UARTn_Config);
+    UARTn_Config.Baudrate = Baudrate;
+    UARTn_Config.Databits = Databit;
+    UARTn_Config.Parity = Paritybit;
+    UARTn_Config.Stopbits = Stopbit;
+
+    HAL_UART_Init((UARTn_Type*)UARTn_PERIPHERAL, &UARTn_Config);
+
+    /* Enable UART Rx interrupt */
+    HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_RBR, ENABLE );
+
+#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
+    // Reset Tx Interrupt state
+    Uartn_TxIntEnable = RESET;
+#else
+    SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 0, Uart1_Transmit_Process);
+#endif
+   
+    RingBuffer_Initialization(&RingBuffer_Rx, false, UARTn_RX_BUFFER_SIZE, &Rx_Buffer[0]);
+    RingBuffer_Initialization(&RingBuffer_Tx, false, UARTn_TX_BUFFER_SIZE, &Tx_Buffer[0]);
+
+    NVIC_SetPriority(UARTn_INTERRUPT_HANDLER, UARTn_INTERRUPT_PRIORITY);
+    NVIC_EnableIRQ(UARTn_INTERRUPT_HANDLER );
+    HAL_INT_EInt_MaskDisable(UARTn_INTERRUPT_MASK);
+}
+
+
+
+void Uart1_Transmit(uint8_t TxData)
+{    
+#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
+    /* Temporarily lock out UART transmit interrupts during this read so the UART transmit interrupt won't cause problems with the index values */
+    HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_THRE, DISABLE );
+
+    RingBuffer_Enqueue(&RingBuffer_Tx, TxData);
+
+    /*
+    * Check if current Tx interrupt enable is reset,
+    * that means the Tx interrupt must be re-enabled
+    * due to call IntTransmit() function to trigger
+    * this interrupt type
+    */
+    if(Uartn_TxIntEnable == RESET)
+    {
+        Uart1_Init_TransmitSet();
+    }
+    /*
+    * Otherwise, re-enables Tx Interrupt
+    */
+    else
+    {
+        HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_THRE, ENABLE );
+    }
+#else
+    RingBuffer_Enqueue(&RingBuffer_Tx, TxData);
+#endif        
+}
+
+
+
+void Uart1_TransmitData(uint8_t* pTxData, uint32_t TxLen)
+{
+    uint32_t i;
+#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)    
+    HAL_UART_ConfigInterrupt( ( UARTn_Type* )UARTn_PERIPHERAL, UARTn_INTCFG_THRE, DISABLE );
+
+    for(i = 0 ; i < TxLen ; i++)
+        RingBuffer_Enqueue(&RingBuffer_Tx, pTxData[i]);
+    
+    if(Uartn_TxIntEnable == RESET)
+    {
+        Uart1_Init_TransmitSet();
+    }    
+    else
+    {
+        HAL_UART_ConfigInterrupt( ( UARTn_Type* )UARTn_PERIPHERAL, UARTn_INTCFG_THRE, ENABLE );
+    }
+#else
+    for(i = 0 ; i < TxLen ; i++)
+        RingBuffer_Enqueue(&RingBuffer_Tx, pTxData[i]);
+#endif
+}
+
+
+#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)    
+static void Uart1_Init_TransmitSet(void)
+{
+    // Disable THRE interrupt
+    HAL_UART_ConfigInterrupt( ( UARTn_Type* )UARTn_PERIPHERAL, UARTn_INTCFG_THRE, DISABLE );
+
+    /* Wait until THR empty */
+    while( HAL_UART_CheckBusy( ( UARTn_Type* )UARTn_PERIPHERAL ) == SET );
+
+    while(RingBuffer_Get_DataSize(&RingBuffer_Tx) != 0)
+    {
+        uint8_t TxData;
+        RingBuffer_GetData(&RingBuffer_Tx, &TxData);
+
+        if(HAL_UART_Transmit( ( UARTn_Type* )UARTn_PERIPHERAL, &TxData, 1, NONE_BLOCKING ) )
+        {
+            /* Update transmit ring FIFO tail pointer */
+            RingBuffer_PopData(&RingBuffer_Tx);
+            break;
+        }
+        else
+        {
+            break;
+        }
+    }
+   
+    /* If there is no more data to send, disable the transmit interrupt - else enable it or keep it enabled */
+    if(RingBuffer_Get_DataSize(&RingBuffer_Tx) == 0)
+    {
+        HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_THRE, DISABLE );
+        // Reset Tx Interrupt state
+        Uartn_TxIntEnable = RESET;
+    }
+    else
+    {
+        // Set Tx Interrupt state
+        Uartn_TxIntEnable = SET;
+        HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_THRE, ENABLE );
+    }
+}
+#else
+static void Uart1_Transmit_Process(void)
+{
+    if(RingBuffer_Get_DataSize(&RingBuffer_Tx) != 0)
+    {
+        uint8_t TxData;
+        RingBuffer_GetData(&RingBuffer_Tx, &TxData);
+         
+        if(HAL_UART_Transmit((UARTn_Type*)UARTn_PERIPHERAL, &TxData, 1, NONE_BLOCKING))
+        {
+            /* Update transmit ring FIFO tail pointer */
+            RingBuffer_PopData(&RingBuffer_Tx);            
+        }
+    }   
+}
+#endif
+
+
+static void Uart1_Receive_Handler(void)
+{
+	uint8_t tmpc;
+	uint32_t rLen;
+
+	while(1)
+    {
+        rLen = HAL_UART_Receive((UARTn_Type*)UARTn_PERIPHERAL, &tmpc, 1, NONE_BLOCKING );
+		if (rLen)
+        {       
+            RingBuffer_Enqueue(&RingBuffer_Rx, tmpc);
+		}		
+		else 
+        {
+			break;
+		}
+	}
+}
+
+/*********************************************************************//**
+ * @brief		UART1 interrupt handler sub-routine
+ * @param[in]	None
+ * @return 		None
+ **********************************************************************/
+void UART1_Handler(void)
+{
+	uint32_t intsrc, tmp;
+
+	/* Determine the interrupt source */
+	intsrc = UARTn_PERIPHERAL->IIR;    
+	tmp = intsrc & UARTn_IIR_INTID_MASK;
+    
+
+	// Receiver Line Status
+	if(tmp == UARTn_IIR_INTID_RLS) // error(Overrun, Parity, Framing or Break Error)
+    {		
+	}
+    else if(tmp == UARTn_IIR_INTID_RDA) // Receiver Data Available
+    {
+        Uart1_Receive_Handler();
+    }
+    else if(tmp == UARTn_IIR_INTID_THRE) // Transmitter Holding Register Empty
+    {
+#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)    
+        Uart1_Init_TransmitSet();
+#endif        
+    }
+    else if(tmp == UARTn_IIR_INTID_TXE) // Transmitter Register Empty
+    {
+    }
+}
+
+
+uint32_t Uart1_Get_RecvDataCount(void)
+{
+    return RingBuffer_Get_DataSize(&RingBuffer_Rx);
+}
+
+uint8_t Uart1_Get_RecvData(void)
+{
+    uint8_t retData;
+    RingBuffer_Dequeue(&RingBuffer_Rx, &retData);     
+    return retData;
+}
diff --git a/Project/Application/uart1.h b/Project/Application/uart1.h
new file mode 100644
index 0000000..0ad4440
--- /dev/null
+++ b/Project/Application/uart1.h
@@ -0,0 +1,15 @@
+/** \file uart1.h */ 
+#if !defined(UART1_H__A3672F4B_1033_433E_A296_1444C586906C__INCLUDED_)
+#define UART1_H__A3672F4B_1033_433E_A296_1444C586906C__INCLUDED_
+
+#include "board_config.h"
+#include "define.h"
+
+
+void Uart1_Initialization(uint32_t Baudrate, UARTn_DATA_BIT_Type Databit, UARTn_PARITY_BIT_Type Paritybit, UARTn_STOP_BIT_Type Stopbit);
+void Uart1_Transmit(uint8_t TxData);
+void Uart1_TransmitData(uint8_t* pTxData, uint32_t TxLen);
+uint32_t Uart1_Get_RecvDataCount(void);
+uint8_t Uart1_Get_RecvData(void);
+
+#endif
diff --git a/Project/Application/uart_packet.c b/Project/Application/uart_packet.c
new file mode 100644
index 0000000..7f88dc0
--- /dev/null
+++ b/Project/Application/uart_packet.c
@@ -0,0 +1,145 @@
+#include "uart_packet.h"
+#include "sw_timer.h"
+#include "uart1.h"
+#include "driver_ds3231_basic.h"
+#include "buzzer.h"
+
+
+#define PACKET_BUFF_SIZE    100
+
+
+static void Uart_Packet_Make_Process(void);
+static void Uart_Packet_Process(uint8_t* pRxBuff);
+
+static uint8_t Pack_Buff[PACKET_BUFF_SIZE];
+static uint8_t Pack_Index;
+static uint8_t Pack_CheckSum;
+static uint8_t Pack_DataLen;
+
+void Uart_Packet_Initialization(void)
+{
+    Pack_Index = 0;
+    SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 0, Uart_Packet_Make_Process);
+}
+
+
+
+
+
+static void Uart_Packet_Make_Process(void)
+{
+    if(Uart1_Get_RecvDataCount() != 0)
+    {
+        uint8_t RxData = Uart1_Get_RecvData();
+
+        if(Pack_Index == PACK_INDEX_STX && RxData == STX)
+        {
+            Pack_Buff[Pack_Index++] = RxData;
+            Pack_CheckSum = RxData;
+            Pack_DataLen = 0;
+        }
+        else if(Pack_Index == PACK_INDEX_CMD && (RxData >= UART_CMD_SET_TIME && RxData < UART_CMD_MAX))
+        {
+            Pack_Buff[Pack_Index++] = RxData;
+            Pack_CheckSum += RxData;
+        }
+        else if(Pack_Index == PACK_INDEX_LEN && RxData < (PACKET_BUFF_SIZE - PACK_INDEX_ETX))
+        {
+            Pack_Buff[Pack_Index++] = RxData;
+            Pack_CheckSum += RxData;
+            Pack_DataLen = RxData;
+        }
+        else if(Pack_Index == (PACK_INDEX_CHECKSUM + Pack_DataLen))
+        {
+            if(RxData != Pack_CheckSum)
+            {
+                Pack_Index = 0;
+            }
+            else
+            {
+                Pack_Buff[Pack_Index++] = RxData;
+            }            
+        }
+        else if(Pack_Index == (PACK_INDEX_ETX + Pack_DataLen))
+        {
+            if(RxData != ETX)
+            {
+                Pack_Index = 0;
+            }
+            else
+            {
+                Pack_Buff[Pack_Index++] = RxData;
+                Uart_Packet_Process(Pack_Buff);
+                Pack_Index = 0;
+            }
+            
+        }
+        else if(Pack_Index >= PACK_INDEX_DATA && Pack_Index < (PACK_INDEX_DATA + Pack_DataLen))
+        {
+            Pack_Buff[Pack_Index++] = RxData;
+            Pack_CheckSum += RxData;
+        }
+        else
+        {
+            Pack_Index = 0;
+        }
+    }
+}
+
+
+static void Uart_Packet_Process(uint8_t* pRxBuff)
+{
+    UART_CMD cmd = pRxBuff[PACK_INDEX_CMD];
+    uint8_t DataLen = pRxBuff[PACK_INDEX_LEN];
+
+    if(cmd == UART_CMD_SET_TIME && DataLen == 7)
+    {
+        uint16_t Year;
+        uint8_t Month;
+        uint8_t Date;
+        uint8_t Hour;
+        uint8_t Min;
+        uint8_t Sec;
+        uint8_t index = 0;
+        ds3231_time_t set_time;         
+        ds3231_basic_get_time(&set_time);
+
+        Year = pRxBuff[PACK_INDEX_DATA + index++] << 8;
+        Year += pRxBuff[PACK_INDEX_DATA + index++];
+        Month = pRxBuff[PACK_INDEX_DATA + index++];
+        Date = pRxBuff[PACK_INDEX_DATA + index++];
+        Hour = pRxBuff[PACK_INDEX_DATA + index++];
+        Min = pRxBuff[PACK_INDEX_DATA + index++];
+        Sec = pRxBuff[PACK_INDEX_DATA + index++];
+
+        set_time.format = DS3231_FORMAT_24H;
+        set_time.year = Year;
+        set_time.month = Month;
+        set_time.date = Date;
+        set_time.hour = Hour;
+        set_time.minute = Min;
+        set_time.second = Sec;       
+
+        // year 2, mon 1, da 1 , h 1, m1, s 1
+        ds3231_basic_set_time(&set_time);
+
+        Buzzer_On(100);
+    }
+
+
+
+
+
+
+}
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Project/Application/uart_packet.h b/Project/Application/uart_packet.h
new file mode 100644
index 0000000..153b205
--- /dev/null
+++ b/Project/Application/uart_packet.h
@@ -0,0 +1,32 @@
+/** \file uart_packet.h */ 
+#if !defined(UART_PACKET_H__4C114ACB_4130_48D0_A3D5_EF34FC3189D2__INCLUDED_)
+#define UART_PACKET_H__4C114ACB_4130_48D0_A3D5_EF34FC3189D2__INCLUDED_
+
+#include "define.h"
+#include "board_config.h"
+
+
+#define STX 0x02
+#define ETX 0x03
+
+typedef enum
+{
+    PACK_INDEX_STX          = 0x00,
+    PACK_INDEX_CMD          = 0x01,
+    PACK_INDEX_LEN          = 0x02,
+    PACK_INDEX_DATA         = 0x03,
+    PACK_INDEX_CHECKSUM     = 0x03,
+    PACK_INDEX_ETX          = 0x04,
+}PACKET_INDEX;
+
+typedef enum
+{
+    UART_CMD_SET_TIME = 0x00,
+    UART_CMD_MAX,
+}UART_CMD;
+
+
+void Uart_Packet_Initialization(void);
+
+
+#endif
diff --git a/Project/EventRecorderStub.scvd b/Project/EventRecorderStub.scvd
new file mode 100644
index 0000000..2956b29
--- /dev/null
+++ b/Project/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>
diff --git a/Project/Listings/S_DustSensorView.map b/Project/Listings/S_DustSensorView.map
new file mode 100644
index 0000000..c000a61
--- /dev/null
+++ b/Project/Listings/S_DustSensorView.map
@@ -0,0 +1,2476 @@
+Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601]
+
+==============================================================================
+
+Section Cross References
+
+    a31g12x_systemclock.o(i.System_Clock_Initialization) refers to a31g12x_hal_scu.o(i.HAL_SCU_ClockSource_Enable) for HAL_SCU_ClockSource_Enable
+    a31g12x_systemclock.o(i.System_Clock_Initialization) refers to a31g12x_hal_scu.o(i.HAL_SCU_SystemClockChange) for HAL_SCU_SystemClockChange
+    a31g12x_systemclock.o(i.System_Clock_Initialization) refers to a31g12x_hal_scu.o(i.HAL_SCU_SystemClockDivider) for HAL_SCU_SystemClockDivider
+    a31g12x_systemclock.o(i.System_Clock_Initialization) refers to a31g12x_hal_scu.o(i.HAL_SCU_ClockMonitoring) for HAL_SCU_ClockMonitoring
+    a31g12x_systemclock.o(i.System_Clock_Initialization) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_ClockConfig) for HAL_SCU_Peripheral_ClockConfig
+    a31g12x_systemclock.o(i.System_Clock_Initialization) refers to system_a31g12x.o(.data) for SystemCoreClock
+    a31g12x_systemclock.o(i.Systick_Initialization) refers to uidiv.o(.text) for __aeabi_uidivmod
+    a31g12x_systemclock.o(i.Systick_Initialization) refers to a31g12x_systemclock.o(i.NVIC_SetPriority) for NVIC_SetPriority
+    a31g12x_systemclock.o(i.Systick_Initialization) refers to system_a31g12x.o(.data) for SystemCoreClock
+    main.o(i.main) refers to a31g12x_systemclock.o(i.System_Clock_Initialization) for System_Clock_Initialization
+    main.o(i.main) refers to a31g12x_systemclock.o(i.Systick_Initialization) for Systick_Initialization
+    main.o(i.main) refers to eeprom.o(i.FlashMEM_Clock_Initialization) for FlashMEM_Clock_Initialization
+    main.o(i.main) refers to timer12.o(i.Timer12_Initialization) for Timer12_Initialization
+    main.o(i.main) refers to uart1.o(i.Uart1_Initialization) for Uart1_Initialization
+    main.o(i.main) refers to spi10.o(i.SPI10_Initialization) for SPI10_Initialization
+    main.o(i.main) refers to gpio_state_led.o(i.Gpio_StateLed_Initialization) for Gpio_StateLed_Initialization
+    main.o(i.main) refers to gpio_switch.o(i.Gpio_Switch_Port_Initialization) for Gpio_Switch_Port_Initialization
+    main.o(i.main) refers to gpio_sensor.o(i.Gpio_Sensor_PWR_Initialization) for Gpio_Sensor_PWR_Initialization
+    main.o(i.main) refers to gpio_i2c.o(i.GPIO_I2C0_Initialization) for GPIO_I2C0_Initialization
+    main.o(i.main) refers to gpio_i2c.o(i.GPIO_I2C1_Initialization) for GPIO_I2C1_Initialization
+    main.o(i.main) refers to gpio_i2c.o(i.GPIO_I2C2_Initialization) for GPIO_I2C2_Initialization
+    main.o(i.main) refers to segment_74hc595d.o(i.Segment_Initialization) for Segment_Initialization
+    main.o(i.main) refers to rtc_process.o(i.RTC_Process_Initialization) for RTC_Process_Initialization
+    main.o(i.main) refers to buzzer.o(i.Buzzer_Initialization) for Buzzer_Initialization
+    main.o(i.main) refers to action_process.o(i.Action_Initialization) for Action_Initialization
+    main.o(i.main) refers to uart_packet.o(i.Uart_Packet_Initialization) for Uart_Packet_Initialization
+    main.o(i.main) refers to sw_timer.o(i.SW_Timer_Callback_Register) for SW_Timer_Callback_Register
+    main.o(i.main) refers to sw_timer.o(i.SW_Timer_Callback_Process) for SW_Timer_Callback_Process
+    main.o(i.main) refers to main.o(i.timer_test) for timer_test
+    dbg_printf.o(i.fputc) refers to uart1.o(i.Uart1_Transmit) for Uart1_Transmit
+    sw_timer.o(i.SW_Timer_Callback_Process) refers to systick_timer.o(i.millis) for millis
+    sw_timer.o(i.SW_Timer_Callback_Process) refers to sw_timer.o(.bss) for SW_Timer_Info
+    sw_timer.o(i.SW_Timer_Callback_Register) refers to systick_timer.o(i.millis) for millis
+    sw_timer.o(i.SW_Timer_Callback_Register) refers to sw_timer.o(.bss) for SW_Timer_Info
+    sw_timer.o(i.SW_Timer_Callback_UnRegister) refers to sw_timer.o(.bss) for SW_Timer_Info
+    systick_timer.o(i.Delay_ms) refers to systick_timer.o(.data) for nDelayCount
+    systick_timer.o(i.SysTick_Handler) refers to systick_timer.o(.data) for tick_count
+    systick_timer.o(i.millis) refers to systick_timer.o(.data) for tick_count
+    ring_buffer.o(i.RingBuffer_Dequeue) refers to ring_buffer.o(i.RingBuffer_isEmpty) for RingBuffer_isEmpty
+    ring_buffer.o(i.RingBuffer_Dequeue) refers to uidiv.o(.text) for __aeabi_uidivmod
+    ring_buffer.o(i.RingBuffer_Enqueue) refers to ring_buffer.o(i.RingBuffer_isFull) for RingBuffer_isFull
+    ring_buffer.o(i.RingBuffer_Enqueue) refers to ring_buffer.o(i.RingBuffer_Dequeue) for RingBuffer_Dequeue
+    ring_buffer.o(i.RingBuffer_Enqueue) refers to uidiv.o(.text) for __aeabi_uidivmod
+    ring_buffer.o(i.RingBuffer_Get_DataSize) refers to ring_buffer.o(i.RingBuffer_isEmpty) for RingBuffer_isEmpty
+    ring_buffer.o(i.RingBuffer_PopData) refers to uidiv.o(.text) for __aeabi_uidivmod
+    gpio_state_led.o(i.Gpio_StateLed_Get_Mode) refers to gpio_state_led.o(.data) for StateLedMode
+    gpio_state_led.o(i.Gpio_StateLed_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_state_led.o(i.Gpio_StateLed_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    gpio_state_led.o(i.Gpio_StateLed_Initialization) refers to gpio_state_led.o(i.Gpio_StateLed_Set_Mode) for Gpio_StateLed_Set_Mode
+    gpio_state_led.o(i.Gpio_StateLed_Initialization) refers to sw_timer.o(i.SW_Timer_Callback_Register) for SW_Timer_Callback_Register
+    gpio_state_led.o(i.Gpio_StateLed_Initialization) refers to gpio_state_led.o(i.State_Led_Output_Process) for State_Led_Output_Process
+    gpio_state_led.o(i.Gpio_StateLed_Set_Mode) refers to gpio_state_led.o(.data) for StateLedMode
+    gpio_state_led.o(i.State_Led_Output_Process) refers to systick_timer.o(i.millis) for millis
+    gpio_state_led.o(i.State_Led_Output_Process) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_state_led.o(i.State_Led_Output_Process) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_state_led.o(i.State_Led_Output_Process) refers to gpio_state_led.o(.data) for StateLedStep
+    gpio_switch.o(i.Gpio_Switch_Check_Process) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ReadPin) for HAL_GPIO_ReadPin
+    gpio_switch.o(i.Gpio_Switch_Check_Process) refers to gpio_switch.o(.data) for KeyCheckInfo
+    gpio_switch.o(i.Gpio_Switch_Port_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_switch.o(i.Gpio_Switch_Port_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    gpio_switch.o(i.Gpio_Switch_Port_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetDebouncePin) for HAL_GPIO_SetDebouncePin
+    gpio_switch.o(i.Gpio_Switch_Port_Initialization) refers to sw_timer.o(i.SW_Timer_Callback_Register) for SW_Timer_Callback_Register
+    gpio_switch.o(i.Gpio_Switch_Port_Initialization) refers to gpio_switch.o(i.Gpio_Switch_Check_Process) for Gpio_Switch_Check_Process
+    gpio_switch.o(i.Gpio_Swtich_Set_Callback) refers to gpio_switch.o(.data) for KeyCheckInfo
+    gpio_switch.o(i.Gpio_Swtich_Set_PushCount) refers to gpio_switch.o(.data) for KeyCheckInfo
+    uart1.o(i.UART1_Handler) refers to uart1.o(i.Uart1_Receive_Handler) for Uart1_Receive_Handler
+    uart1.o(i.Uart1_Get_RecvData) refers to ring_buffer.o(i.RingBuffer_Dequeue) for RingBuffer_Dequeue
+    uart1.o(i.Uart1_Get_RecvData) refers to uart1.o(.bss) for RingBuffer_Rx
+    uart1.o(i.Uart1_Get_RecvDataCount) refers to ring_buffer.o(i.RingBuffer_Get_DataSize) for RingBuffer_Get_DataSize
+    uart1.o(i.Uart1_Get_RecvDataCount) refers to uart1.o(.bss) for RingBuffer_Rx
+    uart1.o(i.Uart1_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    uart1.o(i.Uart1_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigFunction) for HAL_GPIO_ConfigFunction
+    uart1.o(i.Uart1_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    uart1.o(i.Uart1_Initialization) refers to a31g12x_hal_uartn.o(i.HAL_UART_ConfigStructInit) for HAL_UART_ConfigStructInit
+    uart1.o(i.Uart1_Initialization) refers to a31g12x_hal_uartn.o(i.HAL_UART_Init) for HAL_UART_Init
+    uart1.o(i.Uart1_Initialization) refers to a31g12x_hal_uartn.o(i.HAL_UART_ConfigInterrupt) for HAL_UART_ConfigInterrupt
+    uart1.o(i.Uart1_Initialization) refers to sw_timer.o(i.SW_Timer_Callback_Register) for SW_Timer_Callback_Register
+    uart1.o(i.Uart1_Initialization) refers to ring_buffer.o(i.RingBuffer_Initialization) for RingBuffer_Initialization
+    uart1.o(i.Uart1_Initialization) refers to uart1.o(i.NVIC_SetPriority) for NVIC_SetPriority
+    uart1.o(i.Uart1_Initialization) refers to a31g12x_hal_intc.o(i.HAL_INT_EInt_MaskDisable) for HAL_INT_EInt_MaskDisable
+    uart1.o(i.Uart1_Initialization) refers to uart1.o(i.Uart1_Transmit_Process) for Uart1_Transmit_Process
+    uart1.o(i.Uart1_Initialization) refers to uart1.o(.bss) for Rx_Buffer
+    uart1.o(i.Uart1_Receive_Handler) refers to a31g12x_hal_uartn.o(i.HAL_UART_Receive) for HAL_UART_Receive
+    uart1.o(i.Uart1_Receive_Handler) refers to ring_buffer.o(i.RingBuffer_Enqueue) for RingBuffer_Enqueue
+    uart1.o(i.Uart1_Receive_Handler) refers to uart1.o(.bss) for RingBuffer_Rx
+    uart1.o(i.Uart1_Transmit) refers to ring_buffer.o(i.RingBuffer_Enqueue) for RingBuffer_Enqueue
+    uart1.o(i.Uart1_Transmit) refers to uart1.o(.bss) for RingBuffer_Tx
+    uart1.o(i.Uart1_TransmitData) refers to ring_buffer.o(i.RingBuffer_Enqueue) for RingBuffer_Enqueue
+    uart1.o(i.Uart1_TransmitData) refers to uart1.o(.bss) for RingBuffer_Tx
+    uart1.o(i.Uart1_Transmit_Process) refers to ring_buffer.o(i.RingBuffer_Get_DataSize) for RingBuffer_Get_DataSize
+    uart1.o(i.Uart1_Transmit_Process) refers to ring_buffer.o(i.RingBuffer_GetData) for RingBuffer_GetData
+    uart1.o(i.Uart1_Transmit_Process) refers to a31g12x_hal_uartn.o(i.HAL_UART_Transmit) for HAL_UART_Transmit
+    uart1.o(i.Uart1_Transmit_Process) refers to ring_buffer.o(i.RingBuffer_PopData) for RingBuffer_PopData
+    uart1.o(i.Uart1_Transmit_Process) refers to uart1.o(.bss) for RingBuffer_Tx
+    segment_74hc595d.o(i.Segemet_Output_Process) refers to memseta.o(.text) for __aeabi_memclr
+    segment_74hc595d.o(i.Segemet_Output_Process) refers to systick_timer.o(i.millis) for millis
+    segment_74hc595d.o(i.Segemet_Output_Process) refers to segment_74hc595d.o(i.__ARM_common_switch8) for __ARM_common_switch8
+    segment_74hc595d.o(i.Segemet_Output_Process) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    segment_74hc595d.o(i.Segemet_Output_Process) refers to segment_74hc595d.o(i.Segment_Output_Data) for Segment_Output_Data
+    segment_74hc595d.o(i.Segemet_Output_Process) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    segment_74hc595d.o(i.Segemet_Output_Process) refers to segment_74hc595d.o(.data) for HC595_OutputData
+    segment_74hc595d.o(i.Segemet_Output_Process) refers to segment.o(.bss) for Segment_OutputBuff
+    segment_74hc595d.o(i.Segment_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    segment_74hc595d.o(i.Segment_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    segment_74hc595d.o(i.Segment_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    segment_74hc595d.o(i.Segment_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    segment_74hc595d.o(i.Segment_Initialization) refers to systick_timer.o(i.millis) for millis
+    segment_74hc595d.o(i.Segment_Initialization) refers to timer12.o(i.Timer12_Set_Match_Interrupt_Callback) for Timer12_Set_Match_Interrupt_Callback
+    segment_74hc595d.o(i.Segment_Initialization) refers to segment_74hc595d.o(.data) for ToggleTickCount
+    segment_74hc595d.o(i.Segment_Initialization) refers to segment_74hc595d.o(i.Segemet_Output_Process) for Segemet_Output_Process
+    segment_74hc595d.o(i.Segment_Output_Data) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    segment_74hc595d.o(i.Segment_Output_Data) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    segment_74hc595d.o(i.Segment_Output_Data) refers to segment_74hc595d.o(.data) for HC595_OutputMode
+    timer12.o(i.TIMER12_Handler) refers to timer12.o(.data) for Timer12_Match_Callback
+    timer12.o(i.Timer12_Initialization) refers to a31g12x_hal_timer1n.o(i.HAL_TIMER1n_Init) for HAL_TIMER1n_Init
+    timer12.o(i.Timer12_Initialization) refers to a31g12x_hal_timer1n.o(i.HAL_TIMER1n_ConfigInterrupt) for HAL_TIMER1n_ConfigInterrupt
+    timer12.o(i.Timer12_Initialization) refers to timer12.o(i.NVIC_SetPriority) for NVIC_SetPriority
+    timer12.o(i.Timer12_Initialization) refers to a31g12x_hal_intc.o(i.HAL_INT_EInt_MaskDisable) for HAL_INT_EInt_MaskDisable
+    timer12.o(i.Timer12_Initialization) refers to a31g12x_hal_timer1n.o(i.HAL_TIMER1n_Cmd) for HAL_TIMER1n_Cmd
+    timer12.o(i.Timer12_Set_Match_Interrupt_Callback) refers to timer12.o(.data) for Timer12_Match_Callback
+    gpio_i2c.o(i.GPIO_I2C0_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C0_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    gpio_i2c.o(i.GPIO_I2C0_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C0_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C0_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C0_Read) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C0_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C0_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C0_Start) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C0_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C0_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C0_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C0_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C0_Stop) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C0_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C0_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C0_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C0_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C0_Write) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C1_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C1_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    gpio_i2c.o(i.GPIO_I2C1_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C1_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C1_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C1_Read) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C1_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C1_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C1_Start) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C1_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C1_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C1_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C1_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C1_Stop) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C1_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C1_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C1_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C1_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C1_Write) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C2_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C2_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    gpio_i2c.o(i.GPIO_I2C2_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C2_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C2_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C2_Read) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C2_Read) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C2_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C2_Start) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C2_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C2_Start) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C2_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C2_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C2_Stop) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.GPIO_I2C2_Stop) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C2_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_i2c.o(i.GPIO_I2C2_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    gpio_i2c.o(i.GPIO_I2C2_Write) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    gpio_i2c.o(i.GPIO_I2C2_Write) refers to gpio_i2c.o(i.Delay_I2C_Delay) for Delay_I2C_Delay
+    gpio_i2c.o(i.I2C0_Read) refers to gpio_i2c.o(i.GPIO_I2C0_Start) for GPIO_I2C0_Start
+    gpio_i2c.o(i.I2C0_Read) refers to gpio_i2c.o(i.GPIO_I2C0_Write) for GPIO_I2C0_Write
+    gpio_i2c.o(i.I2C0_Read) refers to gpio_i2c.o(i.GPIO_I2C0_Read) for GPIO_I2C0_Read
+    gpio_i2c.o(i.I2C0_Read) refers to gpio_i2c.o(i.GPIO_I2C0_Stop) for GPIO_I2C0_Stop
+    gpio_i2c.o(i.I2C0_Write) refers to gpio_i2c.o(i.GPIO_I2C0_Start) for GPIO_I2C0_Start
+    gpio_i2c.o(i.I2C0_Write) refers to gpio_i2c.o(i.GPIO_I2C0_Write) for GPIO_I2C0_Write
+    gpio_i2c.o(i.I2C0_Write) refers to gpio_i2c.o(i.GPIO_I2C0_Stop) for GPIO_I2C0_Stop
+    gpio_i2c.o(i.I2C1_Read) refers to gpio_i2c.o(i.GPIO_I2C1_Start) for GPIO_I2C1_Start
+    gpio_i2c.o(i.I2C1_Read) refers to gpio_i2c.o(i.GPIO_I2C1_Write) for GPIO_I2C1_Write
+    gpio_i2c.o(i.I2C1_Read) refers to gpio_i2c.o(i.GPIO_I2C1_Read) for GPIO_I2C1_Read
+    gpio_i2c.o(i.I2C1_Read) refers to gpio_i2c.o(i.GPIO_I2C1_Stop) for GPIO_I2C1_Stop
+    gpio_i2c.o(i.I2C1_Write) refers to gpio_i2c.o(i.GPIO_I2C1_Start) for GPIO_I2C1_Start
+    gpio_i2c.o(i.I2C1_Write) refers to gpio_i2c.o(i.GPIO_I2C1_Write) for GPIO_I2C1_Write
+    gpio_i2c.o(i.I2C1_Write) refers to gpio_i2c.o(i.GPIO_I2C1_Stop) for GPIO_I2C1_Stop
+    gpio_i2c.o(i.I2C2_Read) refers to gpio_i2c.o(i.GPIO_I2C2_Start) for GPIO_I2C2_Start
+    gpio_i2c.o(i.I2C2_Read) refers to gpio_i2c.o(i.GPIO_I2C2_Write) for GPIO_I2C2_Write
+    gpio_i2c.o(i.I2C2_Read) refers to gpio_i2c.o(i.GPIO_I2C2_Read) for GPIO_I2C2_Read
+    gpio_i2c.o(i.I2C2_Read) refers to gpio_i2c.o(i.GPIO_I2C2_Stop) for GPIO_I2C2_Stop
+    gpio_i2c.o(i.I2C2_Write) refers to gpio_i2c.o(i.GPIO_I2C2_Start) for GPIO_I2C2_Start
+    gpio_i2c.o(i.I2C2_Write) refers to gpio_i2c.o(i.GPIO_I2C2_Write) for GPIO_I2C2_Write
+    gpio_i2c.o(i.I2C2_Write) refers to gpio_i2c.o(i.GPIO_I2C2_Stop) for GPIO_I2C2_Stop
+    spi10.o(i.SPI10_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    spi10.o(i.SPI10_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigFunction) for HAL_GPIO_ConfigFunction
+    spi10.o(i.SPI10_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    spi10.o(i.SPI10_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    spi10.o(i.SPI10_Initialization) refers to a31g12x_hal_usart1n.o(i.HAL_USART_SPI_Mode_Config) for HAL_USART_SPI_Mode_Config
+    spi10.o(i.SPI10_Initialization) refers to a31g12x_hal_usart1n.o(i.HAL_USART_Init) for HAL_USART_Init
+    spi10.o(i.SPI10_Initialization) refers to a31g12x_hal_usart1n.o(i.HAL_USART_DataControlConfig) for HAL_USART_DataControlConfig
+    spi10.o(i.SPI10_Initialization) refers to a31g12x_hal_usart1n.o(i.HAL_USART_Enable) for HAL_USART_Enable
+    driver_ds3231.o(i.a_ds3231_hex2bcd) refers to idiv.o(.text) for __aeabi_idivmod
+    driver_ds3231.o(i.ds3231_aging_offset_convert_to_data) refers to fflti.o(.text) for __aeabi_i2f
+    driver_ds3231.o(i.ds3231_aging_offset_convert_to_data) refers to fmul.o(.text) for __aeabi_fmul
+    driver_ds3231.o(i.ds3231_aging_offset_convert_to_register) refers to fdiv.o(.text) for __aeabi_fdiv
+    driver_ds3231.o(i.ds3231_aging_offset_convert_to_register) refers to ffixi.o(.text) for __aeabi_f2iz
+    driver_ds3231.o(i.ds3231_alarm_clear) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_alarm_clear) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_get_32khz_output) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_aging_offset) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_alarm1) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_alarm1) refers to driver_ds3231.o(i.a_ds3231_bcd2hex) for a_ds3231_bcd2hex
+    driver_ds3231.o(i.ds3231_get_alarm2) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_alarm2) refers to driver_ds3231.o(i.a_ds3231_bcd2hex) for a_ds3231_bcd2hex
+    driver_ds3231.o(i.ds3231_get_alarm_interrupt) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_oscillator) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_pin) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_square_wave) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_status) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_temperature) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_temperature) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_get_temperature) refers to fflti.o(.text) for __aeabi_i2f
+    driver_ds3231.o(i.ds3231_get_temperature) refers to fmul.o(.text) for __aeabi_fmul
+    driver_ds3231.o(i.ds3231_get_time) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_get_time) refers to driver_ds3231.o(i.a_ds3231_bcd2hex) for a_ds3231_bcd2hex
+    driver_ds3231.o(i.ds3231_info) refers to memseta.o(.text) for __aeabi_memclr4
+    driver_ds3231.o(i.ds3231_info) refers to strncpy.o(.text) for strncpy
+    driver_ds3231.o(i.ds3231_init) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_init) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_irq_handler) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_set_32khz_output) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_set_32khz_output) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_set_aging_offset) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_set_alarm1) refers to driver_ds3231.o(i.a_ds3231_hex2bcd) for a_ds3231_hex2bcd
+    driver_ds3231.o(i.ds3231_set_alarm1) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_set_alarm2) refers to driver_ds3231.o(i.a_ds3231_hex2bcd) for a_ds3231_hex2bcd
+    driver_ds3231.o(i.ds3231_set_alarm2) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_set_alarm_interrupt) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_set_alarm_interrupt) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_set_oscillator) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_set_oscillator) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_set_pin) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_set_pin) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_set_square_wave) refers to driver_ds3231.o(i.a_ds3231_iic_multiple_read) for a_ds3231_iic_multiple_read
+    driver_ds3231.o(i.ds3231_set_square_wave) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231.o(i.ds3231_set_time) refers to driver_ds3231.o(i.a_ds3231_hex2bcd) for a_ds3231_hex2bcd
+    driver_ds3231.o(i.ds3231_set_time) refers to driver_ds3231.o(i.a_ds3231_iic_write) for a_ds3231_iic_write
+    driver_ds3231_basic.o(i.ds3231_basic_deinit) refers to driver_ds3231.o(i.ds3231_deinit) for ds3231_deinit
+    driver_ds3231_basic.o(i.ds3231_basic_deinit) refers to driver_ds3231_basic.o(.bss) for gs_handle
+    driver_ds3231_basic.o(i.ds3231_basic_get_ascii_time) refers to driver_ds3231.o(i.ds3231_get_time) for ds3231_get_time
+    driver_ds3231_basic.o(i.ds3231_basic_get_ascii_time) refers to printfa.o(i.__0snprintf) for __2snprintf
+    driver_ds3231_basic.o(i.ds3231_basic_get_ascii_time) refers to driver_ds3231_basic.o(.bss) for gs_handle
+    driver_ds3231_basic.o(i.ds3231_basic_get_temperature) refers to driver_ds3231.o(i.ds3231_get_temperature) for ds3231_get_temperature
+    driver_ds3231_basic.o(i.ds3231_basic_get_temperature) refers to driver_ds3231_basic.o(.bss) for gs_handle
+    driver_ds3231_basic.o(i.ds3231_basic_get_time) refers to driver_ds3231.o(i.ds3231_get_time) for ds3231_get_time
+    driver_ds3231_basic.o(i.ds3231_basic_get_time) refers to driver_ds3231_basic.o(.bss) for gs_handle
+    driver_ds3231_basic.o(i.ds3231_basic_get_timestamp) refers to driver_ds3231.o(i.ds3231_get_time) for ds3231_get_time
+    driver_ds3231_basic.o(i.ds3231_basic_get_timestamp) refers to idiv.o(.text) for __aeabi_idivmod
+    driver_ds3231_basic.o(i.ds3231_basic_get_timestamp) refers to mktime.o(.text) for mktime
+    driver_ds3231_basic.o(i.ds3231_basic_get_timestamp) refers to driver_ds3231_basic.o(.bss) for gs_handle
+    driver_ds3231_basic.o(i.ds3231_basic_get_timestamp) refers to driver_ds3231_basic.o(.data) for gs_time_zone
+    driver_ds3231_basic.o(i.ds3231_basic_get_timestamp_time_zone) refers to driver_ds3231_basic.o(.data) for gs_time_zone
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to memseta.o(.text) for __aeabi_memclr4
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_init) for ds3231_init
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231_interface_template.o(i.ds3231_interface_debug_print) for ds3231_interface_debug_print
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_set_oscillator) for ds3231_set_oscillator
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_deinit) for ds3231_deinit
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_set_alarm_interrupt) for ds3231_set_alarm_interrupt
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_set_pin) for ds3231_set_pin
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_set_square_wave) for ds3231_set_square_wave
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_set_32khz_output) for ds3231_set_32khz_output
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_aging_offset_convert_to_register) for ds3231_aging_offset_convert_to_register
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231.o(i.ds3231_set_aging_offset) for ds3231_set_aging_offset
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231_basic.o(.bss) for gs_handle
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231_interface_template.o(i.ds3231_interface_iic_init) for ds3231_interface_iic_init
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231_interface_template.o(i.ds3231_interface_iic_deinit) for ds3231_interface_iic_deinit
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231_interface_template.o(i.ds3231_interface_iic_read) for ds3231_interface_iic_read
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231_interface_template.o(i.ds3231_interface_iic_write) for ds3231_interface_iic_write
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231_interface_template.o(i.ds3231_interface_delay_ms) for ds3231_interface_delay_ms
+    driver_ds3231_basic.o(i.ds3231_basic_init) refers to driver_ds3231_interface_template.o(i.ds3231_interface_receive_callback) for ds3231_interface_receive_callback
+    driver_ds3231_basic.o(i.ds3231_basic_set_time) refers to driver_ds3231.o(i.ds3231_set_time) for ds3231_set_time
+    driver_ds3231_basic.o(i.ds3231_basic_set_time) refers to driver_ds3231_basic.o(.bss) for gs_handle
+    driver_ds3231_basic.o(i.ds3231_basic_set_timestamp) refers to localtime_w.o(.text) for localtime
+    driver_ds3231_basic.o(i.ds3231_basic_set_timestamp) refers to driver_ds3231.o(i.ds3231_set_time) for ds3231_set_time
+    driver_ds3231_basic.o(i.ds3231_basic_set_timestamp) refers to driver_ds3231_basic.o(.data) for gs_time_zone
+    driver_ds3231_basic.o(i.ds3231_basic_set_timestamp) refers to driver_ds3231_basic.o(.bss) for gs_handle
+    driver_ds3231_basic.o(i.ds3231_basic_set_timestamp_time_zone) refers to driver_ds3231_basic.o(.data) for gs_time_zone
+    driver_ds3231_interface_template.o(i.ds3231_interface_delay_ms) refers to systick_timer.o(i.Delay_ms) for Delay_ms
+    driver_ds3231_interface_template.o(i.ds3231_interface_iic_read) refers to gpio_i2c.o(i.I2C2_Write) for I2C2_Write
+    driver_ds3231_interface_template.o(i.ds3231_interface_iic_read) refers to gpio_i2c.o(i.I2C2_Read) for I2C2_Read
+    driver_ds3231_interface_template.o(i.ds3231_interface_iic_write) refers to memcpya.o(.text) for __aeabi_memcpy
+    driver_ds3231_interface_template.o(i.ds3231_interface_iic_write) refers to gpio_i2c.o(i.I2C2_Write) for I2C2_Write
+    driver_ds3231_interface_template.o(i.ds3231_interface_receive_callback) refers to driver_ds3231_interface_template.o(i.ds3231_interface_debug_print) for ds3231_interface_debug_print
+    rtc_process.o(i.RTC_Get_IC_Time_Process) refers to driver_ds3231_basic.o(i.ds3231_basic_get_time) for ds3231_basic_get_time
+    rtc_process.o(i.RTC_Get_IC_Time_Process) refers to idiv.o(.text) for __aeabi_idivmod
+    rtc_process.o(i.RTC_Get_IC_Time_Process) refers to rtc_process.o(.data) for rtc_Time
+    rtc_process.o(i.RTC_Get_Time) refers to memcpya.o(.text) for __aeabi_memcpy
+    rtc_process.o(i.RTC_Get_Time) refers to rtc_process.o(.data) for rtc_Time
+    rtc_process.o(i.RTC_Process_Initialization) refers to driver_ds3231_basic.o(i.ds3231_basic_init) for ds3231_basic_init
+    rtc_process.o(i.RTC_Process_Initialization) refers to sw_timer.o(i.SW_Timer_Callback_Register) for SW_Timer_Callback_Register
+    rtc_process.o(i.RTC_Process_Initialization) refers to rtc_process.o(i.RTC_Get_IC_Time_Process) for RTC_Get_IC_Time_Process
+    action_process.o(i.Action_Initialization) refers to sw_timer.o(i.SW_Timer_Callback_Register) for SW_Timer_Callback_Register
+    action_process.o(i.Action_Initialization) refers to action_process.o(i.Action_Process) for Action_Process
+    eeprom.o(i.EEPROM_Read_Mode) refers to memcpya.o(.text) for __aeabi_memcpy
+    eeprom.o(i.EEPROM_Read_Mode) refers to eeprom.o(.bss) for eeprom_info
+    eeprom.o(i.EEPROM_Write_Mode) refers to memseta.o(.text) for __aeabi_memclr
+    eeprom.o(i.EEPROM_Write_Mode) refers to eeprom.o(i.FlashMem_Do_PageEr) for FlashMem_Do_PageEr
+    eeprom.o(i.EEPROM_Write_Mode) refers to eeprom.o(i.FlashMem_Do_PageWt) for FlashMem_Do_PageWt
+    eeprom.o(i.EEPROM_Write_Mode) refers to eeprom.o(.bss) for eeprom_info
+    eeprom.o(i.FlashMEM_Clock_Initialization) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    eeprom.o(i.FlashMEM_Clock_Initialization) refers to a31g12x_hal_crc.o(i.HAL_CRC_Init) for HAL_CRC_Init
+    eeprom.o(i.FlashMem_Do_PageEr) refers to a31g12x_hal_fmc.o(i.HAL_FMC_PageErase) for HAL_FMC_PageErase
+    eeprom.o(i.FlashMem_Do_PageWt) refers to a31g12x_hal_fmc.o(i.HAL_FMC_PageWrite) for HAL_FMC_PageWrite
+    buzzer.o(i.Buzzer_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    buzzer.o(i.Buzzer_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    buzzer.o(i.Buzzer_Initialization) refers to sw_timer.o(i.SW_Timer_Callback_Register) for SW_Timer_Callback_Register
+    buzzer.o(i.Buzzer_Initialization) refers to buzzer.o(i.Buzzer_Output_Process) for Buzzer_Output_Process
+    buzzer.o(i.Buzzer_On) refers to systick_timer.o(i.millis) for millis
+    buzzer.o(i.Buzzer_On) refers to buzzer.o(.data) for isBuzzerOn
+    buzzer.o(i.Buzzer_Output_Process) refers to systick_timer.o(i.millis) for millis
+    buzzer.o(i.Buzzer_Output_Process) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    buzzer.o(i.Buzzer_Output_Process) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    buzzer.o(i.Buzzer_Output_Process) refers to buzzer.o(.data) for isBuzzerOn
+    gpio_sensor.o(i.Gpio_Sensor_PWR_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    gpio_sensor.o(i.Gpio_Sensor_PWR_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup) for HAL_GPIO_ConfigPullup
+    gpio_sensor.o(i.Gpio_Sensor_PWR_Initialization) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    segment.o(i.Segment_All_Set_Data) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_In_Sensor_Error) refers to segment_74hc595d.o(.data) for Segment_Toggle_In
+    segment.o(i.Segment_In_Sensor_Error) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_In_Sensor_Error) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_In_Set_Humidity) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_In_Set_Humidity) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_In_Set_Humidity) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_In_Set_PM_10) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_In_Set_PM_10) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_In_Set_PM_10) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_In_Set_PM_1p0) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_In_Set_PM_1p0) refers to segment_74hc595d.o(.data) for Segment_Toggle_In
+    segment.o(i.Segment_In_Set_PM_1p0) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_In_Set_PM_1p0) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_In_Set_PM_2p5) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_In_Set_PM_2p5) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_In_Set_PM_2p5) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_In_Set_PM_4p0) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_In_Set_PM_4p0) refers to segment_74hc595d.o(.data) for Segment_Toggle_In
+    segment.o(i.Segment_In_Set_PM_4p0) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_In_Set_PM_4p0) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_In_Set_Temperature) refers to idiv.o(.text) for __aeabi_idivmod
+    segment.o(i.Segment_In_Set_Temperature) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_In_Set_Temperature) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Out_Sensor_Error) refers to segment_74hc595d.o(.data) for Segment_Toggle_Out
+    segment.o(i.Segment_Out_Sensor_Error) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_Out_Sensor_Error) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Out_Set_Humidity) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_Out_Set_Humidity) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_Out_Set_Humidity) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Out_Set_PM_10) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_Out_Set_PM_10) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_Out_Set_PM_10) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Out_Set_PM_1p0) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_Out_Set_PM_1p0) refers to segment_74hc595d.o(.data) for Segment_Toggle_Out
+    segment.o(i.Segment_Out_Set_PM_1p0) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_Out_Set_PM_1p0) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Out_Set_PM_2p5) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_Out_Set_PM_2p5) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_Out_Set_PM_2p5) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Out_Set_PM_4p0) refers to uidiv.o(.text) for __aeabi_uidivmod
+    segment.o(i.Segment_Out_Set_PM_4p0) refers to segment_74hc595d.o(.data) for Segment_Toggle_Out
+    segment.o(i.Segment_Out_Set_PM_4p0) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_Out_Set_PM_4p0) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Out_Set_Temperature) refers to idiv.o(.text) for __aeabi_idivmod
+    segment.o(i.Segment_Out_Set_Temperature) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_Out_Set_Temperature) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Show_Mode) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Show_Mode) refers to segment.o(.constdata) for SegmentData
+    segment.o(i.Segment_Show_Version) refers to idiv.o(.text) for __aeabi_idivmod
+    segment.o(i.Segment_Show_Version) refers to segment.o(.bss) for Segment_OutputBuff
+    segment.o(i.Segment_Show_Version) refers to segment.o(.constdata) for SegmentData
+    uart_packet.o(i.Uart_Packet_Initialization) refers to sw_timer.o(i.SW_Timer_Callback_Register) for SW_Timer_Callback_Register
+    uart_packet.o(i.Uart_Packet_Initialization) refers to uart_packet.o(.data) for Pack_Index
+    uart_packet.o(i.Uart_Packet_Initialization) refers to uart_packet.o(i.Uart_Packet_Make_Process) for Uart_Packet_Make_Process
+    uart_packet.o(i.Uart_Packet_Make_Process) refers to uart1.o(i.Uart1_Get_RecvDataCount) for Uart1_Get_RecvDataCount
+    uart_packet.o(i.Uart_Packet_Make_Process) refers to uart1.o(i.Uart1_Get_RecvData) for Uart1_Get_RecvData
+    uart_packet.o(i.Uart_Packet_Make_Process) refers to uart_packet.o(i.Uart_Packet_Process) for Uart_Packet_Process
+    uart_packet.o(i.Uart_Packet_Make_Process) refers to uart_packet.o(.data) for Pack_Index
+    uart_packet.o(i.Uart_Packet_Make_Process) refers to uart_packet.o(.bss) for Pack_Buff
+    uart_packet.o(i.Uart_Packet_Process) refers to driver_ds3231_basic.o(i.ds3231_basic_get_time) for ds3231_basic_get_time
+    uart_packet.o(i.Uart_Packet_Process) refers to driver_ds3231_basic.o(i.ds3231_basic_set_time) for ds3231_basic_set_time
+    uart_packet.o(i.Uart_Packet_Process) refers to buzzer.o(i.Buzzer_On) for Buzzer_On
+    a31g12x_hal_adc.o(i.HAL_ADC_DeInit) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_adc.o(i.HAL_ADC_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_crc.o(i.HAL_CRC_ConfigAutoMode) refers to system_a31g12x.o(.data) for SystemCoreClock
+    a31g12x_hal_crc.o(i.HAL_CRC_DeInit) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_SetReset2) for HAL_SCU_Peripheral_SetReset2
+    a31g12x_hal_crc.o(i.HAL_CRC_DeInit) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_crc.o(i.HAL_CRC_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_debug_frmwrk.o(i.UARTGetCh) refers to a31g12x_hal_uartn.o(i.HAL_UART_ReceiveByte) for HAL_UART_ReceiveByte
+    a31g12x_hal_debug_frmwrk.o(i.UARTGetChar) refers to a31g12x_hal_uartn.o(i.HAL_UART_Receive) for HAL_UART_Receive
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) refers to a31g12x_hal_uartn.o(i.HAL_UART_Transmit) for HAL_UART_Transmit
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutDec) refers to idiv.o(.text) for __aeabi_idivmod
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutDec) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutDec16) refers to idiv.o(.text) for __aeabi_idivmod
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutDec16) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutDec32) refers to uidiv.o(.text) for __aeabi_uidivmod
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutDec32) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutHex) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutHex16) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.UARTPutHex32) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.UARTPuts) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.UARTPuts_) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPuts) for UARTPuts
+    a31g12x_hal_debug_frmwrk.o(i.cprintf) refers to printfa.o(i.__0vsprintf) for vsprintf
+    a31g12x_hal_debug_frmwrk.o(i.cprintf) refers to a31g12x_hal_debug_frmwrk.o(.data) for _db_msg
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput) for HAL_GPIO_ConfigOutput
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigFunction) for HAL_GPIO_ConfigFunction
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_uartn.o(i.HAL_UART_ConfigStructInit) for HAL_UART_ConfigStructInit
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_uartn.o(i.HAL_UART_Init) for HAL_UART_Init
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPuts) for UARTPuts
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(.data) for _db_msg
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPuts_) for UARTPuts_
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutHex) for UARTPutHex
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutHex16) for UARTPutHex16
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutHex32) for UARTPutHex32
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutDec) for UARTPutDec
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutDec16) for UARTPutDec16
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutDec32) for UARTPutDec32
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTGetChar) for UARTGetChar
+    a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init) refers to a31g12x_hal_debug_frmwrk.o(i.UARTGetCh) for UARTGetCh
+    a31g12x_hal_debug_frmwrk.o(i.getstring) refers to a31g12x_hal_debug_frmwrk.o(i.UARTGetChar) for UARTGetChar
+    a31g12x_hal_debug_frmwrk.o(i.getstring) refers to a31g12x_hal_debug_frmwrk.o(i.UARTPutChar) for UARTPutChar
+    a31g12x_hal_debug_frmwrk.o(i.getstring) refers to a31g12x_hal_uartn.o(.data) for InCount
+    a31g12x_hal_debug_frmwrk.o(i.getstring) refers to a31g12x_hal_uartn.o(.bss) for InData
+    a31g12x_hal_fmc.o(i.HAL_FMC_BulkErase) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashEntry) for HAL_FMC_FlashEntry
+    a31g12x_hal_fmc.o(i.HAL_FMC_BulkErase) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashFunction) for HAL_FMC_FlashFunction
+    a31g12x_hal_fmc.o(i.HAL_FMC_BulkErase) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashExit) for HAL_FMC_FlashExit
+    a31g12x_hal_fmc.o(i.HAL_FMC_BulkErase) refers to a31g12x_hal_fmc.o(.data) for flash_addr_code1
+    a31g12x_hal_fmc.o(i.HAL_FMC_FlashEntry) refers to a31g12x_hal_fmc.o(.data) for flash_id1_reg
+    a31g12x_hal_fmc.o(i.HAL_FMC_FlashExit) refers to a31g12x_hal_fmc.o(.data) for flash_id1_reg
+    a31g12x_hal_fmc.o(i.HAL_FMC_FlashFunction) refers to a31g12x_hal_fmc.o(.data) for flash_addr_code0
+    a31g12x_hal_fmc.o(i.HAL_FMC_PageErase) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashEntry) for HAL_FMC_FlashEntry
+    a31g12x_hal_fmc.o(i.HAL_FMC_PageErase) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashFunction) for HAL_FMC_FlashFunction
+    a31g12x_hal_fmc.o(i.HAL_FMC_PageErase) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashExit) for HAL_FMC_FlashExit
+    a31g12x_hal_fmc.o(i.HAL_FMC_PageWrite) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashEntry) for HAL_FMC_FlashEntry
+    a31g12x_hal_fmc.o(i.HAL_FMC_PageWrite) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashFunction) for HAL_FMC_FlashFunction
+    a31g12x_hal_fmc.o(i.HAL_FMC_PageWrite) refers to a31g12x_hal_fmc.o(i.HAL_FMC_FlashExit) for HAL_FMC_FlashExit
+    a31g12x_hal_i2cn.o(i.HAL_I2C_ConfigInterrupt) refers to a31g12x_hal_i2cn.o(i.NVIC_ClearPendingIRQ) for NVIC_ClearPendingIRQ
+    a31g12x_hal_i2cn.o(i.HAL_I2C_ConfigInterrupt) refers to a31g12x_hal_i2cn.o(i.NVIC_EnableIRQ) for NVIC_EnableIRQ
+    a31g12x_hal_i2cn.o(i.HAL_I2C_ConfigInterrupt) refers to a31g12x_hal_i2cn.o(i.NVIC_DisableIRQ) for NVIC_DisableIRQ
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_SetReset2) for HAL_SCU_Peripheral_SetReset2
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Init) refers to uidiv.o(.text) for __aeabi_uidivmod
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Init) refers to system_a31g12x.o(.data) for SystemPeriClock
+    a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData) refers to a31g12x_hal_i2cn.o(i.I2Cn_MWait) for I2Cn_MWait
+    a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData) refers to a31g12x_hal_i2cn.o(i.I2Cn_getNum) for I2Cn_getNum
+    a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData) refers to memcpya.o(.text) for __aeabi_memcpy4
+    a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData) refers to a31g12x_hal_i2cn.o(i.HAL_I2C_ConfigInterrupt) for HAL_I2C_ConfigInterrupt
+    a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData) refers to a31g12x_hal_i2cn.o(.data) for I2Cn_MasterComplete
+    a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData) refers to a31g12x_hal_i2cn.o(.bss) for i2cdat
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Master_GetState) refers to a31g12x_hal_i2cn.o(i.I2Cn_getNum) for I2Cn_getNum
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Master_GetState) refers to a31g12x_hal_i2cn.o(.data) for I2Cn_MasterComplete
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Master_IRQHandler_IT) refers to a31g12x_hal_i2cn.o(i.I2Cn_getNum) for I2Cn_getNum
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Master_IRQHandler_IT) refers to a31g12x_hal_i2cn.o(i.HAL_I2C_ConfigInterrupt) for HAL_I2C_ConfigInterrupt
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Master_IRQHandler_IT) refers to a31g12x_hal_i2cn.o(.bss) for i2cdat
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Master_IRQHandler_IT) refers to a31g12x_hal_i2cn.o(.data) for I2Cn_MasterComplete
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Master_Receive) refers to a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData) for HAL_I2C_MasterTransferData
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Master_Transmit) refers to a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData) for HAL_I2C_MasterTransferData
+    a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData) refers to a31g12x_hal_i2cn.o(i.I2Cn_SWait) for I2Cn_SWait
+    a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData) refers to segment_74hc595d.o(i.__ARM_common_switch8) for __ARM_common_switch8
+    a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData) refers to a31g12x_hal_i2cn.o(i.I2Cn_getNum) for I2Cn_getNum
+    a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData) refers to memcpya.o(.text) for __aeabi_memcpy4
+    a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData) refers to a31g12x_hal_i2cn.o(i.HAL_I2C_ConfigInterrupt) for HAL_I2C_ConfigInterrupt
+    a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData) refers to a31g12x_hal_i2cn.o(.data) for I2Cn_SlaveComplete
+    a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData) refers to a31g12x_hal_i2cn.o(.bss) for i2cdat
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_GetState) refers to a31g12x_hal_i2cn.o(i.I2Cn_getNum) for I2Cn_getNum
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_GetState) refers to a31g12x_hal_i2cn.o(.data) for I2Cn_SlaveComplete
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_IRQHandler_IT) refers to a31g12x_hal_i2cn.o(i.I2Cn_getNum) for I2Cn_getNum
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_IRQHandler_IT) refers to a31g12x_hal_i2cn.o(i.HAL_I2C_ConfigInterrupt) for HAL_I2C_ConfigInterrupt
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_IRQHandler_IT) refers to a31g12x_hal_i2cn.o(.bss) for i2cdat
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_IRQHandler_IT) refers to a31g12x_hal_i2cn.o(.data) for I2Cn_SlaveComplete
+    a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_Receive) refers to a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData) for HAL_I2C_SlaveTransferData
+    a31g12x_hal_lcd.o(i.HAL_LCD_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_pcu.o(i.HAL_GPIO_TogglePin) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    a31g12x_hal_pcu.o(i.HAL_GPIO_TogglePin) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    a31g12x_hal_sculv.o(i.HAL_LVI_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_timer1n.o(i.HAL_TIMER1n_DeInit) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock1) for HAL_SCU_Peripheral_EnableClock1
+    a31g12x_hal_timer1n.o(i.HAL_TIMER1n_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock1) for HAL_SCU_Peripheral_EnableClock1
+    a31g12x_hal_uartn.o(i.HAL_UART_DeInit) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_SetReset2) for HAL_SCU_Peripheral_SetReset2
+    a31g12x_hal_uartn.o(i.HAL_UART_DeInit) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_uartn.o(i.HAL_UART_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_uartn.o(i.HAL_UART_Init) refers to a31g12x_hal_uartn.o(i.uart_set_divisors) for uart_set_divisors
+    a31g12x_hal_uartn.o(i.HAL_UART_Init) refers to system_a31g12x.o(.data) for SystemPeriClock
+    a31g12x_hal_uartn.o(i.HAL_UART_Init) refers to a31g12x_hal_uartn.o(.data) for UARTn_BaseClock
+    a31g12x_hal_uartn.o(i.HAL_UART_Receive) refers to a31g12x_hal_uartn.o(i.HAL_UART_ReceiveByte) for HAL_UART_ReceiveByte
+    a31g12x_hal_uartn.o(i.HAL_UART_Transmit) refers to a31g12x_hal_uartn.o(i.HAL_UART_TransmitByte) for HAL_UART_TransmitByte
+    a31g12x_hal_uartn.o(i.uart_set_divisors) refers to uidiv.o(.text) for __aeabi_uidivmod
+    a31g12x_hal_uartn.o(i.uart_set_divisors) refers to a31g12x_hal_uartn.o(.data) for UARTn_BaseClock
+    a31g12x_hal_usart1n.o(i.HAL_USART_DataControlConfig) refers to segment_74hc595d.o(i.__ARM_common_switch8) for __ARM_common_switch8
+    a31g12x_hal_usart1n.o(i.HAL_USART_DeInit) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_SetReset2) for HAL_SCU_Peripheral_SetReset2
+    a31g12x_hal_usart1n.o(i.HAL_USART_DeInit) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_usart1n.o(i.HAL_USART_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_usart1n.o(i.HAL_USART_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_SetReset2) for HAL_SCU_Peripheral_SetReset2
+    a31g12x_hal_usart1n.o(i.HAL_USART_Init) refers to a31g12x_hal_usart1n.o(i.usart_set_divisors) for usart_set_divisors
+    a31g12x_hal_usart1n.o(i.HAL_USART_Init) refers to a31g12x_hal_usart1n.o(i.HAL_USART_ClearStatus) for HAL_USART_ClearStatus
+    a31g12x_hal_usart1n.o(i.HAL_USART_Init) refers to a31g12x_hal_usart1n.o(i.HAL_USART_ReceiveByte) for HAL_USART_ReceiveByte
+    a31g12x_hal_usart1n.o(i.HAL_USART_Init) refers to system_a31g12x.o(.data) for SystemPeriClock
+    a31g12x_hal_usart1n.o(i.HAL_USART_Init) refers to a31g12x_hal_usart1n.o(.data) for USART1n_BaseClock
+    a31g12x_hal_usart1n.o(i.HAL_USART_Receive) refers to a31g12x_hal_usart1n.o(i.HAL_USART_ReceiveByte) for HAL_USART_ReceiveByte
+    a31g12x_hal_usart1n.o(i.HAL_USART_Transmit) refers to a31g12x_hal_usart1n.o(i.HAL_USART_TransmitByte) for HAL_USART_TransmitByte
+    a31g12x_hal_usart1n.o(i.HAL_USART_Transmit) refers to a31g12x_hal_usart1n.o(i.HAL_USART_ClearStatus) for HAL_USART_ClearStatus
+    a31g12x_hal_usart1n.o(i.usart_set_divisors) refers to uidiv.o(.text) for __aeabi_uidivmod
+    a31g12x_hal_usart1n.o(i.usart_set_divisors) refers to a31g12x_hal_usart1n.o(.data) for USART1n_BaseClock
+    a31g12x_hal_wdt.o(i.HAL_WDT_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    a31g12x_hal_wt.o(i.HAL_WT_Init) refers to a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2) for HAL_SCU_Peripheral_EnableClock2
+    startup_a31g12x.o(RESET) refers to startup_a31g12x.o(STACK) for __initial_sp
+    startup_a31g12x.o(RESET) refers to startup_a31g12x.o(.text) for Reset_Handler
+    startup_a31g12x.o(RESET) refers to a31g12x_interrupt.o(i.NMI_Handler) for NMI_Handler
+    startup_a31g12x.o(RESET) refers to a31g12x_interrupt.o(i.HardFault_Handler) for HardFault_Handler
+    startup_a31g12x.o(RESET) refers to a31g12x_interrupt.o(i.SVC_Handler) for SVC_Handler
+    startup_a31g12x.o(RESET) refers to a31g12x_interrupt.o(i.PendSV_Handler) for PendSV_Handler
+    startup_a31g12x.o(RESET) refers to systick_timer.o(i.SysTick_Handler) for SysTick_Handler
+    startup_a31g12x.o(RESET) refers to timer12.o(i.TIMER12_Handler) for TIMER12_Handler
+    startup_a31g12x.o(RESET) refers to uart1.o(i.UART1_Handler) for UART1_Handler
+    startup_a31g12x.o(.text) refers to system_a31g12x.o(i.SystemInit) for SystemInit
+    startup_a31g12x.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
+    system_a31g12x.o(i.SystemCoreClockUpdate) refers to system_a31g12x.o(.data) for ClkSrcTbl
+    fatfs.o(i.MX_FATFS_Init) refers to ff_gen_drv.o(i.FATFS_LinkDriver) for FATFS_LinkDriver
+    fatfs.o(i.MX_FATFS_Init) refers to fatfs.o(.data) for USERPath
+    fatfs.o(i.MX_FATFS_Init) refers to user_diskio.o(.data) for USER_Driver
+    user_diskio.o(i.USER_initialize) refers to user_diskio_spi.o(i.USER_SPI_initialize) for USER_SPI_initialize
+    user_diskio.o(i.USER_ioctl) refers to user_diskio_spi.o(i.USER_SPI_ioctl) for USER_SPI_ioctl
+    user_diskio.o(i.USER_read) refers to user_diskio_spi.o(i.USER_SPI_read) for USER_SPI_read
+    user_diskio.o(i.USER_status) refers to user_diskio_spi.o(i.USER_SPI_status) for USER_SPI_status
+    user_diskio.o(i.USER_write) refers to user_diskio_spi.o(i.USER_SPI_write) for USER_SPI_write
+    user_diskio.o(.data) refers to user_diskio.o(i.USER_initialize) for USER_initialize
+    user_diskio.o(.data) refers to user_diskio.o(i.USER_status) for USER_status
+    user_diskio.o(.data) refers to user_diskio.o(i.USER_read) for USER_read
+    user_diskio.o(.data) refers to user_diskio.o(i.USER_write) for USER_write
+    user_diskio.o(.data) refers to user_diskio.o(i.USER_ioctl) for USER_ioctl
+    user_diskio_spi.o(i.SPI_Timer_On) refers to systick_timer.o(i.millis) for millis
+    user_diskio_spi.o(i.SPI_Timer_On) refers to user_diskio_spi.o(.data) for spiTimerTickStart
+    user_diskio_spi.o(i.SPI_Timer_Status) refers to systick_timer.o(i.millis) for millis
+    user_diskio_spi.o(i.SPI_Timer_Status) refers to user_diskio_spi.o(.data) for spiTimerTickStart
+    user_diskio_spi.o(i.despiselect) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin) for HAL_GPIO_SetPin
+    user_diskio_spi.o(i.despiselect) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.rcvr_datablock) refers to user_diskio_spi.o(i.SPI_Timer_On) for SPI_Timer_On
+    user_diskio_spi.o(i.rcvr_datablock) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.rcvr_datablock) refers to user_diskio_spi.o(i.SPI_Timer_Status) for SPI_Timer_Status
+    user_diskio_spi.o(i.rcvr_datablock) refers to user_diskio_spi.o(i.rcvr_spi_multi) for rcvr_spi_multi
+    user_diskio_spi.o(i.rcvr_spi_multi) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.send_cmd) refers to user_diskio_spi.o(i.despiselect) for despiselect
+    user_diskio_spi.o(i.send_cmd) refers to user_diskio_spi.o(i.spiselect) for spiselect
+    user_diskio_spi.o(i.send_cmd) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.spiselect) refers to a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin) for HAL_GPIO_ClearPin
+    user_diskio_spi.o(i.spiselect) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.spiselect) refers to user_diskio_spi.o(i.wait_ready) for wait_ready
+    user_diskio_spi.o(i.spiselect) refers to user_diskio_spi.o(i.despiselect) for despiselect
+    user_diskio_spi.o(i.wait_ready) refers to systick_timer.o(i.millis) for millis
+    user_diskio_spi.o(i.wait_ready) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.xchg_spi) refers to spi10.o(i.SPI10_SendReceiveByte) for SPI10_SendReceiveByte
+    user_diskio_spi.o(i.xmit_datablock) refers to user_diskio_spi.o(i.wait_ready) for wait_ready
+    user_diskio_spi.o(i.xmit_datablock) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.xmit_datablock) refers to user_diskio_spi.o(i.xmit_spi_multi) for xmit_spi_multi
+    user_diskio_spi.o(i.xmit_spi_multi) refers to spi10.o(i.SPI10_Transmit) for SPI10_Transmit
+    diskio.o(i.disk_initialize) refers to ff_gen_drv.o(.bss) for disk
+    diskio.o(i.disk_ioctl) refers to ff_gen_drv.o(.bss) for disk
+    diskio.o(i.disk_read) refers to ff_gen_drv.o(.bss) for disk
+    diskio.o(i.disk_status) refers to ff_gen_drv.o(.bss) for disk
+    diskio.o(i.disk_write) refers to ff_gen_drv.o(.bss) for disk
+    ff.o(i.check_fs) refers to ff.o(i.move_window) for move_window
+    ff.o(i.chk_lock) refers to ff.o(.bss) for Files
+    ff.o(i.clear_lock) refers to ff.o(.bss) for Files
+    ff.o(i.clmt_clust) refers to uidiv.o(.text) for __aeabi_uidivmod
+    ff.o(i.create_chain) refers to ff.o(i.get_fat) for get_fat
+    ff.o(i.create_chain) refers to ff.o(i.put_fat) for put_fat
+    ff.o(i.create_name) refers to ff.o(i.mem_set) for mem_set
+    ff.o(i.create_name) refers to ff.o(i.chk_chr) for chk_chr
+    ff.o(i.create_name) refers to ff.o(.constdata) for ExCvt
+    ff.o(i.dec_lock) refers to ff.o(.bss) for Files
+    ff.o(i.dir_alloc) refers to ff.o(i.dir_sdi) for dir_sdi
+    ff.o(i.dir_alloc) refers to ff.o(i.move_window) for move_window
+    ff.o(i.dir_alloc) refers to ff.o(i.dir_next) for dir_next
+    ff.o(i.dir_find) refers to ff.o(i.dir_sdi) for dir_sdi
+    ff.o(i.dir_find) refers to ff.o(i.move_window) for move_window
+    ff.o(i.dir_find) refers to ff.o(i.mem_cmp) for mem_cmp
+    ff.o(i.dir_find) refers to ff.o(i.dir_next) for dir_next
+    ff.o(i.dir_next) refers to ff.o(i.get_fat) for get_fat
+    ff.o(i.dir_next) refers to ff.o(i.create_chain) for create_chain
+    ff.o(i.dir_next) refers to ff.o(i.sync_window) for sync_window
+    ff.o(i.dir_next) refers to ff.o(i.mem_set) for mem_set
+    ff.o(i.dir_next) refers to ff.o(i.clust2sect) for clust2sect
+    ff.o(i.dir_read) refers to ff.o(i.move_window) for move_window
+    ff.o(i.dir_read) refers to ff.o(i.dir_next) for dir_next
+    ff.o(i.dir_register) refers to ff.o(i.dir_alloc) for dir_alloc
+    ff.o(i.dir_register) refers to ff.o(i.move_window) for move_window
+    ff.o(i.dir_register) refers to ff.o(i.mem_set) for mem_set
+    ff.o(i.dir_register) refers to ff.o(i.mem_cpy) for mem_cpy
+    ff.o(i.dir_remove) refers to ff.o(i.dir_sdi) for dir_sdi
+    ff.o(i.dir_remove) refers to ff.o(i.move_window) for move_window
+    ff.o(i.dir_remove) refers to ff.o(i.mem_set) for mem_set
+    ff.o(i.dir_sdi) refers to ff.o(i.get_fat) for get_fat
+    ff.o(i.dir_sdi) refers to ff.o(i.clust2sect) for clust2sect
+    ff.o(i.enq_lock) refers to ff.o(.bss) for Files
+    ff.o(i.f_chmod) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_chmod) refers to ff.o(i.follow_path) for follow_path
+    ff.o(i.f_chmod) refers to ff.o(i.sync_fs) for sync_fs
+    ff.o(i.f_close) refers to ff.o(i.f_sync) for f_sync
+    ff.o(i.f_close) refers to ff.o(i.validate) for validate
+    ff.o(i.f_close) refers to ff.o(i.dec_lock) for dec_lock
+    ff.o(i.f_closedir) refers to ff.o(i.validate) for validate
+    ff.o(i.f_closedir) refers to ff.o(i.dec_lock) for dec_lock
+    ff.o(i.f_getfree) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_getfree) refers to ff.o(i.get_fat) for get_fat
+    ff.o(i.f_getfree) refers to ff.o(i.move_window) for move_window
+    ff.o(i.f_gets) refers to ff.o(i.f_read) for f_read
+    ff.o(i.f_lseek) refers to ff.o(i.validate) for validate
+    ff.o(i.f_lseek) refers to ff.o(i.get_fat) for get_fat
+    ff.o(i.f_lseek) refers to ff.o(i.clmt_clust) for clmt_clust
+    ff.o(i.f_lseek) refers to ff.o(i.clust2sect) for clust2sect
+    ff.o(i.f_lseek) refers to diskio.o(i.disk_write) for disk_write
+    ff.o(i.f_lseek) refers to diskio.o(i.disk_read) for disk_read
+    ff.o(i.f_lseek) refers to uidiv.o(.text) for __aeabi_uidivmod
+    ff.o(i.f_lseek) refers to ff.o(i.create_chain) for create_chain
+    ff.o(i.f_mkdir) refers to fatfs.o(i.get_fattime) for get_fattime
+    ff.o(i.f_mkdir) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_mkdir) refers to ff.o(i.follow_path) for follow_path
+    ff.o(i.f_mkdir) refers to ff.o(i.create_chain) for create_chain
+    ff.o(i.f_mkdir) refers to ff.o(i.sync_window) for sync_window
+    ff.o(i.f_mkdir) refers to ff.o(i.clust2sect) for clust2sect
+    ff.o(i.f_mkdir) refers to ff.o(i.mem_set) for mem_set
+    ff.o(i.f_mkdir) refers to ff.o(i.st_clust) for st_clust
+    ff.o(i.f_mkdir) refers to ff.o(i.mem_cpy) for mem_cpy
+    ff.o(i.f_mkdir) refers to ff.o(i.dir_register) for dir_register
+    ff.o(i.f_mkdir) refers to ff.o(i.remove_chain) for remove_chain
+    ff.o(i.f_mkdir) refers to ff.o(i.sync_fs) for sync_fs
+    ff.o(i.f_mkfs) refers to ff.o(i.get_ldnumber) for get_ldnumber
+    ff.o(i.f_mkfs) refers to diskio.o(i.disk_initialize) for disk_initialize
+    ff.o(i.f_mkfs) refers to diskio.o(i.disk_ioctl) for disk_ioctl
+    ff.o(i.f_mkfs) refers to uidiv.o(.text) for __aeabi_uidivmod
+    ff.o(i.f_mkfs) refers to ff.o(i.mem_set) for mem_set
+    ff.o(i.f_mkfs) refers to diskio.o(i.disk_write) for disk_write
+    ff.o(i.f_mkfs) refers to ff.o(i.mem_cpy) for mem_cpy
+    ff.o(i.f_mkfs) refers to fatfs.o(i.get_fattime) for get_fattime
+    ff.o(i.f_mkfs) refers to ff.o(.data) for FatFs
+    ff.o(i.f_mkfs) refers to ff.o(.constdata) for vst
+    ff.o(i.f_mount) refers to ff.o(i.get_ldnumber) for get_ldnumber
+    ff.o(i.f_mount) refers to ff.o(i.clear_lock) for clear_lock
+    ff.o(i.f_mount) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_mount) refers to ff.o(.data) for FatFs
+    ff.o(i.f_open) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_open) refers to ff.o(i.follow_path) for follow_path
+    ff.o(i.f_open) refers to ff.o(i.chk_lock) for chk_lock
+    ff.o(i.f_open) refers to ff.o(i.enq_lock) for enq_lock
+    ff.o(i.f_open) refers to ff.o(i.dir_register) for dir_register
+    ff.o(i.f_open) refers to fatfs.o(i.get_fattime) for get_fattime
+    ff.o(i.f_open) refers to ff.o(i.ld_clust) for ld_clust
+    ff.o(i.f_open) refers to ff.o(i.st_clust) for st_clust
+    ff.o(i.f_open) refers to ff.o(i.remove_chain) for remove_chain
+    ff.o(i.f_open) refers to ff.o(i.move_window) for move_window
+    ff.o(i.f_open) refers to ff.o(i.inc_lock) for inc_lock
+    ff.o(i.f_opendir) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_opendir) refers to ff.o(i.follow_path) for follow_path
+    ff.o(i.f_opendir) refers to ff.o(i.ld_clust) for ld_clust
+    ff.o(i.f_opendir) refers to ff.o(i.dir_sdi) for dir_sdi
+    ff.o(i.f_opendir) refers to ff.o(i.inc_lock) for inc_lock
+    ff.o(i.f_printf) refers to ff.o(i.putc_bfd) for putc_bfd
+    ff.o(i.f_printf) refers to uidiv.o(.text) for __aeabi_uidivmod
+    ff.o(i.f_printf) refers to ff.o(i.f_write) for f_write
+    ff.o(i.f_putc) refers to ff.o(i.putc_bfd) for putc_bfd
+    ff.o(i.f_putc) refers to ff.o(i.f_write) for f_write
+    ff.o(i.f_puts) refers to ff.o(i.putc_bfd) for putc_bfd
+    ff.o(i.f_puts) refers to ff.o(i.f_write) for f_write
+    ff.o(i.f_read) refers to ff.o(i.validate) for validate
+    ff.o(i.f_read) refers to ff.o(i.clmt_clust) for clmt_clust
+    ff.o(i.f_read) refers to ff.o(i.get_fat) for get_fat
+    ff.o(i.f_read) refers to ff.o(i.clust2sect) for clust2sect
+    ff.o(i.f_read) refers to diskio.o(i.disk_read) for disk_read
+    ff.o(i.f_read) refers to ff.o(i.mem_cpy) for mem_cpy
+    ff.o(i.f_read) refers to diskio.o(i.disk_write) for disk_write
+    ff.o(i.f_readdir) refers to ff.o(i.validate) for validate
+    ff.o(i.f_readdir) refers to ff.o(i.dir_sdi) for dir_sdi
+    ff.o(i.f_readdir) refers to ff.o(i.dir_read) for dir_read
+    ff.o(i.f_readdir) refers to ff.o(i.get_fileinfo) for get_fileinfo
+    ff.o(i.f_readdir) refers to ff.o(i.dir_next) for dir_next
+    ff.o(i.f_rename) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_rename) refers to ff.o(i.follow_path) for follow_path
+    ff.o(i.f_rename) refers to ff.o(i.chk_lock) for chk_lock
+    ff.o(i.f_rename) refers to ff.o(i.mem_cpy) for mem_cpy
+    ff.o(i.f_rename) refers to ff.o(i.get_ldnumber) for get_ldnumber
+    ff.o(i.f_rename) refers to ff.o(i.dir_register) for dir_register
+    ff.o(i.f_rename) refers to ff.o(i.ld_clust) for ld_clust
+    ff.o(i.f_rename) refers to ff.o(i.clust2sect) for clust2sect
+    ff.o(i.f_rename) refers to ff.o(i.move_window) for move_window
+    ff.o(i.f_rename) refers to ff.o(i.st_clust) for st_clust
+    ff.o(i.f_rename) refers to ff.o(i.dir_remove) for dir_remove
+    ff.o(i.f_rename) refers to ff.o(i.sync_fs) for sync_fs
+    ff.o(i.f_stat) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_stat) refers to ff.o(i.follow_path) for follow_path
+    ff.o(i.f_stat) refers to ff.o(i.get_fileinfo) for get_fileinfo
+    ff.o(i.f_sync) refers to ff.o(i.validate) for validate
+    ff.o(i.f_sync) refers to diskio.o(i.disk_write) for disk_write
+    ff.o(i.f_sync) refers to ff.o(i.move_window) for move_window
+    ff.o(i.f_sync) refers to ff.o(i.st_clust) for st_clust
+    ff.o(i.f_sync) refers to fatfs.o(i.get_fattime) for get_fattime
+    ff.o(i.f_sync) refers to ff.o(i.sync_fs) for sync_fs
+    ff.o(i.f_truncate) refers to ff.o(i.validate) for validate
+    ff.o(i.f_truncate) refers to ff.o(i.remove_chain) for remove_chain
+    ff.o(i.f_truncate) refers to ff.o(i.get_fat) for get_fat
+    ff.o(i.f_truncate) refers to ff.o(i.put_fat) for put_fat
+    ff.o(i.f_truncate) refers to diskio.o(i.disk_write) for disk_write
+    ff.o(i.f_unlink) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_unlink) refers to ff.o(i.follow_path) for follow_path
+    ff.o(i.f_unlink) refers to ff.o(i.chk_lock) for chk_lock
+    ff.o(i.f_unlink) refers to ff.o(i.ld_clust) for ld_clust
+    ff.o(i.f_unlink) refers to ff.o(i.mem_cpy) for mem_cpy
+    ff.o(i.f_unlink) refers to ff.o(i.dir_sdi) for dir_sdi
+    ff.o(i.f_unlink) refers to ff.o(i.dir_read) for dir_read
+    ff.o(i.f_unlink) refers to ff.o(i.dir_remove) for dir_remove
+    ff.o(i.f_unlink) refers to ff.o(i.remove_chain) for remove_chain
+    ff.o(i.f_unlink) refers to ff.o(i.sync_fs) for sync_fs
+    ff.o(i.f_utime) refers to ff.o(i.find_volume) for find_volume
+    ff.o(i.f_utime) refers to ff.o(i.follow_path) for follow_path
+    ff.o(i.f_utime) refers to ff.o(i.sync_fs) for sync_fs
+    ff.o(i.f_write) refers to ff.o(i.validate) for validate
+    ff.o(i.f_write) refers to ff.o(i.create_chain) for create_chain
+    ff.o(i.f_write) refers to ff.o(i.clmt_clust) for clmt_clust
+    ff.o(i.f_write) refers to diskio.o(i.disk_write) for disk_write
+    ff.o(i.f_write) refers to ff.o(i.clust2sect) for clust2sect
+    ff.o(i.f_write) refers to ff.o(i.mem_cpy) for mem_cpy
+    ff.o(i.f_write) refers to diskio.o(i.disk_read) for disk_read
+    ff.o(i.find_volume) refers to ff.o(i.get_ldnumber) for get_ldnumber
+    ff.o(i.find_volume) refers to diskio.o(i.disk_status) for disk_status
+    ff.o(i.find_volume) refers to diskio.o(i.disk_initialize) for disk_initialize
+    ff.o(i.find_volume) refers to ff.o(i.check_fs) for check_fs
+    ff.o(i.find_volume) refers to uidiv.o(.text) for __aeabi_uidivmod
+    ff.o(i.find_volume) refers to ff.o(i.move_window) for move_window
+    ff.o(i.find_volume) refers to ff.o(.data) for FatFs
+    ff.o(i.find_volume) refers to ff.o(i.clear_lock) for clear_lock
+    ff.o(i.follow_path) refers to ff.o(i.dir_sdi) for dir_sdi
+    ff.o(i.follow_path) refers to ff.o(i.create_name) for create_name
+    ff.o(i.follow_path) refers to ff.o(i.dir_find) for dir_find
+    ff.o(i.follow_path) refers to ff.o(i.ld_clust) for ld_clust
+    ff.o(i.get_fat) refers to ff.o(i.move_window) for move_window
+    ff.o(i.inc_lock) refers to ff.o(.bss) for Files
+    ff.o(i.move_window) refers to ff.o(i.sync_window) for sync_window
+    ff.o(i.move_window) refers to diskio.o(i.disk_read) for disk_read
+    ff.o(i.put_fat) refers to ff.o(i.move_window) for move_window
+    ff.o(i.putc_bfd) refers to ff.o(i.f_write) for f_write
+    ff.o(i.remove_chain) refers to ff.o(i.get_fat) for get_fat
+    ff.o(i.remove_chain) refers to ff.o(i.put_fat) for put_fat
+    ff.o(i.sync_fs) refers to ff.o(i.sync_window) for sync_window
+    ff.o(i.sync_fs) refers to ff.o(i.mem_set) for mem_set
+    ff.o(i.sync_fs) refers to diskio.o(i.disk_write) for disk_write
+    ff.o(i.sync_fs) refers to diskio.o(i.disk_ioctl) for disk_ioctl
+    ff.o(i.sync_window) refers to diskio.o(i.disk_write) for disk_write
+    ff.o(i.validate) refers to diskio.o(i.disk_status) for disk_status
+    ff_gen_drv.o(i.FATFS_GetAttachedDriversNbr) refers to ff_gen_drv.o(.bss) for disk
+    ff_gen_drv.o(i.FATFS_LinkDriver) refers to ff_gen_drv.o(i.FATFS_LinkDriverEx) for FATFS_LinkDriverEx
+    ff_gen_drv.o(i.FATFS_LinkDriverEx) refers to ff_gen_drv.o(.bss) for disk
+    ff_gen_drv.o(i.FATFS_UnLinkDriver) refers to ff_gen_drv.o(i.FATFS_UnLinkDriverEx) for FATFS_UnLinkDriverEx
+    ff_gen_drv.o(i.FATFS_UnLinkDriverEx) refers to ff_gen_drv.o(.bss) for disk
+    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000F) for __rt_final_cpp
+    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$00000011) for __rt_final_exit
+    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry12b.o(.ARM.Collect$$$$0000000E) for __rt_lib_shutdown_fini
+    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
+    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
+    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
+    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
+    entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
+    idiv.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod
+    localtime.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod
+    localtime.o(.text) refers to localtime.o(.bss) for .bss
+    localtime.o(.text) refers to localtime.o(.constdata) for .constdata
+    mktime.o(.text) refers to idiv.o(.text) for __aeabi_idivmod
+    mktime.o(.text) refers to localtime_i.o(.text) for _localtime
+    mktime.o(.text) refers to mktime.o(.constdata) for .constdata
+    printfb.o(i.__0fprintf$bare) refers to printfb.o(i._printf_core) for _printf_core
+    printfb.o(i.__0fprintf$bare) refers to dbg_printf.o(i.fputc) for fputc
+    printfb.o(i.__0printf$bare) refers to printfb.o(i._printf_core) for _printf_core
+    printfb.o(i.__0printf$bare) refers to dbg_printf.o(i.fputc) for fputc
+    printfb.o(i.__0printf$bare) refers to stdout.o(.data) for __stdout
+    printfb.o(i.__0snprintf$bare) refers to printfb.o(i._printf_core) for _printf_core
+    printfb.o(i.__0snprintf$bare) refers to printfb.o(i._snputc) for _snputc
+    printfb.o(i.__0sprintf$bare) refers to printfb.o(i._printf_core) for _printf_core
+    printfb.o(i.__0sprintf$bare) refers to printfb.o(i._sputc) for _sputc
+    printfb.o(i.__0vfprintf$bare) refers to printfb.o(i._printf_core) for _printf_core
+    printfb.o(i.__0vfprintf$bare) refers to dbg_printf.o(i.fputc) for fputc
+    printfb.o(i.__0vprintf$bare) refers to printfb.o(i._printf_core) for _printf_core
+    printfb.o(i.__0vprintf$bare) refers to dbg_printf.o(i.fputc) for fputc
+    printfb.o(i.__0vprintf$bare) refers to stdout.o(.data) for __stdout
+    printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._printf_core) for _printf_core
+    printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._snputc) for _snputc
+    printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._printf_core) for _printf_core
+    printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._sputc) for _sputc
+    printf0.o(i.__0fprintf$0) refers to printf0.o(i._printf_core) for _printf_core
+    printf0.o(i.__0fprintf$0) refers to dbg_printf.o(i.fputc) for fputc
+    printf0.o(i.__0printf$0) refers to printf0.o(i._printf_core) for _printf_core
+    printf0.o(i.__0printf$0) refers to dbg_printf.o(i.fputc) for fputc
+    printf0.o(i.__0printf$0) refers to stdout.o(.data) for __stdout
+    printf0.o(i.__0snprintf$0) refers to printf0.o(i._printf_core) for _printf_core
+    printf0.o(i.__0snprintf$0) refers to printf0.o(i._snputc) for _snputc
+    printf0.o(i.__0sprintf$0) refers to printf0.o(i._printf_core) for _printf_core
+    printf0.o(i.__0sprintf$0) refers to printf0.o(i._sputc) for _sputc
+    printf0.o(i.__0vfprintf$0) refers to printf0.o(i._printf_core) for _printf_core
+    printf0.o(i.__0vfprintf$0) refers to dbg_printf.o(i.fputc) for fputc
+    printf0.o(i.__0vprintf$0) refers to printf0.o(i._printf_core) for _printf_core
+    printf0.o(i.__0vprintf$0) refers to dbg_printf.o(i.fputc) for fputc
+    printf0.o(i.__0vprintf$0) refers to stdout.o(.data) for __stdout
+    printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._printf_core) for _printf_core
+    printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._snputc) for _snputc
+    printf0.o(i.__0vsprintf$0) refers to printf0.o(i._printf_core) for _printf_core
+    printf0.o(i.__0vsprintf$0) refers to printf0.o(i._sputc) for _sputc
+    printf1.o(i.__0fprintf$1) refers to printf1.o(i._printf_core) for _printf_core
+    printf1.o(i.__0fprintf$1) refers to dbg_printf.o(i.fputc) for fputc
+    printf1.o(i.__0printf$1) refers to printf1.o(i._printf_core) for _printf_core
+    printf1.o(i.__0printf$1) refers to dbg_printf.o(i.fputc) for fputc
+    printf1.o(i.__0printf$1) refers to stdout.o(.data) for __stdout
+    printf1.o(i.__0snprintf$1) refers to printf1.o(i._printf_core) for _printf_core
+    printf1.o(i.__0snprintf$1) refers to printf1.o(i._snputc) for _snputc
+    printf1.o(i.__0sprintf$1) refers to printf1.o(i._printf_core) for _printf_core
+    printf1.o(i.__0sprintf$1) refers to printf1.o(i._sputc) for _sputc
+    printf1.o(i.__0vfprintf$1) refers to printf1.o(i._printf_core) for _printf_core
+    printf1.o(i.__0vfprintf$1) refers to dbg_printf.o(i.fputc) for fputc
+    printf1.o(i.__0vprintf$1) refers to printf1.o(i._printf_core) for _printf_core
+    printf1.o(i.__0vprintf$1) refers to dbg_printf.o(i.fputc) for fputc
+    printf1.o(i.__0vprintf$1) refers to stdout.o(.data) for __stdout
+    printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._printf_core) for _printf_core
+    printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._snputc) for _snputc
+    printf1.o(i.__0vsprintf$1) refers to printf1.o(i._printf_core) for _printf_core
+    printf1.o(i.__0vsprintf$1) refers to printf1.o(i._sputc) for _sputc
+    printf1.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod
+    printf2.o(i.__0fprintf$2) refers to printf2.o(i._printf_core) for _printf_core
+    printf2.o(i.__0fprintf$2) refers to dbg_printf.o(i.fputc) for fputc
+    printf2.o(i.__0printf$2) refers to printf2.o(i._printf_core) for _printf_core
+    printf2.o(i.__0printf$2) refers to dbg_printf.o(i.fputc) for fputc
+    printf2.o(i.__0printf$2) refers to stdout.o(.data) for __stdout
+    printf2.o(i.__0snprintf$2) refers to printf2.o(i._printf_core) for _printf_core
+    printf2.o(i.__0snprintf$2) refers to printf2.o(i._snputc) for _snputc
+    printf2.o(i.__0sprintf$2) refers to printf2.o(i._printf_core) for _printf_core
+    printf2.o(i.__0sprintf$2) refers to printf2.o(i._sputc) for _sputc
+    printf2.o(i.__0vfprintf$2) refers to printf2.o(i._printf_core) for _printf_core
+    printf2.o(i.__0vfprintf$2) refers to dbg_printf.o(i.fputc) for fputc
+    printf2.o(i.__0vprintf$2) refers to printf2.o(i._printf_core) for _printf_core
+    printf2.o(i.__0vprintf$2) refers to dbg_printf.o(i.fputc) for fputc
+    printf2.o(i.__0vprintf$2) refers to stdout.o(.data) for __stdout
+    printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._printf_core) for _printf_core
+    printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._snputc) for _snputc
+    printf2.o(i.__0vsprintf$2) refers to printf2.o(i._printf_core) for _printf_core
+    printf2.o(i.__0vsprintf$2) refers to printf2.o(i._sputc) for _sputc
+    printf3.o(i.__0fprintf$3) refers to printf3.o(i._printf_core) for _printf_core
+    printf3.o(i.__0fprintf$3) refers to dbg_printf.o(i.fputc) for fputc
+    printf3.o(i.__0printf$3) refers to printf3.o(i._printf_core) for _printf_core
+    printf3.o(i.__0printf$3) refers to dbg_printf.o(i.fputc) for fputc
+    printf3.o(i.__0printf$3) refers to stdout.o(.data) for __stdout
+    printf3.o(i.__0snprintf$3) refers to printf3.o(i._printf_core) for _printf_core
+    printf3.o(i.__0snprintf$3) refers to printf3.o(i._snputc) for _snputc
+    printf3.o(i.__0sprintf$3) refers to printf3.o(i._printf_core) for _printf_core
+    printf3.o(i.__0sprintf$3) refers to printf3.o(i._sputc) for _sputc
+    printf3.o(i.__0vfprintf$3) refers to printf3.o(i._printf_core) for _printf_core
+    printf3.o(i.__0vfprintf$3) refers to dbg_printf.o(i.fputc) for fputc
+    printf3.o(i.__0vprintf$3) refers to printf3.o(i._printf_core) for _printf_core
+    printf3.o(i.__0vprintf$3) refers to dbg_printf.o(i.fputc) for fputc
+    printf3.o(i.__0vprintf$3) refers to stdout.o(.data) for __stdout
+    printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._printf_core) for _printf_core
+    printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._snputc) for _snputc
+    printf3.o(i.__0vsprintf$3) refers to printf3.o(i._printf_core) for _printf_core
+    printf3.o(i.__0vsprintf$3) refers to printf3.o(i._sputc) for _sputc
+    printf3.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod
+    printf4.o(i.__0fprintf$4) refers to printf4.o(i._printf_core) for _printf_core
+    printf4.o(i.__0fprintf$4) refers to dbg_printf.o(i.fputc) for fputc
+    printf4.o(i.__0printf$4) refers to printf4.o(i._printf_core) for _printf_core
+    printf4.o(i.__0printf$4) refers to dbg_printf.o(i.fputc) for fputc
+    printf4.o(i.__0printf$4) refers to stdout.o(.data) for __stdout
+    printf4.o(i.__0snprintf$4) refers to printf4.o(i._printf_core) for _printf_core
+    printf4.o(i.__0snprintf$4) refers to printf4.o(i._snputc) for _snputc
+    printf4.o(i.__0sprintf$4) refers to printf4.o(i._printf_core) for _printf_core
+    printf4.o(i.__0sprintf$4) refers to printf4.o(i._sputc) for _sputc
+    printf4.o(i.__0vfprintf$4) refers to printf4.o(i._printf_core) for _printf_core
+    printf4.o(i.__0vfprintf$4) refers to dbg_printf.o(i.fputc) for fputc
+    printf4.o(i.__0vprintf$4) refers to printf4.o(i._printf_core) for _printf_core
+    printf4.o(i.__0vprintf$4) refers to dbg_printf.o(i.fputc) for fputc
+    printf4.o(i.__0vprintf$4) refers to stdout.o(.data) for __stdout
+    printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._printf_core) for _printf_core
+    printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._snputc) for _snputc
+    printf4.o(i.__0vsprintf$4) refers to printf4.o(i._printf_core) for _printf_core
+    printf4.o(i.__0vsprintf$4) refers to printf4.o(i._sputc) for _sputc
+    printf4.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod
+    printf5.o(i.__0fprintf$5) refers to printf5.o(i._printf_core) for _printf_core
+    printf5.o(i.__0fprintf$5) refers to dbg_printf.o(i.fputc) for fputc
+    printf5.o(i.__0printf$5) refers to printf5.o(i._printf_core) for _printf_core
+    printf5.o(i.__0printf$5) refers to dbg_printf.o(i.fputc) for fputc
+    printf5.o(i.__0printf$5) refers to stdout.o(.data) for __stdout
+    printf5.o(i.__0snprintf$5) refers to printf5.o(i._printf_core) for _printf_core
+    printf5.o(i.__0snprintf$5) refers to printf5.o(i._snputc) for _snputc
+    printf5.o(i.__0sprintf$5) refers to printf5.o(i._printf_core) for _printf_core
+    printf5.o(i.__0sprintf$5) refers to printf5.o(i._sputc) for _sputc
+    printf5.o(i.__0vfprintf$5) refers to printf5.o(i._printf_core) for _printf_core
+    printf5.o(i.__0vfprintf$5) refers to dbg_printf.o(i.fputc) for fputc
+    printf5.o(i.__0vprintf$5) refers to printf5.o(i._printf_core) for _printf_core
+    printf5.o(i.__0vprintf$5) refers to dbg_printf.o(i.fputc) for fputc
+    printf5.o(i.__0vprintf$5) refers to stdout.o(.data) for __stdout
+    printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._printf_core) for _printf_core
+    printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._snputc) for _snputc
+    printf5.o(i.__0vsprintf$5) refers to printf5.o(i._printf_core) for _printf_core
+    printf5.o(i.__0vsprintf$5) refers to printf5.o(i._sputc) for _sputc
+    printf5.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod
+    printf6.o(i.__0fprintf$6) refers to printf6.o(i._printf_core) for _printf_core
+    printf6.o(i.__0fprintf$6) refers to dbg_printf.o(i.fputc) for fputc
+    printf6.o(i.__0printf$6) refers to printf6.o(i._printf_core) for _printf_core
+    printf6.o(i.__0printf$6) refers to dbg_printf.o(i.fputc) for fputc
+    printf6.o(i.__0printf$6) refers to stdout.o(.data) for __stdout
+    printf6.o(i.__0snprintf$6) refers to printf6.o(i._printf_core) for _printf_core
+    printf6.o(i.__0snprintf$6) refers to printf6.o(i._snputc) for _snputc
+    printf6.o(i.__0sprintf$6) refers to printf6.o(i._printf_core) for _printf_core
+    printf6.o(i.__0sprintf$6) refers to printf6.o(i._sputc) for _sputc
+    printf6.o(i.__0vfprintf$6) refers to printf6.o(i._printf_core) for _printf_core
+    printf6.o(i.__0vfprintf$6) refers to dbg_printf.o(i.fputc) for fputc
+    printf6.o(i.__0vprintf$6) refers to printf6.o(i._printf_core) for _printf_core
+    printf6.o(i.__0vprintf$6) refers to dbg_printf.o(i.fputc) for fputc
+    printf6.o(i.__0vprintf$6) refers to stdout.o(.data) for __stdout
+    printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._printf_core) for _printf_core
+    printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._snputc) for _snputc
+    printf6.o(i.__0vsprintf$6) refers to printf6.o(i._printf_core) for _printf_core
+    printf6.o(i.__0vsprintf$6) refers to printf6.o(i._sputc) for _sputc
+    printf6.o(i._printf_core) refers to printf6.o(i._printf_pre_padding) for _printf_pre_padding
+    printf6.o(i._printf_core) refers to printf6.o(i._printf_post_padding) for _printf_post_padding
+    printf6.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod
+    printf7.o(i.__0fprintf$7) refers to printf7.o(i._printf_core) for _printf_core
+    printf7.o(i.__0fprintf$7) refers to dbg_printf.o(i.fputc) for fputc
+    printf7.o(i.__0printf$7) refers to printf7.o(i._printf_core) for _printf_core
+    printf7.o(i.__0printf$7) refers to dbg_printf.o(i.fputc) for fputc
+    printf7.o(i.__0printf$7) refers to stdout.o(.data) for __stdout
+    printf7.o(i.__0snprintf$7) refers to printf7.o(i._printf_core) for _printf_core
+    printf7.o(i.__0snprintf$7) refers to printf7.o(i._snputc) for _snputc
+    printf7.o(i.__0sprintf$7) refers to printf7.o(i._printf_core) for _printf_core
+    printf7.o(i.__0sprintf$7) refers to printf7.o(i._sputc) for _sputc
+    printf7.o(i.__0vfprintf$7) refers to printf7.o(i._printf_core) for _printf_core
+    printf7.o(i.__0vfprintf$7) refers to dbg_printf.o(i.fputc) for fputc
+    printf7.o(i.__0vprintf$7) refers to printf7.o(i._printf_core) for _printf_core
+    printf7.o(i.__0vprintf$7) refers to dbg_printf.o(i.fputc) for fputc
+    printf7.o(i.__0vprintf$7) refers to stdout.o(.data) for __stdout
+    printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._printf_core) for _printf_core
+    printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._snputc) for _snputc
+    printf7.o(i.__0vsprintf$7) refers to printf7.o(i._printf_core) for _printf_core
+    printf7.o(i.__0vsprintf$7) refers to printf7.o(i._sputc) for _sputc
+    printf7.o(i._printf_core) refers to printf7.o(i._printf_pre_padding) for _printf_pre_padding
+    printf7.o(i._printf_core) refers to printf7.o(i._printf_post_padding) for _printf_post_padding
+    printf7.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod
+    printf8.o(i.__0fprintf$8) refers to printf8.o(i._printf_core) for _printf_core
+    printf8.o(i.__0fprintf$8) refers to dbg_printf.o(i.fputc) for fputc
+    printf8.o(i.__0printf$8) refers to printf8.o(i._printf_core) for _printf_core
+    printf8.o(i.__0printf$8) refers to dbg_printf.o(i.fputc) for fputc
+    printf8.o(i.__0printf$8) refers to stdout.o(.data) for __stdout
+    printf8.o(i.__0snprintf$8) refers to printf8.o(i._printf_core) for _printf_core
+    printf8.o(i.__0snprintf$8) refers to printf8.o(i._snputc) for _snputc
+    printf8.o(i.__0sprintf$8) refers to printf8.o(i._printf_core) for _printf_core
+    printf8.o(i.__0sprintf$8) refers to printf8.o(i._sputc) for _sputc
+    printf8.o(i.__0vfprintf$8) refers to printf8.o(i._printf_core) for _printf_core
+    printf8.o(i.__0vfprintf$8) refers to dbg_printf.o(i.fputc) for fputc
+    printf8.o(i.__0vprintf$8) refers to printf8.o(i._printf_core) for _printf_core
+    printf8.o(i.__0vprintf$8) refers to dbg_printf.o(i.fputc) for fputc
+    printf8.o(i.__0vprintf$8) refers to stdout.o(.data) for __stdout
+    printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._printf_core) for _printf_core
+    printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._snputc) for _snputc
+    printf8.o(i.__0vsprintf$8) refers to printf8.o(i._printf_core) for _printf_core
+    printf8.o(i.__0vsprintf$8) refers to printf8.o(i._sputc) for _sputc
+    printf8.o(i._printf_core) refers to printf8.o(i._printf_pre_padding) for _printf_pre_padding
+    printf8.o(i._printf_core) refers to printf8.o(i._printf_post_padding) for _printf_post_padding
+    printf8.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod
+    printfa.o(i.__0fprintf) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i.__0fprintf) refers to printfa.o(i._printf_core) for _printf_core
+    printfa.o(i.__0fprintf) refers to dbg_printf.o(i.fputc) for fputc
+    printfa.o(i.__0printf) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i.__0printf) refers to printfa.o(i._printf_core) for _printf_core
+    printfa.o(i.__0printf) refers to dbg_printf.o(i.fputc) for fputc
+    printfa.o(i.__0printf) refers to stdout.o(.data) for __stdout
+    printfa.o(i.__0snprintf) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i.__0snprintf) refers to printfa.o(i._printf_core) for _printf_core
+    printfa.o(i.__0snprintf) refers to printfa.o(i._snputc) for _snputc
+    printfa.o(i.__0sprintf) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i.__0sprintf) refers to printfa.o(i._printf_core) for _printf_core
+    printfa.o(i.__0sprintf) refers to printfa.o(i._sputc) for _sputc
+    printfa.o(i.__0vfprintf) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i.__0vfprintf) refers to printfa.o(i._printf_core) for _printf_core
+    printfa.o(i.__0vfprintf) refers to dbg_printf.o(i.fputc) for fputc
+    printfa.o(i.__0vprintf) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i.__0vprintf) refers to printfa.o(i._printf_core) for _printf_core
+    printfa.o(i.__0vprintf) refers to dbg_printf.o(i.fputc) for fputc
+    printfa.o(i.__0vprintf) refers to stdout.o(.data) for __stdout
+    printfa.o(i.__0vsnprintf) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i.__0vsnprintf) refers to printfa.o(i._printf_core) for _printf_core
+    printfa.o(i.__0vsnprintf) refers to printfa.o(i._snputc) for _snputc
+    printfa.o(i.__0vsprintf) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i.__0vsprintf) refers to printfa.o(i._printf_core) for _printf_core
+    printfa.o(i.__0vsprintf) refers to printfa.o(i._sputc) for _sputc
+    printfa.o(i._fp_digits) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i._fp_digits) refers to dmul.o(.text) for __aeabi_dmul
+    printfa.o(i._fp_digits) refers to ddiv.o(.text) for __aeabi_ddiv
+    printfa.o(i._fp_digits) refers to cdrcmple.o(.text) for __aeabi_cdrcmple
+    printfa.o(i._fp_digits) refers to dadd.o(.text) for __aeabi_dadd
+    printfa.o(i._fp_digits) refers to dfixul.o(.text) for __aeabi_d2ulz
+    printfa.o(i._fp_digits) refers to uldiv.o(.text) for __aeabi_uldivmod
+    printfa.o(i._printf_core) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i._printf_core) refers to printfa.o(i._printf_pre_padding) for _printf_pre_padding
+    printfa.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod
+    printfa.o(i._printf_core) refers to printfa.o(i._printf_post_padding) for _printf_post_padding
+    printfa.o(i._printf_core) refers to printfa.o(i._fp_digits) for _fp_digits
+    printfa.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod
+    printfa.o(i._printf_post_padding) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i._printf_pre_padding) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i._snputc) refers (Special) to iusefp.o(.text) for __I$use$fp
+    printfa.o(i._sputc) refers (Special) to iusefp.o(.text) for __I$use$fp
+    fmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
+    fdiv.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
+    fdiv.o(.text) refers to fepilogue.o(.text) for _float_round
+    fflti.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
+    fflti.o(.text) refers to fepilogue.o(.text) for _float_epilogue
+    ffixi.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp
+    entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
+    entry2.o(.ARM.Collect$$$$00002712) refers to startup_a31g12x.o(STACK) for __initial_sp
+    entry2.o(__vectab_stack_and_reset_area) refers to startup_a31g12x.o(STACK) for __initial_sp
+    entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
+    entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
+    entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main
+    entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main
+    uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr
+    uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl
+    localtime_w.o(.text) refers to localtime_i.o(.text) for _localtime
+    localtime_w.o(.text) refers to localtime_w.o(.bss) for .bss
+    localtime_i.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod
+    localtime_i.o(.text) refers to localtime_i.o(.constdata) for .constdata
+    dadd.o(.text) refers to llshl.o(.text) for __aeabi_llsl
+    dadd.o(.text) refers to llsshr.o(.text) for __aeabi_lasr
+    dadd.o(.text) refers to depilogue.o(.text) for _double_epilogue
+    dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue
+    ddiv.o(.text) refers to depilogue.o(.text) for _double_round
+    dfixul.o(.text) refers to llushr.o(.text) for __aeabi_llsr
+    dfixul.o(.text) refers to llshl.o(.text) for __aeabi_llsl
+    init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
+    depilogue.o(.text) refers to depilogue.o(i.__ARM_clz) for __ARM_clz
+    depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl
+    depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr
+    user_diskio_spi.o(i.USER_SPI_initialize) refers to spi10.o(i.SPI10_Initialization) for SPI10_Initialization
+    user_diskio_spi.o(i.USER_SPI_initialize) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.USER_SPI_initialize) refers to user_diskio_spi.o(i.send_cmd) for send_cmd
+    user_diskio_spi.o(i.USER_SPI_initialize) refers to user_diskio_spi.o(i.SPI_Timer_On) for SPI_Timer_On
+    user_diskio_spi.o(i.USER_SPI_initialize) refers to user_diskio_spi.o(i.SPI_Timer_Status) for SPI_Timer_Status
+    user_diskio_spi.o(i.USER_SPI_initialize) refers to user_diskio_spi.o(i.despiselect) for despiselect
+    user_diskio_spi.o(i.USER_SPI_initialize) refers to user_diskio_spi.o(.data) for Stat
+    user_diskio_spi.o(i.USER_SPI_status) refers to user_diskio_spi.o(.data) for Stat
+    user_diskio_spi.o(i.USER_SPI_read) refers to user_diskio_spi.o(i.send_cmd) for send_cmd
+    user_diskio_spi.o(i.USER_SPI_read) refers to user_diskio_spi.o(i.rcvr_datablock) for rcvr_datablock
+    user_diskio_spi.o(i.USER_SPI_read) refers to user_diskio_spi.o(i.despiselect) for despiselect
+    user_diskio_spi.o(i.USER_SPI_read) refers to user_diskio_spi.o(.data) for Stat
+    user_diskio_spi.o(i.USER_SPI_write) refers to user_diskio_spi.o(i.send_cmd) for send_cmd
+    user_diskio_spi.o(i.USER_SPI_write) refers to user_diskio_spi.o(i.xmit_datablock) for xmit_datablock
+    user_diskio_spi.o(i.USER_SPI_write) refers to user_diskio_spi.o(i.despiselect) for despiselect
+    user_diskio_spi.o(i.USER_SPI_write) refers to user_diskio_spi.o(.data) for Stat
+    user_diskio_spi.o(i.USER_SPI_ioctl) refers to user_diskio_spi.o(i.spiselect) for spiselect
+    user_diskio_spi.o(i.USER_SPI_ioctl) refers to user_diskio_spi.o(i.send_cmd) for send_cmd
+    user_diskio_spi.o(i.USER_SPI_ioctl) refers to user_diskio_spi.o(i.rcvr_datablock) for rcvr_datablock
+    user_diskio_spi.o(i.USER_SPI_ioctl) refers to user_diskio_spi.o(i.xchg_spi) for xchg_spi
+    user_diskio_spi.o(i.USER_SPI_ioctl) refers to user_diskio_spi.o(i.wait_ready) for wait_ready
+    user_diskio_spi.o(i.USER_SPI_ioctl) refers to user_diskio_spi.o(i.despiselect) for despiselect
+    user_diskio_spi.o(i.USER_SPI_ioctl) refers to user_diskio_spi.o(.data) for Stat
+
+
+==============================================================================
+
+Removing Unused input sections from the image.
+
+    Removing a31g12x_systemclock.o(.rev16_text), (4 bytes).
+    Removing a31g12x_systemclock.o(.revsh_text), (4 bytes).
+    Removing main.o(.rev16_text), (4 bytes).
+    Removing main.o(.revsh_text), (4 bytes).
+    Removing dbg_printf.o(.rev16_text), (4 bytes).
+    Removing dbg_printf.o(.revsh_text), (4 bytes).
+    Removing dbg_printf.o(i.fputc), (16 bytes).
+    Removing sw_timer.o(.rev16_text), (4 bytes).
+    Removing sw_timer.o(.revsh_text), (4 bytes).
+    Removing sw_timer.o(i.SW_Timer_Callback_UnRegister), (52 bytes).
+    Removing systick_timer.o(.rev16_text), (4 bytes).
+    Removing systick_timer.o(.revsh_text), (4 bytes).
+    Removing ring_buffer.o(.rev16_text), (4 bytes).
+    Removing ring_buffer.o(.revsh_text), (4 bytes).
+    Removing ring_buffer.o(i.RingBuffer_Clear), (34 bytes).
+    Removing gpio_state_led.o(.rev16_text), (4 bytes).
+    Removing gpio_state_led.o(.revsh_text), (4 bytes).
+    Removing gpio_state_led.o(i.Gpio_StateLed_Get_Mode), (12 bytes).
+    Removing gpio_switch.o(.rev16_text), (4 bytes).
+    Removing gpio_switch.o(.revsh_text), (4 bytes).
+    Removing gpio_switch.o(i.Gpio_Swtich_Set_Callback), (40 bytes).
+    Removing gpio_switch.o(i.Gpio_Swtich_Set_PushCount), (32 bytes).
+    Removing uart1.o(.rev16_text), (4 bytes).
+    Removing uart1.o(.revsh_text), (4 bytes).
+    Removing uart1.o(i.Uart1_Transmit), (20 bytes).
+    Removing uart1.o(i.Uart1_TransmitData), (32 bytes).
+    Removing segment_74hc595d.o(.rev16_text), (4 bytes).
+    Removing segment_74hc595d.o(.revsh_text), (4 bytes).
+    Removing segment_74hc595d.o(.bss), (32 bytes).
+    Removing timer12.o(.rev16_text), (4 bytes).
+    Removing timer12.o(.revsh_text), (4 bytes).
+    Removing gpio_i2c.o(.rev16_text), (4 bytes).
+    Removing gpio_i2c.o(.revsh_text), (4 bytes).
+    Removing gpio_i2c.o(i.GPIO_I2C0_Read), (148 bytes).
+    Removing gpio_i2c.o(i.GPIO_I2C0_Start), (76 bytes).
+    Removing gpio_i2c.o(i.GPIO_I2C0_Stop), (64 bytes).
+    Removing gpio_i2c.o(i.GPIO_I2C0_Write), (148 bytes).
+    Removing gpio_i2c.o(i.GPIO_I2C1_Read), (148 bytes).
+    Removing gpio_i2c.o(i.GPIO_I2C1_Start), (76 bytes).
+    Removing gpio_i2c.o(i.GPIO_I2C1_Stop), (64 bytes).
+    Removing gpio_i2c.o(i.GPIO_I2C1_Write), (148 bytes).
+    Removing gpio_i2c.o(i.I2C0_Read), (60 bytes).
+    Removing gpio_i2c.o(i.I2C0_Write), (46 bytes).
+    Removing gpio_i2c.o(i.I2C1_Read), (60 bytes).
+    Removing gpio_i2c.o(i.I2C1_Write), (46 bytes).
+    Removing spi10.o(.rev16_text), (4 bytes).
+    Removing spi10.o(.revsh_text), (4 bytes).
+    Removing spi10.o(i.SPI10_SendReceiveByte), (48 bytes).
+    Removing spi10.o(i.SPI10_SendRecv), (60 bytes).
+    Removing spi10.o(i.SPI10_Transmit), (60 bytes).
+    Removing save_file.o(.rev16_text), (4 bytes).
+    Removing save_file.o(.revsh_text), (4 bytes).
+    Removing save_file.o(i.Save_SensorData_SDCard), (4 bytes).
+    Removing save_file.o(.bss), (1628 bytes).
+    Removing save_file.o(.data), (18 bytes).
+    Removing driver_ds3231.o(i.ds3231_aging_offset_convert_to_data), (52 bytes).
+    Removing driver_ds3231.o(i.ds3231_alarm_clear), (160 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_32khz_output), (100 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_aging_offset), (88 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_alarm1), (320 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_alarm2), (300 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_alarm_interrupt), (104 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_oscillator), (100 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_pin), (100 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_reg), (54 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_square_wave), (100 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_status), (88 bytes).
+    Removing driver_ds3231.o(i.ds3231_get_temperature), (444 bytes).
+    Removing driver_ds3231.o(i.ds3231_info), (152 bytes).
+    Removing driver_ds3231.o(i.ds3231_irq_handler), (136 bytes).
+    Removing driver_ds3231.o(i.ds3231_set_alarm1), (944 bytes).
+    Removing driver_ds3231.o(i.ds3231_set_alarm2), (788 bytes).
+    Removing driver_ds3231.o(i.ds3231_set_reg), (54 bytes).
+    Removing driver_ds3231_basic.o(i.ds3231_basic_deinit), (24 bytes).
+    Removing driver_ds3231_basic.o(i.ds3231_basic_get_ascii_time), (228 bytes).
+    Removing driver_ds3231_basic.o(i.ds3231_basic_get_temperature), (32 bytes).
+    Removing driver_ds3231_basic.o(i.ds3231_basic_get_timestamp), (144 bytes).
+    Removing driver_ds3231_basic.o(i.ds3231_basic_get_timestamp_time_zone), (20 bytes).
+    Removing driver_ds3231_basic.o(i.ds3231_basic_set_timestamp), (128 bytes).
+    Removing driver_ds3231_basic.o(i.ds3231_basic_set_timestamp_time_zone), (16 bytes).
+    Removing driver_ds3231_basic.o(.data), (1 bytes).
+    Removing driver_ds3231_interface_template.o(.rev16_text), (4 bytes).
+    Removing driver_ds3231_interface_template.o(.revsh_text), (4 bytes).
+    Removing rtc_process.o(.rev16_text), (4 bytes).
+    Removing rtc_process.o(.revsh_text), (4 bytes).
+    Removing rtc_process.o(i.RTC_Get_Time), (20 bytes).
+    Removing action_process.o(.rev16_text), (4 bytes).
+    Removing action_process.o(.revsh_text), (4 bytes).
+    Removing action_process.o(.bss), (12 bytes).
+    Removing eeprom.o(.rev16_text), (4 bytes).
+    Removing eeprom.o(.revsh_text), (4 bytes).
+    Removing eeprom.o(i.EEPROM_Read_Mode), (144 bytes).
+    Removing eeprom.o(i.EEPROM_Write_Mode), (156 bytes).
+    Removing eeprom.o(i.FlashMem_Do_PageEr), (20 bytes).
+    Removing eeprom.o(i.FlashMem_Do_PageWt), (24 bytes).
+    Removing eeprom.o(.bss), (128 bytes).
+    Removing buzzer.o(.rev16_text), (4 bytes).
+    Removing buzzer.o(.revsh_text), (4 bytes).
+    Removing gpio_sensor.o(.rev16_text), (4 bytes).
+    Removing gpio_sensor.o(.revsh_text), (4 bytes).
+    Removing segment.o(.rev16_text), (4 bytes).
+    Removing segment.o(.revsh_text), (4 bytes).
+    Removing segment.o(i.Segment_All_Set_Data), (44 bytes).
+    Removing segment.o(i.Segment_In_Sensor_Error), (140 bytes).
+    Removing segment.o(i.Segment_In_Set_Humidity), (96 bytes).
+    Removing segment.o(i.Segment_In_Set_PM_10), (332 bytes).
+    Removing segment.o(i.Segment_In_Set_PM_1p0), (348 bytes).
+    Removing segment.o(i.Segment_In_Set_PM_2p5), (336 bytes).
+    Removing segment.o(i.Segment_In_Set_PM_4p0), (348 bytes).
+    Removing segment.o(i.Segment_In_Set_Temperature), (172 bytes).
+    Removing segment.o(i.Segment_Out_Sensor_Error), (148 bytes).
+    Removing segment.o(i.Segment_Out_Set_Humidity), (100 bytes).
+    Removing segment.o(i.Segment_Out_Set_PM_10), (344 bytes).
+    Removing segment.o(i.Segment_Out_Set_PM_1p0), (352 bytes).
+    Removing segment.o(i.Segment_Out_Set_PM_2p5), (344 bytes).
+    Removing segment.o(i.Segment_Out_Set_PM_4p0), (352 bytes).
+    Removing segment.o(i.Segment_Out_Set_Temperature), (172 bytes).
+    Removing segment.o(i.Segment_Show_Mode), (88 bytes).
+    Removing segment.o(i.Segment_Show_Version), (148 bytes).
+    Removing segment.o(.constdata), (38 bytes).
+    Removing uart_packet.o(.rev16_text), (4 bytes).
+    Removing uart_packet.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_adc.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_adc.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_ChannelSel), (28 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_ClearStatus), (22 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_ConfigInterrupt), (38 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_DeInit), (30 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_GetData), (12 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_GetStatus), (10 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_Init), (66 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_Start), (24 bytes).
+    Removing a31g12x_hal_adc.o(i.HAL_ADC_Stop), (24 bytes).
+    Removing a31g12x_hal_crc.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_crc.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_crc.o(i.HAL_CRC_ConfigAutoMode), (160 bytes).
+    Removing a31g12x_hal_crc.o(i.HAL_CRC_ConfigUserMode), (48 bytes).
+    Removing a31g12x_hal_crc.o(i.HAL_CRC_DeInit), (24 bytes).
+    Removing a31g12x_hal_crc.o(i.HAL_CRC_SetAddress), (40 bytes).
+    Removing a31g12x_hal_crc.o(i.HAL_CRC_UserInput), (76 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTGetCh), (32 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTGetChar), (26 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPutChar), (18 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPutDec), (92 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPutDec16), (168 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPutDec32), (328 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPutHex), (54 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPutHex16), (54 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPutHex32), (54 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPuts), (28 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.UARTPuts_), (28 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.cprintf), (56 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.debug_frmwrk_init), (228 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(i.getstring), (128 bytes).
+    Removing a31g12x_hal_debug_frmwrk.o(.data), (44 bytes).
+    Removing a31g12x_hal_fmc.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_fmc.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_fmc.o(i.HAL_FMC_BulkErase), (76 bytes).
+    Removing a31g12x_hal_fmc.o(i.HAL_FMC_FlashEntry), (96 bytes).
+    Removing a31g12x_hal_fmc.o(i.HAL_FMC_FlashExit), (56 bytes).
+    Removing a31g12x_hal_fmc.o(i.HAL_FMC_FlashFunction), (424 bytes).
+    Removing a31g12x_hal_fmc.o(i.HAL_FMC_PageErase), (64 bytes).
+    Removing a31g12x_hal_fmc.o(i.HAL_FMC_PageWrite), (64 bytes).
+    Removing a31g12x_hal_fmc.o(.data), (16 bytes).
+    Removing a31g12x_hal_i2cn.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_i2cn.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_ConfigInterrupt), (128 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_DeInit), (88 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Init), (184 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_MasterTransferData), (568 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Master_GetState), (32 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Master_IRQHandler_IT), (328 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Master_Receive), (30 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Master_Transmit), (30 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_SlaveTransferData), (204 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_GetState), (32 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_IRQHandler_IT), (172 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_Receive), (30 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_SetAddress1), (34 bytes).
+    Removing a31g12x_hal_i2cn.o(i.HAL_I2C_Slave_SetAddress2), (34 bytes).
+    Removing a31g12x_hal_i2cn.o(i.I2Cn_MWait), (106 bytes).
+    Removing a31g12x_hal_i2cn.o(i.I2Cn_SWait), (114 bytes).
+    Removing a31g12x_hal_i2cn.o(i.I2Cn_getNum), (52 bytes).
+    Removing a31g12x_hal_i2cn.o(i.NVIC_ClearPendingIRQ), (20 bytes).
+    Removing a31g12x_hal_i2cn.o(i.NVIC_DisableIRQ), (20 bytes).
+    Removing a31g12x_hal_i2cn.o(i.NVIC_EnableIRQ), (20 bytes).
+    Removing a31g12x_hal_i2cn.o(.bss), (96 bytes).
+    Removing a31g12x_hal_i2cn.o(.data), (6 bytes).
+    Removing a31g12x_hal_intc.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_intc.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EIntCfg), (288 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EIntPB_ClearIntStatus), (12 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EIntPB_GetIntStatus), (12 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EIntPC_ClearIntStatus), (12 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EIntPC_GetIntStatus), (12 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EIntPE_ClearIntStatus), (12 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EIntPE_GetIntStatus), (12 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EIntPx_SetReg), (184 bytes).
+    Removing a31g12x_hal_intc.o(i.HAL_INT_EInt_MaskEnable), (16 bytes).
+    Removing a31g12x_hal_lcd.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_lcd.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_lcd.o(i.HAL_LCD_ClearDspRam), (28 bytes).
+    Removing a31g12x_hal_lcd.o(i.HAL_LCD_Init), (60 bytes).
+    Removing a31g12x_hal_lcd.o(i.HAL_LCD_SetRegister), (16 bytes).
+    Removing a31g12x_hal_lcd.o(i.HAL_LCD_WriteDspRam), (44 bytes).
+    Removing a31g12x_hal_pcu.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_pcu.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutDataMask), (26 bytes).
+    Removing a31g12x_hal_pcu.o(i.HAL_GPIO_Init), (18 bytes).
+    Removing a31g12x_hal_pcu.o(i.HAL_GPIO_TogglePin), (34 bytes).
+    Removing a31g12x_hal_pcu.o(i.HAL_GPIO_WritePin), (4 bytes).
+    Removing a31g12x_hal_pwr.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_pwr.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_pwr.o(i.HAL_PWR_EnterPowerDownMode), (24 bytes).
+    Removing a31g12x_hal_pwr.o(i.HAL_PWR_EnterSleepMode), (24 bytes).
+    Removing a31g12x_hal_scu.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_scu.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_CLKO_PinConfig), (64 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_ClockMonitoring_Disable), (32 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_ClockOutput), (20 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_ClockSource_Config), (36 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_ClockSource_Disable), (32 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_HIRCTRM_ClockConfig), (72 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_MainXtal_PinConfig), (76 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_ClockSelection), (24 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_ResetConfig), (36 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_SetReset1), (28 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_ResetSourceStatus), (16 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_SetNMI), (12 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_SetWakupData), (12 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_SoftwareReset_Config), (28 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_SubXtal_PinConfig), (60 bytes).
+    Removing a31g12x_hal_scu.o(i.HAL_SCU_WDTRCTRM_ClockConfig), (108 bytes).
+    Removing a31g12x_hal_sculv.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_sculv.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_sculv.o(i.HAL_LVI_Init), (32 bytes).
+    Removing a31g12x_hal_timer1n.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_timer1n.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_timer1n.o(i.HAL_TIMER1n_DeInit), (152 bytes).
+    Removing a31g12x_hal_timer1n.o(i.HAL_TIMER1n_SetRegister), (18 bytes).
+    Removing a31g12x_hal_timer2n.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_timer2n.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_ClearCounter), (32 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_ClearStatus), (24 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_Cmd), (40 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_ConfigInterrupt), (88 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_DeInit), (76 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_GetCaptureData), (6 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_GetStatus), (8 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_Init), (348 bytes).
+    Removing a31g12x_hal_timer2n.o(i.HAL_TIMER2n_UpdateCountValue), (34 bytes).
+    Removing a31g12x_hal_timer3n.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_timer3n.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_ClearStatus_IT), (16 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_ClockPrescaler), (20 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_ConfigInterrupt), (38 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_DeInit), (52 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_GetStatus_IT), (6 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_Init), (100 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_MPWMCmd), (32 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_OutputCtrl), (44 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_SetADCTrigger), (18 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_SetADuty), (18 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_SetBDuty), (18 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_SetCDuty), (18 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_SetDelayTime), (44 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_SetHizReg), (16 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_SetPeriod), (18 bytes).
+    Removing a31g12x_hal_timer3n.o(i.HAL_TIMER3n_Start), (42 bytes).
+    Removing a31g12x_hal_uartn.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_uartn.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_uartn.o(i.HAL_UART_CheckBusy), (20 bytes).
+    Removing a31g12x_hal_uartn.o(i.HAL_UART_DataControlConfig), (78 bytes).
+    Removing a31g12x_hal_uartn.o(i.HAL_UART_DeInit), (64 bytes).
+    Removing a31g12x_hal_uartn.o(i.HAL_UART_ForceBreak), (22 bytes).
+    Removing a31g12x_hal_uartn.o(i.HAL_UART_GetLineStatus), (10 bytes).
+    Removing a31g12x_hal_uartn.o(i.HAL_UART_IFDelayConfig), (20 bytes).
+    Removing a31g12x_hal_uartn.o(.bss), (80 bytes).
+    Removing a31g12x_hal_usart1n.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_usart1n.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_CheckBusy), (20 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_ConfigInterrupt), (76 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_DeInit), (112 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_GetStatus), (8 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_Receive), (114 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_Transmit), (132 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_TransmitByte), (16 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_UART_Mode_Config), (34 bytes).
+    Removing a31g12x_hal_usart1n.o(i.HAL_USART_USRT_Mode_Config), (42 bytes).
+    Removing a31g12x_hal_wdt.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_wdt.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_wdt.o(i.HAL_WDT_ClearStatus), (16 bytes).
+    Removing a31g12x_hal_wdt.o(i.HAL_WDT_ConfigInterrupt), (76 bytes).
+    Removing a31g12x_hal_wdt.o(i.HAL_WDT_DeInit), (20 bytes).
+    Removing a31g12x_hal_wdt.o(i.HAL_WDT_GetCurrentCount), (12 bytes).
+    Removing a31g12x_hal_wdt.o(i.HAL_WDT_GetStatus), (12 bytes).
+    Removing a31g12x_hal_wdt.o(i.HAL_WDT_Init), (88 bytes).
+    Removing a31g12x_hal_wdt.o(i.HAL_WDT_ReloadTimeCounter), (16 bytes).
+    Removing a31g12x_hal_wdt.o(i.HAL_WDT_Start), (48 bytes).
+    Removing a31g12x_hal_wt.o(.rev16_text), (4 bytes).
+    Removing a31g12x_hal_wt.o(.revsh_text), (4 bytes).
+    Removing a31g12x_hal_wt.o(i.HAL_WT_ClearStatus), (20 bytes).
+    Removing a31g12x_hal_wt.o(i.HAL_WT_ConfigInterrupt), (44 bytes).
+    Removing a31g12x_hal_wt.o(i.HAL_WT_DeInit), (12 bytes).
+    Removing a31g12x_hal_wt.o(i.HAL_WT_GetCurrentCount), (16 bytes).
+    Removing a31g12x_hal_wt.o(i.HAL_WT_GetStatus), (16 bytes).
+    Removing a31g12x_hal_wt.o(i.HAL_WT_Init), (48 bytes).
+    Removing a31g12x_hal_wt.o(i.HAL_WT_SetRegister), (16 bytes).
+    Removing a31g12x_hal_wt.o(i.HAL_WT_Start), (40 bytes).
+    Removing startup_a31g12x.o(HEAP), (128 bytes).
+    Removing system_a31g12x.o(.rev16_text), (4 bytes).
+    Removing system_a31g12x.o(.revsh_text), (4 bytes).
+    Removing system_a31g12x.o(i.SystemCoreClockUpdate), (136 bytes).
+    Removing fatfs.o(.rev16_text), (4 bytes).
+    Removing fatfs.o(.revsh_text), (4 bytes).
+    Removing fatfs.o(i.MX_FATFS_Init), (28 bytes).
+    Removing fatfs.o(i.get_fattime), (4 bytes).
+    Removing fatfs.o(.bss), (1116 bytes).
+    Removing fatfs.o(.data), (5 bytes).
+    Removing user_diskio.o(.rev16_text), (4 bytes).
+    Removing user_diskio.o(.revsh_text), (4 bytes).
+    Removing user_diskio.o(i.USER_initialize), (12 bytes).
+    Removing user_diskio.o(i.USER_ioctl), (20 bytes).
+    Removing user_diskio.o(i.USER_read), (24 bytes).
+    Removing user_diskio.o(i.USER_status), (12 bytes).
+    Removing user_diskio.o(i.USER_write), (24 bytes).
+    Removing user_diskio.o(.data), (24 bytes).
+    Removing user_diskio_spi.o(.rev16_text), (4 bytes).
+    Removing user_diskio_spi.o(.revsh_text), (4 bytes).
+    Removing user_diskio_spi.o(i.SPI_Timer_On), (28 bytes).
+    Removing user_diskio_spi.o(i.SPI_Timer_Status), (36 bytes).
+    Removing user_diskio_spi.o(i.despiselect), (20 bytes).
+    Removing user_diskio_spi.o(i.rcvr_datablock), (66 bytes).
+    Removing user_diskio_spi.o(i.rcvr_spi_multi), (26 bytes).
+    Removing user_diskio_spi.o(i.send_cmd), (156 bytes).
+    Removing user_diskio_spi.o(i.spiselect), (42 bytes).
+    Removing user_diskio_spi.o(i.wait_ready), (48 bytes).
+    Removing user_diskio_spi.o(i.xchg_spi), (16 bytes).
+    Removing user_diskio_spi.o(i.xmit_datablock), (76 bytes).
+    Removing user_diskio_spi.o(i.xmit_spi_multi), (16 bytes).
+    Removing user_diskio_spi.o(.data), (12 bytes).
+    Removing diskio.o(.rev16_text), (4 bytes).
+    Removing diskio.o(.revsh_text), (4 bytes).
+    Removing diskio.o(i.disk_initialize), (48 bytes).
+    Removing diskio.o(i.disk_ioctl), (36 bytes).
+    Removing diskio.o(i.disk_read), (44 bytes).
+    Removing diskio.o(i.disk_status), (28 bytes).
+    Removing diskio.o(i.disk_write), (44 bytes).
+    Removing diskio.o(i.get_fattime), (4 bytes).
+    Removing ff.o(.rev16_text), (4 bytes).
+    Removing ff.o(.revsh_text), (4 bytes).
+    Removing ff.o(i.check_fs), (164 bytes).
+    Removing ff.o(i.chk_chr), (22 bytes).
+    Removing ff.o(i.chk_lock), (152 bytes).
+    Removing ff.o(i.clear_lock), (44 bytes).
+    Removing ff.o(i.clmt_clust), (70 bytes).
+    Removing ff.o(i.clust2sect), (40 bytes).
+    Removing ff.o(i.create_chain), (260 bytes).
+    Removing ff.o(i.create_name), (296 bytes).
+    Removing ff.o(i.dec_lock), (76 bytes).
+    Removing ff.o(i.dir_alloc), (110 bytes).
+    Removing ff.o(i.dir_find), (114 bytes).
+    Removing ff.o(i.dir_next), (444 bytes).
+    Removing ff.o(i.dir_read), (142 bytes).
+    Removing ff.o(i.dir_register), (88 bytes).
+    Removing ff.o(i.dir_remove), (88 bytes).
+    Removing ff.o(i.dir_sdi), (264 bytes).
+    Removing ff.o(i.enq_lock), (40 bytes).
+    Removing ff.o(i.f_chmod), (100 bytes).
+    Removing ff.o(i.f_close), (56 bytes).
+    Removing ff.o(i.f_closedir), (54 bytes).
+    Removing ff.o(i.f_getfree), (304 bytes).
+    Removing ff.o(i.f_gets), (84 bytes).
+    Removing ff.o(i.f_lseek), (1104 bytes).
+    Removing ff.o(i.f_mkdir), (410 bytes).
+    Removing ff.o(i.f_mkfs), (1728 bytes).
+    Removing ff.o(i.f_mount), (112 bytes).
+    Removing ff.o(i.f_open), (540 bytes).
+    Removing ff.o(i.f_opendir), (210 bytes).
+    Removing ff.o(i.f_printf), (672 bytes).
+    Removing ff.o(i.f_putc), (66 bytes).
+    Removing ff.o(i.f_puts), (76 bytes).
+    Removing ff.o(i.f_read), (660 bytes).
+    Removing ff.o(i.f_readdir), (106 bytes).
+    Removing ff.o(i.f_rename), (338 bytes).
+    Removing ff.o(i.f_stat), (72 bytes).
+    Removing ff.o(i.f_sync), (256 bytes).
+    Removing ff.o(i.f_truncate), (308 bytes).
+    Removing ff.o(i.f_unlink), (226 bytes).
+    Removing ff.o(i.f_utime), (102 bytes).
+    Removing ff.o(i.f_write), (776 bytes).
+    Removing ff.o(i.find_volume), (1144 bytes).
+    Removing ff.o(i.follow_path), (174 bytes).
+    Removing ff.o(i.get_fat), (260 bytes).
+    Removing ff.o(i.get_fileinfo), (118 bytes).
+    Removing ff.o(i.get_ldnumber), (76 bytes).
+    Removing ff.o(i.inc_lock), (228 bytes).
+    Removing ff.o(i.ld_clust), (38 bytes).
+    Removing ff.o(i.mem_cmp), (42 bytes).
+    Removing ff.o(i.mem_cpy), (26 bytes).
+    Removing ff.o(i.mem_set), (20 bytes).
+    Removing ff.o(i.move_window), (68 bytes).
+    Removing ff.o(i.put_fat), (354 bytes).
+    Removing ff.o(i.putc_bfd), (78 bytes).
+    Removing ff.o(i.remove_chain), (140 bytes).
+    Removing ff.o(i.st_clust), (20 bytes).
+    Removing ff.o(i.sync_fs), (280 bytes).
+    Removing ff.o(i.sync_window), (116 bytes).
+    Removing ff.o(i.validate), (96 bytes).
+    Removing ff.o(.bss), (24 bytes).
+    Removing ff.o(.constdata), (172 bytes).
+    Removing ff.o(.data), (6 bytes).
+    Removing ff_gen_drv.o(.rev16_text), (4 bytes).
+    Removing ff_gen_drv.o(.revsh_text), (4 bytes).
+    Removing ff_gen_drv.o(i.FATFS_GetAttachedDriversNbr), (12 bytes).
+    Removing ff_gen_drv.o(i.FATFS_LinkDriver), (18 bytes).
+    Removing ff_gen_drv.o(i.FATFS_LinkDriverEx), (84 bytes).
+    Removing ff_gen_drv.o(i.FATFS_UnLinkDriver), (14 bytes).
+    Removing ff_gen_drv.o(i.FATFS_UnLinkDriverEx), (68 bytes).
+    Removing ff_gen_drv.o(.bss), (12 bytes).
+    Removing fmul.o(.text), (122 bytes).
+    Removing fflti.o(.text), (22 bytes).
+    Removing dadd.o(.text), (360 bytes).
+    Removing dmul.o(.text), (208 bytes).
+    Removing ddiv.o(.text), (240 bytes).
+    Removing dfixul.o(.text), (64 bytes).
+    Removing cdrcmple.o(.text), (40 bytes).
+    Removing depilogue.o(.text), (190 bytes).
+    Removing user_diskio_spi.o(i.USER_SPI_initialize), (352 bytes).
+    Removing user_diskio_spi.o(i.USER_SPI_status), (20 bytes).
+    Removing user_diskio_spi.o(i.USER_SPI_read), (160 bytes).
+    Removing user_diskio_spi.o(i.USER_SPI_write), (200 bytes).
+    Removing user_diskio_spi.o(i.USER_SPI_ioctl), (576 bytes).
+    Removing depilogue.o(i.__ARM_clz), (46 bytes).
+
+436 unused section(s) (total 41236 bytes) removed from the image.
+
+==============================================================================
+
+Image Symbol Table
+
+    Local Symbols
+
+    Symbol Name                              Value     Ov Type        Size  Object(Section)
+
+    RESET                                    0x00000000   Section      176  startup_a31g12x.o(RESET)
+    ../clib/microlib/division.c              0x00000000   Number         0  idiv.o ABSOLUTE
+    ../clib/microlib/division.c              0x00000000   Number         0  uldiv.o ABSOLUTE
+    ../clib/microlib/division.c              0x00000000   Number         0  uidiv.o ABSOLUTE
+    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry8a.o ABSOLUTE
+    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry12b.o ABSOLUTE
+    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry12a.o ABSOLUTE
+    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry7b.o ABSOLUTE
+    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry7a.o ABSOLUTE
+    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry11b.o ABSOLUTE
+    ../clib/microlib/init/entry.s            0x00000000   Number         0  entry11a.o ABSOLUTE
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+    i.HAL_TIMER1n_Init                       0x00000a68   Section        0  a31g12x_hal_timer1n.o(i.HAL_TIMER1n_Init)
+    i.HAL_UART_ConfigInterrupt               0x00000bd0   Section        0  a31g12x_hal_uartn.o(i.HAL_UART_ConfigInterrupt)
+    i.HAL_UART_ConfigStructInit              0x00000c1c   Section        0  a31g12x_hal_uartn.o(i.HAL_UART_ConfigStructInit)
+    i.HAL_UART_Init                          0x00000c3c   Section        0  a31g12x_hal_uartn.o(i.HAL_UART_Init)
+    i.HAL_UART_Receive                       0x00000d40   Section        0  a31g12x_hal_uartn.o(i.HAL_UART_Receive)
+    i.HAL_UART_ReceiveByte                   0x00000db4   Section        0  a31g12x_hal_uartn.o(i.HAL_UART_ReceiveByte)
+    i.HAL_UART_Transmit                      0x00000dbc   Section        0  a31g12x_hal_uartn.o(i.HAL_UART_Transmit)
+    i.HAL_UART_TransmitByte                  0x00000e3c   Section        0  a31g12x_hal_uartn.o(i.HAL_UART_TransmitByte)
+    i.HAL_USART_ClearStatus                  0x00000e4c   Section        0  a31g12x_hal_usart1n.o(i.HAL_USART_ClearStatus)
+    i.HAL_USART_DataControlConfig            0x00000e86   Section        0  a31g12x_hal_usart1n.o(i.HAL_USART_DataControlConfig)
+    i.HAL_USART_Enable                       0x00000ef0   Section        0  a31g12x_hal_usart1n.o(i.HAL_USART_Enable)
+    i.HAL_USART_Init                         0x00000f18   Section        0  a31g12x_hal_usart1n.o(i.HAL_USART_Init)
+    i.HAL_USART_ReceiveByte                  0x0000100c   Section        0  a31g12x_hal_usart1n.o(i.HAL_USART_ReceiveByte)
+    i.HAL_USART_SPI_Mode_Config              0x00001014   Section        0  a31g12x_hal_usart1n.o(i.HAL_USART_SPI_Mode_Config)
+    i.HardFault_Handler                      0x0000103c   Section        0  a31g12x_interrupt.o(i.HardFault_Handler)
+    i.I2C2_Read                              0x00001040   Section        0  gpio_i2c.o(i.I2C2_Read)
+    i.I2C2_Write                             0x0000107c   Section        0  gpio_i2c.o(i.I2C2_Write)
+    i.NMI_Handler                            0x000010aa   Section        0  a31g12x_interrupt.o(i.NMI_Handler)
+    i.NVIC_SetPriority                       0x000010ac   Section        0  a31g12x_systemclock.o(i.NVIC_SetPriority)
+    NVIC_SetPriority                         0x000010ad   Thumb Code   110  a31g12x_systemclock.o(i.NVIC_SetPriority)
+    i.NVIC_SetPriority                       0x00001124   Section        0  uart1.o(i.NVIC_SetPriority)
+    NVIC_SetPriority                         0x00001125   Thumb Code   110  uart1.o(i.NVIC_SetPriority)
+    i.NVIC_SetPriority                       0x0000119c   Section        0  timer12.o(i.NVIC_SetPriority)
+    NVIC_SetPriority                         0x0000119d   Thumb Code   110  timer12.o(i.NVIC_SetPriority)
+    i.PendSV_Handler                         0x00001214   Section        0  a31g12x_interrupt.o(i.PendSV_Handler)
+    i.RTC_Get_IC_Time_Process                0x00001218   Section        0  rtc_process.o(i.RTC_Get_IC_Time_Process)
+    RTC_Get_IC_Time_Process                  0x00001219   Thumb Code    84  rtc_process.o(i.RTC_Get_IC_Time_Process)
+    i.RTC_Process_Initialization             0x00001270   Section        0  rtc_process.o(i.RTC_Process_Initialization)
+    i.RingBuffer_Dequeue                     0x00001288   Section        0  ring_buffer.o(i.RingBuffer_Dequeue)
+    i.RingBuffer_Enqueue                     0x000012c6   Section        0  ring_buffer.o(i.RingBuffer_Enqueue)
+    i.RingBuffer_GetData                     0x00001306   Section        0  ring_buffer.o(i.RingBuffer_GetData)
+    i.RingBuffer_Get_DataSize                0x00001314   Section        0  ring_buffer.o(i.RingBuffer_Get_DataSize)
+    i.RingBuffer_Initialization              0x00001346   Section        0  ring_buffer.o(i.RingBuffer_Initialization)
+    i.RingBuffer_PopData                     0x0000136c   Section        0  ring_buffer.o(i.RingBuffer_PopData)
+    i.RingBuffer_isEmpty                     0x00001392   Section        0  ring_buffer.o(i.RingBuffer_isEmpty)
+    i.RingBuffer_isFull                      0x000013a4   Section        0  ring_buffer.o(i.RingBuffer_isFull)
+    i.SPI10_Initialization                   0x000013c8   Section        0  spi10.o(i.SPI10_Initialization)
+    i.SVC_Handler                            0x000014bc   Section        0  a31g12x_interrupt.o(i.SVC_Handler)
+    i.SW_Timer_Callback_Process              0x000014c0   Section        0  sw_timer.o(i.SW_Timer_Callback_Process)
+    i.SW_Timer_Callback_Register             0x00001540   Section        0  sw_timer.o(i.SW_Timer_Callback_Register)
+    i.Segemet_Output_Process                 0x00001594   Section        0  segment_74hc595d.o(i.Segemet_Output_Process)
+    Segemet_Output_Process                   0x00001595   Thumb Code   388  segment_74hc595d.o(i.Segemet_Output_Process)
+    i.Segment_Initialization                 0x00001738   Section        0  segment_74hc595d.o(i.Segment_Initialization)
+    i.Segment_Output_Data                    0x000017bc   Section        0  segment_74hc595d.o(i.Segment_Output_Data)
+    Segment_Output_Data                      0x000017bd   Thumb Code   190  segment_74hc595d.o(i.Segment_Output_Data)
+    i.State_Led_Output_Process               0x00001884   Section        0  gpio_state_led.o(i.State_Led_Output_Process)
+    State_Led_Output_Process                 0x00001885   Thumb Code   128  gpio_state_led.o(i.State_Led_Output_Process)
+    i.SysTick_Handler                        0x00001914   Section        0  systick_timer.o(i.SysTick_Handler)
+    i.SystemInit                             0x0000193c   Section        0  system_a31g12x.o(i.SystemInit)
+    i.System_Clock_Initialization            0x00001960   Section        0  a31g12x_systemclock.o(i.System_Clock_Initialization)
+    i.Systick_Initialization                 0x000019b0   Section        0  a31g12x_systemclock.o(i.Systick_Initialization)
+    i.TIMER12_Handler                        0x00001a08   Section        0  timer12.o(i.TIMER12_Handler)
+    i.Timer12_Initialization                 0x00001a3c   Section        0  timer12.o(i.Timer12_Initialization)
+    i.Timer12_Set_Match_Interrupt_Callback   0x00001a98   Section        0  timer12.o(i.Timer12_Set_Match_Interrupt_Callback)
+    i.UART1_Handler                          0x00001aa4   Section        0  uart1.o(i.UART1_Handler)
+    i.Uart1_Get_RecvData                     0x00001acc   Section        0  uart1.o(i.Uart1_Get_RecvData)
+    i.Uart1_Get_RecvDataCount                0x00001ae0   Section        0  uart1.o(i.Uart1_Get_RecvDataCount)
+    i.Uart1_Initialization                   0x00001af0   Section        0  uart1.o(i.Uart1_Initialization)
+    i.Uart1_Receive_Handler                  0x00001bb0   Section        0  uart1.o(i.Uart1_Receive_Handler)
+    Uart1_Receive_Handler                    0x00001bb1   Thumb Code    42  uart1.o(i.Uart1_Receive_Handler)
+    i.Uart1_Transmit_Process                 0x00001be4   Section        0  uart1.o(i.Uart1_Transmit_Process)
+    Uart1_Transmit_Process                   0x00001be5   Thumb Code    46  uart1.o(i.Uart1_Transmit_Process)
+    i.Uart_Packet_Initialization             0x00001c1c   Section        0  uart_packet.o(i.Uart_Packet_Initialization)
+    i.Uart_Packet_Make_Process               0x00001c38   Section        0  uart_packet.o(i.Uart_Packet_Make_Process)
+    Uart_Packet_Make_Process                 0x00001c39   Thumb Code   308  uart_packet.o(i.Uart_Packet_Make_Process)
+    i.Uart_Packet_Process                    0x00001d7c   Section        0  uart_packet.o(i.Uart_Packet_Process)
+    Uart_Packet_Process                      0x00001d7d   Thumb Code   150  uart_packet.o(i.Uart_Packet_Process)
+    i.__ARM_common_switch8                   0x00001e12   Section        0  segment_74hc595d.o(i.__ARM_common_switch8)
+    i.__scatterload_copy                     0x00001e2e   Section       14  handlers.o(i.__scatterload_copy)
+    i.__scatterload_null                     0x00001e3c   Section        2  handlers.o(i.__scatterload_null)
+    i.__scatterload_zeroinit                 0x00001e3e   Section       14  handlers.o(i.__scatterload_zeroinit)
+    i.a_ds3231_bcd2hex                       0x00001e4c   Section        0  driver_ds3231.o(i.a_ds3231_bcd2hex)
+    a_ds3231_bcd2hex                         0x00001e4d   Thumb Code    20  driver_ds3231.o(i.a_ds3231_bcd2hex)
+    i.a_ds3231_hex2bcd                       0x00001e60   Section        0  driver_ds3231.o(i.a_ds3231_hex2bcd)
+    a_ds3231_hex2bcd                         0x00001e61   Thumb Code    34  driver_ds3231.o(i.a_ds3231_hex2bcd)
+    i.a_ds3231_iic_multiple_read             0x00001e82   Section        0  driver_ds3231.o(i.a_ds3231_iic_multiple_read)
+    a_ds3231_iic_multiple_read               0x00001e83   Thumb Code    36  driver_ds3231.o(i.a_ds3231_iic_multiple_read)
+    i.a_ds3231_iic_write                     0x00001ea6   Section        0  driver_ds3231.o(i.a_ds3231_iic_write)
+    a_ds3231_iic_write                       0x00001ea7   Thumb Code    30  driver_ds3231.o(i.a_ds3231_iic_write)
+    i.ds3231_aging_offset_convert_to_register 0x00001ec4   Section        0  driver_ds3231.o(i.ds3231_aging_offset_convert_to_register)
+    i.ds3231_basic_get_time                  0x00001ef8   Section        0  driver_ds3231_basic.o(i.ds3231_basic_get_time)
+    i.ds3231_basic_init                      0x00001f14   Section        0  driver_ds3231_basic.o(i.ds3231_basic_init)
+    i.ds3231_basic_set_time                  0x000021a8   Section        0  driver_ds3231_basic.o(i.ds3231_basic_set_time)
+    i.ds3231_deinit                          0x000021c4   Section        0  driver_ds3231.o(i.ds3231_deinit)
+    i.ds3231_get_time                        0x00002210   Section        0  driver_ds3231.o(i.ds3231_get_time)
+    i.ds3231_init                            0x0000231c   Section        0  driver_ds3231.o(i.ds3231_init)
+    i.ds3231_interface_debug_print           0x00002508   Section        0  driver_ds3231_interface_template.o(i.ds3231_interface_debug_print)
+    i.ds3231_interface_delay_ms              0x0000250a   Section        0  driver_ds3231_interface_template.o(i.ds3231_interface_delay_ms)
+    i.ds3231_interface_iic_deinit            0x00002516   Section        0  driver_ds3231_interface_template.o(i.ds3231_interface_iic_deinit)
+    i.ds3231_interface_iic_init              0x0000251a   Section        0  driver_ds3231_interface_template.o(i.ds3231_interface_iic_init)
+    i.ds3231_interface_iic_read              0x0000251e   Section        0  driver_ds3231_interface_template.o(i.ds3231_interface_iic_read)
+    i.ds3231_interface_iic_write             0x00002540   Section        0  driver_ds3231_interface_template.o(i.ds3231_interface_iic_write)
+    i.ds3231_interface_receive_callback      0x00002570   Section        0  driver_ds3231_interface_template.o(i.ds3231_interface_receive_callback)
+    i.ds3231_set_32khz_output                0x000025c4   Section        0  driver_ds3231.o(i.ds3231_set_32khz_output)
+    i.ds3231_set_aging_offset                0x00002670   Section        0  driver_ds3231.o(i.ds3231_set_aging_offset)
+    i.ds3231_set_alarm_interrupt             0x000026c8   Section        0  driver_ds3231.o(i.ds3231_set_alarm_interrupt)
+    i.ds3231_set_oscillator                  0x00002778   Section        0  driver_ds3231.o(i.ds3231_set_oscillator)
+    i.ds3231_set_pin                         0x0000282c   Section        0  driver_ds3231.o(i.ds3231_set_pin)
+    i.ds3231_set_square_wave                 0x000028d8   Section        0  driver_ds3231.o(i.ds3231_set_square_wave)
+    i.ds3231_set_time                        0x00002984   Section        0  driver_ds3231.o(i.ds3231_set_time)
+    i.main                                   0x00002e98   Section        0  main.o(i.main)
+    i.millis                                 0x00002f0c   Section        0  systick_timer.o(i.millis)
+    i.timer_test                             0x00002f18   Section        0  main.o(i.timer_test)
+    i.uart_set_divisors                      0x00002f1c   Section        0  a31g12x_hal_uartn.o(i.uart_set_divisors)
+    uart_set_divisors                        0x00002f1d   Thumb Code    56  a31g12x_hal_uartn.o(i.uart_set_divisors)
+    i.usart_set_divisors                     0x00002f58   Section        0  a31g12x_hal_usart1n.o(i.usart_set_divisors)
+    usart_set_divisors                       0x00002f59   Thumb Code    58  a31g12x_hal_usart1n.o(i.usart_set_divisors)
+    .ARM.__AT_0x1FFFF200                     0x1ffff200   Section       68  option_a31g12x.o(.ARM.__AT_0x1FFFF200)
+    .ARM.__AT_0x1FFFF400                     0x1ffff400   Section      128  option_a31g12x.o(.ARM.__AT_0x1FFFF400)
+    .ARM.__AT_0x1FFFF600                     0x1ffff600   Section      128  option_a31g12x.o(.ARM.__AT_0x1FFFF600)
+    .data                                    0x20000000   Section        8  systick_timer.o(.data)
+    tick_count                               0x20000000   Data           4  systick_timer.o(.data)
+    .data                                    0x20000008   Section       64  gpio_state_led.o(.data)
+    StateLedMode                             0x20000008   Data           1  gpio_state_led.o(.data)
+    StateLedStep                             0x20000009   Data           1  gpio_state_led.o(.data)
+    StateLedTime                             0x2000000c   Data           8  gpio_state_led.o(.data)
+    StateLedCheckTime                        0x20000014   Data           4  gpio_state_led.o(.data)
+    StateLedOnOffTime                        0x20000018   Data          48  gpio_state_led.o(.data)
+    .data                                    0x20000048   Section       36  gpio_switch.o(.data)
+    KeyCheckInfo                             0x20000048   Data          36  gpio_switch.o(.data)
+    .data                                    0x2000006c   Section       16  segment_74hc595d.o(.data)
+    SegmentOutputStep                        0x2000006c   Data           1  segment_74hc595d.o(.data)
+    HC595_OutputData                         0x2000006d   Data           5  segment_74hc595d.o(.data)
+    HC595_OutputMode                         0x20000072   Data           1  segment_74hc595d.o(.data)
+    ToggleTickCount                          0x20000074   Data           4  segment_74hc595d.o(.data)
+    isToggle                                 0x20000078   Data           1  segment_74hc595d.o(.data)
+    temp                                     0x2000007b   Data           1  segment_74hc595d.o(.data)
+    .data                                    0x2000007c   Section        4  timer12.o(.data)
+    Timer12_Match_Callback                   0x2000007c   Data           4  timer12.o(.data)
+    .data                                    0x20000080   Section        8  rtc_process.o(.data)
+    rtc_Time                                 0x20000080   Data           8  rtc_process.o(.data)
+    .data                                    0x20000088   Section       12  buzzer.o(.data)
+    isBuzzerOn                               0x20000088   Data           1  buzzer.o(.data)
+    BuzzerStartTick                          0x2000008c   Data           4  buzzer.o(.data)
+    BuzzerOnTimeCount                        0x20000090   Data           4  buzzer.o(.data)
+    .data                                    0x20000094   Section        3  uart_packet.o(.data)
+    Pack_Index                               0x20000094   Data           1  uart_packet.o(.data)
+    Pack_CheckSum                            0x20000095   Data           1  uart_packet.o(.data)
+    Pack_DataLen                             0x20000096   Data           1  uart_packet.o(.data)
+    .data                                    0x20000098   Section       12  a31g12x_hal_uartn.o(.data)
+    UARTn_BaseClock                          0x20000098   Data           4  a31g12x_hal_uartn.o(.data)
+    .data                                    0x200000a4   Section        4  a31g12x_hal_usart1n.o(.data)
+    .data                                    0x200000a8   Section       28  system_a31g12x.o(.data)
+    .bss                                     0x200000c4   Section      160  sw_timer.o(.bss)
+    SW_Timer_Info                            0x200000c4   Data         160  sw_timer.o(.bss)
+    .bss                                     0x20000164   Section      340  uart1.o(.bss)
+    Tx_Buffer                                0x20000164   Data         200  uart1.o(.bss)
+    Rx_Buffer                                0x2000022c   Data         100  uart1.o(.bss)
+    RingBuffer_Tx                            0x20000290   Data          20  uart1.o(.bss)
+    RingBuffer_Rx                            0x200002a4   Data          20  uart1.o(.bss)
+    .bss                                     0x200002b8   Section       32  driver_ds3231_basic.o(.bss)
+    gs_handle                                0x200002b8   Data          32  driver_ds3231_basic.o(.bss)
+    .bss                                     0x200002d8   Section       32  segment.o(.bss)
+    .bss                                     0x200002f8   Section      100  uart_packet.o(.bss)
+    Pack_Buff                                0x200002f8   Data         100  uart_packet.o(.bss)
+    STACK                                    0x20000360   Section     1280  startup_a31g12x.o(STACK)
+
+    Global Symbols
+
+    Symbol Name                              Value     Ov Type        Size  Object(Section)
+
+    BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000   Number         0  anon$$obj.o ABSOLUTE
+    __ARM_use_no_argv                        0x00000000   Number         0  main.o ABSOLUTE
+    __Vectors                                0x00000000   Data           4  startup_a31g12x.o(RESET)
+    _printf_a                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_c                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_charcount                        0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_d                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_e                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_f                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_flags                            0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_fp_dec                           0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_fp_hex                           0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_g                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_i                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_int_dec                          0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_l                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_lc                               0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_ll                               0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_lld                              0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_lli                              0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_llo                              0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_llu                              0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_llx                              0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_longlong_dec                     0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_longlong_hex                     0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_longlong_oct                     0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_ls                               0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_mbtowc                           0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_n                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_o                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_p                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_percent                          0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_pre_padding                      0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_return_value                     0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_s                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_sizespec                         0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_str                              0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_truncate_signed                  0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_truncate_unsigned                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_u                                0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_wc                               0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_wctomb                           0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_widthprec                        0x00000000   Number         0  stubs.o ABSOLUTE
+    _printf_x                                0x00000000   Number         0  stubs.o ABSOLUTE
+    __arm_fini_                               - Undefined Weak Reference
+    __cpp_initialize__aeabi_                  - Undefined Weak Reference
+    __cxa_finalize                            - Undefined Weak Reference
+    __decompress                              - Undefined Weak Reference
+    _clock_init                               - Undefined Weak Reference
+    _microlib_exit                            - Undefined Weak Reference
+    __Vectors_End                            0x000000b0   Data           0  startup_a31g12x.o(RESET)
+    __Vectors_Size                           0x000000b0   Number         0  startup_a31g12x.o ABSOLUTE
+    __main                                   0x000000b1   Thumb Code     0  entry.o(.ARM.Collect$$$$00000000)
+    _main_stk                                0x000000b1   Thumb Code     0  entry2.o(.ARM.Collect$$$$00000001)
+    _main_scatterload                        0x000000b5   Thumb Code     0  entry5.o(.ARM.Collect$$$$00000004)
+    __main_after_scatterload                 0x000000b9   Thumb Code     0  entry5.o(.ARM.Collect$$$$00000004)
+    _main_clock                              0x000000b9   Thumb Code     0  entry7b.o(.ARM.Collect$$$$00000008)
+    _main_cpp_init                           0x000000b9   Thumb Code     0  entry8b.o(.ARM.Collect$$$$0000000A)
+    _main_init                               0x000000b9   Thumb Code     0  entry9a.o(.ARM.Collect$$$$0000000B)
+    __rt_lib_shutdown_fini                   0x000000c1   Thumb Code     0  entry12b.o(.ARM.Collect$$$$0000000E)
+    __rt_final_cpp                           0x000000c5   Thumb Code     0  entry10a.o(.ARM.Collect$$$$0000000F)
+    __rt_final_exit                          0x000000c5   Thumb Code     0  entry11a.o(.ARM.Collect$$$$00000011)
+    Reset_Handler                            0x000000c9   Thumb Code     8  startup_a31g12x.o(.text)
+    ADC_Handler                              0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    EINT0_Handler                            0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    EINT1_Handler                            0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    EINT2_Handler                            0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    EINT3_Handler                            0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    I2C0_Handler                             0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    I2C1_Handler                             0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    I2C2_Handler                             0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    LVI_Handler                              0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER10_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER11_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER13_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER14_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER15_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER16_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER20_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER21_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    TIMER30_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    UART0_Handler                            0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    USART10_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    USART11_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    USART12_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    USART13_Handler                          0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    WDT_Handler                              0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    WT_Handler                               0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    WUT_Handler                              0x000000db   Thumb Code     0  startup_a31g12x.o(.text)
+    __aeabi_uidiv                            0x000000e5   Thumb Code     0  uidiv.o(.text)
+    __aeabi_uidivmod                         0x000000e5   Thumb Code    44  uidiv.o(.text)
+    __aeabi_idiv                             0x00000111   Thumb Code     0  idiv.o(.text)
+    __aeabi_idivmod                          0x00000111   Thumb Code    40  idiv.o(.text)
+    __aeabi_memcpy                           0x00000139   Thumb Code    36  memcpya.o(.text)
+    __aeabi_memcpy4                          0x00000139   Thumb Code     0  memcpya.o(.text)
+    __aeabi_memcpy8                          0x00000139   Thumb Code     0  memcpya.o(.text)
+    __aeabi_memset                           0x0000015d   Thumb Code    14  memseta.o(.text)
+    __aeabi_memset4                          0x0000015d   Thumb Code     0  memseta.o(.text)
+    __aeabi_memset8                          0x0000015d   Thumb Code     0  memseta.o(.text)
+    __aeabi_memclr                           0x0000016b   Thumb Code     4  memseta.o(.text)
+    __aeabi_memclr4                          0x0000016b   Thumb Code     0  memseta.o(.text)
+    __aeabi_memclr8                          0x0000016b   Thumb Code     0  memseta.o(.text)
+    _memset$wrapper                          0x0000016f   Thumb Code    18  memseta.o(.text)
+    __aeabi_fdiv                             0x00000181   Thumb Code   124  fdiv.o(.text)
+    __aeabi_f2iz                             0x000001fd   Thumb Code    50  ffixi.o(.text)
+    __I$use$fp                               0x0000022f   Thumb Code     0  iusefp.o(.text)
+    _float_round                             0x0000022f   Thumb Code    16  fepilogue.o(.text)
+    _float_epilogue                          0x0000023f   Thumb Code   114  fepilogue.o(.text)
+    __scatterload                            0x000002b1   Thumb Code    28  init.o(.text)
+    __scatterload_rt2                        0x000002b1   Thumb Code     0  init.o(.text)
+    Action_Initialization                    0x000002d5   Thumb Code    14  action_process.o(i.Action_Initialization)
+    Buzzer_Initialization                    0x000002ed   Thumb Code    34  buzzer.o(i.Buzzer_Initialization)
+    Buzzer_On                                0x00000319   Thumb Code    24  buzzer.o(i.Buzzer_On)
+    Delay_I2C_Delay                          0x0000038d   Thumb Code    14  gpio_i2c.o(i.Delay_I2C_Delay)
+    Delay_ms                                 0x0000039d   Thumb Code    16  systick_timer.o(i.Delay_ms)
+    FlashMEM_Clock_Initialization            0x000003b1   Thumb Code    16  eeprom.o(i.FlashMEM_Clock_Initialization)
+    GPIO_I2C0_Initialization                 0x000003c1   Thumb Code    60  gpio_i2c.o(i.GPIO_I2C0_Initialization)
+    GPIO_I2C1_Initialization                 0x00000401   Thumb Code    60  gpio_i2c.o(i.GPIO_I2C1_Initialization)
+    GPIO_I2C2_Initialization                 0x00000441   Thumb Code    60  gpio_i2c.o(i.GPIO_I2C2_Initialization)
+    GPIO_I2C2_Read                           0x00000481   Thumb Code   142  gpio_i2c.o(i.GPIO_I2C2_Read)
+    GPIO_I2C2_Start                          0x00000515   Thumb Code    70  gpio_i2c.o(i.GPIO_I2C2_Start)
+    GPIO_I2C2_Stop                           0x00000561   Thumb Code    58  gpio_i2c.o(i.GPIO_I2C2_Stop)
+    GPIO_I2C2_Write                          0x000005a1   Thumb Code   142  gpio_i2c.o(i.GPIO_I2C2_Write)
+    Gpio_Sensor_PWR_Initialization           0x00000635   Thumb Code    32  gpio_sensor.o(i.Gpio_Sensor_PWR_Initialization)
+    Gpio_StateLed_Initialization             0x00000659   Thumb Code    40  gpio_state_led.o(i.Gpio_StateLed_Initialization)
+    Gpio_StateLed_Set_Mode                   0x00000689   Thumb Code    36  gpio_state_led.o(i.Gpio_StateLed_Set_Mode)
+    Gpio_Switch_Port_Initialization          0x000007fd   Thumb Code    46  gpio_switch.o(i.Gpio_Switch_Port_Initialization)
+    HAL_CRC_Init                             0x00000835   Thumb Code    14  a31g12x_hal_crc.o(i.HAL_CRC_Init)
+    HAL_GPIO_ClearPin                        0x00000843   Thumb Code     4  a31g12x_hal_pcu.o(i.HAL_GPIO_ClearPin)
+    HAL_GPIO_ConfigFunction                  0x00000847   Thumb Code    68  a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigFunction)
+    HAL_GPIO_ConfigOutput                    0x0000088b   Thumb Code    70  a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigOutput)
+    HAL_GPIO_ConfigPullup                    0x000008d1   Thumb Code    30  a31g12x_hal_pcu.o(i.HAL_GPIO_ConfigPullup)
+    HAL_GPIO_ReadPin                         0x000008ef   Thumb Code     8  a31g12x_hal_pcu.o(i.HAL_GPIO_ReadPin)
+    HAL_GPIO_SetDebouncePin                  0x000008f7   Thumb Code    22  a31g12x_hal_pcu.o(i.HAL_GPIO_SetDebouncePin)
+    HAL_GPIO_SetPin                          0x0000090d   Thumb Code     4  a31g12x_hal_pcu.o(i.HAL_GPIO_SetPin)
+    HAL_INT_EInt_MaskDisable                 0x00000911   Thumb Code    12  a31g12x_hal_intc.o(i.HAL_INT_EInt_MaskDisable)
+    HAL_SCU_ClockMonitoring                  0x00000921   Thumb Code    50  a31g12x_hal_scu.o(i.HAL_SCU_ClockMonitoring)
+    HAL_SCU_ClockSource_Enable               0x0000095d   Thumb Code    22  a31g12x_hal_scu.o(i.HAL_SCU_ClockSource_Enable)
+    HAL_SCU_Peripheral_ClockConfig           0x00000981   Thumb Code     8  a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_ClockConfig)
+    HAL_SCU_Peripheral_EnableClock1          0x0000098d   Thumb Code    28  a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock1)
+    HAL_SCU_Peripheral_EnableClock2          0x000009ad   Thumb Code    28  a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_EnableClock2)
+    HAL_SCU_Peripheral_SetReset2             0x000009cd   Thumb Code    24  a31g12x_hal_scu.o(i.HAL_SCU_Peripheral_SetReset2)
+    HAL_SCU_SystemClockChange                0x000009e9   Thumb Code    10  a31g12x_hal_scu.o(i.HAL_SCU_SystemClockChange)
+    HAL_SCU_SystemClockDivider               0x000009fd   Thumb Code     8  a31g12x_hal_scu.o(i.HAL_SCU_SystemClockDivider)
+    HAL_TIMER1n_Cmd                          0x00000a09   Thumb Code    38  a31g12x_hal_timer1n.o(i.HAL_TIMER1n_Cmd)
+    HAL_TIMER1n_ConfigInterrupt              0x00000a2f   Thumb Code    56  a31g12x_hal_timer1n.o(i.HAL_TIMER1n_ConfigInterrupt)
+    HAL_TIMER1n_Init                         0x00000a69   Thumb Code   332  a31g12x_hal_timer1n.o(i.HAL_TIMER1n_Init)
+    HAL_UART_ConfigInterrupt                 0x00000bd1   Thumb Code    76  a31g12x_hal_uartn.o(i.HAL_UART_ConfigInterrupt)
+    HAL_UART_ConfigStructInit                0x00000c1d   Thumb Code    30  a31g12x_hal_uartn.o(i.HAL_UART_ConfigStructInit)
+    HAL_UART_Init                            0x00000c3d   Thumb Code   244  a31g12x_hal_uartn.o(i.HAL_UART_Init)
+    HAL_UART_Receive                         0x00000d41   Thumb Code   110  a31g12x_hal_uartn.o(i.HAL_UART_Receive)
+    HAL_UART_ReceiveByte                     0x00000db5   Thumb Code     8  a31g12x_hal_uartn.o(i.HAL_UART_ReceiveByte)
+    HAL_UART_Transmit                        0x00000dbd   Thumb Code   122  a31g12x_hal_uartn.o(i.HAL_UART_Transmit)
+    HAL_UART_TransmitByte                    0x00000e3d   Thumb Code    16  a31g12x_hal_uartn.o(i.HAL_UART_TransmitByte)
+    HAL_USART_ClearStatus                    0x00000e4d   Thumb Code    58  a31g12x_hal_usart1n.o(i.HAL_USART_ClearStatus)
+    HAL_USART_DataControlConfig              0x00000e87   Thumb Code   106  a31g12x_hal_usart1n.o(i.HAL_USART_DataControlConfig)
+    HAL_USART_Enable                         0x00000ef1   Thumb Code    38  a31g12x_hal_usart1n.o(i.HAL_USART_Enable)
+    HAL_USART_Init                           0x00000f19   Thumb Code   218  a31g12x_hal_usart1n.o(i.HAL_USART_Init)
+    HAL_USART_ReceiveByte                    0x0000100d   Thumb Code     8  a31g12x_hal_usart1n.o(i.HAL_USART_ReceiveByte)
+    HAL_USART_SPI_Mode_Config                0x00001015   Thumb Code    40  a31g12x_hal_usart1n.o(i.HAL_USART_SPI_Mode_Config)
+    HardFault_Handler                        0x0000103d   Thumb Code     4  a31g12x_interrupt.o(i.HardFault_Handler)
+    I2C2_Read                                0x00001041   Thumb Code    60  gpio_i2c.o(i.I2C2_Read)
+    I2C2_Write                               0x0000107d   Thumb Code    46  gpio_i2c.o(i.I2C2_Write)
+    NMI_Handler                              0x000010ab   Thumb Code     2  a31g12x_interrupt.o(i.NMI_Handler)
+    PendSV_Handler                           0x00001215   Thumb Code     2  a31g12x_interrupt.o(i.PendSV_Handler)
+    RTC_Process_Initialization               0x00001271   Thumb Code    20  rtc_process.o(i.RTC_Process_Initialization)
+    RingBuffer_Dequeue                       0x00001289   Thumb Code    62  ring_buffer.o(i.RingBuffer_Dequeue)
+    RingBuffer_Enqueue                       0x000012c7   Thumb Code    64  ring_buffer.o(i.RingBuffer_Enqueue)
+    RingBuffer_GetData                       0x00001307   Thumb Code    14  ring_buffer.o(i.RingBuffer_GetData)
+    RingBuffer_Get_DataSize                  0x00001315   Thumb Code    50  ring_buffer.o(i.RingBuffer_Get_DataSize)
+    RingBuffer_Initialization                0x00001347   Thumb Code    38  ring_buffer.o(i.RingBuffer_Initialization)
+    RingBuffer_PopData                       0x0000136d   Thumb Code    38  ring_buffer.o(i.RingBuffer_PopData)
+    RingBuffer_isEmpty                       0x00001393   Thumb Code    18  ring_buffer.o(i.RingBuffer_isEmpty)
+    RingBuffer_isFull                        0x000013a5   Thumb Code    36  ring_buffer.o(i.RingBuffer_isFull)
+    SPI10_Initialization                     0x000013c9   Thumb Code   234  spi10.o(i.SPI10_Initialization)
+    SVC_Handler                              0x000014bd   Thumb Code     2  a31g12x_interrupt.o(i.SVC_Handler)
+    SW_Timer_Callback_Process                0x000014c1   Thumb Code   124  sw_timer.o(i.SW_Timer_Callback_Process)
+    SW_Timer_Callback_Register               0x00001541   Thumb Code    78  sw_timer.o(i.SW_Timer_Callback_Register)
+    Segment_Initialization                   0x00001739   Thumb Code   114  segment_74hc595d.o(i.Segment_Initialization)
+    SysTick_Handler                          0x00001915   Thumb Code    30  systick_timer.o(i.SysTick_Handler)
+    SystemInit                               0x0000193d   Thumb Code    22  system_a31g12x.o(i.SystemInit)
+    System_Clock_Initialization              0x00001961   Thumb Code    66  a31g12x_systemclock.o(i.System_Clock_Initialization)
+    Systick_Initialization                   0x000019b1   Thumb Code    76  a31g12x_systemclock.o(i.Systick_Initialization)
+    TIMER12_Handler                          0x00001a09   Thumb Code    44  timer12.o(i.TIMER12_Handler)
+    Timer12_Initialization                   0x00001a3d   Thumb Code    84  timer12.o(i.Timer12_Initialization)
+    Timer12_Set_Match_Interrupt_Callback     0x00001a99   Thumb Code     6  timer12.o(i.Timer12_Set_Match_Interrupt_Callback)
+    UART1_Handler                            0x00001aa5   Thumb Code    34  uart1.o(i.UART1_Handler)
+    Uart1_Get_RecvData                       0x00001acd   Thumb Code    16  uart1.o(i.Uart1_Get_RecvData)
+    Uart1_Get_RecvDataCount                  0x00001ae1   Thumb Code    10  uart1.o(i.Uart1_Get_RecvDataCount)
+    Uart1_Initialization                     0x00001af1   Thumb Code   158  uart1.o(i.Uart1_Initialization)
+    Uart_Packet_Initialization               0x00001c1d   Thumb Code    20  uart_packet.o(i.Uart_Packet_Initialization)
+    __ARM_common_switch8                     0x00001e13   Thumb Code    28  segment_74hc595d.o(i.__ARM_common_switch8)
+    __scatterload_copy                       0x00001e2f   Thumb Code    14  handlers.o(i.__scatterload_copy)
+    __scatterload_null                       0x00001e3d   Thumb Code     2  handlers.o(i.__scatterload_null)
+    __scatterload_zeroinit                   0x00001e3f   Thumb Code    14  handlers.o(i.__scatterload_zeroinit)
+    ds3231_aging_offset_convert_to_register  0x00001ec5   Thumb Code    48  driver_ds3231.o(i.ds3231_aging_offset_convert_to_register)
+    ds3231_basic_get_time                    0x00001ef9   Thumb Code    24  driver_ds3231_basic.o(i.ds3231_basic_get_time)
+    ds3231_basic_init                        0x00001f15   Thumb Code   316  driver_ds3231_basic.o(i.ds3231_basic_init)
+    ds3231_basic_set_time                    0x000021a9   Thumb Code    24  driver_ds3231_basic.o(i.ds3231_basic_set_time)
+    ds3231_deinit                            0x000021c5   Thumb Code    48  driver_ds3231.o(i.ds3231_deinit)
+    ds3231_get_time                          0x00002211   Thumb Code   208  driver_ds3231.o(i.ds3231_get_time)
+    ds3231_init                              0x0000231d   Thumb Code   218  driver_ds3231.o(i.ds3231_init)
+    ds3231_interface_debug_print             0x00002509   Thumb Code     2  driver_ds3231_interface_template.o(i.ds3231_interface_debug_print)
+    ds3231_interface_delay_ms                0x0000250b   Thumb Code    12  driver_ds3231_interface_template.o(i.ds3231_interface_delay_ms)
+    ds3231_interface_iic_deinit              0x00002517   Thumb Code     4  driver_ds3231_interface_template.o(i.ds3231_interface_iic_deinit)
+    ds3231_interface_iic_init                0x0000251b   Thumb Code     4  driver_ds3231_interface_template.o(i.ds3231_interface_iic_init)
+    ds3231_interface_iic_read                0x0000251f   Thumb Code    34  driver_ds3231_interface_template.o(i.ds3231_interface_iic_read)
+    ds3231_interface_iic_write               0x00002541   Thumb Code    46  driver_ds3231_interface_template.o(i.ds3231_interface_iic_write)
+    ds3231_interface_receive_callback        0x00002571   Thumb Code    34  driver_ds3231_interface_template.o(i.ds3231_interface_receive_callback)
+    ds3231_set_32khz_output                  0x000025c5   Thumb Code   106  driver_ds3231.o(i.ds3231_set_32khz_output)
+    ds3231_set_aging_offset                  0x00002671   Thumb Code    54  driver_ds3231.o(i.ds3231_set_aging_offset)
+    ds3231_set_alarm_interrupt               0x000026c9   Thumb Code   112  driver_ds3231.o(i.ds3231_set_alarm_interrupt)
+    ds3231_set_oscillator                    0x00002779   Thumb Code   114  driver_ds3231.o(i.ds3231_set_oscillator)
+    ds3231_set_pin                           0x0000282d   Thumb Code   106  driver_ds3231.o(i.ds3231_set_pin)
+    ds3231_set_square_wave                   0x000028d9   Thumb Code   106  driver_ds3231.o(i.ds3231_set_square_wave)
+    ds3231_set_time                          0x00002985   Thumb Code   662  driver_ds3231.o(i.ds3231_set_time)
+    main                                     0x00002e99   Thumb Code   108  main.o(i.main)
+    millis                                   0x00002f0d   Thumb Code     6  systick_timer.o(i.millis)
+    timer_test                               0x00002f19   Thumb Code     2  main.o(i.timer_test)
+    Region$$Table$$Base                      0x00002f98   Number         0  anon$$obj.o(Region$$Table)
+    Region$$Table$$Limit                     0x00002fb8   Number         0  anon$$obj.o(Region$$Table)
+    nDelayCount                              0x20000004   Data           4  systick_timer.o(.data)
+    Segment_Toggle_In                        0x20000079   Data           1  segment_74hc595d.o(.data)
+    Segment_Toggle_Out                       0x2000007a   Data           1  segment_74hc595d.o(.data)
+    InFlag                                   0x2000009c   Data           4  a31g12x_hal_uartn.o(.data)
+    InCount                                  0x200000a0   Data           4  a31g12x_hal_uartn.o(.data)
+    USART1n_BaseClock                        0x200000a4   Data           4  a31g12x_hal_usart1n.o(.data)
+    mclk                                     0x200000a8   Data           4  system_a31g12x.o(.data)
+    SystemCoreClock                          0x200000ac   Data           4  system_a31g12x.o(.data)
+    SystemPeriClock                          0x200000b0   Data           4  system_a31g12x.o(.data)
+    ClkSrcTbl                                0x200000b4   Data          16  system_a31g12x.o(.data)
+    Segment_OutputBuff                       0x200002d8   Data          32  segment.o(.bss)
+    __initial_sp                             0x20000860   Data           0  startup_a31g12x.o(STACK)
+
+
+
+==============================================================================
+
+Memory Map of the image
+
+  Image Entry point : 0x000000b1
+
+  Load Region LR_IROM1 (Base: 0x00000000, Size: 0x0000307c, Max: 0x00010000, ABSOLUTE)
+
+    Execution Region ER_IROM1 (Exec base: 0x00000000, Load base: 0x00000000, Size: 0x00002fb8, Max: 0x00010000, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x00000000   0x00000000   0x000000b0   Data   RO         2940    RESET               startup_a31g12x.o
+    0x000000b0   0x000000b0   0x00000000   Code   RO         3654  * .ARM.Collect$$$$00000000  mc_p.l(entry.o)
+    0x000000b0   0x000000b0   0x00000004   Code   RO         3945    .ARM.Collect$$$$00000001  mc_p.l(entry2.o)
+    0x000000b4   0x000000b4   0x00000004   Code   RO         3948    .ARM.Collect$$$$00000004  mc_p.l(entry5.o)
+    0x000000b8   0x000000b8   0x00000000   Code   RO         3950    .ARM.Collect$$$$00000008  mc_p.l(entry7b.o)
+    0x000000b8   0x000000b8   0x00000000   Code   RO         3952    .ARM.Collect$$$$0000000A  mc_p.l(entry8b.o)
+    0x000000b8   0x000000b8   0x00000008   Code   RO         3953    .ARM.Collect$$$$0000000B  mc_p.l(entry9a.o)
+    0x000000c0   0x000000c0   0x00000004   Code   RO         3960    .ARM.Collect$$$$0000000E  mc_p.l(entry12b.o)
+    0x000000c4   0x000000c4   0x00000000   Code   RO         3955    .ARM.Collect$$$$0000000F  mc_p.l(entry10a.o)
+    0x000000c4   0x000000c4   0x00000000   Code   RO         3957    .ARM.Collect$$$$00000011  mc_p.l(entry11a.o)
+    0x000000c4   0x000000c4   0x00000004   Code   RO         3946    .ARM.Collect$$$$00002712  mc_p.l(entry2.o)
+    0x000000c8   0x000000c8   0x0000001c   Code   RO         2941    .text               startup_a31g12x.o
+    0x000000e4   0x000000e4   0x0000002c   Code   RO         3657    .text               mc_p.l(uidiv.o)
+    0x00000110   0x00000110   0x00000028   Code   RO         3659    .text               mc_p.l(idiv.o)
+    0x00000138   0x00000138   0x00000024   Code   RO         3668    .text               mc_p.l(memcpya.o)
+    0x0000015c   0x0000015c   0x00000024   Code   RO         3670    .text               mc_p.l(memseta.o)
+    0x00000180   0x00000180   0x0000007c   Code   RO         3939    .text               mf_p.l(fdiv.o)
+    0x000001fc   0x000001fc   0x00000032   Code   RO         3943    .text               mf_p.l(ffixi.o)
+    0x0000022e   0x0000022e   0x00000000   Code   RO         3970    .text               mc_p.l(iusefp.o)
+    0x0000022e   0x0000022e   0x00000082   Code   RO         3971    .text               mf_p.l(fepilogue.o)
+    0x000002b0   0x000002b0   0x00000024   Code   RO         3983    .text               mc_p.l(init.o)
+    0x000002d4   0x000002d4   0x00000014   Code   RO         1276    i.Action_Initialization  action_process.o
+    0x000002e8   0x000002e8   0x00000002   Code   RO         1277    i.Action_Process    action_process.o
+    0x000002ea   0x000002ea   0x00000002   PAD
+    0x000002ec   0x000002ec   0x0000002c   Code   RO         1352    i.Buzzer_Initialization  buzzer.o
+    0x00000318   0x00000318   0x00000024   Code   RO         1353    i.Buzzer_On         buzzer.o
+    0x0000033c   0x0000033c   0x00000050   Code   RO         1354    i.Buzzer_Output_Process  buzzer.o
+    0x0000038c   0x0000038c   0x0000000e   Code   RO          673    i.Delay_I2C_Delay   gpio_i2c.o
+    0x0000039a   0x0000039a   0x00000002   PAD
+    0x0000039c   0x0000039c   0x00000014   Code   RO          341    i.Delay_ms          systick_timer.o
+    0x000003b0   0x000003b0   0x00000010   Code   RO         1308    i.FlashMEM_Clock_Initialization  eeprom.o
+    0x000003c0   0x000003c0   0x00000040   Code   RO          674    i.GPIO_I2C0_Initialization  gpio_i2c.o
+    0x00000400   0x00000400   0x00000040   Code   RO          679    i.GPIO_I2C1_Initialization  gpio_i2c.o
+    0x00000440   0x00000440   0x00000040   Code   RO          684    i.GPIO_I2C2_Initialization  gpio_i2c.o
+    0x00000480   0x00000480   0x00000094   Code   RO          685    i.GPIO_I2C2_Read    gpio_i2c.o
+    0x00000514   0x00000514   0x0000004c   Code   RO          686    i.GPIO_I2C2_Start   gpio_i2c.o
+    0x00000560   0x00000560   0x00000040   Code   RO          687    i.GPIO_I2C2_Stop    gpio_i2c.o
+    0x000005a0   0x000005a0   0x00000094   Code   RO          688    i.GPIO_I2C2_Write   gpio_i2c.o
+    0x00000634   0x00000634   0x00000024   Code   RO         1385    i.Gpio_Sensor_PWR_Initialization  gpio_sensor.o
+    0x00000658   0x00000658   0x00000030   Code   RO          448    i.Gpio_StateLed_Initialization  gpio_state_led.o
+    0x00000688   0x00000688   0x00000034   Code   RO          449    i.Gpio_StateLed_Set_Mode  gpio_state_led.o
+    0x000006bc   0x000006bc   0x00000140   Code   RO          486    i.Gpio_Switch_Check_Process  gpio_switch.o
+    0x000007fc   0x000007fc   0x00000038   Code   RO          487    i.Gpio_Switch_Port_Initialization  gpio_switch.o
+    0x00000834   0x00000834   0x0000000e   Code   RO         1635    i.HAL_CRC_Init      a31g12x_hal_crc.o
+    0x00000842   0x00000842   0x00000004   Code   RO         2094    i.HAL_GPIO_ClearPin  a31g12x_hal_pcu.o
+    0x00000846   0x00000846   0x00000044   Code   RO         2095    i.HAL_GPIO_ConfigFunction  a31g12x_hal_pcu.o
+    0x0000088a   0x0000088a   0x00000046   Code   RO         2097    i.HAL_GPIO_ConfigOutput  a31g12x_hal_pcu.o
+    0x000008d0   0x000008d0   0x0000001e   Code   RO         2098    i.HAL_GPIO_ConfigPullup  a31g12x_hal_pcu.o
+    0x000008ee   0x000008ee   0x00000008   Code   RO         2100    i.HAL_GPIO_ReadPin  a31g12x_hal_pcu.o
+    0x000008f6   0x000008f6   0x00000016   Code   RO         2101    i.HAL_GPIO_SetDebouncePin  a31g12x_hal_pcu.o
+    0x0000090c   0x0000090c   0x00000004   Code   RO         2102    i.HAL_GPIO_SetPin   a31g12x_hal_pcu.o
+    0x00000910   0x00000910   0x00000010   Code   RO         1990    i.HAL_INT_EInt_MaskDisable  a31g12x_hal_intc.o
+    0x00000920   0x00000920   0x0000003c   Code   RO         2201    i.HAL_SCU_ClockMonitoring  a31g12x_hal_scu.o
+    0x0000095c   0x0000095c   0x00000024   Code   RO         2206    i.HAL_SCU_ClockSource_Enable  a31g12x_hal_scu.o
+    0x00000980   0x00000980   0x0000000c   Code   RO         2209    i.HAL_SCU_Peripheral_ClockConfig  a31g12x_hal_scu.o
+    0x0000098c   0x0000098c   0x00000020   Code   RO         2211    i.HAL_SCU_Peripheral_EnableClock1  a31g12x_hal_scu.o
+    0x000009ac   0x000009ac   0x00000020   Code   RO         2212    i.HAL_SCU_Peripheral_EnableClock2  a31g12x_hal_scu.o
+    0x000009cc   0x000009cc   0x0000001c   Code   RO         2215    i.HAL_SCU_Peripheral_SetReset2  a31g12x_hal_scu.o
+    0x000009e8   0x000009e8   0x00000014   Code   RO         2221    i.HAL_SCU_SystemClockChange  a31g12x_hal_scu.o
+    0x000009fc   0x000009fc   0x0000000c   Code   RO         2222    i.HAL_SCU_SystemClockDivider  a31g12x_hal_scu.o
+    0x00000a08   0x00000a08   0x00000026   Code   RO         2378    i.HAL_TIMER1n_Cmd   a31g12x_hal_timer1n.o
+    0x00000a2e   0x00000a2e   0x00000038   Code   RO         2379    i.HAL_TIMER1n_ConfigInterrupt  a31g12x_hal_timer1n.o
+    0x00000a66   0x00000a66   0x00000002   PAD
+    0x00000a68   0x00000a68   0x00000168   Code   RO         2381    i.HAL_TIMER1n_Init  a31g12x_hal_timer1n.o
+    0x00000bd0   0x00000bd0   0x0000004c   Code   RO         2601    i.HAL_UART_ConfigInterrupt  a31g12x_hal_uartn.o
+    0x00000c1c   0x00000c1c   0x0000001e   Code   RO         2602    i.HAL_UART_ConfigStructInit  a31g12x_hal_uartn.o
+    0x00000c3a   0x00000c3a   0x00000002   PAD
+    0x00000c3c   0x00000c3c   0x00000104   Code   RO         2608    i.HAL_UART_Init     a31g12x_hal_uartn.o
+    0x00000d40   0x00000d40   0x00000074   Code   RO         2609    i.HAL_UART_Receive  a31g12x_hal_uartn.o
+    0x00000db4   0x00000db4   0x00000008   Code   RO         2610    i.HAL_UART_ReceiveByte  a31g12x_hal_uartn.o
+    0x00000dbc   0x00000dbc   0x00000080   Code   RO         2611    i.HAL_UART_Transmit  a31g12x_hal_uartn.o
+    0x00000e3c   0x00000e3c   0x00000010   Code   RO         2612    i.HAL_UART_TransmitByte  a31g12x_hal_uartn.o
+    0x00000e4c   0x00000e4c   0x0000003a   Code   RO         2705    i.HAL_USART_ClearStatus  a31g12x_hal_usart1n.o
+    0x00000e86   0x00000e86   0x0000006a   Code   RO         2707    i.HAL_USART_DataControlConfig  a31g12x_hal_usart1n.o
+    0x00000ef0   0x00000ef0   0x00000026   Code   RO         2709    i.HAL_USART_Enable  a31g12x_hal_usart1n.o
+    0x00000f16   0x00000f16   0x00000002   PAD
+    0x00000f18   0x00000f18   0x000000f4   Code   RO         2711    i.HAL_USART_Init    a31g12x_hal_usart1n.o
+    0x0000100c   0x0000100c   0x00000008   Code   RO         2713    i.HAL_USART_ReceiveByte  a31g12x_hal_usart1n.o
+    0x00001014   0x00001014   0x00000028   Code   RO         2714    i.HAL_USART_SPI_Mode_Config  a31g12x_hal_usart1n.o
+    0x0000103c   0x0000103c   0x00000004   Code   RO            1    i.HardFault_Handler  a31g12x_interrupt.o
+    0x00001040   0x00001040   0x0000003c   Code   RO          693    i.I2C2_Read         gpio_i2c.o
+    0x0000107c   0x0000107c   0x0000002e   Code   RO          694    i.I2C2_Write        gpio_i2c.o
+    0x000010aa   0x000010aa   0x00000002   Code   RO            2    i.NMI_Handler       a31g12x_interrupt.o
+    0x000010ac   0x000010ac   0x00000078   Code   RO           38    i.NVIC_SetPriority  a31g12x_systemclock.o
+    0x00001124   0x00001124   0x00000078   Code   RO          525    i.NVIC_SetPriority  uart1.o
+    0x0000119c   0x0000119c   0x00000078   Code   RO          634    i.NVIC_SetPriority  timer12.o
+    0x00001214   0x00001214   0x00000002   Code   RO            3    i.PendSV_Handler    a31g12x_interrupt.o
+    0x00001216   0x00001216   0x00000002   PAD
+    0x00001218   0x00001218   0x00000058   Code   RO         1243    i.RTC_Get_IC_Time_Process  rtc_process.o
+    0x00001270   0x00001270   0x00000018   Code   RO         1245    i.RTC_Process_Initialization  rtc_process.o
+    0x00001288   0x00001288   0x0000003e   Code   RO          377    i.RingBuffer_Dequeue  ring_buffer.o
+    0x000012c6   0x000012c6   0x00000040   Code   RO          378    i.RingBuffer_Enqueue  ring_buffer.o
+    0x00001306   0x00001306   0x0000000e   Code   RO          379    i.RingBuffer_GetData  ring_buffer.o
+    0x00001314   0x00001314   0x00000032   Code   RO          380    i.RingBuffer_Get_DataSize  ring_buffer.o
+    0x00001346   0x00001346   0x00000026   Code   RO          381    i.RingBuffer_Initialization  ring_buffer.o
+    0x0000136c   0x0000136c   0x00000026   Code   RO          382    i.RingBuffer_PopData  ring_buffer.o
+    0x00001392   0x00001392   0x00000012   Code   RO          383    i.RingBuffer_isEmpty  ring_buffer.o
+    0x000013a4   0x000013a4   0x00000024   Code   RO          384    i.RingBuffer_isFull  ring_buffer.o
+    0x000013c8   0x000013c8   0x000000f4   Code   RO          819    i.SPI10_Initialization  spi10.o
+    0x000014bc   0x000014bc   0x00000002   Code   RO            4    i.SVC_Handler       a31g12x_interrupt.o
+    0x000014be   0x000014be   0x00000002   PAD
+    0x000014c0   0x000014c0   0x00000080   Code   RO          307    i.SW_Timer_Callback_Process  sw_timer.o
+    0x00001540   0x00001540   0x00000054   Code   RO          308    i.SW_Timer_Callback_Register  sw_timer.o
+    0x00001594   0x00001594   0x000001a4   Code   RO          595    i.Segemet_Output_Process  segment_74hc595d.o
+    0x00001738   0x00001738   0x00000084   Code   RO          596    i.Segment_Initialization  segment_74hc595d.o
+    0x000017bc   0x000017bc   0x000000c8   Code   RO          597    i.Segment_Output_Data  segment_74hc595d.o
+    0x00001884   0x00001884   0x00000090   Code   RO          450    i.State_Led_Output_Process  gpio_state_led.o
+    0x00001914   0x00001914   0x00000028   Code   RO          342    i.SysTick_Handler   systick_timer.o
+    0x0000193c   0x0000193c   0x00000024   Code   RO         2948    i.SystemInit        system_a31g12x.o
+    0x00001960   0x00001960   0x00000050   Code   RO           39    i.System_Clock_Initialization  a31g12x_systemclock.o
+    0x000019b0   0x000019b0   0x00000058   Code   RO           40    i.Systick_Initialization  a31g12x_systemclock.o
+    0x00001a08   0x00001a08   0x00000034   Code   RO          635    i.TIMER12_Handler   timer12.o
+    0x00001a3c   0x00001a3c   0x0000005c   Code   RO          636    i.Timer12_Initialization  timer12.o
+    0x00001a98   0x00001a98   0x0000000c   Code   RO          637    i.Timer12_Set_Match_Interrupt_Callback  timer12.o
+    0x00001aa4   0x00001aa4   0x00000028   Code   RO          526    i.UART1_Handler     uart1.o
+    0x00001acc   0x00001acc   0x00000014   Code   RO          527    i.Uart1_Get_RecvData  uart1.o
+    0x00001ae0   0x00001ae0   0x00000010   Code   RO          528    i.Uart1_Get_RecvDataCount  uart1.o
+    0x00001af0   0x00001af0   0x000000c0   Code   RO          529    i.Uart1_Initialization  uart1.o
+    0x00001bb0   0x00001bb0   0x00000034   Code   RO          530    i.Uart1_Receive_Handler  uart1.o
+    0x00001be4   0x00001be4   0x00000038   Code   RO          533    i.Uart1_Transmit_Process  uart1.o
+    0x00001c1c   0x00001c1c   0x0000001c   Code   RO         1528    i.Uart_Packet_Initialization  uart_packet.o
+    0x00001c38   0x00001c38   0x00000144   Code   RO         1529    i.Uart_Packet_Make_Process  uart_packet.o
+    0x00001d7c   0x00001d7c   0x00000096   Code   RO         1530    i.Uart_Packet_Process  uart_packet.o
+    0x00001e12   0x00001e12   0x0000001c   Code   RO          624    i.__ARM_common_switch8  segment_74hc595d.o
+    0x00001e2e   0x00001e2e   0x0000000e   Code   RO         3997    i.__scatterload_copy  mc_p.l(handlers.o)
+    0x00001e3c   0x00001e3c   0x00000002   Code   RO         3998    i.__scatterload_null  mc_p.l(handlers.o)
+    0x00001e3e   0x00001e3e   0x0000000e   Code   RO         3999    i.__scatterload_zeroinit  mc_p.l(handlers.o)
+    0x00001e4c   0x00001e4c   0x00000014   Code   RO          908    i.a_ds3231_bcd2hex  driver_ds3231.o
+    0x00001e60   0x00001e60   0x00000022   Code   RO          909    i.a_ds3231_hex2bcd  driver_ds3231.o
+    0x00001e82   0x00001e82   0x00000024   Code   RO          910    i.a_ds3231_iic_multiple_read  driver_ds3231.o
+    0x00001ea6   0x00001ea6   0x0000001e   Code   RO          911    i.a_ds3231_iic_write  driver_ds3231.o
+    0x00001ec4   0x00001ec4   0x00000034   Code   RO          913    i.ds3231_aging_offset_convert_to_register  driver_ds3231.o
+    0x00001ef8   0x00001ef8   0x0000001c   Code   RO         1115    i.ds3231_basic_get_time  driver_ds3231_basic.o
+    0x00001f14   0x00001f14   0x00000294   Code   RO         1118    i.ds3231_basic_init  driver_ds3231_basic.o
+    0x000021a8   0x000021a8   0x0000001c   Code   RO         1119    i.ds3231_basic_set_time  driver_ds3231_basic.o
+    0x000021c4   0x000021c4   0x0000004c   Code   RO          915    i.ds3231_deinit     driver_ds3231.o
+    0x00002210   0x00002210   0x0000010c   Code   RO          927    i.ds3231_get_time   driver_ds3231.o
+    0x0000231c   0x0000231c   0x000001ec   Code   RO          929    i.ds3231_init       driver_ds3231.o
+    0x00002508   0x00002508   0x00000002   Code   RO         1187    i.ds3231_interface_debug_print  driver_ds3231_interface_template.o
+    0x0000250a   0x0000250a   0x0000000c   Code   RO         1188    i.ds3231_interface_delay_ms  driver_ds3231_interface_template.o
+    0x00002516   0x00002516   0x00000004   Code   RO         1189    i.ds3231_interface_iic_deinit  driver_ds3231_interface_template.o
+    0x0000251a   0x0000251a   0x00000004   Code   RO         1190    i.ds3231_interface_iic_init  driver_ds3231_interface_template.o
+    0x0000251e   0x0000251e   0x00000022   Code   RO         1191    i.ds3231_interface_iic_read  driver_ds3231_interface_template.o
+    0x00002540   0x00002540   0x0000002e   Code   RO         1192    i.ds3231_interface_iic_write  driver_ds3231_interface_template.o
+    0x0000256e   0x0000256e   0x00000002   PAD
+    0x00002570   0x00002570   0x00000054   Code   RO         1193    i.ds3231_interface_receive_callback  driver_ds3231_interface_template.o
+    0x000025c4   0x000025c4   0x000000ac   Code   RO          931    i.ds3231_set_32khz_output  driver_ds3231.o
+    0x00002670   0x00002670   0x00000058   Code   RO          932    i.ds3231_set_aging_offset  driver_ds3231.o
+    0x000026c8   0x000026c8   0x000000b0   Code   RO          935    i.ds3231_set_alarm_interrupt  driver_ds3231.o
+    0x00002778   0x00002778   0x000000b4   Code   RO          936    i.ds3231_set_oscillator  driver_ds3231.o
+    0x0000282c   0x0000282c   0x000000ac   Code   RO          937    i.ds3231_set_pin    driver_ds3231.o
+    0x000028d8   0x000028d8   0x000000ac   Code   RO          939    i.ds3231_set_square_wave  driver_ds3231.o
+    0x00002984   0x00002984   0x00000514   Code   RO          940    i.ds3231_set_time   driver_ds3231.o
+    0x00002e98   0x00002e98   0x00000074   Code   RO          187    i.main              main.o
+    0x00002f0c   0x00002f0c   0x0000000c   Code   RO          343    i.millis            systick_timer.o
+    0x00002f18   0x00002f18   0x00000002   Code   RO          188    i.timer_test        main.o
+    0x00002f1a   0x00002f1a   0x00000002   PAD
+    0x00002f1c   0x00002f1c   0x0000003c   Code   RO         2613    i.uart_set_divisors  a31g12x_hal_uartn.o
+    0x00002f58   0x00002f58   0x00000040   Code   RO         2719    i.usart_set_divisors  a31g12x_hal_usart1n.o
+    0x00002f98   0x00002f98   0x00000020   Data   RO         3995    Region$$Table       anon$$obj.o
+
+
+    Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x00002fb8, Size: 0x00000860, Max: 0x00001800, ABSOLUTE)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x20000000   0x00002fb8   0x00000008   Data   RW          344    .data               systick_timer.o
+    0x20000008   0x00002fc0   0x00000040   Data   RW          451    .data               gpio_state_led.o
+    0x20000048   0x00003000   0x00000024   Data   RW          490    .data               gpio_switch.o
+    0x2000006c   0x00003024   0x00000010   Data   RW          599    .data               segment_74hc595d.o
+    0x2000007c   0x00003034   0x00000004   Data   RW          638    .data               timer12.o
+    0x20000080   0x00003038   0x00000008   Data   RW         1246    .data               rtc_process.o
+    0x20000088   0x00003040   0x0000000c   Data   RW         1355    .data               buzzer.o
+    0x20000094   0x0000304c   0x00000003   Data   RW         1532    .data               uart_packet.o
+    0x20000097   0x0000304f   0x00000001   PAD
+    0x20000098   0x00003050   0x0000000c   Data   RW         2615    .data               a31g12x_hal_uartn.o
+    0x200000a4   0x0000305c   0x00000004   Data   RW         2720    .data               a31g12x_hal_usart1n.o
+    0x200000a8   0x00003060   0x0000001c   Data   RW         2949    .data               system_a31g12x.o
+    0x200000c4        -       0x000000a0   Zero   RW          310    .bss                sw_timer.o
+    0x20000164        -       0x00000154   Zero   RW          534    .bss                uart1.o
+    0x200002b8        -       0x00000020   Zero   RW         1122    .bss                driver_ds3231_basic.o
+    0x200002d8        -       0x00000020   Zero   RW         1422    .bss                segment.o
+    0x200002f8        -       0x00000064   Zero   RW         1531    .bss                uart_packet.o
+    0x2000035c   0x0000307c   0x00000004   PAD
+    0x20000360        -       0x00000500   Zero   RW         2938    STACK               startup_a31g12x.o
+
+
+
+  Load Region LR$$.ARM.__AT_0x1FFFF200 (Base: 0x1ffff200, Size: 0x00000044, Max: 0x00000044, ABSOLUTE)
+
+    Execution Region ER$$.ARM.__AT_0x1FFFF200 (Exec base: 0x1ffff200, Load base: 0x1ffff200, Size: 0x00000044, Max: 0x00000044, ABSOLUTE, UNINIT)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x1ffff200   0x1ffff200   0x00000044   Code   RO         2983    .ARM.__AT_0x1FFFF200  option_a31g12x.o
+
+
+
+  Load Region LR$$.ARM.__AT_0x1FFFF400 (Base: 0x1ffff400, Size: 0x00000080, Max: 0x00000080, ABSOLUTE)
+
+    Execution Region ER$$.ARM.__AT_0x1FFFF400 (Exec base: 0x1ffff400, Load base: 0x1ffff400, Size: 0x00000080, Max: 0x00000080, ABSOLUTE, UNINIT)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x1ffff400   0x1ffff400   0x00000080   Code   RO         2984    .ARM.__AT_0x1FFFF400  option_a31g12x.o
+
+
+
+  Load Region LR$$.ARM.__AT_0x1FFFF600 (Base: 0x1ffff600, Size: 0x00000080, Max: 0x00000080, ABSOLUTE)
+
+    Execution Region ER$$.ARM.__AT_0x1FFFF600 (Exec base: 0x1ffff600, Load base: 0x1ffff600, Size: 0x00000080, Max: 0x00000080, ABSOLUTE, UNINIT)
+
+    Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x1ffff600   0x1ffff600   0x00000080   Code   RO         2985    .ARM.__AT_0x1FFFF600  option_a31g12x.o
+
+
+==============================================================================
+
+Image component sizes
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Object Name
+
+         0          0          0          0          0       2184   a31g12x_hal_adc.o
+        14          0          0          0          0        491   a31g12x_hal_crc.o
+        16          4          0          0          0        507   a31g12x_hal_intc.o
+       206          0          0          0          0       4837   a31g12x_hal_pcu.o
+       232         54          0          0          0       4444   a31g12x_hal_scu.o
+       454         28          0          0          0       3039   a31g12x_hal_timer1n.o
+       694         32          0         12          0       9205   a31g12x_hal_uartn.o
+       558         44          0          4          0       5550   a31g12x_hal_usart1n.o
+        10          0          0          0          0       3109   a31g12x_interrupt.o
+       288         36          0          0          0     424063   a31g12x_systemclock.o
+        22          6          0          0          0        828   action_process.o
+       160         38          0         12          0       1596   buzzer.o
+      3268       1366          0          0          0      11951   driver_ds3231.o
+       716        352          0          0         32       2636   driver_ds3231_basic.o
+       186         50          0          0          0       4702   driver_ds3231_interface_template.o
+        16          0          0          0          0        460   eeprom.o
+       748         36          0          0          0       5794   gpio_i2c.o
+        36          4          0          0          0        473   gpio_sensor.o
+       244         40          0         64          0       2148   gpio_state_led.o
+       376         16          0         36          0       1958   gpio_switch.o
+       118          8          0          0          0       8592   main.o
+       324        324          0          0          0        648   option_a31g12x.o
+       320          0          0          0          0       5599   ring_buffer.o
+       112          8          0          8          0       1105   rtc_process.o
+         0          0          0          0         32        689   segment.o
+       780         70          0         16          0       5065   segment_74hc595d.o
+       244         10          0          0          0        751   spi10.o
+        28          8        176          0       1280        628   startup_a31g12x.o
+       212         10          0          0        160       2057   sw_timer.o
+        36         14          0         28          0       1270   system_a31g12x.o
+        72         20          0          8          0       1920   systick_timer.o
+       276         32          0          4          0       2242   timer12.o
+       496         80          0          0        340      11182   uart1.o
+       502         24          0          3        100       2757   uart_packet.o
+
+    ----------------------------------------------------------------------
+     11782       2714        208        196       1948     534480   Object Totals
+         0          0         32          0          0          0   (incl. Generated)
+        18          0          0          1          4          0   (incl. Padding)
+
+    ----------------------------------------------------------------------
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Member Name
+
+         0          0          0          0          0          0   entry.o
+         0          0          0          0          0          0   entry10a.o
+         0          0          0          0          0          0   entry11a.o
+         4          0          0          0          0          0   entry12b.o
+         8          4          0          0          0          0   entry2.o
+         4          0          0          0          0          0   entry5.o
+         0          0          0          0          0          0   entry7b.o
+         0          0          0          0          0          0   entry8b.o
+         8          4          0          0          0          0   entry9a.o
+        30          0          0          0          0          0   handlers.o
+        40          0          0          0          0         72   idiv.o
+        36          8          0          0          0         68   init.o
+         0          0          0          0          0          0   iusefp.o
+        36          0          0          0          0         60   memcpya.o
+        36          0          0          0          0        100   memseta.o
+        44          0          0          0          0         72   uidiv.o
+       124          0          0          0          0         72   fdiv.o
+       130          0          0          0          0        144   fepilogue.o
+        50          0          0          0          0         60   ffixi.o
+
+    ----------------------------------------------------------------------
+       550         16          0          0          0        648   Library Totals
+         0          0          0          0          0          0   (incl. Padding)
+
+    ----------------------------------------------------------------------
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   Library Name
+
+       246         16          0          0          0        372   mc_p.l
+       304          0          0          0          0        276   mf_p.l
+
+    ----------------------------------------------------------------------
+       550         16          0          0          0        648   Library Totals
+
+    ----------------------------------------------------------------------
+
+==============================================================================
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
+
+     12332       2730        208        196       1948     529692   Grand Totals
+     12332       2730        208        196       1948     529692   ELF Image Totals
+     12332       2730        208        196          0          0   ROM Totals
+
+==============================================================================
+
+    Total RO  Size (Code + RO Data)                12540 (  12.25kB)
+    Total RW  Size (RW Data + ZI Data)              2144 (   2.09kB)
+    Total ROM Size (Code + RO Data + RW Data)      12736 (  12.44kB)
+
+==============================================================================
+
diff --git a/Project/Listings/option_a31g12x.lst b/Project/Listings/option_a31g12x.lst
new file mode 100644
index 0000000..cdd18d0
--- /dev/null
+++ b/Project/Listings/option_a31g12x.lst
@@ -0,0 +1,1299 @@
+
+
+
+ARM Macro Assembler    Page 1 
+
+
+    1 00000000         ;-------------------------------------------------------
+                       ------------------------
+    2 00000000         ; This file is used for configure option setting, Area 1
+                       /2/3.
+    3 00000000         ;-------------------------------------------------------
+                       ------------------------
+    4 00000000         ;// <<< Use Configuration Wizard in Context Menu >>>
+    5 00000000         ;/******************************************************
+                       ***********************/
+    6 00000000         ;/* This file is part of the uVision/ARM development too
+                       ls.                   */
+    7 00000000         ;/* Copyright (c) 2005-2008 Keil Software. All rights re
+                       served.               */
+    8 00000000         ;/* This software may only be used under the terms of a 
+                       valid, current,       */
+    9 00000000         ;/* end user licence from KEIL for a compatible version 
+                       of KEIL software      */
+   10 00000000         ;/* development tools. Nothing else gives you the right 
+                       to use this software. */
+   11 00000000         ;/******************************************************
+                       ***********************/
+   12 00000000         
+   13 00000000         
+   14 00000000         ;// <e> Configure Option Page 1
+   15 00000000 00000001 
+                       CONFIGURE_OPTION_1
+                               EQU              1
+   16 00000000         
+   17 00000000         ;// <h> Read Protection Configuration
+   18 00000000         ;//    <o.0..2> Read Protection
+   19 00000000         ;//       <3=> Level 0 <2=> Level 1 <0=> Level 2
+   20 00000000         ;// </h>
+   21 00000000 69C8A273 
+                       RPCNFIG EQU              0x69C8A273
+   22 00000000         
+   23 00000000         ;// <h> Extra User Data
+   24 00000000         ;//   <o0> Word 0 <0x0000-0xFFFF>
+   25 00000000         ;//   <o1> Word 1 <0x0000-0xFFFF>
+   26 00000000         ;// </h>
+   27 00000000 0000FFFF 
+                       EX0CNFIG
+                               EQU              0xFFFF
+   28 00000000 0000FFFF 
+                       EX1CNFIG
+                               EQU              0xFFFF
+   29 00000000 00000000 
+                       nEX0CNFIG
+                               EQU              EX0CNFIG:EOR:0xFFFF
+   30 00000000 00000000 
+                       nEX1CNFIG
+                               EQU              EX1CNFIG:EOR:0xFFFF
+   31 00000000         
+   32 00000000         ;// <h> Watch-Dog Timer Configuration
+   33 00000000         ;//    <o.4..15> WDTRC Enable Selection
+   34 00000000         ;//       <0x96D=> By S/W (CLKSRCR Register) <0x2A7=> En
+                       able but disable at deep sleep <0xFFF=> Always Enable
+   35 00000000         ;//    <o.2> Watch-Dog Timer Clock Selection
+   36 00000000         ;//       <0=> By S/W (PPCLKSR Register) <1=> WDTRC
+   37 00000000         ;//    <o.1> Watch-Dog Timer Reset Enable Selection
+
+
+
+ARM Macro Assembler    Page 2 
+
+
+   38 00000000         ;//       <0=> Enable WDT Reset <1=> By S/W (WDTCR Regis
+                       ter)
+   39 00000000         ;//    <o.0> Watch-Dog Timer Counter Enable Selection
+   40 00000000         ;//       <0=> Enable WDT Counter <1=> By S/W (WDTCR Reg
+                       ister)
+   41 00000000         ;// </h>
+   42 00000000 FFFF96DB 
+                       WDTCNFIG
+                               EQU              0xFFFF96DB
+   43 00000000         
+   44 00000000         ;// <h> Low Voltage Reset Configuration
+   45 00000000         ;//    <o.8..15> LVR Operation Control Selection
+   46 00000000         ;//       <0xAA=> By S/W (LVRCR Register) <0xFF=> Always
+                        Enable
+   47 00000000         ;//    <o.0..3> LVR Voltage Selection
+   48 00000000         ;//       <15=> 1.62V <11=> 2.00V <10=> 2.13V <9=> 2.28V
+                        <8=> 2.46V <7=> 2.67V <6=> 3.04V <5=> 3.20V <4=> 3.55V 
+                       <3=> 3.75V <2=> 3.99V <1=> 4.25V <0=> 4.55V
+   49 00000000         ;// </h>
+   50 00000000 FFFFAAFF 
+                       LVRCNFIG
+                               EQU              0xFFFFAAFF
+   51 00000000         
+   52 00000000         ;// <h> Configure Option Page Erase/Write Protection
+   53 00000000         ;//    <o.0> Option Page 1, 0x1FFFF200 to 0x1FFFF27F
+   54 00000000         ;//    <o.1> Option Page 2, 0x1FFFF400 to 0x1FFFF47F
+   55 00000000         ;//    <o.2> Option Page 3, 0x1FFFF600 to 0x1FFFF67F
+   56 00000000         ;// </h>
+   57 00000000 00000000 
+                       OPTIONPAGE
+                               EQU              0x00000000
+   58 00000000 FFFFFFFF 
+                       CNFIGWTP1
+                               EQU              ~OPTIONPAGE
+   59 00000000         
+   60 00000000         ;// <h> Flash Memory Erase/Write Protection
+   61 00000000         ;//    <o.0> Sector 0, 0x10000000 to 0x100007FF
+   62 00000000         ;//    <o.1> Sector 1, 0x10000800 to 0x10000FFF
+   63 00000000         ;//    <o.2> Sector 2, 0x10001000 to 0x100017FF
+   64 00000000         ;//    <o.3> Sector 3, 0x10001800 to 0x10001FFF
+   65 00000000         ;//    <o.4> Sector 4, 0x10002000 to 0x100027FF
+   66 00000000         ;//    <o.5> Sector 5, 0x10002800 to 0x10002FFF
+   67 00000000         ;//    <o.6> Sector 6, 0x10003000 to 0x100037FF
+   68 00000000         ;//    <o.7> Sector 7, 0x10003800 to 0x10003FFF
+   69 00000000         ;//    <o.8> Sector 8, 0x10004000 to 0x100047FF
+   70 00000000         ;//    <o.9> Sector 9, 0x10004800 to 0x10004FFF
+   71 00000000         ;//    <o.10> Sector 10, 0x10005000 to 0x100057FF
+   72 00000000         ;//    <o.11> Sector 11, 0x10005800 to 0x10005FFF
+   73 00000000         ;//    <o.12> Sector 12, 0x10006000 to 0x100067FF
+   74 00000000         ;//    <o.13> Sector 13, 0x10006800 to 0x10006FFF
+   75 00000000         ;//    <o.14> Sector 14, 0x10007000 to 0x100077FF
+   76 00000000         ;//    <o.15> Sector 15, 0x10007800 to 0x10007FFF
+   77 00000000         ;//    <o.16> Sector 16, 0x10008000 to 0x100087FF
+   78 00000000         ;//    <o.17> Sector 17, 0x10008800 to 0x10008FFF
+   79 00000000         ;//    <o.18> Sector 18, 0x10009000 to 0x100097FF
+   80 00000000         ;//    <o.19> Sector 19, 0x10009800 to 0x10009FFF
+   81 00000000         ;//    <o.20> Sector 20, 0x1000A000 to 0x1000A7FF
+   82 00000000         ;//    <o.21> Sector 21, 0x1000A800 to 0x1000AFFF
+   83 00000000         ;//    <o.22> Sector 22, 0x1000B000 to 0x1000B7FF
+
+
+
+ARM Macro Assembler    Page 3 
+
+
+   84 00000000         ;//    <o.23> Sector 23, 0x1000B800 to 0x1000BFFF
+   85 00000000         ;//    <o.24> Sector 24, 0x1000C000 to 0x1000C7FF
+   86 00000000         ;//    <o.25> Sector 25, 0x1000C800 to 0x1000CFFF
+   87 00000000         ;//    <o.26> Sector 26, 0x1000D000 to 0x1000D7FF
+   88 00000000         ;//    <o.27> Sector 27, 0x1000D800 to 0x1000DFFF
+   89 00000000         ;//    <o.28> Sector 28, 0x1000E000 to 0x1000E7FF
+   90 00000000         ;//    <o.29> Sector 29, 0x1000E800 to 0x1000EFFF
+   91 00000000         ;//    <o.30> Sector 30, 0x1000F000 to 0x1000F7FF
+   92 00000000         ;//    <o.31> Sector 31, 0x1000F800 to 0x1000FFFF
+   93 00000000         ;// </h>
+   94 00000000 00000000 
+                       FLASHSECTOR
+                               EQU              0x00000000
+   95 00000000 FFFFFFFF 
+                       FMWTP0  EQU              ~FLASHSECTOR
+   96 00000000         ;// </e>
+   97 00000000         
+   98 00000000         ;// <e> Configure Option Page 2
+   99 00000000 00000001 
+                       CONFIGURE_OPTION_2
+                               EQU              1
+  100 00000000         
+  101 00000000         ;// <h> User Data Area 0
+  102 00000000         ;//   <o0> Double 0 <0x00000000-0xFFFFFFFF>
+  103 00000000         ;//   <o1> Double 1 <0x00000000-0xFFFFFFFF>
+  104 00000000         ;//   <o2> Double 2 <0x00000000-0xFFFFFFFF>
+  105 00000000         ;//   <o3> Double 3 <0x00000000-0xFFFFFFFF>
+  106 00000000         ;//   <o4> Double 4 <0x00000000-0xFFFFFFFF>
+  107 00000000         ;//   <o5> Double 5 <0x00000000-0xFFFFFFFF>
+  108 00000000         ;//   <o6> Double 6 <0x00000000-0xFFFFFFFF>
+  109 00000000         ;//   <o7> Double 7 <0x00000000-0xFFFFFFFF>
+  110 00000000         ;//   <o8> Double 8 <0x00000000-0xFFFFFFFF>
+  111 00000000         ;//   <o9> Double 9 <0x00000000-0xFFFFFFFF>
+  112 00000000         ;//   <o10> Double 10 <0x00000000-0xFFFFFFFF>
+  113 00000000         ;//   <o11> Double 11 <0x00000000-0xFFFFFFFF>
+  114 00000000         ;//   <o12> Double 12 <0x00000000-0xFFFFFFFF>
+  115 00000000         ;//   <o13> Double 13 <0x00000000-0xFFFFFFFF>
+  116 00000000         ;//   <o14> Double 14 <0x00000000-0xFFFFFFFF>
+  117 00000000         ;//   <o15> Double 15 <0x00000000-0xFFFFFFFF>
+  118 00000000         ;//   <o16> Double 16 <0x00000000-0xFFFFFFFF>
+  119 00000000         ;//   <o17> Double 17 <0x00000000-0xFFFFFFFF>
+  120 00000000         ;//   <o18> Double 18 <0x00000000-0xFFFFFFFF>
+  121 00000000         ;//   <o19> Double 19 <0x00000000-0xFFFFFFFF>
+  122 00000000         ;//   <o20> Double 20 <0x00000000-0xFFFFFFFF>
+  123 00000000         ;//   <o21> Double 21 <0x00000000-0xFFFFFFFF>
+  124 00000000         ;//   <o22> Double 22 <0x00000000-0xFFFFFFFF>
+  125 00000000         ;//   <o23> Double 23 <0x00000000-0xFFFFFFFF>
+  126 00000000         ;//   <o24> Double 24 <0x00000000-0xFFFFFFFF>
+  127 00000000         ;//   <o25> Double 25 <0x00000000-0xFFFFFFFF>
+  128 00000000         ;//   <o26> Double 26 <0x00000000-0xFFFFFFFF>
+  129 00000000         ;//   <o27> Double 27 <0x00000000-0xFFFFFFFF>
+  130 00000000         ;//   <o28> Double 28 <0x00000000-0xFFFFFFFF>
+  131 00000000         ;//   <o29> Double 29 <0x00000000-0xFFFFFFFF>
+  132 00000000         ;//   <o30> Double 30 <0x00000000-0xFFFFFFFF>
+  133 00000000         ;//   <o31> Double 31 <0x00000000-0xFFFFFFFF>
+  134 00000000         ;// </h>
+  135 00000000 E2E2E2E2 
+                       AREA0_0 EQU              0xe2e2e2e2
+  136 00000000 FFFFFFFF 
+
+
+
+ARM Macro Assembler    Page 4 
+
+
+                       AREA0_1 EQU              0xFFFFFFFF
+  137 00000000 FFFFFFFF 
+                       AREA0_2 EQU              0xFFFFFFFF
+  138 00000000 FFFFFFFF 
+                       AREA0_3 EQU              0xFFFFFFFF
+  139 00000000 FFFFFFFF 
+                       AREA0_4 EQU              0xFFFFFFFF
+  140 00000000 FFFFFFFF 
+                       AREA0_5 EQU              0xFFFFFFFF
+  141 00000000 FFFFFFFF 
+                       AREA0_6 EQU              0xFFFFFFFF
+  142 00000000 FFFFFFFF 
+                       AREA0_7 EQU              0xFFFFFFFF
+  143 00000000 FFFFFFFF 
+                       AREA0_8 EQU              0xFFFFFFFF
+  144 00000000 FFFFFFFF 
+                       AREA0_9 EQU              0xFFFFFFFF
+  145 00000000 FFFFFFFF 
+                       AREA0_10
+                               EQU              0xFFFFFFFF
+  146 00000000 FFFFFFFF 
+                       AREA0_11
+                               EQU              0xFFFFFFFF
+  147 00000000 FFFFFFFF 
+                       AREA0_12
+                               EQU              0xFFFFFFFF
+  148 00000000 FFFFFFFF 
+                       AREA0_13
+                               EQU              0xFFFFFFFF
+  149 00000000 FFFFFFFF 
+                       AREA0_14
+                               EQU              0xFFFFFFFF
+  150 00000000 FFFFFFFF 
+                       AREA0_15
+                               EQU              0xFFFFFFFF
+  151 00000000 FFFFFFFF 
+                       AREA0_16
+                               EQU              0xFFFFFFFF
+  152 00000000 FFFFFFFF 
+                       AREA0_17
+                               EQU              0xFFFFFFFF
+  153 00000000 FFFFFFFF 
+                       AREA0_18
+                               EQU              0xFFFFFFFF
+  154 00000000 FFFFFFFF 
+                       AREA0_19
+                               EQU              0xFFFFFFFF
+  155 00000000 FFFFFFFF 
+                       AREA0_20
+                               EQU              0xFFFFFFFF
+  156 00000000 FFFFFFFF 
+                       AREA0_21
+                               EQU              0xFFFFFFFF
+  157 00000000 FFFFFFFF 
+                       AREA0_22
+                               EQU              0xFFFFFFFF
+  158 00000000 FFFFFFFF 
+                       AREA0_23
+                               EQU              0xFFFFFFFF
+
+
+
+ARM Macro Assembler    Page 5 
+
+
+  159 00000000 FFFFFFFF 
+                       AREA0_24
+                               EQU              0xFFFFFFFF
+  160 00000000 FFFFFFFF 
+                       AREA0_25
+                               EQU              0xFFFFFFFF
+  161 00000000 FFFFFFFF 
+                       AREA0_26
+                               EQU              0xFFFFFFFF
+  162 00000000 FFFFFFFF 
+                       AREA0_27
+                               EQU              0xFFFFFFFF
+  163 00000000 FFFFFFFF 
+                       AREA0_28
+                               EQU              0xFFFFFFFF
+  164 00000000 FFFFFFFF 
+                       AREA0_29
+                               EQU              0xFFFFFFFF
+  165 00000000 FFFFFFFF 
+                       AREA0_30
+                               EQU              0xFFFFFFFF
+  166 00000000 E2E2E2E2 
+                       AREA0_31
+                               EQU              0xe2e2e2e2
+  167 00000000         ;// </e>
+  168 00000000         
+  169 00000000         ;// <e> Configure Option Page 3
+  170 00000000 00000001 
+                       CONFIGURE_OPTION_3
+                               EQU              1
+  171 00000000         
+  172 00000000         ;// <h> User Data Area 1
+  173 00000000         ;//   <o0> Double 0 <0x00000000-0xFFFFFFFF>
+  174 00000000         ;//   <o1> Double 1 <0x00000000-0xFFFFFFFF>
+  175 00000000         ;//   <o2> Double 2 <0x00000000-0xFFFFFFFF>
+  176 00000000         ;//   <o3> Double 3 <0x00000000-0xFFFFFFFF>
+  177 00000000         ;//   <o4> Double 4 <0x00000000-0xFFFFFFFF>
+  178 00000000         ;//   <o5> Double 5 <0x00000000-0xFFFFFFFF>
+  179 00000000         ;//   <o6> Double 6 <0x00000000-0xFFFFFFFF>
+  180 00000000         ;//   <o7> Double 7 <0x00000000-0xFFFFFFFF>
+  181 00000000         ;//   <o8> Double 8 <0x00000000-0xFFFFFFFF>
+  182 00000000         ;//   <o9> Double 9 <0x00000000-0xFFFFFFFF>
+  183 00000000         ;//   <o10> Double 10 <0x00000000-0xFFFFFFFF>
+  184 00000000         ;//   <o11> Double 11 <0x00000000-0xFFFFFFFF>
+  185 00000000         ;//   <o12> Double 12 <0x00000000-0xFFFFFFFF>
+  186 00000000         ;//   <o13> Double 13 <0x00000000-0xFFFFFFFF>
+  187 00000000         ;//   <o14> Double 14 <0x00000000-0xFFFFFFFF>
+  188 00000000         ;//   <o15> Double 15 <0x00000000-0xFFFFFFFF>
+  189 00000000         ;//   <o16> Double 16 <0x00000000-0xFFFFFFFF>
+  190 00000000         ;//   <o17> Double 17 <0x00000000-0xFFFFFFFF>
+  191 00000000         ;//   <o18> Double 18 <0x00000000-0xFFFFFFFF>
+  192 00000000         ;//   <o19> Double 19 <0x00000000-0xFFFFFFFF>
+  193 00000000         ;//   <o20> Double 20 <0x00000000-0xFFFFFFFF>
+  194 00000000         ;//   <o21> Double 21 <0x00000000-0xFFFFFFFF>
+  195 00000000         ;//   <o22> Double 22 <0x00000000-0xFFFFFFFF>
+  196 00000000         ;//   <o23> Double 23 <0x00000000-0xFFFFFFFF>
+  197 00000000         ;//   <o24> Double 24 <0x00000000-0xFFFFFFFF>
+  198 00000000         ;//   <o25> Double 25 <0x00000000-0xFFFFFFFF>
+  199 00000000         ;//   <o26> Double 26 <0x00000000-0xFFFFFFFF>
+
+
+
+ARM Macro Assembler    Page 6 
+
+
+  200 00000000         ;//   <o27> Double 27 <0x00000000-0xFFFFFFFF>
+  201 00000000         ;//   <o28> Double 28 <0x00000000-0xFFFFFFFF>
+  202 00000000         ;//   <o29> Double 29 <0x00000000-0xFFFFFFFF>
+  203 00000000         ;//   <o30> Double 30 <0x00000000-0xFFFFFFFF>
+  204 00000000         ;//   <o31> Double 31 <0x00000000-0xFFFFFFFF>
+  205 00000000         ;// </h>
+  206 00000000 E3E3E3E3 
+                       AREA1_0 EQU              0xe3e3e3e3
+  207 00000000 FFFFFFFF 
+                       AREA1_1 EQU              0xFFFFFFFF
+  208 00000000 FFFFFFFF 
+                       AREA1_2 EQU              0xFFFFFFFF
+  209 00000000 FFFFFFFF 
+                       AREA1_3 EQU              0xFFFFFFFF
+  210 00000000 FFFFFFFF 
+                       AREA1_4 EQU              0xFFFFFFFF
+  211 00000000 FFFFFFFF 
+                       AREA1_5 EQU              0xFFFFFFFF
+  212 00000000 FFFFFFFF 
+                       AREA1_6 EQU              0xFFFFFFFF
+  213 00000000 FFFFFFFF 
+                       AREA1_7 EQU              0xFFFFFFFF
+  214 00000000 FFFFFFFF 
+                       AREA1_8 EQU              0xFFFFFFFF
+  215 00000000 FFFFFFFF 
+                       AREA1_9 EQU              0xFFFFFFFF
+  216 00000000 FFFFFFFF 
+                       AREA1_10
+                               EQU              0xFFFFFFFF
+  217 00000000 FFFFFFFF 
+                       AREA1_11
+                               EQU              0xFFFFFFFF
+  218 00000000 FFFFFFFF 
+                       AREA1_12
+                               EQU              0xFFFFFFFF
+  219 00000000 FFFFFFFF 
+                       AREA1_13
+                               EQU              0xFFFFFFFF
+  220 00000000 FFFFFFFF 
+                       AREA1_14
+                               EQU              0xFFFFFFFF
+  221 00000000 FFFFFFFF 
+                       AREA1_15
+                               EQU              0xFFFFFFFF
+  222 00000000 FFFFFFFF 
+                       AREA1_16
+                               EQU              0xFFFFFFFF
+  223 00000000 FFFFFFFF 
+                       AREA1_17
+                               EQU              0xFFFFFFFF
+  224 00000000 FFFFFFFF 
+                       AREA1_18
+                               EQU              0xFFFFFFFF
+  225 00000000 FFFFFFFF 
+                       AREA1_19
+                               EQU              0xFFFFFFFF
+  226 00000000 FFFFFFFF 
+                       AREA1_20
+                               EQU              0xFFFFFFFF
+
+
+
+ARM Macro Assembler    Page 7 
+
+
+  227 00000000 FFFFFFFF 
+                       AREA1_21
+                               EQU              0xFFFFFFFF
+  228 00000000 FFFFFFFF 
+                       AREA1_22
+                               EQU              0xFFFFFFFF
+  229 00000000 FFFFFFFF 
+                       AREA1_23
+                               EQU              0xFFFFFFFF
+  230 00000000 FFFFFFFF 
+                       AREA1_24
+                               EQU              0xFFFFFFFF
+  231 00000000 FFFFFFFF 
+                       AREA1_25
+                               EQU              0xFFFFFFFF
+  232 00000000 FFFFFFFF 
+                       AREA1_26
+                               EQU              0xFFFFFFFF
+  233 00000000 FFFFFFFF 
+                       AREA1_27
+                               EQU              0xFFFFFFFF
+  234 00000000 FFFFFFFF 
+                       AREA1_28
+                               EQU              0xFFFFFFFF
+  235 00000000 FFFFFFFF 
+                       AREA1_29
+                               EQU              0xFFFFFFFF
+  236 00000000 FFFFFFFF 
+                       AREA1_30
+                               EQU              0xFFFFFFFF
+  237 00000000 E3E3E3E3 
+                       AREA1_31
+                               EQU              0xe3e3e3e3
+  238 00000000         ;// </e>
+  239 00000000         
+  240 00000000                 IF               CONFIGURE_OPTION_1 <> 0
+  241 00000000                 AREA             |.ARM.__AT_0x1FFFF200|, CODE, R
+EADONLY
+  242 00000000 69C8A273        DCD              RPCNFIG
+  243 00000004 FF FF 00 
+              00 FF FF 
+              00 00            DCW              EX0CNFIG, nEX0CNFIG, EX1CNFIG, 
+nEX1CNFIG
+  244 0000000C FFFF96DB        DCD              WDTCNFIG
+  245 00000010 FFFFAAFF        DCD              LVRCNFIG
+  246 00000014 FFFFFFFF        DCD              CNFIGWTP1
+  247 00000018 FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+              FF FF FF 
+
+
+
+ARM Macro Assembler    Page 8 
+
+
+              FF               FILL             40,0xFF,1
+  248 00000040 FFFFFFFF        DCD              FMWTP0
+  249 00000044                 ENDIF
+  250 00000044         
+  251 00000044                 IF               CONFIGURE_OPTION_2 <> 0
+  252 00000044                 AREA             |.ARM.__AT_0x1FFFF400|, CODE, R
+EADONLY
+  253 00000000 E2E2E2E2 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF         DCD              AREA0_0, AREA0_1, AREA0_2, AREA
+0_3, AREA0_4, AREA0_5, AREA0_6, AREA0_7
+  254 00000020 FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF         DCD              AREA0_8, AREA0_9, AREA0_10, ARE
+A0_11, AREA0_12, AREA0_13, AREA0_14, AREA0_15
+  255 00000040 FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF         DCD              AREA0_16, AREA0_17, AREA0_18, A
+REA0_19, AREA0_20, AREA0_21, AREA0_22, AREA0_23
+  256 00000060 FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              E2E2E2E2         DCD              AREA0_24, AREA0_25, AREA0_26, A
+REA0_27, AREA0_28, AREA0_29, AREA0_30, AREA0_31
+  257 00000080                 ENDIF
+  258 00000080         
+  259 00000080                 IF               CONFIGURE_OPTION_3 <> 0
+  260 00000080                 AREA             |.ARM.__AT_0x1FFFF600|, CODE, R
+EADONLY
+  261 00000000 E3E3E3E3 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF         DCD              AREA1_0, AREA1_1, AREA1_2, AREA
+1_3, AREA1_4, AREA1_5, AREA1_6, AREA1_7
+  262 00000020 FFFFFFFF 
+              FFFFFFFF 
+
+
+
+ARM Macro Assembler    Page 9 
+
+
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF         DCD              AREA1_8, AREA1_9, AREA1_10, ARE
+A1_11, AREA1_12, AREA1_13, AREA1_14, AREA1_15
+  263 00000040 FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF         DCD              AREA1_16, AREA1_17, AREA1_18, A
+REA1_19, AREA1_20, AREA1_21, AREA1_22, AREA1_23
+  264 00000060 FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              FFFFFFFF 
+              E3E3E3E3         DCD              AREA1_24, AREA1_25, AREA1_26, A
+REA1_27, AREA1_28, AREA1_29, AREA1_30, AREA1_31
+  265 00000080                 ENDIF
+  266 00000080         
+  267 00000080                 END
+Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw
+ork --depend=.\objects\option_a31g12x.d -o.\objects\option_a31g12x.o -IC:\Users
+\Imbis\AppData\Local\Arm\Packs\ABOV\CM0_DFP\1.0.4\A31G12x\Core\include -I"C:\Pr
+ogram Files (x86)\Keil_v5\ARM\CMSIS\Include" --predefine="__MICROLIB SETA 1" --
+predefine="__UVISION_VERSION SETA 533" --list=.\listings\option_a31g12x.lst SDK
+_V2_5_0\Option\option_A31G12x.s
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.ARM.__AT_0x1FFFF200 00000000
+
+Symbol: .ARM.__AT_0x1FFFF200
+   Definitions
+      At line 241 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      None
+Comment: .ARM.__AT_0x1FFFF200 unused
+1 symbol
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.ARM.__AT_0x1FFFF400 00000000
+
+Symbol: .ARM.__AT_0x1FFFF400
+   Definitions
+      At line 252 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      None
+Comment: .ARM.__AT_0x1FFFF400 unused
+1 symbol
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.ARM.__AT_0x1FFFF600 00000000
+
+Symbol: .ARM.__AT_0x1FFFF600
+   Definitions
+      At line 260 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      None
+Comment: .ARM.__AT_0x1FFFF600 unused
+1 symbol
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Absolute symbols
+
+AREA0_0 E2E2E2E2
+
+Symbol: AREA0_0
+   Definitions
+      At line 135 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 253 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_0 used once
+AREA0_1 FFFFFFFF
+
+Symbol: AREA0_1
+   Definitions
+      At line 136 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 253 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_1 used once
+AREA0_10 FFFFFFFF
+
+Symbol: AREA0_10
+   Definitions
+      At line 145 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 254 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_10 used once
+AREA0_11 FFFFFFFF
+
+Symbol: AREA0_11
+   Definitions
+      At line 146 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 254 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_11 used once
+AREA0_12 FFFFFFFF
+
+Symbol: AREA0_12
+   Definitions
+      At line 147 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 254 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_12 used once
+AREA0_13 FFFFFFFF
+
+Symbol: AREA0_13
+   Definitions
+      At line 148 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 254 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_13 used once
+AREA0_14 FFFFFFFF
+
+Symbol: AREA0_14
+   Definitions
+      At line 149 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 254 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_14 used once
+AREA0_15 FFFFFFFF
+
+Symbol: AREA0_15
+
+
+
+ARM Macro Assembler    Page 2 Alphabetic symbol ordering
+Absolute symbols
+
+   Definitions
+      At line 150 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 254 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_15 used once
+AREA0_16 FFFFFFFF
+
+Symbol: AREA0_16
+   Definitions
+      At line 151 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 255 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_16 used once
+AREA0_17 FFFFFFFF
+
+Symbol: AREA0_17
+   Definitions
+      At line 152 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 255 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_17 used once
+AREA0_18 FFFFFFFF
+
+Symbol: AREA0_18
+   Definitions
+      At line 153 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 255 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_18 used once
+AREA0_19 FFFFFFFF
+
+Symbol: AREA0_19
+   Definitions
+      At line 154 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 255 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_19 used once
+AREA0_2 FFFFFFFF
+
+Symbol: AREA0_2
+   Definitions
+      At line 137 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 253 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_2 used once
+AREA0_20 FFFFFFFF
+
+Symbol: AREA0_20
+   Definitions
+      At line 155 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 255 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_20 used once
+AREA0_21 FFFFFFFF
+
+Symbol: AREA0_21
+   Definitions
+      At line 156 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+
+
+
+ARM Macro Assembler    Page 3 Alphabetic symbol ordering
+Absolute symbols
+
+      At line 255 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_21 used once
+AREA0_22 FFFFFFFF
+
+Symbol: AREA0_22
+   Definitions
+      At line 157 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 255 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_22 used once
+AREA0_23 FFFFFFFF
+
+Symbol: AREA0_23
+   Definitions
+      At line 158 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 255 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_23 used once
+AREA0_24 FFFFFFFF
+
+Symbol: AREA0_24
+   Definitions
+      At line 159 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 256 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_24 used once
+AREA0_25 FFFFFFFF
+
+Symbol: AREA0_25
+   Definitions
+      At line 160 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 256 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_25 used once
+AREA0_26 FFFFFFFF
+
+Symbol: AREA0_26
+   Definitions
+      At line 161 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 256 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_26 used once
+AREA0_27 FFFFFFFF
+
+Symbol: AREA0_27
+   Definitions
+      At line 162 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 256 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_27 used once
+AREA0_28 FFFFFFFF
+
+Symbol: AREA0_28
+   Definitions
+      At line 163 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 256 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_28 used once
+AREA0_29 FFFFFFFF
+
+
+
+ARM Macro Assembler    Page 4 Alphabetic symbol ordering
+Absolute symbols
+
+
+Symbol: AREA0_29
+   Definitions
+      At line 164 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 256 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_29 used once
+AREA0_3 FFFFFFFF
+
+Symbol: AREA0_3
+   Definitions
+      At line 138 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 253 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_3 used once
+AREA0_30 FFFFFFFF
+
+Symbol: AREA0_30
+   Definitions
+      At line 165 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 256 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_30 used once
+AREA0_31 E2E2E2E2
+
+Symbol: AREA0_31
+   Definitions
+      At line 166 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 256 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_31 used once
+AREA0_4 FFFFFFFF
+
+Symbol: AREA0_4
+   Definitions
+      At line 139 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 253 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_4 used once
+AREA0_5 FFFFFFFF
+
+Symbol: AREA0_5
+   Definitions
+      At line 140 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 253 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_5 used once
+AREA0_6 FFFFFFFF
+
+Symbol: AREA0_6
+   Definitions
+      At line 141 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 253 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_6 used once
+AREA0_7 FFFFFFFF
+
+Symbol: AREA0_7
+   Definitions
+
+
+
+ARM Macro Assembler    Page 5 Alphabetic symbol ordering
+Absolute symbols
+
+      At line 142 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 253 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_7 used once
+AREA0_8 FFFFFFFF
+
+Symbol: AREA0_8
+   Definitions
+      At line 143 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 254 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_8 used once
+AREA0_9 FFFFFFFF
+
+Symbol: AREA0_9
+   Definitions
+      At line 144 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 254 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA0_9 used once
+AREA1_0 E3E3E3E3
+
+Symbol: AREA1_0
+   Definitions
+      At line 206 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 261 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_0 used once
+AREA1_1 FFFFFFFF
+
+Symbol: AREA1_1
+   Definitions
+      At line 207 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 261 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_1 used once
+AREA1_10 FFFFFFFF
+
+Symbol: AREA1_10
+   Definitions
+      At line 216 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 262 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_10 used once
+AREA1_11 FFFFFFFF
+
+Symbol: AREA1_11
+   Definitions
+      At line 217 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 262 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_11 used once
+AREA1_12 FFFFFFFF
+
+Symbol: AREA1_12
+   Definitions
+      At line 218 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 262 in file SDK_V2_5_0\Option\option_A31G12x.s
+
+
+
+ARM Macro Assembler    Page 6 Alphabetic symbol ordering
+Absolute symbols
+
+Comment: AREA1_12 used once
+AREA1_13 FFFFFFFF
+
+Symbol: AREA1_13
+   Definitions
+      At line 219 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 262 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_13 used once
+AREA1_14 FFFFFFFF
+
+Symbol: AREA1_14
+   Definitions
+      At line 220 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 262 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_14 used once
+AREA1_15 FFFFFFFF
+
+Symbol: AREA1_15
+   Definitions
+      At line 221 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 262 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_15 used once
+AREA1_16 FFFFFFFF
+
+Symbol: AREA1_16
+   Definitions
+      At line 222 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 263 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_16 used once
+AREA1_17 FFFFFFFF
+
+Symbol: AREA1_17
+   Definitions
+      At line 223 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 263 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_17 used once
+AREA1_18 FFFFFFFF
+
+Symbol: AREA1_18
+   Definitions
+      At line 224 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 263 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_18 used once
+AREA1_19 FFFFFFFF
+
+Symbol: AREA1_19
+   Definitions
+      At line 225 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 263 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_19 used once
+AREA1_2 FFFFFFFF
+
+
+
+
+ARM Macro Assembler    Page 7 Alphabetic symbol ordering
+Absolute symbols
+
+Symbol: AREA1_2
+   Definitions
+      At line 208 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 261 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_2 used once
+AREA1_20 FFFFFFFF
+
+Symbol: AREA1_20
+   Definitions
+      At line 226 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 263 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_20 used once
+AREA1_21 FFFFFFFF
+
+Symbol: AREA1_21
+   Definitions
+      At line 227 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 263 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_21 used once
+AREA1_22 FFFFFFFF
+
+Symbol: AREA1_22
+   Definitions
+      At line 228 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 263 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_22 used once
+AREA1_23 FFFFFFFF
+
+Symbol: AREA1_23
+   Definitions
+      At line 229 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 263 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_23 used once
+AREA1_24 FFFFFFFF
+
+Symbol: AREA1_24
+   Definitions
+      At line 230 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 264 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_24 used once
+AREA1_25 FFFFFFFF
+
+Symbol: AREA1_25
+   Definitions
+      At line 231 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 264 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_25 used once
+AREA1_26 FFFFFFFF
+
+Symbol: AREA1_26
+   Definitions
+      At line 232 in file SDK_V2_5_0\Option\option_A31G12x.s
+
+
+
+ARM Macro Assembler    Page 8 Alphabetic symbol ordering
+Absolute symbols
+
+   Uses
+      At line 264 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_26 used once
+AREA1_27 FFFFFFFF
+
+Symbol: AREA1_27
+   Definitions
+      At line 233 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 264 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_27 used once
+AREA1_28 FFFFFFFF
+
+Symbol: AREA1_28
+   Definitions
+      At line 234 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 264 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_28 used once
+AREA1_29 FFFFFFFF
+
+Symbol: AREA1_29
+   Definitions
+      At line 235 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 264 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_29 used once
+AREA1_3 FFFFFFFF
+
+Symbol: AREA1_3
+   Definitions
+      At line 209 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 261 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_3 used once
+AREA1_30 FFFFFFFF
+
+Symbol: AREA1_30
+   Definitions
+      At line 236 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 264 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_30 used once
+AREA1_31 E3E3E3E3
+
+Symbol: AREA1_31
+   Definitions
+      At line 237 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 264 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_31 used once
+AREA1_4 FFFFFFFF
+
+Symbol: AREA1_4
+   Definitions
+      At line 210 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 261 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_4 used once
+
+
+
+ARM Macro Assembler    Page 9 Alphabetic symbol ordering
+Absolute symbols
+
+AREA1_5 FFFFFFFF
+
+Symbol: AREA1_5
+   Definitions
+      At line 211 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 261 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_5 used once
+AREA1_6 FFFFFFFF
+
+Symbol: AREA1_6
+   Definitions
+      At line 212 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 261 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_6 used once
+AREA1_7 FFFFFFFF
+
+Symbol: AREA1_7
+   Definitions
+      At line 213 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 261 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_7 used once
+AREA1_8 FFFFFFFF
+
+Symbol: AREA1_8
+   Definitions
+      At line 214 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 262 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_8 used once
+AREA1_9 FFFFFFFF
+
+Symbol: AREA1_9
+   Definitions
+      At line 215 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 262 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: AREA1_9 used once
+CNFIGWTP1 FFFFFFFF
+
+Symbol: CNFIGWTP1
+   Definitions
+      At line 58 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 246 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: CNFIGWTP1 used once
+CONFIGURE_OPTION_1 00000001
+
+Symbol: CONFIGURE_OPTION_1
+   Definitions
+      At line 15 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 240 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: CONFIGURE_OPTION_1 used once
+CONFIGURE_OPTION_2 00000001
+
+Symbol: CONFIGURE_OPTION_2
+
+
+
+ARM Macro Assembler    Page 10 Alphabetic symbol ordering
+Absolute symbols
+
+   Definitions
+      At line 99 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 251 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: CONFIGURE_OPTION_2 used once
+CONFIGURE_OPTION_3 00000001
+
+Symbol: CONFIGURE_OPTION_3
+   Definitions
+      At line 170 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 259 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: CONFIGURE_OPTION_3 used once
+EX0CNFIG 0000FFFF
+
+Symbol: EX0CNFIG
+   Definitions
+      At line 27 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 29 in file SDK_V2_5_0\Option\option_A31G12x.s
+      At line 243 in file SDK_V2_5_0\Option\option_A31G12x.s
+
+EX1CNFIG 0000FFFF
+
+Symbol: EX1CNFIG
+   Definitions
+      At line 28 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 30 in file SDK_V2_5_0\Option\option_A31G12x.s
+      At line 243 in file SDK_V2_5_0\Option\option_A31G12x.s
+
+FLASHSECTOR 00000000
+
+Symbol: FLASHSECTOR
+   Definitions
+      At line 94 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 95 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: FLASHSECTOR used once
+FMWTP0 FFFFFFFF
+
+Symbol: FMWTP0
+   Definitions
+      At line 95 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 248 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: FMWTP0 used once
+LVRCNFIG FFFFAAFF
+
+Symbol: LVRCNFIG
+   Definitions
+      At line 50 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 245 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: LVRCNFIG used once
+OPTIONPAGE 00000000
+
+Symbol: OPTIONPAGE
+   Definitions
+
+
+
+ARM Macro Assembler    Page 11 Alphabetic symbol ordering
+Absolute symbols
+
+      At line 57 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 58 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: OPTIONPAGE used once
+RPCNFIG 69C8A273
+
+Symbol: RPCNFIG
+   Definitions
+      At line 21 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 242 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: RPCNFIG used once
+WDTCNFIG FFFF96DB
+
+Symbol: WDTCNFIG
+   Definitions
+      At line 42 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 244 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: WDTCNFIG used once
+nEX0CNFIG 00000000
+
+Symbol: nEX0CNFIG
+   Definitions
+      At line 29 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 243 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: nEX0CNFIG used once
+nEX1CNFIG 00000000
+
+Symbol: nEX1CNFIG
+   Definitions
+      At line 30 in file SDK_V2_5_0\Option\option_A31G12x.s
+   Uses
+      At line 243 in file SDK_V2_5_0\Option\option_A31G12x.s
+Comment: nEX1CNFIG used once
+78 symbols
+413 symbols in table
diff --git a/Project/Listings/startup_a31g12x.lst b/Project/Listings/startup_a31g12x.lst
new file mode 100644
index 0000000..04e6a05
--- /dev/null
+++ b/Project/Listings/startup_a31g12x.lst
@@ -0,0 +1,866 @@
+
+
+
+ARM Macro Assembler    Page 1 
+
+
+    1 00000000         ;/******************************************************
+                       ********************//**
+    2 00000000         ; * @file     startup_A31G12x.s
+    3 00000000         ; * @brief    CMSIS Core Device Startup File for
+    4 00000000         ; *           A31G12x Device Series
+    5 00000000         ; * @version  V5.00
+    6 00000000         ; * @date     02. March 2016
+    7 00000000         ; ******************************************************
+                       ************************/
+    8 00000000         ;/*
+    9 00000000         ; * Copyright (c) 2009-2016 ARM Limited. All rights rese
+                       rved.
+   10 00000000         ; *
+   11 00000000         ; * SPDX-License-Identifier: Apache-2.0
+   12 00000000         ; *
+   13 00000000         ; * Licensed under the Apache License, Version 2.0 (the 
+                       License); you may
+   14 00000000         ; * not use this file except in compliance with the Lice
+                       nse.
+   15 00000000         ; * You may obtain a copy of the License at
+   16 00000000         ; *
+   17 00000000         ; * www.apache.org/licenses/LICENSE-2.0
+   18 00000000         ; *
+   19 00000000         ; * Unless required by applicable law or agreed to in wr
+                       iting, software
+   20 00000000         ; * distributed under the License is distributed on an A
+                       S IS BASIS, WITHOUT
+   21 00000000         ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express
+                        or implied.
+   22 00000000         ; * See the License for the specific language governing 
+                       permissions and
+   23 00000000         ; * limitations under the License.
+   24 00000000         ; */
+   25 00000000         
+   26 00000000         ;/*
+   27 00000000         ;//-------- <<< Use Configuration Wizard in Context Menu
+                        >>> ------------------
+   28 00000000         ;*/
+   29 00000000         
+   30 00000000         
+   31 00000000         ; <h> Stack Configuration
+   32 00000000         ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+   33 00000000         ; </h>
+   34 00000000         
+   35 00000000 00000500 
+                       Stack_Size
+                               EQU              0x00000500
+   36 00000000         
+   37 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
+=3
+   38 00000000         Stack_Mem
+                               SPACE            Stack_Size
+   39 00000500         __initial_sp
+   40 00000500         
+   41 00000500         
+   42 00000500         ; <h> Heap Configuration
+   43 00000500         ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+   44 00000500         ; </h>
+   45 00000500         
+
+
+
+ARM Macro Assembler    Page 2 
+
+
+   46 00000500 00000080 
+                       Heap_Size
+                               EQU              0x00000080
+   47 00000500         
+   48 00000500                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
+3
+   49 00000000         __heap_base
+   50 00000000         Heap_Mem
+                               SPACE            Heap_Size
+   51 00000080         __heap_limit
+   52 00000080         
+   53 00000080         
+   54 00000080                 PRESERVE8
+   55 00000080                 THUMB
+   56 00000080         
+   57 00000080         
+   58 00000080         ; Vector Table Mapped to Address 0 at Reset
+   59 00000080         
+   60 00000080                 AREA             RESET, DATA, READONLY
+   61 00000000                 EXPORT           __Vectors
+   62 00000000                 EXPORT           __Vectors_End
+   63 00000000                 EXPORT           __Vectors_Size
+   64 00000000         
+   65 00000000 00000000 
+                       __Vectors
+                               DCD              __initial_sp ; Top of Stack
+   66 00000004 00000000        DCD              Reset_Handler ; Reset Handler
+   67 00000008 00000000        DCD              NMI_Handler ; NMI Handler
+   68 0000000C 00000000        DCD              HardFault_Handler ; Hard Fault 
+                                                            Handler
+   69 00000010 00000000        DCD              0           ; Reserved
+   70 00000014 00000000        DCD              0           ; Reserved
+   71 00000018 00000000        DCD              0           ; Reserved
+   72 0000001C 00000000        DCD              0           ; Reserved
+   73 00000020 00000000        DCD              0           ; Reserved
+   74 00000024 00000000        DCD              0           ; Reserved
+   75 00000028 00000000        DCD              0           ; Reserved
+   76 0000002C 00000000        DCD              SVC_Handler ; SVCall Handler
+   77 00000030 00000000        DCD              0           ; Reserved
+   78 00000034 00000000        DCD              0           ; Reserved
+   79 00000038 00000000        DCD              PendSV_Handler ; PendSV Handler
+                                                            
+   80 0000003C 00000000        DCD              SysTick_Handler 
+                                                            ; SysTick Handler
+   81 00000040         
+   82 00000040         ; External Interrupts
+   83 00000040 00000000        DCD              LVI_Handler ; IRQ 0
+   84 00000044 00000000        DCD              WUT_Handler ; IRQ 1
+   85 00000048 00000000        DCD              WDT_Handler ; IRQ 2
+   86 0000004C 00000000        DCD              EINT0_Handler ; IRQ 3
+   87 00000050 00000000        DCD              EINT1_Handler ; IRQ 4
+   88 00000054 00000000        DCD              EINT2_Handler ; IRQ 5
+   89 00000058 00000000        DCD              EINT3_Handler ; IRQ 6
+   90 0000005C 00000000        DCD              TIMER10_Handler ; IRQ 7
+   91 00000060 00000000        DCD              TIMER11_Handler ; IRQ 8
+   92 00000064 00000000        DCD              TIMER12_Handler ; IRQ 9
+   93 00000068 00000000        DCD              I2C0_Handler ; IRQ 10
+   94 0000006C 00000000        DCD              USART10_Handler ; IRQ 11
+   95 00000070 00000000        DCD              WT_Handler  ; IRQ 12
+
+
+
+ARM Macro Assembler    Page 3 
+
+
+   96 00000074 00000000        DCD              TIMER30_Handler ; IRQ 13
+   97 00000078 00000000        DCD              I2C1_Handler ; IRQ 14
+   98 0000007C 00000000        DCD              TIMER20_Handler ; IRQ 15
+   99 00000080 00000000        DCD              TIMER21_Handler ; IRQ 16
+  100 00000084 00000000        DCD              USART11_Handler ; IRQ 17
+  101 00000088 00000000        DCD              ADC_Handler ; IRQ 18
+  102 0000008C 00000000        DCD              UART0_Handler ; IRQ 19
+  103 00000090 00000000        DCD              UART1_Handler ; IRQ 20
+  104 00000094 00000000        DCD              TIMER13_Handler ; IRQ 21
+  105 00000098 00000000        DCD              TIMER14_Handler ; IRQ 22
+  106 0000009C 00000000        DCD              TIMER15_Handler ; IRQ 23
+  107 000000A0 00000000        DCD              TIMER16_Handler ; IRQ 24
+  108 000000A4 00000000        DCD              I2C2_Handler ; IRQ 25
+  109 000000A8 00000000        DCD              USART12_Handler ; IRQ 26
+  110 000000AC 00000000        DCD              USART13_Handler ; IRQ 27
+  111 000000B0         ;DCD     RESERVED_Handler          ; IRQ 28
+  112 000000B0         ;DCD     RESERVED_Handler          ; IRQ 29
+  113 000000B0         ;DCD     RESERVED_Handler          ; IRQ 30
+  114 000000B0         ;DCD     RESERVED_Handler          ; IRQ 31
+  115 000000B0         __Vectors_End
+  116 000000B0         
+  117 000000B0 000000B0 
+                       __Vectors_Size
+                               EQU              __Vectors_End - __Vectors
+  118 000000B0         
+  119 000000B0                 AREA             |.text|, CODE, READONLY
+  120 00000000         
+  121 00000000         
+  122 00000000         ; Reset Handler
+  123 00000000         
+  124 00000000         Reset_Handler
+                               PROC
+  125 00000000                 EXPORT           Reset_Handler             [WEAK
+]
+  126 00000000                 IMPORT           SystemInit
+  127 00000000                 IMPORT           __main
+  128 00000000 4804            LDR              R0, =SystemInit
+  129 00000002 4780            BLX              R0
+  130 00000004 4804            LDR              R0, =__main
+  131 00000006 4700            BX               R0
+  132 00000008                 ENDP
+  133 00000008         
+  134 00000008         
+  135 00000008         ; Dummy Exception Handlers (infinite loops which can be 
+                       modified)
+  136 00000008         
+  137 00000008         NMI_Handler
+                               PROC
+  138 00000008                 EXPORT           NMI_Handler               [WEAK
+]
+  139 00000008 E7FE            B                .
+  140 0000000A                 ENDP
+  142 0000000A         HardFault_Handler
+                               PROC
+  143 0000000A                 EXPORT           HardFault_Handler         [WEAK
+]
+  144 0000000A E7FE            B                .
+  145 0000000C                 ENDP
+  146 0000000C         SVC_Handler
+
+
+
+ARM Macro Assembler    Page 4 
+
+
+                               PROC
+  147 0000000C                 EXPORT           SVC_Handler               [WEAK
+]
+  148 0000000C E7FE            B                .
+  149 0000000E                 ENDP
+  150 0000000E         PendSV_Handler
+                               PROC
+  151 0000000E                 EXPORT           PendSV_Handler            [WEAK
+]
+  152 0000000E E7FE            B                .
+  153 00000010                 ENDP
+  154 00000010         SysTick_Handler
+                               PROC
+  155 00000010                 EXPORT           SysTick_Handler           [WEAK
+]
+  156 00000010 E7FE            B                .
+  157 00000012                 ENDP
+  158 00000012         
+  159 00000012         DEVICE_Handler
+                               PROC
+  160 00000012         
+  161 00000012                 EXPORT           LVI_Handler               [WEAK
+]
+  162 00000012                 EXPORT           WUT_Handler               [WEAK
+]
+  163 00000012                 EXPORT           WDT_Handler               [WEAK
+]
+  164 00000012                 EXPORT           EINT0_Handler             [WEAK
+]
+  165 00000012                 EXPORT           EINT1_Handler             [WEAK
+]
+  166 00000012                 EXPORT           EINT2_Handler             [WEAK
+]
+  167 00000012                 EXPORT           EINT3_Handler             [WEAK
+]
+  168 00000012                 EXPORT           TIMER10_Handler           [WEAK
+]
+  169 00000012                 EXPORT           TIMER11_Handler           [WEAK
+]
+  170 00000012                 EXPORT           TIMER12_Handler           [WEAK
+]
+  171 00000012                 EXPORT           I2C0_Handler              [WEAK
+]
+  172 00000012                 EXPORT           USART10_Handler           [WEAK
+]
+  173 00000012                 EXPORT           WT_Handler                [WEAK
+]
+  174 00000012                 EXPORT           TIMER30_Handler           [WEAK
+]
+  175 00000012                 EXPORT           I2C1_Handler              [WEAK
+]
+  176 00000012                 EXPORT           TIMER20_Handler           [WEAK
+]
+  177 00000012                 EXPORT           TIMER21_Handler           [WEAK
+]
+  178 00000012                 EXPORT           USART11_Handler           [WEAK
+]
+  179 00000012                 EXPORT           ADC_Handler               [WEAK
+]
+
+
+
+ARM Macro Assembler    Page 5 
+
+
+  180 00000012                 EXPORT           UART0_Handler             [WEAK
+]
+  181 00000012                 EXPORT           UART1_Handler             [WEAK
+]
+  182 00000012                 EXPORT           TIMER13_Handler           [WEAK
+]
+  183 00000012                 EXPORT           TIMER14_Handler           [WEAK
+]
+  184 00000012                 EXPORT           TIMER15_Handler           [WEAK
+]
+  185 00000012                 EXPORT           TIMER16_Handler           [WEAK
+]
+  186 00000012                 EXPORT           I2C2_Handler              [WEAK
+]
+  187 00000012                 EXPORT           USART12_Handler           [WEAK
+]
+  188 00000012                 EXPORT           USART13_Handler           [WEAK
+]
+  189 00000012         
+  190 00000012         LVI_Handler
+  191 00000012         WUT_Handler
+  192 00000012         WDT_Handler
+  193 00000012         EINT0_Handler
+  194 00000012         EINT1_Handler
+  195 00000012         EINT2_Handler
+  196 00000012         EINT3_Handler
+  197 00000012         TIMER10_Handler
+  198 00000012         TIMER11_Handler
+  199 00000012         TIMER12_Handler
+  200 00000012         I2C0_Handler
+  201 00000012         USART10_Handler
+  202 00000012         WT_Handler
+  203 00000012         TIMER30_Handler
+  204 00000012         I2C1_Handler
+  205 00000012         TIMER20_Handler
+  206 00000012         TIMER21_Handler
+  207 00000012         USART11_Handler
+  208 00000012         ADC_Handler
+  209 00000012         UART0_Handler
+  210 00000012         UART1_Handler
+  211 00000012         TIMER13_Handler
+  212 00000012         TIMER14_Handler
+  213 00000012         TIMER15_Handler
+  214 00000012         TIMER16_Handler
+  215 00000012         I2C2_Handler
+  216 00000012         USART12_Handler
+  217 00000012         USART13_Handler
+  218 00000012 E7FE            B                .
+  219 00000014         
+  220 00000014                 ENDP
+  221 00000014         
+  222 00000014         
+  223 00000014                 ALIGN
+  224 00000014         
+  225 00000014         
+  226 00000014         ; User Initial Stack & Heap
+  227 00000014         
+  228 00000014                 IF               :DEF:__MICROLIB
+  229 00000014         
+
+
+
+ARM Macro Assembler    Page 6 
+
+
+  230 00000014                 EXPORT           __initial_sp
+  231 00000014                 EXPORT           __heap_base
+  232 00000014                 EXPORT           __heap_limit
+  233 00000014         
+  234 00000014                 ELSE
+  249                          ENDIF
+  250 00000014         
+  251 00000014         
+  252 00000014                 END
+              00000000 
+              00000000 
+Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw
+ork --depend=.\objects\startup_a31g12x.d -o.\objects\startup_a31g12x.o -IC:\Use
+rs\Imbis\AppData\Local\Arm\Packs\ABOV\CM0_DFP\1.0.4\A31G12x\Core\include -I"C:\
+Program Files (x86)\Keil_v5\ARM\CMSIS\Include" --predefine="__MICROLIB SETA 1" 
+--predefine="__UVISION_VERSION SETA 533" --list=.\listings\startup_a31g12x.lst 
+SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+STACK 00000000
+
+Symbol: STACK
+   Definitions
+      At line 37 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      None
+Comment: STACK unused
+Stack_Mem 00000000
+
+Symbol: Stack_Mem
+   Definitions
+      At line 38 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      None
+Comment: Stack_Mem unused
+__initial_sp 00000500
+
+Symbol: __initial_sp
+   Definitions
+      At line 39 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 65 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 230 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+3 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+HEAP 00000000
+
+Symbol: HEAP
+   Definitions
+      At line 48 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      None
+Comment: HEAP unused
+Heap_Mem 00000000
+
+Symbol: Heap_Mem
+   Definitions
+      At line 50 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      None
+Comment: Heap_Mem unused
+__heap_base 00000000
+
+Symbol: __heap_base
+   Definitions
+      At line 49 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 231 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+Comment: __heap_base used once
+__heap_limit 00000080
+
+Symbol: __heap_limit
+   Definitions
+      At line 51 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 232 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+Comment: __heap_limit used once
+4 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+RESET 00000000
+
+Symbol: RESET
+   Definitions
+      At line 60 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      None
+Comment: RESET unused
+__Vectors 00000000
+
+Symbol: __Vectors
+   Definitions
+      At line 65 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 61 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 117 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+__Vectors_End 000000B0
+
+Symbol: __Vectors_End
+   Definitions
+      At line 115 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 62 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 117 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+3 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.text 00000000
+
+Symbol: .text
+   Definitions
+      At line 119 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      None
+Comment: .text unused
+ADC_Handler 00000012
+
+Symbol: ADC_Handler
+   Definitions
+      At line 208 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 101 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 179 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+DEVICE_Handler 00000012
+
+Symbol: DEVICE_Handler
+   Definitions
+      At line 159 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      None
+Comment: DEVICE_Handler unused
+EINT0_Handler 00000012
+
+Symbol: EINT0_Handler
+   Definitions
+      At line 193 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 86 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 164 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+EINT1_Handler 00000012
+
+Symbol: EINT1_Handler
+   Definitions
+      At line 194 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 87 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 165 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+EINT2_Handler 00000012
+
+Symbol: EINT2_Handler
+   Definitions
+      At line 195 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 88 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 166 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+EINT3_Handler 00000012
+
+Symbol: EINT3_Handler
+   Definitions
+      At line 196 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 89 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+
+
+ARM Macro Assembler    Page 2 Alphabetic symbol ordering
+Relocatable symbols
+
+      At line 167 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+HardFault_Handler 0000000A
+
+Symbol: HardFault_Handler
+   Definitions
+      At line 142 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 68 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 143 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+I2C0_Handler 00000012
+
+Symbol: I2C0_Handler
+   Definitions
+      At line 200 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 93 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 171 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+I2C1_Handler 00000012
+
+Symbol: I2C1_Handler
+   Definitions
+      At line 204 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 97 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 175 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+I2C2_Handler 00000012
+
+Symbol: I2C2_Handler
+   Definitions
+      At line 215 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 108 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 186 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+LVI_Handler 00000012
+
+Symbol: LVI_Handler
+   Definitions
+      At line 190 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 83 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 161 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+NMI_Handler 00000008
+
+Symbol: NMI_Handler
+   Definitions
+      At line 137 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 67 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 138 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+PendSV_Handler 0000000E
+
+Symbol: PendSV_Handler
+
+
+
+ARM Macro Assembler    Page 3 Alphabetic symbol ordering
+Relocatable symbols
+
+   Definitions
+      At line 150 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 79 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 151 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+Reset_Handler 00000000
+
+Symbol: Reset_Handler
+   Definitions
+      At line 124 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 66 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 125 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+SVC_Handler 0000000C
+
+Symbol: SVC_Handler
+   Definitions
+      At line 146 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 76 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 147 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+SysTick_Handler 00000010
+
+Symbol: SysTick_Handler
+   Definitions
+      At line 154 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 80 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 155 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER10_Handler 00000012
+
+Symbol: TIMER10_Handler
+   Definitions
+      At line 197 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 90 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 168 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER11_Handler 00000012
+
+Symbol: TIMER11_Handler
+   Definitions
+      At line 198 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 91 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 169 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER12_Handler 00000012
+
+Symbol: TIMER12_Handler
+   Definitions
+      At line 199 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 92 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 170 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+
+
+ARM Macro Assembler    Page 4 Alphabetic symbol ordering
+Relocatable symbols
+
+
+TIMER13_Handler 00000012
+
+Symbol: TIMER13_Handler
+   Definitions
+      At line 211 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 104 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 182 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER14_Handler 00000012
+
+Symbol: TIMER14_Handler
+   Definitions
+      At line 212 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 105 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 183 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER15_Handler 00000012
+
+Symbol: TIMER15_Handler
+   Definitions
+      At line 213 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 106 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 184 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER16_Handler 00000012
+
+Symbol: TIMER16_Handler
+   Definitions
+      At line 214 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 107 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 185 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER20_Handler 00000012
+
+Symbol: TIMER20_Handler
+   Definitions
+      At line 205 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 98 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 176 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER21_Handler 00000012
+
+Symbol: TIMER21_Handler
+   Definitions
+      At line 206 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 99 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 177 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+TIMER30_Handler 00000012
+
+Symbol: TIMER30_Handler
+   Definitions
+
+
+
+ARM Macro Assembler    Page 5 Alphabetic symbol ordering
+Relocatable symbols
+
+      At line 203 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 96 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 174 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+UART0_Handler 00000012
+
+Symbol: UART0_Handler
+   Definitions
+      At line 209 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 102 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 180 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+UART1_Handler 00000012
+
+Symbol: UART1_Handler
+   Definitions
+      At line 210 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 103 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 181 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+USART10_Handler 00000012
+
+Symbol: USART10_Handler
+   Definitions
+      At line 201 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 94 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 172 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+USART11_Handler 00000012
+
+Symbol: USART11_Handler
+   Definitions
+      At line 207 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 100 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 178 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+USART12_Handler 00000012
+
+Symbol: USART12_Handler
+   Definitions
+      At line 216 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 109 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 187 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+USART13_Handler 00000012
+
+Symbol: USART13_Handler
+   Definitions
+      At line 217 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 110 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 188 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+
+
+
+ARM Macro Assembler    Page 6 Alphabetic symbol ordering
+Relocatable symbols
+
+WDT_Handler 00000012
+
+Symbol: WDT_Handler
+   Definitions
+      At line 192 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 85 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 163 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+WT_Handler 00000012
+
+Symbol: WT_Handler
+   Definitions
+      At line 202 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 95 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 173 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+WUT_Handler 00000012
+
+Symbol: WUT_Handler
+   Definitions
+      At line 191 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 84 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+      At line 162 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+
+36 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Absolute symbols
+
+Heap_Size 00000080
+
+Symbol: Heap_Size
+   Definitions
+      At line 46 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 50 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+Comment: Heap_Size used once
+Stack_Size 00000500
+
+Symbol: Stack_Size
+   Definitions
+      At line 35 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 38 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+Comment: Stack_Size used once
+__Vectors_Size 000000B0
+
+Symbol: __Vectors_Size
+   Definitions
+      At line 117 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 63 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+Comment: __Vectors_Size used once
+3 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+External symbols
+
+SystemInit 00000000
+
+Symbol: SystemInit
+   Definitions
+      At line 126 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 128 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+Comment: SystemInit used once
+__main 00000000
+
+Symbol: __main
+   Definitions
+      At line 127 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+   Uses
+      At line 130 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
+Comment: __main used once
+2 symbols
+385 symbols in table
diff --git a/Project/SDK_V2_5_0/Core/cmsis_armcc.h b/Project/SDK_V2_5_0/Core/cmsis_armcc.h
new file mode 100644
index 0000000..74c49c6
--- /dev/null
+++ b/Project/SDK_V2_5_0/Core/cmsis_armcc.h
@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    value  Value to rotate
+  \param [in]    value  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Project/SDK_V2_5_0/Core/core_cm0plus.h b/Project/SDK_V2_5_0/Core/core_cm0plus.h
new file mode 100644
index 0000000..b04aa39
--- /dev/null
+++ b/Project/SDK_V2_5_0/Core/core_cm0plus.h
@@ -0,0 +1,914 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                   /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                   /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Project/SDK_V2_5_0/Core/core_cmfunc.h b/Project/SDK_V2_5_0/Core/core_cmfunc.h
new file mode 100644
index 0000000..652a48a
--- /dev/null
+++ b/Project/SDK_V2_5_0/Core/core_cmfunc.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Project/SDK_V2_5_0/Core/core_cminstr.h b/Project/SDK_V2_5_0/Core/core_cminstr.h
new file mode 100644
index 0000000..f474b0e
--- /dev/null
+++ b/Project/SDK_V2_5_0/Core/core_cminstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Project/SDK_V2_5_0/Debugging_Info/A31G12x.SFR b/Project/SDK_V2_5_0/Debugging_Info/A31G12x.SFR
new file mode 100644
index 0000000..a38538d
Binary files /dev/null and b/Project/SDK_V2_5_0/Debugging_Info/A31G12x.SFR differ
diff --git a/Project/SDK_V2_5_0/Debugging_Info/A31G12x.sfd b/Project/SDK_V2_5_0/Debugging_Info/A31G12x.sfd
new file mode 100644
index 0000000..3bfa9fd
--- /dev/null
+++ b/Project/SDK_V2_5_0/Debugging_Info/A31G12x.sfd
@@ -0,0 +1,63162 @@
+/*
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontroller, but can be equally used for other
+ * suitable processor architectures. This file can be freely distributed.
+ * Modifications to this file shall be clearly marked.
+ * 
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * @file     A31G12x.sfd
+ * @brief    CMSIS-SVD SFD File
+ * @version  1.0
+ * @date     23. July 2020
+ * @note     Generated by SVDConv V3.3.18 on Thursday, 23.07.2020 15:12:47
+ *           from File 'A31G12x.svd',
+ *           last modified on Thursday, 23.07.2020 05:38:08
+ */
+
+
+
+
+// ---------------------------  Register Item Address: INTC_PBTRIG  -------------------------------
+// SVD Line: 117
+
+unsigned int INTC_PBTRIG __AT (0x40001004);
+
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG11  --------------------------------
+// SVD Line: 126
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG11
+//    <name> ITRIG11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 11\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.11..11> ITRIG11
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG10  --------------------------------
+// SVD Line: 144
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG10
+//    <name> ITRIG10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 10\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.10..10> ITRIG10
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG9  ---------------------------------
+// SVD Line: 162
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG9
+//    <name> ITRIG9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 9\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.9..9> ITRIG9
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG8  ---------------------------------
+// SVD Line: 180
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG8
+//    <name> ITRIG8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 8\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.8..8> ITRIG8
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG7  ---------------------------------
+// SVD Line: 198
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG7
+//    <name> ITRIG7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 7\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.7..7> ITRIG7
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG6  ---------------------------------
+// SVD Line: 216
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG6
+//    <name> ITRIG6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 6\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.6..6> ITRIG6
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG5  ---------------------------------
+// SVD Line: 234
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG5
+//    <name> ITRIG5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 5\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.5..5> ITRIG5
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG4  ---------------------------------
+// SVD Line: 252
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG4
+//    <name> ITRIG4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 4\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.4..4> ITRIG4
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG3  ---------------------------------
+// SVD Line: 270
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG3
+//    <name> ITRIG3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 3\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.3..3> ITRIG3
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG2  ---------------------------------
+// SVD Line: 288
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG2
+//    <name> ITRIG2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 2\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.2..2> ITRIG2
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG1  ---------------------------------
+// SVD Line: 306
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG1
+//    <name> ITRIG1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 1\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.1..1> ITRIG1
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBTRIG_ITRIG0  ---------------------------------
+// SVD Line: 324
+
+//  <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG0
+//    <name> ITRIG0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001004) \nPort B Interrupt Trigger Selection 0\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBTRIG ) </loc>
+//      <o.0..0> ITRIG0
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: INTC_PBTRIG  ----------------------------------
+// SVD Line: 117
+
+//  <rtree> SFDITEM_REG__INTC_PBTRIG
+//    <name> PBTRIG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001004) Port B Interrupt Trigger Selection Register </i>
+//    <loc> ( (unsigned int)((INTC_PBTRIG >> 0) & 0xFFFFFFFF), ((INTC_PBTRIG = (INTC_PBTRIG & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG11 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG10 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG9 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG8 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG7 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG6 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG5 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG4 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG3 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG2 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG1 </item>
+//    <item> SFDITEM_FIELD__INTC_PBTRIG_ITRIG0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: INTC_PCTRIG  -------------------------------
+// SVD Line: 344
+
+unsigned int INTC_PCTRIG __AT (0x40001008);
+
+
+
+// -----------------------------  Field Item: INTC_PCTRIG_ITRIG3  ---------------------------------
+// SVD Line: 353
+
+//  <item> SFDITEM_FIELD__INTC_PCTRIG_ITRIG3
+//    <name> ITRIG3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001008) \nPort C Interrupt Trigger Selection 3\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCTRIG ) </loc>
+//      <o.3..3> ITRIG3
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PCTRIG_ITRIG2  ---------------------------------
+// SVD Line: 371
+
+//  <item> SFDITEM_FIELD__INTC_PCTRIG_ITRIG2
+//    <name> ITRIG2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001008) \nPort C Interrupt Trigger Selection 2\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCTRIG ) </loc>
+//      <o.2..2> ITRIG2
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PCTRIG_ITRIG1  ---------------------------------
+// SVD Line: 389
+
+//  <item> SFDITEM_FIELD__INTC_PCTRIG_ITRIG1
+//    <name> ITRIG1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001008) \nPort C Interrupt Trigger Selection 1\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCTRIG ) </loc>
+//      <o.1..1> ITRIG1
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PCTRIG_ITRIG0  ---------------------------------
+// SVD Line: 407
+
+//  <item> SFDITEM_FIELD__INTC_PCTRIG_ITRIG0
+//    <name> ITRIG0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001008) \nPort C Interrupt Trigger Selection 0\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCTRIG ) </loc>
+//      <o.0..0> ITRIG0
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: INTC_PCTRIG  ----------------------------------
+// SVD Line: 344
+
+//  <rtree> SFDITEM_REG__INTC_PCTRIG
+//    <name> PCTRIG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001008) Port C Interrupt Trigger Selection Register </i>
+//    <loc> ( (unsigned int)((INTC_PCTRIG >> 0) & 0xFFFFFFFF), ((INTC_PCTRIG = (INTC_PCTRIG & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PCTRIG_ITRIG3 </item>
+//    <item> SFDITEM_FIELD__INTC_PCTRIG_ITRIG2 </item>
+//    <item> SFDITEM_FIELD__INTC_PCTRIG_ITRIG1 </item>
+//    <item> SFDITEM_FIELD__INTC_PCTRIG_ITRIG0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: INTC_PETRIG  -------------------------------
+// SVD Line: 427
+
+unsigned int INTC_PETRIG __AT (0x40001010);
+
+
+
+// -----------------------------  Field Item: INTC_PETRIG_ITRIG3  ---------------------------------
+// SVD Line: 436
+
+//  <item> SFDITEM_FIELD__INTC_PETRIG_ITRIG3
+//    <name> ITRIG3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001010) \nPort E Interrupt Trigger Selection 3\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PETRIG ) </loc>
+//      <o.3..3> ITRIG3
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PETRIG_ITRIG2  ---------------------------------
+// SVD Line: 454
+
+//  <item> SFDITEM_FIELD__INTC_PETRIG_ITRIG2
+//    <name> ITRIG2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001010) \nPort E Interrupt Trigger Selection 2\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PETRIG ) </loc>
+//      <o.2..2> ITRIG2
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PETRIG_ITRIG1  ---------------------------------
+// SVD Line: 472
+
+//  <item> SFDITEM_FIELD__INTC_PETRIG_ITRIG1
+//    <name> ITRIG1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001010) \nPort E Interrupt Trigger Selection 1\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PETRIG ) </loc>
+//      <o.1..1> ITRIG1
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PETRIG_ITRIG0  ---------------------------------
+// SVD Line: 490
+
+//  <item> SFDITEM_FIELD__INTC_PETRIG_ITRIG0
+//    <name> ITRIG0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001010) \nPort E Interrupt Trigger Selection 0\n0 : Edge = Edge trigger interrupt\n1 : Level = Level trigger interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PETRIG ) </loc>
+//      <o.0..0> ITRIG0
+//        <0=> 0: Edge = Edge trigger interrupt
+//        <1=> 1: Level = Level trigger interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: INTC_PETRIG  ----------------------------------
+// SVD Line: 427
+
+//  <rtree> SFDITEM_REG__INTC_PETRIG
+//    <name> PETRIG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001010) Port E Interrupt Trigger Selection Register </i>
+//    <loc> ( (unsigned int)((INTC_PETRIG >> 0) & 0xFFFFFFFF), ((INTC_PETRIG = (INTC_PETRIG & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PETRIG_ITRIG3 </item>
+//    <item> SFDITEM_FIELD__INTC_PETRIG_ITRIG2 </item>
+//    <item> SFDITEM_FIELD__INTC_PETRIG_ITRIG1 </item>
+//    <item> SFDITEM_FIELD__INTC_PETRIG_ITRIG0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: INTC_PBCR  --------------------------------
+// SVD Line: 510
+
+unsigned int INTC_PBCR __AT (0x40001104);
+
+
+
+// -----------------------------  Field Item: INTC_PBCR_INTCTL11  ---------------------------------
+// SVD Line: 519
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL11
+//    <name> INTCTL11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x40001104) \nPort B Interrupt Control 11\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.23..22> INTCTL11
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBCR_INTCTL10  ---------------------------------
+// SVD Line: 547
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL10
+//    <name> INTCTL10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x40001104) \nPort B Interrupt Control 10\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.21..20> INTCTL10
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL9  ---------------------------------
+// SVD Line: 575
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL9
+//    <name> INTCTL9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x40001104) \nPort B Interrupt Control 9\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.19..18> INTCTL9
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL8  ---------------------------------
+// SVD Line: 603
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL8
+//    <name> INTCTL8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x40001104) \nPort B Interrupt Control 8\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.17..16> INTCTL8
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL7  ---------------------------------
+// SVD Line: 631
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL7
+//    <name> INTCTL7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x40001104) \nPort B Interrupt Control 7\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.15..14> INTCTL7
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL6  ---------------------------------
+// SVD Line: 659
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL6
+//    <name> INTCTL6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40001104) \nPort B Interrupt Control 6\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.13..12> INTCTL6
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL5  ---------------------------------
+// SVD Line: 687
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL5
+//    <name> INTCTL5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x40001104) \nPort B Interrupt Control 5\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.11..10> INTCTL5
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL4  ---------------------------------
+// SVD Line: 715
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL4
+//    <name> INTCTL4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x40001104) \nPort B Interrupt Control 4\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.9..8> INTCTL4
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL3  ---------------------------------
+// SVD Line: 743
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL3
+//    <name> INTCTL3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40001104) \nPort B Interrupt Control 3\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.7..6> INTCTL3
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL2  ---------------------------------
+// SVD Line: 771
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL2
+//    <name> INTCTL2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x40001104) \nPort B Interrupt Control 2\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.5..4> INTCTL2
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL1  ---------------------------------
+// SVD Line: 799
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL1
+//    <name> INTCTL1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x40001104) \nPort B Interrupt Control 1\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.3..2> INTCTL1
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBCR_INTCTL0  ---------------------------------
+// SVD Line: 827
+
+//  <item> SFDITEM_FIELD__INTC_PBCR_INTCTL0
+//    <name> INTCTL0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x40001104) \nPort B Interrupt Control 0\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBCR ) </loc>
+//      <o.1..0> INTCTL0
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: INTC_PBCR  -----------------------------------
+// SVD Line: 510
+
+//  <rtree> SFDITEM_REG__INTC_PBCR
+//    <name> PBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001104) Port B Interrupt Control Register </i>
+//    <loc> ( (unsigned int)((INTC_PBCR >> 0) & 0xFFFFFFFF), ((INTC_PBCR = (INTC_PBCR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL11 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL10 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL9 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL8 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL7 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL6 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL5 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL4 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL3 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL2 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL1 </item>
+//    <item> SFDITEM_FIELD__INTC_PBCR_INTCTL0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: INTC_PCCR  --------------------------------
+// SVD Line: 857
+
+unsigned int INTC_PCCR __AT (0x40001108);
+
+
+
+// ------------------------------  Field Item: INTC_PCCR_INTCTL3  ---------------------------------
+// SVD Line: 866
+
+//  <item> SFDITEM_FIELD__INTC_PCCR_INTCTL3
+//    <name> INTCTL3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40001108) \nPort C Interrupt Control 3\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCCR ) </loc>
+//      <o.7..6> INTCTL3
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PCCR_INTCTL2  ---------------------------------
+// SVD Line: 894
+
+//  <item> SFDITEM_FIELD__INTC_PCCR_INTCTL2
+//    <name> INTCTL2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x40001108) \nPort C Interrupt Control 2\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCCR ) </loc>
+//      <o.5..4> INTCTL2
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PCCR_INTCTL1  ---------------------------------
+// SVD Line: 922
+
+//  <item> SFDITEM_FIELD__INTC_PCCR_INTCTL1
+//    <name> INTCTL1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x40001108) \nPort C Interrupt Control 1\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCCR ) </loc>
+//      <o.3..2> INTCTL1
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PCCR_INTCTL0  ---------------------------------
+// SVD Line: 950
+
+//  <item> SFDITEM_FIELD__INTC_PCCR_INTCTL0
+//    <name> INTCTL0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x40001108) \nPort C Interrupt Control 0\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCCR ) </loc>
+//      <o.1..0> INTCTL0
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: INTC_PCCR  -----------------------------------
+// SVD Line: 857
+
+//  <rtree> SFDITEM_REG__INTC_PCCR
+//    <name> PCCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001108) Port C Interrupt Control Register </i>
+//    <loc> ( (unsigned int)((INTC_PCCR >> 0) & 0xFFFFFFFF), ((INTC_PCCR = (INTC_PCCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PCCR_INTCTL3 </item>
+//    <item> SFDITEM_FIELD__INTC_PCCR_INTCTL2 </item>
+//    <item> SFDITEM_FIELD__INTC_PCCR_INTCTL1 </item>
+//    <item> SFDITEM_FIELD__INTC_PCCR_INTCTL0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: INTC_PECR  --------------------------------
+// SVD Line: 980
+
+unsigned int INTC_PECR __AT (0x40001110);
+
+
+
+// ------------------------------  Field Item: INTC_PECR_INTCTL3  ---------------------------------
+// SVD Line: 989
+
+//  <item> SFDITEM_FIELD__INTC_PECR_INTCTL3
+//    <name> INTCTL3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40001110) \nPort E Interrupt Control 3\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PECR ) </loc>
+//      <o.7..6> INTCTL3
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PECR_INTCTL2  ---------------------------------
+// SVD Line: 1017
+
+//  <item> SFDITEM_FIELD__INTC_PECR_INTCTL2
+//    <name> INTCTL2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x40001110) \nPort E Interrupt Control 2\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PECR ) </loc>
+//      <o.5..4> INTCTL2
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PECR_INTCTL1  ---------------------------------
+// SVD Line: 1045
+
+//  <item> SFDITEM_FIELD__INTC_PECR_INTCTL1
+//    <name> INTCTL1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x40001110) \nPort E Interrupt Control 1\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PECR ) </loc>
+//      <o.3..2> INTCTL1
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PECR_INTCTL0  ---------------------------------
+// SVD Line: 1073
+
+//  <item> SFDITEM_FIELD__INTC_PECR_INTCTL0
+//    <name> INTCTL0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x40001110) \nPort E Interrupt Control 0\n0 : Disable = Disable external interrupt.\n1 : FallingEdgeLowLevel = Interrupt on falling edge or on low level\n2 : RisingEdgeHighLevel = Interrupt on rising edge or on high level\n3 : BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PECR ) </loc>
+//      <o.1..0> INTCTL0
+//        <0=> 0: Disable = Disable external interrupt.
+//        <1=> 1: FallingEdgeLowLevel = Interrupt on falling edge or on low level
+//        <2=> 2: RisingEdgeHighLevel = Interrupt on rising edge or on high level
+//        <3=> 3: BothEdgeNoLevel = Interrupt on both falling and rising edge, No level interrupt
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: INTC_PECR  -----------------------------------
+// SVD Line: 980
+
+//  <rtree> SFDITEM_REG__INTC_PECR
+//    <name> PECR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001110) Port E Interrupt Control Register </i>
+//    <loc> ( (unsigned int)((INTC_PECR >> 0) & 0xFFFFFFFF), ((INTC_PECR = (INTC_PECR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PECR_INTCTL3 </item>
+//    <item> SFDITEM_FIELD__INTC_PECR_INTCTL2 </item>
+//    <item> SFDITEM_FIELD__INTC_PECR_INTCTL1 </item>
+//    <item> SFDITEM_FIELD__INTC_PECR_INTCTL0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: INTC_PBFLAG  -------------------------------
+// SVD Line: 1103
+
+unsigned int INTC_PBFLAG __AT (0x40001204);
+
+
+
+// -----------------------------  Field Item: INTC_PBFLAG_FLAG11  ---------------------------------
+// SVD Line: 1112
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG11
+//    <name> FLAG11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40001204) \nPort B Interrupt Flag 11\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.11..11> FLAG11
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_PBFLAG_FLAG10  ---------------------------------
+// SVD Line: 1130
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG10
+//    <name> FLAG10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40001204) \nPort B Interrupt Flag 10\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.10..10> FLAG10
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG9  ---------------------------------
+// SVD Line: 1148
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG9
+//    <name> FLAG9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40001204) \nPort B Interrupt Flag 9\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.9..9> FLAG9
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG8  ---------------------------------
+// SVD Line: 1166
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG8
+//    <name> FLAG8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40001204) \nPort B Interrupt Flag 8\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.8..8> FLAG8
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG7  ---------------------------------
+// SVD Line: 1184
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG7
+//    <name> FLAG7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40001204) \nPort B Interrupt Flag 7\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.7..7> FLAG7
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG6  ---------------------------------
+// SVD Line: 1202
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG6
+//    <name> FLAG6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40001204) \nPort B Interrupt Flag 6\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.6..6> FLAG6
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG5  ---------------------------------
+// SVD Line: 1220
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG5
+//    <name> FLAG5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40001204) \nPort B Interrupt Flag 5\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.5..5> FLAG5
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG4  ---------------------------------
+// SVD Line: 1238
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG4
+//    <name> FLAG4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40001204) \nPort B Interrupt Flag 4\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.4..4> FLAG4
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG3  ---------------------------------
+// SVD Line: 1256
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG3
+//    <name> FLAG3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001204) \nPort B Interrupt Flag 3\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.3..3> FLAG3
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG2  ---------------------------------
+// SVD Line: 1274
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG2
+//    <name> FLAG2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001204) \nPort B Interrupt Flag 2\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.2..2> FLAG2
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG1  ---------------------------------
+// SVD Line: 1292
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG1
+//    <name> FLAG1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001204) \nPort B Interrupt Flag 1\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.1..1> FLAG1
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PBFLAG_FLAG0  ---------------------------------
+// SVD Line: 1310
+
+//  <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG0
+//    <name> FLAG0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001204) \nPort B Interrupt Flag 0\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PBFLAG ) </loc>
+//      <o.0..0> FLAG0
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: INTC_PBFLAG  ----------------------------------
+// SVD Line: 1103
+
+//  <rtree> SFDITEM_REG__INTC_PBFLAG
+//    <name> PBFLAG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001204) Port B Interrupt Flag Register </i>
+//    <loc> ( (unsigned int)((INTC_PBFLAG >> 0) & 0xFFFFFFFF), ((INTC_PBFLAG = (INTC_PBFLAG & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG11 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG10 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG9 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG8 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG7 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG6 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG5 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG4 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG3 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG2 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG1 </item>
+//    <item> SFDITEM_FIELD__INTC_PBFLAG_FLAG0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: INTC_PCFLAG  -------------------------------
+// SVD Line: 1330
+
+unsigned int INTC_PCFLAG __AT (0x40001208);
+
+
+
+// ------------------------------  Field Item: INTC_PCFLAG_FLAG3  ---------------------------------
+// SVD Line: 1339
+
+//  <item> SFDITEM_FIELD__INTC_PCFLAG_FLAG3
+//    <name> FLAG3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001208) \nPort C Interrupt Flag 3\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCFLAG ) </loc>
+//      <o.3..3> FLAG3
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PCFLAG_FLAG2  ---------------------------------
+// SVD Line: 1357
+
+//  <item> SFDITEM_FIELD__INTC_PCFLAG_FLAG2
+//    <name> FLAG2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001208) \nPort C Interrupt Flag 2\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCFLAG ) </loc>
+//      <o.2..2> FLAG2
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PCFLAG_FLAG1  ---------------------------------
+// SVD Line: 1375
+
+//  <item> SFDITEM_FIELD__INTC_PCFLAG_FLAG1
+//    <name> FLAG1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001208) \nPort C Interrupt Flag 1\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCFLAG ) </loc>
+//      <o.1..1> FLAG1
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PCFLAG_FLAG0  ---------------------------------
+// SVD Line: 1393
+
+//  <item> SFDITEM_FIELD__INTC_PCFLAG_FLAG0
+//    <name> FLAG0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001208) \nPort C Interrupt Flag 0\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PCFLAG ) </loc>
+//      <o.0..0> FLAG0
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: INTC_PCFLAG  ----------------------------------
+// SVD Line: 1330
+
+//  <rtree> SFDITEM_REG__INTC_PCFLAG
+//    <name> PCFLAG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001208) Port C Interrupt Flag Register </i>
+//    <loc> ( (unsigned int)((INTC_PCFLAG >> 0) & 0xFFFFFFFF), ((INTC_PCFLAG = (INTC_PCFLAG & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PCFLAG_FLAG3 </item>
+//    <item> SFDITEM_FIELD__INTC_PCFLAG_FLAG2 </item>
+//    <item> SFDITEM_FIELD__INTC_PCFLAG_FLAG1 </item>
+//    <item> SFDITEM_FIELD__INTC_PCFLAG_FLAG0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: INTC_PEFLAG  -------------------------------
+// SVD Line: 1413
+
+unsigned int INTC_PEFLAG __AT (0x40001210);
+
+
+
+// ------------------------------  Field Item: INTC_PEFLAG_FLAG3  ---------------------------------
+// SVD Line: 1422
+
+//  <item> SFDITEM_FIELD__INTC_PEFLAG_FLAG3
+//    <name> FLAG3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001210) \nPort E Interrupt Flag 3\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PEFLAG ) </loc>
+//      <o.3..3> FLAG3
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PEFLAG_FLAG2  ---------------------------------
+// SVD Line: 1440
+
+//  <item> SFDITEM_FIELD__INTC_PEFLAG_FLAG2
+//    <name> FLAG2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001210) \nPort E Interrupt Flag 2\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PEFLAG ) </loc>
+//      <o.2..2> FLAG2
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PEFLAG_FLAG1  ---------------------------------
+// SVD Line: 1458
+
+//  <item> SFDITEM_FIELD__INTC_PEFLAG_FLAG1
+//    <name> FLAG1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001210) \nPort E Interrupt Flag 1\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PEFLAG ) </loc>
+//      <o.1..1> FLAG1
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: INTC_PEFLAG_FLAG0  ---------------------------------
+// SVD Line: 1476
+
+//  <item> SFDITEM_FIELD__INTC_PEFLAG_FLAG0
+//    <name> FLAG0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001210) \nPort E Interrupt Flag 0\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_PEFLAG ) </loc>
+//      <o.0..0> FLAG0
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: INTC_PEFLAG  ----------------------------------
+// SVD Line: 1413
+
+//  <rtree> SFDITEM_REG__INTC_PEFLAG
+//    <name> PEFLAG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001210) Port E Interrupt Flag Register </i>
+//    <loc> ( (unsigned int)((INTC_PEFLAG >> 0) & 0xFFFFFFFF), ((INTC_PEFLAG = (INTC_PEFLAG & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_PEFLAG_FLAG3 </item>
+//    <item> SFDITEM_FIELD__INTC_PEFLAG_FLAG2 </item>
+//    <item> SFDITEM_FIELD__INTC_PEFLAG_FLAG1 </item>
+//    <item> SFDITEM_FIELD__INTC_PEFLAG_FLAG0 </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: INTC_EINT0CONF1  -----------------------------
+// SVD Line: 1496
+
+unsigned int INTC_EINT0CONF1 __AT (0x40001300);
+
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF1_CONF7  -------------------------------
+// SVD Line: 1505
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF7
+//    <name> CONF7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x40001300) \nExternal Interrupt 0 Configuration 7\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF1 ) </loc>
+//      <o.31..28> CONF7
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF1_CONF6  -------------------------------
+// SVD Line: 1543
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF6
+//    <name> CONF6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x40001300) \nExternal Interrupt 0 Configuration 6\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF1 ) </loc>
+//      <o.27..24> CONF6
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF1_CONF5  -------------------------------
+// SVD Line: 1581
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF5
+//    <name> CONF5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x40001300) \nExternal Interrupt 0 Configuration 5\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF1 ) </loc>
+//      <o.23..20> CONF5
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF1_CONF4  -------------------------------
+// SVD Line: 1619
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF4
+//    <name> CONF4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x40001300) \nExternal Interrupt 0 Configuration 4\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF1 ) </loc>
+//      <o.19..16> CONF4
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF1_CONF3  -------------------------------
+// SVD Line: 1657
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF3
+//    <name> CONF3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x40001300) \nExternal Interrupt 0 Configuration 3\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF1 ) </loc>
+//      <o.15..12> CONF3
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF1_CONF2  -------------------------------
+// SVD Line: 1695
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF2
+//    <name> CONF2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x40001300) \nExternal Interrupt 0 Configuration 2\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF1 ) </loc>
+//      <o.11..8> CONF2
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF1_CONF1  -------------------------------
+// SVD Line: 1733
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF1
+//    <name> CONF1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x40001300) \nExternal Interrupt 0 Configuration 1\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF1 ) </loc>
+//      <o.7..4> CONF1
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF1_CONF0  -------------------------------
+// SVD Line: 1771
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF0
+//    <name> CONF0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40001300) \nExternal Interrupt 0 Configuration 0\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF1 ) </loc>
+//      <o.3..0> CONF0
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: INTC_EINT0CONF1  --------------------------------
+// SVD Line: 1496
+
+//  <rtree> SFDITEM_REG__INTC_EINT0CONF1
+//    <name> EINT0CONF1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001300) External Interrupt 0 Configuration Register 1 </i>
+//    <loc> ( (unsigned int)((INTC_EINT0CONF1 >> 0) & 0xFFFFFFFF), ((INTC_EINT0CONF1 = (INTC_EINT0CONF1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF7 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF6 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF5 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF4 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF3 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF2 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF1 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF1_CONF0 </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: INTC_EINT1CONF1  -----------------------------
+// SVD Line: 1811
+
+unsigned int INTC_EINT1CONF1 __AT (0x40001304);
+
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF1_CONF7  -------------------------------
+// SVD Line: 1820
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF7
+//    <name> CONF7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x40001304) \nExternal Interrupt 1 Configuration 7\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF1 ) </loc>
+//      <o.31..28> CONF7
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF1_CONF6  -------------------------------
+// SVD Line: 1858
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF6
+//    <name> CONF6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x40001304) \nExternal Interrupt 1 Configuration 6\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF1 ) </loc>
+//      <o.27..24> CONF6
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF1_CONF5  -------------------------------
+// SVD Line: 1896
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF5
+//    <name> CONF5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x40001304) \nExternal Interrupt 1 Configuration 5\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF1 ) </loc>
+//      <o.23..20> CONF5
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF1_CONF4  -------------------------------
+// SVD Line: 1934
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF4
+//    <name> CONF4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x40001304) \nExternal Interrupt 1 Configuration 4\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF1 ) </loc>
+//      <o.19..16> CONF4
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF1_CONF3  -------------------------------
+// SVD Line: 1972
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF3
+//    <name> CONF3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x40001304) \nExternal Interrupt 1 Configuration 3\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF1 ) </loc>
+//      <o.15..12> CONF3
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF1_CONF2  -------------------------------
+// SVD Line: 2010
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF2
+//    <name> CONF2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x40001304) \nExternal Interrupt 1 Configuration 2\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF1 ) </loc>
+//      <o.11..8> CONF2
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF1_CONF1  -------------------------------
+// SVD Line: 2048
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF1
+//    <name> CONF1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x40001304) \nExternal Interrupt 1 Configuration 1\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF1 ) </loc>
+//      <o.7..4> CONF1
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF1_CONF0  -------------------------------
+// SVD Line: 2086
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF0
+//    <name> CONF0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40001304) \nExternal Interrupt 1 Configuration 0\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF1 ) </loc>
+//      <o.3..0> CONF0
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: INTC_EINT1CONF1  --------------------------------
+// SVD Line: 1811
+
+//  <rtree> SFDITEM_REG__INTC_EINT1CONF1
+//    <name> EINT1CONF1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001304) External Interrupt 1 Configuration Register 1 </i>
+//    <loc> ( (unsigned int)((INTC_EINT1CONF1 >> 0) & 0xFFFFFFFF), ((INTC_EINT1CONF1 = (INTC_EINT1CONF1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF7 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF6 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF5 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF4 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF3 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF2 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF1 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF1_CONF0 </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: INTC_EINT2CONF1  -----------------------------
+// SVD Line: 2126
+
+unsigned int INTC_EINT2CONF1 __AT (0x40001308);
+
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF1_CONF7  -------------------------------
+// SVD Line: 2135
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF7
+//    <name> CONF7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x40001308) \nExternal Interrupt 2 Configuration 7\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF1 ) </loc>
+//      <o.31..28> CONF7
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF1_CONF6  -------------------------------
+// SVD Line: 2173
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF6
+//    <name> CONF6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x40001308) \nExternal Interrupt 2 Configuration 6\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF1 ) </loc>
+//      <o.27..24> CONF6
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF1_CONF5  -------------------------------
+// SVD Line: 2211
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF5
+//    <name> CONF5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x40001308) \nExternal Interrupt 2 Configuration 5\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF1 ) </loc>
+//      <o.23..20> CONF5
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF1_CONF4  -------------------------------
+// SVD Line: 2249
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF4
+//    <name> CONF4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x40001308) \nExternal Interrupt 2 Configuration 4\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF1 ) </loc>
+//      <o.19..16> CONF4
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF1_CONF3  -------------------------------
+// SVD Line: 2287
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF3
+//    <name> CONF3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x40001308) \nExternal Interrupt 2 Configuration 3\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF1 ) </loc>
+//      <o.15..12> CONF3
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF1_CONF2  -------------------------------
+// SVD Line: 2325
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF2
+//    <name> CONF2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x40001308) \nExternal Interrupt 2 Configuration 2\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF1 ) </loc>
+//      <o.11..8> CONF2
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF1_CONF1  -------------------------------
+// SVD Line: 2363
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF1
+//    <name> CONF1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x40001308) \nExternal Interrupt 2 Configuration 1\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF1 ) </loc>
+//      <o.7..4> CONF1
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF1_CONF0  -------------------------------
+// SVD Line: 2401
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF0
+//    <name> CONF0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40001308) \nExternal Interrupt 2 Configuration 0\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF1 ) </loc>
+//      <o.3..0> CONF0
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: INTC_EINT2CONF1  --------------------------------
+// SVD Line: 2126
+
+//  <rtree> SFDITEM_REG__INTC_EINT2CONF1
+//    <name> EINT2CONF1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001308) External Interrupt 2 Configuration Register 1 </i>
+//    <loc> ( (unsigned int)((INTC_EINT2CONF1 >> 0) & 0xFFFFFFFF), ((INTC_EINT2CONF1 = (INTC_EINT2CONF1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF7 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF6 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF5 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF4 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF3 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF2 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF1 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF1_CONF0 </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: INTC_EINT3CONF1  -----------------------------
+// SVD Line: 2441
+
+unsigned int INTC_EINT3CONF1 __AT (0x4000130C);
+
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF1_CONF7  -------------------------------
+// SVD Line: 2450
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF7
+//    <name> CONF7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x4000130C) \nExternal Interrupt 3 Configuration 7\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF1 ) </loc>
+//      <o.31..28> CONF7
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF1_CONF6  -------------------------------
+// SVD Line: 2488
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF6
+//    <name> CONF6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x4000130C) \nExternal Interrupt 3 Configuration 6\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF1 ) </loc>
+//      <o.27..24> CONF6
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF1_CONF5  -------------------------------
+// SVD Line: 2526
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF5
+//    <name> CONF5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x4000130C) \nExternal Interrupt 3 Configuration 5\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF1 ) </loc>
+//      <o.23..20> CONF5
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF1_CONF4  -------------------------------
+// SVD Line: 2564
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF4
+//    <name> CONF4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x4000130C) \nExternal Interrupt 3 Configuration 4\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF1 ) </loc>
+//      <o.19..16> CONF4
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF1_CONF3  -------------------------------
+// SVD Line: 2602
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF3
+//    <name> CONF3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x4000130C) \nExternal Interrupt 3 Configuration 3\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF1 ) </loc>
+//      <o.15..12> CONF3
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF1_CONF2  -------------------------------
+// SVD Line: 2640
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF2
+//    <name> CONF2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x4000130C) \nExternal Interrupt 3 Configuration 2\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF1 ) </loc>
+//      <o.11..8> CONF2
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF1_CONF1  -------------------------------
+// SVD Line: 2678
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF1
+//    <name> CONF1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x4000130C) \nExternal Interrupt 3 Configuration 1\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF1 ) </loc>
+//      <o.7..4> CONF1
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF1_CONF0  -------------------------------
+// SVD Line: 2716
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF0
+//    <name> CONF0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x4000130C) \nExternal Interrupt 3 Configuration 0\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF1 ) </loc>
+//      <o.3..0> CONF0
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: INTC_EINT3CONF1  --------------------------------
+// SVD Line: 2441
+
+//  <rtree> SFDITEM_REG__INTC_EINT3CONF1
+//    <name> EINT3CONF1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000130C) External Interrupt 3 Configuration Register 1 </i>
+//    <loc> ( (unsigned int)((INTC_EINT3CONF1 >> 0) & 0xFFFFFFFF), ((INTC_EINT3CONF1 = (INTC_EINT3CONF1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF7 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF6 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF5 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF4 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF3 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF2 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF1 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF1_CONF0 </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: INTC_EINT0CONF2  -----------------------------
+// SVD Line: 2756
+
+unsigned int INTC_EINT0CONF2 __AT (0x40001310);
+
+
+
+// ---------------------------  Field Item: INTC_EINT0CONF2_CONF11  -------------------------------
+// SVD Line: 2765
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF2_CONF11
+//    <name> CONF11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x40001310) \nExternal Interrupt 0 Configuration 11\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF2 ) </loc>
+//      <o.15..12> CONF11
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_EINT0CONF2_CONF10  -------------------------------
+// SVD Line: 2803
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF2_CONF10
+//    <name> CONF10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x40001310) \nExternal Interrupt 0 Configuration 10\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF2 ) </loc>
+//      <o.11..8> CONF10
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF2_CONF9  -------------------------------
+// SVD Line: 2841
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF2_CONF9
+//    <name> CONF9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x40001310) \nExternal Interrupt 0 Configuration 9\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF2 ) </loc>
+//      <o.7..4> CONF9
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT0CONF2_CONF8  -------------------------------
+// SVD Line: 2879
+
+//  <item> SFDITEM_FIELD__INTC_EINT0CONF2_CONF8
+//    <name> CONF8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40001310) \nExternal Interrupt 0 Configuration 8\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT0CONF2 ) </loc>
+//      <o.3..0> CONF8
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: INTC_EINT0CONF2  --------------------------------
+// SVD Line: 2756
+
+//  <rtree> SFDITEM_REG__INTC_EINT0CONF2
+//    <name> EINT0CONF2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001310) External Interrupt 0 Configuration Register 2 </i>
+//    <loc> ( (unsigned int)((INTC_EINT0CONF2 >> 0) & 0xFFFFFFFF), ((INTC_EINT0CONF2 = (INTC_EINT0CONF2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF2_CONF11 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF2_CONF10 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF2_CONF9 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT0CONF2_CONF8 </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: INTC_EINT1CONF2  -----------------------------
+// SVD Line: 2919
+
+unsigned int INTC_EINT1CONF2 __AT (0x40001314);
+
+
+
+// ---------------------------  Field Item: INTC_EINT1CONF2_CONF11  -------------------------------
+// SVD Line: 2928
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF2_CONF11
+//    <name> CONF11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x40001314) \nExternal Interrupt 1 Configuration 11\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF2 ) </loc>
+//      <o.15..12> CONF11
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_EINT1CONF2_CONF10  -------------------------------
+// SVD Line: 2966
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF2_CONF10
+//    <name> CONF10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x40001314) \nExternal Interrupt 1 Configuration 10\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF2 ) </loc>
+//      <o.11..8> CONF10
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF2_CONF9  -------------------------------
+// SVD Line: 3004
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF2_CONF9
+//    <name> CONF9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x40001314) \nExternal Interrupt 1 Configuration 9\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF2 ) </loc>
+//      <o.7..4> CONF9
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT1CONF2_CONF8  -------------------------------
+// SVD Line: 3042
+
+//  <item> SFDITEM_FIELD__INTC_EINT1CONF2_CONF8
+//    <name> CONF8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40001314) \nExternal Interrupt 1 Configuration 8\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT1CONF2 ) </loc>
+//      <o.3..0> CONF8
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: INTC_EINT1CONF2  --------------------------------
+// SVD Line: 2919
+
+//  <rtree> SFDITEM_REG__INTC_EINT1CONF2
+//    <name> EINT1CONF2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001314) External Interrupt 1 Configuration Register 2 </i>
+//    <loc> ( (unsigned int)((INTC_EINT1CONF2 >> 0) & 0xFFFFFFFF), ((INTC_EINT1CONF2 = (INTC_EINT1CONF2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF2_CONF11 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF2_CONF10 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF2_CONF9 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT1CONF2_CONF8 </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: INTC_EINT2CONF2  -----------------------------
+// SVD Line: 3082
+
+unsigned int INTC_EINT2CONF2 __AT (0x40001318);
+
+
+
+// ---------------------------  Field Item: INTC_EINT2CONF2_CONF11  -------------------------------
+// SVD Line: 3091
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF2_CONF11
+//    <name> CONF11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x40001318) \nExternal Interrupt 2 Configuration 11\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF2 ) </loc>
+//      <o.15..12> CONF11
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_EINT2CONF2_CONF10  -------------------------------
+// SVD Line: 3129
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF2_CONF10
+//    <name> CONF10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x40001318) \nExternal Interrupt 2 Configuration 10\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF2 ) </loc>
+//      <o.11..8> CONF10
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF2_CONF9  -------------------------------
+// SVD Line: 3167
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF2_CONF9
+//    <name> CONF9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x40001318) \nExternal Interrupt 2 Configuration 9\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF2 ) </loc>
+//      <o.7..4> CONF9
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT2CONF2_CONF8  -------------------------------
+// SVD Line: 3205
+
+//  <item> SFDITEM_FIELD__INTC_EINT2CONF2_CONF8
+//    <name> CONF8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40001318) \nExternal Interrupt 2 Configuration 8\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT2CONF2 ) </loc>
+//      <o.3..0> CONF8
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: INTC_EINT2CONF2  --------------------------------
+// SVD Line: 3082
+
+//  <rtree> SFDITEM_REG__INTC_EINT2CONF2
+//    <name> EINT2CONF2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001318) External Interrupt 2 Configuration Register 2 </i>
+//    <loc> ( (unsigned int)((INTC_EINT2CONF2 >> 0) & 0xFFFFFFFF), ((INTC_EINT2CONF2 = (INTC_EINT2CONF2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF2_CONF11 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF2_CONF10 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF2_CONF9 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT2CONF2_CONF8 </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: INTC_EINT3CONF2  -----------------------------
+// SVD Line: 3245
+
+unsigned int INTC_EINT3CONF2 __AT (0x4000131C);
+
+
+
+// ---------------------------  Field Item: INTC_EINT3CONF2_CONF11  -------------------------------
+// SVD Line: 3254
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF2_CONF11
+//    <name> CONF11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x4000131C) \nExternal Interrupt 3 Configuration 11\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF2 ) </loc>
+//      <o.15..12> CONF11
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_EINT3CONF2_CONF10  -------------------------------
+// SVD Line: 3292
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF2_CONF10
+//    <name> CONF10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x4000131C) \nExternal Interrupt 3 Configuration 10\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF2 ) </loc>
+//      <o.11..8> CONF10
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF2_CONF9  -------------------------------
+// SVD Line: 3330
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF2_CONF9
+//    <name> CONF9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x4000131C) \nExternal Interrupt 3 Configuration 9\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF2 ) </loc>
+//      <o.7..4> CONF9
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_EINT3CONF2_CONF8  -------------------------------
+// SVD Line: 3368
+
+//  <item> SFDITEM_FIELD__INTC_EINT3CONF2_CONF8
+//    <name> CONF8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x4000131C) \nExternal Interrupt 3 Configuration 8\n0 : PA = Select PA.\n1 : PB = Select PB.\n2 : PC = Select PC.\n3 : PD = Select PD.\n4 : PE = Select PE.\n5 : PF = Select PF.\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_EINT3CONF2 ) </loc>
+//      <o.3..0> CONF8
+//        <0=> 0: PA = Select PA.
+//        <1=> 1: PB = Select PB.
+//        <2=> 2: PC = Select PC.
+//        <3=> 3: PD = Select PD.
+//        <4=> 4: PE = Select PE.
+//        <5=> 5: PF = Select PF.
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: INTC_EINT3CONF2  --------------------------------
+// SVD Line: 3245
+
+//  <rtree> SFDITEM_REG__INTC_EINT3CONF2
+//    <name> EINT3CONF2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000131C) External Interrupt 3 Configuration Register 2 </i>
+//    <loc> ( (unsigned int)((INTC_EINT3CONF2 >> 0) & 0xFFFFFFFF), ((INTC_EINT3CONF2 = (INTC_EINT3CONF2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF2_CONF11 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF2_CONF10 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF2_CONF9 </item>
+//    <item> SFDITEM_FIELD__INTC_EINT3CONF2_CONF8 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: INTC_MSK  --------------------------------
+// SVD Line: 3408
+
+unsigned int INTC_MSK __AT (0x40001400);
+
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK31_NULL  --------------------------------
+// SVD Line: 3417
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK31_NULL
+//    <name> IMSK31_NULL </name>
+//    <rw> 
+//    <i> [Bit 31] RW (@ 0x40001400) \nInterrupt Source Mask 31 (RSVD)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.31..31> IMSK31_NULL
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK30_NULL  --------------------------------
+// SVD Line: 3435
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK30_NULL
+//    <name> IMSK30_NULL </name>
+//    <rw> 
+//    <i> [Bit 30] RW (@ 0x40001400) \nInterrupt Source Mask 30 (RSVD)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.30..30> IMSK30_NULL
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK29_NULL  --------------------------------
+// SVD Line: 3453
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK29_NULL
+//    <name> IMSK29_NULL </name>
+//    <rw> 
+//    <i> [Bit 29] RW (@ 0x40001400) \nInterrupt Source Mask 29 (RSVD)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.29..29> IMSK29_NULL
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK28_NULL  --------------------------------
+// SVD Line: 3471
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK28_NULL
+//    <name> IMSK28_NULL </name>
+//    <rw> 
+//    <i> [Bit 28] RW (@ 0x40001400) \nInterrupt Source Mask 28 (RSVD)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.28..28> IMSK28_NULL
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK27_USART13  ------------------------------
+// SVD Line: 3489
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK27_USART13
+//    <name> IMSK27_USART13 </name>
+//    <rw> 
+//    <i> [Bit 27] RW (@ 0x40001400) \nInterrupt Source Mask 27 (USART13)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.27..27> IMSK27_USART13
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK26_USART12  ------------------------------
+// SVD Line: 3507
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK26_USART12
+//    <name> IMSK26_USART12 </name>
+//    <rw> 
+//    <i> [Bit 26] RW (@ 0x40001400) \nInterrupt Source Mask 26 (USART12)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.26..26> IMSK26_USART12
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK25_I2C2  --------------------------------
+// SVD Line: 3525
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK25_I2C2
+//    <name> IMSK25_I2C2 </name>
+//    <rw> 
+//    <i> [Bit 25] RW (@ 0x40001400) \nInterrupt Source Mask 25 (I2C2)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.25..25> IMSK25_I2C2
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK24_TIMER16  ------------------------------
+// SVD Line: 3543
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK24_TIMER16
+//    <name> IMSK24_TIMER16 </name>
+//    <rw> 
+//    <i> [Bit 24] RW (@ 0x40001400) \nInterrupt Source Mask 24 (TIMER16)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.24..24> IMSK24_TIMER16
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK23_TIMER15  ------------------------------
+// SVD Line: 3561
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK23_TIMER15
+//    <name> IMSK23_TIMER15 </name>
+//    <rw> 
+//    <i> [Bit 23] RW (@ 0x40001400) \nInterrupt Source Mask 23 (TIMER15)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.23..23> IMSK23_TIMER15
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK22_TIMER14  ------------------------------
+// SVD Line: 3579
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK22_TIMER14
+//    <name> IMSK22_TIMER14 </name>
+//    <rw> 
+//    <i> [Bit 22] RW (@ 0x40001400) \nInterrupt Source Mask 22 (TIMER14)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.22..22> IMSK22_TIMER14
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK21_TIMER13  ------------------------------
+// SVD Line: 3597
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK21_TIMER13
+//    <name> IMSK21_TIMER13 </name>
+//    <rw> 
+//    <i> [Bit 21] RW (@ 0x40001400) \nInterrupt Source Mask 21 (TIMER13)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.21..21> IMSK21_TIMER13
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK20_UART1  -------------------------------
+// SVD Line: 3615
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK20_UART1
+//    <name> IMSK20_UART1 </name>
+//    <rw> 
+//    <i> [Bit 20] RW (@ 0x40001400) \nInterrupt Source Mask 20 (UART1)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.20..20> IMSK20_UART1
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK19_UART0  -------------------------------
+// SVD Line: 3633
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK19_UART0
+//    <name> IMSK19_UART0 </name>
+//    <rw> 
+//    <i> [Bit 19] RW (@ 0x40001400) \nInterrupt Source Mask 19 (UART0)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.19..19> IMSK19_UART0
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_MSK_IMSK18_ADC  --------------------------------
+// SVD Line: 3651
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK18_ADC
+//    <name> IMSK18_ADC </name>
+//    <rw> 
+//    <i> [Bit 18] RW (@ 0x40001400) \nInterrupt Source Mask 18 (ADC)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.18..18> IMSK18_ADC
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK17_USART11  ------------------------------
+// SVD Line: 3669
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK17_USART11
+//    <name> IMSK17_USART11 </name>
+//    <rw> 
+//    <i> [Bit 17] RW (@ 0x40001400) \nInterrupt Source Mask 17 (USART11)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.17..17> IMSK17_USART11
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK16_TIMER21  ------------------------------
+// SVD Line: 3687
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK16_TIMER21
+//    <name> IMSK16_TIMER21 </name>
+//    <rw> 
+//    <i> [Bit 16] RW (@ 0x40001400) \nInterrupt Source Mask 16 (TIMER21)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.16..16> IMSK16_TIMER21
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK15_TIMER20  ------------------------------
+// SVD Line: 3705
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK15_TIMER20
+//    <name> IMSK15_TIMER20 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40001400) \nInterrupt Source Mask 15 (TIMER20)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.15..15> IMSK15_TIMER20
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK14_I2C1  --------------------------------
+// SVD Line: 3723
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK14_I2C1
+//    <name> IMSK14_I2C1 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40001400) \nInterrupt Source Mask 14 (I2C1)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.14..14> IMSK14_I2C1
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK13_TIMER30  ------------------------------
+// SVD Line: 3741
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK13_TIMER30
+//    <name> IMSK13_TIMER30 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x40001400) \nInterrupt Source Mask 13 (TIMER30)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.13..13> IMSK13_TIMER30
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_MSK_IMSK12_WT  ---------------------------------
+// SVD Line: 3759
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK12_WT
+//    <name> IMSK12_WT </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x40001400) \nInterrupt Source Mask 12 (WT)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.12..12> IMSK12_WT
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK11_USART10  ------------------------------
+// SVD Line: 3777
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK11_USART10
+//    <name> IMSK11_USART10 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40001400) \nInterrupt Source Mask 11 (USART10)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.11..11> IMSK11_USART10
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK10_I2C0  --------------------------------
+// SVD Line: 3795
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK10_I2C0
+//    <name> IMSK10_I2C0 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40001400) \nInterrupt Source Mask 10 (I2C0)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.10..10> IMSK10_I2C0
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK9_TIMER12  -------------------------------
+// SVD Line: 3813
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK9_TIMER12
+//    <name> IMSK9_TIMER12 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40001400) \nInterrupt Source Mask 9 (TIMER12)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.9..9> IMSK9_TIMER12
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK8_TIMER11  -------------------------------
+// SVD Line: 3831
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK8_TIMER11
+//    <name> IMSK8_TIMER11 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40001400) \nInterrupt Source Mask 8 (TIMER11)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.8..8> IMSK8_TIMER11
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: INTC_MSK_IMSK7_TIMER10  -------------------------------
+// SVD Line: 3849
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK7_TIMER10
+//    <name> IMSK7_TIMER10 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40001400) \nInterrupt Source Mask 7 (TIMER10)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.7..7> IMSK7_TIMER10
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK6_EINT3  --------------------------------
+// SVD Line: 3867
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK6_EINT3
+//    <name> IMSK6_EINT3 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40001400) \nInterrupt Source Mask 6 (EINT3)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.6..6> IMSK6_EINT3
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK5_EINT2  --------------------------------
+// SVD Line: 3885
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK5_EINT2
+//    <name> IMSK5_EINT2 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40001400) \nInterrupt Source Mask 5 (EINT2)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.5..5> IMSK5_EINT2
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK4_EINT1  --------------------------------
+// SVD Line: 3903
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK4_EINT1
+//    <name> IMSK4_EINT1 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40001400) \nInterrupt Source Mask 4 (EINT1)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.4..4> IMSK4_EINT1
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: INTC_MSK_IMSK3_EINT0  --------------------------------
+// SVD Line: 3921
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK3_EINT0
+//    <name> IMSK3_EINT0 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001400) \nInterrupt Source Mask 3 (EINT0)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.3..3> IMSK3_EINT0
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_MSK_IMSK2_WDT  ---------------------------------
+// SVD Line: 3939
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK2_WDT
+//    <name> IMSK2_WDT </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001400) \nInterrupt Source Mask 2 (WDT)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.2..2> IMSK2_WDT
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_MSK_IMSK1_WUT  ---------------------------------
+// SVD Line: 3957
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK1_WUT
+//    <name> IMSK1_WUT </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001400) \nInterrupt Source Mask 1 (WUT)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.1..1> IMSK1_WUT
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: INTC_MSK_IMSK0_LVI  ---------------------------------
+// SVD Line: 3975
+
+//  <item> SFDITEM_FIELD__INTC_MSK_IMSK0_LVI
+//    <name> IMSK0_LVI </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001400) \nInterrupt Source Mask 0 (LVI)\n0 : Mask = Mask Interrupt Source\n1 : Unmask = Unmask Interrupt Source </i>
+//    <combo> 
+//      <loc> ( (unsigned int) INTC_MSK ) </loc>
+//      <o.0..0> IMSK0_LVI
+//        <0=> 0: Mask = Mask Interrupt Source
+//        <1=> 1: Unmask = Unmask Interrupt Source
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: INTC_MSK  ------------------------------------
+// SVD Line: 3408
+
+//  <rtree> SFDITEM_REG__INTC_MSK
+//    <name> MSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001400) Interrupt Source Mask Register </i>
+//    <loc> ( (unsigned int)((INTC_MSK >> 0) & 0xFFFFFFFF), ((INTC_MSK = (INTC_MSK & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK31_NULL </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK30_NULL </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK29_NULL </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK28_NULL </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK27_USART13 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK26_USART12 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK25_I2C2 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK24_TIMER16 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK23_TIMER15 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK22_TIMER14 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK21_TIMER13 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK20_UART1 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK19_UART0 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK18_ADC </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK17_USART11 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK16_TIMER21 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK15_TIMER20 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK14_I2C1 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK13_TIMER30 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK12_WT </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK11_USART10 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK10_I2C0 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK9_TIMER12 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK8_TIMER11 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK7_TIMER10 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK6_EINT3 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK5_EINT2 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK4_EINT1 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK3_EINT0 </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK2_WDT </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK1_WUT </item>
+//    <item> SFDITEM_FIELD__INTC_MSK_IMSK0_LVI </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: INTC  -------------------------------------
+// SVD Line: 83
+
+//  <view> INTC
+//    <name> INTC </name>
+//    <item> SFDITEM_REG__INTC_PBTRIG </item>
+//    <item> SFDITEM_REG__INTC_PCTRIG </item>
+//    <item> SFDITEM_REG__INTC_PETRIG </item>
+//    <item> SFDITEM_REG__INTC_PBCR </item>
+//    <item> SFDITEM_REG__INTC_PCCR </item>
+//    <item> SFDITEM_REG__INTC_PECR </item>
+//    <item> SFDITEM_REG__INTC_PBFLAG </item>
+//    <item> SFDITEM_REG__INTC_PCFLAG </item>
+//    <item> SFDITEM_REG__INTC_PEFLAG </item>
+//    <item> SFDITEM_REG__INTC_EINT0CONF1 </item>
+//    <item> SFDITEM_REG__INTC_EINT1CONF1 </item>
+//    <item> SFDITEM_REG__INTC_EINT2CONF1 </item>
+//    <item> SFDITEM_REG__INTC_EINT3CONF1 </item>
+//    <item> SFDITEM_REG__INTC_EINT0CONF2 </item>
+//    <item> SFDITEM_REG__INTC_EINT1CONF2 </item>
+//    <item> SFDITEM_REG__INTC_EINT2CONF2 </item>
+//    <item> SFDITEM_REG__INTC_EINT3CONF2 </item>
+//    <item> SFDITEM_REG__INTC_MSK </item>
+//  </view>
+//  
+
+
+// --------------------------  Register Item Address: SCUCC_VENDORID  -----------------------------
+// SVD Line: 4016
+
+unsigned int SCUCC_VENDORID __AT (0x4000F000);
+
+
+
+// ----------------------------  Field Item: SCUCC_VENDORID_VENDID  -------------------------------
+// SVD Line: 4025
+
+//  <item> SFDITEM_FIELD__SCUCC_VENDORID_VENDID
+//    <name> VENDID </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000F000) Vendor Identification </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((SCUCC_VENDORID >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: SCUCC_VENDORID  ---------------------------------
+// SVD Line: 4016
+
+//  <rtree> SFDITEM_REG__SCUCC_VENDORID
+//    <name> VENDORID </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000F000) Vendor Identification Register </i>
+//    <loc> ( (unsigned int)((SCUCC_VENDORID >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_VENDORID_VENDID </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCC_CHIPID  ------------------------------
+// SVD Line: 4033
+
+unsigned int SCUCC_CHIPID __AT (0x4000F004);
+
+
+
+// -----------------------------  Field Item: SCUCC_CHIPID_CHIPID  --------------------------------
+// SVD Line: 4042
+
+//  <item> SFDITEM_FIELD__SCUCC_CHIPID_CHIPID
+//    <name> CHIPID </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000F004) Chip Identification </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((SCUCC_CHIPID >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCC_CHIPID  ----------------------------------
+// SVD Line: 4033
+
+//  <rtree> SFDITEM_REG__SCUCC_CHIPID
+//    <name> CHIPID </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000F004) Chip Identification Register </i>
+//    <loc> ( (unsigned int)((SCUCC_CHIPID >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_CHIPID_CHIPID </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCC_REVNR  -------------------------------
+// SVD Line: 4050
+
+unsigned int SCUCC_REVNR __AT (0x4000F008);
+
+
+
+// ------------------------------  Field Item: SCUCC_REVNR_REVNO  ---------------------------------
+// SVD Line: 4059
+
+//  <item> SFDITEM_FIELD__SCUCC_REVNR_REVNO
+//    <name> REVNO </name>
+//    <r> 
+//    <i> [Bits 7..0] RO (@ 0x4000F008) Chip Revision Number </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_REVNR >> 0) & 0xFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: SCUCC_REVNR  ----------------------------------
+// SVD Line: 4050
+
+//  <rtree> SFDITEM_REG__SCUCC_REVNR
+//    <name> REVNR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000F008) Revision Number Register </i>
+//    <loc> ( (unsigned int)((SCUCC_REVNR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_REVNR_REVNO </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCC_PMREMAP  ------------------------------
+// SVD Line: 4067
+
+unsigned int SCUCC_PMREMAP __AT (0x4000F014);
+
+
+
+// ----------------------------  Field Item: SCUCC_PMREMAP_WTIDKY  --------------------------------
+// SVD Line: 4076
+
+//  <item> SFDITEM_FIELD__SCUCC_PMREMAP_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x4000F014) Write Identification Key (0xe2f1) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((SCUCC_PMREMAP >> 16) & 0x0), ((SCUCC_PMREMAP = (SCUCC_PMREMAP & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCC_PMREMAP_nPMREM  --------------------------------
+// SVD Line: 4089
+
+//  <item> SFDITEM_FIELD__SCUCC_PMREMAP_nPMREM
+//    <name> nPMREM </name>
+//    <w> 
+//    <i> [Bits 15..8] WO (@ 0x4000F014) Write Complement Key </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_PMREMAP >> 8) & 0x0), ((SCUCC_PMREMAP = (SCUCC_PMREMAP & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_PMREMAP_PMREM  --------------------------------
+// SVD Line: 4107
+
+//  <item> SFDITEM_FIELD__SCUCC_PMREMAP_PMREM
+//    <name> PMREM </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x4000F014) Program Memory Remap </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_PMREMAP >> 0) & 0xFF), ((SCUCC_PMREMAP = (SCUCC_PMREMAP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCC_PMREMAP  ---------------------------------
+// SVD Line: 4067
+
+//  <rtree> SFDITEM_REG__SCUCC_PMREMAP
+//    <name> PMREMAP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000F014) Program Memory Remap Register </i>
+//    <loc> ( (unsigned int)((SCUCC_PMREMAP >> 0) & 0xFFFFFFFF), ((SCUCC_PMREMAP = (SCUCC_PMREMAP & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_PMREMAP_WTIDKY </item>
+//    <item> SFDITEM_FIELD__SCUCC_PMREMAP_nPMREM </item>
+//    <item> SFDITEM_FIELD__SCUCC_PMREMAP_PMREM </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCC_BTPSCR  ------------------------------
+// SVD Line: 4127
+
+unsigned int SCUCC_BTPSCR __AT (0x4000F018);
+
+
+
+// -----------------------------  Field Item: SCUCC_BTPSCR_BFIND  ---------------------------------
+// SVD Line: 4136
+
+//  <item> SFDITEM_FIELD__SCUCC_BTPSCR_BFIND
+//    <name> BFIND </name>
+//    <rw> 
+//    <i> [Bits 6..5] RW (@ 0x4000F018) \nBOOT Pin Function Indicator\n0 : Reserved - do not use\n1 : Reserved - do not use\n2 : PORorEXTR = Check the BOOT pin when a system reset occurs by nRESET including POR.\n3 : POR = Check the BOOT pin when a system reset occurs only by POR. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_BTPSCR ) </loc>
+//      <o.6..5> BFIND
+//        <0=> 0: 
+//        <1=> 1: 
+//        <2=> 2: PORorEXTR = Check the BOOT pin when a system reset occurs by nRESET including POR.
+//        <3=> 3: POR = Check the BOOT pin when a system reset occurs only by POR.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_BTPSCR_BTPSTA  --------------------------------
+// SVD Line: 4154
+
+//  <item> SFDITEM_FIELD__SCUCC_BTPSCR_BTPSTA
+//    <name> BTPSTA </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x4000F018) \nBOOT Pin Status\n0 : Low = The BOOT pin is low level.\n1 : High = The BOOT pin is high level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_BTPSCR ) </loc>
+//      <o.0..0> BTPSTA
+//        <0=> 0: Low = The BOOT pin is low level.
+//        <1=> 1: High = The BOOT pin is high level.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCC_BTPSCR  ----------------------------------
+// SVD Line: 4127
+
+//  <rtree> SFDITEM_REG__SCUCC_BTPSCR
+//    <name> BTPSCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000F018) Boot Pin Status and Control Register </i>
+//    <loc> ( (unsigned int)((SCUCC_BTPSCR >> 0) & 0xFFFFFFFF), ((SCUCC_BTPSCR = (SCUCC_BTPSCR & ~(0x60UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x60) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_BTPSCR_BFIND </item>
+//    <item> SFDITEM_FIELD__SCUCC_BTPSCR_BTPSTA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCC_RSTSSR  ------------------------------
+// SVD Line: 4174
+
+unsigned int SCUCC_RSTSSR __AT (0x4000F01C);
+
+
+
+// -----------------------------  Field Item: SCUCC_RSTSSR_MONSTA  --------------------------------
+// SVD Line: 4183
+
+//  <item> SFDITEM_FIELD__SCUCC_RSTSSR_MONSTA
+//    <name> MONSTA </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x4000F01C) \nClock Monitoring Reset Status\n0 : NotDetected = Not detected.\n1 : Detected = CMR was detected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_RSTSSR ) </loc>
+//      <o.5..5> MONSTA
+//        <0=> 0: NotDetected = Not detected.
+//        <1=> 1: Detected = CMR was detected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_RSTSSR_SWSTA  ---------------------------------
+// SVD Line: 4201
+
+//  <item> SFDITEM_FIELD__SCUCC_RSTSSR_SWSTA
+//    <name> SWSTA </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x4000F01C) \nSoftware Reset Status\n0 : NotDetected = Not detected.\n1 : Detected = SWR was detected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_RSTSSR ) </loc>
+//      <o.4..4> SWSTA
+//        <0=> 0: NotDetected = Not detected.
+//        <1=> 1: Detected = SWR was detected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_RSTSSR_EXTSTA  --------------------------------
+// SVD Line: 4219
+
+//  <item> SFDITEM_FIELD__SCUCC_RSTSSR_EXTSTA
+//    <name> EXTSTA </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x4000F01C) \nExternal Pin Reset Status\n0 : NotDetected = Not detected.\n1 : Detected = EXTR was detected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_RSTSSR ) </loc>
+//      <o.3..3> EXTSTA
+//        <0=> 0: NotDetected = Not detected.
+//        <1=> 1: Detected = EXTR was detected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_RSTSSR_WDTSTA  --------------------------------
+// SVD Line: 4237
+
+//  <item> SFDITEM_FIELD__SCUCC_RSTSSR_WDTSTA
+//    <name> WDTSTA </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x4000F01C) \nWatch-Dog Timer Reset Status\n0 : NotDetected = Not detected.\n1 : Detected = WDTR was detected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_RSTSSR ) </loc>
+//      <o.2..2> WDTSTA
+//        <0=> 0: NotDetected = Not detected.
+//        <1=> 1: Detected = WDTR was detected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_RSTSSR_LVRSTA  --------------------------------
+// SVD Line: 4255
+
+//  <item> SFDITEM_FIELD__SCUCC_RSTSSR_LVRSTA
+//    <name> LVRSTA </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x4000F01C) \nLVR Reset Status\n0 : NotDetected = Not detected.\n1 : Detected = LVR was detected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_RSTSSR ) </loc>
+//      <o.1..1> LVRSTA
+//        <0=> 0: NotDetected = Not detected.
+//        <1=> 1: Detected = LVR was detected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_RSTSSR_PORSTA  --------------------------------
+// SVD Line: 4273
+
+//  <item> SFDITEM_FIELD__SCUCC_RSTSSR_PORSTA
+//    <name> PORSTA </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x4000F01C) \nPOR Reset Status\n0 : NotDetected = Not detected.\n1 : Detected = POR was detected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_RSTSSR ) </loc>
+//      <o.0..0> PORSTA
+//        <0=> 0: NotDetected = Not detected.
+//        <1=> 1: Detected = POR was detected.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCC_RSTSSR  ----------------------------------
+// SVD Line: 4174
+
+//  <rtree> SFDITEM_REG__SCUCC_RSTSSR
+//    <name> RSTSSR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000F01C) Reset Source Status Register </i>
+//    <loc> ( (unsigned int)((SCUCC_RSTSSR >> 0) & 0xFFFFFFFF), ((SCUCC_RSTSSR = (SCUCC_RSTSSR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_RSTSSR_MONSTA </item>
+//    <item> SFDITEM_FIELD__SCUCC_RSTSSR_SWSTA </item>
+//    <item> SFDITEM_FIELD__SCUCC_RSTSSR_EXTSTA </item>
+//    <item> SFDITEM_FIELD__SCUCC_RSTSSR_WDTSTA </item>
+//    <item> SFDITEM_FIELD__SCUCC_RSTSSR_LVRSTA </item>
+//    <item> SFDITEM_FIELD__SCUCC_RSTSSR_PORSTA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCC_NMISRCR  ------------------------------
+// SVD Line: 4293
+
+unsigned int SCUCC_NMISRCR __AT (0x4000F020);
+
+
+
+// ----------------------------  Field Item: SCUCC_NMISRCR_NMICON  --------------------------------
+// SVD Line: 4302
+
+//  <item> SFDITEM_FIELD__SCUCC_NMISRCR_NMICON
+//    <name> NMICON </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x4000F020) \nNon-Maskable Interrupt (NMI) Control\n0 : Disable = Disable NMI.\n1 : Enable = Enable NMI. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_NMISRCR ) </loc>
+//      <o.7..7> NMICON
+//        <0=> 0: Disable = Disable NMI.
+//        <1=> 1: Enable = Enable NMI.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCC_NMISRCR_MONINT  --------------------------------
+// SVD Line: 4320
+
+//  <item> SFDITEM_FIELD__SCUCC_NMISRCR_MONINT
+//    <name> MONINT </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x4000F020) \nClock Monitoring Interrupt Selection\n0 : NotSelect = Non-select clock monitoring interrupt for NMI source.\n1 : Select = Select clock monitoring interrupt for NMI source. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_NMISRCR ) </loc>
+//      <o.6..6> MONINT
+//        <0=> 0: NotSelect = Non-select clock monitoring interrupt for NMI source.
+//        <1=> 1: Select = Select clock monitoring interrupt for NMI source.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCC_NMISRCR_NMISRC  --------------------------------
+// SVD Line: 4338
+
+//  <item> SFDITEM_FIELD__SCUCC_NMISRCR_NMISRC
+//    <name> NMISRC </name>
+//    <rw> 
+//    <i> [Bits 4..0] RW (@ 0x4000F020) Non-Maskable Interrupt Source Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_NMISRCR >> 0) & 0x1F), ((SCUCC_NMISRCR = (SCUCC_NMISRCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCC_NMISRCR  ---------------------------------
+// SVD Line: 4293
+
+//  <rtree> SFDITEM_REG__SCUCC_NMISRCR
+//    <name> NMISRCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000F020) NMI Source Selection Register </i>
+//    <loc> ( (unsigned int)((SCUCC_NMISRCR >> 0) & 0xFFFFFFFF), ((SCUCC_NMISRCR = (SCUCC_NMISRCR & ~(0xDFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_NMISRCR_NMICON </item>
+//    <item> SFDITEM_FIELD__SCUCC_NMISRCR_MONINT </item>
+//    <item> SFDITEM_FIELD__SCUCC_NMISRCR_NMISRC </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCC_SWRSTR  ------------------------------
+// SVD Line: 4346
+
+unsigned int SCUCC_SWRSTR __AT (0x4000F024);
+
+
+
+// -----------------------------  Field Item: SCUCC_SWRSTR_WTIDKY  --------------------------------
+// SVD Line: 4355
+
+//  <item> SFDITEM_FIELD__SCUCC_SWRSTR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x4000F024) Write Identification Key (0x9eb3) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((SCUCC_SWRSTR >> 16) & 0x0), ((SCUCC_SWRSTR = (SCUCC_SWRSTR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_SWRSTR_SWRST  ---------------------------------
+// SVD Line: 4368
+
+//  <item> SFDITEM_FIELD__SCUCC_SWRSTR_SWRST
+//    <name> SWRST </name>
+//    <w> 
+//    <i> [Bits 7..0] WO (@ 0x4000F024) Software Reset (System Reset) </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_SWRSTR >> 0) & 0x0), ((SCUCC_SWRSTR = (SCUCC_SWRSTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCC_SWRSTR  ----------------------------------
+// SVD Line: 4346
+
+//  <rtree> SFDITEM_REG__SCUCC_SWRSTR
+//    <name> SWRSTR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x4000F024) Software Reset Register </i>
+//    <loc> ( (unsigned int)((SCUCC_SWRSTR >> 0) & 0xFFFFFFFF), ((SCUCC_SWRSTR = (SCUCC_SWRSTR & ~(0xFFFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF00FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_SWRSTR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__SCUCC_SWRSTR_SWRST </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCC_SRSTVR  ------------------------------
+// SVD Line: 4388
+
+unsigned int SCUCC_SRSTVR __AT (0x4000F028);
+
+
+
+// -----------------------------  Field Item: SCUCC_SRSTVR_VALID  ---------------------------------
+// SVD Line: 4397
+
+//  <item> SFDITEM_FIELD__SCUCC_SRSTVR_VALID
+//    <name> VALID </name>
+//    <r> 
+//    <i> [Bits 7..0] RO (@ 0x4000F028) System Reset Validation </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_SRSTVR >> 0) & 0xFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCC_SRSTVR  ----------------------------------
+// SVD Line: 4388
+
+//  <rtree> SFDITEM_REG__SCUCC_SRSTVR
+//    <name> SRSTVR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000F028) System Reset Validation Register </i>
+//    <loc> ( (unsigned int)((SCUCC_SRSTVR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_SRSTVR_VALID </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCC_WUTCR  -------------------------------
+// SVD Line: 4405
+
+unsigned int SCUCC_WUTCR __AT (0x4000F02C);
+
+
+
+// -----------------------------  Field Item: SCUCC_WUTCR_WUTIEN  ---------------------------------
+// SVD Line: 4414
+
+//  <item> SFDITEM_FIELD__SCUCC_WUTCR_WUTIEN
+//    <name> WUTIEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x4000F02C) \nWake-Up Timer Interrupt Enable\n0 : Disable = Disable Wake-Up Timer interrupt.\n1 : Enable = Enable Wake-Up Timer interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_WUTCR ) </loc>
+//      <o.7..7> WUTIEN
+//        <0=> 0: Disable = Disable Wake-Up Timer interrupt.
+//        <1=> 1: Enable = Enable Wake-Up Timer interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_WUTCR_CNTRLD  ---------------------------------
+// SVD Line: 4432
+
+//  <item> SFDITEM_FIELD__SCUCC_WUTCR_CNTRLD
+//    <name> CNTRLD </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x4000F02C) \nCounter Reload\n0 : NoEffect = No effect.\n1 : Reload = Reload data to counter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_WUTCR ) </loc>
+//      <o.1..1> CNTRLD
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Reload = Reload data to counter.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCC_WUTCR_WUTIFLAG  --------------------------------
+// SVD Line: 4450
+
+//  <item> SFDITEM_FIELD__SCUCC_WUTCR_WUTIFLAG
+//    <name> WUTIFLAG </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x4000F02C) \nWake-Up Timer Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCC_WUTCR ) </loc>
+//      <o.0..0> WUTIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: SCUCC_WUTCR  ----------------------------------
+// SVD Line: 4405
+
+//  <rtree> SFDITEM_REG__SCUCC_WUTCR
+//    <name> WUTCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000F02C) Wake-Up Timer Control Register </i>
+//    <loc> ( (unsigned int)((SCUCC_WUTCR >> 0) & 0xFFFFFFFF), ((SCUCC_WUTCR = (SCUCC_WUTCR & ~(0x83UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x83) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_WUTCR_WUTIEN </item>
+//    <item> SFDITEM_FIELD__SCUCC_WUTCR_CNTRLD </item>
+//    <item> SFDITEM_FIELD__SCUCC_WUTCR_WUTIFLAG </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCC_WUTDR  -------------------------------
+// SVD Line: 4470
+
+unsigned int SCUCC_WUTDR __AT (0x4000F030);
+
+
+
+// -----------------------------  Field Item: SCUCC_WUTDR_WUTDATA  --------------------------------
+// SVD Line: 4479
+
+//  <item> SFDITEM_FIELD__SCUCC_WUTDR_WUTDATA
+//    <name> WUTDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x4000F030) Wake-Up Timer Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((SCUCC_WUTDR >> 0) & 0xFFFF), ((SCUCC_WUTDR = (SCUCC_WUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: SCUCC_WUTDR  ----------------------------------
+// SVD Line: 4470
+
+//  <rtree> SFDITEM_REG__SCUCC_WUTDR
+//    <name> WUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000F030) Wake-Up Timer Data Register </i>
+//    <loc> ( (unsigned int)((SCUCC_WUTDR >> 0) & 0xFFFFFFFF), ((SCUCC_WUTDR = (SCUCC_WUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_WUTDR_WUTDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCC_HIRCTRM  ------------------------------
+// SVD Line: 4487
+
+unsigned int SCUCC_HIRCTRM __AT (0x4000F0A8);
+
+
+
+// ----------------------------  Field Item: SCUCC_HIRCTRM_WTIDKY  --------------------------------
+// SVD Line: 4496
+
+//  <item> SFDITEM_FIELD__SCUCC_HIRCTRM_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x4000F0A8) Write Identification Key (0xa6b5) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((SCUCC_HIRCTRM >> 16) & 0x0), ((SCUCC_HIRCTRM = (SCUCC_HIRCTRM & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_HIRCTRM_nTRMH  --------------------------------
+// SVD Line: 4509
+
+//  <item> SFDITEM_FIELD__SCUCC_HIRCTRM_nTRMH
+//    <name> nTRMH </name>
+//    <w> 
+//    <i> [Bits 15..8] WO (@ 0x4000F0A8) Write Complement Key </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_HIRCTRM >> 8) & 0x0), ((SCUCC_HIRCTRM = (SCUCC_HIRCTRM & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_HIRCTRM_CTRMH  --------------------------------
+// SVD Line: 4515
+
+//  <item> SFDITEM_FIELD__SCUCC_HIRCTRM_CTRMH
+//    <name> CTRMH </name>
+//    <r> 
+//    <i> [Bits 7..5] RO (@ 0x4000F0A8) Factory HIRC Coarse Trim </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_HIRCTRM >> 5) & 0x7) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCC_HIRCTRM_FTRMH  --------------------------------
+// SVD Line: 4521
+
+//  <item> SFDITEM_FIELD__SCUCC_HIRCTRM_FTRMH
+//    <name> FTRMH </name>
+//    <rw> 
+//    <i> [Bits 4..0] RW (@ 0x4000F0A8) Factory HIRC Fine Trim </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_HIRCTRM >> 0) & 0x1F), ((SCUCC_HIRCTRM = (SCUCC_HIRCTRM & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCC_HIRCTRM  ---------------------------------
+// SVD Line: 4487
+
+//  <rtree> SFDITEM_REG__SCUCC_HIRCTRM
+//    <name> HIRCTRM </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000F0A8) High Frequency Internal RC Trim Register (HIRCNFIG) </i>
+//    <loc> ( (unsigned int)((SCUCC_HIRCTRM >> 0) & 0xFFFFFFFF), ((SCUCC_HIRCTRM = (SCUCC_HIRCTRM & ~(0xFFFFFF1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF1F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_HIRCTRM_WTIDKY </item>
+//    <item> SFDITEM_FIELD__SCUCC_HIRCTRM_nTRMH </item>
+//    <item> SFDITEM_FIELD__SCUCC_HIRCTRM_CTRMH </item>
+//    <item> SFDITEM_FIELD__SCUCC_HIRCTRM_FTRMH </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCC_WDTRCTRM  -----------------------------
+// SVD Line: 4529
+
+unsigned int SCUCC_WDTRCTRM __AT (0x4000F0AC);
+
+
+
+// ----------------------------  Field Item: SCUCC_WDTRCTRM_WTIDKY  -------------------------------
+// SVD Line: 4538
+
+//  <item> SFDITEM_FIELD__SCUCC_WDTRCTRM_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x4000F0AC) Write Identification Key (0x4c3d) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((SCUCC_WDTRCTRM >> 16) & 0x0), ((SCUCC_WDTRCTRM = (SCUCC_WDTRCTRM & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCC_WDTRCTRM_nTRMW  --------------------------------
+// SVD Line: 4551
+
+//  <item> SFDITEM_FIELD__SCUCC_WDTRCTRM_nTRMW
+//    <name> nTRMW </name>
+//    <w> 
+//    <i> [Bits 15..8] WO (@ 0x4000F0AC) Write Complement Key </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_WDTRCTRM >> 8) & 0x0), ((SCUCC_WDTRCTRM = (SCUCC_WDTRCTRM & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCC_WDTRCTRM_CTRMW  --------------------------------
+// SVD Line: 4557
+
+//  <item> SFDITEM_FIELD__SCUCC_WDTRCTRM_CTRMW
+//    <name> CTRMW </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x4000F0AC) Factory WDTRC Coarse Trim </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_WDTRCTRM >> 4) & 0xF), ((SCUCC_WDTRCTRM = (SCUCC_WDTRCTRM & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCC_WDTRCTRM_FTRMW  --------------------------------
+// SVD Line: 4563
+
+//  <item> SFDITEM_FIELD__SCUCC_WDTRCTRM_FTRMW
+//    <name> FTRMW </name>
+//    <rw> 
+//    <i> [Bits 2..0] RW (@ 0x4000F0AC) Factory WDTRC Fine Trim </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCUCC_WDTRCTRM >> 0) & 0x7), ((SCUCC_WDTRCTRM = (SCUCC_WDTRCTRM & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: SCUCC_WDTRCTRM  ---------------------------------
+// SVD Line: 4529
+
+//  <rtree> SFDITEM_REG__SCUCC_WDTRCTRM
+//    <name> WDTRCTRM </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000F0AC) Watch-Dog Timer RC Trim Register (WDTRCNFIG) </i>
+//    <loc> ( (unsigned int)((SCUCC_WDTRCTRM >> 0) & 0xFFFFFFFF), ((SCUCC_WDTRCTRM = (SCUCC_WDTRCTRM & ~(0xFFFFFFF7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFF7) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCC_WDTRCTRM_WTIDKY </item>
+//    <item> SFDITEM_FIELD__SCUCC_WDTRCTRM_nTRMW </item>
+//    <item> SFDITEM_FIELD__SCUCC_WDTRCTRM_CTRMW </item>
+//    <item> SFDITEM_FIELD__SCUCC_WDTRCTRM_FTRMW </item>
+//  </rtree>
+//  
+
+
+// ---------------------------------  Peripheral View: SCUCC  -------------------------------------
+// SVD Line: 3997
+
+//  <view> SCUCC
+//    <name> SCUCC </name>
+//    <item> SFDITEM_REG__SCUCC_VENDORID </item>
+//    <item> SFDITEM_REG__SCUCC_CHIPID </item>
+//    <item> SFDITEM_REG__SCUCC_REVNR </item>
+//    <item> SFDITEM_REG__SCUCC_PMREMAP </item>
+//    <item> SFDITEM_REG__SCUCC_BTPSCR </item>
+//    <item> SFDITEM_REG__SCUCC_RSTSSR </item>
+//    <item> SFDITEM_REG__SCUCC_NMISRCR </item>
+//    <item> SFDITEM_REG__SCUCC_SWRSTR </item>
+//    <item> SFDITEM_REG__SCUCC_SRSTVR </item>
+//    <item> SFDITEM_REG__SCUCC_WUTCR </item>
+//    <item> SFDITEM_REG__SCUCC_WUTDR </item>
+//    <item> SFDITEM_REG__SCUCC_HIRCTRM </item>
+//    <item> SFDITEM_REG__SCUCC_WDTRCTRM </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: SCUCG_SCCR  -------------------------------
+// SVD Line: 4587
+
+unsigned int SCUCG_SCCR __AT (0x40001800);
+
+
+
+// ------------------------------  Field Item: SCUCG_SCCR_WTIDKY  ---------------------------------
+// SVD Line: 4596
+
+//  <item> SFDITEM_FIELD__SCUCG_SCCR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x40001800) Write Identification Key (0x570a) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((SCUCG_SCCR >> 16) & 0x0), ((SCUCG_SCCR = (SCUCG_SCCR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_SCCR_MCLKSEL  ---------------------------------
+// SVD Line: 4609
+
+//  <item> SFDITEM_FIELD__SCUCG_SCCR_MCLKSEL
+//    <name> MCLKSEL </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x40001800) \nMain Clock Selection, MCLK\n0 : HIRC = High Frequency Internal RC Oscillator (40MHz), HIRC\n1 : XMOSC = External Main Oscillator (2 - 40MHz), XMOSC\n2 : XSOSC = External Sub Oscillator (32.768kHz), XSOSC\n3 : WDTRC = Internal Watch-Dog Timer RC Oscillator (40kHz), WDTRC </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_SCCR ) </loc>
+//      <o.1..0> MCLKSEL
+//        <0=> 0: HIRC = High Frequency Internal RC Oscillator (40MHz), HIRC
+//        <1=> 1: XMOSC = External Main Oscillator (2 - 40MHz), XMOSC
+//        <2=> 2: XSOSC = External Sub Oscillator (32.768kHz), XSOSC
+//        <3=> 3: WDTRC = Internal Watch-Dog Timer RC Oscillator (40kHz), WDTRC
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: SCUCG_SCCR  -----------------------------------
+// SVD Line: 4587
+
+//  <rtree> SFDITEM_REG__SCUCG_SCCR
+//    <name> SCCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001800) System Clock Control Register </i>
+//    <loc> ( (unsigned int)((SCUCG_SCCR >> 0) & 0xFFFFFFFF), ((SCUCG_SCCR = (SCUCG_SCCR & ~(0xFFFF0003UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0003) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_SCCR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__SCUCG_SCCR_MCLKSEL </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCG_CLKSRCR  ------------------------------
+// SVD Line: 4639
+
+unsigned int SCUCG_CLKSRCR __AT (0x40001804);
+
+
+
+// ----------------------------  Field Item: SCUCG_CLKSRCR_WTIDKY  --------------------------------
+// SVD Line: 4648
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKSRCR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x40001804) Write Identification Key (0xa507) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((SCUCG_CLKSRCR >> 16) & 0x0), ((SCUCG_CLKSRCR = (SCUCG_CLKSRCR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CLKSRCR_HIRCSEL  -------------------------------
+// SVD Line: 4661
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKSRCR_HIRCSEL
+//    <name> HIRCSEL </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40001804) \nHIRC Frequency Selection\n0 : HIRC1 = 40MHz HIRC\n1 : HIRC2 = 20MHz HIRC\n2 : HIRC4 = 10MHz HIRC\n3 : HIRC8 = 5MHz HIRC </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKSRCR ) </loc>
+//      <o.13..12> HIRCSEL
+//        <0=> 0: HIRC1 = 40MHz HIRC
+//        <1=> 1: HIRC2 = 20MHz HIRC
+//        <2=> 2: HIRC4 = 10MHz HIRC
+//        <3=> 3: HIRC8 = 5MHz HIRC
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CLKSRCR_XMFRNG  --------------------------------
+// SVD Line: 4689
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKSRCR_XMFRNG
+//    <name> XMFRNG </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40001804) \nMain Oscillator Type and Frequency Range Selection\n0 : Xtal = X-tal for XMOSC, 2 to 16MHz\n1 : Clock = External Clock for XMOSC, 2MHz to 40MHz </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKSRCR ) </loc>
+//      <o.8..8> XMFRNG
+//        <0=> 0: Xtal = X-tal for XMOSC, 2 to 16MHz
+//        <1=> 1: Clock = External Clock for XMOSC, 2MHz to 40MHz
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CLKSRCR_WDTRCEN  -------------------------------
+// SVD Line: 4707
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKSRCR_WDTRCEN
+//    <name> WDTRCEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001804) \nWDTRC Enable\n0 : Disable = Disable WDTRC.\n1 : Enable = Enable WDTRC. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKSRCR ) </loc>
+//      <o.3..3> WDTRCEN
+//        <0=> 0: Disable = Disable WDTRC.
+//        <1=> 1: Enable = Enable WDTRC.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CLKSRCR_HIRCEN  --------------------------------
+// SVD Line: 4725
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKSRCR_HIRCEN
+//    <name> HIRCEN </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001804) \nHIRC Enable\n0 : Disable = Disable HIRC.\n1 : Enable = Enable HIRC. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKSRCR ) </loc>
+//      <o.2..2> HIRCEN
+//        <0=> 0: Disable = Disable HIRC.
+//        <1=> 1: Enable = Enable HIRC.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CLKSRCR_XMOSCEN  -------------------------------
+// SVD Line: 4743
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKSRCR_XMOSCEN
+//    <name> XMOSCEN </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001804) \nXMOSC Enable\n0 : Disable = Disable XMOSC.\n1 : Enable = Enable XMOSC. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKSRCR ) </loc>
+//      <o.1..1> XMOSCEN
+//        <0=> 0: Disable = Disable XMOSC.
+//        <1=> 1: Enable = Enable XMOSC.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CLKSRCR_XSOSCEN  -------------------------------
+// SVD Line: 4761
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKSRCR_XSOSCEN
+//    <name> XSOSCEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001804) \nXSOSC Enable\n0 : Disable = Disable XSOSC.\n1 : Enable = Enable XSOSC. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKSRCR ) </loc>
+//      <o.0..0> XSOSCEN
+//        <0=> 0: Disable = Disable XSOSC.
+//        <1=> 1: Enable = Enable XSOSC.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_CLKSRCR  ---------------------------------
+// SVD Line: 4639
+
+//  <rtree> SFDITEM_REG__SCUCG_CLKSRCR
+//    <name> CLKSRCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001804) Clock Source Control Register </i>
+//    <loc> ( (unsigned int)((SCUCG_CLKSRCR >> 0) & 0xFFFFFFFF), ((SCUCG_CLKSRCR = (SCUCG_CLKSRCR & ~(0xFFFF310FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF310F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_CLKSRCR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKSRCR_HIRCSEL </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKSRCR_XMFRNG </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKSRCR_WDTRCEN </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKSRCR_HIRCEN </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKSRCR_XMOSCEN </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKSRCR_XSOSCEN </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCG_SCDIVR1  ------------------------------
+// SVD Line: 4781
+
+unsigned int SCUCG_SCDIVR1 __AT (0x40001808);
+
+
+
+// -----------------------------  Field Item: SCUCG_SCDIVR1_WLDIV  --------------------------------
+// SVD Line: 4790
+
+//  <item> SFDITEM_FIELD__SCUCG_SCDIVR1_WLDIV
+//    <name> WLDIV </name>
+//    <rw> 
+//    <i> [Bits 6..4] RW (@ 0x40001808) \nClock Divide for Watch Timer and LCD Driver, Divider 2\n0 : MCLK64 = MCLK/64\n1 : MCLK128 = MCLK/128\n2 : MCLK256 = MCLK/256\n3 : MCLK512 = MCLK/512\n4 : MCLK1024 = MCLK/1024\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_SCDIVR1 ) </loc>
+//      <o.6..4> WLDIV
+//        <0=> 0: MCLK64 = MCLK/64
+//        <1=> 1: MCLK128 = MCLK/128
+//        <2=> 2: MCLK256 = MCLK/256
+//        <3=> 3: MCLK512 = MCLK/512
+//        <4=> 4: MCLK1024 = MCLK/1024
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_SCDIVR1_HDIV  ---------------------------------
+// SVD Line: 4823
+
+//  <item> SFDITEM_FIELD__SCUCG_SCDIVR1_HDIV
+//    <name> HDIV </name>
+//    <rw> 
+//    <i> [Bits 2..0] RW (@ 0x40001808) \nClock Divide for HCLK, Divider 0\n0 : MCLK16 = MCLK/16\n1 : MCLK8 = MCLK/8\n2 : MCLK4 = MCLK/4\n3 : MCLK2 = MCLK/2\n4 : MCLK1 = MCLK/1\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_SCDIVR1 ) </loc>
+//      <o.2..0> HDIV
+//        <0=> 0: MCLK16 = MCLK/16
+//        <1=> 1: MCLK8 = MCLK/8
+//        <2=> 2: MCLK4 = MCLK/4
+//        <3=> 3: MCLK2 = MCLK/2
+//        <4=> 4: MCLK1 = MCLK/1
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_SCDIVR1  ---------------------------------
+// SVD Line: 4781
+
+//  <rtree> SFDITEM_REG__SCUCG_SCDIVR1
+//    <name> SCDIVR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001808) System Clock Divide Register 1 </i>
+//    <loc> ( (unsigned int)((SCUCG_SCDIVR1 >> 0) & 0xFFFFFFFF), ((SCUCG_SCDIVR1 = (SCUCG_SCDIVR1 & ~(0x77UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x77) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_SCDIVR1_WLDIV </item>
+//    <item> SFDITEM_FIELD__SCUCG_SCDIVR1_HDIV </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCG_SCDIVR2  ------------------------------
+// SVD Line: 4858
+
+unsigned int SCUCG_SCDIVR2 __AT (0x4000180C);
+
+
+
+// ----------------------------  Field Item: SCUCG_SCDIVR2_SYSTDIV  -------------------------------
+// SVD Line: 4867
+
+//  <item> SFDITEM_FIELD__SCUCG_SCDIVR2_SYSTDIV
+//    <name> SYSTDIV </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x4000180C) \nClock Divide for SysTick Timer, Divider 3\n0 : HCLK1 = HCLK/1\n1 : HCLK2 = HCLK/2\n2 : HCLK4 = HCLK/4\n3 : HCLK8 = HCLK/8 </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_SCDIVR2 ) </loc>
+//      <o.5..4> SYSTDIV
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK2 = HCLK/2
+//        <2=> 2: HCLK4 = HCLK/4
+//        <3=> 3: HCLK8 = HCLK/8
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_SCDIVR2_PDIV  ---------------------------------
+// SVD Line: 4895
+
+//  <item> SFDITEM_FIELD__SCUCG_SCDIVR2_PDIV
+//    <name> PDIV </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x4000180C) \nClock Divide for PCLK, Divider 1\n0 : HCLK1 = HCLK/1\n1 : HCLK2 = HCLK/2\n2 : HCLK4 = HCLK/4\n3 : HCLK8 = HCLK/8 </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_SCDIVR2 ) </loc>
+//      <o.1..0> PDIV
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK2 = HCLK/2
+//        <2=> 2: HCLK4 = HCLK/4
+//        <3=> 3: HCLK8 = HCLK/8
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_SCDIVR2  ---------------------------------
+// SVD Line: 4858
+
+//  <rtree> SFDITEM_REG__SCUCG_SCDIVR2
+//    <name> SCDIVR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000180C) System Clock Divide Register 2 </i>
+//    <loc> ( (unsigned int)((SCUCG_SCDIVR2 >> 0) & 0xFFFFFFFF), ((SCUCG_SCDIVR2 = (SCUCG_SCDIVR2 & ~(0x33UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_SCDIVR2_SYSTDIV </item>
+//    <item> SFDITEM_FIELD__SCUCG_SCDIVR2_PDIV </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCG_CLKOCR  ------------------------------
+// SVD Line: 4925
+
+unsigned int SCUCG_CLKOCR __AT (0x40001810);
+
+
+
+// -----------------------------  Field Item: SCUCG_CLKOCR_CLKOEN  --------------------------------
+// SVD Line: 4934
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKOCR_CLKOEN
+//    <name> CLKOEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40001810) \nClock Output Enable\n0 : Disable = Disable clock output.\n1 : Enable = Enable clock output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKOCR ) </loc>
+//      <o.7..7> CLKOEN
+//        <0=> 0: Disable = Disable clock output.
+//        <1=> 1: Enable = Enable clock output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_CLKOCR_POLSEL  --------------------------------
+// SVD Line: 4952
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKOCR_POLSEL
+//    <name> POLSEL </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40001810) \nClock Output Polarity Selection when Disable\n0 : Low = Low level during disable\n1 : High = High level during disable </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKOCR ) </loc>
+//      <o.6..6> POLSEL
+//        <0=> 0: Low = Low level during disable
+//        <1=> 1: High = High level during disable
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CLKOCR_CLKODIV  --------------------------------
+// SVD Line: 4970
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKOCR_CLKODIV
+//    <name> CLKODIV </name>
+//    <rw> 
+//    <i> [Bits 5..3] RW (@ 0x40001810) \nOutput Clock Divide, Divider 4\n0 : SelectedClock1 = Selected Clock/1\n1 : SelectedClock2 = Selected Clock/2\n2 : SelectedClock4 = Selected Clock/4\n3 : SelectedClock8 = Selected Clock/8\n4 : SelectedClock16 = Selected Clock/16\n5 : SelectedClock32 = Selected Clock/32\n6 : SelectedClock64 = Selected Clock/64\n7 : SelectedClock128 = Selected Clock/128 </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKOCR ) </loc>
+//      <o.5..3> CLKODIV
+//        <0=> 0: SelectedClock1 = Selected Clock/1
+//        <1=> 1: SelectedClock2 = Selected Clock/2
+//        <2=> 2: SelectedClock4 = Selected Clock/4
+//        <3=> 3: SelectedClock8 = Selected Clock/8
+//        <4=> 4: SelectedClock16 = Selected Clock/16
+//        <5=> 5: SelectedClock32 = Selected Clock/32
+//        <6=> 6: SelectedClock64 = Selected Clock/64
+//        <7=> 7: SelectedClock128 = Selected Clock/128
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_CLKOCR_CLKOS  ---------------------------------
+// SVD Line: 5018
+
+//  <item> SFDITEM_FIELD__SCUCG_CLKOCR_CLKOS
+//    <name> CLKOS </name>
+//    <rw> 
+//    <i> [Bits 2..0] RW (@ 0x40001810) \nClock Output Selection\n0 : MCLK = Select MCLK.\n1 : WDTRC = Select WDTRC.\n2 : HIRC = Select HIRC.\n3 : HCLK = Select HCLK.\n4 : PCLK = Select PCLK.\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CLKOCR ) </loc>
+//      <o.2..0> CLKOS
+//        <0=> 0: MCLK = Select MCLK.
+//        <1=> 1: WDTRC = Select WDTRC.
+//        <2=> 2: HIRC = Select HIRC.
+//        <3=> 3: HCLK = Select HCLK.
+//        <4=> 4: PCLK = Select PCLK.
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_CLKOCR  ----------------------------------
+// SVD Line: 4925
+
+//  <rtree> SFDITEM_REG__SCUCG_CLKOCR
+//    <name> CLKOCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001810) Clock Output Control Register </i>
+//    <loc> ( (unsigned int)((SCUCG_CLKOCR >> 0) & 0xFFFFFFFF), ((SCUCG_CLKOCR = (SCUCG_CLKOCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_CLKOCR_CLKOEN </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKOCR_POLSEL </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKOCR_CLKODIV </item>
+//    <item> SFDITEM_FIELD__SCUCG_CLKOCR_CLKOS </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCG_CMONCR  ------------------------------
+// SVD Line: 5053
+
+unsigned int SCUCG_CMONCR __AT (0x40001814);
+
+
+
+// -----------------------------  Field Item: SCUCG_CMONCR_MONEN  ---------------------------------
+// SVD Line: 5062
+
+//  <item> SFDITEM_FIELD__SCUCG_CMONCR_MONEN
+//    <name> MONEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40001814) \nClock Monitoring Enable\n0 : Disable = Disable clock monitoring.\n1 : Enable = Enable clock monitoring. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CMONCR ) </loc>
+//      <o.7..7> MONEN
+//        <0=> 0: Disable = Disable clock monitoring.
+//        <1=> 1: Enable = Enable clock monitoring.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_CMONCR_MACTS  ---------------------------------
+// SVD Line: 5080
+
+//  <item> SFDITEM_FIELD__SCUCG_CMONCR_MACTS
+//    <name> MACTS </name>
+//    <rw> 
+//    <i> [Bits 6..5] RW (@ 0x40001814) \nClock Monitoring Action Selection\n0 : FlagChk = No action by clock monitoring, but flags will be set/cleared on condition\n1 : RstGen = Reset generation by clock monitoring\n2 : SysClkChg = The system clock will be changed to the WDTRC regardless of MCLKSEL[1:0] bits of system clock control register (SCU_SCCR) only when the MCLK is selected for monitoring\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CMONCR ) </loc>
+//      <o.6..5> MACTS
+//        <0=> 0: FlagChk = No action by clock monitoring, but flags will be set/cleared on condition
+//        <1=> 1: RstGen = Reset generation by clock monitoring
+//        <2=> 2: SysClkChg = The system clock will be changed to the WDTRC regardless of MCLKSEL[1:0] bits of system clock control register (SCU_SCCR) only when the MCLK is selected for monitoring
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CMONCR_MONFLAG  --------------------------------
+// SVD Line: 5103
+
+//  <item> SFDITEM_FIELD__SCUCG_CMONCR_MONFLAG
+//    <name> MONFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001814) \nClock Monitoring Result Flag\n0 : NotReady = The clock to be monitored is not ready\n1 : Ready = The clock to be monitored is ready </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CMONCR ) </loc>
+//      <o.3..3> MONFLAG
+//        <0=> 0: NotReady = The clock to be monitored is not ready
+//        <1=> 1: Ready = The clock to be monitored is ready
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_CMONCR_NMINTFG  --------------------------------
+// SVD Line: 5121
+
+//  <item> SFDITEM_FIELD__SCUCG_CMONCR_NMINTFG
+//    <name> NMINTFG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001814) \nClock Monitoring Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CMONCR ) </loc>
+//      <o.2..2> NMINTFG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_CMONCR_MONCS  ---------------------------------
+// SVD Line: 5139
+
+//  <item> SFDITEM_FIELD__SCUCG_CMONCR_MONCS
+//    <name> MONCS </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x40001814) \nMonitored Clock Selection\n0 : MCLK = Select MCLK.\n1 : HIRC = Select HIRC.\n2 : XMOSC = Select XMOSC.\n3 : XSOSC = Select XSOSC. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_CMONCR ) </loc>
+//      <o.1..0> MONCS
+//        <0=> 0: MCLK = Select MCLK.
+//        <1=> 1: HIRC = Select HIRC.
+//        <2=> 2: XMOSC = Select XMOSC.
+//        <3=> 3: XSOSC = Select XSOSC.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_CMONCR  ----------------------------------
+// SVD Line: 5053
+
+//  <rtree> SFDITEM_REG__SCUCG_CMONCR
+//    <name> CMONCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001814) Clock Monitoring Control Register </i>
+//    <loc> ( (unsigned int)((SCUCG_CMONCR >> 0) & 0xFFFFFFFF), ((SCUCG_CMONCR = (SCUCG_CMONCR & ~(0xEFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xEF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_CMONCR_MONEN </item>
+//    <item> SFDITEM_FIELD__SCUCG_CMONCR_MACTS </item>
+//    <item> SFDITEM_FIELD__SCUCG_CMONCR_MONFLAG </item>
+//    <item> SFDITEM_FIELD__SCUCG_CMONCR_NMINTFG </item>
+//    <item> SFDITEM_FIELD__SCUCG_CMONCR_MONCS </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCG_PPCLKEN1  -----------------------------
+// SVD Line: 5169
+
+unsigned int SCUCG_PPCLKEN1 __AT (0x40001820);
+
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T21CLKE  -------------------------------
+// SVD Line: 5178
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T21CLKE
+//    <name> T21CLKE </name>
+//    <rw> 
+//    <i> [Bit 21] RW (@ 0x40001820) \nTIMER21 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.21..21> T21CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T20CLKE  -------------------------------
+// SVD Line: 5196
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T20CLKE
+//    <name> T20CLKE </name>
+//    <rw> 
+//    <i> [Bit 20] RW (@ 0x40001820) \nTIMER20 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.20..20> T20CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T30CLKE  -------------------------------
+// SVD Line: 5214
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T30CLKE
+//    <name> T30CLKE </name>
+//    <rw> 
+//    <i> [Bit 19] RW (@ 0x40001820) \nTIMER30 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.19..19> T30CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T12CLKE  -------------------------------
+// SVD Line: 5232
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T12CLKE
+//    <name> T12CLKE </name>
+//    <rw> 
+//    <i> [Bit 18] RW (@ 0x40001820) \nTIMER12 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.18..18> T12CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T11CLKE  -------------------------------
+// SVD Line: 5250
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T11CLKE
+//    <name> T11CLKE </name>
+//    <rw> 
+//    <i> [Bit 17] RW (@ 0x40001820) \nTIMER11 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.17..17> T11CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T10CLKE  -------------------------------
+// SVD Line: 5268
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T10CLKE
+//    <name> T10CLKE </name>
+//    <rw> 
+//    <i> [Bit 16] RW (@ 0x40001820) \nTIMER10 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.16..16> T10CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T16CLKE  -------------------------------
+// SVD Line: 5286
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T16CLKE
+//    <name> T16CLKE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40001820) \nTIMER16 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.11..11> T16CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T15CLKE  -------------------------------
+// SVD Line: 5304
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T15CLKE
+//    <name> T15CLKE </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40001820) \nTIMER15 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.10..10> T15CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T14CLKE  -------------------------------
+// SVD Line: 5322
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T14CLKE
+//    <name> T14CLKE </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40001820) \nTIMER14 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.9..9> T14CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN1_T13CLKE  -------------------------------
+// SVD Line: 5340
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T13CLKE
+//    <name> T13CLKE </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40001820) \nTIMER13 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.8..8> T13CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN1_PFCLKE  -------------------------------
+// SVD Line: 5358
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PFCLKE
+//    <name> PFCLKE </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40001820) \nPort F Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.5..5> PFCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN1_PECLKE  -------------------------------
+// SVD Line: 5376
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PECLKE
+//    <name> PECLKE </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40001820) \nPort E Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.4..4> PECLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN1_PDCLKE  -------------------------------
+// SVD Line: 5394
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PDCLKE
+//    <name> PDCLKE </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001820) \nPort D Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.3..3> PDCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN1_PCCLKE  -------------------------------
+// SVD Line: 5412
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PCCLKE
+//    <name> PCCLKE </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001820) \nPort C Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.2..2> PCCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN1_PBCLKE  -------------------------------
+// SVD Line: 5430
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PBCLKE
+//    <name> PBCLKE </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001820) \nPort B Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.1..1> PBCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN1_PACLKE  -------------------------------
+// SVD Line: 5448
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PACLKE
+//    <name> PACLKE </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001820) \nPort A Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN1 ) </loc>
+//      <o.0..0> PACLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: SCUCG_PPCLKEN1  ---------------------------------
+// SVD Line: 5169
+
+//  <rtree> SFDITEM_REG__SCUCG_PPCLKEN1
+//    <name> PPCLKEN1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001820) Peripheral Clock Enable Register 1 </i>
+//    <loc> ( (unsigned int)((SCUCG_PPCLKEN1 >> 0) & 0xFFFFFFFF), ((SCUCG_PPCLKEN1 = (SCUCG_PPCLKEN1 & ~(0x3F0F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F0F3F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T21CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T20CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T30CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T12CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T11CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T10CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T16CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T15CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T14CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_T13CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PFCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PECLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PDCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PCCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PBCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN1_PACLKE </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCG_PPCLKEN2  -----------------------------
+// SVD Line: 5468
+
+unsigned int SCUCG_PPCLKEN2 __AT (0x40001824);
+
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN2_FMCLKE  -------------------------------
+// SVD Line: 5477
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_FMCLKE
+//    <name> FMCLKE </name>
+//    <rw> 
+//    <i> [Bit 19] RW (@ 0x40001824) \nFMC (Flash Memory Controller) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.19..19> FMCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN2_LVICLKE  -------------------------------
+// SVD Line: 5495
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_LVICLKE
+//    <name> LVICLKE </name>
+//    <rw> 
+//    <i> [Bit 18] RW (@ 0x40001824) \nLVI (Low Voltage Indicator) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.18..18> LVICLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN2_WDTCLKE  -------------------------------
+// SVD Line: 5513
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_WDTCLKE
+//    <name> WDTCLKE </name>
+//    <rw> 
+//    <i> [Bit 17] RW (@ 0x40001824) \nWDT (Watch-Dog Timer) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.17..17> WDTCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN2_WTCLKE  -------------------------------
+// SVD Line: 5531
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_WTCLKE
+//    <name> WTCLKE </name>
+//    <rw> 
+//    <i> [Bit 16] RW (@ 0x40001824) \nWT (Watch Timer) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.16..16> WTCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN2_LCDCLKE  -------------------------------
+// SVD Line: 5549
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_LCDCLKE
+//    <name> LCDCLKE </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x40001824) \nLCD (LCD Driver) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.13..13> LCDCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN2_CRCLKE  -------------------------------
+// SVD Line: 5567
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_CRCLKE
+//    <name> CRCLKE </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x40001824) \nCRC (Cyclic Redundancy Check) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.12..12> CRCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKEN2_ADCLKE  -------------------------------
+// SVD Line: 5585
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_ADCLKE
+//    <name> ADCLKE </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40001824) \nADC (Analog to Digital Converter) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.10..10> ADCLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN2_I2C2CLKE  ------------------------------
+// SVD Line: 5603
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_I2C2CLKE
+//    <name> I2C2CLKE </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40001824) \nI2C2 (Inter-IC) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.8..8> I2C2CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN2_I2C1CLKE  ------------------------------
+// SVD Line: 5621
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_I2C1CLKE
+//    <name> I2C1CLKE </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40001824) \nI2C1 (Inter-IC) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.7..7> I2C1CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN2_I2C0CLKE  ------------------------------
+// SVD Line: 5639
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_I2C0CLKE
+//    <name> I2C0CLKE </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40001824) \nI2C0 (Inter-IC) Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.6..6> I2C0CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: SCUCG_PPCLKEN2_UST13CLKE  ------------------------------
+// SVD Line: 5657
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UST13CLKE
+//    <name> UST13CLKE </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40001824) \nUSART13 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.5..5> UST13CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: SCUCG_PPCLKEN2_UST12CLKE  ------------------------------
+// SVD Line: 5675
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UST12CLKE
+//    <name> UST12CLKE </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40001824) \nUSART12 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.4..4> UST12CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN2_UT1CLKE  -------------------------------
+// SVD Line: 5693
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UT1CLKE
+//    <name> UT1CLKE </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001824) \nUART1 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.3..3> UT1CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: SCUCG_PPCLKEN2_UT0CLKE  -------------------------------
+// SVD Line: 5711
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UT0CLKE
+//    <name> UT0CLKE </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001824) \nUART0 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.2..2> UT0CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: SCUCG_PPCLKEN2_UST11CLKE  ------------------------------
+// SVD Line: 5729
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UST11CLKE
+//    <name> UST11CLKE </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001824) \nUSART11 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.1..1> UST11CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: SCUCG_PPCLKEN2_UST10CLKE  ------------------------------
+// SVD Line: 5747
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UST10CLKE
+//    <name> UST10CLKE </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001824) \nUSART10 Clock Enable\n0 : Disable = Disable clock.\n1 : Enable = Enable clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKEN2 ) </loc>
+//      <o.0..0> UST10CLKE
+//        <0=> 0: Disable = Disable clock.
+//        <1=> 1: Enable = Enable clock.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: SCUCG_PPCLKEN2  ---------------------------------
+// SVD Line: 5468
+
+//  <rtree> SFDITEM_REG__SCUCG_PPCLKEN2
+//    <name> PPCLKEN2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001824) Peripheral Clock Enable Register 2 </i>
+//    <loc> ( (unsigned int)((SCUCG_PPCLKEN2 >> 0) & 0xFFFFFFFF), ((SCUCG_PPCLKEN2 = (SCUCG_PPCLKEN2 & ~(0xF35FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF35FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_FMCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_LVICLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_WDTCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_WTCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_LCDCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_CRCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_ADCLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_I2C2CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_I2C1CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_I2C0CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UST13CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UST12CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UT1CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UT0CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UST11CLKE </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKEN2_UST10CLKE </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: SCUCG_PPCLKSR  ------------------------------
+// SVD Line: 5767
+
+unsigned int SCUCG_PPCLKSR __AT (0x40001840);
+
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKSR_T20CLK  --------------------------------
+// SVD Line: 5776
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKSR_T20CLK
+//    <name> T20CLK </name>
+//    <rw> 
+//    <i> [Bit 20] RW (@ 0x40001840) \nTIMER20 Clock Selection\n0 : XSOSC = XSOSC clock\n1 : PCLK = PCLK clock </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKSR ) </loc>
+//      <o.20..20> T20CLK
+//        <0=> 0: XSOSC = XSOSC clock
+//        <1=> 1: PCLK = PCLK clock
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKSR_T30CLK  --------------------------------
+// SVD Line: 5794
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKSR_T30CLK
+//    <name> T30CLK </name>
+//    <rw> 
+//    <i> [Bit 17] RW (@ 0x40001840) \nTIMER30 Clock Selection\n0 : MCLK = MCLK clock\n1 : PCLK = PCLK clock </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKSR ) </loc>
+//      <o.17..17> T30CLK
+//        <0=> 0: MCLK = MCLK clock
+//        <1=> 1: PCLK = PCLK clock
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKSR_LCDCLK  --------------------------------
+// SVD Line: 5812
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKSR_LCDCLK
+//    <name> LCDCLK </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40001840) \nLCD (LCD Driver) Clock Selection\n0 : DividedMCLK = A clock of the MCLK which is divided by divider 2\n1 : XSOSC = XSOSC clock\n2 : WDTRC = WDTRC clock\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKSR ) </loc>
+//      <o.7..6> LCDCLK
+//        <0=> 0: DividedMCLK = A clock of the MCLK which is divided by divider 2
+//        <1=> 1: XSOSC = XSOSC clock
+//        <2=> 2: WDTRC = WDTRC clock
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPCLKSR_WTCLK  --------------------------------
+// SVD Line: 5835
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKSR_WTCLK
+//    <name> WTCLK </name>
+//    <rw> 
+//    <i> [Bits 4..3] RW (@ 0x40001840) \nWT (Watch Timer) Clock Selection\n0 : DividedMCLK = A clock of the MCLK which is divided by divider 2\n1 : XSOSC = XSOSC clock\n2 : WDTRC = WDTRC clock\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKSR ) </loc>
+//      <o.4..3> WTCLK
+//        <0=> 0: DividedMCLK = A clock of the MCLK which is divided by divider 2
+//        <1=> 1: XSOSC = XSOSC clock
+//        <2=> 2: WDTRC = WDTRC clock
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPCLKSR_WDTCLK  --------------------------------
+// SVD Line: 5858
+
+//  <item> SFDITEM_FIELD__SCUCG_PPCLKSR_WDTCLK
+//    <name> WDTCLK </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001840) \nWDT (Watch-Dog Timer) Clock Selection\n0 : WDTRC = WDTRC clock\n1 : PCLK = PCLK clock </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_PPCLKSR ) </loc>
+//      <o.0..0> WDTCLK
+//        <0=> 0: WDTRC = WDTRC clock
+//        <1=> 1: PCLK = PCLK clock
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_PPCLKSR  ---------------------------------
+// SVD Line: 5767
+
+//  <rtree> SFDITEM_REG__SCUCG_PPCLKSR
+//    <name> PPCLKSR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001840) Peripheral Clock Selection Register </i>
+//    <loc> ( (unsigned int)((SCUCG_PPCLKSR >> 0) & 0xFFFFFFFF), ((SCUCG_PPCLKSR = (SCUCG_PPCLKSR & ~(0x1200D9UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1200D9) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKSR_T20CLK </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKSR_T30CLK </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKSR_LCDCLK </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKSR_WTCLK </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPCLKSR_WDTCLK </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCG_PPRST1  ------------------------------
+// SVD Line: 5878
+
+unsigned int SCUCG_PPRST1 __AT (0x40001860);
+
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T21RST  --------------------------------
+// SVD Line: 5887
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T21RST
+//    <name> T21RST </name>
+//    <rw> 
+//    <i> [Bit 21] RW (@ 0x40001860) TIMER21 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.21..21> T21RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T20RST  --------------------------------
+// SVD Line: 5893
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T20RST
+//    <name> T20RST </name>
+//    <rw> 
+//    <i> [Bit 20] RW (@ 0x40001860) TIMER20 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.20..20> T20RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T30RST  --------------------------------
+// SVD Line: 5899
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T30RST
+//    <name> T30RST </name>
+//    <rw> 
+//    <i> [Bit 19] RW (@ 0x40001860) TIMER30 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.19..19> T30RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T12RST  --------------------------------
+// SVD Line: 5905
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T12RST
+//    <name> T12RST </name>
+//    <rw> 
+//    <i> [Bit 18] RW (@ 0x40001860) TIMER12 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.18..18> T12RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T11RST  --------------------------------
+// SVD Line: 5911
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T11RST
+//    <name> T11RST </name>
+//    <rw> 
+//    <i> [Bit 17] RW (@ 0x40001860) TIMER11 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.17..17> T11RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T10RST  --------------------------------
+// SVD Line: 5917
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T10RST
+//    <name> T10RST </name>
+//    <rw> 
+//    <i> [Bit 16] RW (@ 0x40001860) TIMER10 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.16..16> T10RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T16RST  --------------------------------
+// SVD Line: 5923
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T16RST
+//    <name> T16RST </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40001860) TIMER16 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.11..11> T16RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T15RST  --------------------------------
+// SVD Line: 5929
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T15RST
+//    <name> T15RST </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40001860) TIMER15 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.10..10> T15RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T14RST  --------------------------------
+// SVD Line: 5935
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T14RST
+//    <name> T14RST </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40001860) TIMER14 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.9..9> T14RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_T13RST  --------------------------------
+// SVD Line: 5941
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_T13RST
+//    <name> T13RST </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40001860) TIMER13 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.8..8> T13RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_PFRST  ---------------------------------
+// SVD Line: 5947
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_PFRST
+//    <name> PFRST </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40001860) Port F Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.5..5> PFRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_PERST  ---------------------------------
+// SVD Line: 5953
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_PERST
+//    <name> PERST </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40001860) Port E Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.4..4> PERST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_PDRST  ---------------------------------
+// SVD Line: 5959
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_PDRST
+//    <name> PDRST </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001860) Port D Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.3..3> PDRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_PCRST  ---------------------------------
+// SVD Line: 5965
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_PCRST
+//    <name> PCRST </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001860) Port C Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.2..2> PCRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_PBRST  ---------------------------------
+// SVD Line: 5971
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_PBRST
+//    <name> PBRST </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001860) Port B Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.1..1> PBRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST1_PARST  ---------------------------------
+// SVD Line: 5977
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST1_PARST
+//    <name> PARST </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001860) Port A Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST1 ) </loc>
+//      <o.0..0> PARST
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_PPRST1  ----------------------------------
+// SVD Line: 5878
+
+//  <rtree> SFDITEM_REG__SCUCG_PPRST1
+//    <name> PPRST1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001860) Peripheral Reset Register 1 </i>
+//    <loc> ( (unsigned int)((SCUCG_PPRST1 >> 0) & 0xFFFFFFFF), ((SCUCG_PPRST1 = (SCUCG_PPRST1 & ~(0x3F0F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F0F3F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T21RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T20RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T30RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T12RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T11RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T10RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T16RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T15RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T14RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_T13RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_PFRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_PERST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_PDRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_PCRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_PBRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST1_PARST </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCG_PPRST2  ------------------------------
+// SVD Line: 5985
+
+unsigned int SCUCG_PPRST2 __AT (0x40001864);
+
+
+
+// -----------------------------  Field Item: SCUCG_PPRST2_FMCRST  --------------------------------
+// SVD Line: 5994
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_FMCRST
+//    <name> FMCRST </name>
+//    <rw> 
+//    <i> [Bit 19] RW (@ 0x40001864) FMC (Flash Memory Controller) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.19..19> FMCRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST2_LVIRST  --------------------------------
+// SVD Line: 6000
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_LVIRST
+//    <name> LVIRST </name>
+//    <rw> 
+//    <i> [Bit 18] RW (@ 0x40001864) LVI (Low Voltage Indicator) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.18..18> LVIRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST2_WTRST  ---------------------------------
+// SVD Line: 6006
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_WTRST
+//    <name> WTRST </name>
+//    <rw> 
+//    <i> [Bit 16] RW (@ 0x40001864) WT (Watch Timer) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.16..16> WTRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST2_LCDRST  --------------------------------
+// SVD Line: 6012
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_LCDRST
+//    <name> LCDRST </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x40001864) LCD (LCD Driver) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.13..13> LCDRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST2_CRRST  ---------------------------------
+// SVD Line: 6018
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_CRRST
+//    <name> CRRST </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x40001864) CRC (Cyclic Redundancy Check) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.12..12> CRRST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST2_ADRST  ---------------------------------
+// SVD Line: 6024
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_ADRST
+//    <name> ADRST </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40001864) ADC (Analog to Digital Converter) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.10..10> ADRST
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPRST2_I2C2RST  --------------------------------
+// SVD Line: 6030
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_I2C2RST
+//    <name> I2C2RST </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40001864) I2C2 (Inter-IC) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.8..8> I2C2RST
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPRST2_I2C1RST  --------------------------------
+// SVD Line: 6036
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_I2C1RST
+//    <name> I2C1RST </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40001864) I2C1 (Inter-IC) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.7..7> I2C1RST
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPRST2_I2C0RST  --------------------------------
+// SVD Line: 6042
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_I2C0RST
+//    <name> I2C0RST </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40001864) I2C0 (Inter-IC) Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.6..6> I2C0RST
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPRST2_UST13RST  -------------------------------
+// SVD Line: 6048
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_UST13RST
+//    <name> UST13RST </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40001864) USART13 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.5..5> UST13RST
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPRST2_UST12RST  -------------------------------
+// SVD Line: 6054
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_UST12RST
+//    <name> UST12RST </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40001864) USART12 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.4..4> UST12RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST2_UT1RST  --------------------------------
+// SVD Line: 6060
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_UT1RST
+//    <name> UT1RST </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001864) UART1 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.3..3> UT1RST
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCUCG_PPRST2_UT0RST  --------------------------------
+// SVD Line: 6066
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_UT0RST
+//    <name> UT0RST </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001864) UART0 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.2..2> UT0RST
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPRST2_UST11RST  -------------------------------
+// SVD Line: 6072
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_UST11RST
+//    <name> UST11RST </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001864) USART11 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.1..1> UST11RST
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: SCUCG_PPRST2_UST10RST  -------------------------------
+// SVD Line: 6078
+
+//  <item> SFDITEM_FIELD__SCUCG_PPRST2_UST10RST
+//    <name> UST10RST </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001864) USART10 Reset </i>
+//    <check> 
+//      <loc> ( (unsigned int) SCUCG_PPRST2 ) </loc>
+//      <o.0..0> UST10RST
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_PPRST2  ----------------------------------
+// SVD Line: 5985
+
+//  <rtree> SFDITEM_REG__SCUCG_PPRST2
+//    <name> PPRST2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001864) Peripheral Reset Register 2 </i>
+//    <loc> ( (unsigned int)((SCUCG_PPRST2 >> 0) & 0xFFFFFFFF), ((SCUCG_PPRST2 = (SCUCG_PPRST2 & ~(0xD35FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD35FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_FMCRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_LVIRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_WTRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_LCDRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_CRRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_ADRST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_I2C2RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_I2C1RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_I2C0RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_UST13RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_UST12RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_UT1RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_UT0RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_UST11RST </item>
+//    <item> SFDITEM_FIELD__SCUCG_PPRST2_UST10RST </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCUCG_XTFLSR  ------------------------------
+// SVD Line: 6085
+
+unsigned int SCUCG_XTFLSR __AT (0x40001880);
+
+
+
+// -----------------------------  Field Item: SCUCG_XTFLSR_WTIDKY  --------------------------------
+// SVD Line: 6094
+
+//  <item> SFDITEM_FIELD__SCUCG_XTFLSR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x40001880) Write Identification Key (0x9b37) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((SCUCG_XTFLSR >> 16) & 0x0), ((SCUCG_XTFLSR = (SCUCG_XTFLSR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: SCUCG_XTFLSR_XRNS  ---------------------------------
+// SVD Line: 6107
+
+//  <item> SFDITEM_FIELD__SCUCG_XTFLSR_XRNS
+//    <name> XRNS </name>
+//    <rw> 
+//    <i> [Bits 2..0] RW (@ 0x40001880) \nExternal Main Oscillator Filter Selection\n0 : LE4p5MHz = x-tal LE 4.5MHz\n1 : LE6p5MHz = 4.5MHz GT x-tal LE 6.5MHz\n2 : LE8p5MHz = 6.5MHz GT x-tal LE 8.5MHz\n3 : LE10p5MHz = 8.5MHz GT x-tal LE 10.5MHz\n4 : LE12p5MHz = 10.5MHz GT x-tal LE 12.5MHz\n5 : LE16p5MHz = 12.5MHz GT x-tal LE 16.5MHz\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCUCG_XTFLSR ) </loc>
+//      <o.2..0> XRNS
+//        <0=> 0: LE4p5MHz = x-tal LE 4.5MHz
+//        <1=> 1: LE6p5MHz = 4.5MHz GT x-tal LE 6.5MHz
+//        <2=> 2: LE8p5MHz = 6.5MHz GT x-tal LE 8.5MHz
+//        <3=> 3: LE10p5MHz = 8.5MHz GT x-tal LE 10.5MHz
+//        <4=> 4: LE12p5MHz = 10.5MHz GT x-tal LE 12.5MHz
+//        <5=> 5: LE16p5MHz = 12.5MHz GT x-tal LE 16.5MHz
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: SCUCG_XTFLSR  ----------------------------------
+// SVD Line: 6085
+
+//  <rtree> SFDITEM_REG__SCUCG_XTFLSR
+//    <name> XTFLSR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001880) X-tal Filter Selection Register </i>
+//    <loc> ( (unsigned int)((SCUCG_XTFLSR >> 0) & 0xFFFFFFFF), ((SCUCG_XTFLSR = (SCUCG_XTFLSR & ~(0xFFFF0007UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0007) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCUCG_XTFLSR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__SCUCG_XTFLSR_XRNS </item>
+//  </rtree>
+//  
+
+
+// ---------------------------------  Peripheral View: SCUCG  -------------------------------------
+// SVD Line: 4573
+
+//  <view> SCUCG
+//    <name> SCUCG </name>
+//    <item> SFDITEM_REG__SCUCG_SCCR </item>
+//    <item> SFDITEM_REG__SCUCG_CLKSRCR </item>
+//    <item> SFDITEM_REG__SCUCG_SCDIVR1 </item>
+//    <item> SFDITEM_REG__SCUCG_SCDIVR2 </item>
+//    <item> SFDITEM_REG__SCUCG_CLKOCR </item>
+//    <item> SFDITEM_REG__SCUCG_CMONCR </item>
+//    <item> SFDITEM_REG__SCUCG_PPCLKEN1 </item>
+//    <item> SFDITEM_REG__SCUCG_PPCLKEN2 </item>
+//    <item> SFDITEM_REG__SCUCG_PPCLKSR </item>
+//    <item> SFDITEM_REG__SCUCG_PPRST1 </item>
+//    <item> SFDITEM_REG__SCUCG_PPRST2 </item>
+//    <item> SFDITEM_REG__SCUCG_XTFLSR </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: SCULV_LVICR  -------------------------------
+// SVD Line: 6168
+
+unsigned int SCULV_LVICR __AT (0x40005100);
+
+
+
+// ------------------------------  Field Item: SCULV_LVICR_LVIEN  ---------------------------------
+// SVD Line: 6177
+
+//  <item> SFDITEM_FIELD__SCULV_LVICR_LVIEN
+//    <name> LVIEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40005100) \nLVI Enable\n0 : Disable = Disable low voltage indicator.\n1 : Enable = Enable low voltage indicator. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCULV_LVICR ) </loc>
+//      <o.7..7> LVIEN
+//        <0=> 0: Disable = Disable low voltage indicator.
+//        <1=> 1: Enable = Enable low voltage indicator.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCULV_LVICR_LVINTEN  --------------------------------
+// SVD Line: 6195
+
+//  <item> SFDITEM_FIELD__SCULV_LVICR_LVINTEN
+//    <name> LVINTEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40005100) \nLVI Interrupt Enable\n0 : Disable = Disable low voltage indicator interrupt.\n1 : Enable = Enable low voltage indicator interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCULV_LVICR ) </loc>
+//      <o.5..5> LVINTEN
+//        <0=> 0: Disable = Disable low voltage indicator interrupt.
+//        <1=> 1: Enable = Enable low voltage indicator interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: SCULV_LVICR_LVIFLAG  --------------------------------
+// SVD Line: 6213
+
+//  <item> SFDITEM_FIELD__SCULV_LVICR_LVIFLAG
+//    <name> LVIFLAG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40005100) \nLVI Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCULV_LVICR ) </loc>
+//      <o.4..4> LVIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: SCULV_LVICR_LVIVS  ---------------------------------
+// SVD Line: 6231
+
+//  <item> SFDITEM_FIELD__SCULV_LVICR_LVIVS
+//    <name> LVIVS </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40005100) \nLVI Voltage Selection\n0 : Reserved - do not use\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : DNW3 = Do not write.\n4 : 2p00V = 2.00V\n5 : 2p13V = 2.13V\n6 : 2p28V = 2.28V\n7 : 2p46V = 2.46V\n8 : 2p67V = 2.67V\n9 : 3p04V = 3.04V\n10 : 3p20V = 3.20V\n11 : 3p55V = 3.55V\n12 : 3p75V = 3.75V\n13 : 3p99V = 3.99V\n14 : 4p25V = 4.25V\n15 : 4p55V = 4.55V </i>
+//    <combo> 
+//      <loc> ( (unsigned int) SCULV_LVICR ) </loc>
+//      <o.3..0> LVIVS
+//        <0=> 0: 
+//        <1=> 1: 
+//        <2=> 2: 
+//        <3=> 3: DNW3 = Do not write.
+//        <4=> 4: 2p00V = 2.00V
+//        <5=> 5: 2p13V = 2.13V
+//        <6=> 6: 2p28V = 2.28V
+//        <7=> 7: 2p46V = 2.46V
+//        <8=> 8: 2p67V = 2.67V
+//        <9=> 9: 3p04V = 3.04V
+//        <10=> 10: 3p20V = 3.20V
+//        <11=> 11: 3p55V = 3.55V
+//        <12=> 12: 3p75V = 3.75V
+//        <13=> 13: 3p99V = 3.99V
+//        <14=> 14: 4p25V = 4.25V
+//        <15=> 15: 4p55V = 4.55V
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: SCULV_LVICR  ----------------------------------
+// SVD Line: 6168
+
+//  <rtree> SFDITEM_REG__SCULV_LVICR
+//    <name> LVICR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40005100) Low Voltage Indicator Control Register </i>
+//    <loc> ( (unsigned int)((SCULV_LVICR >> 0) & 0xFFFFFFFF), ((SCULV_LVICR = (SCULV_LVICR & ~(0xBFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xBF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCULV_LVICR_LVIEN </item>
+//    <item> SFDITEM_FIELD__SCULV_LVICR_LVINTEN </item>
+//    <item> SFDITEM_FIELD__SCULV_LVICR_LVIFLAG </item>
+//    <item> SFDITEM_FIELD__SCULV_LVICR_LVIVS </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: SCULV_LVRCR  -------------------------------
+// SVD Line: 6306
+
+unsigned int SCULV_LVRCR __AT (0x40005104);
+
+
+
+// ------------------------------  Field Item: SCULV_LVRCR_LVREN  ---------------------------------
+// SVD Line: 6315
+
+//  <item> SFDITEM_FIELD__SCULV_LVRCR_LVREN
+//    <name> LVREN </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40005104) LVR Enable </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((SCULV_LVRCR >> 0) & 0xFF), ((SCULV_LVRCR = (SCULV_LVRCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: SCULV_LVRCR  ----------------------------------
+// SVD Line: 6306
+
+//  <rtree> SFDITEM_REG__SCULV_LVRCR
+//    <name> LVRCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40005104) Low Voltage Reset Control Register </i>
+//    <loc> ( (unsigned int)((SCULV_LVRCR >> 0) & 0xFFFFFFFF), ((SCULV_LVRCR = (SCULV_LVRCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__SCULV_LVRCR_LVREN </item>
+//  </rtree>
+//  
+
+
+// ---------------------------------  Peripheral View: SCULV  -------------------------------------
+// SVD Line: 6149
+
+//  <view> SCULV
+//    <name> SCULV </name>
+//    <item> SFDITEM_REG__SCULV_LVICR </item>
+//    <item> SFDITEM_REG__SCULV_LVRCR </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: Pn_MOD  ---------------------------------
+// SVD Line: 6351
+
+unsigned int Pn_MOD __AT (0x50000000);
+
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE15  -----------------------------------
+// SVD Line: 6360
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x50000000) \nPort n Mode Selection 15\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.31..30> MODE15
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE14  -----------------------------------
+// SVD Line: 6383
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x50000000) \nPort n Mode Selection 14\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.29..28> MODE14
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE13  -----------------------------------
+// SVD Line: 6406
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x50000000) \nPort n Mode Selection 13\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.27..26> MODE13
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE12  -----------------------------------
+// SVD Line: 6429
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x50000000) \nPort n Mode Selection 12\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.25..24> MODE12
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE11  -----------------------------------
+// SVD Line: 6452
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x50000000) \nPort n Mode Selection 11\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.23..22> MODE11
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE10  -----------------------------------
+// SVD Line: 6475
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x50000000) \nPort n Mode Selection 10\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.21..20> MODE10
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE9  ------------------------------------
+// SVD Line: 6498
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x50000000) \nPort n Mode Selection 9\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.19..18> MODE9
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE8  ------------------------------------
+// SVD Line: 6521
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x50000000) \nPort n Mode Selection 8\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.17..16> MODE8
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE7  ------------------------------------
+// SVD Line: 6544
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x50000000) \nPort n Mode Selection 7\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.15..14> MODE7
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE6  ------------------------------------
+// SVD Line: 6567
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x50000000) \nPort n Mode Selection 6\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.13..12> MODE6
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE5  ------------------------------------
+// SVD Line: 6590
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x50000000) \nPort n Mode Selection 5\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.11..10> MODE5
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE4  ------------------------------------
+// SVD Line: 6613
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x50000000) \nPort n Mode Selection 4\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.9..8> MODE4
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE3  ------------------------------------
+// SVD Line: 6636
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x50000000) \nPort n Mode Selection 3\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.7..6> MODE3
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE2  ------------------------------------
+// SVD Line: 6659
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x50000000) \nPort n Mode Selection 2\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.5..4> MODE2
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE1  ------------------------------------
+// SVD Line: 6682
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x50000000) \nPort n Mode Selection 1\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.3..2> MODE1
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_MOD_MODE0  ------------------------------------
+// SVD Line: 6705
+
+//  <item> SFDITEM_FIELD__Pn_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x50000000) \nPort n Mode Selection 0\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_MOD ) </loc>
+//      <o.1..0> MODE0
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: Pn_MOD  -------------------------------------
+// SVD Line: 6351
+
+//  <rtree> SFDITEM_REG__Pn_MOD
+//    <name> MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x50000000) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((Pn_MOD >> 0) & 0xFFFFFFFF), ((Pn_MOD = (Pn_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__Pn_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: Pn_TYP  ---------------------------------
+// SVD Line: 6730
+
+unsigned int Pn_TYP __AT (0x50000004);
+
+
+
+// --------------------------------  Field Item: Pn_TYP_TYP15  ------------------------------------
+// SVD Line: 6739
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x50000004) \nPort n Output Type Selection 15\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.15..15> TYP15
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_TYP_TYP14  ------------------------------------
+// SVD Line: 6757
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x50000004) \nPort n Output Type Selection 14\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.14..14> TYP14
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_TYP_TYP13  ------------------------------------
+// SVD Line: 6775
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x50000004) \nPort n Output Type Selection 13\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.13..13> TYP13
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_TYP_TYP12  ------------------------------------
+// SVD Line: 6793
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x50000004) \nPort n Output Type Selection 12\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.12..12> TYP12
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_TYP_TYP11  ------------------------------------
+// SVD Line: 6811
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x50000004) \nPort n Output Type Selection 11\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.11..11> TYP11
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_TYP_TYP10  ------------------------------------
+// SVD Line: 6829
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x50000004) \nPort n Output Type Selection 10\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.10..10> TYP10
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP9  ------------------------------------
+// SVD Line: 6847
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x50000004) \nPort n Output Type Selection 9\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.9..9> TYP9
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP8  ------------------------------------
+// SVD Line: 6865
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x50000004) \nPort n Output Type Selection 8\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.8..8> TYP8
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP7  ------------------------------------
+// SVD Line: 6883
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x50000004) \nPort n Output Type Selection 7\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.7..7> TYP7
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP6  ------------------------------------
+// SVD Line: 6901
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x50000004) \nPort n Output Type Selection 6\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.6..6> TYP6
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP5  ------------------------------------
+// SVD Line: 6919
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x50000004) \nPort n Output Type Selection 5\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.5..5> TYP5
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP4  ------------------------------------
+// SVD Line: 6937
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x50000004) \nPort n Output Type Selection 4\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.4..4> TYP4
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP3  ------------------------------------
+// SVD Line: 6955
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x50000004) \nPort n Output Type Selection 3\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.3..3> TYP3
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP2  ------------------------------------
+// SVD Line: 6973
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x50000004) \nPort n Output Type Selection 2\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.2..2> TYP2
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP1  ------------------------------------
+// SVD Line: 6991
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x50000004) \nPort n Output Type Selection 1\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.1..1> TYP1
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_TYP_TYP0  ------------------------------------
+// SVD Line: 7009
+
+//  <item> SFDITEM_FIELD__Pn_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x50000004) \nPort n Output Type Selection 0\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_TYP ) </loc>
+//      <o.0..0> TYP0
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: Pn_TYP  -------------------------------------
+// SVD Line: 6730
+
+//  <rtree> SFDITEM_REG__Pn_TYP
+//    <name> TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x50000004) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((Pn_TYP >> 0) & 0xFFFFFFFF), ((Pn_TYP = (Pn_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__Pn_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: Pn_AFSR1  --------------------------------
+// SVD Line: 7029
+
+unsigned int Pn_AFSR1 __AT (0x50000008);
+
+
+
+// -------------------------------  Field Item: Pn_AFSR1_AFSR7  -----------------------------------
+// SVD Line: 7038
+
+//  <item> SFDITEM_FIELD__Pn_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x50000008) \nPort n Alternative Function Selection 7\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR1 ) </loc>
+//      <o.31..28> AFSR7
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR1_AFSR6  -----------------------------------
+// SVD Line: 7071
+
+//  <item> SFDITEM_FIELD__Pn_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x50000008) \nPort n Alternative Function Selection 6\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR1 ) </loc>
+//      <o.27..24> AFSR6
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR1_AFSR5  -----------------------------------
+// SVD Line: 7104
+
+//  <item> SFDITEM_FIELD__Pn_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x50000008) \nPort n Alternative Function Selection 5\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR1 ) </loc>
+//      <o.23..20> AFSR5
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR1_AFSR4  -----------------------------------
+// SVD Line: 7137
+
+//  <item> SFDITEM_FIELD__Pn_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x50000008) \nPort n Alternative Function Selection 4\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR1 ) </loc>
+//      <o.19..16> AFSR4
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR1_AFSR3  -----------------------------------
+// SVD Line: 7170
+
+//  <item> SFDITEM_FIELD__Pn_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x50000008) \nPort n Alternative Function Selection 3\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR1 ) </loc>
+//      <o.15..12> AFSR3
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR1_AFSR2  -----------------------------------
+// SVD Line: 7203
+
+//  <item> SFDITEM_FIELD__Pn_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x50000008) \nPort n Alternative Function Selection 2\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR1 ) </loc>
+//      <o.11..8> AFSR2
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR1_AFSR1  -----------------------------------
+// SVD Line: 7236
+
+//  <item> SFDITEM_FIELD__Pn_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x50000008) \nPort n Alternative Function Selection 1\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR1 ) </loc>
+//      <o.7..4> AFSR1
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR1_AFSR0  -----------------------------------
+// SVD Line: 7269
+
+//  <item> SFDITEM_FIELD__Pn_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x50000008) \nPort n Alternative Function Selection 0\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR1 ) </loc>
+//      <o.3..0> AFSR0
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: Pn_AFSR1  ------------------------------------
+// SVD Line: 7029
+
+//  <rtree> SFDITEM_REG__Pn_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x50000008) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((Pn_AFSR1 >> 0) & 0xFFFFFFFF), ((Pn_AFSR1 = (Pn_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: Pn_AFSR2  --------------------------------
+// SVD Line: 7304
+
+unsigned int Pn_AFSR2 __AT (0x5000000C);
+
+
+
+// -------------------------------  Field Item: Pn_AFSR2_AFSR15  ----------------------------------
+// SVD Line: 7313
+
+//  <item> SFDITEM_FIELD__Pn_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x5000000C) \nPort n Alternative Function Selection 15\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR2 ) </loc>
+//      <o.31..28> AFSR15
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR2_AFSR14  ----------------------------------
+// SVD Line: 7346
+
+//  <item> SFDITEM_FIELD__Pn_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x5000000C) \nPort n Alternative Function Selection 14\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR2 ) </loc>
+//      <o.27..24> AFSR14
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR2_AFSR13  ----------------------------------
+// SVD Line: 7379
+
+//  <item> SFDITEM_FIELD__Pn_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x5000000C) \nPort n Alternative Function Selection 13\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR2 ) </loc>
+//      <o.23..20> AFSR13
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR2_AFSR12  ----------------------------------
+// SVD Line: 7412
+
+//  <item> SFDITEM_FIELD__Pn_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x5000000C) \nPort n Alternative Function Selection 12\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR2 ) </loc>
+//      <o.19..16> AFSR12
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR2_AFSR11  ----------------------------------
+// SVD Line: 7445
+
+//  <item> SFDITEM_FIELD__Pn_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x5000000C) \nPort n Alternative Function Selection 11\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR2 ) </loc>
+//      <o.15..12> AFSR11
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR2_AFSR10  ----------------------------------
+// SVD Line: 7478
+
+//  <item> SFDITEM_FIELD__Pn_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x5000000C) \nPort n Alternative Function Selection 10\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR2 ) </loc>
+//      <o.11..8> AFSR10
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR2_AFSR9  -----------------------------------
+// SVD Line: 7511
+
+//  <item> SFDITEM_FIELD__Pn_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x5000000C) \nPort n Alternative Function Selection 9\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR2 ) </loc>
+//      <o.7..4> AFSR9
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_AFSR2_AFSR8  -----------------------------------
+// SVD Line: 7544
+
+//  <item> SFDITEM_FIELD__Pn_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x5000000C) \nPort n Alternative Function Selection 8\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_AFSR2 ) </loc>
+//      <o.3..0> AFSR8
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: Pn_AFSR2  ------------------------------------
+// SVD Line: 7304
+
+//  <rtree> SFDITEM_REG__Pn_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x5000000C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((Pn_AFSR2 >> 0) & 0xFFFFFFFF), ((Pn_AFSR2 = (Pn_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__Pn_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: Pn_PUPD  ---------------------------------
+// SVD Line: 7579
+
+unsigned int Pn_PUPD __AT (0x50000010);
+
+
+
+// -------------------------------  Field Item: Pn_PUPD_PUPD15  -----------------------------------
+// SVD Line: 7588
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 15\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.31..30> PUPD15
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_PUPD_PUPD14  -----------------------------------
+// SVD Line: 7611
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 14\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.29..28> PUPD14
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_PUPD_PUPD13  -----------------------------------
+// SVD Line: 7634
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 13\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.27..26> PUPD13
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_PUPD_PUPD12  -----------------------------------
+// SVD Line: 7657
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 12\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.25..24> PUPD12
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_PUPD_PUPD11  -----------------------------------
+// SVD Line: 7680
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 11\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.23..22> PUPD11
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_PUPD_PUPD10  -----------------------------------
+// SVD Line: 7703
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 10\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.21..20> PUPD10
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD9  -----------------------------------
+// SVD Line: 7726
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 9\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.19..18> PUPD9
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD8  -----------------------------------
+// SVD Line: 7749
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 8\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.17..16> PUPD8
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD7  -----------------------------------
+// SVD Line: 7772
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 7\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.15..14> PUPD7
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD6  -----------------------------------
+// SVD Line: 7795
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 6\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.13..12> PUPD6
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD5  -----------------------------------
+// SVD Line: 7818
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 5\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.11..10> PUPD5
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD4  -----------------------------------
+// SVD Line: 7841
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 4\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.9..8> PUPD4
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD3  -----------------------------------
+// SVD Line: 7864
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 3\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.7..6> PUPD3
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD2  -----------------------------------
+// SVD Line: 7887
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 2\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.5..4> PUPD2
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD1  -----------------------------------
+// SVD Line: 7910
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 1\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.3..2> PUPD1
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_PUPD_PUPD0  -----------------------------------
+// SVD Line: 7933
+
+//  <item> SFDITEM_FIELD__Pn_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x50000010) \nPort n Pull-Up/Down Resistor Selection 0\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_PUPD ) </loc>
+//      <o.1..0> PUPD0
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: Pn_PUPD  ------------------------------------
+// SVD Line: 7579
+
+//  <rtree> SFDITEM_REG__Pn_PUPD
+//    <name> PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x50000010) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((Pn_PUPD >> 0) & 0xFFFFFFFF), ((Pn_PUPD = (Pn_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__Pn_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: Pn_INDR  ---------------------------------
+// SVD Line: 7958
+
+unsigned int Pn_INDR __AT (0x50000014);
+
+
+
+// -------------------------------  Field Item: Pn_INDR_INDR15  -----------------------------------
+// SVD Line: 7967
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x50000014) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_INDR_INDR14  -----------------------------------
+// SVD Line: 7973
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x50000014) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_INDR_INDR13  -----------------------------------
+// SVD Line: 7979
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x50000014) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_INDR_INDR12  -----------------------------------
+// SVD Line: 7985
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x50000014) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_INDR_INDR11  -----------------------------------
+// SVD Line: 7991
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x50000014) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_INDR_INDR10  -----------------------------------
+// SVD Line: 7997
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x50000014) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR9  -----------------------------------
+// SVD Line: 8003
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x50000014) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR8  -----------------------------------
+// SVD Line: 8009
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x50000014) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR7  -----------------------------------
+// SVD Line: 8015
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x50000014) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR6  -----------------------------------
+// SVD Line: 8021
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x50000014) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR5  -----------------------------------
+// SVD Line: 8027
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x50000014) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR4  -----------------------------------
+// SVD Line: 8033
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x50000014) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR3  -----------------------------------
+// SVD Line: 8039
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x50000014) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR2  -----------------------------------
+// SVD Line: 8045
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x50000014) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR1  -----------------------------------
+// SVD Line: 8051
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x50000014) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_INDR_INDR0  -----------------------------------
+// SVD Line: 8057
+
+//  <item> SFDITEM_FIELD__Pn_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x50000014) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: Pn_INDR  ------------------------------------
+// SVD Line: 7958
+
+//  <rtree> SFDITEM_REG__Pn_INDR
+//    <name> INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x50000014) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((Pn_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__Pn_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: Pn_OUTDR  --------------------------------
+// SVD Line: 8065
+
+unsigned int Pn_OUTDR __AT (0x50000018);
+
+
+
+// ------------------------------  Field Item: Pn_OUTDR_OUTDR15  ----------------------------------
+// SVD Line: 8074
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x50000018) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: Pn_OUTDR_OUTDR14  ----------------------------------
+// SVD Line: 8080
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x50000018) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: Pn_OUTDR_OUTDR13  ----------------------------------
+// SVD Line: 8086
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x50000018) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: Pn_OUTDR_OUTDR12  ----------------------------------
+// SVD Line: 8092
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x50000018) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: Pn_OUTDR_OUTDR11  ----------------------------------
+// SVD Line: 8098
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x50000018) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: Pn_OUTDR_OUTDR10  ----------------------------------
+// SVD Line: 8104
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x50000018) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR9  ----------------------------------
+// SVD Line: 8110
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x50000018) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR8  ----------------------------------
+// SVD Line: 8116
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x50000018) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR7  ----------------------------------
+// SVD Line: 8122
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x50000018) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR6  ----------------------------------
+// SVD Line: 8128
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x50000018) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR5  ----------------------------------
+// SVD Line: 8134
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x50000018) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR4  ----------------------------------
+// SVD Line: 8140
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x50000018) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR3  ----------------------------------
+// SVD Line: 8146
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x50000018) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR2  ----------------------------------
+// SVD Line: 8152
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x50000018) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR1  ----------------------------------
+// SVD Line: 8158
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x50000018) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_OUTDR_OUTDR0  ----------------------------------
+// SVD Line: 8164
+
+//  <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x50000018) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) Pn_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: Pn_OUTDR  ------------------------------------
+// SVD Line: 8065
+
+//  <rtree> SFDITEM_REG__Pn_OUTDR
+//    <name> OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x50000018) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((Pn_OUTDR >> 0) & 0xFFFFFFFF), ((Pn_OUTDR = (Pn_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: Pn_BSR  ---------------------------------
+// SVD Line: 8172
+
+unsigned int Pn_BSR __AT (0x5000001C);
+
+
+
+// --------------------------------  Field Item: Pn_BSR_BSR15  ------------------------------------
+// SVD Line: 8181
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x5000001C) \nPort n Output Bit Set 15\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.15..15> BSR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BSR_BSR14  ------------------------------------
+// SVD Line: 8199
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x5000001C) \nPort n Output Bit Set 14\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.14..14> BSR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BSR_BSR13  ------------------------------------
+// SVD Line: 8217
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x5000001C) \nPort n Output Bit Set 13\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.13..13> BSR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BSR_BSR12  ------------------------------------
+// SVD Line: 8235
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x5000001C) \nPort n Output Bit Set 12\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.12..12> BSR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BSR_BSR11  ------------------------------------
+// SVD Line: 8253
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x5000001C) \nPort n Output Bit Set 11\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.11..11> BSR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BSR_BSR10  ------------------------------------
+// SVD Line: 8271
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x5000001C) \nPort n Output Bit Set 10\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.10..10> BSR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR9  ------------------------------------
+// SVD Line: 8289
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x5000001C) \nPort n Output Bit Set 9\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.9..9> BSR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR8  ------------------------------------
+// SVD Line: 8307
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x5000001C) \nPort n Output Bit Set 8\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.8..8> BSR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR7  ------------------------------------
+// SVD Line: 8325
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x5000001C) \nPort n Output Bit Set 7\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.7..7> BSR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR6  ------------------------------------
+// SVD Line: 8343
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x5000001C) \nPort n Output Bit Set 6\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.6..6> BSR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR5  ------------------------------------
+// SVD Line: 8361
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x5000001C) \nPort n Output Bit Set 5\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.5..5> BSR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR4  ------------------------------------
+// SVD Line: 8379
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x5000001C) \nPort n Output Bit Set 4\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.4..4> BSR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR3  ------------------------------------
+// SVD Line: 8397
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x5000001C) \nPort n Output Bit Set 3\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.3..3> BSR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR2  ------------------------------------
+// SVD Line: 8415
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x5000001C) \nPort n Output Bit Set 2\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.2..2> BSR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR1  ------------------------------------
+// SVD Line: 8433
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x5000001C) \nPort n Output Bit Set 1\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.1..1> BSR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BSR_BSR0  ------------------------------------
+// SVD Line: 8451
+
+//  <item> SFDITEM_FIELD__Pn_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x5000001C) \nPort n Output Bit Set 0\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BSR ) </loc>
+//      <o.0..0> BSR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: Pn_BSR  -------------------------------------
+// SVD Line: 8172
+
+//  <rtree> SFDITEM_REG__Pn_BSR
+//    <name> BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x5000001C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((Pn_BSR >> 0) & 0xFFFFFFFF), ((Pn_BSR = (Pn_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__Pn_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: Pn_BCR  ---------------------------------
+// SVD Line: 8471
+
+unsigned int Pn_BCR __AT (0x50000020);
+
+
+
+// --------------------------------  Field Item: Pn_BCR_BCR15  ------------------------------------
+// SVD Line: 8480
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x50000020) \nPort n Output Bit Clear 15\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.15..15> BCR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BCR_BCR14  ------------------------------------
+// SVD Line: 8498
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x50000020) \nPort n Output Bit Clear 14\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.14..14> BCR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BCR_BCR13  ------------------------------------
+// SVD Line: 8516
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x50000020) \nPort n Output Bit Clear 13\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.13..13> BCR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BCR_BCR12  ------------------------------------
+// SVD Line: 8534
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x50000020) \nPort n Output Bit Clear 12\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.12..12> BCR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BCR_BCR11  ------------------------------------
+// SVD Line: 8552
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x50000020) \nPort n Output Bit Clear 11\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.11..11> BCR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_BCR_BCR10  ------------------------------------
+// SVD Line: 8570
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x50000020) \nPort n Output Bit Clear 10\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.10..10> BCR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR9  ------------------------------------
+// SVD Line: 8588
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x50000020) \nPort n Output Bit Clear 9\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.9..9> BCR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR8  ------------------------------------
+// SVD Line: 8606
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x50000020) \nPort n Output Bit Clear 8\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.8..8> BCR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR7  ------------------------------------
+// SVD Line: 8624
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x50000020) \nPort n Output Bit Clear 7\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.7..7> BCR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR6  ------------------------------------
+// SVD Line: 8642
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x50000020) \nPort n Output Bit Clear 6\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.6..6> BCR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR5  ------------------------------------
+// SVD Line: 8660
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x50000020) \nPort n Output Bit Clear 5\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.5..5> BCR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR4  ------------------------------------
+// SVD Line: 8678
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x50000020) \nPort n Output Bit Clear 4\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.4..4> BCR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR3  ------------------------------------
+// SVD Line: 8696
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x50000020) \nPort n Output Bit Clear 3\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.3..3> BCR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR2  ------------------------------------
+// SVD Line: 8714
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x50000020) \nPort n Output Bit Clear 2\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.2..2> BCR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR1  ------------------------------------
+// SVD Line: 8732
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x50000020) \nPort n Output Bit Clear 1\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.1..1> BCR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: Pn_BCR_BCR0  ------------------------------------
+// SVD Line: 8750
+
+//  <item> SFDITEM_FIELD__Pn_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x50000020) \nPort n Output Bit Clear 0\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_BCR ) </loc>
+//      <o.0..0> BCR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: Pn_BCR  -------------------------------------
+// SVD Line: 8471
+
+//  <rtree> SFDITEM_REG__Pn_BCR
+//    <name> BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x50000020) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((Pn_BCR >> 0) & 0xFFFFFFFF), ((Pn_BCR = (Pn_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__Pn_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: Pn_OUTDMSK  -------------------------------
+// SVD Line: 8770
+
+unsigned int Pn_OUTDMSK __AT (0x50000024);
+
+
+
+// ----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK15  --------------------------------
+// SVD Line: 8779
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x50000024) \nPort n Output Data Mask 15\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK14  --------------------------------
+// SVD Line: 8797
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x50000024) \nPort n Output Data Mask 14\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK13  --------------------------------
+// SVD Line: 8815
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x50000024) \nPort n Output Data Mask 13\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK12  --------------------------------
+// SVD Line: 8833
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x50000024) \nPort n Output Data Mask 12\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK11  --------------------------------
+// SVD Line: 8851
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x50000024) \nPort n Output Data Mask 11\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK10  --------------------------------
+// SVD Line: 8869
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x50000024) \nPort n Output Data Mask 10\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK9  --------------------------------
+// SVD Line: 8887
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x50000024) \nPort n Output Data Mask 9\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK8  --------------------------------
+// SVD Line: 8905
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x50000024) \nPort n Output Data Mask 8\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK7  --------------------------------
+// SVD Line: 8923
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x50000024) \nPort n Output Data Mask 7\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK6  --------------------------------
+// SVD Line: 8941
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x50000024) \nPort n Output Data Mask 6\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK5  --------------------------------
+// SVD Line: 8959
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x50000024) \nPort n Output Data Mask 5\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK4  --------------------------------
+// SVD Line: 8977
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x50000024) \nPort n Output Data Mask 4\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK3  --------------------------------
+// SVD Line: 8995
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x50000024) \nPort n Output Data Mask 3\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK2  --------------------------------
+// SVD Line: 9013
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x50000024) \nPort n Output Data Mask 2\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK1  --------------------------------
+// SVD Line: 9031
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x50000024) \nPort n Output Data Mask 1\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: Pn_OUTDMSK_OUTDMSK0  --------------------------------
+// SVD Line: 9049
+
+//  <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x50000024) \nPort n Output Data Mask 0\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: Pn_OUTDMSK  -----------------------------------
+// SVD Line: 8770
+
+//  <rtree> SFDITEM_REG__Pn_OUTDMSK
+//    <name> OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x50000024) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((Pn_OUTDMSK >> 0) & 0xFFFFFFFF), ((Pn_OUTDMSK = (Pn_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__Pn_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: Pn_DBCR  ---------------------------------
+// SVD Line: 9069
+
+unsigned int Pn_DBCR __AT (0x50000028);
+
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBCLK  -----------------------------------
+// SVD Line: 9078
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x50000028) \nPort n Debounce Filter Sampling Clock Selection\n0 : HCLK1 = HCLK/1\n1 : HCLK4 = HCLK/4\n2 : HCLK16 = HCLK/16\n3 : HCLK64 = HCLK/64\n4 : HCLK256 = HCLK/256\n5 : HCLK1024 = HCLK/1024\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.18..16> DBCLK
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK4 = HCLK/4
+//        <2=> 2: HCLK16 = HCLK/16
+//        <3=> 3: HCLK64 = HCLK/64
+//        <4=> 4: HCLK256 = HCLK/256
+//        <5=> 5: HCLK1024 = HCLK/1024
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_DBCR_DBEN11  -----------------------------------
+// SVD Line: 9116
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN11
+//    <name> DBEN11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x50000028) \nPort n Debounce Enable 11\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.11..11> DBEN11
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: Pn_DBCR_DBEN10  -----------------------------------
+// SVD Line: 9134
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN10
+//    <name> DBEN10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x50000028) \nPort n Debounce Enable 10\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.10..10> DBEN10
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN9  -----------------------------------
+// SVD Line: 9152
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN9
+//    <name> DBEN9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x50000028) \nPort n Debounce Enable 9\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.9..9> DBEN9
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN8  -----------------------------------
+// SVD Line: 9170
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN8
+//    <name> DBEN8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x50000028) \nPort n Debounce Enable 8\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.8..8> DBEN8
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN7  -----------------------------------
+// SVD Line: 9188
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN7
+//    <name> DBEN7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x50000028) \nPort n Debounce Enable 7\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.7..7> DBEN7
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN6  -----------------------------------
+// SVD Line: 9206
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN6
+//    <name> DBEN6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x50000028) \nPort n Debounce Enable 6\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.6..6> DBEN6
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN5  -----------------------------------
+// SVD Line: 9224
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN5
+//    <name> DBEN5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x50000028) \nPort n Debounce Enable 5\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.5..5> DBEN5
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN4  -----------------------------------
+// SVD Line: 9242
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN4
+//    <name> DBEN4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x50000028) \nPort n Debounce Enable 4\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.4..4> DBEN4
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN3  -----------------------------------
+// SVD Line: 9260
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x50000028) \nPort n Debounce Enable 3\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN2  -----------------------------------
+// SVD Line: 9278
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x50000028) \nPort n Debounce Enable 2\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN1  -----------------------------------
+// SVD Line: 9296
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x50000028) \nPort n Debounce Enable 1\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: Pn_DBCR_DBEN0  -----------------------------------
+// SVD Line: 9314
+
+//  <item> SFDITEM_FIELD__Pn_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x50000028) \nPort n Debounce Enable 0\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) Pn_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: Pn_DBCR  ------------------------------------
+// SVD Line: 9069
+
+//  <rtree> SFDITEM_REG__Pn_DBCR
+//    <name> DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x50000028) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((Pn_DBCR >> 0) & 0xFFFFFFFF), ((Pn_DBCR = (Pn_DBCR & ~(0x70FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN11 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN10 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN9 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN8 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN7 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN6 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN5 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN4 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__Pn_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------------  Peripheral View: Pn  --------------------------------------
+// SVD Line: 6337
+
+//  <view> Pn
+//    <name> Pn </name>
+//    <item> SFDITEM_REG__Pn_MOD </item>
+//    <item> SFDITEM_REG__Pn_TYP </item>
+//    <item> SFDITEM_REG__Pn_AFSR1 </item>
+//    <item> SFDITEM_REG__Pn_AFSR2 </item>
+//    <item> SFDITEM_REG__Pn_PUPD </item>
+//    <item> SFDITEM_REG__Pn_INDR </item>
+//    <item> SFDITEM_REG__Pn_OUTDR </item>
+//    <item> SFDITEM_REG__Pn_BSR </item>
+//    <item> SFDITEM_REG__Pn_BCR </item>
+//    <item> SFDITEM_REG__Pn_OUTDMSK </item>
+//    <item> SFDITEM_REG__Pn_DBCR </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: PA_MOD  ---------------------------------
+// SVD Line: 6351
+
+unsigned int PA_MOD __AT (0x30000000);
+
+
+
+// --------------------------------  Field Item: PA_MOD_MODE15  -----------------------------------
+// SVD Line: 6360
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000000) \nPort n Mode Selection 15\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.31..30> MODE15
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE14  -----------------------------------
+// SVD Line: 6383
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000000) \nPort n Mode Selection 14\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.29..28> MODE14
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE13  -----------------------------------
+// SVD Line: 6406
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000000) \nPort n Mode Selection 13\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.27..26> MODE13
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE12  -----------------------------------
+// SVD Line: 6429
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000000) \nPort n Mode Selection 12\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.25..24> MODE12
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE11  -----------------------------------
+// SVD Line: 6452
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000000) \nPort n Mode Selection 11\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.23..22> MODE11
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE10  -----------------------------------
+// SVD Line: 6475
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000000) \nPort n Mode Selection 10\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.21..20> MODE10
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE9  ------------------------------------
+// SVD Line: 6498
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000000) \nPort n Mode Selection 9\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.19..18> MODE9
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE8  ------------------------------------
+// SVD Line: 6521
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000000) \nPort n Mode Selection 8\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.17..16> MODE8
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE7  ------------------------------------
+// SVD Line: 6544
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000000) \nPort n Mode Selection 7\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.15..14> MODE7
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE6  ------------------------------------
+// SVD Line: 6567
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000000) \nPort n Mode Selection 6\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.13..12> MODE6
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE5  ------------------------------------
+// SVD Line: 6590
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000000) \nPort n Mode Selection 5\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.11..10> MODE5
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE4  ------------------------------------
+// SVD Line: 6613
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000000) \nPort n Mode Selection 4\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.9..8> MODE4
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE3  ------------------------------------
+// SVD Line: 6636
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000000) \nPort n Mode Selection 3\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.7..6> MODE3
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE2  ------------------------------------
+// SVD Line: 6659
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000000) \nPort n Mode Selection 2\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.5..4> MODE2
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE1  ------------------------------------
+// SVD Line: 6682
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000000) \nPort n Mode Selection 1\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.3..2> MODE1
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_MOD_MODE0  ------------------------------------
+// SVD Line: 6705
+
+//  <item> SFDITEM_FIELD__PA_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000000) \nPort n Mode Selection 0\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_MOD ) </loc>
+//      <o.1..0> MODE0
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PA_MOD  -------------------------------------
+// SVD Line: 6351
+
+//  <rtree> SFDITEM_REG__PA_MOD
+//    <name> MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000000) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PA_MOD >> 0) & 0xFFFFFFFF), ((PA_MOD = (PA_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PA_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PA_TYP  ---------------------------------
+// SVD Line: 6730
+
+unsigned int PA_TYP __AT (0x30000004);
+
+
+
+// --------------------------------  Field Item: PA_TYP_TYP15  ------------------------------------
+// SVD Line: 6739
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000004) \nPort n Output Type Selection 15\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.15..15> TYP15
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_TYP_TYP14  ------------------------------------
+// SVD Line: 6757
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000004) \nPort n Output Type Selection 14\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.14..14> TYP14
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_TYP_TYP13  ------------------------------------
+// SVD Line: 6775
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000004) \nPort n Output Type Selection 13\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.13..13> TYP13
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_TYP_TYP12  ------------------------------------
+// SVD Line: 6793
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000004) \nPort n Output Type Selection 12\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.12..12> TYP12
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_TYP_TYP11  ------------------------------------
+// SVD Line: 6811
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000004) \nPort n Output Type Selection 11\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.11..11> TYP11
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_TYP_TYP10  ------------------------------------
+// SVD Line: 6829
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000004) \nPort n Output Type Selection 10\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.10..10> TYP10
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP9  ------------------------------------
+// SVD Line: 6847
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000004) \nPort n Output Type Selection 9\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.9..9> TYP9
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP8  ------------------------------------
+// SVD Line: 6865
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000004) \nPort n Output Type Selection 8\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.8..8> TYP8
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP7  ------------------------------------
+// SVD Line: 6883
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000004) \nPort n Output Type Selection 7\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.7..7> TYP7
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP6  ------------------------------------
+// SVD Line: 6901
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000004) \nPort n Output Type Selection 6\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.6..6> TYP6
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP5  ------------------------------------
+// SVD Line: 6919
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000004) \nPort n Output Type Selection 5\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.5..5> TYP5
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP4  ------------------------------------
+// SVD Line: 6937
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000004) \nPort n Output Type Selection 4\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.4..4> TYP4
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP3  ------------------------------------
+// SVD Line: 6955
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000004) \nPort n Output Type Selection 3\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.3..3> TYP3
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP2  ------------------------------------
+// SVD Line: 6973
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000004) \nPort n Output Type Selection 2\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.2..2> TYP2
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP1  ------------------------------------
+// SVD Line: 6991
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000004) \nPort n Output Type Selection 1\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.1..1> TYP1
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_TYP_TYP0  ------------------------------------
+// SVD Line: 7009
+
+//  <item> SFDITEM_FIELD__PA_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000004) \nPort n Output Type Selection 0\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_TYP ) </loc>
+//      <o.0..0> TYP0
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PA_TYP  -------------------------------------
+// SVD Line: 6730
+
+//  <rtree> SFDITEM_REG__PA_TYP
+//    <name> TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000004) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PA_TYP >> 0) & 0xFFFFFFFF), ((PA_TYP = (PA_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PA_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PA_AFSR1  --------------------------------
+// SVD Line: 7029
+
+unsigned int PA_AFSR1 __AT (0x30000008);
+
+
+
+// -------------------------------  Field Item: PA_AFSR1_AFSR7  -----------------------------------
+// SVD Line: 7038
+
+//  <item> SFDITEM_FIELD__PA_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000008) \nPort n Alternative Function Selection 7\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR1 ) </loc>
+//      <o.31..28> AFSR7
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR1_AFSR6  -----------------------------------
+// SVD Line: 7071
+
+//  <item> SFDITEM_FIELD__PA_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000008) \nPort n Alternative Function Selection 6\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR1 ) </loc>
+//      <o.27..24> AFSR6
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR1_AFSR5  -----------------------------------
+// SVD Line: 7104
+
+//  <item> SFDITEM_FIELD__PA_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000008) \nPort n Alternative Function Selection 5\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR1 ) </loc>
+//      <o.23..20> AFSR5
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR1_AFSR4  -----------------------------------
+// SVD Line: 7137
+
+//  <item> SFDITEM_FIELD__PA_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000008) \nPort n Alternative Function Selection 4\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR1 ) </loc>
+//      <o.19..16> AFSR4
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR1_AFSR3  -----------------------------------
+// SVD Line: 7170
+
+//  <item> SFDITEM_FIELD__PA_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000008) \nPort n Alternative Function Selection 3\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR1 ) </loc>
+//      <o.15..12> AFSR3
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR1_AFSR2  -----------------------------------
+// SVD Line: 7203
+
+//  <item> SFDITEM_FIELD__PA_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000008) \nPort n Alternative Function Selection 2\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR1 ) </loc>
+//      <o.11..8> AFSR2
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR1_AFSR1  -----------------------------------
+// SVD Line: 7236
+
+//  <item> SFDITEM_FIELD__PA_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000008) \nPort n Alternative Function Selection 1\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR1 ) </loc>
+//      <o.7..4> AFSR1
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR1_AFSR0  -----------------------------------
+// SVD Line: 7269
+
+//  <item> SFDITEM_FIELD__PA_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000008) \nPort n Alternative Function Selection 0\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR1 ) </loc>
+//      <o.3..0> AFSR0
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PA_AFSR1  ------------------------------------
+// SVD Line: 7029
+
+//  <rtree> SFDITEM_REG__PA_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000008) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PA_AFSR1 >> 0) & 0xFFFFFFFF), ((PA_AFSR1 = (PA_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PA_AFSR2  --------------------------------
+// SVD Line: 7304
+
+unsigned int PA_AFSR2 __AT (0x3000000C);
+
+
+
+// -------------------------------  Field Item: PA_AFSR2_AFSR15  ----------------------------------
+// SVD Line: 7313
+
+//  <item> SFDITEM_FIELD__PA_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x3000000C) \nPort n Alternative Function Selection 15\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR2 ) </loc>
+//      <o.31..28> AFSR15
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR2_AFSR14  ----------------------------------
+// SVD Line: 7346
+
+//  <item> SFDITEM_FIELD__PA_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x3000000C) \nPort n Alternative Function Selection 14\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR2 ) </loc>
+//      <o.27..24> AFSR14
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR2_AFSR13  ----------------------------------
+// SVD Line: 7379
+
+//  <item> SFDITEM_FIELD__PA_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x3000000C) \nPort n Alternative Function Selection 13\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR2 ) </loc>
+//      <o.23..20> AFSR13
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR2_AFSR12  ----------------------------------
+// SVD Line: 7412
+
+//  <item> SFDITEM_FIELD__PA_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000000C) \nPort n Alternative Function Selection 12\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR2 ) </loc>
+//      <o.19..16> AFSR12
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR2_AFSR11  ----------------------------------
+// SVD Line: 7445
+
+//  <item> SFDITEM_FIELD__PA_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000000C) \nPort n Alternative Function Selection 11\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR2 ) </loc>
+//      <o.15..12> AFSR11
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR2_AFSR10  ----------------------------------
+// SVD Line: 7478
+
+//  <item> SFDITEM_FIELD__PA_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000000C) \nPort n Alternative Function Selection 10\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR2 ) </loc>
+//      <o.11..8> AFSR10
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR2_AFSR9  -----------------------------------
+// SVD Line: 7511
+
+//  <item> SFDITEM_FIELD__PA_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000000C) \nPort n Alternative Function Selection 9\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR2 ) </loc>
+//      <o.7..4> AFSR9
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_AFSR2_AFSR8  -----------------------------------
+// SVD Line: 7544
+
+//  <item> SFDITEM_FIELD__PA_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000000C) \nPort n Alternative Function Selection 8\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_AFSR2 ) </loc>
+//      <o.3..0> AFSR8
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PA_AFSR2  ------------------------------------
+// SVD Line: 7304
+
+//  <rtree> SFDITEM_REG__PA_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000000C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PA_AFSR2 >> 0) & 0xFFFFFFFF), ((PA_AFSR2 = (PA_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PA_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PA_PUPD  ---------------------------------
+// SVD Line: 7579
+
+unsigned int PA_PUPD __AT (0x30000010);
+
+
+
+// -------------------------------  Field Item: PA_PUPD_PUPD15  -----------------------------------
+// SVD Line: 7588
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 15\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.31..30> PUPD15
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PUPD_PUPD14  -----------------------------------
+// SVD Line: 7611
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 14\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.29..28> PUPD14
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PUPD_PUPD13  -----------------------------------
+// SVD Line: 7634
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 13\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.27..26> PUPD13
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PUPD_PUPD12  -----------------------------------
+// SVD Line: 7657
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 12\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.25..24> PUPD12
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PUPD_PUPD11  -----------------------------------
+// SVD Line: 7680
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 11\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.23..22> PUPD11
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PUPD_PUPD10  -----------------------------------
+// SVD Line: 7703
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 10\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.21..20> PUPD10
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD9  -----------------------------------
+// SVD Line: 7726
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 9\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.19..18> PUPD9
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD8  -----------------------------------
+// SVD Line: 7749
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 8\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.17..16> PUPD8
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD7  -----------------------------------
+// SVD Line: 7772
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 7\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.15..14> PUPD7
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD6  -----------------------------------
+// SVD Line: 7795
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 6\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.13..12> PUPD6
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD5  -----------------------------------
+// SVD Line: 7818
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 5\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.11..10> PUPD5
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD4  -----------------------------------
+// SVD Line: 7841
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 4\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.9..8> PUPD4
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD3  -----------------------------------
+// SVD Line: 7864
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 3\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.7..6> PUPD3
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD2  -----------------------------------
+// SVD Line: 7887
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 2\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.5..4> PUPD2
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD1  -----------------------------------
+// SVD Line: 7910
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 1\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.3..2> PUPD1
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_PUPD_PUPD0  -----------------------------------
+// SVD Line: 7933
+
+//  <item> SFDITEM_FIELD__PA_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000010) \nPort n Pull-Up/Down Resistor Selection 0\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_PUPD ) </loc>
+//      <o.1..0> PUPD0
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PA_PUPD  ------------------------------------
+// SVD Line: 7579
+
+//  <rtree> SFDITEM_REG__PA_PUPD
+//    <name> PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PA_PUPD >> 0) & 0xFFFFFFFF), ((PA_PUPD = (PA_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PA_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PA_INDR  ---------------------------------
+// SVD Line: 7958
+
+unsigned int PA_INDR __AT (0x30000014);
+
+
+
+// -------------------------------  Field Item: PA_INDR_INDR15  -----------------------------------
+// SVD Line: 7967
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x30000014) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_INDR_INDR14  -----------------------------------
+// SVD Line: 7973
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x30000014) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_INDR_INDR13  -----------------------------------
+// SVD Line: 7979
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x30000014) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_INDR_INDR12  -----------------------------------
+// SVD Line: 7985
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000014) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_INDR_INDR11  -----------------------------------
+// SVD Line: 7991
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000014) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_INDR_INDR10  -----------------------------------
+// SVD Line: 7997
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000014) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR9  -----------------------------------
+// SVD Line: 8003
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000014) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR8  -----------------------------------
+// SVD Line: 8009
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000014) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR7  -----------------------------------
+// SVD Line: 8015
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000014) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR6  -----------------------------------
+// SVD Line: 8021
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000014) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR5  -----------------------------------
+// SVD Line: 8027
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000014) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR4  -----------------------------------
+// SVD Line: 8033
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000014) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR3  -----------------------------------
+// SVD Line: 8039
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000014) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR2  -----------------------------------
+// SVD Line: 8045
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000014) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR1  -----------------------------------
+// SVD Line: 8051
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000014) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_INDR_INDR0  -----------------------------------
+// SVD Line: 8057
+
+//  <item> SFDITEM_FIELD__PA_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000014) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PA_INDR  ------------------------------------
+// SVD Line: 7958
+
+//  <rtree> SFDITEM_REG__PA_INDR
+//    <name> INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000014) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PA_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PA_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PA_OUTDR  --------------------------------
+// SVD Line: 8065
+
+unsigned int PA_OUTDR __AT (0x30000018);
+
+
+
+// ------------------------------  Field Item: PA_OUTDR_OUTDR15  ----------------------------------
+// SVD Line: 8074
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000018) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_OUTDR_OUTDR14  ----------------------------------
+// SVD Line: 8080
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000018) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_OUTDR_OUTDR13  ----------------------------------
+// SVD Line: 8086
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000018) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_OUTDR_OUTDR12  ----------------------------------
+// SVD Line: 8092
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000018) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_OUTDR_OUTDR11  ----------------------------------
+// SVD Line: 8098
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000018) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_OUTDR_OUTDR10  ----------------------------------
+// SVD Line: 8104
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000018) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR9  ----------------------------------
+// SVD Line: 8110
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000018) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR8  ----------------------------------
+// SVD Line: 8116
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000018) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR7  ----------------------------------
+// SVD Line: 8122
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000018) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR6  ----------------------------------
+// SVD Line: 8128
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000018) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR5  ----------------------------------
+// SVD Line: 8134
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000018) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR4  ----------------------------------
+// SVD Line: 8140
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000018) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR3  ----------------------------------
+// SVD Line: 8146
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000018) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR2  ----------------------------------
+// SVD Line: 8152
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000018) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR1  ----------------------------------
+// SVD Line: 8158
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000018) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_OUTDR_OUTDR0  ----------------------------------
+// SVD Line: 8164
+
+//  <item> SFDITEM_FIELD__PA_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000018) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PA_OUTDR  ------------------------------------
+// SVD Line: 8065
+
+//  <rtree> SFDITEM_REG__PA_OUTDR
+//    <name> OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000018) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PA_OUTDR >> 0) & 0xFFFFFFFF), ((PA_OUTDR = (PA_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PA_BSR  ---------------------------------
+// SVD Line: 8172
+
+unsigned int PA_BSR __AT (0x3000001C);
+
+
+
+// --------------------------------  Field Item: PA_BSR_BSR15  ------------------------------------
+// SVD Line: 8181
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x3000001C) \nPort n Output Bit Set 15\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.15..15> BSR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BSR_BSR14  ------------------------------------
+// SVD Line: 8199
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x3000001C) \nPort n Output Bit Set 14\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.14..14> BSR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BSR_BSR13  ------------------------------------
+// SVD Line: 8217
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x3000001C) \nPort n Output Bit Set 13\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.13..13> BSR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BSR_BSR12  ------------------------------------
+// SVD Line: 8235
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000001C) \nPort n Output Bit Set 12\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.12..12> BSR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BSR_BSR11  ------------------------------------
+// SVD Line: 8253
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000001C) \nPort n Output Bit Set 11\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.11..11> BSR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BSR_BSR10  ------------------------------------
+// SVD Line: 8271
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000001C) \nPort n Output Bit Set 10\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.10..10> BSR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR9  ------------------------------------
+// SVD Line: 8289
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000001C) \nPort n Output Bit Set 9\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.9..9> BSR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR8  ------------------------------------
+// SVD Line: 8307
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000001C) \nPort n Output Bit Set 8\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.8..8> BSR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR7  ------------------------------------
+// SVD Line: 8325
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000001C) \nPort n Output Bit Set 7\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.7..7> BSR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR6  ------------------------------------
+// SVD Line: 8343
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000001C) \nPort n Output Bit Set 6\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.6..6> BSR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR5  ------------------------------------
+// SVD Line: 8361
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000001C) \nPort n Output Bit Set 5\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.5..5> BSR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR4  ------------------------------------
+// SVD Line: 8379
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000001C) \nPort n Output Bit Set 4\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.4..4> BSR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR3  ------------------------------------
+// SVD Line: 8397
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000001C) \nPort n Output Bit Set 3\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.3..3> BSR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR2  ------------------------------------
+// SVD Line: 8415
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000001C) \nPort n Output Bit Set 2\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.2..2> BSR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR1  ------------------------------------
+// SVD Line: 8433
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000001C) \nPort n Output Bit Set 1\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.1..1> BSR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BSR_BSR0  ------------------------------------
+// SVD Line: 8451
+
+//  <item> SFDITEM_FIELD__PA_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000001C) \nPort n Output Bit Set 0\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BSR ) </loc>
+//      <o.0..0> BSR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PA_BSR  -------------------------------------
+// SVD Line: 8172
+
+//  <rtree> SFDITEM_REG__PA_BSR
+//    <name> BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000001C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PA_BSR >> 0) & 0xFFFFFFFF), ((PA_BSR = (PA_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PA_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PA_BCR  ---------------------------------
+// SVD Line: 8471
+
+unsigned int PA_BCR __AT (0x30000020);
+
+
+
+// --------------------------------  Field Item: PA_BCR_BCR15  ------------------------------------
+// SVD Line: 8480
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x30000020) \nPort n Output Bit Clear 15\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.15..15> BCR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BCR_BCR14  ------------------------------------
+// SVD Line: 8498
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x30000020) \nPort n Output Bit Clear 14\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.14..14> BCR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BCR_BCR13  ------------------------------------
+// SVD Line: 8516
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x30000020) \nPort n Output Bit Clear 13\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.13..13> BCR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BCR_BCR12  ------------------------------------
+// SVD Line: 8534
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000020) \nPort n Output Bit Clear 12\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.12..12> BCR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BCR_BCR11  ------------------------------------
+// SVD Line: 8552
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000020) \nPort n Output Bit Clear 11\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.11..11> BCR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_BCR_BCR10  ------------------------------------
+// SVD Line: 8570
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000020) \nPort n Output Bit Clear 10\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.10..10> BCR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR9  ------------------------------------
+// SVD Line: 8588
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000020) \nPort n Output Bit Clear 9\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.9..9> BCR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR8  ------------------------------------
+// SVD Line: 8606
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000020) \nPort n Output Bit Clear 8\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.8..8> BCR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR7  ------------------------------------
+// SVD Line: 8624
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000020) \nPort n Output Bit Clear 7\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.7..7> BCR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR6  ------------------------------------
+// SVD Line: 8642
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000020) \nPort n Output Bit Clear 6\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.6..6> BCR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR5  ------------------------------------
+// SVD Line: 8660
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000020) \nPort n Output Bit Clear 5\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.5..5> BCR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR4  ------------------------------------
+// SVD Line: 8678
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000020) \nPort n Output Bit Clear 4\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.4..4> BCR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR3  ------------------------------------
+// SVD Line: 8696
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000020) \nPort n Output Bit Clear 3\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.3..3> BCR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR2  ------------------------------------
+// SVD Line: 8714
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000020) \nPort n Output Bit Clear 2\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.2..2> BCR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR1  ------------------------------------
+// SVD Line: 8732
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000020) \nPort n Output Bit Clear 1\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.1..1> BCR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PA_BCR_BCR0  ------------------------------------
+// SVD Line: 8750
+
+//  <item> SFDITEM_FIELD__PA_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000020) \nPort n Output Bit Clear 0\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_BCR ) </loc>
+//      <o.0..0> BCR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PA_BCR  -------------------------------------
+// SVD Line: 8471
+
+//  <rtree> SFDITEM_REG__PA_BCR
+//    <name> BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000020) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PA_BCR >> 0) & 0xFFFFFFFF), ((PA_BCR = (PA_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PA_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PA_OUTDMSK  -------------------------------
+// SVD Line: 8770
+
+unsigned int PA_OUTDMSK __AT (0x30000024);
+
+
+
+// ----------------------------  Field Item: PA_OUTDMSK_OUTDMSK15  --------------------------------
+// SVD Line: 8779
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000024) \nPort n Output Data Mask 15\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PA_OUTDMSK_OUTDMSK14  --------------------------------
+// SVD Line: 8797
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000024) \nPort n Output Data Mask 14\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PA_OUTDMSK_OUTDMSK13  --------------------------------
+// SVD Line: 8815
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000024) \nPort n Output Data Mask 13\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PA_OUTDMSK_OUTDMSK12  --------------------------------
+// SVD Line: 8833
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000024) \nPort n Output Data Mask 12\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PA_OUTDMSK_OUTDMSK11  --------------------------------
+// SVD Line: 8851
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000024) \nPort n Output Data Mask 11\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PA_OUTDMSK_OUTDMSK10  --------------------------------
+// SVD Line: 8869
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000024) \nPort n Output Data Mask 10\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK9  --------------------------------
+// SVD Line: 8887
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000024) \nPort n Output Data Mask 9\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK8  --------------------------------
+// SVD Line: 8905
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000024) \nPort n Output Data Mask 8\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK7  --------------------------------
+// SVD Line: 8923
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000024) \nPort n Output Data Mask 7\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK6  --------------------------------
+// SVD Line: 8941
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000024) \nPort n Output Data Mask 6\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK5  --------------------------------
+// SVD Line: 8959
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000024) \nPort n Output Data Mask 5\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK4  --------------------------------
+// SVD Line: 8977
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000024) \nPort n Output Data Mask 4\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK3  --------------------------------
+// SVD Line: 8995
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000024) \nPort n Output Data Mask 3\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK2  --------------------------------
+// SVD Line: 9013
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000024) \nPort n Output Data Mask 2\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK1  --------------------------------
+// SVD Line: 9031
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000024) \nPort n Output Data Mask 1\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_OUTDMSK_OUTDMSK0  --------------------------------
+// SVD Line: 9049
+
+//  <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000024) \nPort n Output Data Mask 0\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PA_OUTDMSK  -----------------------------------
+// SVD Line: 8770
+
+//  <rtree> SFDITEM_REG__PA_OUTDMSK
+//    <name> OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000024) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PA_OUTDMSK >> 0) & 0xFFFFFFFF), ((PA_OUTDMSK = (PA_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PA_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PA_DBCR  ---------------------------------
+// SVD Line: 9069
+
+unsigned int PA_DBCR __AT (0x30000028);
+
+
+
+// --------------------------------  Field Item: PA_DBCR_DBCLK  -----------------------------------
+// SVD Line: 9078
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000028) \nPort n Debounce Filter Sampling Clock Selection\n0 : HCLK1 = HCLK/1\n1 : HCLK4 = HCLK/4\n2 : HCLK16 = HCLK/16\n3 : HCLK64 = HCLK/64\n4 : HCLK256 = HCLK/256\n5 : HCLK1024 = HCLK/1024\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.18..16> DBCLK
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK4 = HCLK/4
+//        <2=> 2: HCLK16 = HCLK/16
+//        <3=> 3: HCLK64 = HCLK/64
+//        <4=> 4: HCLK256 = HCLK/256
+//        <5=> 5: HCLK1024 = HCLK/1024
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_DBCR_DBEN11  -----------------------------------
+// SVD Line: 9116
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN11
+//    <name> DBEN11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000028) \nPort n Debounce Enable 11\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.11..11> DBEN11
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_DBCR_DBEN10  -----------------------------------
+// SVD Line: 9134
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN10
+//    <name> DBEN10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000028) \nPort n Debounce Enable 10\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.10..10> DBEN10
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN9  -----------------------------------
+// SVD Line: 9152
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN9
+//    <name> DBEN9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000028) \nPort n Debounce Enable 9\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.9..9> DBEN9
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN8  -----------------------------------
+// SVD Line: 9170
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN8
+//    <name> DBEN8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000028) \nPort n Debounce Enable 8\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.8..8> DBEN8
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN7  -----------------------------------
+// SVD Line: 9188
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN7
+//    <name> DBEN7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000028) \nPort n Debounce Enable 7\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.7..7> DBEN7
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN6  -----------------------------------
+// SVD Line: 9206
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN6
+//    <name> DBEN6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000028) \nPort n Debounce Enable 6\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.6..6> DBEN6
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN5  -----------------------------------
+// SVD Line: 9224
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN5
+//    <name> DBEN5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000028) \nPort n Debounce Enable 5\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.5..5> DBEN5
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN4  -----------------------------------
+// SVD Line: 9242
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN4
+//    <name> DBEN4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000028) \nPort n Debounce Enable 4\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.4..4> DBEN4
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN3  -----------------------------------
+// SVD Line: 9260
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000028) \nPort n Debounce Enable 3\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN2  -----------------------------------
+// SVD Line: 9278
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000028) \nPort n Debounce Enable 2\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN1  -----------------------------------
+// SVD Line: 9296
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000028) \nPort n Debounce Enable 1\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PA_DBCR_DBEN0  -----------------------------------
+// SVD Line: 9314
+
+//  <item> SFDITEM_FIELD__PA_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000028) \nPort n Debounce Enable 0\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PA_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PA_DBCR  ------------------------------------
+// SVD Line: 9069
+
+//  <rtree> SFDITEM_REG__PA_DBCR
+//    <name> DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000028) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PA_DBCR >> 0) & 0xFFFFFFFF), ((PA_DBCR = (PA_DBCR & ~(0x70FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN11 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN10 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN9 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN8 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN7 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN6 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN5 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN4 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PA_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PA_PA_MOD  --------------------------------
+// SVD Line: 9350
+
+unsigned int PA_PA_MOD __AT (0x30000000);
+
+
+
+// ------------------------------  Field Item: PA_PA_MOD_MODE11  ----------------------------------
+// SVD Line: 9360
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000000) Port n Mode Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 22) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_MOD_MODE10  ----------------------------------
+// SVD Line: 9366
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000000) Port n Mode Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 20) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE9  ----------------------------------
+// SVD Line: 9372
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000000) Port n Mode Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 18) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE8  ----------------------------------
+// SVD Line: 9378
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000000) Port n Mode Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 16) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE7  ----------------------------------
+// SVD Line: 9384
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000000) Port n Mode Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 14) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE6  ----------------------------------
+// SVD Line: 9390
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000000) Port n Mode Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 12) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE5  ----------------------------------
+// SVD Line: 9396
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000000) Port n Mode Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 10) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE4  ----------------------------------
+// SVD Line: 9402
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000000) Port n Mode Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 8) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE3  ----------------------------------
+// SVD Line: 9408
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000000) Port n Mode Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 6) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE2  ----------------------------------
+// SVD Line: 9414
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000000) Port n Mode Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 4) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE1  ----------------------------------
+// SVD Line: 9420
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000000) Port n Mode Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 2) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_MOD_MODE0  ----------------------------------
+// SVD Line: 9426
+
+//  <item> SFDITEM_FIELD__PA_PA_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000000) Port n Mode Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_MOD >> 0) & 0x3), ((PA_PA_MOD = (PA_PA_MOD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PA_PA_MOD  -----------------------------------
+// SVD Line: 9350
+
+//  <rtree> SFDITEM_REG__PA_PA_MOD
+//    <name> PA_MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000000) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PA_PA_MOD >> 0) & 0xFFFFFFFF), ((PA_PA_MOD = (PA_PA_MOD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PA_PA_TYP  --------------------------------
+// SVD Line: 9434
+
+unsigned int PA_PA_TYP __AT (0x30000004);
+
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP11  ----------------------------------
+// SVD Line: 9444
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000004) Port n Output Type Selection 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.11..11> TYP11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP10  ----------------------------------
+// SVD Line: 9450
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000004) Port n Output Type Selection 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.10..10> TYP10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP9  -----------------------------------
+// SVD Line: 9456
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000004) Port n Output Type Selection 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.9..9> TYP9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP8  -----------------------------------
+// SVD Line: 9462
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000004) Port n Output Type Selection 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.8..8> TYP8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP7  -----------------------------------
+// SVD Line: 9468
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000004) Port n Output Type Selection 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.7..7> TYP7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP6  -----------------------------------
+// SVD Line: 9474
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000004) Port n Output Type Selection 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.6..6> TYP6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP5  -----------------------------------
+// SVD Line: 9480
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000004) Port n Output Type Selection 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.5..5> TYP5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP4  -----------------------------------
+// SVD Line: 9486
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000004) Port n Output Type Selection 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.4..4> TYP4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP3  -----------------------------------
+// SVD Line: 9492
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000004) Port n Output Type Selection 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.3..3> TYP3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP2  -----------------------------------
+// SVD Line: 9498
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000004) Port n Output Type Selection 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.2..2> TYP2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP1  -----------------------------------
+// SVD Line: 9504
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000004) Port n Output Type Selection 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.1..1> TYP1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_TYP_TYP0  -----------------------------------
+// SVD Line: 9510
+
+//  <item> SFDITEM_FIELD__PA_PA_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000004) Port n Output Type Selection 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_TYP ) </loc>
+//      <o.0..0> TYP0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PA_PA_TYP  -----------------------------------
+// SVD Line: 9434
+
+//  <rtree> SFDITEM_REG__PA_PA_TYP
+//    <name> PA_TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000004) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PA_PA_TYP >> 0) & 0xFFFFFFFF), ((PA_PA_TYP = (PA_PA_TYP & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PA_PA_AFSR1  -------------------------------
+// SVD Line: 9518
+
+unsigned int PA_PA_AFSR1 __AT (0x30000008);
+
+
+
+// ------------------------------  Field Item: PA_PA_AFSR1_AFSR7  ---------------------------------
+// SVD Line: 9528
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000008) Port n Alternative Function Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR1 >> 28) & 0xF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR1_AFSR6  ---------------------------------
+// SVD Line: 9534
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000008) Port n Alternative Function Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR1 >> 24) & 0xF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR1_AFSR5  ---------------------------------
+// SVD Line: 9540
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000008) Port n Alternative Function Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR1 >> 20) & 0xF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR1_AFSR4  ---------------------------------
+// SVD Line: 9546
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000008) Port n Alternative Function Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR1 >> 16) & 0xF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR1_AFSR3  ---------------------------------
+// SVD Line: 9552
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000008) Port n Alternative Function Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR1 >> 12) & 0xF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR1_AFSR2  ---------------------------------
+// SVD Line: 9558
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000008) Port n Alternative Function Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR1 >> 8) & 0xF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR1_AFSR1  ---------------------------------
+// SVD Line: 9564
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000008) Port n Alternative Function Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR1 >> 4) & 0xF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR1_AFSR0  ---------------------------------
+// SVD Line: 9570
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000008) Port n Alternative Function Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR1 >> 0) & 0xF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PA_PA_AFSR1  ----------------------------------
+// SVD Line: 9518
+
+//  <rtree> SFDITEM_REG__PA_PA_AFSR1
+//    <name> PA_AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000008) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PA_PA_AFSR1 >> 0) & 0xFFFFFFFF), ((PA_PA_AFSR1 = (PA_PA_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PA_PA_AFSR2  -------------------------------
+// SVD Line: 9578
+
+unsigned int PA_PA_AFSR2 __AT (0x3000000C);
+
+
+
+// -----------------------------  Field Item: PA_PA_AFSR2_AFSR11  ---------------------------------
+// SVD Line: 9588
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000000C) Port n Alternative Function Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR2 >> 12) & 0xF), ((PA_PA_AFSR2 = (PA_PA_AFSR2 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_AFSR2_AFSR10  ---------------------------------
+// SVD Line: 9594
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000000C) Port n Alternative Function Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR2 >> 8) & 0xF), ((PA_PA_AFSR2 = (PA_PA_AFSR2 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR2_AFSR9  ---------------------------------
+// SVD Line: 9600
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000000C) Port n Alternative Function Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR2 >> 4) & 0xF), ((PA_PA_AFSR2 = (PA_PA_AFSR2 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_AFSR2_AFSR8  ---------------------------------
+// SVD Line: 9606
+
+//  <item> SFDITEM_FIELD__PA_PA_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000000C) Port n Alternative Function Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_AFSR2 >> 0) & 0xF), ((PA_PA_AFSR2 = (PA_PA_AFSR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PA_PA_AFSR2  ----------------------------------
+// SVD Line: 9578
+
+//  <rtree> SFDITEM_REG__PA_PA_AFSR2
+//    <name> PA_AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000000C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PA_PA_AFSR2 >> 0) & 0xFFFFFFFF), ((PA_PA_AFSR2 = (PA_PA_AFSR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PA_PA_PUPD  -------------------------------
+// SVD Line: 9614
+
+unsigned int PA_PA_PUPD __AT (0x30000010);
+
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD11  ---------------------------------
+// SVD Line: 9624
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 22) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD10  ---------------------------------
+// SVD Line: 9630
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 20) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD9  ----------------------------------
+// SVD Line: 9636
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 18) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD8  ----------------------------------
+// SVD Line: 9642
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 16) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD7  ----------------------------------
+// SVD Line: 9648
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 14) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD6  ----------------------------------
+// SVD Line: 9654
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 12) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD5  ----------------------------------
+// SVD Line: 9660
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 10) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD4  ----------------------------------
+// SVD Line: 9666
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 8) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD3  ----------------------------------
+// SVD Line: 9672
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 6) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD2  ----------------------------------
+// SVD Line: 9678
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 4) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD1  ----------------------------------
+// SVD Line: 9684
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 2) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_PUPD_PUPD0  ----------------------------------
+// SVD Line: 9690
+
+//  <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PA_PA_PUPD >> 0) & 0x3), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PA_PA_PUPD  -----------------------------------
+// SVD Line: 9614
+
+//  <rtree> SFDITEM_REG__PA_PA_PUPD
+//    <name> PA_PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000010) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PA_PA_PUPD >> 0) & 0xFFFFFFFF), ((PA_PA_PUPD = (PA_PA_PUPD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PA_PA_INDR  -------------------------------
+// SVD Line: 9698
+
+unsigned int PA_PA_INDR __AT (0x30000014);
+
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR11  ---------------------------------
+// SVD Line: 9708
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000014) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR10  ---------------------------------
+// SVD Line: 9714
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000014) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR9  ----------------------------------
+// SVD Line: 9720
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000014) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR8  ----------------------------------
+// SVD Line: 9726
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000014) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR7  ----------------------------------
+// SVD Line: 9732
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000014) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR6  ----------------------------------
+// SVD Line: 9738
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000014) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR5  ----------------------------------
+// SVD Line: 9744
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000014) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR4  ----------------------------------
+// SVD Line: 9750
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000014) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR3  ----------------------------------
+// SVD Line: 9756
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000014) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR2  ----------------------------------
+// SVD Line: 9762
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000014) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR1  ----------------------------------
+// SVD Line: 9768
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000014) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PA_PA_INDR_INDR0  ----------------------------------
+// SVD Line: 9774
+
+//  <item> SFDITEM_FIELD__PA_PA_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000014) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PA_PA_INDR  -----------------------------------
+// SVD Line: 9698
+
+//  <rtree> SFDITEM_REG__PA_PA_INDR
+//    <name> PA_INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000014) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PA_PA_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PA_PA_OUTDR  -------------------------------
+// SVD Line: 9782
+
+unsigned int PA_PA_OUTDR __AT (0x30000018);
+
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR11  --------------------------------
+// SVD Line: 9792
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000018) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR10  --------------------------------
+// SVD Line: 9798
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000018) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR9  ---------------------------------
+// SVD Line: 9804
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000018) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR8  ---------------------------------
+// SVD Line: 9810
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000018) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR7  ---------------------------------
+// SVD Line: 9816
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000018) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR6  ---------------------------------
+// SVD Line: 9822
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000018) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR5  ---------------------------------
+// SVD Line: 9828
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000018) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR4  ---------------------------------
+// SVD Line: 9834
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000018) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR3  ---------------------------------
+// SVD Line: 9840
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000018) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR2  ---------------------------------
+// SVD Line: 9846
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000018) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR1  ---------------------------------
+// SVD Line: 9852
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000018) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PA_PA_OUTDR_OUTDR0  ---------------------------------
+// SVD Line: 9858
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000018) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PA_PA_OUTDR  ----------------------------------
+// SVD Line: 9782
+
+//  <rtree> SFDITEM_REG__PA_PA_OUTDR
+//    <name> PA_OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000018) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PA_PA_OUTDR >> 0) & 0xFFFFFFFF), ((PA_PA_OUTDR = (PA_PA_OUTDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PA_PA_BSR  --------------------------------
+// SVD Line: 9866
+
+unsigned int PA_PA_BSR __AT (0x3000001C);
+
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR11  ----------------------------------
+// SVD Line: 9876
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000001C) Port n Output Bit Set 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.11..11> BSR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR10  ----------------------------------
+// SVD Line: 9882
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000001C) Port n Output Bit Set 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.10..10> BSR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR9  -----------------------------------
+// SVD Line: 9888
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000001C) Port n Output Bit Set 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.9..9> BSR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR8  -----------------------------------
+// SVD Line: 9894
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000001C) Port n Output Bit Set 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.8..8> BSR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR7  -----------------------------------
+// SVD Line: 9900
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000001C) Port n Output Bit Set 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.7..7> BSR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR6  -----------------------------------
+// SVD Line: 9906
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000001C) Port n Output Bit Set 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.6..6> BSR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR5  -----------------------------------
+// SVD Line: 9912
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000001C) Port n Output Bit Set 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.5..5> BSR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR4  -----------------------------------
+// SVD Line: 9918
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000001C) Port n Output Bit Set 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.4..4> BSR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR3  -----------------------------------
+// SVD Line: 9924
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000001C) Port n Output Bit Set 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.3..3> BSR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR2  -----------------------------------
+// SVD Line: 9930
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000001C) Port n Output Bit Set 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.2..2> BSR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR1  -----------------------------------
+// SVD Line: 9936
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000001C) Port n Output Bit Set 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.1..1> BSR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BSR_BSR0  -----------------------------------
+// SVD Line: 9942
+
+//  <item> SFDITEM_FIELD__PA_PA_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000001C) Port n Output Bit Set 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BSR ) </loc>
+//      <o.0..0> BSR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PA_PA_BSR  -----------------------------------
+// SVD Line: 9866
+
+//  <rtree> SFDITEM_REG__PA_PA_BSR
+//    <name> PA_BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000001C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PA_PA_BSR >> 0) & 0xFFFFFFFF), ((PA_PA_BSR = (PA_PA_BSR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PA_PA_BCR  --------------------------------
+// SVD Line: 9950
+
+unsigned int PA_PA_BCR __AT (0x30000020);
+
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR11  ----------------------------------
+// SVD Line: 9960
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000020) Port n Output Bit Clear 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.11..11> BCR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR10  ----------------------------------
+// SVD Line: 9966
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000020) Port n Output Bit Clear 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.10..10> BCR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR9  -----------------------------------
+// SVD Line: 9972
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000020) Port n Output Bit Clear 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.9..9> BCR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR8  -----------------------------------
+// SVD Line: 9978
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000020) Port n Output Bit Clear 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.8..8> BCR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR7  -----------------------------------
+// SVD Line: 9984
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000020) Port n Output Bit Clear 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.7..7> BCR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR6  -----------------------------------
+// SVD Line: 9990
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000020) Port n Output Bit Clear 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.6..6> BCR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR5  -----------------------------------
+// SVD Line: 9996
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000020) Port n Output Bit Clear 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.5..5> BCR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR4  -----------------------------------
+// SVD Line: 10002
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000020) Port n Output Bit Clear 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.4..4> BCR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR3  -----------------------------------
+// SVD Line: 10008
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000020) Port n Output Bit Clear 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.3..3> BCR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR2  -----------------------------------
+// SVD Line: 10014
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000020) Port n Output Bit Clear 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.2..2> BCR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR1  -----------------------------------
+// SVD Line: 10020
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000020) Port n Output Bit Clear 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.1..1> BCR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PA_PA_BCR_BCR0  -----------------------------------
+// SVD Line: 10026
+
+//  <item> SFDITEM_FIELD__PA_PA_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000020) Port n Output Bit Clear 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_BCR ) </loc>
+//      <o.0..0> BCR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PA_PA_BCR  -----------------------------------
+// SVD Line: 9950
+
+//  <rtree> SFDITEM_REG__PA_PA_BCR
+//    <name> PA_BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000020) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PA_PA_BCR >> 0) & 0xFFFFFFFF), ((PA_PA_BCR = (PA_PA_BCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: PA_PA_OUTDMSK  ------------------------------
+// SVD Line: 10034
+
+unsigned int PA_PA_OUTDMSK __AT (0x30000024);
+
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK11  ------------------------------
+// SVD Line: 10044
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000024) Port n Output Data Mask 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK10  ------------------------------
+// SVD Line: 10050
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000024) Port n Output Data Mask 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK9  -------------------------------
+// SVD Line: 10056
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000024) Port n Output Data Mask 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK8  -------------------------------
+// SVD Line: 10062
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000024) Port n Output Data Mask 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK7  -------------------------------
+// SVD Line: 10068
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000024) Port n Output Data Mask 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK6  -------------------------------
+// SVD Line: 10074
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000024) Port n Output Data Mask 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK5  -------------------------------
+// SVD Line: 10080
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000024) Port n Output Data Mask 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK4  -------------------------------
+// SVD Line: 10086
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000024) Port n Output Data Mask 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK3  -------------------------------
+// SVD Line: 10092
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000024) Port n Output Data Mask 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK2  -------------------------------
+// SVD Line: 10098
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000024) Port n Output Data Mask 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK1  -------------------------------
+// SVD Line: 10104
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000024) Port n Output Data Mask 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PA_PA_OUTDMSK_OUTDMSK0  -------------------------------
+// SVD Line: 10110
+
+//  <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000024) Port n Output Data Mask 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PA_PA_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: PA_PA_OUTDMSK  ---------------------------------
+// SVD Line: 10034
+
+//  <rtree> SFDITEM_REG__PA_PA_OUTDMSK
+//    <name> PA_OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000024) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PA_PA_OUTDMSK >> 0) & 0xFFFFFFFF), ((PA_PA_OUTDMSK = (PA_PA_OUTDMSK & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PA_PA_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------------  Peripheral View: PA  --------------------------------------
+// SVD Line: 9336
+
+//  <view> PA
+//    <name> PA </name>
+//    <item> SFDITEM_REG__PA_MOD </item>
+//    <item> SFDITEM_REG__PA_TYP </item>
+//    <item> SFDITEM_REG__PA_AFSR1 </item>
+//    <item> SFDITEM_REG__PA_AFSR2 </item>
+//    <item> SFDITEM_REG__PA_PUPD </item>
+//    <item> SFDITEM_REG__PA_INDR </item>
+//    <item> SFDITEM_REG__PA_OUTDR </item>
+//    <item> SFDITEM_REG__PA_BSR </item>
+//    <item> SFDITEM_REG__PA_BCR </item>
+//    <item> SFDITEM_REG__PA_OUTDMSK </item>
+//    <item> SFDITEM_REG__PA_DBCR </item>
+//    <item> SFDITEM_REG__PA_PA_MOD </item>
+//    <item> SFDITEM_REG__PA_PA_TYP </item>
+//    <item> SFDITEM_REG__PA_PA_AFSR1 </item>
+//    <item> SFDITEM_REG__PA_PA_AFSR2 </item>
+//    <item> SFDITEM_REG__PA_PA_PUPD </item>
+//    <item> SFDITEM_REG__PA_PA_INDR </item>
+//    <item> SFDITEM_REG__PA_PA_OUTDR </item>
+//    <item> SFDITEM_REG__PA_PA_BSR </item>
+//    <item> SFDITEM_REG__PA_PA_BCR </item>
+//    <item> SFDITEM_REG__PA_PA_OUTDMSK </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: PB_MOD  ---------------------------------
+// SVD Line: 6351
+
+unsigned int PB_MOD __AT (0x30000100);
+
+
+
+// --------------------------------  Field Item: PB_MOD_MODE15  -----------------------------------
+// SVD Line: 6360
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000100) \nPort n Mode Selection 15\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.31..30> MODE15
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE14  -----------------------------------
+// SVD Line: 6383
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000100) \nPort n Mode Selection 14\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.29..28> MODE14
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE13  -----------------------------------
+// SVD Line: 6406
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000100) \nPort n Mode Selection 13\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.27..26> MODE13
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE12  -----------------------------------
+// SVD Line: 6429
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000100) \nPort n Mode Selection 12\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.25..24> MODE12
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE11  -----------------------------------
+// SVD Line: 6452
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000100) \nPort n Mode Selection 11\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.23..22> MODE11
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE10  -----------------------------------
+// SVD Line: 6475
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000100) \nPort n Mode Selection 10\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.21..20> MODE10
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE9  ------------------------------------
+// SVD Line: 6498
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000100) \nPort n Mode Selection 9\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.19..18> MODE9
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE8  ------------------------------------
+// SVD Line: 6521
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000100) \nPort n Mode Selection 8\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.17..16> MODE8
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE7  ------------------------------------
+// SVD Line: 6544
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000100) \nPort n Mode Selection 7\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.15..14> MODE7
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE6  ------------------------------------
+// SVD Line: 6567
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000100) \nPort n Mode Selection 6\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.13..12> MODE6
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE5  ------------------------------------
+// SVD Line: 6590
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000100) \nPort n Mode Selection 5\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.11..10> MODE5
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE4  ------------------------------------
+// SVD Line: 6613
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000100) \nPort n Mode Selection 4\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.9..8> MODE4
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE3  ------------------------------------
+// SVD Line: 6636
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000100) \nPort n Mode Selection 3\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.7..6> MODE3
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE2  ------------------------------------
+// SVD Line: 6659
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000100) \nPort n Mode Selection 2\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.5..4> MODE2
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE1  ------------------------------------
+// SVD Line: 6682
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000100) \nPort n Mode Selection 1\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.3..2> MODE1
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_MOD_MODE0  ------------------------------------
+// SVD Line: 6705
+
+//  <item> SFDITEM_FIELD__PB_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000100) \nPort n Mode Selection 0\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_MOD ) </loc>
+//      <o.1..0> MODE0
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PB_MOD  -------------------------------------
+// SVD Line: 6351
+
+//  <rtree> SFDITEM_REG__PB_MOD
+//    <name> MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000100) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PB_MOD >> 0) & 0xFFFFFFFF), ((PB_MOD = (PB_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PB_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PB_TYP  ---------------------------------
+// SVD Line: 6730
+
+unsigned int PB_TYP __AT (0x30000104);
+
+
+
+// --------------------------------  Field Item: PB_TYP_TYP15  ------------------------------------
+// SVD Line: 6739
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000104) \nPort n Output Type Selection 15\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.15..15> TYP15
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_TYP_TYP14  ------------------------------------
+// SVD Line: 6757
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000104) \nPort n Output Type Selection 14\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.14..14> TYP14
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_TYP_TYP13  ------------------------------------
+// SVD Line: 6775
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000104) \nPort n Output Type Selection 13\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.13..13> TYP13
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_TYP_TYP12  ------------------------------------
+// SVD Line: 6793
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000104) \nPort n Output Type Selection 12\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.12..12> TYP12
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_TYP_TYP11  ------------------------------------
+// SVD Line: 6811
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000104) \nPort n Output Type Selection 11\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.11..11> TYP11
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_TYP_TYP10  ------------------------------------
+// SVD Line: 6829
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000104) \nPort n Output Type Selection 10\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.10..10> TYP10
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP9  ------------------------------------
+// SVD Line: 6847
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000104) \nPort n Output Type Selection 9\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.9..9> TYP9
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP8  ------------------------------------
+// SVD Line: 6865
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000104) \nPort n Output Type Selection 8\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.8..8> TYP8
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP7  ------------------------------------
+// SVD Line: 6883
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000104) \nPort n Output Type Selection 7\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.7..7> TYP7
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP6  ------------------------------------
+// SVD Line: 6901
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000104) \nPort n Output Type Selection 6\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.6..6> TYP6
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP5  ------------------------------------
+// SVD Line: 6919
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000104) \nPort n Output Type Selection 5\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.5..5> TYP5
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP4  ------------------------------------
+// SVD Line: 6937
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000104) \nPort n Output Type Selection 4\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.4..4> TYP4
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP3  ------------------------------------
+// SVD Line: 6955
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000104) \nPort n Output Type Selection 3\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.3..3> TYP3
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP2  ------------------------------------
+// SVD Line: 6973
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000104) \nPort n Output Type Selection 2\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.2..2> TYP2
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP1  ------------------------------------
+// SVD Line: 6991
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000104) \nPort n Output Type Selection 1\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.1..1> TYP1
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_TYP_TYP0  ------------------------------------
+// SVD Line: 7009
+
+//  <item> SFDITEM_FIELD__PB_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000104) \nPort n Output Type Selection 0\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_TYP ) </loc>
+//      <o.0..0> TYP0
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PB_TYP  -------------------------------------
+// SVD Line: 6730
+
+//  <rtree> SFDITEM_REG__PB_TYP
+//    <name> TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000104) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PB_TYP >> 0) & 0xFFFFFFFF), ((PB_TYP = (PB_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PB_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PB_AFSR1  --------------------------------
+// SVD Line: 7029
+
+unsigned int PB_AFSR1 __AT (0x30000108);
+
+
+
+// -------------------------------  Field Item: PB_AFSR1_AFSR7  -----------------------------------
+// SVD Line: 7038
+
+//  <item> SFDITEM_FIELD__PB_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000108) \nPort n Alternative Function Selection 7\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR1 ) </loc>
+//      <o.31..28> AFSR7
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR1_AFSR6  -----------------------------------
+// SVD Line: 7071
+
+//  <item> SFDITEM_FIELD__PB_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000108) \nPort n Alternative Function Selection 6\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR1 ) </loc>
+//      <o.27..24> AFSR6
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR1_AFSR5  -----------------------------------
+// SVD Line: 7104
+
+//  <item> SFDITEM_FIELD__PB_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000108) \nPort n Alternative Function Selection 5\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR1 ) </loc>
+//      <o.23..20> AFSR5
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR1_AFSR4  -----------------------------------
+// SVD Line: 7137
+
+//  <item> SFDITEM_FIELD__PB_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000108) \nPort n Alternative Function Selection 4\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR1 ) </loc>
+//      <o.19..16> AFSR4
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR1_AFSR3  -----------------------------------
+// SVD Line: 7170
+
+//  <item> SFDITEM_FIELD__PB_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000108) \nPort n Alternative Function Selection 3\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR1 ) </loc>
+//      <o.15..12> AFSR3
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR1_AFSR2  -----------------------------------
+// SVD Line: 7203
+
+//  <item> SFDITEM_FIELD__PB_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000108) \nPort n Alternative Function Selection 2\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR1 ) </loc>
+//      <o.11..8> AFSR2
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR1_AFSR1  -----------------------------------
+// SVD Line: 7236
+
+//  <item> SFDITEM_FIELD__PB_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000108) \nPort n Alternative Function Selection 1\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR1 ) </loc>
+//      <o.7..4> AFSR1
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR1_AFSR0  -----------------------------------
+// SVD Line: 7269
+
+//  <item> SFDITEM_FIELD__PB_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000108) \nPort n Alternative Function Selection 0\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR1 ) </loc>
+//      <o.3..0> AFSR0
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PB_AFSR1  ------------------------------------
+// SVD Line: 7029
+
+//  <rtree> SFDITEM_REG__PB_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000108) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PB_AFSR1 >> 0) & 0xFFFFFFFF), ((PB_AFSR1 = (PB_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PB_AFSR2  --------------------------------
+// SVD Line: 7304
+
+unsigned int PB_AFSR2 __AT (0x3000010C);
+
+
+
+// -------------------------------  Field Item: PB_AFSR2_AFSR15  ----------------------------------
+// SVD Line: 7313
+
+//  <item> SFDITEM_FIELD__PB_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x3000010C) \nPort n Alternative Function Selection 15\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR2 ) </loc>
+//      <o.31..28> AFSR15
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR2_AFSR14  ----------------------------------
+// SVD Line: 7346
+
+//  <item> SFDITEM_FIELD__PB_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x3000010C) \nPort n Alternative Function Selection 14\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR2 ) </loc>
+//      <o.27..24> AFSR14
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR2_AFSR13  ----------------------------------
+// SVD Line: 7379
+
+//  <item> SFDITEM_FIELD__PB_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x3000010C) \nPort n Alternative Function Selection 13\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR2 ) </loc>
+//      <o.23..20> AFSR13
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR2_AFSR12  ----------------------------------
+// SVD Line: 7412
+
+//  <item> SFDITEM_FIELD__PB_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000010C) \nPort n Alternative Function Selection 12\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR2 ) </loc>
+//      <o.19..16> AFSR12
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR2_AFSR11  ----------------------------------
+// SVD Line: 7445
+
+//  <item> SFDITEM_FIELD__PB_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000010C) \nPort n Alternative Function Selection 11\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR2 ) </loc>
+//      <o.15..12> AFSR11
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR2_AFSR10  ----------------------------------
+// SVD Line: 7478
+
+//  <item> SFDITEM_FIELD__PB_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000010C) \nPort n Alternative Function Selection 10\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR2 ) </loc>
+//      <o.11..8> AFSR10
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR2_AFSR9  -----------------------------------
+// SVD Line: 7511
+
+//  <item> SFDITEM_FIELD__PB_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000010C) \nPort n Alternative Function Selection 9\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR2 ) </loc>
+//      <o.7..4> AFSR9
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_AFSR2_AFSR8  -----------------------------------
+// SVD Line: 7544
+
+//  <item> SFDITEM_FIELD__PB_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000010C) \nPort n Alternative Function Selection 8\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_AFSR2 ) </loc>
+//      <o.3..0> AFSR8
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PB_AFSR2  ------------------------------------
+// SVD Line: 7304
+
+//  <rtree> SFDITEM_REG__PB_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000010C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PB_AFSR2 >> 0) & 0xFFFFFFFF), ((PB_AFSR2 = (PB_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PB_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PB_PUPD  ---------------------------------
+// SVD Line: 7579
+
+unsigned int PB_PUPD __AT (0x30000110);
+
+
+
+// -------------------------------  Field Item: PB_PUPD_PUPD15  -----------------------------------
+// SVD Line: 7588
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 15\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.31..30> PUPD15
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PUPD_PUPD14  -----------------------------------
+// SVD Line: 7611
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 14\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.29..28> PUPD14
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PUPD_PUPD13  -----------------------------------
+// SVD Line: 7634
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 13\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.27..26> PUPD13
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PUPD_PUPD12  -----------------------------------
+// SVD Line: 7657
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 12\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.25..24> PUPD12
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PUPD_PUPD11  -----------------------------------
+// SVD Line: 7680
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 11\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.23..22> PUPD11
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PUPD_PUPD10  -----------------------------------
+// SVD Line: 7703
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 10\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.21..20> PUPD10
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD9  -----------------------------------
+// SVD Line: 7726
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 9\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.19..18> PUPD9
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD8  -----------------------------------
+// SVD Line: 7749
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 8\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.17..16> PUPD8
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD7  -----------------------------------
+// SVD Line: 7772
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 7\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.15..14> PUPD7
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD6  -----------------------------------
+// SVD Line: 7795
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 6\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.13..12> PUPD6
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD5  -----------------------------------
+// SVD Line: 7818
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 5\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.11..10> PUPD5
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD4  -----------------------------------
+// SVD Line: 7841
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 4\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.9..8> PUPD4
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD3  -----------------------------------
+// SVD Line: 7864
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 3\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.7..6> PUPD3
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD2  -----------------------------------
+// SVD Line: 7887
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 2\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.5..4> PUPD2
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD1  -----------------------------------
+// SVD Line: 7910
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 1\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.3..2> PUPD1
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_PUPD_PUPD0  -----------------------------------
+// SVD Line: 7933
+
+//  <item> SFDITEM_FIELD__PB_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000110) \nPort n Pull-Up/Down Resistor Selection 0\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_PUPD ) </loc>
+//      <o.1..0> PUPD0
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PB_PUPD  ------------------------------------
+// SVD Line: 7579
+
+//  <rtree> SFDITEM_REG__PB_PUPD
+//    <name> PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PB_PUPD >> 0) & 0xFFFFFFFF), ((PB_PUPD = (PB_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PB_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PB_INDR  ---------------------------------
+// SVD Line: 7958
+
+unsigned int PB_INDR __AT (0x30000114);
+
+
+
+// -------------------------------  Field Item: PB_INDR_INDR15  -----------------------------------
+// SVD Line: 7967
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x30000114) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_INDR_INDR14  -----------------------------------
+// SVD Line: 7973
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x30000114) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_INDR_INDR13  -----------------------------------
+// SVD Line: 7979
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x30000114) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_INDR_INDR12  -----------------------------------
+// SVD Line: 7985
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000114) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_INDR_INDR11  -----------------------------------
+// SVD Line: 7991
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000114) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_INDR_INDR10  -----------------------------------
+// SVD Line: 7997
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000114) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR9  -----------------------------------
+// SVD Line: 8003
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000114) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR8  -----------------------------------
+// SVD Line: 8009
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000114) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR7  -----------------------------------
+// SVD Line: 8015
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000114) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR6  -----------------------------------
+// SVD Line: 8021
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000114) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR5  -----------------------------------
+// SVD Line: 8027
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000114) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR4  -----------------------------------
+// SVD Line: 8033
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000114) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR3  -----------------------------------
+// SVD Line: 8039
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000114) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR2  -----------------------------------
+// SVD Line: 8045
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000114) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR1  -----------------------------------
+// SVD Line: 8051
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000114) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_INDR_INDR0  -----------------------------------
+// SVD Line: 8057
+
+//  <item> SFDITEM_FIELD__PB_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000114) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PB_INDR  ------------------------------------
+// SVD Line: 7958
+
+//  <rtree> SFDITEM_REG__PB_INDR
+//    <name> INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000114) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PB_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PB_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PB_OUTDR  --------------------------------
+// SVD Line: 8065
+
+unsigned int PB_OUTDR __AT (0x30000118);
+
+
+
+// ------------------------------  Field Item: PB_OUTDR_OUTDR15  ----------------------------------
+// SVD Line: 8074
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000118) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_OUTDR_OUTDR14  ----------------------------------
+// SVD Line: 8080
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000118) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_OUTDR_OUTDR13  ----------------------------------
+// SVD Line: 8086
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000118) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_OUTDR_OUTDR12  ----------------------------------
+// SVD Line: 8092
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000118) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_OUTDR_OUTDR11  ----------------------------------
+// SVD Line: 8098
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000118) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_OUTDR_OUTDR10  ----------------------------------
+// SVD Line: 8104
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000118) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR9  ----------------------------------
+// SVD Line: 8110
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000118) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR8  ----------------------------------
+// SVD Line: 8116
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000118) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR7  ----------------------------------
+// SVD Line: 8122
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000118) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR6  ----------------------------------
+// SVD Line: 8128
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000118) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR5  ----------------------------------
+// SVD Line: 8134
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000118) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR4  ----------------------------------
+// SVD Line: 8140
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000118) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR3  ----------------------------------
+// SVD Line: 8146
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000118) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR2  ----------------------------------
+// SVD Line: 8152
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000118) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR1  ----------------------------------
+// SVD Line: 8158
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000118) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_OUTDR_OUTDR0  ----------------------------------
+// SVD Line: 8164
+
+//  <item> SFDITEM_FIELD__PB_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000118) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PB_OUTDR  ------------------------------------
+// SVD Line: 8065
+
+//  <rtree> SFDITEM_REG__PB_OUTDR
+//    <name> OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000118) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PB_OUTDR >> 0) & 0xFFFFFFFF), ((PB_OUTDR = (PB_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PB_BSR  ---------------------------------
+// SVD Line: 8172
+
+unsigned int PB_BSR __AT (0x3000011C);
+
+
+
+// --------------------------------  Field Item: PB_BSR_BSR15  ------------------------------------
+// SVD Line: 8181
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x3000011C) \nPort n Output Bit Set 15\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.15..15> BSR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BSR_BSR14  ------------------------------------
+// SVD Line: 8199
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x3000011C) \nPort n Output Bit Set 14\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.14..14> BSR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BSR_BSR13  ------------------------------------
+// SVD Line: 8217
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x3000011C) \nPort n Output Bit Set 13\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.13..13> BSR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BSR_BSR12  ------------------------------------
+// SVD Line: 8235
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000011C) \nPort n Output Bit Set 12\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.12..12> BSR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BSR_BSR11  ------------------------------------
+// SVD Line: 8253
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000011C) \nPort n Output Bit Set 11\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.11..11> BSR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BSR_BSR10  ------------------------------------
+// SVD Line: 8271
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000011C) \nPort n Output Bit Set 10\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.10..10> BSR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR9  ------------------------------------
+// SVD Line: 8289
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000011C) \nPort n Output Bit Set 9\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.9..9> BSR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR8  ------------------------------------
+// SVD Line: 8307
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000011C) \nPort n Output Bit Set 8\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.8..8> BSR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR7  ------------------------------------
+// SVD Line: 8325
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000011C) \nPort n Output Bit Set 7\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.7..7> BSR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR6  ------------------------------------
+// SVD Line: 8343
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000011C) \nPort n Output Bit Set 6\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.6..6> BSR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR5  ------------------------------------
+// SVD Line: 8361
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000011C) \nPort n Output Bit Set 5\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.5..5> BSR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR4  ------------------------------------
+// SVD Line: 8379
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000011C) \nPort n Output Bit Set 4\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.4..4> BSR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR3  ------------------------------------
+// SVD Line: 8397
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000011C) \nPort n Output Bit Set 3\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.3..3> BSR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR2  ------------------------------------
+// SVD Line: 8415
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000011C) \nPort n Output Bit Set 2\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.2..2> BSR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR1  ------------------------------------
+// SVD Line: 8433
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000011C) \nPort n Output Bit Set 1\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.1..1> BSR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BSR_BSR0  ------------------------------------
+// SVD Line: 8451
+
+//  <item> SFDITEM_FIELD__PB_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000011C) \nPort n Output Bit Set 0\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BSR ) </loc>
+//      <o.0..0> BSR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PB_BSR  -------------------------------------
+// SVD Line: 8172
+
+//  <rtree> SFDITEM_REG__PB_BSR
+//    <name> BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000011C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PB_BSR >> 0) & 0xFFFFFFFF), ((PB_BSR = (PB_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PB_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PB_BCR  ---------------------------------
+// SVD Line: 8471
+
+unsigned int PB_BCR __AT (0x30000120);
+
+
+
+// --------------------------------  Field Item: PB_BCR_BCR15  ------------------------------------
+// SVD Line: 8480
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x30000120) \nPort n Output Bit Clear 15\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.15..15> BCR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BCR_BCR14  ------------------------------------
+// SVD Line: 8498
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x30000120) \nPort n Output Bit Clear 14\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.14..14> BCR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BCR_BCR13  ------------------------------------
+// SVD Line: 8516
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x30000120) \nPort n Output Bit Clear 13\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.13..13> BCR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BCR_BCR12  ------------------------------------
+// SVD Line: 8534
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000120) \nPort n Output Bit Clear 12\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.12..12> BCR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BCR_BCR11  ------------------------------------
+// SVD Line: 8552
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000120) \nPort n Output Bit Clear 11\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.11..11> BCR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_BCR_BCR10  ------------------------------------
+// SVD Line: 8570
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000120) \nPort n Output Bit Clear 10\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.10..10> BCR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR9  ------------------------------------
+// SVD Line: 8588
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000120) \nPort n Output Bit Clear 9\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.9..9> BCR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR8  ------------------------------------
+// SVD Line: 8606
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000120) \nPort n Output Bit Clear 8\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.8..8> BCR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR7  ------------------------------------
+// SVD Line: 8624
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000120) \nPort n Output Bit Clear 7\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.7..7> BCR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR6  ------------------------------------
+// SVD Line: 8642
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000120) \nPort n Output Bit Clear 6\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.6..6> BCR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR5  ------------------------------------
+// SVD Line: 8660
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000120) \nPort n Output Bit Clear 5\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.5..5> BCR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR4  ------------------------------------
+// SVD Line: 8678
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000120) \nPort n Output Bit Clear 4\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.4..4> BCR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR3  ------------------------------------
+// SVD Line: 8696
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000120) \nPort n Output Bit Clear 3\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.3..3> BCR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR2  ------------------------------------
+// SVD Line: 8714
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000120) \nPort n Output Bit Clear 2\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.2..2> BCR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR1  ------------------------------------
+// SVD Line: 8732
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000120) \nPort n Output Bit Clear 1\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.1..1> BCR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PB_BCR_BCR0  ------------------------------------
+// SVD Line: 8750
+
+//  <item> SFDITEM_FIELD__PB_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000120) \nPort n Output Bit Clear 0\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_BCR ) </loc>
+//      <o.0..0> BCR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PB_BCR  -------------------------------------
+// SVD Line: 8471
+
+//  <rtree> SFDITEM_REG__PB_BCR
+//    <name> BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000120) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PB_BCR >> 0) & 0xFFFFFFFF), ((PB_BCR = (PB_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PB_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PB_OUTDMSK  -------------------------------
+// SVD Line: 8770
+
+unsigned int PB_OUTDMSK __AT (0x30000124);
+
+
+
+// ----------------------------  Field Item: PB_OUTDMSK_OUTDMSK15  --------------------------------
+// SVD Line: 8779
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000124) \nPort n Output Data Mask 15\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PB_OUTDMSK_OUTDMSK14  --------------------------------
+// SVD Line: 8797
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000124) \nPort n Output Data Mask 14\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PB_OUTDMSK_OUTDMSK13  --------------------------------
+// SVD Line: 8815
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000124) \nPort n Output Data Mask 13\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PB_OUTDMSK_OUTDMSK12  --------------------------------
+// SVD Line: 8833
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000124) \nPort n Output Data Mask 12\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PB_OUTDMSK_OUTDMSK11  --------------------------------
+// SVD Line: 8851
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000124) \nPort n Output Data Mask 11\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PB_OUTDMSK_OUTDMSK10  --------------------------------
+// SVD Line: 8869
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000124) \nPort n Output Data Mask 10\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK9  --------------------------------
+// SVD Line: 8887
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000124) \nPort n Output Data Mask 9\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK8  --------------------------------
+// SVD Line: 8905
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000124) \nPort n Output Data Mask 8\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK7  --------------------------------
+// SVD Line: 8923
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000124) \nPort n Output Data Mask 7\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK6  --------------------------------
+// SVD Line: 8941
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000124) \nPort n Output Data Mask 6\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK5  --------------------------------
+// SVD Line: 8959
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000124) \nPort n Output Data Mask 5\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK4  --------------------------------
+// SVD Line: 8977
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000124) \nPort n Output Data Mask 4\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK3  --------------------------------
+// SVD Line: 8995
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000124) \nPort n Output Data Mask 3\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK2  --------------------------------
+// SVD Line: 9013
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000124) \nPort n Output Data Mask 2\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK1  --------------------------------
+// SVD Line: 9031
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000124) \nPort n Output Data Mask 1\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_OUTDMSK_OUTDMSK0  --------------------------------
+// SVD Line: 9049
+
+//  <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000124) \nPort n Output Data Mask 0\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PB_OUTDMSK  -----------------------------------
+// SVD Line: 8770
+
+//  <rtree> SFDITEM_REG__PB_OUTDMSK
+//    <name> OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000124) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PB_OUTDMSK >> 0) & 0xFFFFFFFF), ((PB_OUTDMSK = (PB_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PB_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PB_DBCR  ---------------------------------
+// SVD Line: 9069
+
+unsigned int PB_DBCR __AT (0x30000128);
+
+
+
+// --------------------------------  Field Item: PB_DBCR_DBCLK  -----------------------------------
+// SVD Line: 9078
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000128) \nPort n Debounce Filter Sampling Clock Selection\n0 : HCLK1 = HCLK/1\n1 : HCLK4 = HCLK/4\n2 : HCLK16 = HCLK/16\n3 : HCLK64 = HCLK/64\n4 : HCLK256 = HCLK/256\n5 : HCLK1024 = HCLK/1024\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.18..16> DBCLK
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK4 = HCLK/4
+//        <2=> 2: HCLK16 = HCLK/16
+//        <3=> 3: HCLK64 = HCLK/64
+//        <4=> 4: HCLK256 = HCLK/256
+//        <5=> 5: HCLK1024 = HCLK/1024
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_DBCR_DBEN11  -----------------------------------
+// SVD Line: 9116
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN11
+//    <name> DBEN11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000128) \nPort n Debounce Enable 11\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.11..11> DBEN11
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_DBCR_DBEN10  -----------------------------------
+// SVD Line: 9134
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN10
+//    <name> DBEN10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000128) \nPort n Debounce Enable 10\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.10..10> DBEN10
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN9  -----------------------------------
+// SVD Line: 9152
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN9
+//    <name> DBEN9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000128) \nPort n Debounce Enable 9\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.9..9> DBEN9
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN8  -----------------------------------
+// SVD Line: 9170
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN8
+//    <name> DBEN8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000128) \nPort n Debounce Enable 8\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.8..8> DBEN8
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN7  -----------------------------------
+// SVD Line: 9188
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN7
+//    <name> DBEN7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000128) \nPort n Debounce Enable 7\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.7..7> DBEN7
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN6  -----------------------------------
+// SVD Line: 9206
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN6
+//    <name> DBEN6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000128) \nPort n Debounce Enable 6\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.6..6> DBEN6
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN5  -----------------------------------
+// SVD Line: 9224
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN5
+//    <name> DBEN5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000128) \nPort n Debounce Enable 5\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.5..5> DBEN5
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN4  -----------------------------------
+// SVD Line: 9242
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN4
+//    <name> DBEN4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000128) \nPort n Debounce Enable 4\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.4..4> DBEN4
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN3  -----------------------------------
+// SVD Line: 9260
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000128) \nPort n Debounce Enable 3\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN2  -----------------------------------
+// SVD Line: 9278
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000128) \nPort n Debounce Enable 2\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN1  -----------------------------------
+// SVD Line: 9296
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000128) \nPort n Debounce Enable 1\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PB_DBCR_DBEN0  -----------------------------------
+// SVD Line: 9314
+
+//  <item> SFDITEM_FIELD__PB_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000128) \nPort n Debounce Enable 0\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PB_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PB_DBCR  ------------------------------------
+// SVD Line: 9069
+
+//  <rtree> SFDITEM_REG__PB_DBCR
+//    <name> DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000128) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PB_DBCR >> 0) & 0xFFFFFFFF), ((PB_DBCR = (PB_DBCR & ~(0x70FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN11 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN10 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN9 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN8 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN7 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN6 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN5 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN4 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PB_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PB_PB_MOD  --------------------------------
+// SVD Line: 10134
+
+unsigned int PB_PB_MOD __AT (0x30000100);
+
+
+
+// ------------------------------  Field Item: PB_PB_MOD_MODE15  ----------------------------------
+// SVD Line: 10144
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000100) Port n Mode Selection 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 30) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_MOD_MODE14  ----------------------------------
+// SVD Line: 10150
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000100) Port n Mode Selection 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 28) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_MOD_MODE13  ----------------------------------
+// SVD Line: 10156
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000100) Port n Mode Selection 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 26) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_MOD_MODE12  ----------------------------------
+// SVD Line: 10162
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000100) Port n Mode Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 24) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_MOD_MODE11  ----------------------------------
+// SVD Line: 10168
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000100) Port n Mode Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 22) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_MOD_MODE10  ----------------------------------
+// SVD Line: 10174
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000100) Port n Mode Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 20) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE9  ----------------------------------
+// SVD Line: 10180
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000100) Port n Mode Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 18) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE8  ----------------------------------
+// SVD Line: 10186
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000100) Port n Mode Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 16) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE7  ----------------------------------
+// SVD Line: 10192
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000100) Port n Mode Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 14) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE6  ----------------------------------
+// SVD Line: 10198
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000100) Port n Mode Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 12) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE5  ----------------------------------
+// SVD Line: 10204
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000100) Port n Mode Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 10) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE4  ----------------------------------
+// SVD Line: 10210
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000100) Port n Mode Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 8) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE3  ----------------------------------
+// SVD Line: 10216
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000100) Port n Mode Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 6) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE2  ----------------------------------
+// SVD Line: 10222
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000100) Port n Mode Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 4) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE1  ----------------------------------
+// SVD Line: 10228
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000100) Port n Mode Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 2) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_MOD_MODE0  ----------------------------------
+// SVD Line: 10234
+
+//  <item> SFDITEM_FIELD__PB_PB_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000100) Port n Mode Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_MOD >> 0) & 0x3), ((PB_PB_MOD = (PB_PB_MOD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PB_PB_MOD  -----------------------------------
+// SVD Line: 10134
+
+//  <rtree> SFDITEM_REG__PB_PB_MOD
+//    <name> PB_MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000100) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PB_PB_MOD >> 0) & 0xFFFFFFFF), ((PB_PB_MOD = (PB_PB_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PB_PB_TYP  --------------------------------
+// SVD Line: 10242
+
+unsigned int PB_PB_TYP __AT (0x30000104);
+
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP15  ----------------------------------
+// SVD Line: 10252
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000104) Port n Output Type Selection 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.15..15> TYP15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP14  ----------------------------------
+// SVD Line: 10258
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000104) Port n Output Type Selection 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.14..14> TYP14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP13  ----------------------------------
+// SVD Line: 10264
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000104) Port n Output Type Selection 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.13..13> TYP13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP12  ----------------------------------
+// SVD Line: 10270
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000104) Port n Output Type Selection 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.12..12> TYP12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP11  ----------------------------------
+// SVD Line: 10276
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000104) Port n Output Type Selection 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.11..11> TYP11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP10  ----------------------------------
+// SVD Line: 10282
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000104) Port n Output Type Selection 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.10..10> TYP10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP9  -----------------------------------
+// SVD Line: 10288
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000104) Port n Output Type Selection 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.9..9> TYP9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP8  -----------------------------------
+// SVD Line: 10294
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000104) Port n Output Type Selection 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.8..8> TYP8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP7  -----------------------------------
+// SVD Line: 10300
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000104) Port n Output Type Selection 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.7..7> TYP7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP6  -----------------------------------
+// SVD Line: 10306
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000104) Port n Output Type Selection 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.6..6> TYP6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP5  -----------------------------------
+// SVD Line: 10312
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000104) Port n Output Type Selection 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.5..5> TYP5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP4  -----------------------------------
+// SVD Line: 10318
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000104) Port n Output Type Selection 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.4..4> TYP4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP3  -----------------------------------
+// SVD Line: 10324
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000104) Port n Output Type Selection 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.3..3> TYP3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP2  -----------------------------------
+// SVD Line: 10330
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000104) Port n Output Type Selection 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.2..2> TYP2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP1  -----------------------------------
+// SVD Line: 10336
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000104) Port n Output Type Selection 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.1..1> TYP1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_TYP_TYP0  -----------------------------------
+// SVD Line: 10342
+
+//  <item> SFDITEM_FIELD__PB_PB_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000104) Port n Output Type Selection 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_TYP ) </loc>
+//      <o.0..0> TYP0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PB_PB_TYP  -----------------------------------
+// SVD Line: 10242
+
+//  <rtree> SFDITEM_REG__PB_PB_TYP
+//    <name> PB_TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000104) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PB_PB_TYP >> 0) & 0xFFFFFFFF), ((PB_PB_TYP = (PB_PB_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PB_PB_AFSR1  -------------------------------
+// SVD Line: 10350
+
+unsigned int PB_PB_AFSR1 __AT (0x30000108);
+
+
+
+// ------------------------------  Field Item: PB_PB_AFSR1_AFSR7  ---------------------------------
+// SVD Line: 10360
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000108) Port n Alternative Function Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR1 >> 28) & 0xF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR1_AFSR6  ---------------------------------
+// SVD Line: 10366
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000108) Port n Alternative Function Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR1 >> 24) & 0xF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR1_AFSR5  ---------------------------------
+// SVD Line: 10372
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000108) Port n Alternative Function Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR1 >> 20) & 0xF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR1_AFSR4  ---------------------------------
+// SVD Line: 10378
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000108) Port n Alternative Function Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR1 >> 16) & 0xF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR1_AFSR3  ---------------------------------
+// SVD Line: 10384
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000108) Port n Alternative Function Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR1 >> 12) & 0xF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR1_AFSR2  ---------------------------------
+// SVD Line: 10390
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000108) Port n Alternative Function Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR1 >> 8) & 0xF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR1_AFSR1  ---------------------------------
+// SVD Line: 10396
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000108) Port n Alternative Function Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR1 >> 4) & 0xF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR1_AFSR0  ---------------------------------
+// SVD Line: 10402
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000108) Port n Alternative Function Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR1 >> 0) & 0xF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PB_PB_AFSR1  ----------------------------------
+// SVD Line: 10350
+
+//  <rtree> SFDITEM_REG__PB_PB_AFSR1
+//    <name> PB_AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000108) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PB_PB_AFSR1 >> 0) & 0xFFFFFFFF), ((PB_PB_AFSR1 = (PB_PB_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PB_PB_AFSR2  -------------------------------
+// SVD Line: 10410
+
+unsigned int PB_PB_AFSR2 __AT (0x3000010C);
+
+
+
+// -----------------------------  Field Item: PB_PB_AFSR2_AFSR15  ---------------------------------
+// SVD Line: 10420
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x3000010C) Port n Alternative Function Selection 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR2 >> 28) & 0xF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_AFSR2_AFSR14  ---------------------------------
+// SVD Line: 10426
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x3000010C) Port n Alternative Function Selection 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR2 >> 24) & 0xF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_AFSR2_AFSR13  ---------------------------------
+// SVD Line: 10432
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x3000010C) Port n Alternative Function Selection 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR2 >> 20) & 0xF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_AFSR2_AFSR12  ---------------------------------
+// SVD Line: 10438
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000010C) Port n Alternative Function Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR2 >> 16) & 0xF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_AFSR2_AFSR11  ---------------------------------
+// SVD Line: 10444
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000010C) Port n Alternative Function Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR2 >> 12) & 0xF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_AFSR2_AFSR10  ---------------------------------
+// SVD Line: 10450
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000010C) Port n Alternative Function Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR2 >> 8) & 0xF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR2_AFSR9  ---------------------------------
+// SVD Line: 10456
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000010C) Port n Alternative Function Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR2 >> 4) & 0xF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_AFSR2_AFSR8  ---------------------------------
+// SVD Line: 10462
+
+//  <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000010C) Port n Alternative Function Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_AFSR2 >> 0) & 0xF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PB_PB_AFSR2  ----------------------------------
+// SVD Line: 10410
+
+//  <rtree> SFDITEM_REG__PB_PB_AFSR2
+//    <name> PB_AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000010C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PB_PB_AFSR2 >> 0) & 0xFFFFFFFF), ((PB_PB_AFSR2 = (PB_PB_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PB_PB_PUPD  -------------------------------
+// SVD Line: 10470
+
+unsigned int PB_PB_PUPD __AT (0x30000110);
+
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD15  ---------------------------------
+// SVD Line: 10480
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 30) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD14  ---------------------------------
+// SVD Line: 10486
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 28) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD13  ---------------------------------
+// SVD Line: 10492
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 26) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD12  ---------------------------------
+// SVD Line: 10498
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 24) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD11  ---------------------------------
+// SVD Line: 10504
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 22) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD10  ---------------------------------
+// SVD Line: 10510
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 20) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD9  ----------------------------------
+// SVD Line: 10516
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 18) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD8  ----------------------------------
+// SVD Line: 10522
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 16) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD7  ----------------------------------
+// SVD Line: 10528
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 14) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD6  ----------------------------------
+// SVD Line: 10534
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 12) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD5  ----------------------------------
+// SVD Line: 10540
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 10) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD4  ----------------------------------
+// SVD Line: 10546
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 8) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD3  ----------------------------------
+// SVD Line: 10552
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 6) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD2  ----------------------------------
+// SVD Line: 10558
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 4) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD1  ----------------------------------
+// SVD Line: 10564
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 2) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_PUPD_PUPD0  ----------------------------------
+// SVD Line: 10570
+
+//  <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_PUPD >> 0) & 0x3), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PB_PB_PUPD  -----------------------------------
+// SVD Line: 10470
+
+//  <rtree> SFDITEM_REG__PB_PB_PUPD
+//    <name> PB_PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000110) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PB_PB_PUPD >> 0) & 0xFFFFFFFF), ((PB_PB_PUPD = (PB_PB_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PB_PB_INDR  -------------------------------
+// SVD Line: 10578
+
+unsigned int PB_PB_INDR __AT (0x30000114);
+
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR15  ---------------------------------
+// SVD Line: 10588
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x30000114) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR14  ---------------------------------
+// SVD Line: 10594
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x30000114) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR13  ---------------------------------
+// SVD Line: 10600
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x30000114) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR12  ---------------------------------
+// SVD Line: 10606
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000114) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR11  ---------------------------------
+// SVD Line: 10612
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000114) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR10  ---------------------------------
+// SVD Line: 10618
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000114) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR9  ----------------------------------
+// SVD Line: 10624
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000114) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR8  ----------------------------------
+// SVD Line: 10630
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000114) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR7  ----------------------------------
+// SVD Line: 10636
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000114) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR6  ----------------------------------
+// SVD Line: 10642
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000114) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR5  ----------------------------------
+// SVD Line: 10648
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000114) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR4  ----------------------------------
+// SVD Line: 10654
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000114) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR3  ----------------------------------
+// SVD Line: 10660
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000114) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR2  ----------------------------------
+// SVD Line: 10666
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000114) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR1  ----------------------------------
+// SVD Line: 10672
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000114) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_INDR_INDR0  ----------------------------------
+// SVD Line: 10678
+
+//  <item> SFDITEM_FIELD__PB_PB_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000114) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PB_PB_INDR  -----------------------------------
+// SVD Line: 10578
+
+//  <rtree> SFDITEM_REG__PB_PB_INDR
+//    <name> PB_INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000114) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PB_PB_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PB_PB_OUTDR  -------------------------------
+// SVD Line: 10686
+
+unsigned int PB_PB_OUTDR __AT (0x30000118);
+
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR15  --------------------------------
+// SVD Line: 10696
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000118) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR14  --------------------------------
+// SVD Line: 10702
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000118) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR13  --------------------------------
+// SVD Line: 10708
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000118) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR12  --------------------------------
+// SVD Line: 10714
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000118) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR11  --------------------------------
+// SVD Line: 10720
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000118) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR10  --------------------------------
+// SVD Line: 10726
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000118) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR9  ---------------------------------
+// SVD Line: 10732
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000118) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR8  ---------------------------------
+// SVD Line: 10738
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000118) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR7  ---------------------------------
+// SVD Line: 10744
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000118) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR6  ---------------------------------
+// SVD Line: 10750
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000118) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR5  ---------------------------------
+// SVD Line: 10756
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000118) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR4  ---------------------------------
+// SVD Line: 10762
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000118) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR3  ---------------------------------
+// SVD Line: 10768
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000118) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR2  ---------------------------------
+// SVD Line: 10774
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000118) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR1  ---------------------------------
+// SVD Line: 10780
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000118) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PB_PB_OUTDR_OUTDR0  ---------------------------------
+// SVD Line: 10786
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000118) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PB_PB_OUTDR  ----------------------------------
+// SVD Line: 10686
+
+//  <rtree> SFDITEM_REG__PB_PB_OUTDR
+//    <name> PB_OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000118) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PB_PB_OUTDR >> 0) & 0xFFFFFFFF), ((PB_PB_OUTDR = (PB_PB_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PB_PB_BSR  --------------------------------
+// SVD Line: 10794
+
+unsigned int PB_PB_BSR __AT (0x3000011C);
+
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR15  ----------------------------------
+// SVD Line: 10804
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x3000011C) Port n Output Bit Set 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.15..15> BSR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR14  ----------------------------------
+// SVD Line: 10810
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x3000011C) Port n Output Bit Set 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.14..14> BSR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR13  ----------------------------------
+// SVD Line: 10816
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x3000011C) Port n Output Bit Set 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.13..13> BSR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR12  ----------------------------------
+// SVD Line: 10822
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000011C) Port n Output Bit Set 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.12..12> BSR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR11  ----------------------------------
+// SVD Line: 10828
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000011C) Port n Output Bit Set 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.11..11> BSR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR10  ----------------------------------
+// SVD Line: 10834
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000011C) Port n Output Bit Set 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.10..10> BSR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR9  -----------------------------------
+// SVD Line: 10840
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000011C) Port n Output Bit Set 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.9..9> BSR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR8  -----------------------------------
+// SVD Line: 10846
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000011C) Port n Output Bit Set 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.8..8> BSR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR7  -----------------------------------
+// SVD Line: 10852
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000011C) Port n Output Bit Set 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.7..7> BSR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR6  -----------------------------------
+// SVD Line: 10858
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000011C) Port n Output Bit Set 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.6..6> BSR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR5  -----------------------------------
+// SVD Line: 10864
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000011C) Port n Output Bit Set 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.5..5> BSR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR4  -----------------------------------
+// SVD Line: 10870
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000011C) Port n Output Bit Set 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.4..4> BSR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR3  -----------------------------------
+// SVD Line: 10876
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000011C) Port n Output Bit Set 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.3..3> BSR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR2  -----------------------------------
+// SVD Line: 10882
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000011C) Port n Output Bit Set 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.2..2> BSR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR1  -----------------------------------
+// SVD Line: 10888
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000011C) Port n Output Bit Set 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.1..1> BSR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BSR_BSR0  -----------------------------------
+// SVD Line: 10894
+
+//  <item> SFDITEM_FIELD__PB_PB_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000011C) Port n Output Bit Set 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BSR ) </loc>
+//      <o.0..0> BSR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PB_PB_BSR  -----------------------------------
+// SVD Line: 10794
+
+//  <rtree> SFDITEM_REG__PB_PB_BSR
+//    <name> PB_BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000011C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PB_PB_BSR >> 0) & 0xFFFFFFFF), ((PB_PB_BSR = (PB_PB_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PB_PB_BCR  --------------------------------
+// SVD Line: 10902
+
+unsigned int PB_PB_BCR __AT (0x30000120);
+
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR15  ----------------------------------
+// SVD Line: 10912
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x30000120) Port n Output Bit Clear 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.15..15> BCR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR14  ----------------------------------
+// SVD Line: 10918
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x30000120) Port n Output Bit Clear 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.14..14> BCR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR13  ----------------------------------
+// SVD Line: 10924
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x30000120) Port n Output Bit Clear 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.13..13> BCR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR12  ----------------------------------
+// SVD Line: 10930
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000120) Port n Output Bit Clear 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.12..12> BCR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR11  ----------------------------------
+// SVD Line: 10936
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000120) Port n Output Bit Clear 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.11..11> BCR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR10  ----------------------------------
+// SVD Line: 10942
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000120) Port n Output Bit Clear 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.10..10> BCR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR9  -----------------------------------
+// SVD Line: 10948
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000120) Port n Output Bit Clear 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.9..9> BCR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR8  -----------------------------------
+// SVD Line: 10954
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000120) Port n Output Bit Clear 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.8..8> BCR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR7  -----------------------------------
+// SVD Line: 10960
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000120) Port n Output Bit Clear 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.7..7> BCR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR6  -----------------------------------
+// SVD Line: 10966
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000120) Port n Output Bit Clear 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.6..6> BCR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR5  -----------------------------------
+// SVD Line: 10972
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000120) Port n Output Bit Clear 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.5..5> BCR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR4  -----------------------------------
+// SVD Line: 10978
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000120) Port n Output Bit Clear 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.4..4> BCR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR3  -----------------------------------
+// SVD Line: 10984
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000120) Port n Output Bit Clear 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.3..3> BCR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR2  -----------------------------------
+// SVD Line: 10990
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000120) Port n Output Bit Clear 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.2..2> BCR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR1  -----------------------------------
+// SVD Line: 10996
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000120) Port n Output Bit Clear 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.1..1> BCR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PB_PB_BCR_BCR0  -----------------------------------
+// SVD Line: 11002
+
+//  <item> SFDITEM_FIELD__PB_PB_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000120) Port n Output Bit Clear 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_BCR ) </loc>
+//      <o.0..0> BCR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PB_PB_BCR  -----------------------------------
+// SVD Line: 10902
+
+//  <rtree> SFDITEM_REG__PB_PB_BCR
+//    <name> PB_BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000120) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PB_PB_BCR >> 0) & 0xFFFFFFFF), ((PB_PB_BCR = (PB_PB_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: PB_PB_OUTDMSK  ------------------------------
+// SVD Line: 11010
+
+unsigned int PB_PB_OUTDMSK __AT (0x30000124);
+
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK15  ------------------------------
+// SVD Line: 11020
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000124) Port n Output Data Mask 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK14  ------------------------------
+// SVD Line: 11026
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000124) Port n Output Data Mask 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK13  ------------------------------
+// SVD Line: 11032
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000124) Port n Output Data Mask 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK12  ------------------------------
+// SVD Line: 11038
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000124) Port n Output Data Mask 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK11  ------------------------------
+// SVD Line: 11044
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000124) Port n Output Data Mask 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK10  ------------------------------
+// SVD Line: 11050
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000124) Port n Output Data Mask 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK9  -------------------------------
+// SVD Line: 11056
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000124) Port n Output Data Mask 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK8  -------------------------------
+// SVD Line: 11062
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000124) Port n Output Data Mask 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK7  -------------------------------
+// SVD Line: 11068
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000124) Port n Output Data Mask 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK6  -------------------------------
+// SVD Line: 11074
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000124) Port n Output Data Mask 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK5  -------------------------------
+// SVD Line: 11080
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000124) Port n Output Data Mask 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK4  -------------------------------
+// SVD Line: 11086
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000124) Port n Output Data Mask 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK3  -------------------------------
+// SVD Line: 11092
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000124) Port n Output Data Mask 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK2  -------------------------------
+// SVD Line: 11098
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000124) Port n Output Data Mask 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK1  -------------------------------
+// SVD Line: 11104
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000124) Port n Output Data Mask 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PB_PB_OUTDMSK_OUTDMSK0  -------------------------------
+// SVD Line: 11110
+
+//  <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000124) Port n Output Data Mask 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: PB_PB_OUTDMSK  ---------------------------------
+// SVD Line: 11010
+
+//  <rtree> SFDITEM_REG__PB_PB_OUTDMSK
+//    <name> PB_OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000124) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PB_PB_OUTDMSK >> 0) & 0xFFFFFFFF), ((PB_PB_OUTDMSK = (PB_PB_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PB_PB_DBCR  -------------------------------
+// SVD Line: 11118
+
+unsigned int PB_PB_DBCR __AT (0x30000128);
+
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBCLK  ----------------------------------
+// SVD Line: 11128
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000128) Port n Debounce Filter Sampling Clock Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PB_PB_DBCR >> 16) & 0x7), ((PB_PB_DBCR = (PB_PB_DBCR & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN11  ---------------------------------
+// SVD Line: 11134
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN11
+//    <name> DBEN11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000128) Port n Debounce Enable 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.11..11> DBEN11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN10  ---------------------------------
+// SVD Line: 11140
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN10
+//    <name> DBEN10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000128) Port n Debounce Enable 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.10..10> DBEN10
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN9  ----------------------------------
+// SVD Line: 11146
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN9
+//    <name> DBEN9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000128) Port n Debounce Enable 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.9..9> DBEN9
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN8  ----------------------------------
+// SVD Line: 11152
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN8
+//    <name> DBEN8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000128) Port n Debounce Enable 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.8..8> DBEN8
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN7  ----------------------------------
+// SVD Line: 11158
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN7
+//    <name> DBEN7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000128) Port n Debounce Enable 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.7..7> DBEN7
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN6  ----------------------------------
+// SVD Line: 11164
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN6
+//    <name> DBEN6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000128) Port n Debounce Enable 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.6..6> DBEN6
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN5  ----------------------------------
+// SVD Line: 11170
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN5
+//    <name> DBEN5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000128) Port n Debounce Enable 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.5..5> DBEN5
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN4  ----------------------------------
+// SVD Line: 11176
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN4
+//    <name> DBEN4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000128) Port n Debounce Enable 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.4..4> DBEN4
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN3  ----------------------------------
+// SVD Line: 11182
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000128) Port n Debounce Enable 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN2  ----------------------------------
+// SVD Line: 11188
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000128) Port n Debounce Enable 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN1  ----------------------------------
+// SVD Line: 11194
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000128) Port n Debounce Enable 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PB_PB_DBCR_DBEN0  ----------------------------------
+// SVD Line: 11200
+
+//  <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000128) Port n Debounce Enable 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PB_PB_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PB_PB_DBCR  -----------------------------------
+// SVD Line: 11118
+
+//  <rtree> SFDITEM_REG__PB_PB_DBCR
+//    <name> PB_DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000128) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PB_PB_DBCR >> 0) & 0xFFFFFFFF), ((PB_PB_DBCR = (PB_PB_DBCR & ~(0x70FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN11 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN10 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN9 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN8 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN7 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN6 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN5 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN4 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PB_PB_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------------  Peripheral View: PB  --------------------------------------
+// SVD Line: 10120
+
+//  <view> PB
+//    <name> PB </name>
+//    <item> SFDITEM_REG__PB_MOD </item>
+//    <item> SFDITEM_REG__PB_TYP </item>
+//    <item> SFDITEM_REG__PB_AFSR1 </item>
+//    <item> SFDITEM_REG__PB_AFSR2 </item>
+//    <item> SFDITEM_REG__PB_PUPD </item>
+//    <item> SFDITEM_REG__PB_INDR </item>
+//    <item> SFDITEM_REG__PB_OUTDR </item>
+//    <item> SFDITEM_REG__PB_BSR </item>
+//    <item> SFDITEM_REG__PB_BCR </item>
+//    <item> SFDITEM_REG__PB_OUTDMSK </item>
+//    <item> SFDITEM_REG__PB_DBCR </item>
+//    <item> SFDITEM_REG__PB_PB_MOD </item>
+//    <item> SFDITEM_REG__PB_PB_TYP </item>
+//    <item> SFDITEM_REG__PB_PB_AFSR1 </item>
+//    <item> SFDITEM_REG__PB_PB_AFSR2 </item>
+//    <item> SFDITEM_REG__PB_PB_PUPD </item>
+//    <item> SFDITEM_REG__PB_PB_INDR </item>
+//    <item> SFDITEM_REG__PB_PB_OUTDR </item>
+//    <item> SFDITEM_REG__PB_PB_BSR </item>
+//    <item> SFDITEM_REG__PB_PB_BCR </item>
+//    <item> SFDITEM_REG__PB_PB_OUTDMSK </item>
+//    <item> SFDITEM_REG__PB_PB_DBCR </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: PC_MOD  ---------------------------------
+// SVD Line: 6351
+
+unsigned int PC_MOD __AT (0x30000200);
+
+
+
+// --------------------------------  Field Item: PC_MOD_MODE15  -----------------------------------
+// SVD Line: 6360
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000200) \nPort n Mode Selection 15\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.31..30> MODE15
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE14  -----------------------------------
+// SVD Line: 6383
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000200) \nPort n Mode Selection 14\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.29..28> MODE14
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE13  -----------------------------------
+// SVD Line: 6406
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000200) \nPort n Mode Selection 13\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.27..26> MODE13
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE12  -----------------------------------
+// SVD Line: 6429
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000200) \nPort n Mode Selection 12\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.25..24> MODE12
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE11  -----------------------------------
+// SVD Line: 6452
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000200) \nPort n Mode Selection 11\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.23..22> MODE11
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE10  -----------------------------------
+// SVD Line: 6475
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000200) \nPort n Mode Selection 10\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.21..20> MODE10
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE9  ------------------------------------
+// SVD Line: 6498
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000200) \nPort n Mode Selection 9\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.19..18> MODE9
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE8  ------------------------------------
+// SVD Line: 6521
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000200) \nPort n Mode Selection 8\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.17..16> MODE8
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE7  ------------------------------------
+// SVD Line: 6544
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000200) \nPort n Mode Selection 7\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.15..14> MODE7
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE6  ------------------------------------
+// SVD Line: 6567
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000200) \nPort n Mode Selection 6\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.13..12> MODE6
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE5  ------------------------------------
+// SVD Line: 6590
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000200) \nPort n Mode Selection 5\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.11..10> MODE5
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE4  ------------------------------------
+// SVD Line: 6613
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000200) \nPort n Mode Selection 4\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.9..8> MODE4
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE3  ------------------------------------
+// SVD Line: 6636
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000200) \nPort n Mode Selection 3\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.7..6> MODE3
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE2  ------------------------------------
+// SVD Line: 6659
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000200) \nPort n Mode Selection 2\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.5..4> MODE2
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE1  ------------------------------------
+// SVD Line: 6682
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000200) \nPort n Mode Selection 1\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.3..2> MODE1
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_MOD_MODE0  ------------------------------------
+// SVD Line: 6705
+
+//  <item> SFDITEM_FIELD__PC_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000200) \nPort n Mode Selection 0\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_MOD ) </loc>
+//      <o.1..0> MODE0
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PC_MOD  -------------------------------------
+// SVD Line: 6351
+
+//  <rtree> SFDITEM_REG__PC_MOD
+//    <name> MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000200) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PC_MOD >> 0) & 0xFFFFFFFF), ((PC_MOD = (PC_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PC_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PC_TYP  ---------------------------------
+// SVD Line: 6730
+
+unsigned int PC_TYP __AT (0x30000204);
+
+
+
+// --------------------------------  Field Item: PC_TYP_TYP15  ------------------------------------
+// SVD Line: 6739
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000204) \nPort n Output Type Selection 15\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.15..15> TYP15
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_TYP_TYP14  ------------------------------------
+// SVD Line: 6757
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000204) \nPort n Output Type Selection 14\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.14..14> TYP14
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_TYP_TYP13  ------------------------------------
+// SVD Line: 6775
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000204) \nPort n Output Type Selection 13\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.13..13> TYP13
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_TYP_TYP12  ------------------------------------
+// SVD Line: 6793
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000204) \nPort n Output Type Selection 12\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.12..12> TYP12
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_TYP_TYP11  ------------------------------------
+// SVD Line: 6811
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000204) \nPort n Output Type Selection 11\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.11..11> TYP11
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_TYP_TYP10  ------------------------------------
+// SVD Line: 6829
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000204) \nPort n Output Type Selection 10\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.10..10> TYP10
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP9  ------------------------------------
+// SVD Line: 6847
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000204) \nPort n Output Type Selection 9\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.9..9> TYP9
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP8  ------------------------------------
+// SVD Line: 6865
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000204) \nPort n Output Type Selection 8\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.8..8> TYP8
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP7  ------------------------------------
+// SVD Line: 6883
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000204) \nPort n Output Type Selection 7\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.7..7> TYP7
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP6  ------------------------------------
+// SVD Line: 6901
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000204) \nPort n Output Type Selection 6\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.6..6> TYP6
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP5  ------------------------------------
+// SVD Line: 6919
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000204) \nPort n Output Type Selection 5\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.5..5> TYP5
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP4  ------------------------------------
+// SVD Line: 6937
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000204) \nPort n Output Type Selection 4\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.4..4> TYP4
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP3  ------------------------------------
+// SVD Line: 6955
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000204) \nPort n Output Type Selection 3\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.3..3> TYP3
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP2  ------------------------------------
+// SVD Line: 6973
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000204) \nPort n Output Type Selection 2\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.2..2> TYP2
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP1  ------------------------------------
+// SVD Line: 6991
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000204) \nPort n Output Type Selection 1\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.1..1> TYP1
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_TYP_TYP0  ------------------------------------
+// SVD Line: 7009
+
+//  <item> SFDITEM_FIELD__PC_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000204) \nPort n Output Type Selection 0\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_TYP ) </loc>
+//      <o.0..0> TYP0
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PC_TYP  -------------------------------------
+// SVD Line: 6730
+
+//  <rtree> SFDITEM_REG__PC_TYP
+//    <name> TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000204) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PC_TYP >> 0) & 0xFFFFFFFF), ((PC_TYP = (PC_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PC_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PC_AFSR1  --------------------------------
+// SVD Line: 7029
+
+unsigned int PC_AFSR1 __AT (0x30000208);
+
+
+
+// -------------------------------  Field Item: PC_AFSR1_AFSR7  -----------------------------------
+// SVD Line: 7038
+
+//  <item> SFDITEM_FIELD__PC_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000208) \nPort n Alternative Function Selection 7\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR1 ) </loc>
+//      <o.31..28> AFSR7
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR1_AFSR6  -----------------------------------
+// SVD Line: 7071
+
+//  <item> SFDITEM_FIELD__PC_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000208) \nPort n Alternative Function Selection 6\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR1 ) </loc>
+//      <o.27..24> AFSR6
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR1_AFSR5  -----------------------------------
+// SVD Line: 7104
+
+//  <item> SFDITEM_FIELD__PC_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000208) \nPort n Alternative Function Selection 5\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR1 ) </loc>
+//      <o.23..20> AFSR5
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR1_AFSR4  -----------------------------------
+// SVD Line: 7137
+
+//  <item> SFDITEM_FIELD__PC_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000208) \nPort n Alternative Function Selection 4\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR1 ) </loc>
+//      <o.19..16> AFSR4
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR1_AFSR3  -----------------------------------
+// SVD Line: 7170
+
+//  <item> SFDITEM_FIELD__PC_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000208) \nPort n Alternative Function Selection 3\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR1 ) </loc>
+//      <o.15..12> AFSR3
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR1_AFSR2  -----------------------------------
+// SVD Line: 7203
+
+//  <item> SFDITEM_FIELD__PC_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000208) \nPort n Alternative Function Selection 2\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR1 ) </loc>
+//      <o.11..8> AFSR2
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR1_AFSR1  -----------------------------------
+// SVD Line: 7236
+
+//  <item> SFDITEM_FIELD__PC_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000208) \nPort n Alternative Function Selection 1\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR1 ) </loc>
+//      <o.7..4> AFSR1
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR1_AFSR0  -----------------------------------
+// SVD Line: 7269
+
+//  <item> SFDITEM_FIELD__PC_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000208) \nPort n Alternative Function Selection 0\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR1 ) </loc>
+//      <o.3..0> AFSR0
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PC_AFSR1  ------------------------------------
+// SVD Line: 7029
+
+//  <rtree> SFDITEM_REG__PC_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000208) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PC_AFSR1 >> 0) & 0xFFFFFFFF), ((PC_AFSR1 = (PC_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PC_AFSR2  --------------------------------
+// SVD Line: 7304
+
+unsigned int PC_AFSR2 __AT (0x3000020C);
+
+
+
+// -------------------------------  Field Item: PC_AFSR2_AFSR15  ----------------------------------
+// SVD Line: 7313
+
+//  <item> SFDITEM_FIELD__PC_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x3000020C) \nPort n Alternative Function Selection 15\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR2 ) </loc>
+//      <o.31..28> AFSR15
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR2_AFSR14  ----------------------------------
+// SVD Line: 7346
+
+//  <item> SFDITEM_FIELD__PC_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x3000020C) \nPort n Alternative Function Selection 14\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR2 ) </loc>
+//      <o.27..24> AFSR14
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR2_AFSR13  ----------------------------------
+// SVD Line: 7379
+
+//  <item> SFDITEM_FIELD__PC_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x3000020C) \nPort n Alternative Function Selection 13\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR2 ) </loc>
+//      <o.23..20> AFSR13
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR2_AFSR12  ----------------------------------
+// SVD Line: 7412
+
+//  <item> SFDITEM_FIELD__PC_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000020C) \nPort n Alternative Function Selection 12\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR2 ) </loc>
+//      <o.19..16> AFSR12
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR2_AFSR11  ----------------------------------
+// SVD Line: 7445
+
+//  <item> SFDITEM_FIELD__PC_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000020C) \nPort n Alternative Function Selection 11\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR2 ) </loc>
+//      <o.15..12> AFSR11
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR2_AFSR10  ----------------------------------
+// SVD Line: 7478
+
+//  <item> SFDITEM_FIELD__PC_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000020C) \nPort n Alternative Function Selection 10\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR2 ) </loc>
+//      <o.11..8> AFSR10
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR2_AFSR9  -----------------------------------
+// SVD Line: 7511
+
+//  <item> SFDITEM_FIELD__PC_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000020C) \nPort n Alternative Function Selection 9\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR2 ) </loc>
+//      <o.7..4> AFSR9
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_AFSR2_AFSR8  -----------------------------------
+// SVD Line: 7544
+
+//  <item> SFDITEM_FIELD__PC_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000020C) \nPort n Alternative Function Selection 8\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_AFSR2 ) </loc>
+//      <o.3..0> AFSR8
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PC_AFSR2  ------------------------------------
+// SVD Line: 7304
+
+//  <rtree> SFDITEM_REG__PC_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000020C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PC_AFSR2 >> 0) & 0xFFFFFFFF), ((PC_AFSR2 = (PC_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PC_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PC_PUPD  ---------------------------------
+// SVD Line: 7579
+
+unsigned int PC_PUPD __AT (0x30000210);
+
+
+
+// -------------------------------  Field Item: PC_PUPD_PUPD15  -----------------------------------
+// SVD Line: 7588
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 15\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.31..30> PUPD15
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PUPD_PUPD14  -----------------------------------
+// SVD Line: 7611
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 14\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.29..28> PUPD14
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PUPD_PUPD13  -----------------------------------
+// SVD Line: 7634
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 13\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.27..26> PUPD13
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PUPD_PUPD12  -----------------------------------
+// SVD Line: 7657
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 12\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.25..24> PUPD12
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PUPD_PUPD11  -----------------------------------
+// SVD Line: 7680
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 11\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.23..22> PUPD11
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PUPD_PUPD10  -----------------------------------
+// SVD Line: 7703
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 10\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.21..20> PUPD10
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD9  -----------------------------------
+// SVD Line: 7726
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 9\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.19..18> PUPD9
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD8  -----------------------------------
+// SVD Line: 7749
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 8\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.17..16> PUPD8
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD7  -----------------------------------
+// SVD Line: 7772
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 7\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.15..14> PUPD7
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD6  -----------------------------------
+// SVD Line: 7795
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 6\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.13..12> PUPD6
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD5  -----------------------------------
+// SVD Line: 7818
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 5\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.11..10> PUPD5
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD4  -----------------------------------
+// SVD Line: 7841
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 4\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.9..8> PUPD4
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD3  -----------------------------------
+// SVD Line: 7864
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 3\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.7..6> PUPD3
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD2  -----------------------------------
+// SVD Line: 7887
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 2\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.5..4> PUPD2
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD1  -----------------------------------
+// SVD Line: 7910
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 1\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.3..2> PUPD1
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_PUPD_PUPD0  -----------------------------------
+// SVD Line: 7933
+
+//  <item> SFDITEM_FIELD__PC_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000210) \nPort n Pull-Up/Down Resistor Selection 0\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_PUPD ) </loc>
+//      <o.1..0> PUPD0
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PC_PUPD  ------------------------------------
+// SVD Line: 7579
+
+//  <rtree> SFDITEM_REG__PC_PUPD
+//    <name> PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PC_PUPD >> 0) & 0xFFFFFFFF), ((PC_PUPD = (PC_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PC_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PC_INDR  ---------------------------------
+// SVD Line: 7958
+
+unsigned int PC_INDR __AT (0x30000214);
+
+
+
+// -------------------------------  Field Item: PC_INDR_INDR15  -----------------------------------
+// SVD Line: 7967
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x30000214) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_INDR_INDR14  -----------------------------------
+// SVD Line: 7973
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x30000214) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_INDR_INDR13  -----------------------------------
+// SVD Line: 7979
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x30000214) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_INDR_INDR12  -----------------------------------
+// SVD Line: 7985
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000214) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_INDR_INDR11  -----------------------------------
+// SVD Line: 7991
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000214) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_INDR_INDR10  -----------------------------------
+// SVD Line: 7997
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000214) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR9  -----------------------------------
+// SVD Line: 8003
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000214) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR8  -----------------------------------
+// SVD Line: 8009
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000214) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR7  -----------------------------------
+// SVD Line: 8015
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000214) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR6  -----------------------------------
+// SVD Line: 8021
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000214) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR5  -----------------------------------
+// SVD Line: 8027
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000214) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR4  -----------------------------------
+// SVD Line: 8033
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000214) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR3  -----------------------------------
+// SVD Line: 8039
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000214) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR2  -----------------------------------
+// SVD Line: 8045
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000214) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR1  -----------------------------------
+// SVD Line: 8051
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000214) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_INDR_INDR0  -----------------------------------
+// SVD Line: 8057
+
+//  <item> SFDITEM_FIELD__PC_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000214) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PC_INDR  ------------------------------------
+// SVD Line: 7958
+
+//  <rtree> SFDITEM_REG__PC_INDR
+//    <name> INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000214) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PC_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PC_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PC_OUTDR  --------------------------------
+// SVD Line: 8065
+
+unsigned int PC_OUTDR __AT (0x30000218);
+
+
+
+// ------------------------------  Field Item: PC_OUTDR_OUTDR15  ----------------------------------
+// SVD Line: 8074
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000218) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_OUTDR_OUTDR14  ----------------------------------
+// SVD Line: 8080
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000218) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_OUTDR_OUTDR13  ----------------------------------
+// SVD Line: 8086
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000218) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_OUTDR_OUTDR12  ----------------------------------
+// SVD Line: 8092
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000218) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_OUTDR_OUTDR11  ----------------------------------
+// SVD Line: 8098
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000218) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_OUTDR_OUTDR10  ----------------------------------
+// SVD Line: 8104
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000218) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR9  ----------------------------------
+// SVD Line: 8110
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000218) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR8  ----------------------------------
+// SVD Line: 8116
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000218) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR7  ----------------------------------
+// SVD Line: 8122
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000218) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR6  ----------------------------------
+// SVD Line: 8128
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000218) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR5  ----------------------------------
+// SVD Line: 8134
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000218) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR4  ----------------------------------
+// SVD Line: 8140
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000218) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR3  ----------------------------------
+// SVD Line: 8146
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000218) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR2  ----------------------------------
+// SVD Line: 8152
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000218) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR1  ----------------------------------
+// SVD Line: 8158
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000218) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_OUTDR_OUTDR0  ----------------------------------
+// SVD Line: 8164
+
+//  <item> SFDITEM_FIELD__PC_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000218) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PC_OUTDR  ------------------------------------
+// SVD Line: 8065
+
+//  <rtree> SFDITEM_REG__PC_OUTDR
+//    <name> OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000218) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PC_OUTDR >> 0) & 0xFFFFFFFF), ((PC_OUTDR = (PC_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PC_BSR  ---------------------------------
+// SVD Line: 8172
+
+unsigned int PC_BSR __AT (0x3000021C);
+
+
+
+// --------------------------------  Field Item: PC_BSR_BSR15  ------------------------------------
+// SVD Line: 8181
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x3000021C) \nPort n Output Bit Set 15\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.15..15> BSR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BSR_BSR14  ------------------------------------
+// SVD Line: 8199
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x3000021C) \nPort n Output Bit Set 14\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.14..14> BSR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BSR_BSR13  ------------------------------------
+// SVD Line: 8217
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x3000021C) \nPort n Output Bit Set 13\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.13..13> BSR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BSR_BSR12  ------------------------------------
+// SVD Line: 8235
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000021C) \nPort n Output Bit Set 12\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.12..12> BSR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BSR_BSR11  ------------------------------------
+// SVD Line: 8253
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000021C) \nPort n Output Bit Set 11\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.11..11> BSR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BSR_BSR10  ------------------------------------
+// SVD Line: 8271
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000021C) \nPort n Output Bit Set 10\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.10..10> BSR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR9  ------------------------------------
+// SVD Line: 8289
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000021C) \nPort n Output Bit Set 9\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.9..9> BSR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR8  ------------------------------------
+// SVD Line: 8307
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000021C) \nPort n Output Bit Set 8\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.8..8> BSR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR7  ------------------------------------
+// SVD Line: 8325
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000021C) \nPort n Output Bit Set 7\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.7..7> BSR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR6  ------------------------------------
+// SVD Line: 8343
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000021C) \nPort n Output Bit Set 6\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.6..6> BSR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR5  ------------------------------------
+// SVD Line: 8361
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000021C) \nPort n Output Bit Set 5\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.5..5> BSR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR4  ------------------------------------
+// SVD Line: 8379
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000021C) \nPort n Output Bit Set 4\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.4..4> BSR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR3  ------------------------------------
+// SVD Line: 8397
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000021C) \nPort n Output Bit Set 3\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.3..3> BSR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR2  ------------------------------------
+// SVD Line: 8415
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000021C) \nPort n Output Bit Set 2\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.2..2> BSR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR1  ------------------------------------
+// SVD Line: 8433
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000021C) \nPort n Output Bit Set 1\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.1..1> BSR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BSR_BSR0  ------------------------------------
+// SVD Line: 8451
+
+//  <item> SFDITEM_FIELD__PC_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000021C) \nPort n Output Bit Set 0\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BSR ) </loc>
+//      <o.0..0> BSR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PC_BSR  -------------------------------------
+// SVD Line: 8172
+
+//  <rtree> SFDITEM_REG__PC_BSR
+//    <name> BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000021C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PC_BSR >> 0) & 0xFFFFFFFF), ((PC_BSR = (PC_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PC_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PC_BCR  ---------------------------------
+// SVD Line: 8471
+
+unsigned int PC_BCR __AT (0x30000220);
+
+
+
+// --------------------------------  Field Item: PC_BCR_BCR15  ------------------------------------
+// SVD Line: 8480
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x30000220) \nPort n Output Bit Clear 15\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.15..15> BCR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BCR_BCR14  ------------------------------------
+// SVD Line: 8498
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x30000220) \nPort n Output Bit Clear 14\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.14..14> BCR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BCR_BCR13  ------------------------------------
+// SVD Line: 8516
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x30000220) \nPort n Output Bit Clear 13\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.13..13> BCR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BCR_BCR12  ------------------------------------
+// SVD Line: 8534
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000220) \nPort n Output Bit Clear 12\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.12..12> BCR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BCR_BCR11  ------------------------------------
+// SVD Line: 8552
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000220) \nPort n Output Bit Clear 11\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.11..11> BCR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_BCR_BCR10  ------------------------------------
+// SVD Line: 8570
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000220) \nPort n Output Bit Clear 10\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.10..10> BCR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR9  ------------------------------------
+// SVD Line: 8588
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000220) \nPort n Output Bit Clear 9\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.9..9> BCR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR8  ------------------------------------
+// SVD Line: 8606
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000220) \nPort n Output Bit Clear 8\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.8..8> BCR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR7  ------------------------------------
+// SVD Line: 8624
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000220) \nPort n Output Bit Clear 7\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.7..7> BCR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR6  ------------------------------------
+// SVD Line: 8642
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000220) \nPort n Output Bit Clear 6\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.6..6> BCR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR5  ------------------------------------
+// SVD Line: 8660
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000220) \nPort n Output Bit Clear 5\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.5..5> BCR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR4  ------------------------------------
+// SVD Line: 8678
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000220) \nPort n Output Bit Clear 4\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.4..4> BCR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR3  ------------------------------------
+// SVD Line: 8696
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000220) \nPort n Output Bit Clear 3\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.3..3> BCR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR2  ------------------------------------
+// SVD Line: 8714
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000220) \nPort n Output Bit Clear 2\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.2..2> BCR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR1  ------------------------------------
+// SVD Line: 8732
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000220) \nPort n Output Bit Clear 1\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.1..1> BCR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PC_BCR_BCR0  ------------------------------------
+// SVD Line: 8750
+
+//  <item> SFDITEM_FIELD__PC_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000220) \nPort n Output Bit Clear 0\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_BCR ) </loc>
+//      <o.0..0> BCR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PC_BCR  -------------------------------------
+// SVD Line: 8471
+
+//  <rtree> SFDITEM_REG__PC_BCR
+//    <name> BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000220) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PC_BCR >> 0) & 0xFFFFFFFF), ((PC_BCR = (PC_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PC_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PC_OUTDMSK  -------------------------------
+// SVD Line: 8770
+
+unsigned int PC_OUTDMSK __AT (0x30000224);
+
+
+
+// ----------------------------  Field Item: PC_OUTDMSK_OUTDMSK15  --------------------------------
+// SVD Line: 8779
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000224) \nPort n Output Data Mask 15\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PC_OUTDMSK_OUTDMSK14  --------------------------------
+// SVD Line: 8797
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000224) \nPort n Output Data Mask 14\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PC_OUTDMSK_OUTDMSK13  --------------------------------
+// SVD Line: 8815
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000224) \nPort n Output Data Mask 13\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PC_OUTDMSK_OUTDMSK12  --------------------------------
+// SVD Line: 8833
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000224) \nPort n Output Data Mask 12\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PC_OUTDMSK_OUTDMSK11  --------------------------------
+// SVD Line: 8851
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000224) \nPort n Output Data Mask 11\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PC_OUTDMSK_OUTDMSK10  --------------------------------
+// SVD Line: 8869
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000224) \nPort n Output Data Mask 10\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK9  --------------------------------
+// SVD Line: 8887
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000224) \nPort n Output Data Mask 9\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK8  --------------------------------
+// SVD Line: 8905
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000224) \nPort n Output Data Mask 8\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK7  --------------------------------
+// SVD Line: 8923
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000224) \nPort n Output Data Mask 7\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK6  --------------------------------
+// SVD Line: 8941
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000224) \nPort n Output Data Mask 6\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK5  --------------------------------
+// SVD Line: 8959
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000224) \nPort n Output Data Mask 5\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK4  --------------------------------
+// SVD Line: 8977
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000224) \nPort n Output Data Mask 4\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK3  --------------------------------
+// SVD Line: 8995
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000224) \nPort n Output Data Mask 3\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK2  --------------------------------
+// SVD Line: 9013
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000224) \nPort n Output Data Mask 2\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK1  --------------------------------
+// SVD Line: 9031
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000224) \nPort n Output Data Mask 1\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_OUTDMSK_OUTDMSK0  --------------------------------
+// SVD Line: 9049
+
+//  <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000224) \nPort n Output Data Mask 0\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PC_OUTDMSK  -----------------------------------
+// SVD Line: 8770
+
+//  <rtree> SFDITEM_REG__PC_OUTDMSK
+//    <name> OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000224) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PC_OUTDMSK >> 0) & 0xFFFFFFFF), ((PC_OUTDMSK = (PC_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PC_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PC_DBCR  ---------------------------------
+// SVD Line: 9069
+
+unsigned int PC_DBCR __AT (0x30000228);
+
+
+
+// --------------------------------  Field Item: PC_DBCR_DBCLK  -----------------------------------
+// SVD Line: 9078
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000228) \nPort n Debounce Filter Sampling Clock Selection\n0 : HCLK1 = HCLK/1\n1 : HCLK4 = HCLK/4\n2 : HCLK16 = HCLK/16\n3 : HCLK64 = HCLK/64\n4 : HCLK256 = HCLK/256\n5 : HCLK1024 = HCLK/1024\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.18..16> DBCLK
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK4 = HCLK/4
+//        <2=> 2: HCLK16 = HCLK/16
+//        <3=> 3: HCLK64 = HCLK/64
+//        <4=> 4: HCLK256 = HCLK/256
+//        <5=> 5: HCLK1024 = HCLK/1024
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_DBCR_DBEN11  -----------------------------------
+// SVD Line: 9116
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN11
+//    <name> DBEN11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000228) \nPort n Debounce Enable 11\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.11..11> DBEN11
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_DBCR_DBEN10  -----------------------------------
+// SVD Line: 9134
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN10
+//    <name> DBEN10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000228) \nPort n Debounce Enable 10\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.10..10> DBEN10
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN9  -----------------------------------
+// SVD Line: 9152
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN9
+//    <name> DBEN9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000228) \nPort n Debounce Enable 9\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.9..9> DBEN9
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN8  -----------------------------------
+// SVD Line: 9170
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN8
+//    <name> DBEN8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000228) \nPort n Debounce Enable 8\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.8..8> DBEN8
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN7  -----------------------------------
+// SVD Line: 9188
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN7
+//    <name> DBEN7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000228) \nPort n Debounce Enable 7\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.7..7> DBEN7
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN6  -----------------------------------
+// SVD Line: 9206
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN6
+//    <name> DBEN6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000228) \nPort n Debounce Enable 6\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.6..6> DBEN6
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN5  -----------------------------------
+// SVD Line: 9224
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN5
+//    <name> DBEN5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000228) \nPort n Debounce Enable 5\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.5..5> DBEN5
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN4  -----------------------------------
+// SVD Line: 9242
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN4
+//    <name> DBEN4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000228) \nPort n Debounce Enable 4\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.4..4> DBEN4
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN3  -----------------------------------
+// SVD Line: 9260
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000228) \nPort n Debounce Enable 3\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN2  -----------------------------------
+// SVD Line: 9278
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000228) \nPort n Debounce Enable 2\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN1  -----------------------------------
+// SVD Line: 9296
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000228) \nPort n Debounce Enable 1\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PC_DBCR_DBEN0  -----------------------------------
+// SVD Line: 9314
+
+//  <item> SFDITEM_FIELD__PC_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000228) \nPort n Debounce Enable 0\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PC_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PC_DBCR  ------------------------------------
+// SVD Line: 9069
+
+//  <rtree> SFDITEM_REG__PC_DBCR
+//    <name> DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000228) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PC_DBCR >> 0) & 0xFFFFFFFF), ((PC_DBCR = (PC_DBCR & ~(0x70FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN11 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN10 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN9 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN8 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN7 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN6 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN5 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN4 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PC_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PC_PC_MOD  --------------------------------
+// SVD Line: 11224
+
+unsigned int PC_PC_MOD __AT (0x30000200);
+
+
+
+// ------------------------------  Field Item: PC_PC_MOD_MODE12  ----------------------------------
+// SVD Line: 11234
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000200) Port n Mode Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 24) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_MOD_MODE11  ----------------------------------
+// SVD Line: 11240
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000200) Port n Mode Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 22) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_MOD_MODE10  ----------------------------------
+// SVD Line: 11246
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000200) Port n Mode Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 20) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE9  ----------------------------------
+// SVD Line: 11252
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000200) Port n Mode Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 18) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE8  ----------------------------------
+// SVD Line: 11258
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000200) Port n Mode Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 16) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE7  ----------------------------------
+// SVD Line: 11264
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000200) Port n Mode Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 14) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE6  ----------------------------------
+// SVD Line: 11270
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000200) Port n Mode Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 12) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE5  ----------------------------------
+// SVD Line: 11276
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000200) Port n Mode Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 10) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE4  ----------------------------------
+// SVD Line: 11282
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000200) Port n Mode Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 8) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE3  ----------------------------------
+// SVD Line: 11288
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000200) Port n Mode Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 6) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE2  ----------------------------------
+// SVD Line: 11294
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000200) Port n Mode Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 4) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE1  ----------------------------------
+// SVD Line: 11300
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000200) Port n Mode Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 2) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_MOD_MODE0  ----------------------------------
+// SVD Line: 11306
+
+//  <item> SFDITEM_FIELD__PC_PC_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000200) Port n Mode Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_MOD >> 0) & 0x3), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PC_PC_MOD  -----------------------------------
+// SVD Line: 11224
+
+//  <rtree> SFDITEM_REG__PC_PC_MOD
+//    <name> PC_MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000200) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PC_PC_MOD >> 0) & 0xFFFFFFFF), ((PC_PC_MOD = (PC_PC_MOD & ~(0x3FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PC_PC_TYP  --------------------------------
+// SVD Line: 11314
+
+unsigned int PC_PC_TYP __AT (0x30000204);
+
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP12  ----------------------------------
+// SVD Line: 11324
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000204) Port n Output Type Selection 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.12..12> TYP12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP11  ----------------------------------
+// SVD Line: 11330
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000204) Port n Output Type Selection 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.11..11> TYP11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP10  ----------------------------------
+// SVD Line: 11336
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000204) Port n Output Type Selection 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.10..10> TYP10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP9  -----------------------------------
+// SVD Line: 11342
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000204) Port n Output Type Selection 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.9..9> TYP9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP8  -----------------------------------
+// SVD Line: 11348
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000204) Port n Output Type Selection 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.8..8> TYP8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP7  -----------------------------------
+// SVD Line: 11354
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000204) Port n Output Type Selection 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.7..7> TYP7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP6  -----------------------------------
+// SVD Line: 11360
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000204) Port n Output Type Selection 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.6..6> TYP6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP5  -----------------------------------
+// SVD Line: 11366
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000204) Port n Output Type Selection 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.5..5> TYP5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP4  -----------------------------------
+// SVD Line: 11372
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000204) Port n Output Type Selection 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.4..4> TYP4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP3  -----------------------------------
+// SVD Line: 11378
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000204) Port n Output Type Selection 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.3..3> TYP3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP2  -----------------------------------
+// SVD Line: 11384
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000204) Port n Output Type Selection 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.2..2> TYP2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP1  -----------------------------------
+// SVD Line: 11390
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000204) Port n Output Type Selection 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.1..1> TYP1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_TYP_TYP0  -----------------------------------
+// SVD Line: 11396
+
+//  <item> SFDITEM_FIELD__PC_PC_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000204) Port n Output Type Selection 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_TYP ) </loc>
+//      <o.0..0> TYP0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PC_PC_TYP  -----------------------------------
+// SVD Line: 11314
+
+//  <rtree> SFDITEM_REG__PC_PC_TYP
+//    <name> PC_TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000204) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PC_PC_TYP >> 0) & 0xFFFFFFFF), ((PC_PC_TYP = (PC_PC_TYP & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PC_PC_AFSR1  -------------------------------
+// SVD Line: 11404
+
+unsigned int PC_PC_AFSR1 __AT (0x30000208);
+
+
+
+// ------------------------------  Field Item: PC_PC_AFSR1_AFSR7  ---------------------------------
+// SVD Line: 11414
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000208) Port n Alternative Function Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR1 >> 28) & 0xF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR1_AFSR6  ---------------------------------
+// SVD Line: 11420
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000208) Port n Alternative Function Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR1 >> 24) & 0xF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR1_AFSR5  ---------------------------------
+// SVD Line: 11426
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000208) Port n Alternative Function Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR1 >> 20) & 0xF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR1_AFSR4  ---------------------------------
+// SVD Line: 11432
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000208) Port n Alternative Function Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR1 >> 16) & 0xF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR1_AFSR3  ---------------------------------
+// SVD Line: 11438
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000208) Port n Alternative Function Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR1 >> 12) & 0xF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR1_AFSR2  ---------------------------------
+// SVD Line: 11444
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000208) Port n Alternative Function Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR1 >> 8) & 0xF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR1_AFSR1  ---------------------------------
+// SVD Line: 11450
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000208) Port n Alternative Function Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR1 >> 4) & 0xF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR1_AFSR0  ---------------------------------
+// SVD Line: 11456
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000208) Port n Alternative Function Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR1 >> 0) & 0xF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PC_PC_AFSR1  ----------------------------------
+// SVD Line: 11404
+
+//  <rtree> SFDITEM_REG__PC_PC_AFSR1
+//    <name> PC_AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000208) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PC_PC_AFSR1 >> 0) & 0xFFFFFFFF), ((PC_PC_AFSR1 = (PC_PC_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PC_PC_AFSR2  -------------------------------
+// SVD Line: 11464
+
+unsigned int PC_PC_AFSR2 __AT (0x3000020C);
+
+
+
+// -----------------------------  Field Item: PC_PC_AFSR2_AFSR12  ---------------------------------
+// SVD Line: 11474
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000020C) Port n Alternative Function Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR2 >> 16) & 0xF), ((PC_PC_AFSR2 = (PC_PC_AFSR2 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_AFSR2_AFSR11  ---------------------------------
+// SVD Line: 11480
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000020C) Port n Alternative Function Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR2 >> 12) & 0xF), ((PC_PC_AFSR2 = (PC_PC_AFSR2 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_AFSR2_AFSR10  ---------------------------------
+// SVD Line: 11486
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000020C) Port n Alternative Function Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR2 >> 8) & 0xF), ((PC_PC_AFSR2 = (PC_PC_AFSR2 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR2_AFSR9  ---------------------------------
+// SVD Line: 11492
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000020C) Port n Alternative Function Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR2 >> 4) & 0xF), ((PC_PC_AFSR2 = (PC_PC_AFSR2 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_AFSR2_AFSR8  ---------------------------------
+// SVD Line: 11498
+
+//  <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000020C) Port n Alternative Function Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_AFSR2 >> 0) & 0xF), ((PC_PC_AFSR2 = (PC_PC_AFSR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PC_PC_AFSR2  ----------------------------------
+// SVD Line: 11464
+
+//  <rtree> SFDITEM_REG__PC_PC_AFSR2
+//    <name> PC_AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000020C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PC_PC_AFSR2 >> 0) & 0xFFFFFFFF), ((PC_PC_AFSR2 = (PC_PC_AFSR2 & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PC_PC_PUPD  -------------------------------
+// SVD Line: 11506
+
+unsigned int PC_PC_PUPD __AT (0x30000210);
+
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD12  ---------------------------------
+// SVD Line: 11516
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 24) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD11  ---------------------------------
+// SVD Line: 11522
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 22) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD10  ---------------------------------
+// SVD Line: 11528
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 20) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD9  ----------------------------------
+// SVD Line: 11534
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 18) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD8  ----------------------------------
+// SVD Line: 11540
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 16) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD7  ----------------------------------
+// SVD Line: 11546
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 14) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD6  ----------------------------------
+// SVD Line: 11552
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 12) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD5  ----------------------------------
+// SVD Line: 11558
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 10) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD4  ----------------------------------
+// SVD Line: 11564
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 8) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD3  ----------------------------------
+// SVD Line: 11570
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 6) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD2  ----------------------------------
+// SVD Line: 11576
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 4) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD1  ----------------------------------
+// SVD Line: 11582
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 2) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_PUPD_PUPD0  ----------------------------------
+// SVD Line: 11588
+
+//  <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_PUPD >> 0) & 0x3), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PC_PC_PUPD  -----------------------------------
+// SVD Line: 11506
+
+//  <rtree> SFDITEM_REG__PC_PC_PUPD
+//    <name> PC_PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000210) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PC_PC_PUPD >> 0) & 0xFFFFFFFF), ((PC_PC_PUPD = (PC_PC_PUPD & ~(0x3FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PC_PC_INDR  -------------------------------
+// SVD Line: 11596
+
+unsigned int PC_PC_INDR __AT (0x30000214);
+
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR12  ---------------------------------
+// SVD Line: 11606
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000214) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR11  ---------------------------------
+// SVD Line: 11612
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000214) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR10  ---------------------------------
+// SVD Line: 11618
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000214) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR9  ----------------------------------
+// SVD Line: 11624
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000214) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR8  ----------------------------------
+// SVD Line: 11630
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000214) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR7  ----------------------------------
+// SVD Line: 11636
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000214) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR6  ----------------------------------
+// SVD Line: 11642
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000214) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR5  ----------------------------------
+// SVD Line: 11648
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000214) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR4  ----------------------------------
+// SVD Line: 11654
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000214) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR3  ----------------------------------
+// SVD Line: 11660
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000214) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR2  ----------------------------------
+// SVD Line: 11666
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000214) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR1  ----------------------------------
+// SVD Line: 11672
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000214) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_INDR_INDR0  ----------------------------------
+// SVD Line: 11678
+
+//  <item> SFDITEM_FIELD__PC_PC_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000214) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PC_PC_INDR  -----------------------------------
+// SVD Line: 11596
+
+//  <rtree> SFDITEM_REG__PC_PC_INDR
+//    <name> PC_INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000214) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PC_PC_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PC_PC_OUTDR  -------------------------------
+// SVD Line: 11686
+
+unsigned int PC_PC_OUTDR __AT (0x30000218);
+
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR12  --------------------------------
+// SVD Line: 11696
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000218) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR11  --------------------------------
+// SVD Line: 11702
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000218) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR10  --------------------------------
+// SVD Line: 11708
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000218) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR9  ---------------------------------
+// SVD Line: 11714
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000218) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR8  ---------------------------------
+// SVD Line: 11720
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000218) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR7  ---------------------------------
+// SVD Line: 11726
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000218) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR6  ---------------------------------
+// SVD Line: 11732
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000218) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR5  ---------------------------------
+// SVD Line: 11738
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000218) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR4  ---------------------------------
+// SVD Line: 11744
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000218) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR3  ---------------------------------
+// SVD Line: 11750
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000218) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR2  ---------------------------------
+// SVD Line: 11756
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000218) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR1  ---------------------------------
+// SVD Line: 11762
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000218) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PC_PC_OUTDR_OUTDR0  ---------------------------------
+// SVD Line: 11768
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000218) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PC_PC_OUTDR  ----------------------------------
+// SVD Line: 11686
+
+//  <rtree> SFDITEM_REG__PC_PC_OUTDR
+//    <name> PC_OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000218) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PC_PC_OUTDR >> 0) & 0xFFFFFFFF), ((PC_PC_OUTDR = (PC_PC_OUTDR & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PC_PC_BSR  --------------------------------
+// SVD Line: 11776
+
+unsigned int PC_PC_BSR __AT (0x3000021C);
+
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR12  ----------------------------------
+// SVD Line: 11786
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000021C) Port n Output Bit Set 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.12..12> BSR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR11  ----------------------------------
+// SVD Line: 11792
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000021C) Port n Output Bit Set 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.11..11> BSR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR10  ----------------------------------
+// SVD Line: 11798
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000021C) Port n Output Bit Set 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.10..10> BSR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR9  -----------------------------------
+// SVD Line: 11804
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000021C) Port n Output Bit Set 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.9..9> BSR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR8  -----------------------------------
+// SVD Line: 11810
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000021C) Port n Output Bit Set 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.8..8> BSR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR7  -----------------------------------
+// SVD Line: 11816
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000021C) Port n Output Bit Set 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.7..7> BSR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR6  -----------------------------------
+// SVD Line: 11822
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000021C) Port n Output Bit Set 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.6..6> BSR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR5  -----------------------------------
+// SVD Line: 11828
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000021C) Port n Output Bit Set 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.5..5> BSR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR4  -----------------------------------
+// SVD Line: 11834
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000021C) Port n Output Bit Set 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.4..4> BSR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR3  -----------------------------------
+// SVD Line: 11840
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000021C) Port n Output Bit Set 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.3..3> BSR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR2  -----------------------------------
+// SVD Line: 11846
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000021C) Port n Output Bit Set 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.2..2> BSR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR1  -----------------------------------
+// SVD Line: 11852
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000021C) Port n Output Bit Set 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.1..1> BSR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BSR_BSR0  -----------------------------------
+// SVD Line: 11858
+
+//  <item> SFDITEM_FIELD__PC_PC_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000021C) Port n Output Bit Set 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BSR ) </loc>
+//      <o.0..0> BSR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PC_PC_BSR  -----------------------------------
+// SVD Line: 11776
+
+//  <rtree> SFDITEM_REG__PC_PC_BSR
+//    <name> PC_BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000021C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PC_PC_BSR >> 0) & 0xFFFFFFFF), ((PC_PC_BSR = (PC_PC_BSR & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PC_PC_BCR  --------------------------------
+// SVD Line: 11866
+
+unsigned int PC_PC_BCR __AT (0x30000220);
+
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR12  ----------------------------------
+// SVD Line: 11876
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000220) Port n Output Bit Clear 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.12..12> BCR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR11  ----------------------------------
+// SVD Line: 11882
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000220) Port n Output Bit Clear 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.11..11> BCR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR10  ----------------------------------
+// SVD Line: 11888
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000220) Port n Output Bit Clear 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.10..10> BCR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR9  -----------------------------------
+// SVD Line: 11894
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000220) Port n Output Bit Clear 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.9..9> BCR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR8  -----------------------------------
+// SVD Line: 11900
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000220) Port n Output Bit Clear 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.8..8> BCR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR7  -----------------------------------
+// SVD Line: 11906
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000220) Port n Output Bit Clear 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.7..7> BCR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR6  -----------------------------------
+// SVD Line: 11912
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000220) Port n Output Bit Clear 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.6..6> BCR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR5  -----------------------------------
+// SVD Line: 11918
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000220) Port n Output Bit Clear 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.5..5> BCR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR4  -----------------------------------
+// SVD Line: 11924
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000220) Port n Output Bit Clear 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.4..4> BCR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR3  -----------------------------------
+// SVD Line: 11930
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000220) Port n Output Bit Clear 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.3..3> BCR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR2  -----------------------------------
+// SVD Line: 11936
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000220) Port n Output Bit Clear 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.2..2> BCR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR1  -----------------------------------
+// SVD Line: 11942
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000220) Port n Output Bit Clear 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.1..1> BCR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PC_PC_BCR_BCR0  -----------------------------------
+// SVD Line: 11948
+
+//  <item> SFDITEM_FIELD__PC_PC_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000220) Port n Output Bit Clear 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_BCR ) </loc>
+//      <o.0..0> BCR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PC_PC_BCR  -----------------------------------
+// SVD Line: 11866
+
+//  <rtree> SFDITEM_REG__PC_PC_BCR
+//    <name> PC_BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000220) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PC_PC_BCR >> 0) & 0xFFFFFFFF), ((PC_PC_BCR = (PC_PC_BCR & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: PC_PC_OUTDMSK  ------------------------------
+// SVD Line: 11956
+
+unsigned int PC_PC_OUTDMSK __AT (0x30000224);
+
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK12  ------------------------------
+// SVD Line: 11966
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000224) Port n Output Data Mask 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK11  ------------------------------
+// SVD Line: 11972
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000224) Port n Output Data Mask 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK10  ------------------------------
+// SVD Line: 11978
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000224) Port n Output Data Mask 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK9  -------------------------------
+// SVD Line: 11984
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000224) Port n Output Data Mask 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK8  -------------------------------
+// SVD Line: 11990
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000224) Port n Output Data Mask 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK7  -------------------------------
+// SVD Line: 11996
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000224) Port n Output Data Mask 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK6  -------------------------------
+// SVD Line: 12002
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000224) Port n Output Data Mask 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK5  -------------------------------
+// SVD Line: 12008
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000224) Port n Output Data Mask 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK4  -------------------------------
+// SVD Line: 12014
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000224) Port n Output Data Mask 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK3  -------------------------------
+// SVD Line: 12020
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000224) Port n Output Data Mask 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK2  -------------------------------
+// SVD Line: 12026
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000224) Port n Output Data Mask 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK1  -------------------------------
+// SVD Line: 12032
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000224) Port n Output Data Mask 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PC_PC_OUTDMSK_OUTDMSK0  -------------------------------
+// SVD Line: 12038
+
+//  <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000224) Port n Output Data Mask 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: PC_PC_OUTDMSK  ---------------------------------
+// SVD Line: 11956
+
+//  <rtree> SFDITEM_REG__PC_PC_OUTDMSK
+//    <name> PC_OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000224) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PC_PC_OUTDMSK >> 0) & 0xFFFFFFFF), ((PC_PC_OUTDMSK = (PC_PC_OUTDMSK & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PC_PC_DBCR  -------------------------------
+// SVD Line: 12046
+
+unsigned int PC_PC_DBCR __AT (0x30000228);
+
+
+
+// ------------------------------  Field Item: PC_PC_DBCR_DBCLK  ----------------------------------
+// SVD Line: 12056
+
+//  <item> SFDITEM_FIELD__PC_PC_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000228) Port n Debounce Filter Sampling Clock Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PC_PC_DBCR >> 16) & 0x7), ((PC_PC_DBCR = (PC_PC_DBCR & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_DBCR_DBEN3  ----------------------------------
+// SVD Line: 12062
+
+//  <item> SFDITEM_FIELD__PC_PC_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000228) Port n Debounce Enable 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_DBCR_DBEN2  ----------------------------------
+// SVD Line: 12068
+
+//  <item> SFDITEM_FIELD__PC_PC_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000228) Port n Debounce Enable 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_DBCR_DBEN1  ----------------------------------
+// SVD Line: 12074
+
+//  <item> SFDITEM_FIELD__PC_PC_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000228) Port n Debounce Enable 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PC_PC_DBCR_DBEN0  ----------------------------------
+// SVD Line: 12080
+
+//  <item> SFDITEM_FIELD__PC_PC_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000228) Port n Debounce Enable 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PC_PC_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PC_PC_DBCR  -----------------------------------
+// SVD Line: 12046
+
+//  <rtree> SFDITEM_REG__PC_PC_DBCR
+//    <name> PC_DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000228) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PC_PC_DBCR >> 0) & 0xFFFFFFFF), ((PC_PC_DBCR = (PC_PC_DBCR & ~(0x7000FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7000F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PC_PC_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PC_PC_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PC_PC_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PC_PC_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PC_PC_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------------  Peripheral View: PC  --------------------------------------
+// SVD Line: 11210
+
+//  <view> PC
+//    <name> PC </name>
+//    <item> SFDITEM_REG__PC_MOD </item>
+//    <item> SFDITEM_REG__PC_TYP </item>
+//    <item> SFDITEM_REG__PC_AFSR1 </item>
+//    <item> SFDITEM_REG__PC_AFSR2 </item>
+//    <item> SFDITEM_REG__PC_PUPD </item>
+//    <item> SFDITEM_REG__PC_INDR </item>
+//    <item> SFDITEM_REG__PC_OUTDR </item>
+//    <item> SFDITEM_REG__PC_BSR </item>
+//    <item> SFDITEM_REG__PC_BCR </item>
+//    <item> SFDITEM_REG__PC_OUTDMSK </item>
+//    <item> SFDITEM_REG__PC_DBCR </item>
+//    <item> SFDITEM_REG__PC_PC_MOD </item>
+//    <item> SFDITEM_REG__PC_PC_TYP </item>
+//    <item> SFDITEM_REG__PC_PC_AFSR1 </item>
+//    <item> SFDITEM_REG__PC_PC_AFSR2 </item>
+//    <item> SFDITEM_REG__PC_PC_PUPD </item>
+//    <item> SFDITEM_REG__PC_PC_INDR </item>
+//    <item> SFDITEM_REG__PC_PC_OUTDR </item>
+//    <item> SFDITEM_REG__PC_PC_BSR </item>
+//    <item> SFDITEM_REG__PC_PC_BCR </item>
+//    <item> SFDITEM_REG__PC_PC_OUTDMSK </item>
+//    <item> SFDITEM_REG__PC_PC_DBCR </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: PD_MOD  ---------------------------------
+// SVD Line: 6351
+
+unsigned int PD_MOD __AT (0x30000300);
+
+
+
+// --------------------------------  Field Item: PD_MOD_MODE15  -----------------------------------
+// SVD Line: 6360
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000300) \nPort n Mode Selection 15\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.31..30> MODE15
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE14  -----------------------------------
+// SVD Line: 6383
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000300) \nPort n Mode Selection 14\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.29..28> MODE14
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE13  -----------------------------------
+// SVD Line: 6406
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000300) \nPort n Mode Selection 13\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.27..26> MODE13
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE12  -----------------------------------
+// SVD Line: 6429
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000300) \nPort n Mode Selection 12\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.25..24> MODE12
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE11  -----------------------------------
+// SVD Line: 6452
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000300) \nPort n Mode Selection 11\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.23..22> MODE11
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE10  -----------------------------------
+// SVD Line: 6475
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000300) \nPort n Mode Selection 10\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.21..20> MODE10
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE9  ------------------------------------
+// SVD Line: 6498
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000300) \nPort n Mode Selection 9\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.19..18> MODE9
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE8  ------------------------------------
+// SVD Line: 6521
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000300) \nPort n Mode Selection 8\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.17..16> MODE8
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE7  ------------------------------------
+// SVD Line: 6544
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000300) \nPort n Mode Selection 7\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.15..14> MODE7
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE6  ------------------------------------
+// SVD Line: 6567
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000300) \nPort n Mode Selection 6\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.13..12> MODE6
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE5  ------------------------------------
+// SVD Line: 6590
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000300) \nPort n Mode Selection 5\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.11..10> MODE5
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE4  ------------------------------------
+// SVD Line: 6613
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000300) \nPort n Mode Selection 4\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.9..8> MODE4
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE3  ------------------------------------
+// SVD Line: 6636
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000300) \nPort n Mode Selection 3\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.7..6> MODE3
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE2  ------------------------------------
+// SVD Line: 6659
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000300) \nPort n Mode Selection 2\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.5..4> MODE2
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE1  ------------------------------------
+// SVD Line: 6682
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000300) \nPort n Mode Selection 1\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.3..2> MODE1
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_MOD_MODE0  ------------------------------------
+// SVD Line: 6705
+
+//  <item> SFDITEM_FIELD__PD_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000300) \nPort n Mode Selection 0\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_MOD ) </loc>
+//      <o.1..0> MODE0
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PD_MOD  -------------------------------------
+// SVD Line: 6351
+
+//  <rtree> SFDITEM_REG__PD_MOD
+//    <name> MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000300) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PD_MOD >> 0) & 0xFFFFFFFF), ((PD_MOD = (PD_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PD_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PD_TYP  ---------------------------------
+// SVD Line: 6730
+
+unsigned int PD_TYP __AT (0x30000304);
+
+
+
+// --------------------------------  Field Item: PD_TYP_TYP15  ------------------------------------
+// SVD Line: 6739
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000304) \nPort n Output Type Selection 15\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.15..15> TYP15
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_TYP_TYP14  ------------------------------------
+// SVD Line: 6757
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000304) \nPort n Output Type Selection 14\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.14..14> TYP14
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_TYP_TYP13  ------------------------------------
+// SVD Line: 6775
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000304) \nPort n Output Type Selection 13\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.13..13> TYP13
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_TYP_TYP12  ------------------------------------
+// SVD Line: 6793
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000304) \nPort n Output Type Selection 12\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.12..12> TYP12
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_TYP_TYP11  ------------------------------------
+// SVD Line: 6811
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000304) \nPort n Output Type Selection 11\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.11..11> TYP11
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_TYP_TYP10  ------------------------------------
+// SVD Line: 6829
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000304) \nPort n Output Type Selection 10\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.10..10> TYP10
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP9  ------------------------------------
+// SVD Line: 6847
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000304) \nPort n Output Type Selection 9\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.9..9> TYP9
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP8  ------------------------------------
+// SVD Line: 6865
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000304) \nPort n Output Type Selection 8\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.8..8> TYP8
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP7  ------------------------------------
+// SVD Line: 6883
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000304) \nPort n Output Type Selection 7\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.7..7> TYP7
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP6  ------------------------------------
+// SVD Line: 6901
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000304) \nPort n Output Type Selection 6\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.6..6> TYP6
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP5  ------------------------------------
+// SVD Line: 6919
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000304) \nPort n Output Type Selection 5\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.5..5> TYP5
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP4  ------------------------------------
+// SVD Line: 6937
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000304) \nPort n Output Type Selection 4\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.4..4> TYP4
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP3  ------------------------------------
+// SVD Line: 6955
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000304) \nPort n Output Type Selection 3\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.3..3> TYP3
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP2  ------------------------------------
+// SVD Line: 6973
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000304) \nPort n Output Type Selection 2\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.2..2> TYP2
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP1  ------------------------------------
+// SVD Line: 6991
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000304) \nPort n Output Type Selection 1\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.1..1> TYP1
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_TYP_TYP0  ------------------------------------
+// SVD Line: 7009
+
+//  <item> SFDITEM_FIELD__PD_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000304) \nPort n Output Type Selection 0\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_TYP ) </loc>
+//      <o.0..0> TYP0
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PD_TYP  -------------------------------------
+// SVD Line: 6730
+
+//  <rtree> SFDITEM_REG__PD_TYP
+//    <name> TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000304) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PD_TYP >> 0) & 0xFFFFFFFF), ((PD_TYP = (PD_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PD_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PD_AFSR1  --------------------------------
+// SVD Line: 7029
+
+unsigned int PD_AFSR1 __AT (0x30000308);
+
+
+
+// -------------------------------  Field Item: PD_AFSR1_AFSR7  -----------------------------------
+// SVD Line: 7038
+
+//  <item> SFDITEM_FIELD__PD_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000308) \nPort n Alternative Function Selection 7\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR1 ) </loc>
+//      <o.31..28> AFSR7
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR1_AFSR6  -----------------------------------
+// SVD Line: 7071
+
+//  <item> SFDITEM_FIELD__PD_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000308) \nPort n Alternative Function Selection 6\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR1 ) </loc>
+//      <o.27..24> AFSR6
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR1_AFSR5  -----------------------------------
+// SVD Line: 7104
+
+//  <item> SFDITEM_FIELD__PD_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000308) \nPort n Alternative Function Selection 5\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR1 ) </loc>
+//      <o.23..20> AFSR5
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR1_AFSR4  -----------------------------------
+// SVD Line: 7137
+
+//  <item> SFDITEM_FIELD__PD_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000308) \nPort n Alternative Function Selection 4\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR1 ) </loc>
+//      <o.19..16> AFSR4
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR1_AFSR3  -----------------------------------
+// SVD Line: 7170
+
+//  <item> SFDITEM_FIELD__PD_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000308) \nPort n Alternative Function Selection 3\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR1 ) </loc>
+//      <o.15..12> AFSR3
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR1_AFSR2  -----------------------------------
+// SVD Line: 7203
+
+//  <item> SFDITEM_FIELD__PD_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000308) \nPort n Alternative Function Selection 2\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR1 ) </loc>
+//      <o.11..8> AFSR2
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR1_AFSR1  -----------------------------------
+// SVD Line: 7236
+
+//  <item> SFDITEM_FIELD__PD_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000308) \nPort n Alternative Function Selection 1\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR1 ) </loc>
+//      <o.7..4> AFSR1
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR1_AFSR0  -----------------------------------
+// SVD Line: 7269
+
+//  <item> SFDITEM_FIELD__PD_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000308) \nPort n Alternative Function Selection 0\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR1 ) </loc>
+//      <o.3..0> AFSR0
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PD_AFSR1  ------------------------------------
+// SVD Line: 7029
+
+//  <rtree> SFDITEM_REG__PD_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000308) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PD_AFSR1 >> 0) & 0xFFFFFFFF), ((PD_AFSR1 = (PD_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PD_AFSR2  --------------------------------
+// SVD Line: 7304
+
+unsigned int PD_AFSR2 __AT (0x3000030C);
+
+
+
+// -------------------------------  Field Item: PD_AFSR2_AFSR15  ----------------------------------
+// SVD Line: 7313
+
+//  <item> SFDITEM_FIELD__PD_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x3000030C) \nPort n Alternative Function Selection 15\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR2 ) </loc>
+//      <o.31..28> AFSR15
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR2_AFSR14  ----------------------------------
+// SVD Line: 7346
+
+//  <item> SFDITEM_FIELD__PD_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x3000030C) \nPort n Alternative Function Selection 14\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR2 ) </loc>
+//      <o.27..24> AFSR14
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR2_AFSR13  ----------------------------------
+// SVD Line: 7379
+
+//  <item> SFDITEM_FIELD__PD_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x3000030C) \nPort n Alternative Function Selection 13\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR2 ) </loc>
+//      <o.23..20> AFSR13
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR2_AFSR12  ----------------------------------
+// SVD Line: 7412
+
+//  <item> SFDITEM_FIELD__PD_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000030C) \nPort n Alternative Function Selection 12\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR2 ) </loc>
+//      <o.19..16> AFSR12
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR2_AFSR11  ----------------------------------
+// SVD Line: 7445
+
+//  <item> SFDITEM_FIELD__PD_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000030C) \nPort n Alternative Function Selection 11\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR2 ) </loc>
+//      <o.15..12> AFSR11
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR2_AFSR10  ----------------------------------
+// SVD Line: 7478
+
+//  <item> SFDITEM_FIELD__PD_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000030C) \nPort n Alternative Function Selection 10\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR2 ) </loc>
+//      <o.11..8> AFSR10
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR2_AFSR9  -----------------------------------
+// SVD Line: 7511
+
+//  <item> SFDITEM_FIELD__PD_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000030C) \nPort n Alternative Function Selection 9\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR2 ) </loc>
+//      <o.7..4> AFSR9
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_AFSR2_AFSR8  -----------------------------------
+// SVD Line: 7544
+
+//  <item> SFDITEM_FIELD__PD_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000030C) \nPort n Alternative Function Selection 8\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_AFSR2 ) </loc>
+//      <o.3..0> AFSR8
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PD_AFSR2  ------------------------------------
+// SVD Line: 7304
+
+//  <rtree> SFDITEM_REG__PD_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000030C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PD_AFSR2 >> 0) & 0xFFFFFFFF), ((PD_AFSR2 = (PD_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PD_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PD_PUPD  ---------------------------------
+// SVD Line: 7579
+
+unsigned int PD_PUPD __AT (0x30000310);
+
+
+
+// -------------------------------  Field Item: PD_PUPD_PUPD15  -----------------------------------
+// SVD Line: 7588
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 15\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.31..30> PUPD15
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PUPD_PUPD14  -----------------------------------
+// SVD Line: 7611
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 14\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.29..28> PUPD14
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PUPD_PUPD13  -----------------------------------
+// SVD Line: 7634
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 13\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.27..26> PUPD13
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PUPD_PUPD12  -----------------------------------
+// SVD Line: 7657
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 12\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.25..24> PUPD12
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PUPD_PUPD11  -----------------------------------
+// SVD Line: 7680
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 11\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.23..22> PUPD11
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PUPD_PUPD10  -----------------------------------
+// SVD Line: 7703
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 10\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.21..20> PUPD10
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD9  -----------------------------------
+// SVD Line: 7726
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 9\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.19..18> PUPD9
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD8  -----------------------------------
+// SVD Line: 7749
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 8\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.17..16> PUPD8
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD7  -----------------------------------
+// SVD Line: 7772
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 7\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.15..14> PUPD7
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD6  -----------------------------------
+// SVD Line: 7795
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 6\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.13..12> PUPD6
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD5  -----------------------------------
+// SVD Line: 7818
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 5\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.11..10> PUPD5
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD4  -----------------------------------
+// SVD Line: 7841
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 4\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.9..8> PUPD4
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD3  -----------------------------------
+// SVD Line: 7864
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 3\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.7..6> PUPD3
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD2  -----------------------------------
+// SVD Line: 7887
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 2\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.5..4> PUPD2
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD1  -----------------------------------
+// SVD Line: 7910
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 1\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.3..2> PUPD1
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_PUPD_PUPD0  -----------------------------------
+// SVD Line: 7933
+
+//  <item> SFDITEM_FIELD__PD_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000310) \nPort n Pull-Up/Down Resistor Selection 0\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_PUPD ) </loc>
+//      <o.1..0> PUPD0
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PD_PUPD  ------------------------------------
+// SVD Line: 7579
+
+//  <rtree> SFDITEM_REG__PD_PUPD
+//    <name> PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PD_PUPD >> 0) & 0xFFFFFFFF), ((PD_PUPD = (PD_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PD_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PD_INDR  ---------------------------------
+// SVD Line: 7958
+
+unsigned int PD_INDR __AT (0x30000314);
+
+
+
+// -------------------------------  Field Item: PD_INDR_INDR15  -----------------------------------
+// SVD Line: 7967
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x30000314) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_INDR_INDR14  -----------------------------------
+// SVD Line: 7973
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x30000314) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_INDR_INDR13  -----------------------------------
+// SVD Line: 7979
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x30000314) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_INDR_INDR12  -----------------------------------
+// SVD Line: 7985
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000314) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_INDR_INDR11  -----------------------------------
+// SVD Line: 7991
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000314) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_INDR_INDR10  -----------------------------------
+// SVD Line: 7997
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000314) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR9  -----------------------------------
+// SVD Line: 8003
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000314) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR8  -----------------------------------
+// SVD Line: 8009
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000314) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR7  -----------------------------------
+// SVD Line: 8015
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000314) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR6  -----------------------------------
+// SVD Line: 8021
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000314) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR5  -----------------------------------
+// SVD Line: 8027
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000314) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR4  -----------------------------------
+// SVD Line: 8033
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000314) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR3  -----------------------------------
+// SVD Line: 8039
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000314) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR2  -----------------------------------
+// SVD Line: 8045
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000314) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR1  -----------------------------------
+// SVD Line: 8051
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000314) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_INDR_INDR0  -----------------------------------
+// SVD Line: 8057
+
+//  <item> SFDITEM_FIELD__PD_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000314) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PD_INDR  ------------------------------------
+// SVD Line: 7958
+
+//  <rtree> SFDITEM_REG__PD_INDR
+//    <name> INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000314) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PD_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PD_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PD_OUTDR  --------------------------------
+// SVD Line: 8065
+
+unsigned int PD_OUTDR __AT (0x30000318);
+
+
+
+// ------------------------------  Field Item: PD_OUTDR_OUTDR15  ----------------------------------
+// SVD Line: 8074
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000318) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_OUTDR_OUTDR14  ----------------------------------
+// SVD Line: 8080
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000318) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_OUTDR_OUTDR13  ----------------------------------
+// SVD Line: 8086
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000318) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_OUTDR_OUTDR12  ----------------------------------
+// SVD Line: 8092
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000318) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_OUTDR_OUTDR11  ----------------------------------
+// SVD Line: 8098
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000318) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_OUTDR_OUTDR10  ----------------------------------
+// SVD Line: 8104
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000318) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR9  ----------------------------------
+// SVD Line: 8110
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000318) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR8  ----------------------------------
+// SVD Line: 8116
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000318) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR7  ----------------------------------
+// SVD Line: 8122
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000318) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR6  ----------------------------------
+// SVD Line: 8128
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000318) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR5  ----------------------------------
+// SVD Line: 8134
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000318) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR4  ----------------------------------
+// SVD Line: 8140
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000318) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR3  ----------------------------------
+// SVD Line: 8146
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000318) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR2  ----------------------------------
+// SVD Line: 8152
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000318) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR1  ----------------------------------
+// SVD Line: 8158
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000318) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_OUTDR_OUTDR0  ----------------------------------
+// SVD Line: 8164
+
+//  <item> SFDITEM_FIELD__PD_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000318) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PD_OUTDR  ------------------------------------
+// SVD Line: 8065
+
+//  <rtree> SFDITEM_REG__PD_OUTDR
+//    <name> OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000318) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PD_OUTDR >> 0) & 0xFFFFFFFF), ((PD_OUTDR = (PD_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PD_BSR  ---------------------------------
+// SVD Line: 8172
+
+unsigned int PD_BSR __AT (0x3000031C);
+
+
+
+// --------------------------------  Field Item: PD_BSR_BSR15  ------------------------------------
+// SVD Line: 8181
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x3000031C) \nPort n Output Bit Set 15\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.15..15> BSR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BSR_BSR14  ------------------------------------
+// SVD Line: 8199
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x3000031C) \nPort n Output Bit Set 14\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.14..14> BSR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BSR_BSR13  ------------------------------------
+// SVD Line: 8217
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x3000031C) \nPort n Output Bit Set 13\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.13..13> BSR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BSR_BSR12  ------------------------------------
+// SVD Line: 8235
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000031C) \nPort n Output Bit Set 12\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.12..12> BSR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BSR_BSR11  ------------------------------------
+// SVD Line: 8253
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000031C) \nPort n Output Bit Set 11\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.11..11> BSR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BSR_BSR10  ------------------------------------
+// SVD Line: 8271
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000031C) \nPort n Output Bit Set 10\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.10..10> BSR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR9  ------------------------------------
+// SVD Line: 8289
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000031C) \nPort n Output Bit Set 9\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.9..9> BSR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR8  ------------------------------------
+// SVD Line: 8307
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000031C) \nPort n Output Bit Set 8\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.8..8> BSR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR7  ------------------------------------
+// SVD Line: 8325
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000031C) \nPort n Output Bit Set 7\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.7..7> BSR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR6  ------------------------------------
+// SVD Line: 8343
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000031C) \nPort n Output Bit Set 6\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.6..6> BSR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR5  ------------------------------------
+// SVD Line: 8361
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000031C) \nPort n Output Bit Set 5\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.5..5> BSR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR4  ------------------------------------
+// SVD Line: 8379
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000031C) \nPort n Output Bit Set 4\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.4..4> BSR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR3  ------------------------------------
+// SVD Line: 8397
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000031C) \nPort n Output Bit Set 3\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.3..3> BSR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR2  ------------------------------------
+// SVD Line: 8415
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000031C) \nPort n Output Bit Set 2\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.2..2> BSR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR1  ------------------------------------
+// SVD Line: 8433
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000031C) \nPort n Output Bit Set 1\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.1..1> BSR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BSR_BSR0  ------------------------------------
+// SVD Line: 8451
+
+//  <item> SFDITEM_FIELD__PD_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000031C) \nPort n Output Bit Set 0\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BSR ) </loc>
+//      <o.0..0> BSR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PD_BSR  -------------------------------------
+// SVD Line: 8172
+
+//  <rtree> SFDITEM_REG__PD_BSR
+//    <name> BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000031C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PD_BSR >> 0) & 0xFFFFFFFF), ((PD_BSR = (PD_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PD_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PD_BCR  ---------------------------------
+// SVD Line: 8471
+
+unsigned int PD_BCR __AT (0x30000320);
+
+
+
+// --------------------------------  Field Item: PD_BCR_BCR15  ------------------------------------
+// SVD Line: 8480
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x30000320) \nPort n Output Bit Clear 15\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.15..15> BCR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BCR_BCR14  ------------------------------------
+// SVD Line: 8498
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x30000320) \nPort n Output Bit Clear 14\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.14..14> BCR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BCR_BCR13  ------------------------------------
+// SVD Line: 8516
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x30000320) \nPort n Output Bit Clear 13\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.13..13> BCR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BCR_BCR12  ------------------------------------
+// SVD Line: 8534
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000320) \nPort n Output Bit Clear 12\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.12..12> BCR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BCR_BCR11  ------------------------------------
+// SVD Line: 8552
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000320) \nPort n Output Bit Clear 11\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.11..11> BCR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_BCR_BCR10  ------------------------------------
+// SVD Line: 8570
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000320) \nPort n Output Bit Clear 10\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.10..10> BCR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR9  ------------------------------------
+// SVD Line: 8588
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000320) \nPort n Output Bit Clear 9\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.9..9> BCR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR8  ------------------------------------
+// SVD Line: 8606
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000320) \nPort n Output Bit Clear 8\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.8..8> BCR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR7  ------------------------------------
+// SVD Line: 8624
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000320) \nPort n Output Bit Clear 7\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.7..7> BCR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR6  ------------------------------------
+// SVD Line: 8642
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000320) \nPort n Output Bit Clear 6\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.6..6> BCR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR5  ------------------------------------
+// SVD Line: 8660
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000320) \nPort n Output Bit Clear 5\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.5..5> BCR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR4  ------------------------------------
+// SVD Line: 8678
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000320) \nPort n Output Bit Clear 4\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.4..4> BCR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR3  ------------------------------------
+// SVD Line: 8696
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000320) \nPort n Output Bit Clear 3\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.3..3> BCR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR2  ------------------------------------
+// SVD Line: 8714
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000320) \nPort n Output Bit Clear 2\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.2..2> BCR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR1  ------------------------------------
+// SVD Line: 8732
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000320) \nPort n Output Bit Clear 1\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.1..1> BCR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PD_BCR_BCR0  ------------------------------------
+// SVD Line: 8750
+
+//  <item> SFDITEM_FIELD__PD_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000320) \nPort n Output Bit Clear 0\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_BCR ) </loc>
+//      <o.0..0> BCR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PD_BCR  -------------------------------------
+// SVD Line: 8471
+
+//  <rtree> SFDITEM_REG__PD_BCR
+//    <name> BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000320) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PD_BCR >> 0) & 0xFFFFFFFF), ((PD_BCR = (PD_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PD_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PD_OUTDMSK  -------------------------------
+// SVD Line: 8770
+
+unsigned int PD_OUTDMSK __AT (0x30000324);
+
+
+
+// ----------------------------  Field Item: PD_OUTDMSK_OUTDMSK15  --------------------------------
+// SVD Line: 8779
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000324) \nPort n Output Data Mask 15\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PD_OUTDMSK_OUTDMSK14  --------------------------------
+// SVD Line: 8797
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000324) \nPort n Output Data Mask 14\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PD_OUTDMSK_OUTDMSK13  --------------------------------
+// SVD Line: 8815
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000324) \nPort n Output Data Mask 13\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PD_OUTDMSK_OUTDMSK12  --------------------------------
+// SVD Line: 8833
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000324) \nPort n Output Data Mask 12\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PD_OUTDMSK_OUTDMSK11  --------------------------------
+// SVD Line: 8851
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000324) \nPort n Output Data Mask 11\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PD_OUTDMSK_OUTDMSK10  --------------------------------
+// SVD Line: 8869
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000324) \nPort n Output Data Mask 10\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK9  --------------------------------
+// SVD Line: 8887
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000324) \nPort n Output Data Mask 9\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK8  --------------------------------
+// SVD Line: 8905
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000324) \nPort n Output Data Mask 8\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK7  --------------------------------
+// SVD Line: 8923
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000324) \nPort n Output Data Mask 7\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK6  --------------------------------
+// SVD Line: 8941
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000324) \nPort n Output Data Mask 6\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK5  --------------------------------
+// SVD Line: 8959
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000324) \nPort n Output Data Mask 5\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK4  --------------------------------
+// SVD Line: 8977
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000324) \nPort n Output Data Mask 4\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK3  --------------------------------
+// SVD Line: 8995
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000324) \nPort n Output Data Mask 3\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK2  --------------------------------
+// SVD Line: 9013
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000324) \nPort n Output Data Mask 2\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK1  --------------------------------
+// SVD Line: 9031
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000324) \nPort n Output Data Mask 1\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_OUTDMSK_OUTDMSK0  --------------------------------
+// SVD Line: 9049
+
+//  <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000324) \nPort n Output Data Mask 0\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PD_OUTDMSK  -----------------------------------
+// SVD Line: 8770
+
+//  <rtree> SFDITEM_REG__PD_OUTDMSK
+//    <name> OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000324) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PD_OUTDMSK >> 0) & 0xFFFFFFFF), ((PD_OUTDMSK = (PD_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PD_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PD_DBCR  ---------------------------------
+// SVD Line: 9069
+
+unsigned int PD_DBCR __AT (0x30000328);
+
+
+
+// --------------------------------  Field Item: PD_DBCR_DBCLK  -----------------------------------
+// SVD Line: 9078
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000328) \nPort n Debounce Filter Sampling Clock Selection\n0 : HCLK1 = HCLK/1\n1 : HCLK4 = HCLK/4\n2 : HCLK16 = HCLK/16\n3 : HCLK64 = HCLK/64\n4 : HCLK256 = HCLK/256\n5 : HCLK1024 = HCLK/1024\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.18..16> DBCLK
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK4 = HCLK/4
+//        <2=> 2: HCLK16 = HCLK/16
+//        <3=> 3: HCLK64 = HCLK/64
+//        <4=> 4: HCLK256 = HCLK/256
+//        <5=> 5: HCLK1024 = HCLK/1024
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_DBCR_DBEN11  -----------------------------------
+// SVD Line: 9116
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN11
+//    <name> DBEN11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000328) \nPort n Debounce Enable 11\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.11..11> DBEN11
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_DBCR_DBEN10  -----------------------------------
+// SVD Line: 9134
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN10
+//    <name> DBEN10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000328) \nPort n Debounce Enable 10\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.10..10> DBEN10
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN9  -----------------------------------
+// SVD Line: 9152
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN9
+//    <name> DBEN9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000328) \nPort n Debounce Enable 9\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.9..9> DBEN9
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN8  -----------------------------------
+// SVD Line: 9170
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN8
+//    <name> DBEN8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000328) \nPort n Debounce Enable 8\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.8..8> DBEN8
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN7  -----------------------------------
+// SVD Line: 9188
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN7
+//    <name> DBEN7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000328) \nPort n Debounce Enable 7\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.7..7> DBEN7
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN6  -----------------------------------
+// SVD Line: 9206
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN6
+//    <name> DBEN6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000328) \nPort n Debounce Enable 6\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.6..6> DBEN6
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN5  -----------------------------------
+// SVD Line: 9224
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN5
+//    <name> DBEN5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000328) \nPort n Debounce Enable 5\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.5..5> DBEN5
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN4  -----------------------------------
+// SVD Line: 9242
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN4
+//    <name> DBEN4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000328) \nPort n Debounce Enable 4\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.4..4> DBEN4
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN3  -----------------------------------
+// SVD Line: 9260
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000328) \nPort n Debounce Enable 3\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN2  -----------------------------------
+// SVD Line: 9278
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000328) \nPort n Debounce Enable 2\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN1  -----------------------------------
+// SVD Line: 9296
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000328) \nPort n Debounce Enable 1\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PD_DBCR_DBEN0  -----------------------------------
+// SVD Line: 9314
+
+//  <item> SFDITEM_FIELD__PD_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000328) \nPort n Debounce Enable 0\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PD_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PD_DBCR  ------------------------------------
+// SVD Line: 9069
+
+//  <rtree> SFDITEM_REG__PD_DBCR
+//    <name> DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000328) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PD_DBCR >> 0) & 0xFFFFFFFF), ((PD_DBCR = (PD_DBCR & ~(0x70FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN11 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN10 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN9 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN8 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN7 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN6 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN5 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN4 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PD_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PD_PD_MOD  --------------------------------
+// SVD Line: 12104
+
+unsigned int PD_PD_MOD __AT (0x30000300);
+
+
+
+// -------------------------------  Field Item: PD_PD_MOD_MODE7  ----------------------------------
+// SVD Line: 12114
+
+//  <item> SFDITEM_FIELD__PD_PD_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000300) Port n Mode Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_MOD >> 14) & 0x3), ((PD_PD_MOD = (PD_PD_MOD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_MOD_MODE6  ----------------------------------
+// SVD Line: 12120
+
+//  <item> SFDITEM_FIELD__PD_PD_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000300) Port n Mode Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_MOD >> 12) & 0x3), ((PD_PD_MOD = (PD_PD_MOD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_MOD_MODE5  ----------------------------------
+// SVD Line: 12126
+
+//  <item> SFDITEM_FIELD__PD_PD_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000300) Port n Mode Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_MOD >> 10) & 0x3), ((PD_PD_MOD = (PD_PD_MOD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_MOD_MODE4  ----------------------------------
+// SVD Line: 12132
+
+//  <item> SFDITEM_FIELD__PD_PD_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000300) Port n Mode Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_MOD >> 8) & 0x3), ((PD_PD_MOD = (PD_PD_MOD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_MOD_MODE3  ----------------------------------
+// SVD Line: 12138
+
+//  <item> SFDITEM_FIELD__PD_PD_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000300) Port n Mode Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_MOD >> 6) & 0x3), ((PD_PD_MOD = (PD_PD_MOD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_MOD_MODE2  ----------------------------------
+// SVD Line: 12144
+
+//  <item> SFDITEM_FIELD__PD_PD_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000300) Port n Mode Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_MOD >> 4) & 0x3), ((PD_PD_MOD = (PD_PD_MOD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_MOD_MODE1  ----------------------------------
+// SVD Line: 12150
+
+//  <item> SFDITEM_FIELD__PD_PD_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000300) Port n Mode Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_MOD >> 2) & 0x3), ((PD_PD_MOD = (PD_PD_MOD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_MOD_MODE0  ----------------------------------
+// SVD Line: 12156
+
+//  <item> SFDITEM_FIELD__PD_PD_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000300) Port n Mode Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_MOD >> 0) & 0x3), ((PD_PD_MOD = (PD_PD_MOD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PD_PD_MOD  -----------------------------------
+// SVD Line: 12104
+
+//  <rtree> SFDITEM_REG__PD_PD_MOD
+//    <name> PD_MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000300) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PD_PD_MOD >> 0) & 0xFFFFFFFF), ((PD_PD_MOD = (PD_PD_MOD & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PD_PD_TYP  --------------------------------
+// SVD Line: 12164
+
+unsigned int PD_PD_TYP __AT (0x30000304);
+
+
+
+// -------------------------------  Field Item: PD_PD_TYP_TYP7  -----------------------------------
+// SVD Line: 12174
+
+//  <item> SFDITEM_FIELD__PD_PD_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000304) Port n Output Type Selection 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_TYP ) </loc>
+//      <o.7..7> TYP7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_TYP_TYP6  -----------------------------------
+// SVD Line: 12180
+
+//  <item> SFDITEM_FIELD__PD_PD_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000304) Port n Output Type Selection 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_TYP ) </loc>
+//      <o.6..6> TYP6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_TYP_TYP5  -----------------------------------
+// SVD Line: 12186
+
+//  <item> SFDITEM_FIELD__PD_PD_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000304) Port n Output Type Selection 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_TYP ) </loc>
+//      <o.5..5> TYP5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_TYP_TYP4  -----------------------------------
+// SVD Line: 12192
+
+//  <item> SFDITEM_FIELD__PD_PD_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000304) Port n Output Type Selection 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_TYP ) </loc>
+//      <o.4..4> TYP4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_TYP_TYP3  -----------------------------------
+// SVD Line: 12198
+
+//  <item> SFDITEM_FIELD__PD_PD_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000304) Port n Output Type Selection 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_TYP ) </loc>
+//      <o.3..3> TYP3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_TYP_TYP2  -----------------------------------
+// SVD Line: 12204
+
+//  <item> SFDITEM_FIELD__PD_PD_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000304) Port n Output Type Selection 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_TYP ) </loc>
+//      <o.2..2> TYP2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_TYP_TYP1  -----------------------------------
+// SVD Line: 12210
+
+//  <item> SFDITEM_FIELD__PD_PD_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000304) Port n Output Type Selection 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_TYP ) </loc>
+//      <o.1..1> TYP1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_TYP_TYP0  -----------------------------------
+// SVD Line: 12216
+
+//  <item> SFDITEM_FIELD__PD_PD_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000304) Port n Output Type Selection 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_TYP ) </loc>
+//      <o.0..0> TYP0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PD_PD_TYP  -----------------------------------
+// SVD Line: 12164
+
+//  <rtree> SFDITEM_REG__PD_PD_TYP
+//    <name> PD_TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000304) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PD_PD_TYP >> 0) & 0xFFFFFFFF), ((PD_PD_TYP = (PD_PD_TYP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PD_PD_AFSR1  -------------------------------
+// SVD Line: 12224
+
+unsigned int PD_PD_AFSR1 __AT (0x30000308);
+
+
+
+// ------------------------------  Field Item: PD_PD_AFSR1_AFSR7  ---------------------------------
+// SVD Line: 12234
+
+//  <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000308) Port n Alternative Function Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_AFSR1 >> 28) & 0xF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_AFSR1_AFSR6  ---------------------------------
+// SVD Line: 12240
+
+//  <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000308) Port n Alternative Function Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_AFSR1 >> 24) & 0xF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_AFSR1_AFSR5  ---------------------------------
+// SVD Line: 12246
+
+//  <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000308) Port n Alternative Function Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_AFSR1 >> 20) & 0xF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_AFSR1_AFSR4  ---------------------------------
+// SVD Line: 12252
+
+//  <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000308) Port n Alternative Function Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_AFSR1 >> 16) & 0xF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_AFSR1_AFSR3  ---------------------------------
+// SVD Line: 12258
+
+//  <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000308) Port n Alternative Function Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_AFSR1 >> 12) & 0xF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_AFSR1_AFSR2  ---------------------------------
+// SVD Line: 12264
+
+//  <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000308) Port n Alternative Function Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_AFSR1 >> 8) & 0xF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_AFSR1_AFSR1  ---------------------------------
+// SVD Line: 12270
+
+//  <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000308) Port n Alternative Function Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_AFSR1 >> 4) & 0xF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_AFSR1_AFSR0  ---------------------------------
+// SVD Line: 12276
+
+//  <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000308) Port n Alternative Function Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_AFSR1 >> 0) & 0xF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PD_PD_AFSR1  ----------------------------------
+// SVD Line: 12224
+
+//  <rtree> SFDITEM_REG__PD_PD_AFSR1
+//    <name> PD_AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000308) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PD_PD_AFSR1 >> 0) & 0xFFFFFFFF), ((PD_PD_AFSR1 = (PD_PD_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PD_PD_AFSR2  -------------------------------
+// SVD Line: 12284
+
+unsigned int PD_PD_AFSR2 __AT (0x3000030C);
+
+
+
+// -------------------------------  Register Item: PD_PD_AFSR2  -----------------------------------
+// SVD Line: 12284
+
+//  <item> SFDITEM_REG__PD_PD_AFSR2
+//    <name> PD_AFSR2 </name>
+//    <i> [Bits 31..0] RW (@ 0x3000030C) Port n Alternative Function Selection Register 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((PD_PD_AFSR2 >> 0) & 0xFFFFFFFF), ((PD_PD_AFSR2 = (PD_PD_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------  Register Item Address: PD_PD_PUPD  -------------------------------
+// SVD Line: 12294
+
+unsigned int PD_PD_PUPD __AT (0x30000310);
+
+
+
+// ------------------------------  Field Item: PD_PD_PUPD_PUPD7  ----------------------------------
+// SVD Line: 12304
+
+//  <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_PUPD >> 14) & 0x3), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_PUPD_PUPD6  ----------------------------------
+// SVD Line: 12310
+
+//  <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_PUPD >> 12) & 0x3), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_PUPD_PUPD5  ----------------------------------
+// SVD Line: 12316
+
+//  <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_PUPD >> 10) & 0x3), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_PUPD_PUPD4  ----------------------------------
+// SVD Line: 12322
+
+//  <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_PUPD >> 8) & 0x3), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_PUPD_PUPD3  ----------------------------------
+// SVD Line: 12328
+
+//  <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_PUPD >> 6) & 0x3), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_PUPD_PUPD2  ----------------------------------
+// SVD Line: 12334
+
+//  <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_PUPD >> 4) & 0x3), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_PUPD_PUPD1  ----------------------------------
+// SVD Line: 12340
+
+//  <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_PUPD >> 2) & 0x3), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_PUPD_PUPD0  ----------------------------------
+// SVD Line: 12346
+
+//  <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PD_PD_PUPD >> 0) & 0x3), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PD_PD_PUPD  -----------------------------------
+// SVD Line: 12294
+
+//  <rtree> SFDITEM_REG__PD_PD_PUPD
+//    <name> PD_PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000310) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PD_PD_PUPD >> 0) & 0xFFFFFFFF), ((PD_PD_PUPD = (PD_PD_PUPD & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PD_PD_INDR  -------------------------------
+// SVD Line: 12354
+
+unsigned int PD_PD_INDR __AT (0x30000314);
+
+
+
+// ------------------------------  Field Item: PD_PD_INDR_INDR7  ----------------------------------
+// SVD Line: 12364
+
+//  <item> SFDITEM_FIELD__PD_PD_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000314) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_INDR_INDR6  ----------------------------------
+// SVD Line: 12370
+
+//  <item> SFDITEM_FIELD__PD_PD_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000314) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_INDR_INDR5  ----------------------------------
+// SVD Line: 12376
+
+//  <item> SFDITEM_FIELD__PD_PD_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000314) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_INDR_INDR4  ----------------------------------
+// SVD Line: 12382
+
+//  <item> SFDITEM_FIELD__PD_PD_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000314) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_INDR_INDR3  ----------------------------------
+// SVD Line: 12388
+
+//  <item> SFDITEM_FIELD__PD_PD_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000314) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_INDR_INDR2  ----------------------------------
+// SVD Line: 12394
+
+//  <item> SFDITEM_FIELD__PD_PD_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000314) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_INDR_INDR1  ----------------------------------
+// SVD Line: 12400
+
+//  <item> SFDITEM_FIELD__PD_PD_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000314) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PD_PD_INDR_INDR0  ----------------------------------
+// SVD Line: 12406
+
+//  <item> SFDITEM_FIELD__PD_PD_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000314) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PD_PD_INDR  -----------------------------------
+// SVD Line: 12354
+
+//  <rtree> SFDITEM_REG__PD_PD_INDR
+//    <name> PD_INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000314) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PD_PD_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PD_PD_OUTDR  -------------------------------
+// SVD Line: 12414
+
+unsigned int PD_PD_OUTDR __AT (0x30000318);
+
+
+
+// -----------------------------  Field Item: PD_PD_OUTDR_OUTDR7  ---------------------------------
+// SVD Line: 12424
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000318) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_PD_OUTDR_OUTDR6  ---------------------------------
+// SVD Line: 12430
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000318) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_PD_OUTDR_OUTDR5  ---------------------------------
+// SVD Line: 12436
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000318) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_PD_OUTDR_OUTDR4  ---------------------------------
+// SVD Line: 12442
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000318) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_PD_OUTDR_OUTDR3  ---------------------------------
+// SVD Line: 12448
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000318) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_PD_OUTDR_OUTDR2  ---------------------------------
+// SVD Line: 12454
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000318) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_PD_OUTDR_OUTDR1  ---------------------------------
+// SVD Line: 12460
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000318) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PD_PD_OUTDR_OUTDR0  ---------------------------------
+// SVD Line: 12466
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000318) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PD_PD_OUTDR  ----------------------------------
+// SVD Line: 12414
+
+//  <rtree> SFDITEM_REG__PD_PD_OUTDR
+//    <name> PD_OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000318) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PD_PD_OUTDR >> 0) & 0xFFFFFFFF), ((PD_PD_OUTDR = (PD_PD_OUTDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PD_PD_BSR  --------------------------------
+// SVD Line: 12474
+
+unsigned int PD_PD_BSR __AT (0x3000031C);
+
+
+
+// -------------------------------  Field Item: PD_PD_BSR_BSR7  -----------------------------------
+// SVD Line: 12484
+
+//  <item> SFDITEM_FIELD__PD_PD_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000031C) Port n Output Bit Set 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BSR ) </loc>
+//      <o.7..7> BSR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BSR_BSR6  -----------------------------------
+// SVD Line: 12490
+
+//  <item> SFDITEM_FIELD__PD_PD_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000031C) Port n Output Bit Set 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BSR ) </loc>
+//      <o.6..6> BSR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BSR_BSR5  -----------------------------------
+// SVD Line: 12496
+
+//  <item> SFDITEM_FIELD__PD_PD_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000031C) Port n Output Bit Set 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BSR ) </loc>
+//      <o.5..5> BSR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BSR_BSR4  -----------------------------------
+// SVD Line: 12502
+
+//  <item> SFDITEM_FIELD__PD_PD_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000031C) Port n Output Bit Set 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BSR ) </loc>
+//      <o.4..4> BSR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BSR_BSR3  -----------------------------------
+// SVD Line: 12508
+
+//  <item> SFDITEM_FIELD__PD_PD_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000031C) Port n Output Bit Set 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BSR ) </loc>
+//      <o.3..3> BSR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BSR_BSR2  -----------------------------------
+// SVD Line: 12514
+
+//  <item> SFDITEM_FIELD__PD_PD_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000031C) Port n Output Bit Set 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BSR ) </loc>
+//      <o.2..2> BSR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BSR_BSR1  -----------------------------------
+// SVD Line: 12520
+
+//  <item> SFDITEM_FIELD__PD_PD_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000031C) Port n Output Bit Set 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BSR ) </loc>
+//      <o.1..1> BSR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BSR_BSR0  -----------------------------------
+// SVD Line: 12526
+
+//  <item> SFDITEM_FIELD__PD_PD_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000031C) Port n Output Bit Set 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BSR ) </loc>
+//      <o.0..0> BSR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PD_PD_BSR  -----------------------------------
+// SVD Line: 12474
+
+//  <rtree> SFDITEM_REG__PD_PD_BSR
+//    <name> PD_BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000031C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PD_PD_BSR >> 0) & 0xFFFFFFFF), ((PD_PD_BSR = (PD_PD_BSR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PD_PD_BCR  --------------------------------
+// SVD Line: 12534
+
+unsigned int PD_PD_BCR __AT (0x30000320);
+
+
+
+// -------------------------------  Field Item: PD_PD_BCR_BCR7  -----------------------------------
+// SVD Line: 12544
+
+//  <item> SFDITEM_FIELD__PD_PD_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000320) Port n Output Bit Clear 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BCR ) </loc>
+//      <o.7..7> BCR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BCR_BCR6  -----------------------------------
+// SVD Line: 12550
+
+//  <item> SFDITEM_FIELD__PD_PD_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000320) Port n Output Bit Clear 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BCR ) </loc>
+//      <o.6..6> BCR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BCR_BCR5  -----------------------------------
+// SVD Line: 12556
+
+//  <item> SFDITEM_FIELD__PD_PD_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000320) Port n Output Bit Clear 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BCR ) </loc>
+//      <o.5..5> BCR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BCR_BCR4  -----------------------------------
+// SVD Line: 12562
+
+//  <item> SFDITEM_FIELD__PD_PD_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000320) Port n Output Bit Clear 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BCR ) </loc>
+//      <o.4..4> BCR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BCR_BCR3  -----------------------------------
+// SVD Line: 12568
+
+//  <item> SFDITEM_FIELD__PD_PD_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000320) Port n Output Bit Clear 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BCR ) </loc>
+//      <o.3..3> BCR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BCR_BCR2  -----------------------------------
+// SVD Line: 12574
+
+//  <item> SFDITEM_FIELD__PD_PD_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000320) Port n Output Bit Clear 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BCR ) </loc>
+//      <o.2..2> BCR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BCR_BCR1  -----------------------------------
+// SVD Line: 12580
+
+//  <item> SFDITEM_FIELD__PD_PD_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000320) Port n Output Bit Clear 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BCR ) </loc>
+//      <o.1..1> BCR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PD_PD_BCR_BCR0  -----------------------------------
+// SVD Line: 12586
+
+//  <item> SFDITEM_FIELD__PD_PD_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000320) Port n Output Bit Clear 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_BCR ) </loc>
+//      <o.0..0> BCR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PD_PD_BCR  -----------------------------------
+// SVD Line: 12534
+
+//  <rtree> SFDITEM_REG__PD_PD_BCR
+//    <name> PD_BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000320) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PD_PD_BCR >> 0) & 0xFFFFFFFF), ((PD_PD_BCR = (PD_PD_BCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: PD_PD_OUTDMSK  ------------------------------
+// SVD Line: 12594
+
+unsigned int PD_PD_OUTDMSK __AT (0x30000324);
+
+
+
+// ---------------------------  Field Item: PD_PD_OUTDMSK_OUTDMSK7  -------------------------------
+// SVD Line: 12604
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000324) Port n Output Data Mask 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PD_PD_OUTDMSK_OUTDMSK6  -------------------------------
+// SVD Line: 12610
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000324) Port n Output Data Mask 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PD_PD_OUTDMSK_OUTDMSK5  -------------------------------
+// SVD Line: 12616
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000324) Port n Output Data Mask 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PD_PD_OUTDMSK_OUTDMSK4  -------------------------------
+// SVD Line: 12622
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000324) Port n Output Data Mask 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PD_PD_OUTDMSK_OUTDMSK3  -------------------------------
+// SVD Line: 12628
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000324) Port n Output Data Mask 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PD_PD_OUTDMSK_OUTDMSK2  -------------------------------
+// SVD Line: 12634
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000324) Port n Output Data Mask 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PD_PD_OUTDMSK_OUTDMSK1  -------------------------------
+// SVD Line: 12640
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000324) Port n Output Data Mask 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PD_PD_OUTDMSK_OUTDMSK0  -------------------------------
+// SVD Line: 12646
+
+//  <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000324) Port n Output Data Mask 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PD_PD_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: PD_PD_OUTDMSK  ---------------------------------
+// SVD Line: 12594
+
+//  <rtree> SFDITEM_REG__PD_PD_OUTDMSK
+//    <name> PD_OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000324) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PD_PD_OUTDMSK >> 0) & 0xFFFFFFFF), ((PD_PD_OUTDMSK = (PD_PD_OUTDMSK & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PD_PD_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------------  Peripheral View: PD  --------------------------------------
+// SVD Line: 12090
+
+//  <view> PD
+//    <name> PD </name>
+//    <item> SFDITEM_REG__PD_MOD </item>
+//    <item> SFDITEM_REG__PD_TYP </item>
+//    <item> SFDITEM_REG__PD_AFSR1 </item>
+//    <item> SFDITEM_REG__PD_AFSR2 </item>
+//    <item> SFDITEM_REG__PD_PUPD </item>
+//    <item> SFDITEM_REG__PD_INDR </item>
+//    <item> SFDITEM_REG__PD_OUTDR </item>
+//    <item> SFDITEM_REG__PD_BSR </item>
+//    <item> SFDITEM_REG__PD_BCR </item>
+//    <item> SFDITEM_REG__PD_OUTDMSK </item>
+//    <item> SFDITEM_REG__PD_DBCR </item>
+//    <item> SFDITEM_REG__PD_PD_MOD </item>
+//    <item> SFDITEM_REG__PD_PD_TYP </item>
+//    <item> SFDITEM_REG__PD_PD_AFSR1 </item>
+//    <item> SFDITEM_REG__PD_PD_AFSR2 </item>
+//    <item> SFDITEM_REG__PD_PD_PUPD </item>
+//    <item> SFDITEM_REG__PD_PD_INDR </item>
+//    <item> SFDITEM_REG__PD_PD_OUTDR </item>
+//    <item> SFDITEM_REG__PD_PD_BSR </item>
+//    <item> SFDITEM_REG__PD_PD_BCR </item>
+//    <item> SFDITEM_REG__PD_PD_OUTDMSK </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: PE_MOD  ---------------------------------
+// SVD Line: 6351
+
+unsigned int PE_MOD __AT (0x30000400);
+
+
+
+// --------------------------------  Field Item: PE_MOD_MODE15  -----------------------------------
+// SVD Line: 6360
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000400) \nPort n Mode Selection 15\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.31..30> MODE15
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE14  -----------------------------------
+// SVD Line: 6383
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000400) \nPort n Mode Selection 14\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.29..28> MODE14
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE13  -----------------------------------
+// SVD Line: 6406
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000400) \nPort n Mode Selection 13\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.27..26> MODE13
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE12  -----------------------------------
+// SVD Line: 6429
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000400) \nPort n Mode Selection 12\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.25..24> MODE12
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE11  -----------------------------------
+// SVD Line: 6452
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000400) \nPort n Mode Selection 11\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.23..22> MODE11
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE10  -----------------------------------
+// SVD Line: 6475
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000400) \nPort n Mode Selection 10\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.21..20> MODE10
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE9  ------------------------------------
+// SVD Line: 6498
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000400) \nPort n Mode Selection 9\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.19..18> MODE9
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE8  ------------------------------------
+// SVD Line: 6521
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000400) \nPort n Mode Selection 8\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.17..16> MODE8
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE7  ------------------------------------
+// SVD Line: 6544
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000400) \nPort n Mode Selection 7\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.15..14> MODE7
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE6  ------------------------------------
+// SVD Line: 6567
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000400) \nPort n Mode Selection 6\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.13..12> MODE6
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE5  ------------------------------------
+// SVD Line: 6590
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000400) \nPort n Mode Selection 5\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.11..10> MODE5
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE4  ------------------------------------
+// SVD Line: 6613
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000400) \nPort n Mode Selection 4\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.9..8> MODE4
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE3  ------------------------------------
+// SVD Line: 6636
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000400) \nPort n Mode Selection 3\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.7..6> MODE3
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE2  ------------------------------------
+// SVD Line: 6659
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000400) \nPort n Mode Selection 2\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.5..4> MODE2
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE1  ------------------------------------
+// SVD Line: 6682
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000400) \nPort n Mode Selection 1\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.3..2> MODE1
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_MOD_MODE0  ------------------------------------
+// SVD Line: 6705
+
+//  <item> SFDITEM_FIELD__PE_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000400) \nPort n Mode Selection 0\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_MOD ) </loc>
+//      <o.1..0> MODE0
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PE_MOD  -------------------------------------
+// SVD Line: 6351
+
+//  <rtree> SFDITEM_REG__PE_MOD
+//    <name> MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000400) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PE_MOD >> 0) & 0xFFFFFFFF), ((PE_MOD = (PE_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PE_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PE_TYP  ---------------------------------
+// SVD Line: 6730
+
+unsigned int PE_TYP __AT (0x30000404);
+
+
+
+// --------------------------------  Field Item: PE_TYP_TYP15  ------------------------------------
+// SVD Line: 6739
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000404) \nPort n Output Type Selection 15\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.15..15> TYP15
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_TYP_TYP14  ------------------------------------
+// SVD Line: 6757
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000404) \nPort n Output Type Selection 14\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.14..14> TYP14
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_TYP_TYP13  ------------------------------------
+// SVD Line: 6775
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000404) \nPort n Output Type Selection 13\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.13..13> TYP13
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_TYP_TYP12  ------------------------------------
+// SVD Line: 6793
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000404) \nPort n Output Type Selection 12\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.12..12> TYP12
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_TYP_TYP11  ------------------------------------
+// SVD Line: 6811
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000404) \nPort n Output Type Selection 11\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.11..11> TYP11
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_TYP_TYP10  ------------------------------------
+// SVD Line: 6829
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000404) \nPort n Output Type Selection 10\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.10..10> TYP10
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP9  ------------------------------------
+// SVD Line: 6847
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000404) \nPort n Output Type Selection 9\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.9..9> TYP9
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP8  ------------------------------------
+// SVD Line: 6865
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000404) \nPort n Output Type Selection 8\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.8..8> TYP8
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP7  ------------------------------------
+// SVD Line: 6883
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000404) \nPort n Output Type Selection 7\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.7..7> TYP7
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP6  ------------------------------------
+// SVD Line: 6901
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000404) \nPort n Output Type Selection 6\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.6..6> TYP6
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP5  ------------------------------------
+// SVD Line: 6919
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000404) \nPort n Output Type Selection 5\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.5..5> TYP5
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP4  ------------------------------------
+// SVD Line: 6937
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000404) \nPort n Output Type Selection 4\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.4..4> TYP4
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP3  ------------------------------------
+// SVD Line: 6955
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000404) \nPort n Output Type Selection 3\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.3..3> TYP3
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP2  ------------------------------------
+// SVD Line: 6973
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000404) \nPort n Output Type Selection 2\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.2..2> TYP2
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP1  ------------------------------------
+// SVD Line: 6991
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000404) \nPort n Output Type Selection 1\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.1..1> TYP1
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_TYP_TYP0  ------------------------------------
+// SVD Line: 7009
+
+//  <item> SFDITEM_FIELD__PE_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000404) \nPort n Output Type Selection 0\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_TYP ) </loc>
+//      <o.0..0> TYP0
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PE_TYP  -------------------------------------
+// SVD Line: 6730
+
+//  <rtree> SFDITEM_REG__PE_TYP
+//    <name> TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000404) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PE_TYP >> 0) & 0xFFFFFFFF), ((PE_TYP = (PE_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PE_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PE_AFSR1  --------------------------------
+// SVD Line: 7029
+
+unsigned int PE_AFSR1 __AT (0x30000408);
+
+
+
+// -------------------------------  Field Item: PE_AFSR1_AFSR7  -----------------------------------
+// SVD Line: 7038
+
+//  <item> SFDITEM_FIELD__PE_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000408) \nPort n Alternative Function Selection 7\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR1 ) </loc>
+//      <o.31..28> AFSR7
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR1_AFSR6  -----------------------------------
+// SVD Line: 7071
+
+//  <item> SFDITEM_FIELD__PE_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000408) \nPort n Alternative Function Selection 6\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR1 ) </loc>
+//      <o.27..24> AFSR6
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR1_AFSR5  -----------------------------------
+// SVD Line: 7104
+
+//  <item> SFDITEM_FIELD__PE_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000408) \nPort n Alternative Function Selection 5\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR1 ) </loc>
+//      <o.23..20> AFSR5
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR1_AFSR4  -----------------------------------
+// SVD Line: 7137
+
+//  <item> SFDITEM_FIELD__PE_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000408) \nPort n Alternative Function Selection 4\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR1 ) </loc>
+//      <o.19..16> AFSR4
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR1_AFSR3  -----------------------------------
+// SVD Line: 7170
+
+//  <item> SFDITEM_FIELD__PE_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000408) \nPort n Alternative Function Selection 3\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR1 ) </loc>
+//      <o.15..12> AFSR3
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR1_AFSR2  -----------------------------------
+// SVD Line: 7203
+
+//  <item> SFDITEM_FIELD__PE_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000408) \nPort n Alternative Function Selection 2\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR1 ) </loc>
+//      <o.11..8> AFSR2
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR1_AFSR1  -----------------------------------
+// SVD Line: 7236
+
+//  <item> SFDITEM_FIELD__PE_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000408) \nPort n Alternative Function Selection 1\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR1 ) </loc>
+//      <o.7..4> AFSR1
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR1_AFSR0  -----------------------------------
+// SVD Line: 7269
+
+//  <item> SFDITEM_FIELD__PE_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000408) \nPort n Alternative Function Selection 0\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR1 ) </loc>
+//      <o.3..0> AFSR0
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PE_AFSR1  ------------------------------------
+// SVD Line: 7029
+
+//  <rtree> SFDITEM_REG__PE_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000408) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PE_AFSR1 >> 0) & 0xFFFFFFFF), ((PE_AFSR1 = (PE_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PE_AFSR2  --------------------------------
+// SVD Line: 7304
+
+unsigned int PE_AFSR2 __AT (0x3000040C);
+
+
+
+// -------------------------------  Field Item: PE_AFSR2_AFSR15  ----------------------------------
+// SVD Line: 7313
+
+//  <item> SFDITEM_FIELD__PE_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x3000040C) \nPort n Alternative Function Selection 15\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR2 ) </loc>
+//      <o.31..28> AFSR15
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR2_AFSR14  ----------------------------------
+// SVD Line: 7346
+
+//  <item> SFDITEM_FIELD__PE_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x3000040C) \nPort n Alternative Function Selection 14\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR2 ) </loc>
+//      <o.27..24> AFSR14
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR2_AFSR13  ----------------------------------
+// SVD Line: 7379
+
+//  <item> SFDITEM_FIELD__PE_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x3000040C) \nPort n Alternative Function Selection 13\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR2 ) </loc>
+//      <o.23..20> AFSR13
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR2_AFSR12  ----------------------------------
+// SVD Line: 7412
+
+//  <item> SFDITEM_FIELD__PE_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000040C) \nPort n Alternative Function Selection 12\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR2 ) </loc>
+//      <o.19..16> AFSR12
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR2_AFSR11  ----------------------------------
+// SVD Line: 7445
+
+//  <item> SFDITEM_FIELD__PE_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000040C) \nPort n Alternative Function Selection 11\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR2 ) </loc>
+//      <o.15..12> AFSR11
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR2_AFSR10  ----------------------------------
+// SVD Line: 7478
+
+//  <item> SFDITEM_FIELD__PE_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000040C) \nPort n Alternative Function Selection 10\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR2 ) </loc>
+//      <o.11..8> AFSR10
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR2_AFSR9  -----------------------------------
+// SVD Line: 7511
+
+//  <item> SFDITEM_FIELD__PE_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000040C) \nPort n Alternative Function Selection 9\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR2 ) </loc>
+//      <o.7..4> AFSR9
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_AFSR2_AFSR8  -----------------------------------
+// SVD Line: 7544
+
+//  <item> SFDITEM_FIELD__PE_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000040C) \nPort n Alternative Function Selection 8\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_AFSR2 ) </loc>
+//      <o.3..0> AFSR8
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PE_AFSR2  ------------------------------------
+// SVD Line: 7304
+
+//  <rtree> SFDITEM_REG__PE_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000040C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PE_AFSR2 >> 0) & 0xFFFFFFFF), ((PE_AFSR2 = (PE_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PE_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PE_PUPD  ---------------------------------
+// SVD Line: 7579
+
+unsigned int PE_PUPD __AT (0x30000410);
+
+
+
+// -------------------------------  Field Item: PE_PUPD_PUPD15  -----------------------------------
+// SVD Line: 7588
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 15\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.31..30> PUPD15
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PUPD_PUPD14  -----------------------------------
+// SVD Line: 7611
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 14\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.29..28> PUPD14
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PUPD_PUPD13  -----------------------------------
+// SVD Line: 7634
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 13\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.27..26> PUPD13
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PUPD_PUPD12  -----------------------------------
+// SVD Line: 7657
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 12\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.25..24> PUPD12
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PUPD_PUPD11  -----------------------------------
+// SVD Line: 7680
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 11\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.23..22> PUPD11
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PUPD_PUPD10  -----------------------------------
+// SVD Line: 7703
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 10\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.21..20> PUPD10
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD9  -----------------------------------
+// SVD Line: 7726
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 9\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.19..18> PUPD9
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD8  -----------------------------------
+// SVD Line: 7749
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 8\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.17..16> PUPD8
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD7  -----------------------------------
+// SVD Line: 7772
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 7\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.15..14> PUPD7
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD6  -----------------------------------
+// SVD Line: 7795
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 6\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.13..12> PUPD6
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD5  -----------------------------------
+// SVD Line: 7818
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 5\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.11..10> PUPD5
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD4  -----------------------------------
+// SVD Line: 7841
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 4\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.9..8> PUPD4
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD3  -----------------------------------
+// SVD Line: 7864
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 3\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.7..6> PUPD3
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD2  -----------------------------------
+// SVD Line: 7887
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 2\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.5..4> PUPD2
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD1  -----------------------------------
+// SVD Line: 7910
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 1\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.3..2> PUPD1
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_PUPD_PUPD0  -----------------------------------
+// SVD Line: 7933
+
+//  <item> SFDITEM_FIELD__PE_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000410) \nPort n Pull-Up/Down Resistor Selection 0\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_PUPD ) </loc>
+//      <o.1..0> PUPD0
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PE_PUPD  ------------------------------------
+// SVD Line: 7579
+
+//  <rtree> SFDITEM_REG__PE_PUPD
+//    <name> PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PE_PUPD >> 0) & 0xFFFFFFFF), ((PE_PUPD = (PE_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PE_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PE_INDR  ---------------------------------
+// SVD Line: 7958
+
+unsigned int PE_INDR __AT (0x30000414);
+
+
+
+// -------------------------------  Field Item: PE_INDR_INDR15  -----------------------------------
+// SVD Line: 7967
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x30000414) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_INDR_INDR14  -----------------------------------
+// SVD Line: 7973
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x30000414) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_INDR_INDR13  -----------------------------------
+// SVD Line: 7979
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x30000414) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_INDR_INDR12  -----------------------------------
+// SVD Line: 7985
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000414) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_INDR_INDR11  -----------------------------------
+// SVD Line: 7991
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000414) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_INDR_INDR10  -----------------------------------
+// SVD Line: 7997
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000414) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR9  -----------------------------------
+// SVD Line: 8003
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000414) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR8  -----------------------------------
+// SVD Line: 8009
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000414) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR7  -----------------------------------
+// SVD Line: 8015
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000414) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR6  -----------------------------------
+// SVD Line: 8021
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000414) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR5  -----------------------------------
+// SVD Line: 8027
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000414) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR4  -----------------------------------
+// SVD Line: 8033
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000414) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR3  -----------------------------------
+// SVD Line: 8039
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000414) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR2  -----------------------------------
+// SVD Line: 8045
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000414) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR1  -----------------------------------
+// SVD Line: 8051
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000414) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_INDR_INDR0  -----------------------------------
+// SVD Line: 8057
+
+//  <item> SFDITEM_FIELD__PE_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000414) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PE_INDR  ------------------------------------
+// SVD Line: 7958
+
+//  <rtree> SFDITEM_REG__PE_INDR
+//    <name> INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000414) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PE_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PE_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PE_OUTDR  --------------------------------
+// SVD Line: 8065
+
+unsigned int PE_OUTDR __AT (0x30000418);
+
+
+
+// ------------------------------  Field Item: PE_OUTDR_OUTDR15  ----------------------------------
+// SVD Line: 8074
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000418) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_OUTDR_OUTDR14  ----------------------------------
+// SVD Line: 8080
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000418) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_OUTDR_OUTDR13  ----------------------------------
+// SVD Line: 8086
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000418) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_OUTDR_OUTDR12  ----------------------------------
+// SVD Line: 8092
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000418) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_OUTDR_OUTDR11  ----------------------------------
+// SVD Line: 8098
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000418) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_OUTDR_OUTDR10  ----------------------------------
+// SVD Line: 8104
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000418) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR9  ----------------------------------
+// SVD Line: 8110
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000418) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR8  ----------------------------------
+// SVD Line: 8116
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000418) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR7  ----------------------------------
+// SVD Line: 8122
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000418) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR6  ----------------------------------
+// SVD Line: 8128
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000418) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR5  ----------------------------------
+// SVD Line: 8134
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000418) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR4  ----------------------------------
+// SVD Line: 8140
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000418) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR3  ----------------------------------
+// SVD Line: 8146
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000418) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR2  ----------------------------------
+// SVD Line: 8152
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000418) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR1  ----------------------------------
+// SVD Line: 8158
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000418) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_OUTDR_OUTDR0  ----------------------------------
+// SVD Line: 8164
+
+//  <item> SFDITEM_FIELD__PE_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000418) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PE_OUTDR  ------------------------------------
+// SVD Line: 8065
+
+//  <rtree> SFDITEM_REG__PE_OUTDR
+//    <name> OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000418) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PE_OUTDR >> 0) & 0xFFFFFFFF), ((PE_OUTDR = (PE_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PE_BSR  ---------------------------------
+// SVD Line: 8172
+
+unsigned int PE_BSR __AT (0x3000041C);
+
+
+
+// --------------------------------  Field Item: PE_BSR_BSR15  ------------------------------------
+// SVD Line: 8181
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x3000041C) \nPort n Output Bit Set 15\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.15..15> BSR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BSR_BSR14  ------------------------------------
+// SVD Line: 8199
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x3000041C) \nPort n Output Bit Set 14\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.14..14> BSR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BSR_BSR13  ------------------------------------
+// SVD Line: 8217
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x3000041C) \nPort n Output Bit Set 13\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.13..13> BSR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BSR_BSR12  ------------------------------------
+// SVD Line: 8235
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000041C) \nPort n Output Bit Set 12\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.12..12> BSR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BSR_BSR11  ------------------------------------
+// SVD Line: 8253
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000041C) \nPort n Output Bit Set 11\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.11..11> BSR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BSR_BSR10  ------------------------------------
+// SVD Line: 8271
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000041C) \nPort n Output Bit Set 10\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.10..10> BSR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR9  ------------------------------------
+// SVD Line: 8289
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000041C) \nPort n Output Bit Set 9\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.9..9> BSR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR8  ------------------------------------
+// SVD Line: 8307
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000041C) \nPort n Output Bit Set 8\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.8..8> BSR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR7  ------------------------------------
+// SVD Line: 8325
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000041C) \nPort n Output Bit Set 7\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.7..7> BSR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR6  ------------------------------------
+// SVD Line: 8343
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000041C) \nPort n Output Bit Set 6\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.6..6> BSR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR5  ------------------------------------
+// SVD Line: 8361
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000041C) \nPort n Output Bit Set 5\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.5..5> BSR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR4  ------------------------------------
+// SVD Line: 8379
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000041C) \nPort n Output Bit Set 4\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.4..4> BSR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR3  ------------------------------------
+// SVD Line: 8397
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000041C) \nPort n Output Bit Set 3\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.3..3> BSR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR2  ------------------------------------
+// SVD Line: 8415
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000041C) \nPort n Output Bit Set 2\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.2..2> BSR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR1  ------------------------------------
+// SVD Line: 8433
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000041C) \nPort n Output Bit Set 1\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.1..1> BSR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BSR_BSR0  ------------------------------------
+// SVD Line: 8451
+
+//  <item> SFDITEM_FIELD__PE_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000041C) \nPort n Output Bit Set 0\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BSR ) </loc>
+//      <o.0..0> BSR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PE_BSR  -------------------------------------
+// SVD Line: 8172
+
+//  <rtree> SFDITEM_REG__PE_BSR
+//    <name> BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000041C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PE_BSR >> 0) & 0xFFFFFFFF), ((PE_BSR = (PE_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PE_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PE_BCR  ---------------------------------
+// SVD Line: 8471
+
+unsigned int PE_BCR __AT (0x30000420);
+
+
+
+// --------------------------------  Field Item: PE_BCR_BCR15  ------------------------------------
+// SVD Line: 8480
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x30000420) \nPort n Output Bit Clear 15\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.15..15> BCR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BCR_BCR14  ------------------------------------
+// SVD Line: 8498
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x30000420) \nPort n Output Bit Clear 14\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.14..14> BCR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BCR_BCR13  ------------------------------------
+// SVD Line: 8516
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x30000420) \nPort n Output Bit Clear 13\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.13..13> BCR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BCR_BCR12  ------------------------------------
+// SVD Line: 8534
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000420) \nPort n Output Bit Clear 12\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.12..12> BCR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BCR_BCR11  ------------------------------------
+// SVD Line: 8552
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000420) \nPort n Output Bit Clear 11\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.11..11> BCR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_BCR_BCR10  ------------------------------------
+// SVD Line: 8570
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000420) \nPort n Output Bit Clear 10\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.10..10> BCR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR9  ------------------------------------
+// SVD Line: 8588
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000420) \nPort n Output Bit Clear 9\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.9..9> BCR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR8  ------------------------------------
+// SVD Line: 8606
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000420) \nPort n Output Bit Clear 8\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.8..8> BCR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR7  ------------------------------------
+// SVD Line: 8624
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000420) \nPort n Output Bit Clear 7\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.7..7> BCR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR6  ------------------------------------
+// SVD Line: 8642
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000420) \nPort n Output Bit Clear 6\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.6..6> BCR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR5  ------------------------------------
+// SVD Line: 8660
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000420) \nPort n Output Bit Clear 5\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.5..5> BCR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR4  ------------------------------------
+// SVD Line: 8678
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000420) \nPort n Output Bit Clear 4\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.4..4> BCR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR3  ------------------------------------
+// SVD Line: 8696
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000420) \nPort n Output Bit Clear 3\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.3..3> BCR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR2  ------------------------------------
+// SVD Line: 8714
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000420) \nPort n Output Bit Clear 2\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.2..2> BCR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR1  ------------------------------------
+// SVD Line: 8732
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000420) \nPort n Output Bit Clear 1\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.1..1> BCR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PE_BCR_BCR0  ------------------------------------
+// SVD Line: 8750
+
+//  <item> SFDITEM_FIELD__PE_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000420) \nPort n Output Bit Clear 0\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_BCR ) </loc>
+//      <o.0..0> BCR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PE_BCR  -------------------------------------
+// SVD Line: 8471
+
+//  <rtree> SFDITEM_REG__PE_BCR
+//    <name> BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000420) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PE_BCR >> 0) & 0xFFFFFFFF), ((PE_BCR = (PE_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PE_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PE_OUTDMSK  -------------------------------
+// SVD Line: 8770
+
+unsigned int PE_OUTDMSK __AT (0x30000424);
+
+
+
+// ----------------------------  Field Item: PE_OUTDMSK_OUTDMSK15  --------------------------------
+// SVD Line: 8779
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000424) \nPort n Output Data Mask 15\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PE_OUTDMSK_OUTDMSK14  --------------------------------
+// SVD Line: 8797
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000424) \nPort n Output Data Mask 14\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PE_OUTDMSK_OUTDMSK13  --------------------------------
+// SVD Line: 8815
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000424) \nPort n Output Data Mask 13\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PE_OUTDMSK_OUTDMSK12  --------------------------------
+// SVD Line: 8833
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000424) \nPort n Output Data Mask 12\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PE_OUTDMSK_OUTDMSK11  --------------------------------
+// SVD Line: 8851
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000424) \nPort n Output Data Mask 11\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PE_OUTDMSK_OUTDMSK10  --------------------------------
+// SVD Line: 8869
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000424) \nPort n Output Data Mask 10\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK9  --------------------------------
+// SVD Line: 8887
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000424) \nPort n Output Data Mask 9\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK8  --------------------------------
+// SVD Line: 8905
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000424) \nPort n Output Data Mask 8\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK7  --------------------------------
+// SVD Line: 8923
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000424) \nPort n Output Data Mask 7\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK6  --------------------------------
+// SVD Line: 8941
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000424) \nPort n Output Data Mask 6\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK5  --------------------------------
+// SVD Line: 8959
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000424) \nPort n Output Data Mask 5\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK4  --------------------------------
+// SVD Line: 8977
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000424) \nPort n Output Data Mask 4\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK3  --------------------------------
+// SVD Line: 8995
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000424) \nPort n Output Data Mask 3\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK2  --------------------------------
+// SVD Line: 9013
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000424) \nPort n Output Data Mask 2\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK1  --------------------------------
+// SVD Line: 9031
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000424) \nPort n Output Data Mask 1\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_OUTDMSK_OUTDMSK0  --------------------------------
+// SVD Line: 9049
+
+//  <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000424) \nPort n Output Data Mask 0\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PE_OUTDMSK  -----------------------------------
+// SVD Line: 8770
+
+//  <rtree> SFDITEM_REG__PE_OUTDMSK
+//    <name> OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000424) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PE_OUTDMSK >> 0) & 0xFFFFFFFF), ((PE_OUTDMSK = (PE_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PE_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PE_DBCR  ---------------------------------
+// SVD Line: 9069
+
+unsigned int PE_DBCR __AT (0x30000428);
+
+
+
+// --------------------------------  Field Item: PE_DBCR_DBCLK  -----------------------------------
+// SVD Line: 9078
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000428) \nPort n Debounce Filter Sampling Clock Selection\n0 : HCLK1 = HCLK/1\n1 : HCLK4 = HCLK/4\n2 : HCLK16 = HCLK/16\n3 : HCLK64 = HCLK/64\n4 : HCLK256 = HCLK/256\n5 : HCLK1024 = HCLK/1024\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.18..16> DBCLK
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK4 = HCLK/4
+//        <2=> 2: HCLK16 = HCLK/16
+//        <3=> 3: HCLK64 = HCLK/64
+//        <4=> 4: HCLK256 = HCLK/256
+//        <5=> 5: HCLK1024 = HCLK/1024
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_DBCR_DBEN11  -----------------------------------
+// SVD Line: 9116
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN11
+//    <name> DBEN11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000428) \nPort n Debounce Enable 11\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.11..11> DBEN11
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_DBCR_DBEN10  -----------------------------------
+// SVD Line: 9134
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN10
+//    <name> DBEN10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000428) \nPort n Debounce Enable 10\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.10..10> DBEN10
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN9  -----------------------------------
+// SVD Line: 9152
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN9
+//    <name> DBEN9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000428) \nPort n Debounce Enable 9\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.9..9> DBEN9
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN8  -----------------------------------
+// SVD Line: 9170
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN8
+//    <name> DBEN8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000428) \nPort n Debounce Enable 8\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.8..8> DBEN8
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN7  -----------------------------------
+// SVD Line: 9188
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN7
+//    <name> DBEN7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000428) \nPort n Debounce Enable 7\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.7..7> DBEN7
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN6  -----------------------------------
+// SVD Line: 9206
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN6
+//    <name> DBEN6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000428) \nPort n Debounce Enable 6\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.6..6> DBEN6
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN5  -----------------------------------
+// SVD Line: 9224
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN5
+//    <name> DBEN5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000428) \nPort n Debounce Enable 5\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.5..5> DBEN5
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN4  -----------------------------------
+// SVD Line: 9242
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN4
+//    <name> DBEN4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000428) \nPort n Debounce Enable 4\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.4..4> DBEN4
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN3  -----------------------------------
+// SVD Line: 9260
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000428) \nPort n Debounce Enable 3\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN2  -----------------------------------
+// SVD Line: 9278
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000428) \nPort n Debounce Enable 2\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN1  -----------------------------------
+// SVD Line: 9296
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000428) \nPort n Debounce Enable 1\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PE_DBCR_DBEN0  -----------------------------------
+// SVD Line: 9314
+
+//  <item> SFDITEM_FIELD__PE_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000428) \nPort n Debounce Enable 0\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PE_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PE_DBCR  ------------------------------------
+// SVD Line: 9069
+
+//  <rtree> SFDITEM_REG__PE_DBCR
+//    <name> DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000428) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PE_DBCR >> 0) & 0xFFFFFFFF), ((PE_DBCR = (PE_DBCR & ~(0x70FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN11 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN10 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN9 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN8 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN7 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN6 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN5 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN4 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PE_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PE_PE_MOD  --------------------------------
+// SVD Line: 12670
+
+unsigned int PE_PE_MOD __AT (0x30000400);
+
+
+
+// ------------------------------  Field Item: PE_PE_MOD_MODE15  ----------------------------------
+// SVD Line: 12680
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000400) Port n Mode Selection 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 30) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_MOD_MODE14  ----------------------------------
+// SVD Line: 12686
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000400) Port n Mode Selection 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 28) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_MOD_MODE13  ----------------------------------
+// SVD Line: 12692
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000400) Port n Mode Selection 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 26) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_MOD_MODE12  ----------------------------------
+// SVD Line: 12698
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000400) Port n Mode Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 24) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_MOD_MODE11  ----------------------------------
+// SVD Line: 12704
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000400) Port n Mode Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 22) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_MOD_MODE10  ----------------------------------
+// SVD Line: 12710
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000400) Port n Mode Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 20) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE9  ----------------------------------
+// SVD Line: 12716
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000400) Port n Mode Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 18) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE8  ----------------------------------
+// SVD Line: 12722
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000400) Port n Mode Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 16) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE7  ----------------------------------
+// SVD Line: 12728
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000400) Port n Mode Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 14) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE6  ----------------------------------
+// SVD Line: 12734
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000400) Port n Mode Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 12) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE5  ----------------------------------
+// SVD Line: 12740
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000400) Port n Mode Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 10) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE4  ----------------------------------
+// SVD Line: 12746
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000400) Port n Mode Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 8) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE3  ----------------------------------
+// SVD Line: 12752
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000400) Port n Mode Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 6) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE2  ----------------------------------
+// SVD Line: 12758
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000400) Port n Mode Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 4) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE1  ----------------------------------
+// SVD Line: 12764
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000400) Port n Mode Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 2) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_MOD_MODE0  ----------------------------------
+// SVD Line: 12770
+
+//  <item> SFDITEM_FIELD__PE_PE_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000400) Port n Mode Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_MOD >> 0) & 0x3), ((PE_PE_MOD = (PE_PE_MOD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PE_PE_MOD  -----------------------------------
+// SVD Line: 12670
+
+//  <rtree> SFDITEM_REG__PE_PE_MOD
+//    <name> PE_MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000400) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PE_PE_MOD >> 0) & 0xFFFFFFFF), ((PE_PE_MOD = (PE_PE_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PE_PE_TYP  --------------------------------
+// SVD Line: 12778
+
+unsigned int PE_PE_TYP __AT (0x30000404);
+
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP15  ----------------------------------
+// SVD Line: 12788
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000404) Port n Output Type Selection 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.15..15> TYP15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP14  ----------------------------------
+// SVD Line: 12794
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000404) Port n Output Type Selection 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.14..14> TYP14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP13  ----------------------------------
+// SVD Line: 12800
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000404) Port n Output Type Selection 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.13..13> TYP13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP12  ----------------------------------
+// SVD Line: 12806
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000404) Port n Output Type Selection 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.12..12> TYP12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP11  ----------------------------------
+// SVD Line: 12812
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000404) Port n Output Type Selection 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.11..11> TYP11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP10  ----------------------------------
+// SVD Line: 12818
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000404) Port n Output Type Selection 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.10..10> TYP10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP9  -----------------------------------
+// SVD Line: 12824
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000404) Port n Output Type Selection 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.9..9> TYP9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP8  -----------------------------------
+// SVD Line: 12830
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000404) Port n Output Type Selection 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.8..8> TYP8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP7  -----------------------------------
+// SVD Line: 12836
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000404) Port n Output Type Selection 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.7..7> TYP7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP6  -----------------------------------
+// SVD Line: 12842
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000404) Port n Output Type Selection 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.6..6> TYP6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP5  -----------------------------------
+// SVD Line: 12848
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000404) Port n Output Type Selection 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.5..5> TYP5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP4  -----------------------------------
+// SVD Line: 12854
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000404) Port n Output Type Selection 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.4..4> TYP4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP3  -----------------------------------
+// SVD Line: 12860
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000404) Port n Output Type Selection 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.3..3> TYP3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP2  -----------------------------------
+// SVD Line: 12866
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000404) Port n Output Type Selection 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.2..2> TYP2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP1  -----------------------------------
+// SVD Line: 12872
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000404) Port n Output Type Selection 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.1..1> TYP1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_TYP_TYP0  -----------------------------------
+// SVD Line: 12878
+
+//  <item> SFDITEM_FIELD__PE_PE_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000404) Port n Output Type Selection 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_TYP ) </loc>
+//      <o.0..0> TYP0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PE_PE_TYP  -----------------------------------
+// SVD Line: 12778
+
+//  <rtree> SFDITEM_REG__PE_PE_TYP
+//    <name> PE_TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000404) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PE_PE_TYP >> 0) & 0xFFFFFFFF), ((PE_PE_TYP = (PE_PE_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PE_PE_AFSR1  -------------------------------
+// SVD Line: 12886
+
+unsigned int PE_PE_AFSR1 __AT (0x30000408);
+
+
+
+// ------------------------------  Field Item: PE_PE_AFSR1_AFSR7  ---------------------------------
+// SVD Line: 12896
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000408) Port n Alternative Function Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR1 >> 28) & 0xF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR1_AFSR6  ---------------------------------
+// SVD Line: 12902
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000408) Port n Alternative Function Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR1 >> 24) & 0xF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR1_AFSR5  ---------------------------------
+// SVD Line: 12908
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000408) Port n Alternative Function Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR1 >> 20) & 0xF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR1_AFSR4  ---------------------------------
+// SVD Line: 12914
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000408) Port n Alternative Function Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR1 >> 16) & 0xF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR1_AFSR3  ---------------------------------
+// SVD Line: 12920
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000408) Port n Alternative Function Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR1 >> 12) & 0xF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR1_AFSR2  ---------------------------------
+// SVD Line: 12926
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000408) Port n Alternative Function Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR1 >> 8) & 0xF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR1_AFSR1  ---------------------------------
+// SVD Line: 12932
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000408) Port n Alternative Function Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR1 >> 4) & 0xF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR1_AFSR0  ---------------------------------
+// SVD Line: 12938
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000408) Port n Alternative Function Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR1 >> 0) & 0xF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PE_PE_AFSR1  ----------------------------------
+// SVD Line: 12886
+
+//  <rtree> SFDITEM_REG__PE_PE_AFSR1
+//    <name> PE_AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000408) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PE_PE_AFSR1 >> 0) & 0xFFFFFFFF), ((PE_PE_AFSR1 = (PE_PE_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PE_PE_AFSR2  -------------------------------
+// SVD Line: 12946
+
+unsigned int PE_PE_AFSR2 __AT (0x3000040C);
+
+
+
+// -----------------------------  Field Item: PE_PE_AFSR2_AFSR15  ---------------------------------
+// SVD Line: 12956
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x3000040C) Port n Alternative Function Selection 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR2 >> 28) & 0xF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_AFSR2_AFSR14  ---------------------------------
+// SVD Line: 12962
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x3000040C) Port n Alternative Function Selection 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR2 >> 24) & 0xF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_AFSR2_AFSR13  ---------------------------------
+// SVD Line: 12968
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x3000040C) Port n Alternative Function Selection 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR2 >> 20) & 0xF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_AFSR2_AFSR12  ---------------------------------
+// SVD Line: 12974
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000040C) Port n Alternative Function Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR2 >> 16) & 0xF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_AFSR2_AFSR11  ---------------------------------
+// SVD Line: 12980
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000040C) Port n Alternative Function Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR2 >> 12) & 0xF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_AFSR2_AFSR10  ---------------------------------
+// SVD Line: 12986
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000040C) Port n Alternative Function Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR2 >> 8) & 0xF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR2_AFSR9  ---------------------------------
+// SVD Line: 12992
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000040C) Port n Alternative Function Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR2 >> 4) & 0xF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_AFSR2_AFSR8  ---------------------------------
+// SVD Line: 12998
+
+//  <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000040C) Port n Alternative Function Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_AFSR2 >> 0) & 0xF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PE_PE_AFSR2  ----------------------------------
+// SVD Line: 12946
+
+//  <rtree> SFDITEM_REG__PE_PE_AFSR2
+//    <name> PE_AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000040C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PE_PE_AFSR2 >> 0) & 0xFFFFFFFF), ((PE_PE_AFSR2 = (PE_PE_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PE_PE_PUPD  -------------------------------
+// SVD Line: 13006
+
+unsigned int PE_PE_PUPD __AT (0x30000410);
+
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD15  ---------------------------------
+// SVD Line: 13016
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 30) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD14  ---------------------------------
+// SVD Line: 13022
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 28) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD13  ---------------------------------
+// SVD Line: 13028
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 26) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD12  ---------------------------------
+// SVD Line: 13034
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 24) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD11  ---------------------------------
+// SVD Line: 13040
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 22) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD10  ---------------------------------
+// SVD Line: 13046
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 20) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD9  ----------------------------------
+// SVD Line: 13052
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 18) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD8  ----------------------------------
+// SVD Line: 13058
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 16) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD7  ----------------------------------
+// SVD Line: 13064
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 14) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD6  ----------------------------------
+// SVD Line: 13070
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 12) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD5  ----------------------------------
+// SVD Line: 13076
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 10) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD4  ----------------------------------
+// SVD Line: 13082
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 8) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD3  ----------------------------------
+// SVD Line: 13088
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 6) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD2  ----------------------------------
+// SVD Line: 13094
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 4) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD1  ----------------------------------
+// SVD Line: 13100
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 2) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_PUPD_PUPD0  ----------------------------------
+// SVD Line: 13106
+
+//  <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_PUPD >> 0) & 0x3), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PE_PE_PUPD  -----------------------------------
+// SVD Line: 13006
+
+//  <rtree> SFDITEM_REG__PE_PE_PUPD
+//    <name> PE_PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000410) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PE_PE_PUPD >> 0) & 0xFFFFFFFF), ((PE_PE_PUPD = (PE_PE_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PE_PE_INDR  -------------------------------
+// SVD Line: 13114
+
+unsigned int PE_PE_INDR __AT (0x30000414);
+
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR15  ---------------------------------
+// SVD Line: 13124
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x30000414) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR14  ---------------------------------
+// SVD Line: 13130
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x30000414) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR13  ---------------------------------
+// SVD Line: 13136
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x30000414) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR12  ---------------------------------
+// SVD Line: 13142
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000414) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR11  ---------------------------------
+// SVD Line: 13148
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000414) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR10  ---------------------------------
+// SVD Line: 13154
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000414) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR9  ----------------------------------
+// SVD Line: 13160
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000414) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR8  ----------------------------------
+// SVD Line: 13166
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000414) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR7  ----------------------------------
+// SVD Line: 13172
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000414) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR6  ----------------------------------
+// SVD Line: 13178
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000414) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR5  ----------------------------------
+// SVD Line: 13184
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000414) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR4  ----------------------------------
+// SVD Line: 13190
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000414) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR3  ----------------------------------
+// SVD Line: 13196
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000414) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR2  ----------------------------------
+// SVD Line: 13202
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000414) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR1  ----------------------------------
+// SVD Line: 13208
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000414) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_INDR_INDR0  ----------------------------------
+// SVD Line: 13214
+
+//  <item> SFDITEM_FIELD__PE_PE_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000414) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PE_PE_INDR  -----------------------------------
+// SVD Line: 13114
+
+//  <rtree> SFDITEM_REG__PE_PE_INDR
+//    <name> PE_INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000414) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PE_PE_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PE_PE_OUTDR  -------------------------------
+// SVD Line: 13222
+
+unsigned int PE_PE_OUTDR __AT (0x30000418);
+
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR15  --------------------------------
+// SVD Line: 13232
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000418) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR14  --------------------------------
+// SVD Line: 13238
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000418) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR13  --------------------------------
+// SVD Line: 13244
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000418) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR12  --------------------------------
+// SVD Line: 13250
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000418) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR11  --------------------------------
+// SVD Line: 13256
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000418) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR10  --------------------------------
+// SVD Line: 13262
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000418) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR9  ---------------------------------
+// SVD Line: 13268
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000418) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR8  ---------------------------------
+// SVD Line: 13274
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000418) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR7  ---------------------------------
+// SVD Line: 13280
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000418) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR6  ---------------------------------
+// SVD Line: 13286
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000418) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR5  ---------------------------------
+// SVD Line: 13292
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000418) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR4  ---------------------------------
+// SVD Line: 13298
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000418) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR3  ---------------------------------
+// SVD Line: 13304
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000418) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR2  ---------------------------------
+// SVD Line: 13310
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000418) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR1  ---------------------------------
+// SVD Line: 13316
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000418) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PE_PE_OUTDR_OUTDR0  ---------------------------------
+// SVD Line: 13322
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000418) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PE_PE_OUTDR  ----------------------------------
+// SVD Line: 13222
+
+//  <rtree> SFDITEM_REG__PE_PE_OUTDR
+//    <name> PE_OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000418) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PE_PE_OUTDR >> 0) & 0xFFFFFFFF), ((PE_PE_OUTDR = (PE_PE_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PE_PE_BSR  --------------------------------
+// SVD Line: 13330
+
+unsigned int PE_PE_BSR __AT (0x3000041C);
+
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR15  ----------------------------------
+// SVD Line: 13340
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x3000041C) Port n Output Bit Set 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.15..15> BSR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR14  ----------------------------------
+// SVD Line: 13346
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x3000041C) Port n Output Bit Set 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.14..14> BSR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR13  ----------------------------------
+// SVD Line: 13352
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x3000041C) Port n Output Bit Set 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.13..13> BSR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR12  ----------------------------------
+// SVD Line: 13358
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000041C) Port n Output Bit Set 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.12..12> BSR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR11  ----------------------------------
+// SVD Line: 13364
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000041C) Port n Output Bit Set 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.11..11> BSR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR10  ----------------------------------
+// SVD Line: 13370
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000041C) Port n Output Bit Set 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.10..10> BSR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR9  -----------------------------------
+// SVD Line: 13376
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000041C) Port n Output Bit Set 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.9..9> BSR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR8  -----------------------------------
+// SVD Line: 13382
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000041C) Port n Output Bit Set 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.8..8> BSR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR7  -----------------------------------
+// SVD Line: 13388
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000041C) Port n Output Bit Set 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.7..7> BSR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR6  -----------------------------------
+// SVD Line: 13394
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000041C) Port n Output Bit Set 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.6..6> BSR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR5  -----------------------------------
+// SVD Line: 13400
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000041C) Port n Output Bit Set 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.5..5> BSR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR4  -----------------------------------
+// SVD Line: 13406
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000041C) Port n Output Bit Set 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.4..4> BSR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR3  -----------------------------------
+// SVD Line: 13412
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000041C) Port n Output Bit Set 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.3..3> BSR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR2  -----------------------------------
+// SVD Line: 13418
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000041C) Port n Output Bit Set 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.2..2> BSR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR1  -----------------------------------
+// SVD Line: 13424
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000041C) Port n Output Bit Set 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.1..1> BSR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BSR_BSR0  -----------------------------------
+// SVD Line: 13430
+
+//  <item> SFDITEM_FIELD__PE_PE_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000041C) Port n Output Bit Set 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BSR ) </loc>
+//      <o.0..0> BSR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PE_PE_BSR  -----------------------------------
+// SVD Line: 13330
+
+//  <rtree> SFDITEM_REG__PE_PE_BSR
+//    <name> PE_BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000041C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PE_PE_BSR >> 0) & 0xFFFFFFFF), ((PE_PE_BSR = (PE_PE_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PE_PE_BCR  --------------------------------
+// SVD Line: 13438
+
+unsigned int PE_PE_BCR __AT (0x30000420);
+
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR15  ----------------------------------
+// SVD Line: 13448
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x30000420) Port n Output Bit Clear 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.15..15> BCR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR14  ----------------------------------
+// SVD Line: 13454
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x30000420) Port n Output Bit Clear 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.14..14> BCR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR13  ----------------------------------
+// SVD Line: 13460
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x30000420) Port n Output Bit Clear 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.13..13> BCR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR12  ----------------------------------
+// SVD Line: 13466
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000420) Port n Output Bit Clear 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.12..12> BCR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR11  ----------------------------------
+// SVD Line: 13472
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000420) Port n Output Bit Clear 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.11..11> BCR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR10  ----------------------------------
+// SVD Line: 13478
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000420) Port n Output Bit Clear 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.10..10> BCR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR9  -----------------------------------
+// SVD Line: 13484
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000420) Port n Output Bit Clear 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.9..9> BCR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR8  -----------------------------------
+// SVD Line: 13490
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000420) Port n Output Bit Clear 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.8..8> BCR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR7  -----------------------------------
+// SVD Line: 13496
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000420) Port n Output Bit Clear 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.7..7> BCR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR6  -----------------------------------
+// SVD Line: 13502
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000420) Port n Output Bit Clear 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.6..6> BCR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR5  -----------------------------------
+// SVD Line: 13508
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000420) Port n Output Bit Clear 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.5..5> BCR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR4  -----------------------------------
+// SVD Line: 13514
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000420) Port n Output Bit Clear 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.4..4> BCR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR3  -----------------------------------
+// SVD Line: 13520
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000420) Port n Output Bit Clear 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.3..3> BCR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR2  -----------------------------------
+// SVD Line: 13526
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000420) Port n Output Bit Clear 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.2..2> BCR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR1  -----------------------------------
+// SVD Line: 13532
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000420) Port n Output Bit Clear 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.1..1> BCR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PE_PE_BCR_BCR0  -----------------------------------
+// SVD Line: 13538
+
+//  <item> SFDITEM_FIELD__PE_PE_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000420) Port n Output Bit Clear 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_BCR ) </loc>
+//      <o.0..0> BCR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PE_PE_BCR  -----------------------------------
+// SVD Line: 13438
+
+//  <rtree> SFDITEM_REG__PE_PE_BCR
+//    <name> PE_BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000420) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PE_PE_BCR >> 0) & 0xFFFFFFFF), ((PE_PE_BCR = (PE_PE_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: PE_PE_OUTDMSK  ------------------------------
+// SVD Line: 13546
+
+unsigned int PE_PE_OUTDMSK __AT (0x30000424);
+
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK15  ------------------------------
+// SVD Line: 13556
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000424) Port n Output Data Mask 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK14  ------------------------------
+// SVD Line: 13562
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000424) Port n Output Data Mask 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK13  ------------------------------
+// SVD Line: 13568
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000424) Port n Output Data Mask 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK12  ------------------------------
+// SVD Line: 13574
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000424) Port n Output Data Mask 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK11  ------------------------------
+// SVD Line: 13580
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000424) Port n Output Data Mask 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK10  ------------------------------
+// SVD Line: 13586
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000424) Port n Output Data Mask 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK9  -------------------------------
+// SVD Line: 13592
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000424) Port n Output Data Mask 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK8  -------------------------------
+// SVD Line: 13598
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000424) Port n Output Data Mask 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK7  -------------------------------
+// SVD Line: 13604
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000424) Port n Output Data Mask 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK6  -------------------------------
+// SVD Line: 13610
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000424) Port n Output Data Mask 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK5  -------------------------------
+// SVD Line: 13616
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000424) Port n Output Data Mask 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK4  -------------------------------
+// SVD Line: 13622
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000424) Port n Output Data Mask 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK3  -------------------------------
+// SVD Line: 13628
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000424) Port n Output Data Mask 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK2  -------------------------------
+// SVD Line: 13634
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000424) Port n Output Data Mask 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK1  -------------------------------
+// SVD Line: 13640
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000424) Port n Output Data Mask 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PE_PE_OUTDMSK_OUTDMSK0  -------------------------------
+// SVD Line: 13646
+
+//  <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000424) Port n Output Data Mask 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: PE_PE_OUTDMSK  ---------------------------------
+// SVD Line: 13546
+
+//  <rtree> SFDITEM_REG__PE_PE_OUTDMSK
+//    <name> PE_OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000424) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PE_PE_OUTDMSK >> 0) & 0xFFFFFFFF), ((PE_PE_OUTDMSK = (PE_PE_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PE_PE_DBCR  -------------------------------
+// SVD Line: 13654
+
+unsigned int PE_PE_DBCR __AT (0x30000428);
+
+
+
+// ------------------------------  Field Item: PE_PE_DBCR_DBCLK  ----------------------------------
+// SVD Line: 13664
+
+//  <item> SFDITEM_FIELD__PE_PE_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000428) Port n Debounce Filter Sampling Clock Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PE_PE_DBCR >> 16) & 0x7), ((PE_PE_DBCR = (PE_PE_DBCR & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_DBCR_DBEN3  ----------------------------------
+// SVD Line: 13670
+
+//  <item> SFDITEM_FIELD__PE_PE_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000428) Port n Debounce Enable 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_DBCR_DBEN2  ----------------------------------
+// SVD Line: 13676
+
+//  <item> SFDITEM_FIELD__PE_PE_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000428) Port n Debounce Enable 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_DBCR_DBEN1  ----------------------------------
+// SVD Line: 13682
+
+//  <item> SFDITEM_FIELD__PE_PE_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000428) Port n Debounce Enable 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PE_PE_DBCR_DBEN0  ----------------------------------
+// SVD Line: 13688
+
+//  <item> SFDITEM_FIELD__PE_PE_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000428) Port n Debounce Enable 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PE_PE_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PE_PE_DBCR  -----------------------------------
+// SVD Line: 13654
+
+//  <rtree> SFDITEM_REG__PE_PE_DBCR
+//    <name> PE_DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000428) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PE_PE_DBCR >> 0) & 0xFFFFFFFF), ((PE_PE_DBCR = (PE_PE_DBCR & ~(0x7000FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7000F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PE_PE_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PE_PE_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PE_PE_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PE_PE_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PE_PE_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------------  Peripheral View: PE  --------------------------------------
+// SVD Line: 12656
+
+//  <view> PE
+//    <name> PE </name>
+//    <item> SFDITEM_REG__PE_MOD </item>
+//    <item> SFDITEM_REG__PE_TYP </item>
+//    <item> SFDITEM_REG__PE_AFSR1 </item>
+//    <item> SFDITEM_REG__PE_AFSR2 </item>
+//    <item> SFDITEM_REG__PE_PUPD </item>
+//    <item> SFDITEM_REG__PE_INDR </item>
+//    <item> SFDITEM_REG__PE_OUTDR </item>
+//    <item> SFDITEM_REG__PE_BSR </item>
+//    <item> SFDITEM_REG__PE_BCR </item>
+//    <item> SFDITEM_REG__PE_OUTDMSK </item>
+//    <item> SFDITEM_REG__PE_DBCR </item>
+//    <item> SFDITEM_REG__PE_PE_MOD </item>
+//    <item> SFDITEM_REG__PE_PE_TYP </item>
+//    <item> SFDITEM_REG__PE_PE_AFSR1 </item>
+//    <item> SFDITEM_REG__PE_PE_AFSR2 </item>
+//    <item> SFDITEM_REG__PE_PE_PUPD </item>
+//    <item> SFDITEM_REG__PE_PE_INDR </item>
+//    <item> SFDITEM_REG__PE_PE_OUTDR </item>
+//    <item> SFDITEM_REG__PE_PE_BSR </item>
+//    <item> SFDITEM_REG__PE_PE_BCR </item>
+//    <item> SFDITEM_REG__PE_PE_OUTDMSK </item>
+//    <item> SFDITEM_REG__PE_PE_DBCR </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: PF_MOD  ---------------------------------
+// SVD Line: 6351
+
+unsigned int PF_MOD __AT (0x30000500);
+
+
+
+// --------------------------------  Field Item: PF_MOD_MODE15  -----------------------------------
+// SVD Line: 6360
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE15
+//    <name> MODE15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000500) \nPort n Mode Selection 15\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.31..30> MODE15
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE14  -----------------------------------
+// SVD Line: 6383
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE14
+//    <name> MODE14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000500) \nPort n Mode Selection 14\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.29..28> MODE14
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE13  -----------------------------------
+// SVD Line: 6406
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE13
+//    <name> MODE13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000500) \nPort n Mode Selection 13\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.27..26> MODE13
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE12  -----------------------------------
+// SVD Line: 6429
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE12
+//    <name> MODE12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000500) \nPort n Mode Selection 12\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.25..24> MODE12
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE11  -----------------------------------
+// SVD Line: 6452
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000500) \nPort n Mode Selection 11\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.23..22> MODE11
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE10  -----------------------------------
+// SVD Line: 6475
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000500) \nPort n Mode Selection 10\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.21..20> MODE10
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE9  ------------------------------------
+// SVD Line: 6498
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000500) \nPort n Mode Selection 9\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.19..18> MODE9
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE8  ------------------------------------
+// SVD Line: 6521
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000500) \nPort n Mode Selection 8\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.17..16> MODE8
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE7  ------------------------------------
+// SVD Line: 6544
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000500) \nPort n Mode Selection 7\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.15..14> MODE7
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE6  ------------------------------------
+// SVD Line: 6567
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000500) \nPort n Mode Selection 6\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.13..12> MODE6
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE5  ------------------------------------
+// SVD Line: 6590
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000500) \nPort n Mode Selection 5\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.11..10> MODE5
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE4  ------------------------------------
+// SVD Line: 6613
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000500) \nPort n Mode Selection 4\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.9..8> MODE4
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE3  ------------------------------------
+// SVD Line: 6636
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000500) \nPort n Mode Selection 3\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.7..6> MODE3
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE2  ------------------------------------
+// SVD Line: 6659
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000500) \nPort n Mode Selection 2\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.5..4> MODE2
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE1  ------------------------------------
+// SVD Line: 6682
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000500) \nPort n Mode Selection 1\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.3..2> MODE1
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_MOD_MODE0  ------------------------------------
+// SVD Line: 6705
+
+//  <item> SFDITEM_FIELD__PF_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000500) \nPort n Mode Selection 0\n0 : Input = Input Mode\n1 : Output = Output Mode\n2 : Alternative = Alternative Function Mode\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_MOD ) </loc>
+//      <o.1..0> MODE0
+//        <0=> 0: Input = Input Mode
+//        <1=> 1: Output = Output Mode
+//        <2=> 2: Alternative = Alternative Function Mode
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PF_MOD  -------------------------------------
+// SVD Line: 6351
+
+//  <rtree> SFDITEM_REG__PF_MOD
+//    <name> MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000500) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PF_MOD >> 0) & 0xFFFFFFFF), ((PF_MOD = (PF_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE15 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE14 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE13 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE12 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PF_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PF_TYP  ---------------------------------
+// SVD Line: 6730
+
+unsigned int PF_TYP __AT (0x30000504);
+
+
+
+// --------------------------------  Field Item: PF_TYP_TYP15  ------------------------------------
+// SVD Line: 6739
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP15
+//    <name> TYP15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000504) \nPort n Output Type Selection 15\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.15..15> TYP15
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_TYP_TYP14  ------------------------------------
+// SVD Line: 6757
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP14
+//    <name> TYP14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000504) \nPort n Output Type Selection 14\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.14..14> TYP14
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_TYP_TYP13  ------------------------------------
+// SVD Line: 6775
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP13
+//    <name> TYP13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000504) \nPort n Output Type Selection 13\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.13..13> TYP13
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_TYP_TYP12  ------------------------------------
+// SVD Line: 6793
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP12
+//    <name> TYP12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000504) \nPort n Output Type Selection 12\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.12..12> TYP12
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_TYP_TYP11  ------------------------------------
+// SVD Line: 6811
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000504) \nPort n Output Type Selection 11\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.11..11> TYP11
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_TYP_TYP10  ------------------------------------
+// SVD Line: 6829
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000504) \nPort n Output Type Selection 10\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.10..10> TYP10
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP9  ------------------------------------
+// SVD Line: 6847
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000504) \nPort n Output Type Selection 9\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.9..9> TYP9
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP8  ------------------------------------
+// SVD Line: 6865
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000504) \nPort n Output Type Selection 8\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.8..8> TYP8
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP7  ------------------------------------
+// SVD Line: 6883
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000504) \nPort n Output Type Selection 7\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.7..7> TYP7
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP6  ------------------------------------
+// SVD Line: 6901
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000504) \nPort n Output Type Selection 6\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.6..6> TYP6
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP5  ------------------------------------
+// SVD Line: 6919
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000504) \nPort n Output Type Selection 5\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.5..5> TYP5
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP4  ------------------------------------
+// SVD Line: 6937
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000504) \nPort n Output Type Selection 4\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.4..4> TYP4
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP3  ------------------------------------
+// SVD Line: 6955
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000504) \nPort n Output Type Selection 3\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.3..3> TYP3
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP2  ------------------------------------
+// SVD Line: 6973
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000504) \nPort n Output Type Selection 2\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.2..2> TYP2
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP1  ------------------------------------
+// SVD Line: 6991
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000504) \nPort n Output Type Selection 1\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.1..1> TYP1
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_TYP_TYP0  ------------------------------------
+// SVD Line: 7009
+
+//  <item> SFDITEM_FIELD__PF_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000504) \nPort n Output Type Selection 0\n0 : PushPull = Push-Pull Output\n1 : OpenDrain = Open-Drain Output </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_TYP ) </loc>
+//      <o.0..0> TYP0
+//        <0=> 0: PushPull = Push-Pull Output
+//        <1=> 1: OpenDrain = Open-Drain Output
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PF_TYP  -------------------------------------
+// SVD Line: 6730
+
+//  <rtree> SFDITEM_REG__PF_TYP
+//    <name> TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000504) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PF_TYP >> 0) & 0xFFFFFFFF), ((PF_TYP = (PF_TYP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP15 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP14 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP13 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP12 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PF_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PF_AFSR1  --------------------------------
+// SVD Line: 7029
+
+unsigned int PF_AFSR1 __AT (0x30000508);
+
+
+
+// -------------------------------  Field Item: PF_AFSR1_AFSR7  -----------------------------------
+// SVD Line: 7038
+
+//  <item> SFDITEM_FIELD__PF_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000508) \nPort n Alternative Function Selection 7\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR1 ) </loc>
+//      <o.31..28> AFSR7
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR1_AFSR6  -----------------------------------
+// SVD Line: 7071
+
+//  <item> SFDITEM_FIELD__PF_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000508) \nPort n Alternative Function Selection 6\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR1 ) </loc>
+//      <o.27..24> AFSR6
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR1_AFSR5  -----------------------------------
+// SVD Line: 7104
+
+//  <item> SFDITEM_FIELD__PF_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000508) \nPort n Alternative Function Selection 5\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR1 ) </loc>
+//      <o.23..20> AFSR5
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR1_AFSR4  -----------------------------------
+// SVD Line: 7137
+
+//  <item> SFDITEM_FIELD__PF_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000508) \nPort n Alternative Function Selection 4\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR1 ) </loc>
+//      <o.19..16> AFSR4
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR1_AFSR3  -----------------------------------
+// SVD Line: 7170
+
+//  <item> SFDITEM_FIELD__PF_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000508) \nPort n Alternative Function Selection 3\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR1 ) </loc>
+//      <o.15..12> AFSR3
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR1_AFSR2  -----------------------------------
+// SVD Line: 7203
+
+//  <item> SFDITEM_FIELD__PF_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000508) \nPort n Alternative Function Selection 2\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR1 ) </loc>
+//      <o.11..8> AFSR2
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR1_AFSR1  -----------------------------------
+// SVD Line: 7236
+
+//  <item> SFDITEM_FIELD__PF_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000508) \nPort n Alternative Function Selection 1\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR1 ) </loc>
+//      <o.7..4> AFSR1
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR1_AFSR0  -----------------------------------
+// SVD Line: 7269
+
+//  <item> SFDITEM_FIELD__PF_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000508) \nPort n Alternative Function Selection 0\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR1 ) </loc>
+//      <o.3..0> AFSR0
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PF_AFSR1  ------------------------------------
+// SVD Line: 7029
+
+//  <rtree> SFDITEM_REG__PF_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000508) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PF_AFSR1 >> 0) & 0xFFFFFFFF), ((PF_AFSR1 = (PF_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PF_AFSR2  --------------------------------
+// SVD Line: 7304
+
+unsigned int PF_AFSR2 __AT (0x3000050C);
+
+
+
+// -------------------------------  Field Item: PF_AFSR2_AFSR15  ----------------------------------
+// SVD Line: 7313
+
+//  <item> SFDITEM_FIELD__PF_AFSR2_AFSR15
+//    <name> AFSR15 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x3000050C) \nPort n Alternative Function Selection 15\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR2 ) </loc>
+//      <o.31..28> AFSR15
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR2_AFSR14  ----------------------------------
+// SVD Line: 7346
+
+//  <item> SFDITEM_FIELD__PF_AFSR2_AFSR14
+//    <name> AFSR14 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x3000050C) \nPort n Alternative Function Selection 14\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR2 ) </loc>
+//      <o.27..24> AFSR14
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR2_AFSR13  ----------------------------------
+// SVD Line: 7379
+
+//  <item> SFDITEM_FIELD__PF_AFSR2_AFSR13
+//    <name> AFSR13 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x3000050C) \nPort n Alternative Function Selection 13\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR2 ) </loc>
+//      <o.23..20> AFSR13
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR2_AFSR12  ----------------------------------
+// SVD Line: 7412
+
+//  <item> SFDITEM_FIELD__PF_AFSR2_AFSR12
+//    <name> AFSR12 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x3000050C) \nPort n Alternative Function Selection 12\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR2 ) </loc>
+//      <o.19..16> AFSR12
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR2_AFSR11  ----------------------------------
+// SVD Line: 7445
+
+//  <item> SFDITEM_FIELD__PF_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000050C) \nPort n Alternative Function Selection 11\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR2 ) </loc>
+//      <o.15..12> AFSR11
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR2_AFSR10  ----------------------------------
+// SVD Line: 7478
+
+//  <item> SFDITEM_FIELD__PF_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000050C) \nPort n Alternative Function Selection 10\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR2 ) </loc>
+//      <o.11..8> AFSR10
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR2_AFSR9  -----------------------------------
+// SVD Line: 7511
+
+//  <item> SFDITEM_FIELD__PF_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000050C) \nPort n Alternative Function Selection 9\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR2 ) </loc>
+//      <o.7..4> AFSR9
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_AFSR2_AFSR8  -----------------------------------
+// SVD Line: 7544
+
+//  <item> SFDITEM_FIELD__PF_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000050C) \nPort n Alternative Function Selection 8\n0 : AF0 = Alternative Function 0 (AF0)\n1 : AF1 = Alternative Function 1 (AF1)\n2 : AF2 = Alternative Function 2 (AF2)\n3 : AF3 = Alternative Function 3 (AF3)\n4 : AF4 = Alternative Function 4 (AF4)\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_AFSR2 ) </loc>
+//      <o.3..0> AFSR8
+//        <0=> 0: AF0 = Alternative Function 0 (AF0)
+//        <1=> 1: AF1 = Alternative Function 1 (AF1)
+//        <2=> 2: AF2 = Alternative Function 2 (AF2)
+//        <3=> 3: AF3 = Alternative Function 3 (AF3)
+//        <4=> 4: AF4 = Alternative Function 4 (AF4)
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PF_AFSR2  ------------------------------------
+// SVD Line: 7304
+
+//  <rtree> SFDITEM_REG__PF_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000050C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PF_AFSR2 >> 0) & 0xFFFFFFFF), ((PF_AFSR2 = (PF_AFSR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_AFSR2_AFSR15 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR2_AFSR14 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR2_AFSR13 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR2_AFSR12 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PF_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PF_PUPD  ---------------------------------
+// SVD Line: 7579
+
+unsigned int PF_PUPD __AT (0x30000510);
+
+
+
+// -------------------------------  Field Item: PF_PUPD_PUPD15  -----------------------------------
+// SVD Line: 7588
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD15
+//    <name> PUPD15 </name>
+//    <rw> 
+//    <i> [Bits 31..30] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 15\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.31..30> PUPD15
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PUPD_PUPD14  -----------------------------------
+// SVD Line: 7611
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD14
+//    <name> PUPD14 </name>
+//    <rw> 
+//    <i> [Bits 29..28] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 14\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.29..28> PUPD14
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PUPD_PUPD13  -----------------------------------
+// SVD Line: 7634
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD13
+//    <name> PUPD13 </name>
+//    <rw> 
+//    <i> [Bits 27..26] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 13\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.27..26> PUPD13
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PUPD_PUPD12  -----------------------------------
+// SVD Line: 7657
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD12
+//    <name> PUPD12 </name>
+//    <rw> 
+//    <i> [Bits 25..24] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 12\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.25..24> PUPD12
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PUPD_PUPD11  -----------------------------------
+// SVD Line: 7680
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 11\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.23..22> PUPD11
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PUPD_PUPD10  -----------------------------------
+// SVD Line: 7703
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 10\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.21..20> PUPD10
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD9  -----------------------------------
+// SVD Line: 7726
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 9\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.19..18> PUPD9
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD8  -----------------------------------
+// SVD Line: 7749
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 8\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.17..16> PUPD8
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD7  -----------------------------------
+// SVD Line: 7772
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 7\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.15..14> PUPD7
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD6  -----------------------------------
+// SVD Line: 7795
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 6\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.13..12> PUPD6
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD5  -----------------------------------
+// SVD Line: 7818
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 5\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.11..10> PUPD5
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD4  -----------------------------------
+// SVD Line: 7841
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 4\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.9..8> PUPD4
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD3  -----------------------------------
+// SVD Line: 7864
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 3\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.7..6> PUPD3
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD2  -----------------------------------
+// SVD Line: 7887
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 2\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.5..4> PUPD2
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD1  -----------------------------------
+// SVD Line: 7910
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 1\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.3..2> PUPD1
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_PUPD_PUPD0  -----------------------------------
+// SVD Line: 7933
+
+//  <item> SFDITEM_FIELD__PF_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000510) \nPort n Pull-Up/Down Resistor Selection 0\n0 : Disable = Disable pull-up/down resistor.\n1 : EnablePU = Enable pull-up resistor.\n2 : EnablePD = Enable pull-down resistor.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_PUPD ) </loc>
+//      <o.1..0> PUPD0
+//        <0=> 0: Disable = Disable pull-up/down resistor.
+//        <1=> 1: EnablePU = Enable pull-up resistor.
+//        <2=> 2: EnablePD = Enable pull-down resistor.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PF_PUPD  ------------------------------------
+// SVD Line: 7579
+
+//  <rtree> SFDITEM_REG__PF_PUPD
+//    <name> PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PF_PUPD >> 0) & 0xFFFFFFFF), ((PF_PUPD = (PF_PUPD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD15 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD14 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD13 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD12 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PF_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PF_INDR  ---------------------------------
+// SVD Line: 7958
+
+unsigned int PF_INDR __AT (0x30000514);
+
+
+
+// -------------------------------  Field Item: PF_INDR_INDR15  -----------------------------------
+// SVD Line: 7967
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR15
+//    <name> INDR15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x30000514) Port n Input Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.15..15> INDR15
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_INDR_INDR14  -----------------------------------
+// SVD Line: 7973
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR14
+//    <name> INDR14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x30000514) Port n Input Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.14..14> INDR14
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_INDR_INDR13  -----------------------------------
+// SVD Line: 7979
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR13
+//    <name> INDR13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x30000514) Port n Input Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.13..13> INDR13
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_INDR_INDR12  -----------------------------------
+// SVD Line: 7985
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR12
+//    <name> INDR12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x30000514) Port n Input Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.12..12> INDR12
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_INDR_INDR11  -----------------------------------
+// SVD Line: 7991
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000514) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_INDR_INDR10  -----------------------------------
+// SVD Line: 7997
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000514) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR9  -----------------------------------
+// SVD Line: 8003
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000514) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR8  -----------------------------------
+// SVD Line: 8009
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000514) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR7  -----------------------------------
+// SVD Line: 8015
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000514) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR6  -----------------------------------
+// SVD Line: 8021
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000514) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR5  -----------------------------------
+// SVD Line: 8027
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000514) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR4  -----------------------------------
+// SVD Line: 8033
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000514) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR3  -----------------------------------
+// SVD Line: 8039
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000514) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR2  -----------------------------------
+// SVD Line: 8045
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000514) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR1  -----------------------------------
+// SVD Line: 8051
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000514) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_INDR_INDR0  -----------------------------------
+// SVD Line: 8057
+
+//  <item> SFDITEM_FIELD__PF_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000514) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PF_INDR  ------------------------------------
+// SVD Line: 7958
+
+//  <rtree> SFDITEM_REG__PF_INDR
+//    <name> INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000514) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PF_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR15 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR14 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR13 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR12 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PF_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PF_OUTDR  --------------------------------
+// SVD Line: 8065
+
+unsigned int PF_OUTDR __AT (0x30000518);
+
+
+
+// ------------------------------  Field Item: PF_OUTDR_OUTDR15  ----------------------------------
+// SVD Line: 8074
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR15
+//    <name> OUTDR15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000518) Port n Output Data 15 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.15..15> OUTDR15
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_OUTDR_OUTDR14  ----------------------------------
+// SVD Line: 8080
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR14
+//    <name> OUTDR14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000518) Port n Output Data 14 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.14..14> OUTDR14
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_OUTDR_OUTDR13  ----------------------------------
+// SVD Line: 8086
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR13
+//    <name> OUTDR13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000518) Port n Output Data 13 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.13..13> OUTDR13
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_OUTDR_OUTDR12  ----------------------------------
+// SVD Line: 8092
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR12
+//    <name> OUTDR12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000518) Port n Output Data 12 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.12..12> OUTDR12
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_OUTDR_OUTDR11  ----------------------------------
+// SVD Line: 8098
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000518) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_OUTDR_OUTDR10  ----------------------------------
+// SVD Line: 8104
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000518) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR9  ----------------------------------
+// SVD Line: 8110
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000518) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR8  ----------------------------------
+// SVD Line: 8116
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000518) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR7  ----------------------------------
+// SVD Line: 8122
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000518) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR6  ----------------------------------
+// SVD Line: 8128
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000518) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR5  ----------------------------------
+// SVD Line: 8134
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000518) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR4  ----------------------------------
+// SVD Line: 8140
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000518) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR3  ----------------------------------
+// SVD Line: 8146
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000518) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR2  ----------------------------------
+// SVD Line: 8152
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000518) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR1  ----------------------------------
+// SVD Line: 8158
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000518) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_OUTDR_OUTDR0  ----------------------------------
+// SVD Line: 8164
+
+//  <item> SFDITEM_FIELD__PF_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000518) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PF_OUTDR  ------------------------------------
+// SVD Line: 8065
+
+//  <rtree> SFDITEM_REG__PF_OUTDR
+//    <name> OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000518) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PF_OUTDR >> 0) & 0xFFFFFFFF), ((PF_OUTDR = (PF_OUTDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR15 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR14 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR13 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR12 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PF_BSR  ---------------------------------
+// SVD Line: 8172
+
+unsigned int PF_BSR __AT (0x3000051C);
+
+
+
+// --------------------------------  Field Item: PF_BSR_BSR15  ------------------------------------
+// SVD Line: 8181
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR15
+//    <name> BSR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x3000051C) \nPort n Output Bit Set 15\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.15..15> BSR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BSR_BSR14  ------------------------------------
+// SVD Line: 8199
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR14
+//    <name> BSR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x3000051C) \nPort n Output Bit Set 14\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.14..14> BSR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BSR_BSR13  ------------------------------------
+// SVD Line: 8217
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR13
+//    <name> BSR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x3000051C) \nPort n Output Bit Set 13\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.13..13> BSR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BSR_BSR12  ------------------------------------
+// SVD Line: 8235
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR12
+//    <name> BSR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x3000051C) \nPort n Output Bit Set 12\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.12..12> BSR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BSR_BSR11  ------------------------------------
+// SVD Line: 8253
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000051C) \nPort n Output Bit Set 11\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.11..11> BSR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BSR_BSR10  ------------------------------------
+// SVD Line: 8271
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000051C) \nPort n Output Bit Set 10\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.10..10> BSR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR9  ------------------------------------
+// SVD Line: 8289
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000051C) \nPort n Output Bit Set 9\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.9..9> BSR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR8  ------------------------------------
+// SVD Line: 8307
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000051C) \nPort n Output Bit Set 8\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.8..8> BSR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR7  ------------------------------------
+// SVD Line: 8325
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000051C) \nPort n Output Bit Set 7\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.7..7> BSR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR6  ------------------------------------
+// SVD Line: 8343
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000051C) \nPort n Output Bit Set 6\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.6..6> BSR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR5  ------------------------------------
+// SVD Line: 8361
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000051C) \nPort n Output Bit Set 5\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.5..5> BSR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR4  ------------------------------------
+// SVD Line: 8379
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000051C) \nPort n Output Bit Set 4\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.4..4> BSR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR3  ------------------------------------
+// SVD Line: 8397
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000051C) \nPort n Output Bit Set 3\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.3..3> BSR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR2  ------------------------------------
+// SVD Line: 8415
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000051C) \nPort n Output Bit Set 2\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.2..2> BSR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR1  ------------------------------------
+// SVD Line: 8433
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000051C) \nPort n Output Bit Set 1\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.1..1> BSR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BSR_BSR0  ------------------------------------
+// SVD Line: 8451
+
+//  <item> SFDITEM_FIELD__PF_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000051C) \nPort n Output Bit Set 0\n0 : NoEffect = No effect.\n1 : Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BSR ) </loc>
+//      <o.0..0> BSR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Set = Set the corresponding OUTDRx bit (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PF_BSR  -------------------------------------
+// SVD Line: 8172
+
+//  <rtree> SFDITEM_REG__PF_BSR
+//    <name> BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000051C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PF_BSR >> 0) & 0xFFFFFFFF), ((PF_BSR = (PF_BSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR15 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR14 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR13 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR12 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PF_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: PF_BCR  ---------------------------------
+// SVD Line: 8471
+
+unsigned int PF_BCR __AT (0x30000520);
+
+
+
+// --------------------------------  Field Item: PF_BCR_BCR15  ------------------------------------
+// SVD Line: 8480
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR15
+//    <name> BCR15 </name>
+//    <w> 
+//    <i> [Bit 15] WO (@ 0x30000520) \nPort n Output Bit Clear 15\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.15..15> BCR15
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BCR_BCR14  ------------------------------------
+// SVD Line: 8498
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR14
+//    <name> BCR14 </name>
+//    <w> 
+//    <i> [Bit 14] WO (@ 0x30000520) \nPort n Output Bit Clear 14\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.14..14> BCR14
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BCR_BCR13  ------------------------------------
+// SVD Line: 8516
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR13
+//    <name> BCR13 </name>
+//    <w> 
+//    <i> [Bit 13] WO (@ 0x30000520) \nPort n Output Bit Clear 13\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.13..13> BCR13
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BCR_BCR12  ------------------------------------
+// SVD Line: 8534
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR12
+//    <name> BCR12 </name>
+//    <w> 
+//    <i> [Bit 12] WO (@ 0x30000520) \nPort n Output Bit Clear 12\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.12..12> BCR12
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BCR_BCR11  ------------------------------------
+// SVD Line: 8552
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000520) \nPort n Output Bit Clear 11\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.11..11> BCR11
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_BCR_BCR10  ------------------------------------
+// SVD Line: 8570
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000520) \nPort n Output Bit Clear 10\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.10..10> BCR10
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR9  ------------------------------------
+// SVD Line: 8588
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000520) \nPort n Output Bit Clear 9\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.9..9> BCR9
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR8  ------------------------------------
+// SVD Line: 8606
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000520) \nPort n Output Bit Clear 8\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.8..8> BCR8
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR7  ------------------------------------
+// SVD Line: 8624
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000520) \nPort n Output Bit Clear 7\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.7..7> BCR7
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR6  ------------------------------------
+// SVD Line: 8642
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000520) \nPort n Output Bit Clear 6\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.6..6> BCR6
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR5  ------------------------------------
+// SVD Line: 8660
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000520) \nPort n Output Bit Clear 5\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.5..5> BCR5
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR4  ------------------------------------
+// SVD Line: 8678
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000520) \nPort n Output Bit Clear 4\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.4..4> BCR4
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR3  ------------------------------------
+// SVD Line: 8696
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000520) \nPort n Output Bit Clear 3\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.3..3> BCR3
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR2  ------------------------------------
+// SVD Line: 8714
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000520) \nPort n Output Bit Clear 2\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.2..2> BCR2
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR1  ------------------------------------
+// SVD Line: 8732
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000520) \nPort n Output Bit Clear 1\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.1..1> BCR1
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: PF_BCR_BCR0  ------------------------------------
+// SVD Line: 8750
+
+//  <item> SFDITEM_FIELD__PF_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000520) \nPort n Output Bit Clear 0\n0 : NoEffect = No effect.\n1 : Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_BCR ) </loc>
+//      <o.0..0> BCR0
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PF_BCR  -------------------------------------
+// SVD Line: 8471
+
+//  <rtree> SFDITEM_REG__PF_BCR
+//    <name> BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000520) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PF_BCR >> 0) & 0xFFFFFFFF), ((PF_BCR = (PF_BCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR15 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR14 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR13 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR12 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PF_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PF_OUTDMSK  -------------------------------
+// SVD Line: 8770
+
+unsigned int PF_OUTDMSK __AT (0x30000524);
+
+
+
+// ----------------------------  Field Item: PF_OUTDMSK_OUTDMSK15  --------------------------------
+// SVD Line: 8779
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK15
+//    <name> OUTDMSK15 </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x30000524) \nPort n Output Data Mask 15\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.15..15> OUTDMSK15
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PF_OUTDMSK_OUTDMSK14  --------------------------------
+// SVD Line: 8797
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK14
+//    <name> OUTDMSK14 </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x30000524) \nPort n Output Data Mask 14\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.14..14> OUTDMSK14
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PF_OUTDMSK_OUTDMSK13  --------------------------------
+// SVD Line: 8815
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK13
+//    <name> OUTDMSK13 </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x30000524) \nPort n Output Data Mask 13\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.13..13> OUTDMSK13
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PF_OUTDMSK_OUTDMSK12  --------------------------------
+// SVD Line: 8833
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK12
+//    <name> OUTDMSK12 </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x30000524) \nPort n Output Data Mask 12\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.12..12> OUTDMSK12
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PF_OUTDMSK_OUTDMSK11  --------------------------------
+// SVD Line: 8851
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000524) \nPort n Output Data Mask 11\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: PF_OUTDMSK_OUTDMSK10  --------------------------------
+// SVD Line: 8869
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000524) \nPort n Output Data Mask 10\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK9  --------------------------------
+// SVD Line: 8887
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000524) \nPort n Output Data Mask 9\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK8  --------------------------------
+// SVD Line: 8905
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000524) \nPort n Output Data Mask 8\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK7  --------------------------------
+// SVD Line: 8923
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000524) \nPort n Output Data Mask 7\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK6  --------------------------------
+// SVD Line: 8941
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000524) \nPort n Output Data Mask 6\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK5  --------------------------------
+// SVD Line: 8959
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000524) \nPort n Output Data Mask 5\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK4  --------------------------------
+// SVD Line: 8977
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000524) \nPort n Output Data Mask 4\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK3  --------------------------------
+// SVD Line: 8995
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000524) \nPort n Output Data Mask 3\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK2  --------------------------------
+// SVD Line: 9013
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000524) \nPort n Output Data Mask 2\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK1  --------------------------------
+// SVD Line: 9031
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000524) \nPort n Output Data Mask 1\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_OUTDMSK_OUTDMSK0  --------------------------------
+// SVD Line: 9049
+
+//  <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000524) \nPort n Output Data Mask 0\n0 : Unmask = Unmask. The corresponding OUTDRx bit can be changed.\n1 : Mask = Mask. The corresponding OUTDRx bit is protected. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//        <0=> 0: Unmask = Unmask. The corresponding OUTDRx bit can be changed.
+//        <1=> 1: Mask = Mask. The corresponding OUTDRx bit is protected.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PF_OUTDMSK  -----------------------------------
+// SVD Line: 8770
+
+//  <rtree> SFDITEM_REG__PF_OUTDMSK
+//    <name> OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000524) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PF_OUTDMSK >> 0) & 0xFFFFFFFF), ((PF_OUTDMSK = (PF_OUTDMSK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK15 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK14 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK13 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK12 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PF_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: PF_DBCR  ---------------------------------
+// SVD Line: 9069
+
+unsigned int PF_DBCR __AT (0x30000528);
+
+
+
+// --------------------------------  Field Item: PF_DBCR_DBCLK  -----------------------------------
+// SVD Line: 9078
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBCLK
+//    <name> DBCLK </name>
+//    <rw> 
+//    <i> [Bits 18..16] RW (@ 0x30000528) \nPort n Debounce Filter Sampling Clock Selection\n0 : HCLK1 = HCLK/1\n1 : HCLK4 = HCLK/4\n2 : HCLK16 = HCLK/16\n3 : HCLK64 = HCLK/64\n4 : HCLK256 = HCLK/256\n5 : HCLK1024 = HCLK/1024\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.18..16> DBCLK
+//        <0=> 0: HCLK1 = HCLK/1
+//        <1=> 1: HCLK4 = HCLK/4
+//        <2=> 2: HCLK16 = HCLK/16
+//        <3=> 3: HCLK64 = HCLK/64
+//        <4=> 4: HCLK256 = HCLK/256
+//        <5=> 5: HCLK1024 = HCLK/1024
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_DBCR_DBEN11  -----------------------------------
+// SVD Line: 9116
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN11
+//    <name> DBEN11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000528) \nPort n Debounce Enable 11\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.11..11> DBEN11
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_DBCR_DBEN10  -----------------------------------
+// SVD Line: 9134
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN10
+//    <name> DBEN10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000528) \nPort n Debounce Enable 10\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.10..10> DBEN10
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN9  -----------------------------------
+// SVD Line: 9152
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN9
+//    <name> DBEN9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000528) \nPort n Debounce Enable 9\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.9..9> DBEN9
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN8  -----------------------------------
+// SVD Line: 9170
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN8
+//    <name> DBEN8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000528) \nPort n Debounce Enable 8\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.8..8> DBEN8
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN7  -----------------------------------
+// SVD Line: 9188
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN7
+//    <name> DBEN7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000528) \nPort n Debounce Enable 7\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.7..7> DBEN7
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN6  -----------------------------------
+// SVD Line: 9206
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN6
+//    <name> DBEN6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000528) \nPort n Debounce Enable 6\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.6..6> DBEN6
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN5  -----------------------------------
+// SVD Line: 9224
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN5
+//    <name> DBEN5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000528) \nPort n Debounce Enable 5\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.5..5> DBEN5
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN4  -----------------------------------
+// SVD Line: 9242
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN4
+//    <name> DBEN4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000528) \nPort n Debounce Enable 4\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.4..4> DBEN4
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN3  -----------------------------------
+// SVD Line: 9260
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN3
+//    <name> DBEN3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000528) \nPort n Debounce Enable 3\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.3..3> DBEN3
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN2  -----------------------------------
+// SVD Line: 9278
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN2
+//    <name> DBEN2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000528) \nPort n Debounce Enable 2\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.2..2> DBEN2
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN1  -----------------------------------
+// SVD Line: 9296
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN1
+//    <name> DBEN1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000528) \nPort n Debounce Enable 1\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.1..1> DBEN1
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: PF_DBCR_DBEN0  -----------------------------------
+// SVD Line: 9314
+
+//  <item> SFDITEM_FIELD__PF_DBCR_DBEN0
+//    <name> DBEN0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000528) \nPort n Debounce Enable 0\n0 : Disable = Disable debounce filter.\n1 : Enable = Enable debounce filter. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) PF_DBCR ) </loc>
+//      <o.0..0> DBEN0
+//        <0=> 0: Disable = Disable debounce filter.
+//        <1=> 1: Enable = Enable debounce filter.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: PF_DBCR  ------------------------------------
+// SVD Line: 9069
+
+//  <rtree> SFDITEM_REG__PF_DBCR
+//    <name> DBCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000528) Port n Debounce Control Register </i>
+//    <loc> ( (unsigned int)((PF_DBCR >> 0) & 0xFFFFFFFF), ((PF_DBCR = (PF_DBCR & ~(0x70FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBCLK </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN11 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN10 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN9 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN8 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN7 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN6 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN5 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN4 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN3 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN2 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN1 </item>
+//    <item> SFDITEM_FIELD__PF_DBCR_DBEN0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PF_PF_MOD  --------------------------------
+// SVD Line: 13712
+
+unsigned int PF_PF_MOD __AT (0x30000500);
+
+
+
+// ------------------------------  Field Item: PF_PF_MOD_MODE11  ----------------------------------
+// SVD Line: 13722
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE11
+//    <name> MODE11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000500) Port n Mode Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 22) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_MOD_MODE10  ----------------------------------
+// SVD Line: 13728
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE10
+//    <name> MODE10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000500) Port n Mode Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 20) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE9  ----------------------------------
+// SVD Line: 13734
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE9
+//    <name> MODE9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000500) Port n Mode Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 18) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE8  ----------------------------------
+// SVD Line: 13740
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE8
+//    <name> MODE8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000500) Port n Mode Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 16) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE7  ----------------------------------
+// SVD Line: 13746
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE7
+//    <name> MODE7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000500) Port n Mode Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 14) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE6  ----------------------------------
+// SVD Line: 13752
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE6
+//    <name> MODE6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000500) Port n Mode Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 12) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE5  ----------------------------------
+// SVD Line: 13758
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE5
+//    <name> MODE5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000500) Port n Mode Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 10) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE4  ----------------------------------
+// SVD Line: 13764
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE4
+//    <name> MODE4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000500) Port n Mode Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 8) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE3  ----------------------------------
+// SVD Line: 13770
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE3
+//    <name> MODE3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000500) Port n Mode Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 6) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE2  ----------------------------------
+// SVD Line: 13776
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE2
+//    <name> MODE2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000500) Port n Mode Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 4) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE1  ----------------------------------
+// SVD Line: 13782
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE1
+//    <name> MODE1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000500) Port n Mode Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 2) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_MOD_MODE0  ----------------------------------
+// SVD Line: 13788
+
+//  <item> SFDITEM_FIELD__PF_PF_MOD_MODE0
+//    <name> MODE0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000500) Port n Mode Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_MOD >> 0) & 0x3), ((PF_PF_MOD = (PF_PF_MOD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PF_PF_MOD  -----------------------------------
+// SVD Line: 13712
+
+//  <rtree> SFDITEM_REG__PF_PF_MOD
+//    <name> PF_MOD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000500) Port n Mode Register </i>
+//    <loc> ( (unsigned int)((PF_PF_MOD >> 0) & 0xFFFFFFFF), ((PF_PF_MOD = (PF_PF_MOD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE8 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_MOD_MODE0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PF_PF_TYP  --------------------------------
+// SVD Line: 13796
+
+unsigned int PF_PF_TYP __AT (0x30000504);
+
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP11  ----------------------------------
+// SVD Line: 13806
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP11
+//    <name> TYP11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000504) Port n Output Type Selection 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.11..11> TYP11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP10  ----------------------------------
+// SVD Line: 13812
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP10
+//    <name> TYP10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000504) Port n Output Type Selection 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.10..10> TYP10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP9  -----------------------------------
+// SVD Line: 13818
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP9
+//    <name> TYP9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000504) Port n Output Type Selection 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.9..9> TYP9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP8  -----------------------------------
+// SVD Line: 13824
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP8
+//    <name> TYP8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000504) Port n Output Type Selection 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.8..8> TYP8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP7  -----------------------------------
+// SVD Line: 13830
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP7
+//    <name> TYP7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000504) Port n Output Type Selection 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.7..7> TYP7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP6  -----------------------------------
+// SVD Line: 13836
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP6
+//    <name> TYP6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000504) Port n Output Type Selection 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.6..6> TYP6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP5  -----------------------------------
+// SVD Line: 13842
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP5
+//    <name> TYP5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000504) Port n Output Type Selection 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.5..5> TYP5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP4  -----------------------------------
+// SVD Line: 13848
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP4
+//    <name> TYP4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000504) Port n Output Type Selection 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.4..4> TYP4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP3  -----------------------------------
+// SVD Line: 13854
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP3
+//    <name> TYP3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000504) Port n Output Type Selection 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.3..3> TYP3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP2  -----------------------------------
+// SVD Line: 13860
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP2
+//    <name> TYP2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000504) Port n Output Type Selection 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.2..2> TYP2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP1  -----------------------------------
+// SVD Line: 13866
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP1
+//    <name> TYP1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000504) Port n Output Type Selection 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.1..1> TYP1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_TYP_TYP0  -----------------------------------
+// SVD Line: 13872
+
+//  <item> SFDITEM_FIELD__PF_PF_TYP_TYP0
+//    <name> TYP0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000504) Port n Output Type Selection 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_TYP ) </loc>
+//      <o.0..0> TYP0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PF_PF_TYP  -----------------------------------
+// SVD Line: 13796
+
+//  <rtree> SFDITEM_REG__PF_PF_TYP
+//    <name> PF_TYP </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000504) Port n Output Type Selection Register </i>
+//    <loc> ( (unsigned int)((PF_PF_TYP >> 0) & 0xFFFFFFFF), ((PF_PF_TYP = (PF_PF_TYP & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP8 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_TYP_TYP0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PF_PF_AFSR1  -------------------------------
+// SVD Line: 13880
+
+unsigned int PF_PF_AFSR1 __AT (0x30000508);
+
+
+
+// ------------------------------  Field Item: PF_PF_AFSR1_AFSR7  ---------------------------------
+// SVD Line: 13890
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR7
+//    <name> AFSR7 </name>
+//    <rw> 
+//    <i> [Bits 31..28] RW (@ 0x30000508) Port n Alternative Function Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR1 >> 28) & 0xF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR1_AFSR6  ---------------------------------
+// SVD Line: 13896
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR6
+//    <name> AFSR6 </name>
+//    <rw> 
+//    <i> [Bits 27..24] RW (@ 0x30000508) Port n Alternative Function Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR1 >> 24) & 0xF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR1_AFSR5  ---------------------------------
+// SVD Line: 13902
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR5
+//    <name> AFSR5 </name>
+//    <rw> 
+//    <i> [Bits 23..20] RW (@ 0x30000508) Port n Alternative Function Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR1 >> 20) & 0xF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR1_AFSR4  ---------------------------------
+// SVD Line: 13908
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR4
+//    <name> AFSR4 </name>
+//    <rw> 
+//    <i> [Bits 19..16] RW (@ 0x30000508) Port n Alternative Function Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR1 >> 16) & 0xF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR1_AFSR3  ---------------------------------
+// SVD Line: 13914
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR3
+//    <name> AFSR3 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x30000508) Port n Alternative Function Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR1 >> 12) & 0xF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR1_AFSR2  ---------------------------------
+// SVD Line: 13920
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR2
+//    <name> AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x30000508) Port n Alternative Function Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR1 >> 8) & 0xF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR1_AFSR1  ---------------------------------
+// SVD Line: 13926
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR1
+//    <name> AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x30000508) Port n Alternative Function Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR1 >> 4) & 0xF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR1_AFSR0  ---------------------------------
+// SVD Line: 13932
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR0
+//    <name> AFSR0 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x30000508) Port n Alternative Function Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR1 >> 0) & 0xF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PF_PF_AFSR1  ----------------------------------
+// SVD Line: 13880
+
+//  <rtree> SFDITEM_REG__PF_PF_AFSR1
+//    <name> PF_AFSR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000508) Port n Alternative Function Selection Register 1 </i>
+//    <loc> ( (unsigned int)((PF_PF_AFSR1 >> 0) & 0xFFFFFFFF), ((PF_PF_AFSR1 = (PF_PF_AFSR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR1_AFSR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PF_PF_AFSR2  -------------------------------
+// SVD Line: 13940
+
+unsigned int PF_PF_AFSR2 __AT (0x3000050C);
+
+
+
+// -----------------------------  Field Item: PF_PF_AFSR2_AFSR11  ---------------------------------
+// SVD Line: 13950
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR2_AFSR11
+//    <name> AFSR11 </name>
+//    <rw> 
+//    <i> [Bits 15..12] RW (@ 0x3000050C) Port n Alternative Function Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR2 >> 12) & 0xF), ((PF_PF_AFSR2 = (PF_PF_AFSR2 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_AFSR2_AFSR10  ---------------------------------
+// SVD Line: 13956
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR2_AFSR10
+//    <name> AFSR10 </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x3000050C) Port n Alternative Function Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR2 >> 8) & 0xF), ((PF_PF_AFSR2 = (PF_PF_AFSR2 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR2_AFSR9  ---------------------------------
+// SVD Line: 13962
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR2_AFSR9
+//    <name> AFSR9 </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x3000050C) Port n Alternative Function Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR2 >> 4) & 0xF), ((PF_PF_AFSR2 = (PF_PF_AFSR2 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_AFSR2_AFSR8  ---------------------------------
+// SVD Line: 13968
+
+//  <item> SFDITEM_FIELD__PF_PF_AFSR2_AFSR8
+//    <name> AFSR8 </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x3000050C) Port n Alternative Function Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_AFSR2 >> 0) & 0xF), ((PF_PF_AFSR2 = (PF_PF_AFSR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PF_PF_AFSR2  ----------------------------------
+// SVD Line: 13940
+
+//  <rtree> SFDITEM_REG__PF_PF_AFSR2
+//    <name> PF_AFSR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000050C) Port n Alternative Function Selection Register 2 </i>
+//    <loc> ( (unsigned int)((PF_PF_AFSR2 >> 0) & 0xFFFFFFFF), ((PF_PF_AFSR2 = (PF_PF_AFSR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR2_AFSR11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR2_AFSR10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR2_AFSR9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_AFSR2_AFSR8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PF_PF_PUPD  -------------------------------
+// SVD Line: 13976
+
+unsigned int PF_PF_PUPD __AT (0x30000510);
+
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD11  ---------------------------------
+// SVD Line: 13986
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD11
+//    <name> PUPD11 </name>
+//    <rw> 
+//    <i> [Bits 23..22] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 22) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD10  ---------------------------------
+// SVD Line: 13992
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD10
+//    <name> PUPD10 </name>
+//    <rw> 
+//    <i> [Bits 21..20] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 20) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD9  ----------------------------------
+// SVD Line: 13998
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD9
+//    <name> PUPD9 </name>
+//    <rw> 
+//    <i> [Bits 19..18] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 18) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD8  ----------------------------------
+// SVD Line: 14004
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD8
+//    <name> PUPD8 </name>
+//    <rw> 
+//    <i> [Bits 17..16] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 16) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD7  ----------------------------------
+// SVD Line: 14010
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD7
+//    <name> PUPD7 </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 14) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD6  ----------------------------------
+// SVD Line: 14016
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD6
+//    <name> PUPD6 </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 12) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD5  ----------------------------------
+// SVD Line: 14022
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD5
+//    <name> PUPD5 </name>
+//    <rw> 
+//    <i> [Bits 11..10] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 10) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD4  ----------------------------------
+// SVD Line: 14028
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD4
+//    <name> PUPD4 </name>
+//    <rw> 
+//    <i> [Bits 9..8] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 8) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD3  ----------------------------------
+// SVD Line: 14034
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD3
+//    <name> PUPD3 </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 6) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD2  ----------------------------------
+// SVD Line: 14040
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD2
+//    <name> PUPD2 </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 4) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD1  ----------------------------------
+// SVD Line: 14046
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD1
+//    <name> PUPD1 </name>
+//    <rw> 
+//    <i> [Bits 3..2] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 2) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_PUPD_PUPD0  ----------------------------------
+// SVD Line: 14052
+
+//  <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD0
+//    <name> PUPD0 </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((PF_PF_PUPD >> 0) & 0x3), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PF_PF_PUPD  -----------------------------------
+// SVD Line: 13976
+
+//  <rtree> SFDITEM_REG__PF_PF_PUPD
+//    <name> PF_PUPD </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000510) Port n Pull-Up/Down Resistor Selection Register </i>
+//    <loc> ( (unsigned int)((PF_PF_PUPD >> 0) & 0xFFFFFFFF), ((PF_PF_PUPD = (PF_PF_PUPD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD8 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_PUPD_PUPD0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PF_PF_INDR  -------------------------------
+// SVD Line: 14060
+
+unsigned int PF_PF_INDR __AT (0x30000514);
+
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR11  ---------------------------------
+// SVD Line: 14070
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR11
+//    <name> INDR11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x30000514) Port n Input Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.11..11> INDR11
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR10  ---------------------------------
+// SVD Line: 14076
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR10
+//    <name> INDR10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x30000514) Port n Input Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.10..10> INDR10
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR9  ----------------------------------
+// SVD Line: 14082
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR9
+//    <name> INDR9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x30000514) Port n Input Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.9..9> INDR9
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR8  ----------------------------------
+// SVD Line: 14088
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR8
+//    <name> INDR8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x30000514) Port n Input Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.8..8> INDR8
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR7  ----------------------------------
+// SVD Line: 14094
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR7
+//    <name> INDR7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x30000514) Port n Input Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.7..7> INDR7
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR6  ----------------------------------
+// SVD Line: 14100
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR6
+//    <name> INDR6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x30000514) Port n Input Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.6..6> INDR6
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR5  ----------------------------------
+// SVD Line: 14106
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR5
+//    <name> INDR5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x30000514) Port n Input Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.5..5> INDR5
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR4  ----------------------------------
+// SVD Line: 14112
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR4
+//    <name> INDR4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x30000514) Port n Input Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.4..4> INDR4
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR3  ----------------------------------
+// SVD Line: 14118
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR3
+//    <name> INDR3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x30000514) Port n Input Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.3..3> INDR3
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR2  ----------------------------------
+// SVD Line: 14124
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR2
+//    <name> INDR2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x30000514) Port n Input Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.2..2> INDR2
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR1  ----------------------------------
+// SVD Line: 14130
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR1
+//    <name> INDR1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x30000514) Port n Input Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.1..1> INDR1
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: PF_PF_INDR_INDR0  ----------------------------------
+// SVD Line: 14136
+
+//  <item> SFDITEM_FIELD__PF_PF_INDR_INDR0
+//    <name> INDR0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x30000514) Port n Input Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_INDR ) </loc>
+//      <o.0..0> INDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PF_PF_INDR  -----------------------------------
+// SVD Line: 14060
+
+//  <rtree> SFDITEM_REG__PF_PF_INDR
+//    <name> PF_INDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30000514) Port n Input Data Register </i>
+//    <loc> ( (unsigned int)((PF_PF_INDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR8 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_INDR_INDR0 </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: PF_PF_OUTDR  -------------------------------
+// SVD Line: 14144
+
+unsigned int PF_PF_OUTDR __AT (0x30000518);
+
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR11  --------------------------------
+// SVD Line: 14154
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR11
+//    <name> OUTDR11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000518) Port n Output Data 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.11..11> OUTDR11
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR10  --------------------------------
+// SVD Line: 14160
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR10
+//    <name> OUTDR10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000518) Port n Output Data 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.10..10> OUTDR10
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR9  ---------------------------------
+// SVD Line: 14166
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR9
+//    <name> OUTDR9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000518) Port n Output Data 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.9..9> OUTDR9
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR8  ---------------------------------
+// SVD Line: 14172
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR8
+//    <name> OUTDR8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000518) Port n Output Data 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.8..8> OUTDR8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR7  ---------------------------------
+// SVD Line: 14178
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR7
+//    <name> OUTDR7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000518) Port n Output Data 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.7..7> OUTDR7
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR6  ---------------------------------
+// SVD Line: 14184
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR6
+//    <name> OUTDR6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000518) Port n Output Data 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.6..6> OUTDR6
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR5  ---------------------------------
+// SVD Line: 14190
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR5
+//    <name> OUTDR5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000518) Port n Output Data 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.5..5> OUTDR5
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR4  ---------------------------------
+// SVD Line: 14196
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR4
+//    <name> OUTDR4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000518) Port n Output Data 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.4..4> OUTDR4
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR3  ---------------------------------
+// SVD Line: 14202
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR3
+//    <name> OUTDR3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000518) Port n Output Data 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.3..3> OUTDR3
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR2  ---------------------------------
+// SVD Line: 14208
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR2
+//    <name> OUTDR2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000518) Port n Output Data 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.2..2> OUTDR2
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR1  ---------------------------------
+// SVD Line: 14214
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR1
+//    <name> OUTDR1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000518) Port n Output Data 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.1..1> OUTDR1
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: PF_PF_OUTDR_OUTDR0  ---------------------------------
+// SVD Line: 14220
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR0
+//    <name> OUTDR0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000518) Port n Output Data 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDR ) </loc>
+//      <o.0..0> OUTDR0
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: PF_PF_OUTDR  ----------------------------------
+// SVD Line: 14144
+
+//  <rtree> SFDITEM_REG__PF_PF_OUTDR
+//    <name> PF_OUTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000518) Port n Output Data Register </i>
+//    <loc> ( (unsigned int)((PF_PF_OUTDR >> 0) & 0xFFFFFFFF), ((PF_PF_OUTDR = (PF_PF_OUTDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR8 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDR_OUTDR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PF_PF_BSR  --------------------------------
+// SVD Line: 14228
+
+unsigned int PF_PF_BSR __AT (0x3000051C);
+
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR11  ----------------------------------
+// SVD Line: 14238
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR11
+//    <name> BSR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x3000051C) Port n Output Bit Set 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.11..11> BSR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR10  ----------------------------------
+// SVD Line: 14244
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR10
+//    <name> BSR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x3000051C) Port n Output Bit Set 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.10..10> BSR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR9  -----------------------------------
+// SVD Line: 14250
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR9
+//    <name> BSR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x3000051C) Port n Output Bit Set 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.9..9> BSR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR8  -----------------------------------
+// SVD Line: 14256
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR8
+//    <name> BSR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x3000051C) Port n Output Bit Set 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.8..8> BSR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR7  -----------------------------------
+// SVD Line: 14262
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR7
+//    <name> BSR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x3000051C) Port n Output Bit Set 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.7..7> BSR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR6  -----------------------------------
+// SVD Line: 14268
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR6
+//    <name> BSR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x3000051C) Port n Output Bit Set 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.6..6> BSR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR5  -----------------------------------
+// SVD Line: 14274
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR5
+//    <name> BSR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x3000051C) Port n Output Bit Set 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.5..5> BSR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR4  -----------------------------------
+// SVD Line: 14280
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR4
+//    <name> BSR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x3000051C) Port n Output Bit Set 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.4..4> BSR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR3  -----------------------------------
+// SVD Line: 14286
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR3
+//    <name> BSR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x3000051C) Port n Output Bit Set 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.3..3> BSR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR2  -----------------------------------
+// SVD Line: 14292
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR2
+//    <name> BSR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x3000051C) Port n Output Bit Set 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.2..2> BSR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR1  -----------------------------------
+// SVD Line: 14298
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR1
+//    <name> BSR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x3000051C) Port n Output Bit Set 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.1..1> BSR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BSR_BSR0  -----------------------------------
+// SVD Line: 14304
+
+//  <item> SFDITEM_FIELD__PF_PF_BSR_BSR0
+//    <name> BSR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x3000051C) Port n Output Bit Set 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BSR ) </loc>
+//      <o.0..0> BSR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PF_PF_BSR  -----------------------------------
+// SVD Line: 14228
+
+//  <rtree> SFDITEM_REG__PF_PF_BSR
+//    <name> PF_BSR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x3000051C) Port n Output Bit Set Register </i>
+//    <loc> ( (unsigned int)((PF_PF_BSR >> 0) & 0xFFFFFFFF), ((PF_PF_BSR = (PF_PF_BSR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR8 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BSR_BSR0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: PF_PF_BCR  --------------------------------
+// SVD Line: 14312
+
+unsigned int PF_PF_BCR __AT (0x30000520);
+
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR11  ----------------------------------
+// SVD Line: 14322
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR11
+//    <name> BCR11 </name>
+//    <w> 
+//    <i> [Bit 11] WO (@ 0x30000520) Port n Output Bit Clear 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.11..11> BCR11
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR10  ----------------------------------
+// SVD Line: 14328
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR10
+//    <name> BCR10 </name>
+//    <w> 
+//    <i> [Bit 10] WO (@ 0x30000520) Port n Output Bit Clear 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.10..10> BCR10
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR9  -----------------------------------
+// SVD Line: 14334
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR9
+//    <name> BCR9 </name>
+//    <w> 
+//    <i> [Bit 9] WO (@ 0x30000520) Port n Output Bit Clear 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.9..9> BCR9
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR8  -----------------------------------
+// SVD Line: 14340
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR8
+//    <name> BCR8 </name>
+//    <w> 
+//    <i> [Bit 8] WO (@ 0x30000520) Port n Output Bit Clear 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.8..8> BCR8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR7  -----------------------------------
+// SVD Line: 14346
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR7
+//    <name> BCR7 </name>
+//    <w> 
+//    <i> [Bit 7] WO (@ 0x30000520) Port n Output Bit Clear 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.7..7> BCR7
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR6  -----------------------------------
+// SVD Line: 14352
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR6
+//    <name> BCR6 </name>
+//    <w> 
+//    <i> [Bit 6] WO (@ 0x30000520) Port n Output Bit Clear 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.6..6> BCR6
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR5  -----------------------------------
+// SVD Line: 14358
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR5
+//    <name> BCR5 </name>
+//    <w> 
+//    <i> [Bit 5] WO (@ 0x30000520) Port n Output Bit Clear 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.5..5> BCR5
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR4  -----------------------------------
+// SVD Line: 14364
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR4
+//    <name> BCR4 </name>
+//    <w> 
+//    <i> [Bit 4] WO (@ 0x30000520) Port n Output Bit Clear 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.4..4> BCR4
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR3  -----------------------------------
+// SVD Line: 14370
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR3
+//    <name> BCR3 </name>
+//    <w> 
+//    <i> [Bit 3] WO (@ 0x30000520) Port n Output Bit Clear 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.3..3> BCR3
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR2  -----------------------------------
+// SVD Line: 14376
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR2
+//    <name> BCR2 </name>
+//    <w> 
+//    <i> [Bit 2] WO (@ 0x30000520) Port n Output Bit Clear 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.2..2> BCR2
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR1  -----------------------------------
+// SVD Line: 14382
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR1
+//    <name> BCR1 </name>
+//    <w> 
+//    <i> [Bit 1] WO (@ 0x30000520) Port n Output Bit Clear 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.1..1> BCR1
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: PF_PF_BCR_BCR0  -----------------------------------
+// SVD Line: 14388
+
+//  <item> SFDITEM_FIELD__PF_PF_BCR_BCR0
+//    <name> BCR0 </name>
+//    <w> 
+//    <i> [Bit 0] WO (@ 0x30000520) Port n Output Bit Clear 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_BCR ) </loc>
+//      <o.0..0> BCR0
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: PF_PF_BCR  -----------------------------------
+// SVD Line: 14312
+
+//  <rtree> SFDITEM_REG__PF_PF_BCR
+//    <name> PF_BCR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x30000520) Port n Output Bit Clear Register </i>
+//    <loc> ( (unsigned int)((PF_PF_BCR >> 0) & 0xFFFFFFFF), ((PF_PF_BCR = (PF_PF_BCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR8 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_BCR_BCR0 </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: PF_PF_OUTDMSK  ------------------------------
+// SVD Line: 14396
+
+unsigned int PF_PF_OUTDMSK __AT (0x30000524);
+
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK11  ------------------------------
+// SVD Line: 14406
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK11
+//    <name> OUTDMSK11 </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x30000524) Port n Output Data Mask 11 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.11..11> OUTDMSK11
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK10  ------------------------------
+// SVD Line: 14412
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK10
+//    <name> OUTDMSK10 </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x30000524) Port n Output Data Mask 10 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.10..10> OUTDMSK10
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK9  -------------------------------
+// SVD Line: 14418
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK9
+//    <name> OUTDMSK9 </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x30000524) Port n Output Data Mask 9 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.9..9> OUTDMSK9
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK8  -------------------------------
+// SVD Line: 14424
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK8
+//    <name> OUTDMSK8 </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x30000524) Port n Output Data Mask 8 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.8..8> OUTDMSK8
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK7  -------------------------------
+// SVD Line: 14430
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK7
+//    <name> OUTDMSK7 </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30000524) Port n Output Data Mask 7 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.7..7> OUTDMSK7
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK6  -------------------------------
+// SVD Line: 14436
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK6
+//    <name> OUTDMSK6 </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30000524) Port n Output Data Mask 6 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.6..6> OUTDMSK6
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK5  -------------------------------
+// SVD Line: 14442
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK5
+//    <name> OUTDMSK5 </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30000524) Port n Output Data Mask 5 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.5..5> OUTDMSK5
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK4  -------------------------------
+// SVD Line: 14448
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK4
+//    <name> OUTDMSK4 </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30000524) Port n Output Data Mask 4 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.4..4> OUTDMSK4
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK3  -------------------------------
+// SVD Line: 14454
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK3
+//    <name> OUTDMSK3 </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30000524) Port n Output Data Mask 3 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.3..3> OUTDMSK3
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK2  -------------------------------
+// SVD Line: 14460
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK2
+//    <name> OUTDMSK2 </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x30000524) Port n Output Data Mask 2 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.2..2> OUTDMSK2
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK1  -------------------------------
+// SVD Line: 14466
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK1
+//    <name> OUTDMSK1 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30000524) Port n Output Data Mask 1 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.1..1> OUTDMSK1
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: PF_PF_OUTDMSK_OUTDMSK0  -------------------------------
+// SVD Line: 14472
+
+//  <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK0
+//    <name> OUTDMSK0 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30000524) Port n Output Data Mask 0 </i>
+//    <check> 
+//      <loc> ( (unsigned int) PF_PF_OUTDMSK ) </loc>
+//      <o.0..0> OUTDMSK0
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: PF_PF_OUTDMSK  ---------------------------------
+// SVD Line: 14396
+
+//  <rtree> SFDITEM_REG__PF_PF_OUTDMSK
+//    <name> PF_OUTDMSK </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30000524) Port n Output Data Mask Register </i>
+//    <loc> ( (unsigned int)((PF_PF_OUTDMSK >> 0) & 0xFFFFFFFF), ((PF_PF_OUTDMSK = (PF_PF_OUTDMSK & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK11 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK10 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK9 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK8 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK7 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK6 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK5 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK4 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK3 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK2 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK1 </item>
+//    <item> SFDITEM_FIELD__PF_PF_OUTDMSK_OUTDMSK0 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------------  Peripheral View: PF  --------------------------------------
+// SVD Line: 13698
+
+//  <view> PF
+//    <name> PF </name>
+//    <item> SFDITEM_REG__PF_MOD </item>
+//    <item> SFDITEM_REG__PF_TYP </item>
+//    <item> SFDITEM_REG__PF_AFSR1 </item>
+//    <item> SFDITEM_REG__PF_AFSR2 </item>
+//    <item> SFDITEM_REG__PF_PUPD </item>
+//    <item> SFDITEM_REG__PF_INDR </item>
+//    <item> SFDITEM_REG__PF_OUTDR </item>
+//    <item> SFDITEM_REG__PF_BSR </item>
+//    <item> SFDITEM_REG__PF_BCR </item>
+//    <item> SFDITEM_REG__PF_OUTDMSK </item>
+//    <item> SFDITEM_REG__PF_DBCR </item>
+//    <item> SFDITEM_REG__PF_PF_MOD </item>
+//    <item> SFDITEM_REG__PF_PF_TYP </item>
+//    <item> SFDITEM_REG__PF_PF_AFSR1 </item>
+//    <item> SFDITEM_REG__PF_PF_AFSR2 </item>
+//    <item> SFDITEM_REG__PF_PF_PUPD </item>
+//    <item> SFDITEM_REG__PF_PF_INDR </item>
+//    <item> SFDITEM_REG__PF_PF_OUTDR </item>
+//    <item> SFDITEM_REG__PF_PF_BSR </item>
+//    <item> SFDITEM_REG__PF_PF_BCR </item>
+//    <item> SFDITEM_REG__PF_PF_OUTDMSK </item>
+//  </view>
+//  
+
+
+// -----------------------------  Register Item Address: FMC_ADR  ---------------------------------
+// SVD Line: 14496
+
+unsigned int FMC_ADR __AT (0x40001B00);
+
+
+
+// --------------------------------  Field Item: FMC_ADR_ADDR  ------------------------------------
+// SVD Line: 14505
+
+//  <item> SFDITEM_FIELD__FMC_ADR_ADDR
+//    <name> ADDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B00) Flash Memory Address Pointer </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((FMC_ADR >> 0) & 0xFFFFFFFF), ((FMC_ADR = (FMC_ADR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: FMC_ADR  ------------------------------------
+// SVD Line: 14496
+
+//  <rtree> SFDITEM_REG__FMC_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B00) Flash Memory Address Register </i>
+//    <loc> ( (unsigned int)((FMC_ADR >> 0) & 0xFFFFFFFF), ((FMC_ADR = (FMC_ADR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__FMC_ADR_ADDR </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: FMC_IDR1  --------------------------------
+// SVD Line: 14513
+
+unsigned int FMC_IDR1 __AT (0x40001B04);
+
+
+
+// --------------------------------  Field Item: FMC_IDR1_ID1  ------------------------------------
+// SVD Line: 14522
+
+//  <item> SFDITEM_FIELD__FMC_IDR1_ID1
+//    <name> ID1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B04) Flash Memory Identification 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((FMC_IDR1 >> 0) & 0xFFFFFFFF), ((FMC_IDR1 = (FMC_IDR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: FMC_IDR1  ------------------------------------
+// SVD Line: 14513
+
+//  <rtree> SFDITEM_REG__FMC_IDR1
+//    <name> IDR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B04) Flash Memory Identification Register 1 </i>
+//    <loc> ( (unsigned int)((FMC_IDR1 >> 0) & 0xFFFFFFFF), ((FMC_IDR1 = (FMC_IDR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__FMC_IDR1_ID1 </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: FMC_IDR2  --------------------------------
+// SVD Line: 14530
+
+unsigned int FMC_IDR2 __AT (0x40001B08);
+
+
+
+// --------------------------------  Field Item: FMC_IDR2_ID2  ------------------------------------
+// SVD Line: 14539
+
+//  <item> SFDITEM_FIELD__FMC_IDR2_ID2
+//    <name> ID2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B08) Flash Memory Identification 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((FMC_IDR2 >> 0) & 0xFFFFFFFF), ((FMC_IDR2 = (FMC_IDR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: FMC_IDR2  ------------------------------------
+// SVD Line: 14530
+
+//  <rtree> SFDITEM_REG__FMC_IDR2
+//    <name> IDR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B08) Flash Memory Identification Register 2 </i>
+//    <loc> ( (unsigned int)((FMC_IDR2 >> 0) & 0xFFFFFFFF), ((FMC_IDR2 = (FMC_IDR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__FMC_IDR2_ID2 </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: FMC_CR  ---------------------------------
+// SVD Line: 14547
+
+unsigned int FMC_CR __AT (0x40001B0C);
+
+
+
+// --------------------------------  Field Item: FMC_CR_WTIDKY  -----------------------------------
+// SVD Line: 14556
+
+//  <item> SFDITEM_FIELD__FMC_CR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x40001B0C) Write Identification Key (0x6c93) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((FMC_CR >> 16) & 0x0), ((FMC_CR = (FMC_CR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: FMC_CR_FMKEY  ------------------------------------
+// SVD Line: 14569
+
+//  <item> SFDITEM_FIELD__FMC_CR_FMKEY
+//    <name> FMKEY </name>
+//    <rw> 
+//    <i> [Bits 15..8] RW (@ 0x40001B0C) Flash Memory Operation Area Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((FMC_CR >> 8) & 0xFF), ((FMC_CR = (FMC_CR & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: FMC_CR_FMBUSY  -----------------------------------
+// SVD Line: 14575
+
+//  <item> SFDITEM_FIELD__FMC_CR_FMBUSY
+//    <name> FMBUSY </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x40001B0C) Flash Memory Operation Mode Busy </i>
+//    <check> 
+//      <loc> ( (unsigned int) FMC_CR ) </loc>
+//      <o.7..7> FMBUSY
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: FMC_CR_FMOD  ------------------------------------
+// SVD Line: 14581
+
+//  <item> SFDITEM_FIELD__FMC_CR_FMOD
+//    <name> FMOD </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40001B0C) Flash Memory Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((FMC_CR >> 0) & 0xF), ((FMC_CR = (FMC_CR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: FMC_CR  -------------------------------------
+// SVD Line: 14547
+
+//  <rtree> SFDITEM_REG__FMC_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B0C) Flash Memory Control Register </i>
+//    <loc> ( (unsigned int)((FMC_CR >> 0) & 0xFFFFFFFF), ((FMC_CR = (FMC_CR & ~(0xFFFFFF0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF0F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__FMC_CR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__FMC_CR_FMKEY </item>
+//    <item> SFDITEM_FIELD__FMC_CR_FMBUSY </item>
+//    <item> SFDITEM_FIELD__FMC_CR_FMOD </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: FMC_BCR  ---------------------------------
+// SVD Line: 14589
+
+unsigned int FMC_BCR __AT (0x40001B10);
+
+
+
+// -------------------------------  Field Item: FMC_BCR_WTIDKY  -----------------------------------
+// SVD Line: 14598
+
+//  <item> SFDITEM_FIELD__FMC_BCR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x40001B10) Write Identification Key (0xc1be) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((FMC_BCR >> 16) & 0x0), ((FMC_BCR = (FMC_BCR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: FMC_BCR_CNF3BEN  ----------------------------------
+// SVD Line: 14611
+
+//  <item> SFDITEM_FIELD__FMC_BCR_CNF3BEN
+//    <name> CNF3BEN </name>
+//    <rw> 
+//    <i> [Bits 11..8] RW (@ 0x40001B10) Configure Option Page 3 Bulk Erase Enable </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((FMC_BCR >> 8) & 0xF), ((FMC_BCR = (FMC_BCR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: FMC_BCR_CNF2BEN  ----------------------------------
+// SVD Line: 14617
+
+//  <item> SFDITEM_FIELD__FMC_BCR_CNF2BEN
+//    <name> CNF2BEN </name>
+//    <rw> 
+//    <i> [Bits 7..4] RW (@ 0x40001B10) Configure Option Page 2 Bulk Erase Enable </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((FMC_BCR >> 4) & 0xF), ((FMC_BCR = (FMC_BCR & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: FMC_BCR_CNF1BEN  ----------------------------------
+// SVD Line: 14623
+
+//  <item> SFDITEM_FIELD__FMC_BCR_CNF1BEN
+//    <name> CNF1BEN </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40001B10) Configure Option Page 1 Bulk Erase Enable </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((FMC_BCR >> 0) & 0xF), ((FMC_BCR = (FMC_BCR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: FMC_BCR  ------------------------------------
+// SVD Line: 14589
+
+//  <rtree> SFDITEM_REG__FMC_BCR
+//    <name> BCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B10) Flash Memory Configure Area Bulk Erase Control Register </i>
+//    <loc> ( (unsigned int)((FMC_BCR >> 0) & 0xFFFFFFFF), ((FMC_BCR = (FMC_BCR & ~(0xFFFF0FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__FMC_BCR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__FMC_BCR_CNF3BEN </item>
+//    <item> SFDITEM_FIELD__FMC_BCR_CNF2BEN </item>
+//    <item> SFDITEM_FIELD__FMC_BCR_CNF1BEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: FMC_ERFLAG  -------------------------------
+// SVD Line: 14631
+
+unsigned int FMC_ERFLAG __AT (0x40001B14);
+
+
+
+// -----------------------------  Field Item: FMC_ERFLAG_INSTFLAG  --------------------------------
+// SVD Line: 14640
+
+//  <item> SFDITEM_FIELD__FMC_ERFLAG_INSTFLAG
+//    <name> INSTFLAG </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001B14) Don't care </i>
+//    <check> 
+//      <loc> ( (unsigned int) FMC_ERFLAG ) </loc>
+//      <o.1..1> INSTFLAG
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: FMC_ERFLAG_FMOPFLAG  --------------------------------
+// SVD Line: 14646
+
+//  <item> SFDITEM_FIELD__FMC_ERFLAG_FMOPFLAG
+//    <name> FMOPFLAG </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001B14) Error bit of Flash Memory Operation Procedure </i>
+//    <check> 
+//      <loc> ( (unsigned int) FMC_ERFLAG ) </loc>
+//      <o.0..0> FMOPFLAG
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: FMC_ERFLAG  -----------------------------------
+// SVD Line: 14631
+
+//  <rtree> SFDITEM_REG__FMC_ERFLAG
+//    <name> ERFLAG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001B14) Flash Memory Error Flag </i>
+//    <loc> ( (unsigned int)((FMC_ERFLAG >> 0) & 0xFFFFFFFF), ((FMC_ERFLAG = (FMC_ERFLAG & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__FMC_ERFLAG_INSTFLAG </item>
+//    <item> SFDITEM_FIELD__FMC_ERFLAG_FMOPFLAG </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: FMC_PAGEBUF  -------------------------------
+// SVD Line: 14654
+
+unsigned int FMC_PAGEBUF __AT (0x40001C00);
+
+
+
+// -------------------------------  Register Item: FMC_PAGEBUF  -----------------------------------
+// SVD Line: 14654
+
+//  <item> SFDITEM_REG__FMC_PAGEBUF
+//    <name> PAGEBUF </name>
+//    <i> [Bits 31..0] WO (@ 0x40001C00) Flash Memory Page Buffer Area (128bytes/Accessed by 32bit Word Only) </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((FMC_PAGEBUF >> 0) & 0xFFFFFFFF), ((FMC_PAGEBUF = (FMC_PAGEBUF & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------------  Peripheral View: FMC  --------------------------------------
+// SVD Line: 14482
+
+//  <view> FMC
+//    <name> FMC </name>
+//    <item> SFDITEM_REG__FMC_ADR </item>
+//    <item> SFDITEM_REG__FMC_IDR1 </item>
+//    <item> SFDITEM_REG__FMC_IDR2 </item>
+//    <item> SFDITEM_REG__FMC_CR </item>
+//    <item> SFDITEM_REG__FMC_BCR </item>
+//    <item> SFDITEM_REG__FMC_ERFLAG </item>
+//    <item> SFDITEM_REG__FMC_PAGEBUF </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: WDT_CR  ---------------------------------
+// SVD Line: 14684
+
+unsigned int WDT_CR __AT (0x40001A00);
+
+
+
+// --------------------------------  Field Item: WDT_CR_WTIDKY  -----------------------------------
+// SVD Line: 14693
+
+//  <item> SFDITEM_FIELD__WDT_CR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x40001A00) Write Identification Key (0x5a69) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((WDT_CR >> 16) & 0x0), ((WDT_CR = (WDT_CR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: WDT_CR_RSTEN  ------------------------------------
+// SVD Line: 14706
+
+//  <item> SFDITEM_FIELD__WDT_CR_RSTEN
+//    <name> RSTEN </name>
+//    <rw> 
+//    <i> [Bits 15..10] RW (@ 0x40001A00) \nWatch-Dog Timer Reset Enable\n0 : Enable = Enable Watch-Dog Timer reset.\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : Reserved - do not use\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : Reserved - do not use\n34 : Reserved - do not use\n35 : Reserved - do not use\n36 : Reserved - do not use\n37 : Disable = Disable Watch-Dog Timer reset. (0x25)\n38 : Reserved - do not use\n39 : Reserved - do not use\n40 : Reserved - do not use\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WDT_CR ) </loc>
+//      <o.15..10> RSTEN
+//        <0=> 0: Enable = Enable Watch-Dog Timer reset.
+//        <1=> 1: 
+//        <2=> 2: 
+//        <3=> 3: 
+//        <4=> 4: 
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//        <16=> 16: 
+//        <17=> 17: 
+//        <18=> 18: 
+//        <19=> 19: 
+//        <20=> 20: 
+//        <21=> 21: 
+//        <22=> 22: 
+//        <23=> 23: 
+//        <24=> 24: 
+//        <25=> 25: 
+//        <26=> 26: 
+//        <27=> 27: 
+//        <28=> 28: 
+//        <29=> 29: 
+//        <30=> 30: 
+//        <31=> 31: 
+//        <32=> 32: 
+//        <33=> 33: 
+//        <34=> 34: 
+//        <35=> 35: 
+//        <36=> 36: 
+//        <37=> 37: Disable = Disable Watch-Dog Timer reset. (0x25)
+//        <38=> 38: 
+//        <39=> 39: 
+//        <40=> 40: 
+//        <41=> 41: 
+//        <42=> 42: 
+//        <43=> 43: 
+//        <44=> 44: 
+//        <45=> 45: 
+//        <46=> 46: 
+//        <47=> 47: 
+//        <48=> 48: 
+//        <49=> 49: 
+//        <50=> 50: 
+//        <51=> 51: 
+//        <52=> 52: 
+//        <53=> 53: 
+//        <54=> 54: 
+//        <55=> 55: 
+//        <56=> 56: 
+//        <57=> 57: 
+//        <58=> 58: 
+//        <59=> 59: 
+//        <60=> 60: 
+//        <61=> 61: 
+//        <62=> 62: 
+//        <63=> 63: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: WDT_CR_CNTEN  ------------------------------------
+// SVD Line: 14724
+
+//  <item> SFDITEM_FIELD__WDT_CR_CNTEN
+//    <name> CNTEN </name>
+//    <rw> 
+//    <i> [Bits 9..4] RW (@ 0x40001A00) \nWatch-Dog Timer Counter Enable\n0 : Enable = Enable Watch-Dog Timer counter.\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : Reserved - do not use\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Disable = Disable Watch-Dog Timer counter. (0x1a)\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : Reserved - do not use\n34 : Reserved - do not use\n35 : Reserved - do not use\n36 : Reserved - do not use\n37 : Reserved - do not use\n38 : Reserved - do not use\n39 : Reserved - do not use\n40 : Reserved - do not use\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WDT_CR ) </loc>
+//      <o.9..4> CNTEN
+//        <0=> 0: Enable = Enable Watch-Dog Timer counter.
+//        <1=> 1: 
+//        <2=> 2: 
+//        <3=> 3: 
+//        <4=> 4: 
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//        <8=> 8: 
+//        <9=> 9: 
+//        <10=> 10: 
+//        <11=> 11: 
+//        <12=> 12: 
+//        <13=> 13: 
+//        <14=> 14: 
+//        <15=> 15: 
+//        <16=> 16: 
+//        <17=> 17: 
+//        <18=> 18: 
+//        <19=> 19: 
+//        <20=> 20: 
+//        <21=> 21: 
+//        <22=> 22: 
+//        <23=> 23: 
+//        <24=> 24: 
+//        <25=> 25: 
+//        <26=> 26: Disable = Disable Watch-Dog Timer counter. (0x1a)
+//        <27=> 27: 
+//        <28=> 28: 
+//        <29=> 29: 
+//        <30=> 30: 
+//        <31=> 31: 
+//        <32=> 32: 
+//        <33=> 33: 
+//        <34=> 34: 
+//        <35=> 35: 
+//        <36=> 36: 
+//        <37=> 37: 
+//        <38=> 38: 
+//        <39=> 39: 
+//        <40=> 40: 
+//        <41=> 41: 
+//        <42=> 42: 
+//        <43=> 43: 
+//        <44=> 44: 
+//        <45=> 45: 
+//        <46=> 46: 
+//        <47=> 47: 
+//        <48=> 48: 
+//        <49=> 49: 
+//        <50=> 50: 
+//        <51=> 51: 
+//        <52=> 52: 
+//        <53=> 53: 
+//        <54=> 54: 
+//        <55=> 55: 
+//        <56=> 56: 
+//        <57=> 57: 
+//        <58=> 58: 
+//        <59=> 59: 
+//        <60=> 60: 
+//        <61=> 61: 
+//        <62=> 62: 
+//        <63=> 63: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: WDT_CR_WINMIEN  -----------------------------------
+// SVD Line: 14742
+
+//  <item> SFDITEM_FIELD__WDT_CR_WINMIEN
+//    <name> WINMIEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40001A00) \nWatch-Dog Timer Window Match Interrupt Enable\n0 : Disable = Disable window data match interrupt.\n1 : Enable = Enable window data match interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WDT_CR ) </loc>
+//      <o.3..3> WINMIEN
+//        <0=> 0: Disable = Disable window data match interrupt.
+//        <1=> 1: Enable = Enable window data match interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: WDT_CR_UNFIEN  -----------------------------------
+// SVD Line: 14760
+
+//  <item> SFDITEM_FIELD__WDT_CR_UNFIEN
+//    <name> UNFIEN </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40001A00) \nWatch-Dog Timer Underflow Interrupt Enable\n0 : Disable = Disable Watch-Dog Timer underflow interrupt.\n1 : Enable = Enable Watch-Dog Timer underflow interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WDT_CR ) </loc>
+//      <o.2..2> UNFIEN
+//        <0=> 0: Disable = Disable Watch-Dog Timer underflow interrupt.
+//        <1=> 1: Enable = Enable Watch-Dog Timer underflow interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: WDT_CR_CLKDIV  -----------------------------------
+// SVD Line: 14778
+
+//  <item> SFDITEM_FIELD__WDT_CR_CLKDIV
+//    <name> CLKDIV </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x40001A00) \nWatch-Dog Timer Clock Divider\n0 : fWDT4 = fWDT/4\n1 : fWDT16 = fWDT/16\n2 : fWDT64 = fWDT/64\n3 : fWDT256 = fWDT/256 </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WDT_CR ) </loc>
+//      <o.1..0> CLKDIV
+//        <0=> 0: fWDT4 = fWDT/4
+//        <1=> 1: fWDT16 = fWDT/16
+//        <2=> 2: fWDT64 = fWDT/64
+//        <3=> 3: fWDT256 = fWDT/256
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: WDT_CR  -------------------------------------
+// SVD Line: 14684
+
+//  <rtree> SFDITEM_REG__WDT_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001A00) Watch-Dog Timer Control Register </i>
+//    <loc> ( (unsigned int)((WDT_CR >> 0) & 0xFFFFFFFF), ((WDT_CR = (WDT_CR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__WDT_CR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__WDT_CR_RSTEN </item>
+//    <item> SFDITEM_FIELD__WDT_CR_CNTEN </item>
+//    <item> SFDITEM_FIELD__WDT_CR_WINMIEN </item>
+//    <item> SFDITEM_FIELD__WDT_CR_UNFIEN </item>
+//    <item> SFDITEM_FIELD__WDT_CR_CLKDIV </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: WDT_SR  ---------------------------------
+// SVD Line: 14808
+
+unsigned int WDT_SR __AT (0x40001A04);
+
+
+
+// -------------------------------  Field Item: WDT_SR_DBGCNTEN  ----------------------------------
+// SVD Line: 14817
+
+//  <item> SFDITEM_FIELD__WDT_SR_DBGCNTEN
+//    <name> DBGCNTEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40001A04) \nWatch-Dog Timer Counter Enable when the core is halted in debug mode\n0 : Run = The Watch-Dog Timer counter continues even if the core is halted\n1 : Stop = The Watch-Dog Timer counter is stopped when the core is halted </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WDT_SR ) </loc>
+//      <o.7..7> DBGCNTEN
+//        <0=> 0: Run = The Watch-Dog Timer counter continues even if the core is halted
+//        <1=> 1: Stop = The Watch-Dog Timer counter is stopped when the core is halted
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: WDT_SR_WINMIFLAG  ----------------------------------
+// SVD Line: 14835
+
+//  <item> SFDITEM_FIELD__WDT_SR_WINMIFLAG
+//    <name> WINMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40001A04) \nWatch-Dog Timer Window Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WDT_SR ) </loc>
+//      <o.1..1> WINMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: WDT_SR_UNFIFLAG  ----------------------------------
+// SVD Line: 14853
+
+//  <item> SFDITEM_FIELD__WDT_SR_UNFIFLAG
+//    <name> UNFIFLAG </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40001A04) \nWatch-Dog Timer Underflow Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WDT_SR ) </loc>
+//      <o.0..0> UNFIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: WDT_SR  -------------------------------------
+// SVD Line: 14808
+
+//  <rtree> SFDITEM_REG__WDT_SR
+//    <name> SR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001A04) Watch-Dog Timer Status Register </i>
+//    <loc> ( (unsigned int)((WDT_SR >> 0) & 0xFFFFFFFF), ((WDT_SR = (WDT_SR & ~(0x83UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x83) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__WDT_SR_DBGCNTEN </item>
+//    <item> SFDITEM_FIELD__WDT_SR_WINMIFLAG </item>
+//    <item> SFDITEM_FIELD__WDT_SR_UNFIFLAG </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: WDT_DR  ---------------------------------
+// SVD Line: 14873
+
+unsigned int WDT_DR __AT (0x40001A08);
+
+
+
+// ---------------------------------  Field Item: WDT_DR_DATA  ------------------------------------
+// SVD Line: 14882
+
+//  <item> SFDITEM_FIELD__WDT_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 23..0] RW (@ 0x40001A08) Watch-Dog Timer Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((WDT_DR >> 0) & 0xFFFFFF), ((WDT_DR = (WDT_DR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: WDT_DR  -------------------------------------
+// SVD Line: 14873
+
+//  <rtree> SFDITEM_REG__WDT_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001A08) Watch-Dog Timer Data Register </i>
+//    <loc> ( (unsigned int)((WDT_DR >> 0) & 0xFFFFFFFF), ((WDT_DR = (WDT_DR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__WDT_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: WDT_CNT  ---------------------------------
+// SVD Line: 14890
+
+unsigned int WDT_CNT __AT (0x40001A0C);
+
+
+
+// ---------------------------------  Field Item: WDT_CNT_CNT  ------------------------------------
+// SVD Line: 14899
+
+//  <item> SFDITEM_FIELD__WDT_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 23..0] RO (@ 0x40001A0C) Watch-Dog Timer Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((WDT_CNT >> 0) & 0xFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: WDT_CNT  ------------------------------------
+// SVD Line: 14890
+
+//  <rtree> SFDITEM_REG__WDT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40001A0C) Watch-Dog Timer Counter Register </i>
+//    <loc> ( (unsigned int)((WDT_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__WDT_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: WDT_WINDR  --------------------------------
+// SVD Line: 14907
+
+unsigned int WDT_WINDR __AT (0x40001A10);
+
+
+
+// -------------------------------  Field Item: WDT_WINDR_WDATA  ----------------------------------
+// SVD Line: 14916
+
+//  <item> SFDITEM_FIELD__WDT_WINDR_WDATA
+//    <name> WDATA </name>
+//    <rw> 
+//    <i> [Bits 23..0] RW (@ 0x40001A10) Watch-Dog Timer Window Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((WDT_WINDR >> 0) & 0xFFFFFF), ((WDT_WINDR = (WDT_WINDR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: WDT_WINDR  -----------------------------------
+// SVD Line: 14907
+
+//  <rtree> SFDITEM_REG__WDT_WINDR
+//    <name> WINDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40001A10) Watch-Dog Timer Window Data Register </i>
+//    <loc> ( (unsigned int)((WDT_WINDR >> 0) & 0xFFFFFFFF), ((WDT_WINDR = (WDT_WINDR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__WDT_WINDR_WDATA </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: WDT_CNTR  --------------------------------
+// SVD Line: 14924
+
+unsigned int WDT_CNTR __AT (0x40001A14);
+
+
+
+// --------------------------------  Field Item: WDT_CNTR_CNTR  -----------------------------------
+// SVD Line: 14933
+
+//  <item> SFDITEM_FIELD__WDT_CNTR_CNTR
+//    <name> CNTR </name>
+//    <w> 
+//    <i> [Bits 7..0] WO (@ 0x40001A14) Watch-Dog Timer Counter Reload </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((WDT_CNTR >> 0) & 0x0), ((WDT_CNTR = (WDT_CNTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: WDT_CNTR  ------------------------------------
+// SVD Line: 14924
+
+//  <rtree> SFDITEM_REG__WDT_CNTR
+//    <name> CNTR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x40001A14) Watch-Dog Timer Counter Reload Register </i>
+//    <loc> ( (unsigned int)((WDT_CNTR >> 0) & 0xFFFFFFFF), ((WDT_CNTR = (WDT_CNTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__WDT_CNTR_CNTR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: WDT  --------------------------------------
+// SVD Line: 14665
+
+//  <view> WDT
+//    <name> WDT </name>
+//    <item> SFDITEM_REG__WDT_CR </item>
+//    <item> SFDITEM_REG__WDT_SR </item>
+//    <item> SFDITEM_REG__WDT_DR </item>
+//    <item> SFDITEM_REG__WDT_CNT </item>
+//    <item> SFDITEM_REG__WDT_WINDR </item>
+//    <item> SFDITEM_REG__WDT_CNTR </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: WT_CR  ----------------------------------
+// SVD Line: 14974
+
+unsigned int WT_CR __AT (0x40002000);
+
+
+
+// ---------------------------------  Field Item: WT_CR_WTEN  -------------------------------------
+// SVD Line: 14983
+
+//  <item> SFDITEM_FIELD__WT_CR_WTEN
+//    <name> WTEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40002000) \nWatch Timer Operation Enable\n0 : Disable = Disable watch timer operation.\n1 : Enable = Enable watch timer operation. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WT_CR ) </loc>
+//      <o.7..7> WTEN
+//        <0=> 0: Disable = Disable watch timer operation.
+//        <1=> 1: Enable = Enable watch timer operation.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: WT_CR_WTINTV  ------------------------------------
+// SVD Line: 15001
+
+//  <item> SFDITEM_FIELD__WT_CR_WTINTV
+//    <name> WTINTV </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x40002000) \nWatch Timer Interval Selection\n0 : fWT2Pow7 = fWT/2^7\n1 : fWT2Pow13 = fWT/2^13\n2 : fWT2Pow14 = fWT/2^14\n3 : fWT2Pow14DR = fWT/(2^14x(WTDR value + 1)) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WT_CR ) </loc>
+//      <o.5..4> WTINTV
+//        <0=> 0: fWT2Pow7 = fWT/2^7
+//        <1=> 1: fWT2Pow13 = fWT/2^13
+//        <2=> 2: fWT2Pow14 = fWT/2^14
+//        <3=> 3: fWT2Pow14DR = fWT/(2^14x(WTDR value + 1))
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: WT_CR_WTIEN  ------------------------------------
+// SVD Line: 15029
+
+//  <item> SFDITEM_FIELD__WT_CR_WTIEN
+//    <name> WTIEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002000) \nWatch Timer Interrupt Enable\n0 : Disable = Disable watch timer interrupt.\n1 : Enable = Enable watch timer interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WT_CR ) </loc>
+//      <o.3..3> WTIEN
+//        <0=> 0: Disable = Disable watch timer interrupt.
+//        <1=> 1: Enable = Enable watch timer interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: WT_CR_WTIFLAG  -----------------------------------
+// SVD Line: 15047
+
+//  <item> SFDITEM_FIELD__WT_CR_WTIFLAG
+//    <name> WTIFLAG </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002000) \nWatch Timer Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WT_CR ) </loc>
+//      <o.1..1> WTIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: WT_CR_WTCLR  ------------------------------------
+// SVD Line: 15065
+
+//  <item> SFDITEM_FIELD__WT_CR_WTCLR
+//    <name> WTCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002000) \nWatch Timer Counter and Divider Clear\n0 : NoEffect = No effect.\n1 : Clear = Clear the counter and divider. (Automatically cleared to '0b' after operation) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) WT_CR ) </loc>
+//      <o.0..0> WTCLR
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear the counter and divider. (Automatically cleared to '0b' after operation)
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------------  Register RTree: WT_CR  -------------------------------------
+// SVD Line: 14974
+
+//  <rtree> SFDITEM_REG__WT_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002000) Watch Timer Control Register </i>
+//    <loc> ( (unsigned int)((WT_CR >> 0) & 0xFFFFFFFF), ((WT_CR = (WT_CR & ~(0xBBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xBB) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__WT_CR_WTEN </item>
+//    <item> SFDITEM_FIELD__WT_CR_WTINTV </item>
+//    <item> SFDITEM_FIELD__WT_CR_WTIEN </item>
+//    <item> SFDITEM_FIELD__WT_CR_WTIFLAG </item>
+//    <item> SFDITEM_FIELD__WT_CR_WTCLR </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: WT_DR  ----------------------------------
+// SVD Line: 15085
+
+unsigned int WT_DR __AT (0x40002004);
+
+
+
+// --------------------------------  Field Item: WT_DR_WTDATA  ------------------------------------
+// SVD Line: 15094
+
+//  <item> SFDITEM_FIELD__WT_DR_WTDATA
+//    <name> WTDATA </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002004) Watch Timer Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((WT_DR >> 0) & 0xFFF), ((WT_DR = (WT_DR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------------  Register RTree: WT_DR  -------------------------------------
+// SVD Line: 15085
+
+//  <rtree> SFDITEM_REG__WT_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002004) Watch Timer Data Register </i>
+//    <loc> ( (unsigned int)((WT_DR >> 0) & 0xFFFFFFFF), ((WT_DR = (WT_DR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__WT_DR_WTDATA </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: WT_CNT  ---------------------------------
+// SVD Line: 15102
+
+unsigned int WT_CNT __AT (0x40002008);
+
+
+
+// ---------------------------------  Field Item: WT_CNT_CNT  -------------------------------------
+// SVD Line: 15111
+
+//  <item> SFDITEM_FIELD__WT_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 11..0] RO (@ 0x40002008) Watch Timer Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((WT_CNT >> 0) & 0xFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: WT_CNT  -------------------------------------
+// SVD Line: 15102
+
+//  <rtree> SFDITEM_REG__WT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002008) Watch Timer Counter Register </i>
+//    <loc> ( (unsigned int)((WT_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__WT_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// -----------------------------------  Peripheral View: WT  --------------------------------------
+// SVD Line: 14955
+
+//  <view> WT
+//    <name> WT </name>
+//    <item> SFDITEM_REG__WT_CR </item>
+//    <item> SFDITEM_REG__WT_DR </item>
+//    <item> SFDITEM_REG__WT_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER1n_CR  -------------------------------
+// SVD Line: 15135
+
+unsigned int TIMER1n_CR __AT (0x51000000);
+
+
+
+// ------------------------------  Field Item: TIMER1n_CR_T1nEN  ----------------------------------
+// SVD Line: 15144
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nEN
+//    <name> T1nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x51000000) TIMER1n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.15..15> T1nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER1n_CR_T1nCLK  ---------------------------------
+// SVD Line: 15150
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nCLK
+//    <name> T1nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x51000000) TIMER1n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.14..14> T1nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER1n_CR_T1nMS  ----------------------------------
+// SVD Line: 15156
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nMS
+//    <name> T1nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x51000000) TIMER1n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER1n_CR >> 12) & 0x3), ((TIMER1n_CR = (TIMER1n_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER1n_CR_T1nECE  ---------------------------------
+// SVD Line: 15162
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nECE
+//    <name> T1nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x51000000) TIMER1n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.11..11> T1nECE
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER1n_CR_T1nOPOL  ---------------------------------
+// SVD Line: 15168
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nOPOL
+//    <name> T1nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x51000000) TIMER1n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.8..8> T1nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER1n_CR_T1nCPOL  ---------------------------------
+// SVD Line: 15174
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nCPOL
+//    <name> T1nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x51000000) TIMER1n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER1n_CR >> 6) & 0x3), ((TIMER1n_CR = (TIMER1n_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER1n_CR_T1nMIEN  ---------------------------------
+// SVD Line: 15180
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nMIEN
+//    <name> T1nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x51000000) TIMER1n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.5..5> T1nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER1n_CR_T1nCIEN  ---------------------------------
+// SVD Line: 15186
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nCIEN
+//    <name> T1nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x51000000) TIMER1n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.4..4> T1nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER1n_CR_T1nMIFLAG  --------------------------------
+// SVD Line: 15192
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nMIFLAG
+//    <name> T1nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x51000000) TIMER1n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.3..3> T1nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER1n_CR_T1nCIFLAG  --------------------------------
+// SVD Line: 15198
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nCIFLAG
+//    <name> T1nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x51000000) TIMER1n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.2..2> T1nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER1n_CR_T1nPAU  ---------------------------------
+// SVD Line: 15204
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nPAU
+//    <name> T1nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x51000000) TIMER1n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.1..1> T1nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER1n_CR_T1nCLR  ---------------------------------
+// SVD Line: 15210
+
+//  <item> SFDITEM_FIELD__TIMER1n_CR_T1nCLR
+//    <name> T1nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x51000000) TIMER1n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER1n_CR ) </loc>
+//      <o.0..0> T1nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER1n_CR  -----------------------------------
+// SVD Line: 15135
+
+//  <rtree> SFDITEM_REG__TIMER1n_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x51000000) TIMER1n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER1n_CR >> 0) & 0xFFFFFFFF), ((TIMER1n_CR = (TIMER1n_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nEN </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nMS </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nECE </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER1n_CR_T1nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER1n_ADR  -------------------------------
+// SVD Line: 15218
+
+unsigned int TIMER1n_ADR __AT (0x51000004);
+
+
+
+// ------------------------------  Field Item: TIMER1n_ADR_ADATA  ---------------------------------
+// SVD Line: 15227
+
+//  <item> SFDITEM_FIELD__TIMER1n_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x51000004) TIMER1n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER1n_ADR >> 0) & 0xFFFF), ((TIMER1n_ADR = (TIMER1n_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER1n_ADR  ----------------------------------
+// SVD Line: 15218
+
+//  <rtree> SFDITEM_REG__TIMER1n_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x51000004) TIMER1n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER1n_ADR >> 0) & 0xFFFFFFFF), ((TIMER1n_ADR = (TIMER1n_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER1n_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER1n_BDR  -------------------------------
+// SVD Line: 15235
+
+unsigned int TIMER1n_BDR __AT (0x51000008);
+
+
+
+// ------------------------------  Field Item: TIMER1n_BDR_BDATA  ---------------------------------
+// SVD Line: 15244
+
+//  <item> SFDITEM_FIELD__TIMER1n_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x51000008) TIMER1n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER1n_BDR >> 0) & 0xFFFF), ((TIMER1n_BDR = (TIMER1n_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER1n_BDR  ----------------------------------
+// SVD Line: 15235
+
+//  <rtree> SFDITEM_REG__TIMER1n_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x51000008) TIMER1n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER1n_BDR >> 0) & 0xFFFFFFFF), ((TIMER1n_BDR = (TIMER1n_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER1n_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER1n_CAPDR  ------------------------------
+// SVD Line: 15252
+
+unsigned int TIMER1n_CAPDR __AT (0x5100000C);
+
+
+
+// -----------------------------  Field Item: TIMER1n_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15261
+
+//  <item> SFDITEM_FIELD__TIMER1n_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x5100000C) TIMER1n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER1n_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER1n_CAPDR  ---------------------------------
+// SVD Line: 15252
+
+//  <rtree> SFDITEM_REG__TIMER1n_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x5100000C) TIMER1n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER1n_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER1n_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER1n_PREDR  ------------------------------
+// SVD Line: 15269
+
+unsigned int TIMER1n_PREDR __AT (0x51000010);
+
+
+
+// -----------------------------  Field Item: TIMER1n_PREDR_PRED  ---------------------------------
+// SVD Line: 15278
+
+//  <item> SFDITEM_FIELD__TIMER1n_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x51000010) TIMER1n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER1n_PREDR >> 0) & 0xFFF), ((TIMER1n_PREDR = (TIMER1n_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER1n_PREDR  ---------------------------------
+// SVD Line: 15269
+
+//  <rtree> SFDITEM_REG__TIMER1n_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x51000010) TIMER1n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER1n_PREDR >> 0) & 0xFFFFFFFF), ((TIMER1n_PREDR = (TIMER1n_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER1n_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER1n_CNT  -------------------------------
+// SVD Line: 15286
+
+unsigned int TIMER1n_CNT __AT (0x51000014);
+
+
+
+// -------------------------------  Field Item: TIMER1n_CNT_CNT  ----------------------------------
+// SVD Line: 15295
+
+//  <item> SFDITEM_FIELD__TIMER1n_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x51000014) TIMER1n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER1n_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER1n_CNT  ----------------------------------
+// SVD Line: 15286
+
+//  <rtree> SFDITEM_REG__TIMER1n_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x51000014) TIMER1n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER1n_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER1n_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER1n  ------------------------------------
+// SVD Line: 15121
+
+//  <view> TIMER1n
+//    <name> TIMER1n </name>
+//    <item> SFDITEM_REG__TIMER1n_CR </item>
+//    <item> SFDITEM_REG__TIMER1n_ADR </item>
+//    <item> SFDITEM_REG__TIMER1n_BDR </item>
+//    <item> SFDITEM_REG__TIMER1n_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER1n_PREDR </item>
+//    <item> SFDITEM_REG__TIMER1n_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER10_CR  -------------------------------
+// SVD Line: 15135
+
+unsigned int TIMER10_CR __AT (0x40002100);
+
+
+
+// ------------------------------  Field Item: TIMER10_CR_T1nEN  ----------------------------------
+// SVD Line: 15144
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nEN
+//    <name> T1nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002100) TIMER1n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.15..15> T1nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER10_CR_T1nCLK  ---------------------------------
+// SVD Line: 15150
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nCLK
+//    <name> T1nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002100) TIMER1n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.14..14> T1nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER10_CR_T1nMS  ----------------------------------
+// SVD Line: 15156
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nMS
+//    <name> T1nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002100) TIMER1n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER10_CR >> 12) & 0x3), ((TIMER10_CR = (TIMER10_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER10_CR_T1nECE  ---------------------------------
+// SVD Line: 15162
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nECE
+//    <name> T1nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002100) TIMER1n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.11..11> T1nECE
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER10_CR_T1nOPOL  ---------------------------------
+// SVD Line: 15168
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nOPOL
+//    <name> T1nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002100) TIMER1n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.8..8> T1nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER10_CR_T1nCPOL  ---------------------------------
+// SVD Line: 15174
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nCPOL
+//    <name> T1nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002100) TIMER1n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER10_CR >> 6) & 0x3), ((TIMER10_CR = (TIMER10_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER10_CR_T1nMIEN  ---------------------------------
+// SVD Line: 15180
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nMIEN
+//    <name> T1nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002100) TIMER1n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.5..5> T1nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER10_CR_T1nCIEN  ---------------------------------
+// SVD Line: 15186
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nCIEN
+//    <name> T1nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002100) TIMER1n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.4..4> T1nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER10_CR_T1nMIFLAG  --------------------------------
+// SVD Line: 15192
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nMIFLAG
+//    <name> T1nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002100) TIMER1n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.3..3> T1nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER10_CR_T1nCIFLAG  --------------------------------
+// SVD Line: 15198
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nCIFLAG
+//    <name> T1nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002100) TIMER1n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.2..2> T1nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER10_CR_T1nPAU  ---------------------------------
+// SVD Line: 15204
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nPAU
+//    <name> T1nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002100) TIMER1n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.1..1> T1nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER10_CR_T1nCLR  ---------------------------------
+// SVD Line: 15210
+
+//  <item> SFDITEM_FIELD__TIMER10_CR_T1nCLR
+//    <name> T1nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002100) TIMER1n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER10_CR ) </loc>
+//      <o.0..0> T1nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER10_CR  -----------------------------------
+// SVD Line: 15135
+
+//  <rtree> SFDITEM_REG__TIMER10_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002100) TIMER1n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER10_CR >> 0) & 0xFFFFFFFF), ((TIMER10_CR = (TIMER10_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nEN </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nMS </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nECE </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER10_CR_T1nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER10_ADR  -------------------------------
+// SVD Line: 15218
+
+unsigned int TIMER10_ADR __AT (0x40002104);
+
+
+
+// ------------------------------  Field Item: TIMER10_ADR_ADATA  ---------------------------------
+// SVD Line: 15227
+
+//  <item> SFDITEM_FIELD__TIMER10_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002104) TIMER1n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER10_ADR >> 0) & 0xFFFF), ((TIMER10_ADR = (TIMER10_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER10_ADR  ----------------------------------
+// SVD Line: 15218
+
+//  <rtree> SFDITEM_REG__TIMER10_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002104) TIMER1n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER10_ADR >> 0) & 0xFFFFFFFF), ((TIMER10_ADR = (TIMER10_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER10_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER10_BDR  -------------------------------
+// SVD Line: 15235
+
+unsigned int TIMER10_BDR __AT (0x40002108);
+
+
+
+// ------------------------------  Field Item: TIMER10_BDR_BDATA  ---------------------------------
+// SVD Line: 15244
+
+//  <item> SFDITEM_FIELD__TIMER10_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002108) TIMER1n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER10_BDR >> 0) & 0xFFFF), ((TIMER10_BDR = (TIMER10_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER10_BDR  ----------------------------------
+// SVD Line: 15235
+
+//  <rtree> SFDITEM_REG__TIMER10_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002108) TIMER1n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER10_BDR >> 0) & 0xFFFFFFFF), ((TIMER10_BDR = (TIMER10_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER10_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER10_CAPDR  ------------------------------
+// SVD Line: 15252
+
+unsigned int TIMER10_CAPDR __AT (0x4000210C);
+
+
+
+// -----------------------------  Field Item: TIMER10_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15261
+
+//  <item> SFDITEM_FIELD__TIMER10_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x4000210C) TIMER1n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER10_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER10_CAPDR  ---------------------------------
+// SVD Line: 15252
+
+//  <rtree> SFDITEM_REG__TIMER10_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000210C) TIMER1n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER10_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER10_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER10_PREDR  ------------------------------
+// SVD Line: 15269
+
+unsigned int TIMER10_PREDR __AT (0x40002110);
+
+
+
+// -----------------------------  Field Item: TIMER10_PREDR_PRED  ---------------------------------
+// SVD Line: 15278
+
+//  <item> SFDITEM_FIELD__TIMER10_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002110) TIMER1n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER10_PREDR >> 0) & 0xFFF), ((TIMER10_PREDR = (TIMER10_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER10_PREDR  ---------------------------------
+// SVD Line: 15269
+
+//  <rtree> SFDITEM_REG__TIMER10_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002110) TIMER1n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER10_PREDR >> 0) & 0xFFFFFFFF), ((TIMER10_PREDR = (TIMER10_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER10_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER10_CNT  -------------------------------
+// SVD Line: 15286
+
+unsigned int TIMER10_CNT __AT (0x40002114);
+
+
+
+// -------------------------------  Field Item: TIMER10_CNT_CNT  ----------------------------------
+// SVD Line: 15295
+
+//  <item> SFDITEM_FIELD__TIMER10_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002114) TIMER1n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER10_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER10_CNT  ----------------------------------
+// SVD Line: 15286
+
+//  <rtree> SFDITEM_REG__TIMER10_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002114) TIMER1n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER10_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER10_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER10  ------------------------------------
+// SVD Line: 15305
+
+//  <view> TIMER10
+//    <name> TIMER10 </name>
+//    <item> SFDITEM_REG__TIMER10_CR </item>
+//    <item> SFDITEM_REG__TIMER10_ADR </item>
+//    <item> SFDITEM_REG__TIMER10_BDR </item>
+//    <item> SFDITEM_REG__TIMER10_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER10_PREDR </item>
+//    <item> SFDITEM_REG__TIMER10_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER11_CR  -------------------------------
+// SVD Line: 15135
+
+unsigned int TIMER11_CR __AT (0x40002200);
+
+
+
+// ------------------------------  Field Item: TIMER11_CR_T1nEN  ----------------------------------
+// SVD Line: 15144
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nEN
+//    <name> T1nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002200) TIMER1n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.15..15> T1nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER11_CR_T1nCLK  ---------------------------------
+// SVD Line: 15150
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nCLK
+//    <name> T1nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002200) TIMER1n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.14..14> T1nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER11_CR_T1nMS  ----------------------------------
+// SVD Line: 15156
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nMS
+//    <name> T1nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002200) TIMER1n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER11_CR >> 12) & 0x3), ((TIMER11_CR = (TIMER11_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER11_CR_T1nECE  ---------------------------------
+// SVD Line: 15162
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nECE
+//    <name> T1nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002200) TIMER1n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.11..11> T1nECE
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER11_CR_T1nOPOL  ---------------------------------
+// SVD Line: 15168
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nOPOL
+//    <name> T1nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002200) TIMER1n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.8..8> T1nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER11_CR_T1nCPOL  ---------------------------------
+// SVD Line: 15174
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nCPOL
+//    <name> T1nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002200) TIMER1n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER11_CR >> 6) & 0x3), ((TIMER11_CR = (TIMER11_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER11_CR_T1nMIEN  ---------------------------------
+// SVD Line: 15180
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nMIEN
+//    <name> T1nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002200) TIMER1n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.5..5> T1nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER11_CR_T1nCIEN  ---------------------------------
+// SVD Line: 15186
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nCIEN
+//    <name> T1nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002200) TIMER1n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.4..4> T1nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER11_CR_T1nMIFLAG  --------------------------------
+// SVD Line: 15192
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nMIFLAG
+//    <name> T1nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002200) TIMER1n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.3..3> T1nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER11_CR_T1nCIFLAG  --------------------------------
+// SVD Line: 15198
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nCIFLAG
+//    <name> T1nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002200) TIMER1n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.2..2> T1nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER11_CR_T1nPAU  ---------------------------------
+// SVD Line: 15204
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nPAU
+//    <name> T1nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002200) TIMER1n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.1..1> T1nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER11_CR_T1nCLR  ---------------------------------
+// SVD Line: 15210
+
+//  <item> SFDITEM_FIELD__TIMER11_CR_T1nCLR
+//    <name> T1nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002200) TIMER1n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER11_CR ) </loc>
+//      <o.0..0> T1nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER11_CR  -----------------------------------
+// SVD Line: 15135
+
+//  <rtree> SFDITEM_REG__TIMER11_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002200) TIMER1n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER11_CR >> 0) & 0xFFFFFFFF), ((TIMER11_CR = (TIMER11_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nEN </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nMS </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nECE </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER11_CR_T1nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER11_ADR  -------------------------------
+// SVD Line: 15218
+
+unsigned int TIMER11_ADR __AT (0x40002204);
+
+
+
+// ------------------------------  Field Item: TIMER11_ADR_ADATA  ---------------------------------
+// SVD Line: 15227
+
+//  <item> SFDITEM_FIELD__TIMER11_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002204) TIMER1n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER11_ADR >> 0) & 0xFFFF), ((TIMER11_ADR = (TIMER11_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER11_ADR  ----------------------------------
+// SVD Line: 15218
+
+//  <rtree> SFDITEM_REG__TIMER11_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002204) TIMER1n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER11_ADR >> 0) & 0xFFFFFFFF), ((TIMER11_ADR = (TIMER11_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER11_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER11_BDR  -------------------------------
+// SVD Line: 15235
+
+unsigned int TIMER11_BDR __AT (0x40002208);
+
+
+
+// ------------------------------  Field Item: TIMER11_BDR_BDATA  ---------------------------------
+// SVD Line: 15244
+
+//  <item> SFDITEM_FIELD__TIMER11_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002208) TIMER1n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER11_BDR >> 0) & 0xFFFF), ((TIMER11_BDR = (TIMER11_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER11_BDR  ----------------------------------
+// SVD Line: 15235
+
+//  <rtree> SFDITEM_REG__TIMER11_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002208) TIMER1n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER11_BDR >> 0) & 0xFFFFFFFF), ((TIMER11_BDR = (TIMER11_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER11_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER11_CAPDR  ------------------------------
+// SVD Line: 15252
+
+unsigned int TIMER11_CAPDR __AT (0x4000220C);
+
+
+
+// -----------------------------  Field Item: TIMER11_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15261
+
+//  <item> SFDITEM_FIELD__TIMER11_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x4000220C) TIMER1n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER11_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER11_CAPDR  ---------------------------------
+// SVD Line: 15252
+
+//  <rtree> SFDITEM_REG__TIMER11_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000220C) TIMER1n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER11_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER11_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER11_PREDR  ------------------------------
+// SVD Line: 15269
+
+unsigned int TIMER11_PREDR __AT (0x40002210);
+
+
+
+// -----------------------------  Field Item: TIMER11_PREDR_PRED  ---------------------------------
+// SVD Line: 15278
+
+//  <item> SFDITEM_FIELD__TIMER11_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002210) TIMER1n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER11_PREDR >> 0) & 0xFFF), ((TIMER11_PREDR = (TIMER11_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER11_PREDR  ---------------------------------
+// SVD Line: 15269
+
+//  <rtree> SFDITEM_REG__TIMER11_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002210) TIMER1n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER11_PREDR >> 0) & 0xFFFFFFFF), ((TIMER11_PREDR = (TIMER11_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER11_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER11_CNT  -------------------------------
+// SVD Line: 15286
+
+unsigned int TIMER11_CNT __AT (0x40002214);
+
+
+
+// -------------------------------  Field Item: TIMER11_CNT_CNT  ----------------------------------
+// SVD Line: 15295
+
+//  <item> SFDITEM_FIELD__TIMER11_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002214) TIMER1n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER11_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER11_CNT  ----------------------------------
+// SVD Line: 15286
+
+//  <rtree> SFDITEM_REG__TIMER11_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002214) TIMER1n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER11_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER11_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER11  ------------------------------------
+// SVD Line: 15324
+
+//  <view> TIMER11
+//    <name> TIMER11 </name>
+//    <item> SFDITEM_REG__TIMER11_CR </item>
+//    <item> SFDITEM_REG__TIMER11_ADR </item>
+//    <item> SFDITEM_REG__TIMER11_BDR </item>
+//    <item> SFDITEM_REG__TIMER11_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER11_PREDR </item>
+//    <item> SFDITEM_REG__TIMER11_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER12_CR  -------------------------------
+// SVD Line: 15135
+
+unsigned int TIMER12_CR __AT (0x40002300);
+
+
+
+// ------------------------------  Field Item: TIMER12_CR_T1nEN  ----------------------------------
+// SVD Line: 15144
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nEN
+//    <name> T1nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002300) TIMER1n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.15..15> T1nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER12_CR_T1nCLK  ---------------------------------
+// SVD Line: 15150
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nCLK
+//    <name> T1nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002300) TIMER1n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.14..14> T1nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER12_CR_T1nMS  ----------------------------------
+// SVD Line: 15156
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nMS
+//    <name> T1nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002300) TIMER1n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER12_CR >> 12) & 0x3), ((TIMER12_CR = (TIMER12_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER12_CR_T1nECE  ---------------------------------
+// SVD Line: 15162
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nECE
+//    <name> T1nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002300) TIMER1n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.11..11> T1nECE
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER12_CR_T1nOPOL  ---------------------------------
+// SVD Line: 15168
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nOPOL
+//    <name> T1nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002300) TIMER1n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.8..8> T1nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER12_CR_T1nCPOL  ---------------------------------
+// SVD Line: 15174
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nCPOL
+//    <name> T1nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002300) TIMER1n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER12_CR >> 6) & 0x3), ((TIMER12_CR = (TIMER12_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER12_CR_T1nMIEN  ---------------------------------
+// SVD Line: 15180
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nMIEN
+//    <name> T1nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002300) TIMER1n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.5..5> T1nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER12_CR_T1nCIEN  ---------------------------------
+// SVD Line: 15186
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nCIEN
+//    <name> T1nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002300) TIMER1n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.4..4> T1nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER12_CR_T1nMIFLAG  --------------------------------
+// SVD Line: 15192
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nMIFLAG
+//    <name> T1nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002300) TIMER1n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.3..3> T1nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER12_CR_T1nCIFLAG  --------------------------------
+// SVD Line: 15198
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nCIFLAG
+//    <name> T1nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002300) TIMER1n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.2..2> T1nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER12_CR_T1nPAU  ---------------------------------
+// SVD Line: 15204
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nPAU
+//    <name> T1nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002300) TIMER1n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.1..1> T1nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER12_CR_T1nCLR  ---------------------------------
+// SVD Line: 15210
+
+//  <item> SFDITEM_FIELD__TIMER12_CR_T1nCLR
+//    <name> T1nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002300) TIMER1n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER12_CR ) </loc>
+//      <o.0..0> T1nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER12_CR  -----------------------------------
+// SVD Line: 15135
+
+//  <rtree> SFDITEM_REG__TIMER12_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002300) TIMER1n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER12_CR >> 0) & 0xFFFFFFFF), ((TIMER12_CR = (TIMER12_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nEN </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nMS </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nECE </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER12_CR_T1nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER12_ADR  -------------------------------
+// SVD Line: 15218
+
+unsigned int TIMER12_ADR __AT (0x40002304);
+
+
+
+// ------------------------------  Field Item: TIMER12_ADR_ADATA  ---------------------------------
+// SVD Line: 15227
+
+//  <item> SFDITEM_FIELD__TIMER12_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002304) TIMER1n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER12_ADR >> 0) & 0xFFFF), ((TIMER12_ADR = (TIMER12_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER12_ADR  ----------------------------------
+// SVD Line: 15218
+
+//  <rtree> SFDITEM_REG__TIMER12_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002304) TIMER1n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER12_ADR >> 0) & 0xFFFFFFFF), ((TIMER12_ADR = (TIMER12_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER12_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER12_BDR  -------------------------------
+// SVD Line: 15235
+
+unsigned int TIMER12_BDR __AT (0x40002308);
+
+
+
+// ------------------------------  Field Item: TIMER12_BDR_BDATA  ---------------------------------
+// SVD Line: 15244
+
+//  <item> SFDITEM_FIELD__TIMER12_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002308) TIMER1n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER12_BDR >> 0) & 0xFFFF), ((TIMER12_BDR = (TIMER12_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER12_BDR  ----------------------------------
+// SVD Line: 15235
+
+//  <rtree> SFDITEM_REG__TIMER12_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002308) TIMER1n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER12_BDR >> 0) & 0xFFFFFFFF), ((TIMER12_BDR = (TIMER12_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER12_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER12_CAPDR  ------------------------------
+// SVD Line: 15252
+
+unsigned int TIMER12_CAPDR __AT (0x4000230C);
+
+
+
+// -----------------------------  Field Item: TIMER12_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15261
+
+//  <item> SFDITEM_FIELD__TIMER12_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x4000230C) TIMER1n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER12_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER12_CAPDR  ---------------------------------
+// SVD Line: 15252
+
+//  <rtree> SFDITEM_REG__TIMER12_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000230C) TIMER1n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER12_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER12_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER12_PREDR  ------------------------------
+// SVD Line: 15269
+
+unsigned int TIMER12_PREDR __AT (0x40002310);
+
+
+
+// -----------------------------  Field Item: TIMER12_PREDR_PRED  ---------------------------------
+// SVD Line: 15278
+
+//  <item> SFDITEM_FIELD__TIMER12_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002310) TIMER1n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER12_PREDR >> 0) & 0xFFF), ((TIMER12_PREDR = (TIMER12_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER12_PREDR  ---------------------------------
+// SVD Line: 15269
+
+//  <rtree> SFDITEM_REG__TIMER12_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002310) TIMER1n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER12_PREDR >> 0) & 0xFFFFFFFF), ((TIMER12_PREDR = (TIMER12_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER12_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER12_CNT  -------------------------------
+// SVD Line: 15286
+
+unsigned int TIMER12_CNT __AT (0x40002314);
+
+
+
+// -------------------------------  Field Item: TIMER12_CNT_CNT  ----------------------------------
+// SVD Line: 15295
+
+//  <item> SFDITEM_FIELD__TIMER12_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002314) TIMER1n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER12_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER12_CNT  ----------------------------------
+// SVD Line: 15286
+
+//  <rtree> SFDITEM_REG__TIMER12_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002314) TIMER1n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER12_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER12_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER12  ------------------------------------
+// SVD Line: 15343
+
+//  <view> TIMER12
+//    <name> TIMER12 </name>
+//    <item> SFDITEM_REG__TIMER12_CR </item>
+//    <item> SFDITEM_REG__TIMER12_ADR </item>
+//    <item> SFDITEM_REG__TIMER12_BDR </item>
+//    <item> SFDITEM_REG__TIMER12_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER12_PREDR </item>
+//    <item> SFDITEM_REG__TIMER12_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER13_CR  -------------------------------
+// SVD Line: 15135
+
+unsigned int TIMER13_CR __AT (0x40002700);
+
+
+
+// ------------------------------  Field Item: TIMER13_CR_T1nEN  ----------------------------------
+// SVD Line: 15144
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nEN
+//    <name> T1nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002700) TIMER1n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.15..15> T1nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER13_CR_T1nCLK  ---------------------------------
+// SVD Line: 15150
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nCLK
+//    <name> T1nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002700) TIMER1n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.14..14> T1nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER13_CR_T1nMS  ----------------------------------
+// SVD Line: 15156
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nMS
+//    <name> T1nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002700) TIMER1n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER13_CR >> 12) & 0x3), ((TIMER13_CR = (TIMER13_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER13_CR_T1nECE  ---------------------------------
+// SVD Line: 15162
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nECE
+//    <name> T1nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002700) TIMER1n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.11..11> T1nECE
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER13_CR_T1nOPOL  ---------------------------------
+// SVD Line: 15168
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nOPOL
+//    <name> T1nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002700) TIMER1n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.8..8> T1nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER13_CR_T1nCPOL  ---------------------------------
+// SVD Line: 15174
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nCPOL
+//    <name> T1nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002700) TIMER1n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER13_CR >> 6) & 0x3), ((TIMER13_CR = (TIMER13_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER13_CR_T1nMIEN  ---------------------------------
+// SVD Line: 15180
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nMIEN
+//    <name> T1nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002700) TIMER1n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.5..5> T1nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER13_CR_T1nCIEN  ---------------------------------
+// SVD Line: 15186
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nCIEN
+//    <name> T1nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002700) TIMER1n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.4..4> T1nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER13_CR_T1nMIFLAG  --------------------------------
+// SVD Line: 15192
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nMIFLAG
+//    <name> T1nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002700) TIMER1n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.3..3> T1nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER13_CR_T1nCIFLAG  --------------------------------
+// SVD Line: 15198
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nCIFLAG
+//    <name> T1nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002700) TIMER1n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.2..2> T1nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER13_CR_T1nPAU  ---------------------------------
+// SVD Line: 15204
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nPAU
+//    <name> T1nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002700) TIMER1n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.1..1> T1nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER13_CR_T1nCLR  ---------------------------------
+// SVD Line: 15210
+
+//  <item> SFDITEM_FIELD__TIMER13_CR_T1nCLR
+//    <name> T1nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002700) TIMER1n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER13_CR ) </loc>
+//      <o.0..0> T1nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER13_CR  -----------------------------------
+// SVD Line: 15135
+
+//  <rtree> SFDITEM_REG__TIMER13_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002700) TIMER1n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER13_CR >> 0) & 0xFFFFFFFF), ((TIMER13_CR = (TIMER13_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nEN </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nMS </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nECE </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER13_CR_T1nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER13_ADR  -------------------------------
+// SVD Line: 15218
+
+unsigned int TIMER13_ADR __AT (0x40002704);
+
+
+
+// ------------------------------  Field Item: TIMER13_ADR_ADATA  ---------------------------------
+// SVD Line: 15227
+
+//  <item> SFDITEM_FIELD__TIMER13_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002704) TIMER1n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER13_ADR >> 0) & 0xFFFF), ((TIMER13_ADR = (TIMER13_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER13_ADR  ----------------------------------
+// SVD Line: 15218
+
+//  <rtree> SFDITEM_REG__TIMER13_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002704) TIMER1n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER13_ADR >> 0) & 0xFFFFFFFF), ((TIMER13_ADR = (TIMER13_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER13_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER13_BDR  -------------------------------
+// SVD Line: 15235
+
+unsigned int TIMER13_BDR __AT (0x40002708);
+
+
+
+// ------------------------------  Field Item: TIMER13_BDR_BDATA  ---------------------------------
+// SVD Line: 15244
+
+//  <item> SFDITEM_FIELD__TIMER13_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002708) TIMER1n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER13_BDR >> 0) & 0xFFFF), ((TIMER13_BDR = (TIMER13_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER13_BDR  ----------------------------------
+// SVD Line: 15235
+
+//  <rtree> SFDITEM_REG__TIMER13_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002708) TIMER1n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER13_BDR >> 0) & 0xFFFFFFFF), ((TIMER13_BDR = (TIMER13_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER13_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER13_CAPDR  ------------------------------
+// SVD Line: 15252
+
+unsigned int TIMER13_CAPDR __AT (0x4000270C);
+
+
+
+// -----------------------------  Field Item: TIMER13_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15261
+
+//  <item> SFDITEM_FIELD__TIMER13_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x4000270C) TIMER1n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER13_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER13_CAPDR  ---------------------------------
+// SVD Line: 15252
+
+//  <rtree> SFDITEM_REG__TIMER13_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000270C) TIMER1n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER13_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER13_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER13_PREDR  ------------------------------
+// SVD Line: 15269
+
+unsigned int TIMER13_PREDR __AT (0x40002710);
+
+
+
+// -----------------------------  Field Item: TIMER13_PREDR_PRED  ---------------------------------
+// SVD Line: 15278
+
+//  <item> SFDITEM_FIELD__TIMER13_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002710) TIMER1n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER13_PREDR >> 0) & 0xFFF), ((TIMER13_PREDR = (TIMER13_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER13_PREDR  ---------------------------------
+// SVD Line: 15269
+
+//  <rtree> SFDITEM_REG__TIMER13_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002710) TIMER1n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER13_PREDR >> 0) & 0xFFFFFFFF), ((TIMER13_PREDR = (TIMER13_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER13_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER13_CNT  -------------------------------
+// SVD Line: 15286
+
+unsigned int TIMER13_CNT __AT (0x40002714);
+
+
+
+// -------------------------------  Field Item: TIMER13_CNT_CNT  ----------------------------------
+// SVD Line: 15295
+
+//  <item> SFDITEM_FIELD__TIMER13_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002714) TIMER1n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER13_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER13_CNT  ----------------------------------
+// SVD Line: 15286
+
+//  <rtree> SFDITEM_REG__TIMER13_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002714) TIMER1n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER13_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER13_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER13  ------------------------------------
+// SVD Line: 15362
+
+//  <view> TIMER13
+//    <name> TIMER13 </name>
+//    <item> SFDITEM_REG__TIMER13_CR </item>
+//    <item> SFDITEM_REG__TIMER13_ADR </item>
+//    <item> SFDITEM_REG__TIMER13_BDR </item>
+//    <item> SFDITEM_REG__TIMER13_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER13_PREDR </item>
+//    <item> SFDITEM_REG__TIMER13_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER14_CR  -------------------------------
+// SVD Line: 15135
+
+unsigned int TIMER14_CR __AT (0x40002800);
+
+
+
+// ------------------------------  Field Item: TIMER14_CR_T1nEN  ----------------------------------
+// SVD Line: 15144
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nEN
+//    <name> T1nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002800) TIMER1n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.15..15> T1nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER14_CR_T1nCLK  ---------------------------------
+// SVD Line: 15150
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nCLK
+//    <name> T1nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002800) TIMER1n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.14..14> T1nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER14_CR_T1nMS  ----------------------------------
+// SVD Line: 15156
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nMS
+//    <name> T1nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002800) TIMER1n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER14_CR >> 12) & 0x3), ((TIMER14_CR = (TIMER14_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER14_CR_T1nECE  ---------------------------------
+// SVD Line: 15162
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nECE
+//    <name> T1nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002800) TIMER1n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.11..11> T1nECE
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER14_CR_T1nOPOL  ---------------------------------
+// SVD Line: 15168
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nOPOL
+//    <name> T1nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002800) TIMER1n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.8..8> T1nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER14_CR_T1nCPOL  ---------------------------------
+// SVD Line: 15174
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nCPOL
+//    <name> T1nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002800) TIMER1n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER14_CR >> 6) & 0x3), ((TIMER14_CR = (TIMER14_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER14_CR_T1nMIEN  ---------------------------------
+// SVD Line: 15180
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nMIEN
+//    <name> T1nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002800) TIMER1n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.5..5> T1nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER14_CR_T1nCIEN  ---------------------------------
+// SVD Line: 15186
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nCIEN
+//    <name> T1nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002800) TIMER1n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.4..4> T1nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER14_CR_T1nMIFLAG  --------------------------------
+// SVD Line: 15192
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nMIFLAG
+//    <name> T1nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002800) TIMER1n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.3..3> T1nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER14_CR_T1nCIFLAG  --------------------------------
+// SVD Line: 15198
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nCIFLAG
+//    <name> T1nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002800) TIMER1n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.2..2> T1nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER14_CR_T1nPAU  ---------------------------------
+// SVD Line: 15204
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nPAU
+//    <name> T1nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002800) TIMER1n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.1..1> T1nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER14_CR_T1nCLR  ---------------------------------
+// SVD Line: 15210
+
+//  <item> SFDITEM_FIELD__TIMER14_CR_T1nCLR
+//    <name> T1nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002800) TIMER1n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER14_CR ) </loc>
+//      <o.0..0> T1nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER14_CR  -----------------------------------
+// SVD Line: 15135
+
+//  <rtree> SFDITEM_REG__TIMER14_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002800) TIMER1n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER14_CR >> 0) & 0xFFFFFFFF), ((TIMER14_CR = (TIMER14_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nEN </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nMS </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nECE </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER14_CR_T1nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER14_ADR  -------------------------------
+// SVD Line: 15218
+
+unsigned int TIMER14_ADR __AT (0x40002804);
+
+
+
+// ------------------------------  Field Item: TIMER14_ADR_ADATA  ---------------------------------
+// SVD Line: 15227
+
+//  <item> SFDITEM_FIELD__TIMER14_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002804) TIMER1n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER14_ADR >> 0) & 0xFFFF), ((TIMER14_ADR = (TIMER14_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER14_ADR  ----------------------------------
+// SVD Line: 15218
+
+//  <rtree> SFDITEM_REG__TIMER14_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002804) TIMER1n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER14_ADR >> 0) & 0xFFFFFFFF), ((TIMER14_ADR = (TIMER14_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER14_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER14_BDR  -------------------------------
+// SVD Line: 15235
+
+unsigned int TIMER14_BDR __AT (0x40002808);
+
+
+
+// ------------------------------  Field Item: TIMER14_BDR_BDATA  ---------------------------------
+// SVD Line: 15244
+
+//  <item> SFDITEM_FIELD__TIMER14_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002808) TIMER1n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER14_BDR >> 0) & 0xFFFF), ((TIMER14_BDR = (TIMER14_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER14_BDR  ----------------------------------
+// SVD Line: 15235
+
+//  <rtree> SFDITEM_REG__TIMER14_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002808) TIMER1n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER14_BDR >> 0) & 0xFFFFFFFF), ((TIMER14_BDR = (TIMER14_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER14_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER14_CAPDR  ------------------------------
+// SVD Line: 15252
+
+unsigned int TIMER14_CAPDR __AT (0x4000280C);
+
+
+
+// -----------------------------  Field Item: TIMER14_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15261
+
+//  <item> SFDITEM_FIELD__TIMER14_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x4000280C) TIMER1n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER14_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER14_CAPDR  ---------------------------------
+// SVD Line: 15252
+
+//  <rtree> SFDITEM_REG__TIMER14_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000280C) TIMER1n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER14_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER14_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER14_PREDR  ------------------------------
+// SVD Line: 15269
+
+unsigned int TIMER14_PREDR __AT (0x40002810);
+
+
+
+// -----------------------------  Field Item: TIMER14_PREDR_PRED  ---------------------------------
+// SVD Line: 15278
+
+//  <item> SFDITEM_FIELD__TIMER14_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002810) TIMER1n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER14_PREDR >> 0) & 0xFFF), ((TIMER14_PREDR = (TIMER14_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER14_PREDR  ---------------------------------
+// SVD Line: 15269
+
+//  <rtree> SFDITEM_REG__TIMER14_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002810) TIMER1n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER14_PREDR >> 0) & 0xFFFFFFFF), ((TIMER14_PREDR = (TIMER14_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER14_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER14_CNT  -------------------------------
+// SVD Line: 15286
+
+unsigned int TIMER14_CNT __AT (0x40002814);
+
+
+
+// -------------------------------  Field Item: TIMER14_CNT_CNT  ----------------------------------
+// SVD Line: 15295
+
+//  <item> SFDITEM_FIELD__TIMER14_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002814) TIMER1n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER14_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER14_CNT  ----------------------------------
+// SVD Line: 15286
+
+//  <rtree> SFDITEM_REG__TIMER14_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002814) TIMER1n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER14_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER14_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER14  ------------------------------------
+// SVD Line: 15381
+
+//  <view> TIMER14
+//    <name> TIMER14 </name>
+//    <item> SFDITEM_REG__TIMER14_CR </item>
+//    <item> SFDITEM_REG__TIMER14_ADR </item>
+//    <item> SFDITEM_REG__TIMER14_BDR </item>
+//    <item> SFDITEM_REG__TIMER14_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER14_PREDR </item>
+//    <item> SFDITEM_REG__TIMER14_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER15_CR  -------------------------------
+// SVD Line: 15135
+
+unsigned int TIMER15_CR __AT (0x40002900);
+
+
+
+// ------------------------------  Field Item: TIMER15_CR_T1nEN  ----------------------------------
+// SVD Line: 15144
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nEN
+//    <name> T1nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002900) TIMER1n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.15..15> T1nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER15_CR_T1nCLK  ---------------------------------
+// SVD Line: 15150
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nCLK
+//    <name> T1nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002900) TIMER1n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.14..14> T1nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER15_CR_T1nMS  ----------------------------------
+// SVD Line: 15156
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nMS
+//    <name> T1nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002900) TIMER1n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER15_CR >> 12) & 0x3), ((TIMER15_CR = (TIMER15_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER15_CR_T1nECE  ---------------------------------
+// SVD Line: 15162
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nECE
+//    <name> T1nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002900) TIMER1n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.11..11> T1nECE
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER15_CR_T1nOPOL  ---------------------------------
+// SVD Line: 15168
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nOPOL
+//    <name> T1nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002900) TIMER1n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.8..8> T1nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER15_CR_T1nCPOL  ---------------------------------
+// SVD Line: 15174
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nCPOL
+//    <name> T1nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002900) TIMER1n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER15_CR >> 6) & 0x3), ((TIMER15_CR = (TIMER15_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER15_CR_T1nMIEN  ---------------------------------
+// SVD Line: 15180
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nMIEN
+//    <name> T1nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002900) TIMER1n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.5..5> T1nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER15_CR_T1nCIEN  ---------------------------------
+// SVD Line: 15186
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nCIEN
+//    <name> T1nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002900) TIMER1n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.4..4> T1nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER15_CR_T1nMIFLAG  --------------------------------
+// SVD Line: 15192
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nMIFLAG
+//    <name> T1nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002900) TIMER1n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.3..3> T1nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER15_CR_T1nCIFLAG  --------------------------------
+// SVD Line: 15198
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nCIFLAG
+//    <name> T1nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002900) TIMER1n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.2..2> T1nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER15_CR_T1nPAU  ---------------------------------
+// SVD Line: 15204
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nPAU
+//    <name> T1nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002900) TIMER1n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.1..1> T1nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER15_CR_T1nCLR  ---------------------------------
+// SVD Line: 15210
+
+//  <item> SFDITEM_FIELD__TIMER15_CR_T1nCLR
+//    <name> T1nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002900) TIMER1n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER15_CR ) </loc>
+//      <o.0..0> T1nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER15_CR  -----------------------------------
+// SVD Line: 15135
+
+//  <rtree> SFDITEM_REG__TIMER15_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002900) TIMER1n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER15_CR >> 0) & 0xFFFFFFFF), ((TIMER15_CR = (TIMER15_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nEN </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nMS </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nECE </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER15_CR_T1nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER15_ADR  -------------------------------
+// SVD Line: 15218
+
+unsigned int TIMER15_ADR __AT (0x40002904);
+
+
+
+// ------------------------------  Field Item: TIMER15_ADR_ADATA  ---------------------------------
+// SVD Line: 15227
+
+//  <item> SFDITEM_FIELD__TIMER15_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002904) TIMER1n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER15_ADR >> 0) & 0xFFFF), ((TIMER15_ADR = (TIMER15_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER15_ADR  ----------------------------------
+// SVD Line: 15218
+
+//  <rtree> SFDITEM_REG__TIMER15_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002904) TIMER1n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER15_ADR >> 0) & 0xFFFFFFFF), ((TIMER15_ADR = (TIMER15_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER15_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER15_BDR  -------------------------------
+// SVD Line: 15235
+
+unsigned int TIMER15_BDR __AT (0x40002908);
+
+
+
+// ------------------------------  Field Item: TIMER15_BDR_BDATA  ---------------------------------
+// SVD Line: 15244
+
+//  <item> SFDITEM_FIELD__TIMER15_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002908) TIMER1n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER15_BDR >> 0) & 0xFFFF), ((TIMER15_BDR = (TIMER15_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER15_BDR  ----------------------------------
+// SVD Line: 15235
+
+//  <rtree> SFDITEM_REG__TIMER15_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002908) TIMER1n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER15_BDR >> 0) & 0xFFFFFFFF), ((TIMER15_BDR = (TIMER15_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER15_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER15_CAPDR  ------------------------------
+// SVD Line: 15252
+
+unsigned int TIMER15_CAPDR __AT (0x4000290C);
+
+
+
+// -----------------------------  Field Item: TIMER15_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15261
+
+//  <item> SFDITEM_FIELD__TIMER15_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x4000290C) TIMER1n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER15_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER15_CAPDR  ---------------------------------
+// SVD Line: 15252
+
+//  <rtree> SFDITEM_REG__TIMER15_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000290C) TIMER1n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER15_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER15_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER15_PREDR  ------------------------------
+// SVD Line: 15269
+
+unsigned int TIMER15_PREDR __AT (0x40002910);
+
+
+
+// -----------------------------  Field Item: TIMER15_PREDR_PRED  ---------------------------------
+// SVD Line: 15278
+
+//  <item> SFDITEM_FIELD__TIMER15_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002910) TIMER1n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER15_PREDR >> 0) & 0xFFF), ((TIMER15_PREDR = (TIMER15_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER15_PREDR  ---------------------------------
+// SVD Line: 15269
+
+//  <rtree> SFDITEM_REG__TIMER15_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002910) TIMER1n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER15_PREDR >> 0) & 0xFFFFFFFF), ((TIMER15_PREDR = (TIMER15_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER15_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER15_CNT  -------------------------------
+// SVD Line: 15286
+
+unsigned int TIMER15_CNT __AT (0x40002914);
+
+
+
+// -------------------------------  Field Item: TIMER15_CNT_CNT  ----------------------------------
+// SVD Line: 15295
+
+//  <item> SFDITEM_FIELD__TIMER15_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002914) TIMER1n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER15_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER15_CNT  ----------------------------------
+// SVD Line: 15286
+
+//  <rtree> SFDITEM_REG__TIMER15_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002914) TIMER1n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER15_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER15_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER15  ------------------------------------
+// SVD Line: 15400
+
+//  <view> TIMER15
+//    <name> TIMER15 </name>
+//    <item> SFDITEM_REG__TIMER15_CR </item>
+//    <item> SFDITEM_REG__TIMER15_ADR </item>
+//    <item> SFDITEM_REG__TIMER15_BDR </item>
+//    <item> SFDITEM_REG__TIMER15_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER15_PREDR </item>
+//    <item> SFDITEM_REG__TIMER15_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER16_CR  -------------------------------
+// SVD Line: 15135
+
+unsigned int TIMER16_CR __AT (0x40002A00);
+
+
+
+// ------------------------------  Field Item: TIMER16_CR_T1nEN  ----------------------------------
+// SVD Line: 15144
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nEN
+//    <name> T1nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002A00) TIMER1n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.15..15> T1nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER16_CR_T1nCLK  ---------------------------------
+// SVD Line: 15150
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nCLK
+//    <name> T1nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002A00) TIMER1n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.14..14> T1nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER16_CR_T1nMS  ----------------------------------
+// SVD Line: 15156
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nMS
+//    <name> T1nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002A00) TIMER1n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER16_CR >> 12) & 0x3), ((TIMER16_CR = (TIMER16_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER16_CR_T1nECE  ---------------------------------
+// SVD Line: 15162
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nECE
+//    <name> T1nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002A00) TIMER1n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.11..11> T1nECE
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER16_CR_T1nOPOL  ---------------------------------
+// SVD Line: 15168
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nOPOL
+//    <name> T1nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002A00) TIMER1n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.8..8> T1nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER16_CR_T1nCPOL  ---------------------------------
+// SVD Line: 15174
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nCPOL
+//    <name> T1nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002A00) TIMER1n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER16_CR >> 6) & 0x3), ((TIMER16_CR = (TIMER16_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER16_CR_T1nMIEN  ---------------------------------
+// SVD Line: 15180
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nMIEN
+//    <name> T1nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002A00) TIMER1n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.5..5> T1nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER16_CR_T1nCIEN  ---------------------------------
+// SVD Line: 15186
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nCIEN
+//    <name> T1nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002A00) TIMER1n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.4..4> T1nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER16_CR_T1nMIFLAG  --------------------------------
+// SVD Line: 15192
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nMIFLAG
+//    <name> T1nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002A00) TIMER1n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.3..3> T1nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER16_CR_T1nCIFLAG  --------------------------------
+// SVD Line: 15198
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nCIFLAG
+//    <name> T1nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002A00) TIMER1n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.2..2> T1nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER16_CR_T1nPAU  ---------------------------------
+// SVD Line: 15204
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nPAU
+//    <name> T1nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002A00) TIMER1n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.1..1> T1nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER16_CR_T1nCLR  ---------------------------------
+// SVD Line: 15210
+
+//  <item> SFDITEM_FIELD__TIMER16_CR_T1nCLR
+//    <name> T1nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002A00) TIMER1n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER16_CR ) </loc>
+//      <o.0..0> T1nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER16_CR  -----------------------------------
+// SVD Line: 15135
+
+//  <rtree> SFDITEM_REG__TIMER16_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002A00) TIMER1n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER16_CR >> 0) & 0xFFFFFFFF), ((TIMER16_CR = (TIMER16_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nEN </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nMS </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nECE </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER16_CR_T1nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER16_ADR  -------------------------------
+// SVD Line: 15218
+
+unsigned int TIMER16_ADR __AT (0x40002A04);
+
+
+
+// ------------------------------  Field Item: TIMER16_ADR_ADATA  ---------------------------------
+// SVD Line: 15227
+
+//  <item> SFDITEM_FIELD__TIMER16_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002A04) TIMER1n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER16_ADR >> 0) & 0xFFFF), ((TIMER16_ADR = (TIMER16_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER16_ADR  ----------------------------------
+// SVD Line: 15218
+
+//  <rtree> SFDITEM_REG__TIMER16_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002A04) TIMER1n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER16_ADR >> 0) & 0xFFFFFFFF), ((TIMER16_ADR = (TIMER16_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER16_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER16_BDR  -------------------------------
+// SVD Line: 15235
+
+unsigned int TIMER16_BDR __AT (0x40002A08);
+
+
+
+// ------------------------------  Field Item: TIMER16_BDR_BDATA  ---------------------------------
+// SVD Line: 15244
+
+//  <item> SFDITEM_FIELD__TIMER16_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002A08) TIMER1n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER16_BDR >> 0) & 0xFFFF), ((TIMER16_BDR = (TIMER16_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER16_BDR  ----------------------------------
+// SVD Line: 15235
+
+//  <rtree> SFDITEM_REG__TIMER16_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002A08) TIMER1n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER16_BDR >> 0) & 0xFFFFFFFF), ((TIMER16_BDR = (TIMER16_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER16_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER16_CAPDR  ------------------------------
+// SVD Line: 15252
+
+unsigned int TIMER16_CAPDR __AT (0x40002A0C);
+
+
+
+// -----------------------------  Field Item: TIMER16_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15261
+
+//  <item> SFDITEM_FIELD__TIMER16_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002A0C) TIMER1n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER16_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER16_CAPDR  ---------------------------------
+// SVD Line: 15252
+
+//  <rtree> SFDITEM_REG__TIMER16_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002A0C) TIMER1n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER16_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER16_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER16_PREDR  ------------------------------
+// SVD Line: 15269
+
+unsigned int TIMER16_PREDR __AT (0x40002A10);
+
+
+
+// -----------------------------  Field Item: TIMER16_PREDR_PRED  ---------------------------------
+// SVD Line: 15278
+
+//  <item> SFDITEM_FIELD__TIMER16_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002A10) TIMER1n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER16_PREDR >> 0) & 0xFFF), ((TIMER16_PREDR = (TIMER16_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER16_PREDR  ---------------------------------
+// SVD Line: 15269
+
+//  <rtree> SFDITEM_REG__TIMER16_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002A10) TIMER1n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER16_PREDR >> 0) & 0xFFFFFFFF), ((TIMER16_PREDR = (TIMER16_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER16_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER16_CNT  -------------------------------
+// SVD Line: 15286
+
+unsigned int TIMER16_CNT __AT (0x40002A14);
+
+
+
+// -------------------------------  Field Item: TIMER16_CNT_CNT  ----------------------------------
+// SVD Line: 15295
+
+//  <item> SFDITEM_FIELD__TIMER16_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002A14) TIMER1n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER16_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER16_CNT  ----------------------------------
+// SVD Line: 15286
+
+//  <rtree> SFDITEM_REG__TIMER16_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002A14) TIMER1n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER16_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER16_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER16  ------------------------------------
+// SVD Line: 15419
+
+//  <view> TIMER16
+//    <name> TIMER16 </name>
+//    <item> SFDITEM_REG__TIMER16_CR </item>
+//    <item> SFDITEM_REG__TIMER16_ADR </item>
+//    <item> SFDITEM_REG__TIMER16_BDR </item>
+//    <item> SFDITEM_REG__TIMER16_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER16_PREDR </item>
+//    <item> SFDITEM_REG__TIMER16_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER2n_CR  -------------------------------
+// SVD Line: 15452
+
+unsigned int TIMER2n_CR __AT (0x52000000);
+
+
+
+// ------------------------------  Field Item: TIMER2n_CR_T2nEN  ----------------------------------
+// SVD Line: 15461
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nEN
+//    <name> T2nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x52000000) TIMER2n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.15..15> T2nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER2n_CR_T2nCLK  ---------------------------------
+// SVD Line: 15467
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nCLK
+//    <name> T2nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x52000000) TIMER2n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.14..14> T2nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER2n_CR_T2nMS  ----------------------------------
+// SVD Line: 15473
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nMS
+//    <name> T2nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x52000000) TIMER2n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER2n_CR >> 12) & 0x3), ((TIMER2n_CR = (TIMER2n_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER2n_CR_T2nECE  ---------------------------------
+// SVD Line: 15479
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nECE
+//    <name> T2nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x52000000) TIMER2n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.11..11> T2nECE
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER2n_CR_CAPSEL  ---------------------------------
+// SVD Line: 15485
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_CAPSEL
+//    <name> CAPSEL </name>
+//    <rw> 
+//    <i> [Bits 10..9] RW (@ 0x52000000) TIMER2n Capture Signal Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER2n_CR >> 9) & 0x3), ((TIMER2n_CR = (TIMER2n_CR & ~(0x3UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 9 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER2n_CR_T2nOPOL  ---------------------------------
+// SVD Line: 15491
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nOPOL
+//    <name> T2nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x52000000) TIMER2n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.8..8> T2nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER2n_CR_T2nCPOL  ---------------------------------
+// SVD Line: 15497
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nCPOL
+//    <name> T2nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x52000000) TIMER2n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER2n_CR >> 6) & 0x3), ((TIMER2n_CR = (TIMER2n_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER2n_CR_T2nMIEN  ---------------------------------
+// SVD Line: 15503
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nMIEN
+//    <name> T2nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x52000000) TIMER2n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.5..5> T2nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER2n_CR_T2nCIEN  ---------------------------------
+// SVD Line: 15509
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nCIEN
+//    <name> T2nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x52000000) TIMER2n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.4..4> T2nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER2n_CR_T2nMIFLAG  --------------------------------
+// SVD Line: 15515
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nMIFLAG
+//    <name> T2nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x52000000) TIMER2n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.3..3> T2nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER2n_CR_T2nCIFLAG  --------------------------------
+// SVD Line: 15521
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nCIFLAG
+//    <name> T2nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x52000000) TIMER2n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.2..2> T2nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER2n_CR_T2nPAU  ---------------------------------
+// SVD Line: 15527
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nPAU
+//    <name> T2nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x52000000) TIMER2n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.1..1> T2nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER2n_CR_T2nCLR  ---------------------------------
+// SVD Line: 15533
+
+//  <item> SFDITEM_FIELD__TIMER2n_CR_T2nCLR
+//    <name> T2nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x52000000) TIMER2n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER2n_CR ) </loc>
+//      <o.0..0> T2nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER2n_CR  -----------------------------------
+// SVD Line: 15452
+
+//  <rtree> SFDITEM_REG__TIMER2n_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x52000000) TIMER2n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER2n_CR >> 0) & 0xFFFFFFFF), ((TIMER2n_CR = (TIMER2n_CR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nEN </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nMS </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nECE </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_CAPSEL </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER2n_CR_T2nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER2n_ADR  -------------------------------
+// SVD Line: 15541
+
+unsigned int TIMER2n_ADR __AT (0x52000004);
+
+
+
+// ------------------------------  Field Item: TIMER2n_ADR_ADATA  ---------------------------------
+// SVD Line: 15550
+
+//  <item> SFDITEM_FIELD__TIMER2n_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x52000004) TIMER2n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER2n_ADR >> 0) & 0xFFFFFFFF), ((TIMER2n_ADR = (TIMER2n_ADR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER2n_ADR  ----------------------------------
+// SVD Line: 15541
+
+//  <rtree> SFDITEM_REG__TIMER2n_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x52000004) TIMER2n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER2n_ADR >> 0) & 0xFFFFFFFF), ((TIMER2n_ADR = (TIMER2n_ADR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER2n_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER2n_BDR  -------------------------------
+// SVD Line: 15558
+
+unsigned int TIMER2n_BDR __AT (0x52000008);
+
+
+
+// ------------------------------  Field Item: TIMER2n_BDR_BDATA  ---------------------------------
+// SVD Line: 15567
+
+//  <item> SFDITEM_FIELD__TIMER2n_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x52000008) TIMER2n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER2n_BDR >> 0) & 0xFFFFFFFF), ((TIMER2n_BDR = (TIMER2n_BDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER2n_BDR  ----------------------------------
+// SVD Line: 15558
+
+//  <rtree> SFDITEM_REG__TIMER2n_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x52000008) TIMER2n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER2n_BDR >> 0) & 0xFFFFFFFF), ((TIMER2n_BDR = (TIMER2n_BDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER2n_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER2n_CAPDR  ------------------------------
+// SVD Line: 15575
+
+unsigned int TIMER2n_CAPDR __AT (0x5200000C);
+
+
+
+// -----------------------------  Field Item: TIMER2n_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15584
+
+//  <item> SFDITEM_FIELD__TIMER2n_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x5200000C) TIMER2n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER2n_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER2n_CAPDR  ---------------------------------
+// SVD Line: 15575
+
+//  <rtree> SFDITEM_REG__TIMER2n_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x5200000C) TIMER2n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER2n_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER2n_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER2n_PREDR  ------------------------------
+// SVD Line: 15592
+
+unsigned int TIMER2n_PREDR __AT (0x52000010);
+
+
+
+// -----------------------------  Field Item: TIMER2n_PREDR_PRED  ---------------------------------
+// SVD Line: 15601
+
+//  <item> SFDITEM_FIELD__TIMER2n_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x52000010) TIMER2n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER2n_PREDR >> 0) & 0xFFF), ((TIMER2n_PREDR = (TIMER2n_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER2n_PREDR  ---------------------------------
+// SVD Line: 15592
+
+//  <rtree> SFDITEM_REG__TIMER2n_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x52000010) TIMER2n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER2n_PREDR >> 0) & 0xFFFFFFFF), ((TIMER2n_PREDR = (TIMER2n_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER2n_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER2n_CNT  -------------------------------
+// SVD Line: 15609
+
+unsigned int TIMER2n_CNT __AT (0x52000014);
+
+
+
+// -------------------------------  Field Item: TIMER2n_CNT_CNT  ----------------------------------
+// SVD Line: 15618
+
+//  <item> SFDITEM_FIELD__TIMER2n_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x52000014) TIMER2n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER2n_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER2n_CNT  ----------------------------------
+// SVD Line: 15609
+
+//  <rtree> SFDITEM_REG__TIMER2n_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x52000014) TIMER2n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER2n_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER2n_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER2n  ------------------------------------
+// SVD Line: 15438
+
+//  <view> TIMER2n
+//    <name> TIMER2n </name>
+//    <item> SFDITEM_REG__TIMER2n_CR </item>
+//    <item> SFDITEM_REG__TIMER2n_ADR </item>
+//    <item> SFDITEM_REG__TIMER2n_BDR </item>
+//    <item> SFDITEM_REG__TIMER2n_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER2n_PREDR </item>
+//    <item> SFDITEM_REG__TIMER2n_CNT </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER20_CR  -------------------------------
+// SVD Line: 15452
+
+unsigned int TIMER20_CR __AT (0x40002500);
+
+
+
+// ------------------------------  Field Item: TIMER20_CR_T2nEN  ----------------------------------
+// SVD Line: 15461
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nEN
+//    <name> T2nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002500) TIMER2n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.15..15> T2nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER20_CR_T2nCLK  ---------------------------------
+// SVD Line: 15467
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nCLK
+//    <name> T2nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002500) TIMER2n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.14..14> T2nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER20_CR_T2nMS  ----------------------------------
+// SVD Line: 15473
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nMS
+//    <name> T2nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002500) TIMER2n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER20_CR >> 12) & 0x3), ((TIMER20_CR = (TIMER20_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER20_CR_T2nECE  ---------------------------------
+// SVD Line: 15479
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nECE
+//    <name> T2nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002500) TIMER2n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.11..11> T2nECE
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER20_CR_CAPSEL  ---------------------------------
+// SVD Line: 15485
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_CAPSEL
+//    <name> CAPSEL </name>
+//    <rw> 
+//    <i> [Bits 10..9] RW (@ 0x40002500) TIMER2n Capture Signal Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER20_CR >> 9) & 0x3), ((TIMER20_CR = (TIMER20_CR & ~(0x3UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 9 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER20_CR_T2nOPOL  ---------------------------------
+// SVD Line: 15491
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nOPOL
+//    <name> T2nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002500) TIMER2n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.8..8> T2nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER20_CR_T2nCPOL  ---------------------------------
+// SVD Line: 15497
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nCPOL
+//    <name> T2nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002500) TIMER2n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER20_CR >> 6) & 0x3), ((TIMER20_CR = (TIMER20_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER20_CR_T2nMIEN  ---------------------------------
+// SVD Line: 15503
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nMIEN
+//    <name> T2nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002500) TIMER2n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.5..5> T2nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER20_CR_T2nCIEN  ---------------------------------
+// SVD Line: 15509
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nCIEN
+//    <name> T2nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002500) TIMER2n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.4..4> T2nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER20_CR_T2nMIFLAG  --------------------------------
+// SVD Line: 15515
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nMIFLAG
+//    <name> T2nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002500) TIMER2n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.3..3> T2nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER20_CR_T2nCIFLAG  --------------------------------
+// SVD Line: 15521
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nCIFLAG
+//    <name> T2nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002500) TIMER2n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.2..2> T2nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER20_CR_T2nPAU  ---------------------------------
+// SVD Line: 15527
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nPAU
+//    <name> T2nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002500) TIMER2n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.1..1> T2nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER20_CR_T2nCLR  ---------------------------------
+// SVD Line: 15533
+
+//  <item> SFDITEM_FIELD__TIMER20_CR_T2nCLR
+//    <name> T2nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002500) TIMER2n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_CR ) </loc>
+//      <o.0..0> T2nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER20_CR  -----------------------------------
+// SVD Line: 15452
+
+//  <rtree> SFDITEM_REG__TIMER20_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002500) TIMER2n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER20_CR >> 0) & 0xFFFFFFFF), ((TIMER20_CR = (TIMER20_CR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nEN </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nMS </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nECE </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_CAPSEL </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER20_CR_T2nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER20_ADR  -------------------------------
+// SVD Line: 15541
+
+unsigned int TIMER20_ADR __AT (0x40002504);
+
+
+
+// ------------------------------  Field Item: TIMER20_ADR_ADATA  ---------------------------------
+// SVD Line: 15550
+
+//  <item> SFDITEM_FIELD__TIMER20_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002504) TIMER2n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER20_ADR >> 0) & 0xFFFFFFFF), ((TIMER20_ADR = (TIMER20_ADR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER20_ADR  ----------------------------------
+// SVD Line: 15541
+
+//  <rtree> SFDITEM_REG__TIMER20_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002504) TIMER2n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER20_ADR >> 0) & 0xFFFFFFFF), ((TIMER20_ADR = (TIMER20_ADR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER20_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER20_BDR  -------------------------------
+// SVD Line: 15558
+
+unsigned int TIMER20_BDR __AT (0x40002508);
+
+
+
+// ------------------------------  Field Item: TIMER20_BDR_BDATA  ---------------------------------
+// SVD Line: 15567
+
+//  <item> SFDITEM_FIELD__TIMER20_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002508) TIMER2n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER20_BDR >> 0) & 0xFFFFFFFF), ((TIMER20_BDR = (TIMER20_BDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER20_BDR  ----------------------------------
+// SVD Line: 15558
+
+//  <rtree> SFDITEM_REG__TIMER20_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002508) TIMER2n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER20_BDR >> 0) & 0xFFFFFFFF), ((TIMER20_BDR = (TIMER20_BDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER20_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER20_CAPDR  ------------------------------
+// SVD Line: 15575
+
+unsigned int TIMER20_CAPDR __AT (0x4000250C);
+
+
+
+// -----------------------------  Field Item: TIMER20_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15584
+
+//  <item> SFDITEM_FIELD__TIMER20_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000250C) TIMER2n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER20_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER20_CAPDR  ---------------------------------
+// SVD Line: 15575
+
+//  <rtree> SFDITEM_REG__TIMER20_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000250C) TIMER2n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER20_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER20_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER20_PREDR  ------------------------------
+// SVD Line: 15592
+
+unsigned int TIMER20_PREDR __AT (0x40002510);
+
+
+
+// -----------------------------  Field Item: TIMER20_PREDR_PRED  ---------------------------------
+// SVD Line: 15601
+
+//  <item> SFDITEM_FIELD__TIMER20_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002510) TIMER2n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER20_PREDR >> 0) & 0xFFF), ((TIMER20_PREDR = (TIMER20_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER20_PREDR  ---------------------------------
+// SVD Line: 15592
+
+//  <rtree> SFDITEM_REG__TIMER20_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002510) TIMER2n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER20_PREDR >> 0) & 0xFFFFFFFF), ((TIMER20_PREDR = (TIMER20_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER20_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER20_CNT  -------------------------------
+// SVD Line: 15609
+
+unsigned int TIMER20_CNT __AT (0x40002514);
+
+
+
+// -------------------------------  Field Item: TIMER20_CNT_CNT  ----------------------------------
+// SVD Line: 15618
+
+//  <item> SFDITEM_FIELD__TIMER20_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002514) TIMER2n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER20_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER20_CNT  ----------------------------------
+// SVD Line: 15609
+
+//  <rtree> SFDITEM_REG__TIMER20_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002514) TIMER2n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER20_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER20_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// ------------------------  Register Item Address: TIMER20_TIMER20_CR  ---------------------------
+// SVD Line: 15647
+
+unsigned int TIMER20_TIMER20_CR __AT (0x40002500);
+
+
+
+// --------------------------  Field Item: TIMER20_TIMER20_CR_T2nEN  ------------------------------
+// SVD Line: 15657
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nEN
+//    <name> T2nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002500) TIMER2n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.15..15> T2nEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER20_TIMER20_CR_T2nCLK  -----------------------------
+// SVD Line: 15663
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCLK
+//    <name> T2nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002500) TIMER2n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.14..14> T2nCLK
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER20_TIMER20_CR_T2nMS  ------------------------------
+// SVD Line: 15669
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nMS
+//    <name> T2nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002500) TIMER2n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER20_TIMER20_CR >> 12) & 0x3), ((TIMER20_TIMER20_CR = (TIMER20_TIMER20_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER20_TIMER20_CR_T2nECE  -----------------------------
+// SVD Line: 15675
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nECE
+//    <name> T2nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002500) TIMER2n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.11..11> T2nECE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER20_TIMER20_CR_CAPSEL  -----------------------------
+// SVD Line: 15681
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_CAPSEL
+//    <name> CAPSEL </name>
+//    <rw> 
+//    <i> [Bits 10..9] RW (@ 0x40002500) TIMER2n Capture Signal Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER20_TIMER20_CR >> 9) & 0x3), ((TIMER20_TIMER20_CR = (TIMER20_TIMER20_CR & ~(0x3UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 9 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER20_TIMER20_CR_T2nOPOL  -----------------------------
+// SVD Line: 15687
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nOPOL
+//    <name> T2nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002500) TIMER2n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.8..8> T2nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER20_TIMER20_CR_T2nCPOL  -----------------------------
+// SVD Line: 15693
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCPOL
+//    <name> T2nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002500) TIMER2n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER20_TIMER20_CR >> 6) & 0x3), ((TIMER20_TIMER20_CR = (TIMER20_TIMER20_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER20_TIMER20_CR_T2nMIEN  -----------------------------
+// SVD Line: 15699
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nMIEN
+//    <name> T2nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002500) TIMER2n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.5..5> T2nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER20_TIMER20_CR_T2nCIEN  -----------------------------
+// SVD Line: 15705
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCIEN
+//    <name> T2nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002500) TIMER2n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.4..4> T2nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------  Field Item: TIMER20_TIMER20_CR_T2nMIFLAG  ----------------------------
+// SVD Line: 15711
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nMIFLAG
+//    <name> T2nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002500) TIMER2n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.3..3> T2nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------  Field Item: TIMER20_TIMER20_CR_T2nCIFLAG  ----------------------------
+// SVD Line: 15717
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCIFLAG
+//    <name> T2nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002500) TIMER2n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.2..2> T2nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER20_TIMER20_CR_T2nPAU  -----------------------------
+// SVD Line: 15723
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nPAU
+//    <name> T2nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002500) TIMER2n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.1..1> T2nPAU
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER20_TIMER20_CR_T2nCLR  -----------------------------
+// SVD Line: 15729
+
+//  <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCLR
+//    <name> T2nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002500) TIMER2n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER20_TIMER20_CR ) </loc>
+//      <o.0..0> T2nCLR
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Register RTree: TIMER20_TIMER20_CR  -------------------------------
+// SVD Line: 15647
+
+//  <rtree> SFDITEM_REG__TIMER20_TIMER20_CR
+//    <name> TIMER20_CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002500) TIMER2n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER20_TIMER20_CR >> 0) & 0xFFFFFFFF), ((TIMER20_TIMER20_CR = (TIMER20_TIMER20_CR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nEN </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nMS </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nECE </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_CAPSEL </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER20_TIMER20_CR_T2nCLR </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER20  ------------------------------------
+// SVD Line: 15628
+
+//  <view> TIMER20
+//    <name> TIMER20 </name>
+//    <item> SFDITEM_REG__TIMER20_CR </item>
+//    <item> SFDITEM_REG__TIMER20_ADR </item>
+//    <item> SFDITEM_REG__TIMER20_BDR </item>
+//    <item> SFDITEM_REG__TIMER20_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER20_PREDR </item>
+//    <item> SFDITEM_REG__TIMER20_CNT </item>
+//    <item> SFDITEM_REG__TIMER20_TIMER20_CR </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER21_CR  -------------------------------
+// SVD Line: 15452
+
+unsigned int TIMER21_CR __AT (0x40002600);
+
+
+
+// ------------------------------  Field Item: TIMER21_CR_T2nEN  ----------------------------------
+// SVD Line: 15461
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nEN
+//    <name> T2nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002600) TIMER2n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.15..15> T2nEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER21_CR_T2nCLK  ---------------------------------
+// SVD Line: 15467
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nCLK
+//    <name> T2nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002600) TIMER2n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.14..14> T2nCLK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER21_CR_T2nMS  ----------------------------------
+// SVD Line: 15473
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nMS
+//    <name> T2nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002600) TIMER2n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER21_CR >> 12) & 0x3), ((TIMER21_CR = (TIMER21_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER21_CR_T2nECE  ---------------------------------
+// SVD Line: 15479
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nECE
+//    <name> T2nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002600) TIMER2n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.11..11> T2nECE
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER21_CR_CAPSEL  ---------------------------------
+// SVD Line: 15485
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_CAPSEL
+//    <name> CAPSEL </name>
+//    <rw> 
+//    <i> [Bits 10..9] RW (@ 0x40002600) TIMER2n Capture Signal Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER21_CR >> 9) & 0x3), ((TIMER21_CR = (TIMER21_CR & ~(0x3UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 9 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER21_CR_T2nOPOL  ---------------------------------
+// SVD Line: 15491
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nOPOL
+//    <name> T2nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002600) TIMER2n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.8..8> T2nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER21_CR_T2nCPOL  ---------------------------------
+// SVD Line: 15497
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nCPOL
+//    <name> T2nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002600) TIMER2n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER21_CR >> 6) & 0x3), ((TIMER21_CR = (TIMER21_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER21_CR_T2nMIEN  ---------------------------------
+// SVD Line: 15503
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nMIEN
+//    <name> T2nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002600) TIMER2n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.5..5> T2nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER21_CR_T2nCIEN  ---------------------------------
+// SVD Line: 15509
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nCIEN
+//    <name> T2nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002600) TIMER2n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.4..4> T2nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER21_CR_T2nMIFLAG  --------------------------------
+// SVD Line: 15515
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nMIFLAG
+//    <name> T2nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002600) TIMER2n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.3..3> T2nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER21_CR_T2nCIFLAG  --------------------------------
+// SVD Line: 15521
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nCIFLAG
+//    <name> T2nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002600) TIMER2n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.2..2> T2nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER21_CR_T2nPAU  ---------------------------------
+// SVD Line: 15527
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nPAU
+//    <name> T2nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002600) TIMER2n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.1..1> T2nPAU
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER21_CR_T2nCLR  ---------------------------------
+// SVD Line: 15533
+
+//  <item> SFDITEM_FIELD__TIMER21_CR_T2nCLR
+//    <name> T2nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002600) TIMER2n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_CR ) </loc>
+//      <o.0..0> T2nCLR
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER21_CR  -----------------------------------
+// SVD Line: 15452
+
+//  <rtree> SFDITEM_REG__TIMER21_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002600) TIMER2n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER21_CR >> 0) & 0xFFFFFFFF), ((TIMER21_CR = (TIMER21_CR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nEN </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nMS </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nECE </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_CAPSEL </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER21_CR_T2nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER21_ADR  -------------------------------
+// SVD Line: 15541
+
+unsigned int TIMER21_ADR __AT (0x40002604);
+
+
+
+// ------------------------------  Field Item: TIMER21_ADR_ADATA  ---------------------------------
+// SVD Line: 15550
+
+//  <item> SFDITEM_FIELD__TIMER21_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002604) TIMER2n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER21_ADR >> 0) & 0xFFFFFFFF), ((TIMER21_ADR = (TIMER21_ADR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER21_ADR  ----------------------------------
+// SVD Line: 15541
+
+//  <rtree> SFDITEM_REG__TIMER21_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002604) TIMER2n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER21_ADR >> 0) & 0xFFFFFFFF), ((TIMER21_ADR = (TIMER21_ADR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER21_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER21_BDR  -------------------------------
+// SVD Line: 15558
+
+unsigned int TIMER21_BDR __AT (0x40002608);
+
+
+
+// ------------------------------  Field Item: TIMER21_BDR_BDATA  ---------------------------------
+// SVD Line: 15567
+
+//  <item> SFDITEM_FIELD__TIMER21_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002608) TIMER2n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER21_BDR >> 0) & 0xFFFFFFFF), ((TIMER21_BDR = (TIMER21_BDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER21_BDR  ----------------------------------
+// SVD Line: 15558
+
+//  <rtree> SFDITEM_REG__TIMER21_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002608) TIMER2n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER21_BDR >> 0) & 0xFFFFFFFF), ((TIMER21_BDR = (TIMER21_BDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER21_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER21_CAPDR  ------------------------------
+// SVD Line: 15575
+
+unsigned int TIMER21_CAPDR __AT (0x4000260C);
+
+
+
+// -----------------------------  Field Item: TIMER21_CAPDR_CAPD  ---------------------------------
+// SVD Line: 15584
+
+//  <item> SFDITEM_FIELD__TIMER21_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000260C) TIMER2n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER21_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER21_CAPDR  ---------------------------------
+// SVD Line: 15575
+
+//  <rtree> SFDITEM_REG__TIMER21_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000260C) TIMER2n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER21_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER21_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER21_PREDR  ------------------------------
+// SVD Line: 15592
+
+unsigned int TIMER21_PREDR __AT (0x40002610);
+
+
+
+// -----------------------------  Field Item: TIMER21_PREDR_PRED  ---------------------------------
+// SVD Line: 15601
+
+//  <item> SFDITEM_FIELD__TIMER21_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002610) TIMER2n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER21_PREDR >> 0) & 0xFFF), ((TIMER21_PREDR = (TIMER21_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER21_PREDR  ---------------------------------
+// SVD Line: 15592
+
+//  <rtree> SFDITEM_REG__TIMER21_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002610) TIMER2n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER21_PREDR >> 0) & 0xFFFFFFFF), ((TIMER21_PREDR = (TIMER21_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER21_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER21_CNT  -------------------------------
+// SVD Line: 15609
+
+unsigned int TIMER21_CNT __AT (0x40002614);
+
+
+
+// -------------------------------  Field Item: TIMER21_CNT_CNT  ----------------------------------
+// SVD Line: 15618
+
+//  <item> SFDITEM_FIELD__TIMER21_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002614) TIMER2n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((TIMER21_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER21_CNT  ----------------------------------
+// SVD Line: 15609
+
+//  <rtree> SFDITEM_REG__TIMER21_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002614) TIMER2n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER21_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER21_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// ------------------------  Register Item Address: TIMER21_TIMER21_CR  ---------------------------
+// SVD Line: 15758
+
+unsigned int TIMER21_TIMER21_CR __AT (0x40002600);
+
+
+
+// --------------------------  Field Item: TIMER21_TIMER21_CR_T2nEN  ------------------------------
+// SVD Line: 15768
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nEN
+//    <name> T2nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002600) TIMER2n Operation Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.15..15> T2nEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER21_TIMER21_CR_T2nCLK  -----------------------------
+// SVD Line: 15774
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCLK
+//    <name> T2nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002600) TIMER2n Clock Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.14..14> T2nCLK
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER21_TIMER21_CR_T2nMS  ------------------------------
+// SVD Line: 15780
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nMS
+//    <name> T2nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002600) TIMER2n Operation Mode Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER21_TIMER21_CR >> 12) & 0x3), ((TIMER21_TIMER21_CR = (TIMER21_TIMER21_CR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER21_TIMER21_CR_T2nECE  -----------------------------
+// SVD Line: 15786
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nECE
+//    <name> T2nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002600) TIMER2n External Clock Edge Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.11..11> T2nECE
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER21_TIMER21_CR_T2nOPOL  -----------------------------
+// SVD Line: 15792
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nOPOL
+//    <name> T2nOPOL </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002600) TIMER2n Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.8..8> T2nOPOL
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER21_TIMER21_CR_T2nCPOL  -----------------------------
+// SVD Line: 15798
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCPOL
+//    <name> T2nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002600) TIMER2n Capture Polarity Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((TIMER21_TIMER21_CR >> 6) & 0x3), ((TIMER21_TIMER21_CR = (TIMER21_TIMER21_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER21_TIMER21_CR_T2nMIEN  -----------------------------
+// SVD Line: 15804
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nMIEN
+//    <name> T2nMIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002600) TIMER2n Match Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.5..5> T2nMIEN
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER21_TIMER21_CR_T2nCIEN  -----------------------------
+// SVD Line: 15810
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCIEN
+//    <name> T2nCIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002600) TIMER2n Capture Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.4..4> T2nCIEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------  Field Item: TIMER21_TIMER21_CR_T2nMIFLAG  ----------------------------
+// SVD Line: 15816
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nMIFLAG
+//    <name> T2nMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002600) TIMER2n Match Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.3..3> T2nMIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------  Field Item: TIMER21_TIMER21_CR_T2nCIFLAG  ----------------------------
+// SVD Line: 15822
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCIFLAG
+//    <name> T2nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002600) TIMER2n Capture Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.2..2> T2nCIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER21_TIMER21_CR_T2nPAU  -----------------------------
+// SVD Line: 15828
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nPAU
+//    <name> T2nPAU </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002600) TIMER2n Counter Temporary Pause Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.1..1> T2nPAU
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER21_TIMER21_CR_T2nCLR  -----------------------------
+// SVD Line: 15834
+
+//  <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCLR
+//    <name> T2nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002600) TIMER2n Counter and Prescaler Clear </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER21_TIMER21_CR ) </loc>
+//      <o.0..0> T2nCLR
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Register RTree: TIMER21_TIMER21_CR  -------------------------------
+// SVD Line: 15758
+
+//  <rtree> SFDITEM_REG__TIMER21_TIMER21_CR
+//    <name> TIMER21_CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002600) TIMER2n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER21_TIMER21_CR >> 0) & 0xFFFFFFFF), ((TIMER21_TIMER21_CR = (TIMER21_TIMER21_CR & ~(0xF9FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF9FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nEN </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nMS </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nECE </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nOPOL </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nPAU </item>
+//    <item> SFDITEM_FIELD__TIMER21_TIMER21_CR_T2nCLR </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER21  ------------------------------------
+// SVD Line: 15739
+
+//  <view> TIMER21
+//    <name> TIMER21 </name>
+//    <item> SFDITEM_REG__TIMER21_CR </item>
+//    <item> SFDITEM_REG__TIMER21_ADR </item>
+//    <item> SFDITEM_REG__TIMER21_BDR </item>
+//    <item> SFDITEM_REG__TIMER21_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER21_PREDR </item>
+//    <item> SFDITEM_REG__TIMER21_CNT </item>
+//    <item> SFDITEM_REG__TIMER21_TIMER21_CR </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER3n_CR  -------------------------------
+// SVD Line: 15858
+
+unsigned int TIMER3n_CR __AT (0x53000000);
+
+
+
+// ------------------------------  Field Item: TIMER3n_CR_T3nEN  ----------------------------------
+// SVD Line: 15867
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_T3nEN
+//    <name> T3nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x53000000) \nTIMER3n Operation Enable\n0 : Disable = Disable TIMER3n Operation.\n1 : Enable = Enable TIMER3n Operation. (Counter Clear and Start) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.15..15> T3nEN
+//        <0=> 0: Disable = Disable TIMER3n Operation.
+//        <1=> 1: Enable = Enable TIMER3n Operation. (Counter Clear and Start)
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER3n_CR_T3nCLK  ---------------------------------
+// SVD Line: 15885
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_T3nCLK
+//    <name> T3nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x53000000) \nTIMER3n Clock Selection\n0 : IntPrescaledClock = Select an Internal Prescaler Clock.\n1 : ExtClock = Select an External Clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.14..14> T3nCLK
+//        <0=> 0: IntPrescaledClock = Select an Internal Prescaler Clock.
+//        <1=> 1: ExtClock = Select an External Clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER3n_CR_T3nMS  ----------------------------------
+// SVD Line: 15903
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_T3nMS
+//    <name> T3nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x53000000) \nTIMER3n Operation Mode Selection\n0 : IntervalMode = Interval mode. (All match interrupts can occur)\n1 : CaptureMode = Capture mode. (The Period-match interrupt can occur)\n2 : BackToBackMode = Back-to-back mode. (All interrupts can occur)\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.13..12> T3nMS
+//        <0=> 0: IntervalMode = Interval mode. (All match interrupts can occur)
+//        <1=> 1: CaptureMode = Capture mode. (The Period-match interrupt can occur)
+//        <2=> 2: BackToBackMode = Back-to-back mode. (All interrupts can occur)
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER3n_CR_T3nECE  ---------------------------------
+// SVD Line: 15926
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_T3nECE
+//    <name> T3nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x53000000) \nTIMER3n External Clock Edge Selection\n0 : FallingEdge = Select falling edge of external clock.\n1 : RisingEdge = Select rising edge of external clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.11..11> T3nECE
+//        <0=> 0: FallingEdge = Select falling edge of external clock.
+//        <1=> 1: RisingEdge = Select rising edge of external clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER3n_CR_FORCA  ----------------------------------
+// SVD Line: 15944
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_FORCA
+//    <name> FORCA </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x53000000) \nTIMER3n Output Mode Selection\n0 : AllChannelMode = 6-Channel mode. (The PWM3nxA/PWM3nxB pins are outputs according to the TIMER30_xDR registers, respectively.)\n1 : AChannelMode = Force A-Channel mode. (All PWM3nxA/PWM3nxB pins are outputs according only to the TIMER30_ADR register.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.10..10> FORCA
+//        <0=> 0: AllChannelMode = 6-Channel mode. (The PWM3nxA/PWM3nxB pins are outputs according to the TIMER30_xDR registers, respectively.)
+//        <1=> 1: AChannelMode = Force A-Channel mode. (All PWM3nxA/PWM3nxB pins are outputs according only to the TIMER30_ADR register.)
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER3n_CR_DLYEN  ----------------------------------
+// SVD Line: 15962
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_DLYEN
+//    <name> DLYEN </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x53000000) \nDelay Time Insertion Enable\n0 : Disable = Disable delay time insertion to the PWM3nxA/PWM3nxB.\n1 : Enable = Enable delay time insertion to the PWM3nxA/PWM3nxB. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.9..9> DLYEN
+//        <0=> 0: Disable = Disable delay time insertion to the PWM3nxA/PWM3nxB.
+//        <1=> 1: Enable = Enable delay time insertion to the PWM3nxA/PWM3nxB.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER3n_CR_DLYPOS  ---------------------------------
+// SVD Line: 15980
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_DLYPOS
+//    <name> DLYPOS </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x53000000) \nDelay Time Insertion Position\n0 : FrontABehindB = Insert in front of PWM3nxA and behind PWM3nxB pins.\n1 : BehindAFrontB = Insert behind PWM3nxA and in front of PWM3nxB pins. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.8..8> DLYPOS
+//        <0=> 0: FrontABehindB = Insert in front of PWM3nxA and behind PWM3nxB pins.
+//        <1=> 1: BehindAFrontB = Insert behind PWM3nxA and in front of PWM3nxB pins.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_CR_T3nCPOL  ---------------------------------
+// SVD Line: 15998
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_T3nCPOL
+//    <name> T3nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x53000000) \nTIMER3n Capture Polarity Selection\n0 : FallingEdge = Capture on falling edge.\n1 : RisingEdge = Capture on rising edge.\n2 : BothEdge = Capture on both falling and rising edge.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.7..6> T3nCPOL
+//        <0=> 0: FallingEdge = Capture on falling edge.
+//        <1=> 1: RisingEdge = Capture on rising edge.
+//        <2=> 2: BothEdge = Capture on both falling and rising edge.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: TIMER3n_CR_UPDT  ----------------------------------
+// SVD Line: 16021
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_UPDT
+//    <name> UPDT </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x53000000) \nData Reload Time Selection\n0 : AtWriting = Update data to buffer at the time of writing.\n1 : AtPeriodMatch = Update data to buffer at period match.\n2 : AtBottom = Update data to buffer at bottom.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.5..4> UPDT
+//        <0=> 0: AtWriting = Update data to buffer at the time of writing.
+//        <1=> 1: AtPeriodMatch = Update data to buffer at period match.
+//        <2=> 2: AtBottom = Update data to buffer at bottom.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: TIMER3n_CR_PMOC  ----------------------------------
+// SVD Line: 16044
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_PMOC
+//    <name> PMOC </name>
+//    <rw> 
+//    <i> [Bits 3..1] RW (@ 0x53000000) \nPeriod Match Interrupt Occurrence Selection\n0 : Every1PeriodMatch = Once every 1 period match.\n1 : Every2PeriodMatch = Once every 2 period match.\n2 : Every3PeriodMatch = Once every 3 period match.\n3 : Every4PeriodMatch = Once every 4 period match.\n4 : Every5PeriodMatch = Once every 5 period match.\n5 : Every6PeriodMatch = Once every 6 period match.\n6 : Every7PeriodMatch = Once every 7 period match.\n7 : Every8PeriodMatch = Once every 8 period match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.3..1> PMOC
+//        <0=> 0: Every1PeriodMatch = Once every 1 period match.
+//        <1=> 1: Every2PeriodMatch = Once every 2 period match.
+//        <2=> 2: Every3PeriodMatch = Once every 3 period match.
+//        <3=> 3: Every4PeriodMatch = Once every 4 period match.
+//        <4=> 4: Every5PeriodMatch = Once every 5 period match.
+//        <5=> 5: Every6PeriodMatch = Once every 6 period match.
+//        <6=> 6: Every7PeriodMatch = Once every 7 period match.
+//        <7=> 7: Every8PeriodMatch = Once every 8 period match.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER3n_CR_T3nCLR  ---------------------------------
+// SVD Line: 16092
+
+//  <item> SFDITEM_FIELD__TIMER3n_CR_T3nCLR
+//    <name> T3nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x53000000) \nTIMER3n Counter and Prescaler Clear\n0 : NoEffect = No effect.\n1 : Clear = Clear TIMER3n counter and prescaler. (Automatically cleared to '0b' after operation) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_CR ) </loc>
+//      <o.0..0> T3nCLR
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear TIMER3n counter and prescaler. (Automatically cleared to '0b' after operation)
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER3n_CR  -----------------------------------
+// SVD Line: 15858
+
+//  <rtree> SFDITEM_REG__TIMER3n_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000000) TIMER3n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_CR >> 0) & 0xFFFFFFFF), ((TIMER3n_CR = (TIMER3n_CR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_T3nEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_T3nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_T3nMS </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_T3nECE </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_FORCA </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_DLYEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_DLYPOS </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_T3nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_UPDT </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_PMOC </item>
+//    <item> SFDITEM_FIELD__TIMER3n_CR_T3nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER3n_PDR  -------------------------------
+// SVD Line: 16112
+
+unsigned int TIMER3n_PDR __AT (0x53000004);
+
+
+
+// ------------------------------  Field Item: TIMER3n_PDR_PDATA  ---------------------------------
+// SVD Line: 16121
+
+//  <item> SFDITEM_FIELD__TIMER3n_PDR_PDATA
+//    <name> PDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x53000004) TIMER3n Period Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_PDR >> 0) & 0xFFFF), ((TIMER3n_PDR = (TIMER3n_PDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER3n_PDR  ----------------------------------
+// SVD Line: 16112
+
+//  <rtree> SFDITEM_REG__TIMER3n_PDR
+//    <name> PDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000004) TIMER3n Period Data Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_PDR >> 0) & 0xFFFFFFFF), ((TIMER3n_PDR = (TIMER3n_PDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_PDR_PDATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER3n_ADR  -------------------------------
+// SVD Line: 16129
+
+unsigned int TIMER3n_ADR __AT (0x53000008);
+
+
+
+// ------------------------------  Field Item: TIMER3n_ADR_ADATA  ---------------------------------
+// SVD Line: 16138
+
+//  <item> SFDITEM_FIELD__TIMER3n_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x53000008) TIMER3n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_ADR >> 0) & 0xFFFF), ((TIMER3n_ADR = (TIMER3n_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER3n_ADR  ----------------------------------
+// SVD Line: 16129
+
+//  <rtree> SFDITEM_REG__TIMER3n_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000008) TIMER3n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_ADR >> 0) & 0xFFFFFFFF), ((TIMER3n_ADR = (TIMER3n_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER3n_BDR  -------------------------------
+// SVD Line: 16146
+
+unsigned int TIMER3n_BDR __AT (0x5300000C);
+
+
+
+// ------------------------------  Field Item: TIMER3n_BDR_BDATA  ---------------------------------
+// SVD Line: 16155
+
+//  <item> SFDITEM_FIELD__TIMER3n_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x5300000C) TIMER3n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_BDR >> 0) & 0xFFFF), ((TIMER3n_BDR = (TIMER3n_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER3n_BDR  ----------------------------------
+// SVD Line: 16146
+
+//  <rtree> SFDITEM_REG__TIMER3n_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x5300000C) TIMER3n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_BDR >> 0) & 0xFFFFFFFF), ((TIMER3n_BDR = (TIMER3n_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER3n_CDR  -------------------------------
+// SVD Line: 16163
+
+unsigned int TIMER3n_CDR __AT (0x53000010);
+
+
+
+// ------------------------------  Field Item: TIMER3n_CDR_CDATA  ---------------------------------
+// SVD Line: 16172
+
+//  <item> SFDITEM_FIELD__TIMER3n_CDR_CDATA
+//    <name> CDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x53000010) TIMER3n C Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_CDR >> 0) & 0xFFFF), ((TIMER3n_CDR = (TIMER3n_CDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER3n_CDR  ----------------------------------
+// SVD Line: 16163
+
+//  <rtree> SFDITEM_REG__TIMER3n_CDR
+//    <name> CDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000010) TIMER3n C Data Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_CDR >> 0) & 0xFFFFFFFF), ((TIMER3n_CDR = (TIMER3n_CDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_CDR_CDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER3n_CAPDR  ------------------------------
+// SVD Line: 16180
+
+unsigned int TIMER3n_CAPDR __AT (0x53000014);
+
+
+
+// -----------------------------  Field Item: TIMER3n_CAPDR_CAPD  ---------------------------------
+// SVD Line: 16189
+
+//  <item> SFDITEM_FIELD__TIMER3n_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x53000014) TIMER3n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER3n_CAPDR  ---------------------------------
+// SVD Line: 16180
+
+//  <rtree> SFDITEM_REG__TIMER3n_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x53000014) TIMER3n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER3n_PREDR  ------------------------------
+// SVD Line: 16197
+
+unsigned int TIMER3n_PREDR __AT (0x53000018);
+
+
+
+// -----------------------------  Field Item: TIMER3n_PREDR_PRED  ---------------------------------
+// SVD Line: 16206
+
+//  <item> SFDITEM_FIELD__TIMER3n_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x53000018) TIMER3n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_PREDR >> 0) & 0xFFF), ((TIMER3n_PREDR = (TIMER3n_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER3n_PREDR  ---------------------------------
+// SVD Line: 16197
+
+//  <rtree> SFDITEM_REG__TIMER3n_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000018) TIMER3n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_PREDR >> 0) & 0xFFFFFFFF), ((TIMER3n_PREDR = (TIMER3n_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER3n_CNT  -------------------------------
+// SVD Line: 16214
+
+unsigned int TIMER3n_CNT __AT (0x5300001C);
+
+
+
+// -------------------------------  Field Item: TIMER3n_CNT_CNT  ----------------------------------
+// SVD Line: 16223
+
+//  <item> SFDITEM_FIELD__TIMER3n_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x5300001C) TIMER3n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER3n_CNT  ----------------------------------
+// SVD Line: 16214
+
+//  <rtree> SFDITEM_REG__TIMER3n_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x5300001C) TIMER3n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER3n_OUTCR  ------------------------------
+// SVD Line: 16231
+
+unsigned int TIMER3n_OUTCR __AT (0x53000020);
+
+
+
+// ----------------------------  Field Item: TIMER3n_OUTCR_WTIDKY  --------------------------------
+// SVD Line: 16240
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x53000020) Write Identification Key </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_OUTCR >> 16) & 0x0), ((TIMER3n_OUTCR = (TIMER3n_OUTCR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_POLB  ---------------------------------
+// SVD Line: 16246
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_POLB
+//    <name> POLB </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x53000020) \nPWM3nxB Output Polarity Selection\n0 : StartLow = Low level start. (The PWM3nxB pins are started with low level after counting.)\n1 : StartHigh = High level start. (The PWM3nxB pins are started with high level after counting) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.15..15> POLB
+//        <0=> 0: StartLow = Low level start. (The PWM3nxB pins are started with low level after counting.)
+//        <1=> 1: StartHigh = High level start. (The PWM3nxB pins are started with high level after counting)
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_POLA  ---------------------------------
+// SVD Line: 16264
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_POLA
+//    <name> POLA </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x53000020) \nPWM3nxA Output Polarity Selection\n0 : StartLow = Low level start. (The PWM3nxA pins are started with low level after counting.)\n1 : StartHigh = High level start. (The PWM3nxA pins are started with high level after counting) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.14..14> POLA
+//        <0=> 0: StartLow = Low level start. (The PWM3nxA pins are started with low level after counting.)
+//        <1=> 1: StartHigh = High level start. (The PWM3nxA pins are started with high level after counting)
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_PABOE  --------------------------------
+// SVD Line: 16282
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_PABOE
+//    <name> PABOE </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x53000020) \nPWM3nAB Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.13..13> PABOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_PBBOE  --------------------------------
+// SVD Line: 16300
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_PBBOE
+//    <name> PBBOE </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x53000020) \nPWM3nBB Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.12..12> PBBOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_PCBOE  --------------------------------
+// SVD Line: 16318
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_PCBOE
+//    <name> PCBOE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x53000020) \nPWM3nCB Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.11..11> PCBOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_PAAOE  --------------------------------
+// SVD Line: 16336
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_PAAOE
+//    <name> PAAOE </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x53000020) \nPWM3nAA Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.10..10> PAAOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_PBAOE  --------------------------------
+// SVD Line: 16354
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_PBAOE
+//    <name> PBAOE </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x53000020) \nPWM3nBA Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.9..9> PBAOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_PCAOE  --------------------------------
+// SVD Line: 16372
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_PCAOE
+//    <name> PCAOE </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x53000020) \nPWM3nCA Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.8..8> PCAOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_LVLAB  --------------------------------
+// SVD Line: 16390
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLAB
+//    <name> LVLAB </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x53000020) \nConfigure PWM3nAB Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.6..6> LVLAB
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_LVLBB  --------------------------------
+// SVD Line: 16408
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLBB
+//    <name> LVLBB </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x53000020) \nConfigure PWM3nBB Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.5..5> LVLBB
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_LVLCB  --------------------------------
+// SVD Line: 16426
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLCB
+//    <name> LVLCB </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x53000020) \nConfigure PWM3nCB Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.4..4> LVLCB
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_LVLAA  --------------------------------
+// SVD Line: 16444
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLAA
+//    <name> LVLAA </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x53000020) \nConfigure PWM3nAA Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.2..2> LVLAA
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_LVLBA  --------------------------------
+// SVD Line: 16462
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLBA
+//    <name> LVLBA </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x53000020) \nConfigure PWM3nBA Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.1..1> LVLBA
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_OUTCR_LVLCA  --------------------------------
+// SVD Line: 16480
+
+//  <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLCA
+//    <name> LVLCA </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x53000020) \nConfigure PWM3nCA Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_OUTCR ) </loc>
+//      <o.0..0> LVLCA
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER3n_OUTCR  ---------------------------------
+// SVD Line: 16231
+
+//  <rtree> SFDITEM_REG__TIMER3n_OUTCR
+//    <name> OUTCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000020) TIMER3n Output Control Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_OUTCR >> 0) & 0xFFFFFFFF), ((TIMER3n_OUTCR = (TIMER3n_OUTCR & ~(0xFFFFFF77UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF77) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_POLB </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_POLA </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_PABOE </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_PBBOE </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_PCBOE </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_PAAOE </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_PBAOE </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_PCAOE </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLAB </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLBB </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLCB </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLAA </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLBA </item>
+//    <item> SFDITEM_FIELD__TIMER3n_OUTCR_LVLCA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER3n_DLY  -------------------------------
+// SVD Line: 16500
+
+unsigned int TIMER3n_DLY __AT (0x53000024);
+
+
+
+// -------------------------------  Field Item: TIMER3n_DLY_DLY  ----------------------------------
+// SVD Line: 16509
+
+//  <item> SFDITEM_FIELD__TIMER3n_DLY_DLY
+//    <name> DLY </name>
+//    <rw> 
+//    <i> [Bits 9..0] RW (@ 0x53000024) TIMER3n PWM Delay Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_DLY >> 0) & 0x3FF), ((TIMER3n_DLY = (TIMER3n_DLY & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER3n_DLY  ----------------------------------
+// SVD Line: 16500
+
+//  <rtree> SFDITEM_REG__TIMER3n_DLY
+//    <name> DLY </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000024) TIMER3n PWM Output Delay Data Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_DLY >> 0) & 0xFFFFFFFF), ((TIMER3n_DLY = (TIMER3n_DLY & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_DLY_DLY </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER3n_INTCR  ------------------------------
+// SVD Line: 16517
+
+unsigned int TIMER3n_INTCR __AT (0x53000028);
+
+
+
+// ----------------------------  Field Item: TIMER3n_INTCR_HIZIEN  --------------------------------
+// SVD Line: 16526
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTCR_HIZIEN
+//    <name> HIZIEN </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x53000028) \nTIMER3n Output High-Impedance Interrupt Enable\n0 : Disable = Disable TIMER3n output high-impedance interrupt.\n1 : Enable = Enable TIMER3n output high-impedance interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTCR ) </loc>
+//      <o.6..6> HIZIEN
+//        <0=> 0: Disable = Disable TIMER3n output high-impedance interrupt.
+//        <1=> 1: Enable = Enable TIMER3n output high-impedance interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER3n_INTCR_T3nCIEN  -------------------------------
+// SVD Line: 16544
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nCIEN
+//    <name> T3nCIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x53000028) \nTIMER3n Capture Interrupt Enable\n0 : Disable = Disable TIMER3n capture interrupt.\n1 : Enable = Enable TIMER3n capture interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTCR ) </loc>
+//      <o.5..5> T3nCIEN
+//        <0=> 0: Disable = Disable TIMER3n capture interrupt.
+//        <1=> 1: Enable = Enable TIMER3n capture interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER3n_INTCR_T3nBTIEN  -------------------------------
+// SVD Line: 16562
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nBTIEN
+//    <name> T3nBTIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x53000028) \nTIMER3n Bottom Interrupt Enable\n0 : Disable = Disable TIMER3n bottom interrupt.\n1 : Enable = Enable TIMER3n bottom interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTCR ) </loc>
+//      <o.4..4> T3nBTIEN
+//        <0=> 0: Disable = Disable TIMER3n bottom interrupt.
+//        <1=> 1: Enable = Enable TIMER3n bottom interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER3n_INTCR_T3nPMIEN  -------------------------------
+// SVD Line: 16580
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nPMIEN
+//    <name> T3nPMIEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x53000028) \nTIMER3n Period Match Interrupt Enable\n0 : Disable = Disable TIMER3n period interrupt.\n1 : Enable = Enable TIMER3n period interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTCR ) </loc>
+//      <o.3..3> T3nPMIEN
+//        <0=> 0: Disable = Disable TIMER3n period interrupt.
+//        <1=> 1: Enable = Enable TIMER3n period interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER3n_INTCR_T3nAMIEN  -------------------------------
+// SVD Line: 16598
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nAMIEN
+//    <name> T3nAMIEN </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x53000028) \nTIMER3n A-ch Match Interrupt Enable\n0 : Disable = Disable TIMER3n A-ch match interrupt.\n1 : Enable = Enable TIMER3n A-ch match interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTCR ) </loc>
+//      <o.2..2> T3nAMIEN
+//        <0=> 0: Disable = Disable TIMER3n A-ch match interrupt.
+//        <1=> 1: Enable = Enable TIMER3n A-ch match interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER3n_INTCR_T3nBMIEN  -------------------------------
+// SVD Line: 16616
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nBMIEN
+//    <name> T3nBMIEN </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x53000028) \nTIMER3n B-ch Match Interrupt Enable\n0 : Disable = Disable TIMER3n B-ch match interrupt.\n1 : Enable = Enable TIMER3n B-ch match interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTCR ) </loc>
+//      <o.1..1> T3nBMIEN
+//        <0=> 0: Disable = Disable TIMER3n B-ch match interrupt.
+//        <1=> 1: Enable = Enable TIMER3n B-ch match interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER3n_INTCR_T3nCMIEN  -------------------------------
+// SVD Line: 16634
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nCMIEN
+//    <name> T3nCMIEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x53000028) \nTIMER3n C-ch Match Interrupt Enable\n0 : Disable = Disable TIMER3n C-ch match interrupt.\n1 : Enable = Enable TIMER3n C-ch match interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTCR ) </loc>
+//      <o.0..0> T3nCMIEN
+//        <0=> 0: Disable = Disable TIMER3n C-ch match interrupt.
+//        <1=> 1: Enable = Enable TIMER3n C-ch match interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER3n_INTCR  ---------------------------------
+// SVD Line: 16517
+
+//  <rtree> SFDITEM_REG__TIMER3n_INTCR
+//    <name> INTCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000028) TIMER3n Interrupt Control Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_INTCR >> 0) & 0xFFFFFFFF), ((TIMER3n_INTCR = (TIMER3n_INTCR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_INTCR_HIZIEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nBTIEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nPMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nAMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nBMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTCR_T3nCMIEN </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: TIMER3n_INTFLAG  -----------------------------
+// SVD Line: 16654
+
+unsigned int TIMER3n_INTFLAG __AT (0x5300002C);
+
+
+
+// --------------------------  Field Item: TIMER3n_INTFLAG_HIZIFLAG  ------------------------------
+// SVD Line: 16663
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTFLAG_HIZIFLAG
+//    <name> HIZIFLAG </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x5300002C) \nTIMER3n Output High-Impedance Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTFLAG ) </loc>
+//      <o.6..6> HIZIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER3n_INTFLAG_T3nCIFLAG  -----------------------------
+// SVD Line: 16681
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nCIFLAG
+//    <name> T3nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x5300002C) \nTIMER3n Capture Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTFLAG ) </loc>
+//      <o.5..5> T3nCIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER3n_INTFLAG_T3nBTIFLAG  -----------------------------
+// SVD Line: 16699
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nBTIFLAG
+//    <name> T3nBTIFLAG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x5300002C) \nTIMER3n Bottom Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTFLAG ) </loc>
+//      <o.4..4> T3nBTIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER3n_INTFLAG_T3nPMIFLAG  -----------------------------
+// SVD Line: 16717
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nPMIFLAG
+//    <name> T3nPMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x5300002C) \nTIMER3n Period Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTFLAG ) </loc>
+//      <o.3..3> T3nPMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER3n_INTFLAG_T3nAMIFLAG  -----------------------------
+// SVD Line: 16735
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nAMIFLAG
+//    <name> T3nAMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x5300002C) \nTIMER3n A-ch Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTFLAG ) </loc>
+//      <o.2..2> T3nAMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER3n_INTFLAG_T3nBMIFLAG  -----------------------------
+// SVD Line: 16753
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nBMIFLAG
+//    <name> T3nBMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x5300002C) \nTIMER3n B-ch Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTFLAG ) </loc>
+//      <o.1..1> T3nBMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER3n_INTFLAG_T3nCMIFLAG  -----------------------------
+// SVD Line: 16771
+
+//  <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nCMIFLAG
+//    <name> T3nCMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x5300002C) \nTIMER3n C-ch Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_INTFLAG ) </loc>
+//      <o.0..0> T3nCMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: TIMER3n_INTFLAG  --------------------------------
+// SVD Line: 16654
+
+//  <rtree> SFDITEM_REG__TIMER3n_INTFLAG
+//    <name> INTFLAG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x5300002C) TIMER3n Interrupt Flag Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_INTFLAG >> 0) & 0xFFFFFFFF), ((TIMER3n_INTFLAG = (TIMER3n_INTFLAG & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_INTFLAG_HIZIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nBTIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nPMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nAMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nBMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_INTFLAG_T3nCMIFLAG </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER3n_HIZCR  ------------------------------
+// SVD Line: 16791
+
+unsigned int TIMER3n_HIZCR __AT (0x53000030);
+
+
+
+// -----------------------------  Field Item: TIMER3n_HIZCR_HIZEN  --------------------------------
+// SVD Line: 16800
+
+//  <item> SFDITEM_FIELD__TIMER3n_HIZCR_HIZEN
+//    <name> HIZEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x53000030) \nPWM3nxA/PWM3nxB Output High-Impedance Enable\n0 : Disable = Disable to control the output high-impedance.\n1 : Enable = Enable to control the output high-impedance. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_HIZCR ) </loc>
+//      <o.7..7> HIZEN
+//        <0=> 0: Disable = Disable to control the output high-impedance.
+//        <1=> 1: Enable = Enable to control the output high-impedance.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_HIZCR_HIZSW  --------------------------------
+// SVD Line: 16818
+
+//  <item> SFDITEM_FIELD__TIMER3n_HIZCR_HIZSW
+//    <name> HIZSW </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x53000030) \nHigh-Impedance Output Software Setting\n0 : NoEffect = No effect.\n1 : HiZ = PWM3nxA/PWM3nxB pins go into high impedance. (Automatically cleared to '0' after operation) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_HIZCR ) </loc>
+//      <o.4..4> HIZSW
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: HiZ = PWM3nxA/PWM3nxB pins go into high impedance. (Automatically cleared to '0' after operation)
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER3n_HIZCR_HEDGE  --------------------------------
+// SVD Line: 16836
+
+//  <item> SFDITEM_FIELD__TIMER3n_HIZCR_HEDGE
+//    <name> HEDGE </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x53000030) \nHigh-Impedance Edge Selection\n0 : FallingEdge = Falling edge of the BLNK pin.\n1 : RisingEdge = Rising edge of the BLNK pin. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_HIZCR ) </loc>
+//      <o.2..2> HEDGE
+//        <0=> 0: FallingEdge = Falling edge of the BLNK pin.
+//        <1=> 1: RisingEdge = Rising edge of the BLNK pin.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER3n_HIZCR_HIZSTA  --------------------------------
+// SVD Line: 16854
+
+//  <item> SFDITEM_FIELD__TIMER3n_HIZCR_HIZSTA
+//    <name> HIZSTA </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x53000030) \nHigh-Impedance Status\n0 : NoHiZ = Indicates that the pins are not under a Hi-Z state.\n1 : HiZ = Indicates that the pins are under a Hi-Z state. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_HIZCR ) </loc>
+//      <o.1..1> HIZSTA
+//        <0=> 0: NoHiZ = Indicates that the pins are not under a Hi-Z state.
+//        <1=> 1: HiZ = Indicates that the pins are under a Hi-Z state.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER3n_HIZCR_HIZCLR  --------------------------------
+// SVD Line: 16872
+
+//  <item> SFDITEM_FIELD__TIMER3n_HIZCR_HIZCLR
+//    <name> HIZCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x53000030) \nHigh-Impedance Output Clear\n0 : NoEffect = No effect.\n1 : Clear = Clear high-impedance output. (The PWM3nxA/PWM3nxB pins returns as output and this bit is automatically cleared to '0' after operation.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_HIZCR ) </loc>
+//      <o.0..0> HIZCLR
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear high-impedance output. (The PWM3nxA/PWM3nxB pins returns as output and this bit is automatically cleared to '0' after operation.)
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER3n_HIZCR  ---------------------------------
+// SVD Line: 16791
+
+//  <rtree> SFDITEM_REG__TIMER3n_HIZCR
+//    <name> HIZCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000030) TIMER3n High-Impedance Control Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_HIZCR >> 0) & 0xFFFFFFFF), ((TIMER3n_HIZCR = (TIMER3n_HIZCR & ~(0x95UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x95) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_HIZCR_HIZEN </item>
+//    <item> SFDITEM_FIELD__TIMER3n_HIZCR_HIZSW </item>
+//    <item> SFDITEM_FIELD__TIMER3n_HIZCR_HEDGE </item>
+//    <item> SFDITEM_FIELD__TIMER3n_HIZCR_HIZSTA </item>
+//    <item> SFDITEM_FIELD__TIMER3n_HIZCR_HIZCLR </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER3n_ADTCR  ------------------------------
+// SVD Line: 16892
+
+unsigned int TIMER3n_ADTCR __AT (0x53000034);
+
+
+
+// ----------------------------  Field Item: TIMER3n_ADTCR_T3nBTTG  -------------------------------
+// SVD Line: 16901
+
+//  <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nBTTG
+//    <name> T3nBTTG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x53000034) \nSelect TIMER3n Bottom for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by bottom.\n1 : Enable = Enable ADC trigger signal generator by bottom. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_ADTCR ) </loc>
+//      <o.4..4> T3nBTTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by bottom.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by bottom.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER3n_ADTCR_T3nPMTG  -------------------------------
+// SVD Line: 16919
+
+//  <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nPMTG
+//    <name> T3nPMTG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x53000034) \nSelect TIMER3n Period Match for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by period match.\n1 : Enable = Enable ADC trigger signal generator by period match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_ADTCR ) </loc>
+//      <o.3..3> T3nPMTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by period match.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by period match.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER3n_ADTCR_T3nAMTG  -------------------------------
+// SVD Line: 16937
+
+//  <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nAMTG
+//    <name> T3nAMTG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x53000034) \nSelect TIMER3n A-ch Match for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by A-ch match.\n1 : Enable = Enable ADC trigger signal generator by A-ch match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_ADTCR ) </loc>
+//      <o.2..2> T3nAMTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by A-ch match.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by A-ch match.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER3n_ADTCR_T3nBMTG  -------------------------------
+// SVD Line: 16955
+
+//  <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nBMTG
+//    <name> T3nBMTG </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x53000034) \nSelect TIMER3n B-ch Match for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by B-ch match.\n1 : Enable = Enable ADC trigger signal generator by B-ch match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_ADTCR ) </loc>
+//      <o.1..1> T3nBMTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by B-ch match.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by B-ch match.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER3n_ADTCR_T3nCMTG  -------------------------------
+// SVD Line: 16973
+
+//  <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nCMTG
+//    <name> T3nCMTG </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x53000034) \nSelect TIMER3n C-ch Match for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by C-ch match.\n1 : Enable = Enable ADC trigger signal generator by C-ch match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER3n_ADTCR ) </loc>
+//      <o.0..0> T3nCMTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by C-ch match.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by C-ch match.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER3n_ADTCR  ---------------------------------
+// SVD Line: 16892
+
+//  <rtree> SFDITEM_REG__TIMER3n_ADTCR
+//    <name> ADTCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000034) TIMER3n ADC Trigger Control Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_ADTCR >> 0) & 0xFFFFFFFF), ((TIMER3n_ADTCR = (TIMER3n_ADTCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nBTTG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nPMTG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nAMTG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nBMTG </item>
+//    <item> SFDITEM_FIELD__TIMER3n_ADTCR_T3nCMTG </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER3n_ADTDR  ------------------------------
+// SVD Line: 16993
+
+unsigned int TIMER3n_ADTDR __AT (0x53000038);
+
+
+
+// ----------------------------  Field Item: TIMER3n_ADTDR_ADTDATA  -------------------------------
+// SVD Line: 17002
+
+//  <item> SFDITEM_FIELD__TIMER3n_ADTDR_ADTDATA
+//    <name> ADTDATA </name>
+//    <rw> 
+//    <i> [Bits 13..0] RW (@ 0x53000038) TIMER3n ADC Trigger Generation Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER3n_ADTDR >> 0) & 0x3FFF), ((TIMER3n_ADTDR = (TIMER3n_ADTDR & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER3n_ADTDR  ---------------------------------
+// SVD Line: 16993
+
+//  <rtree> SFDITEM_REG__TIMER3n_ADTDR
+//    <name> ADTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x53000038) TIMER3n ADC Trigger Generator Data Register </i>
+//    <loc> ( (unsigned int)((TIMER3n_ADTDR >> 0) & 0xFFFFFFFF), ((TIMER3n_ADTDR = (TIMER3n_ADTDR & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER3n_ADTDR_ADTDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER3n  ------------------------------------
+// SVD Line: 15844
+
+//  <view> TIMER3n
+//    <name> TIMER3n </name>
+//    <item> SFDITEM_REG__TIMER3n_CR </item>
+//    <item> SFDITEM_REG__TIMER3n_PDR </item>
+//    <item> SFDITEM_REG__TIMER3n_ADR </item>
+//    <item> SFDITEM_REG__TIMER3n_BDR </item>
+//    <item> SFDITEM_REG__TIMER3n_CDR </item>
+//    <item> SFDITEM_REG__TIMER3n_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER3n_PREDR </item>
+//    <item> SFDITEM_REG__TIMER3n_CNT </item>
+//    <item> SFDITEM_REG__TIMER3n_OUTCR </item>
+//    <item> SFDITEM_REG__TIMER3n_DLY </item>
+//    <item> SFDITEM_REG__TIMER3n_INTCR </item>
+//    <item> SFDITEM_REG__TIMER3n_INTFLAG </item>
+//    <item> SFDITEM_REG__TIMER3n_HIZCR </item>
+//    <item> SFDITEM_REG__TIMER3n_ADTCR </item>
+//    <item> SFDITEM_REG__TIMER3n_ADTDR </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: TIMER30_CR  -------------------------------
+// SVD Line: 15858
+
+unsigned int TIMER30_CR __AT (0x40002400);
+
+
+
+// ------------------------------  Field Item: TIMER30_CR_T3nEN  ----------------------------------
+// SVD Line: 15867
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_T3nEN
+//    <name> T3nEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002400) \nTIMER3n Operation Enable\n0 : Disable = Disable TIMER3n Operation.\n1 : Enable = Enable TIMER3n Operation. (Counter Clear and Start) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.15..15> T3nEN
+//        <0=> 0: Disable = Disable TIMER3n Operation.
+//        <1=> 1: Enable = Enable TIMER3n Operation. (Counter Clear and Start)
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER30_CR_T3nCLK  ---------------------------------
+// SVD Line: 15885
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_T3nCLK
+//    <name> T3nCLK </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002400) \nTIMER3n Clock Selection\n0 : IntPrescaledClock = Select an Internal Prescaler Clock.\n1 : ExtClock = Select an External Clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.14..14> T3nCLK
+//        <0=> 0: IntPrescaledClock = Select an Internal Prescaler Clock.
+//        <1=> 1: ExtClock = Select an External Clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER30_CR_T3nMS  ----------------------------------
+// SVD Line: 15903
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_T3nMS
+//    <name> T3nMS </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40002400) \nTIMER3n Operation Mode Selection\n0 : IntervalMode = Interval mode. (All match interrupts can occur)\n1 : CaptureMode = Capture mode. (The Period-match interrupt can occur)\n2 : BackToBackMode = Back-to-back mode. (All interrupts can occur)\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.13..12> T3nMS
+//        <0=> 0: IntervalMode = Interval mode. (All match interrupts can occur)
+//        <1=> 1: CaptureMode = Capture mode. (The Period-match interrupt can occur)
+//        <2=> 2: BackToBackMode = Back-to-back mode. (All interrupts can occur)
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER30_CR_T3nECE  ---------------------------------
+// SVD Line: 15926
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_T3nECE
+//    <name> T3nECE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002400) \nTIMER3n External Clock Edge Selection\n0 : FallingEdge = Select falling edge of external clock.\n1 : RisingEdge = Select rising edge of external clock. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.11..11> T3nECE
+//        <0=> 0: FallingEdge = Select falling edge of external clock.
+//        <1=> 1: RisingEdge = Select rising edge of external clock.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER30_CR_FORCA  ----------------------------------
+// SVD Line: 15944
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_FORCA
+//    <name> FORCA </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40002400) \nTIMER3n Output Mode Selection\n0 : AllChannelMode = 6-Channel mode. (The PWM3nxA/PWM3nxB pins are outputs according to the TIMER30_xDR registers, respectively.)\n1 : AChannelMode = Force A-Channel mode. (All PWM3nxA/PWM3nxB pins are outputs according only to the TIMER30_ADR register.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.10..10> FORCA
+//        <0=> 0: AllChannelMode = 6-Channel mode. (The PWM3nxA/PWM3nxB pins are outputs according to the TIMER30_xDR registers, respectively.)
+//        <1=> 1: AChannelMode = Force A-Channel mode. (All PWM3nxA/PWM3nxB pins are outputs according only to the TIMER30_ADR register.)
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER30_CR_DLYEN  ----------------------------------
+// SVD Line: 15962
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_DLYEN
+//    <name> DLYEN </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40002400) \nDelay Time Insertion Enable\n0 : Disable = Disable delay time insertion to the PWM3nxA/PWM3nxB.\n1 : Enable = Enable delay time insertion to the PWM3nxA/PWM3nxB. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.9..9> DLYEN
+//        <0=> 0: Disable = Disable delay time insertion to the PWM3nxA/PWM3nxB.
+//        <1=> 1: Enable = Enable delay time insertion to the PWM3nxA/PWM3nxB.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER30_CR_DLYPOS  ---------------------------------
+// SVD Line: 15980
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_DLYPOS
+//    <name> DLYPOS </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002400) \nDelay Time Insertion Position\n0 : FrontABehindB = Insert in front of PWM3nxA and behind PWM3nxB pins.\n1 : BehindAFrontB = Insert behind PWM3nxA and in front of PWM3nxB pins. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.8..8> DLYPOS
+//        <0=> 0: FrontABehindB = Insert in front of PWM3nxA and behind PWM3nxB pins.
+//        <1=> 1: BehindAFrontB = Insert behind PWM3nxA and in front of PWM3nxB pins.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_CR_T3nCPOL  ---------------------------------
+// SVD Line: 15998
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_T3nCPOL
+//    <name> T3nCPOL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40002400) \nTIMER3n Capture Polarity Selection\n0 : FallingEdge = Capture on falling edge.\n1 : RisingEdge = Capture on rising edge.\n2 : BothEdge = Capture on both falling and rising edge.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.7..6> T3nCPOL
+//        <0=> 0: FallingEdge = Capture on falling edge.
+//        <1=> 1: RisingEdge = Capture on rising edge.
+//        <2=> 2: BothEdge = Capture on both falling and rising edge.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: TIMER30_CR_UPDT  ----------------------------------
+// SVD Line: 16021
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_UPDT
+//    <name> UPDT </name>
+//    <rw> 
+//    <i> [Bits 5..4] RW (@ 0x40002400) \nData Reload Time Selection\n0 : AtWriting = Update data to buffer at the time of writing.\n1 : AtPeriodMatch = Update data to buffer at period match.\n2 : AtBottom = Update data to buffer at bottom.\n3 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.5..4> UPDT
+//        <0=> 0: AtWriting = Update data to buffer at the time of writing.
+//        <1=> 1: AtPeriodMatch = Update data to buffer at period match.
+//        <2=> 2: AtBottom = Update data to buffer at bottom.
+//        <3=> 3: 
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: TIMER30_CR_PMOC  ----------------------------------
+// SVD Line: 16044
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_PMOC
+//    <name> PMOC </name>
+//    <rw> 
+//    <i> [Bits 3..1] RW (@ 0x40002400) \nPeriod Match Interrupt Occurrence Selection\n0 : Every1PeriodMatch = Once every 1 period match.\n1 : Every2PeriodMatch = Once every 2 period match.\n2 : Every3PeriodMatch = Once every 3 period match.\n3 : Every4PeriodMatch = Once every 4 period match.\n4 : Every5PeriodMatch = Once every 5 period match.\n5 : Every6PeriodMatch = Once every 6 period match.\n6 : Every7PeriodMatch = Once every 7 period match.\n7 : Every8PeriodMatch = Once every 8 period match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.3..1> PMOC
+//        <0=> 0: Every1PeriodMatch = Once every 1 period match.
+//        <1=> 1: Every2PeriodMatch = Once every 2 period match.
+//        <2=> 2: Every3PeriodMatch = Once every 3 period match.
+//        <3=> 3: Every4PeriodMatch = Once every 4 period match.
+//        <4=> 4: Every5PeriodMatch = Once every 5 period match.
+//        <5=> 5: Every6PeriodMatch = Once every 6 period match.
+//        <6=> 6: Every7PeriodMatch = Once every 7 period match.
+//        <7=> 7: Every8PeriodMatch = Once every 8 period match.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: TIMER30_CR_T3nCLR  ---------------------------------
+// SVD Line: 16092
+
+//  <item> SFDITEM_FIELD__TIMER30_CR_T3nCLR
+//    <name> T3nCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002400) \nTIMER3n Counter and Prescaler Clear\n0 : NoEffect = No effect.\n1 : Clear = Clear TIMER3n counter and prescaler. (Automatically cleared to '0b' after operation) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_CR ) </loc>
+//      <o.0..0> T3nCLR
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear TIMER3n counter and prescaler. (Automatically cleared to '0b' after operation)
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER30_CR  -----------------------------------
+// SVD Line: 15858
+
+//  <rtree> SFDITEM_REG__TIMER30_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002400) TIMER3n Control Register </i>
+//    <loc> ( (unsigned int)((TIMER30_CR >> 0) & 0xFFFFFFFF), ((TIMER30_CR = (TIMER30_CR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_CR_T3nEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_T3nCLK </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_T3nMS </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_T3nECE </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_FORCA </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_DLYEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_DLYPOS </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_T3nCPOL </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_UPDT </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_PMOC </item>
+//    <item> SFDITEM_FIELD__TIMER30_CR_T3nCLR </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER30_PDR  -------------------------------
+// SVD Line: 16112
+
+unsigned int TIMER30_PDR __AT (0x40002404);
+
+
+
+// ------------------------------  Field Item: TIMER30_PDR_PDATA  ---------------------------------
+// SVD Line: 16121
+
+//  <item> SFDITEM_FIELD__TIMER30_PDR_PDATA
+//    <name> PDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002404) TIMER3n Period Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_PDR >> 0) & 0xFFFF), ((TIMER30_PDR = (TIMER30_PDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER30_PDR  ----------------------------------
+// SVD Line: 16112
+
+//  <rtree> SFDITEM_REG__TIMER30_PDR
+//    <name> PDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002404) TIMER3n Period Data Register </i>
+//    <loc> ( (unsigned int)((TIMER30_PDR >> 0) & 0xFFFFFFFF), ((TIMER30_PDR = (TIMER30_PDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_PDR_PDATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER30_ADR  -------------------------------
+// SVD Line: 16129
+
+unsigned int TIMER30_ADR __AT (0x40002408);
+
+
+
+// ------------------------------  Field Item: TIMER30_ADR_ADATA  ---------------------------------
+// SVD Line: 16138
+
+//  <item> SFDITEM_FIELD__TIMER30_ADR_ADATA
+//    <name> ADATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002408) TIMER3n A Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_ADR >> 0) & 0xFFFF), ((TIMER30_ADR = (TIMER30_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER30_ADR  ----------------------------------
+// SVD Line: 16129
+
+//  <rtree> SFDITEM_REG__TIMER30_ADR
+//    <name> ADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002408) TIMER3n A Data Register </i>
+//    <loc> ( (unsigned int)((TIMER30_ADR >> 0) & 0xFFFFFFFF), ((TIMER30_ADR = (TIMER30_ADR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_ADR_ADATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER30_BDR  -------------------------------
+// SVD Line: 16146
+
+unsigned int TIMER30_BDR __AT (0x4000240C);
+
+
+
+// ------------------------------  Field Item: TIMER30_BDR_BDATA  ---------------------------------
+// SVD Line: 16155
+
+//  <item> SFDITEM_FIELD__TIMER30_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x4000240C) TIMER3n B Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_BDR >> 0) & 0xFFFF), ((TIMER30_BDR = (TIMER30_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER30_BDR  ----------------------------------
+// SVD Line: 16146
+
+//  <rtree> SFDITEM_REG__TIMER30_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000240C) TIMER3n B Data Register </i>
+//    <loc> ( (unsigned int)((TIMER30_BDR >> 0) & 0xFFFFFFFF), ((TIMER30_BDR = (TIMER30_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER30_CDR  -------------------------------
+// SVD Line: 16163
+
+unsigned int TIMER30_CDR __AT (0x40002410);
+
+
+
+// ------------------------------  Field Item: TIMER30_CDR_CDATA  ---------------------------------
+// SVD Line: 16172
+
+//  <item> SFDITEM_FIELD__TIMER30_CDR_CDATA
+//    <name> CDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40002410) TIMER3n C Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_CDR >> 0) & 0xFFFF), ((TIMER30_CDR = (TIMER30_CDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER30_CDR  ----------------------------------
+// SVD Line: 16163
+
+//  <rtree> SFDITEM_REG__TIMER30_CDR
+//    <name> CDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002410) TIMER3n C Data Register </i>
+//    <loc> ( (unsigned int)((TIMER30_CDR >> 0) & 0xFFFFFFFF), ((TIMER30_CDR = (TIMER30_CDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_CDR_CDATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER30_CAPDR  ------------------------------
+// SVD Line: 16180
+
+unsigned int TIMER30_CAPDR __AT (0x40002414);
+
+
+
+// -----------------------------  Field Item: TIMER30_CAPDR_CAPD  ---------------------------------
+// SVD Line: 16189
+
+//  <item> SFDITEM_FIELD__TIMER30_CAPDR_CAPD
+//    <name> CAPD </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x40002414) TIMER3n Capture Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_CAPDR >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER30_CAPDR  ---------------------------------
+// SVD Line: 16180
+
+//  <rtree> SFDITEM_REG__TIMER30_CAPDR
+//    <name> CAPDR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40002414) TIMER3n Capture Data Register </i>
+//    <loc> ( (unsigned int)((TIMER30_CAPDR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_CAPDR_CAPD </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER30_PREDR  ------------------------------
+// SVD Line: 16197
+
+unsigned int TIMER30_PREDR __AT (0x40002418);
+
+
+
+// -----------------------------  Field Item: TIMER30_PREDR_PRED  ---------------------------------
+// SVD Line: 16206
+
+//  <item> SFDITEM_FIELD__TIMER30_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40002418) TIMER3n Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_PREDR >> 0) & 0xFFF), ((TIMER30_PREDR = (TIMER30_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER30_PREDR  ---------------------------------
+// SVD Line: 16197
+
+//  <rtree> SFDITEM_REG__TIMER30_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002418) TIMER3n Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((TIMER30_PREDR >> 0) & 0xFFFFFFFF), ((TIMER30_PREDR = (TIMER30_PREDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER30_CNT  -------------------------------
+// SVD Line: 16214
+
+unsigned int TIMER30_CNT __AT (0x4000241C);
+
+
+
+// -------------------------------  Field Item: TIMER30_CNT_CNT  ----------------------------------
+// SVD Line: 16223
+
+//  <item> SFDITEM_FIELD__TIMER30_CNT_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x4000241C) TIMER3n Counter </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_CNT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER30_CNT  ----------------------------------
+// SVD Line: 16214
+
+//  <rtree> SFDITEM_REG__TIMER30_CNT
+//    <name> CNT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x4000241C) TIMER3n Counter Register </i>
+//    <loc> ( (unsigned int)((TIMER30_CNT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_CNT_CNT </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER30_OUTCR  ------------------------------
+// SVD Line: 16231
+
+unsigned int TIMER30_OUTCR __AT (0x40002420);
+
+
+
+// ----------------------------  Field Item: TIMER30_OUTCR_WTIDKY  --------------------------------
+// SVD Line: 16240
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x40002420) Write Identification Key </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_OUTCR >> 16) & 0x0), ((TIMER30_OUTCR = (TIMER30_OUTCR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_POLB  ---------------------------------
+// SVD Line: 16246
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_POLB
+//    <name> POLB </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002420) \nPWM3nxB Output Polarity Selection\n0 : StartLow = Low level start. (The PWM3nxB pins are started with low level after counting.)\n1 : StartHigh = High level start. (The PWM3nxB pins are started with high level after counting) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.15..15> POLB
+//        <0=> 0: StartLow = Low level start. (The PWM3nxB pins are started with low level after counting.)
+//        <1=> 1: StartHigh = High level start. (The PWM3nxB pins are started with high level after counting)
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_POLA  ---------------------------------
+// SVD Line: 16264
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_POLA
+//    <name> POLA </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002420) \nPWM3nxA Output Polarity Selection\n0 : StartLow = Low level start. (The PWM3nxA pins are started with low level after counting.)\n1 : StartHigh = High level start. (The PWM3nxA pins are started with high level after counting) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.14..14> POLA
+//        <0=> 0: StartLow = Low level start. (The PWM3nxA pins are started with low level after counting.)
+//        <1=> 1: StartHigh = High level start. (The PWM3nxA pins are started with high level after counting)
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_PABOE  --------------------------------
+// SVD Line: 16282
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_PABOE
+//    <name> PABOE </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x40002420) \nPWM3nAB Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.13..13> PABOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_PBBOE  --------------------------------
+// SVD Line: 16300
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_PBBOE
+//    <name> PBBOE </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x40002420) \nPWM3nBB Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.12..12> PBBOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_PCBOE  --------------------------------
+// SVD Line: 16318
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_PCBOE
+//    <name> PCBOE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002420) \nPWM3nCB Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.11..11> PCBOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_PAAOE  --------------------------------
+// SVD Line: 16336
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_PAAOE
+//    <name> PAAOE </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40002420) \nPWM3nAA Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.10..10> PAAOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_PBAOE  --------------------------------
+// SVD Line: 16354
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_PBAOE
+//    <name> PBAOE </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40002420) \nPWM3nBA Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.9..9> PBAOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_PCAOE  --------------------------------
+// SVD Line: 16372
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_PCAOE
+//    <name> PCAOE </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002420) \nPWM3nCA Output Enable\n0 : Disable = Disable output.\n1 : Enable = Enable output. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.8..8> PCAOE
+//        <0=> 0: Disable = Disable output.
+//        <1=> 1: Enable = Enable output.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_LVLAB  --------------------------------
+// SVD Line: 16390
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLAB
+//    <name> LVLAB </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40002420) \nConfigure PWM3nAB Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.6..6> LVLAB
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_LVLBB  --------------------------------
+// SVD Line: 16408
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLBB
+//    <name> LVLBB </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002420) \nConfigure PWM3nBB Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.5..5> LVLBB
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_LVLCB  --------------------------------
+// SVD Line: 16426
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLCB
+//    <name> LVLCB </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002420) \nConfigure PWM3nCB Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.4..4> LVLCB
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_LVLAA  --------------------------------
+// SVD Line: 16444
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLAA
+//    <name> LVLAA </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002420) \nConfigure PWM3nAA Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.2..2> LVLAA
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_LVLBA  --------------------------------
+// SVD Line: 16462
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLBA
+//    <name> LVLBA </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002420) \nConfigure PWM3nBA Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.1..1> LVLBA
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_OUTCR_LVLCA  --------------------------------
+// SVD Line: 16480
+
+//  <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLCA
+//    <name> LVLCA </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002420) \nConfigure PWM3nCA Output when Disable\n0 : Low = Low level.\n1 : High = High level. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_OUTCR ) </loc>
+//      <o.0..0> LVLCA
+//        <0=> 0: Low = Low level.
+//        <1=> 1: High = High level.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER30_OUTCR  ---------------------------------
+// SVD Line: 16231
+
+//  <rtree> SFDITEM_REG__TIMER30_OUTCR
+//    <name> OUTCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002420) TIMER3n Output Control Register </i>
+//    <loc> ( (unsigned int)((TIMER30_OUTCR >> 0) & 0xFFFFFFFF), ((TIMER30_OUTCR = (TIMER30_OUTCR & ~(0xFFFFFF77UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF77) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_POLB </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_POLA </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_PABOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_PBBOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_PCBOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_PAAOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_PBAOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_PCAOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLAB </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLBB </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLCB </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLAA </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLBA </item>
+//    <item> SFDITEM_FIELD__TIMER30_OUTCR_LVLCA </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: TIMER30_DLY  -------------------------------
+// SVD Line: 16500
+
+unsigned int TIMER30_DLY __AT (0x40002424);
+
+
+
+// -------------------------------  Field Item: TIMER30_DLY_DLY  ----------------------------------
+// SVD Line: 16509
+
+//  <item> SFDITEM_FIELD__TIMER30_DLY_DLY
+//    <name> DLY </name>
+//    <rw> 
+//    <i> [Bits 9..0] RW (@ 0x40002424) TIMER3n PWM Delay Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_DLY >> 0) & 0x3FF), ((TIMER30_DLY = (TIMER30_DLY & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: TIMER30_DLY  ----------------------------------
+// SVD Line: 16500
+
+//  <rtree> SFDITEM_REG__TIMER30_DLY
+//    <name> DLY </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002424) TIMER3n PWM Output Delay Data Register </i>
+//    <loc> ( (unsigned int)((TIMER30_DLY >> 0) & 0xFFFFFFFF), ((TIMER30_DLY = (TIMER30_DLY & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_DLY_DLY </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER30_INTCR  ------------------------------
+// SVD Line: 16517
+
+unsigned int TIMER30_INTCR __AT (0x40002428);
+
+
+
+// ----------------------------  Field Item: TIMER30_INTCR_HIZIEN  --------------------------------
+// SVD Line: 16526
+
+//  <item> SFDITEM_FIELD__TIMER30_INTCR_HIZIEN
+//    <name> HIZIEN </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40002428) \nTIMER3n Output High-Impedance Interrupt Enable\n0 : Disable = Disable TIMER3n output high-impedance interrupt.\n1 : Enable = Enable TIMER3n output high-impedance interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTCR ) </loc>
+//      <o.6..6> HIZIEN
+//        <0=> 0: Disable = Disable TIMER3n output high-impedance interrupt.
+//        <1=> 1: Enable = Enable TIMER3n output high-impedance interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER30_INTCR_T3nCIEN  -------------------------------
+// SVD Line: 16544
+
+//  <item> SFDITEM_FIELD__TIMER30_INTCR_T3nCIEN
+//    <name> T3nCIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002428) \nTIMER3n Capture Interrupt Enable\n0 : Disable = Disable TIMER3n capture interrupt.\n1 : Enable = Enable TIMER3n capture interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTCR ) </loc>
+//      <o.5..5> T3nCIEN
+//        <0=> 0: Disable = Disable TIMER3n capture interrupt.
+//        <1=> 1: Enable = Enable TIMER3n capture interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_INTCR_T3nBTIEN  -------------------------------
+// SVD Line: 16562
+
+//  <item> SFDITEM_FIELD__TIMER30_INTCR_T3nBTIEN
+//    <name> T3nBTIEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002428) \nTIMER3n Bottom Interrupt Enable\n0 : Disable = Disable TIMER3n bottom interrupt.\n1 : Enable = Enable TIMER3n bottom interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTCR ) </loc>
+//      <o.4..4> T3nBTIEN
+//        <0=> 0: Disable = Disable TIMER3n bottom interrupt.
+//        <1=> 1: Enable = Enable TIMER3n bottom interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_INTCR_T3nPMIEN  -------------------------------
+// SVD Line: 16580
+
+//  <item> SFDITEM_FIELD__TIMER30_INTCR_T3nPMIEN
+//    <name> T3nPMIEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002428) \nTIMER3n Period Match Interrupt Enable\n0 : Disable = Disable TIMER3n period interrupt.\n1 : Enable = Enable TIMER3n period interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTCR ) </loc>
+//      <o.3..3> T3nPMIEN
+//        <0=> 0: Disable = Disable TIMER3n period interrupt.
+//        <1=> 1: Enable = Enable TIMER3n period interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_INTCR_T3nAMIEN  -------------------------------
+// SVD Line: 16598
+
+//  <item> SFDITEM_FIELD__TIMER30_INTCR_T3nAMIEN
+//    <name> T3nAMIEN </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002428) \nTIMER3n A-ch Match Interrupt Enable\n0 : Disable = Disable TIMER3n A-ch match interrupt.\n1 : Enable = Enable TIMER3n A-ch match interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTCR ) </loc>
+//      <o.2..2> T3nAMIEN
+//        <0=> 0: Disable = Disable TIMER3n A-ch match interrupt.
+//        <1=> 1: Enable = Enable TIMER3n A-ch match interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_INTCR_T3nBMIEN  -------------------------------
+// SVD Line: 16616
+
+//  <item> SFDITEM_FIELD__TIMER30_INTCR_T3nBMIEN
+//    <name> T3nBMIEN </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002428) \nTIMER3n B-ch Match Interrupt Enable\n0 : Disable = Disable TIMER3n B-ch match interrupt.\n1 : Enable = Enable TIMER3n B-ch match interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTCR ) </loc>
+//      <o.1..1> T3nBMIEN
+//        <0=> 0: Disable = Disable TIMER3n B-ch match interrupt.
+//        <1=> 1: Enable = Enable TIMER3n B-ch match interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_INTCR_T3nCMIEN  -------------------------------
+// SVD Line: 16634
+
+//  <item> SFDITEM_FIELD__TIMER30_INTCR_T3nCMIEN
+//    <name> T3nCMIEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002428) \nTIMER3n C-ch Match Interrupt Enable\n0 : Disable = Disable TIMER3n C-ch match interrupt.\n1 : Enable = Enable TIMER3n C-ch match interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTCR ) </loc>
+//      <o.0..0> T3nCMIEN
+//        <0=> 0: Disable = Disable TIMER3n C-ch match interrupt.
+//        <1=> 1: Enable = Enable TIMER3n C-ch match interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER30_INTCR  ---------------------------------
+// SVD Line: 16517
+
+//  <rtree> SFDITEM_REG__TIMER30_INTCR
+//    <name> INTCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002428) TIMER3n Interrupt Control Register </i>
+//    <loc> ( (unsigned int)((TIMER30_INTCR >> 0) & 0xFFFFFFFF), ((TIMER30_INTCR = (TIMER30_INTCR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_INTCR_HIZIEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTCR_T3nCIEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTCR_T3nBTIEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTCR_T3nPMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTCR_T3nAMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTCR_T3nBMIEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTCR_T3nCMIEN </item>
+//  </rtree>
+//  
+
+
+// -------------------------  Register Item Address: TIMER30_INTFLAG  -----------------------------
+// SVD Line: 16654
+
+unsigned int TIMER30_INTFLAG __AT (0x4000242C);
+
+
+
+// --------------------------  Field Item: TIMER30_INTFLAG_HIZIFLAG  ------------------------------
+// SVD Line: 16663
+
+//  <item> SFDITEM_FIELD__TIMER30_INTFLAG_HIZIFLAG
+//    <name> HIZIFLAG </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x4000242C) \nTIMER3n Output High-Impedance Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTFLAG ) </loc>
+//      <o.6..6> HIZIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: TIMER30_INTFLAG_T3nCIFLAG  -----------------------------
+// SVD Line: 16681
+
+//  <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nCIFLAG
+//    <name> T3nCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x4000242C) \nTIMER3n Capture Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTFLAG ) </loc>
+//      <o.5..5> T3nCIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER30_INTFLAG_T3nBTIFLAG  -----------------------------
+// SVD Line: 16699
+
+//  <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nBTIFLAG
+//    <name> T3nBTIFLAG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x4000242C) \nTIMER3n Bottom Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTFLAG ) </loc>
+//      <o.4..4> T3nBTIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER30_INTFLAG_T3nPMIFLAG  -----------------------------
+// SVD Line: 16717
+
+//  <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nPMIFLAG
+//    <name> T3nPMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x4000242C) \nTIMER3n Period Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTFLAG ) </loc>
+//      <o.3..3> T3nPMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER30_INTFLAG_T3nAMIFLAG  -----------------------------
+// SVD Line: 16735
+
+//  <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nAMIFLAG
+//    <name> T3nAMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x4000242C) \nTIMER3n A-ch Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTFLAG ) </loc>
+//      <o.2..2> T3nAMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER30_INTFLAG_T3nBMIFLAG  -----------------------------
+// SVD Line: 16753
+
+//  <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nBMIFLAG
+//    <name> T3nBMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x4000242C) \nTIMER3n B-ch Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTFLAG ) </loc>
+//      <o.1..1> T3nBMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------  Field Item: TIMER30_INTFLAG_T3nCMIFLAG  -----------------------------
+// SVD Line: 16771
+
+//  <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nCMIFLAG
+//    <name> T3nCMIFLAG </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x4000242C) \nTIMER3n C-ch Match Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_INTFLAG ) </loc>
+//      <o.0..0> T3nCMIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred. The bit will be cleared to '0' when '1' is written to this bit.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: TIMER30_INTFLAG  --------------------------------
+// SVD Line: 16654
+
+//  <rtree> SFDITEM_REG__TIMER30_INTFLAG
+//    <name> INTFLAG </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000242C) TIMER3n Interrupt Flag Register </i>
+//    <loc> ( (unsigned int)((TIMER30_INTFLAG >> 0) & 0xFFFFFFFF), ((TIMER30_INTFLAG = (TIMER30_INTFLAG & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_INTFLAG_HIZIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nCIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nBTIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nPMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nAMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nBMIFLAG </item>
+//    <item> SFDITEM_FIELD__TIMER30_INTFLAG_T3nCMIFLAG </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER30_HIZCR  ------------------------------
+// SVD Line: 16791
+
+unsigned int TIMER30_HIZCR __AT (0x40002430);
+
+
+
+// -----------------------------  Field Item: TIMER30_HIZCR_HIZEN  --------------------------------
+// SVD Line: 16800
+
+//  <item> SFDITEM_FIELD__TIMER30_HIZCR_HIZEN
+//    <name> HIZEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40002430) \nPWM3nxA/PWM3nxB Output High-Impedance Enable\n0 : Disable = Disable to control the output high-impedance.\n1 : Enable = Enable to control the output high-impedance. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_HIZCR ) </loc>
+//      <o.7..7> HIZEN
+//        <0=> 0: Disable = Disable to control the output high-impedance.
+//        <1=> 1: Enable = Enable to control the output high-impedance.
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_HIZCR_HIZSW  --------------------------------
+// SVD Line: 16818
+
+//  <item> SFDITEM_FIELD__TIMER30_HIZCR_HIZSW
+//    <name> HIZSW </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002430) \nHigh-Impedance Output Software Setting\n0 : NoEffect = No effect.\n1 : HiZ = PWM3nxA/PWM3nxB pins go into high impedance. (Automatically cleared to '0' after operation) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_HIZCR ) </loc>
+//      <o.4..4> HIZSW
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: HiZ = PWM3nxA/PWM3nxB pins go into high impedance. (Automatically cleared to '0' after operation)
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: TIMER30_HIZCR_HEDGE  --------------------------------
+// SVD Line: 16836
+
+//  <item> SFDITEM_FIELD__TIMER30_HIZCR_HEDGE
+//    <name> HEDGE </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002430) \nHigh-Impedance Edge Selection\n0 : FallingEdge = Falling edge of the BLNK pin.\n1 : RisingEdge = Rising edge of the BLNK pin. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_HIZCR ) </loc>
+//      <o.2..2> HEDGE
+//        <0=> 0: FallingEdge = Falling edge of the BLNK pin.
+//        <1=> 1: RisingEdge = Rising edge of the BLNK pin.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER30_HIZCR_HIZSTA  --------------------------------
+// SVD Line: 16854
+
+//  <item> SFDITEM_FIELD__TIMER30_HIZCR_HIZSTA
+//    <name> HIZSTA </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x40002430) \nHigh-Impedance Status\n0 : NoHiZ = Indicates that the pins are not under a Hi-Z state.\n1 : HiZ = Indicates that the pins are under a Hi-Z state. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_HIZCR ) </loc>
+//      <o.1..1> HIZSTA
+//        <0=> 0: NoHiZ = Indicates that the pins are not under a Hi-Z state.
+//        <1=> 1: HiZ = Indicates that the pins are under a Hi-Z state.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER30_HIZCR_HIZCLR  --------------------------------
+// SVD Line: 16872
+
+//  <item> SFDITEM_FIELD__TIMER30_HIZCR_HIZCLR
+//    <name> HIZCLR </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002430) \nHigh-Impedance Output Clear\n0 : NoEffect = No effect.\n1 : Clear = Clear high-impedance output. (The PWM3nxA/PWM3nxB pins returns as output and this bit is automatically cleared to '0' after operation.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_HIZCR ) </loc>
+//      <o.0..0> HIZCLR
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Clear = Clear high-impedance output. (The PWM3nxA/PWM3nxB pins returns as output and this bit is automatically cleared to '0' after operation.)
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER30_HIZCR  ---------------------------------
+// SVD Line: 16791
+
+//  <rtree> SFDITEM_REG__TIMER30_HIZCR
+//    <name> HIZCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002430) TIMER3n High-Impedance Control Register </i>
+//    <loc> ( (unsigned int)((TIMER30_HIZCR >> 0) & 0xFFFFFFFF), ((TIMER30_HIZCR = (TIMER30_HIZCR & ~(0x95UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x95) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_HIZCR_HIZEN </item>
+//    <item> SFDITEM_FIELD__TIMER30_HIZCR_HIZSW </item>
+//    <item> SFDITEM_FIELD__TIMER30_HIZCR_HEDGE </item>
+//    <item> SFDITEM_FIELD__TIMER30_HIZCR_HIZSTA </item>
+//    <item> SFDITEM_FIELD__TIMER30_HIZCR_HIZCLR </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER30_ADTCR  ------------------------------
+// SVD Line: 16892
+
+unsigned int TIMER30_ADTCR __AT (0x40002434);
+
+
+
+// ----------------------------  Field Item: TIMER30_ADTCR_T3nBTTG  -------------------------------
+// SVD Line: 16901
+
+//  <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nBTTG
+//    <name> T3nBTTG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002434) \nSelect TIMER3n Bottom for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by bottom.\n1 : Enable = Enable ADC trigger signal generator by bottom. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_ADTCR ) </loc>
+//      <o.4..4> T3nBTTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by bottom.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by bottom.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER30_ADTCR_T3nPMTG  -------------------------------
+// SVD Line: 16919
+
+//  <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nPMTG
+//    <name> T3nPMTG </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40002434) \nSelect TIMER3n Period Match for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by period match.\n1 : Enable = Enable ADC trigger signal generator by period match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_ADTCR ) </loc>
+//      <o.3..3> T3nPMTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by period match.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by period match.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER30_ADTCR_T3nAMTG  -------------------------------
+// SVD Line: 16937
+
+//  <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nAMTG
+//    <name> T3nAMTG </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002434) \nSelect TIMER3n A-ch Match for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by A-ch match.\n1 : Enable = Enable ADC trigger signal generator by A-ch match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_ADTCR ) </loc>
+//      <o.2..2> T3nAMTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by A-ch match.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by A-ch match.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER30_ADTCR_T3nBMTG  -------------------------------
+// SVD Line: 16955
+
+//  <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nBMTG
+//    <name> T3nBMTG </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002434) \nSelect TIMER3n B-ch Match for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by B-ch match.\n1 : Enable = Enable ADC trigger signal generator by B-ch match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_ADTCR ) </loc>
+//      <o.1..1> T3nBMTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by B-ch match.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by B-ch match.
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: TIMER30_ADTCR_T3nCMTG  -------------------------------
+// SVD Line: 16973
+
+//  <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nCMTG
+//    <name> T3nCMTG </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002434) \nSelect TIMER3n C-ch Match for ADC Trigger Signal Generator.\n0 : Disable = Disable ADC trigger signal generator by C-ch match.\n1 : Enable = Enable ADC trigger signal generator by C-ch match. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) TIMER30_ADTCR ) </loc>
+//      <o.0..0> T3nCMTG
+//        <0=> 0: Disable = Disable ADC trigger signal generator by C-ch match.
+//        <1=> 1: Enable = Enable ADC trigger signal generator by C-ch match.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER30_ADTCR  ---------------------------------
+// SVD Line: 16892
+
+//  <rtree> SFDITEM_REG__TIMER30_ADTCR
+//    <name> ADTCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002434) TIMER3n ADC Trigger Control Register </i>
+//    <loc> ( (unsigned int)((TIMER30_ADTCR >> 0) & 0xFFFFFFFF), ((TIMER30_ADTCR = (TIMER30_ADTCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nBTTG </item>
+//    <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nPMTG </item>
+//    <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nAMTG </item>
+//    <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nBMTG </item>
+//    <item> SFDITEM_FIELD__TIMER30_ADTCR_T3nCMTG </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: TIMER30_ADTDR  ------------------------------
+// SVD Line: 16993
+
+unsigned int TIMER30_ADTDR __AT (0x40002438);
+
+
+
+// ----------------------------  Field Item: TIMER30_ADTDR_ADTDATA  -------------------------------
+// SVD Line: 17002
+
+//  <item> SFDITEM_FIELD__TIMER30_ADTDR_ADTDATA
+//    <name> ADTDATA </name>
+//    <rw> 
+//    <i> [Bits 13..0] RW (@ 0x40002438) TIMER3n ADC Trigger Generation Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_ADTDR >> 0) & 0x3FFF), ((TIMER30_ADTDR = (TIMER30_ADTDR & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: TIMER30_ADTDR  ---------------------------------
+// SVD Line: 16993
+
+//  <rtree> SFDITEM_REG__TIMER30_ADTDR
+//    <name> ADTDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002438) TIMER3n ADC Trigger Generator Data Register </i>
+//    <loc> ( (unsigned int)((TIMER30_ADTDR >> 0) & 0xFFFFFFFF), ((TIMER30_ADTDR = (TIMER30_ADTDR & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_ADTDR_ADTDATA </item>
+//  </rtree>
+//  
+
+
+// ------------------------  Register Item Address: TIMER30_T30_OUTCR  ----------------------------
+// SVD Line: 17031
+
+unsigned int TIMER30_T30_OUTCR __AT (0x40002420);
+
+
+
+// --------------------------  Field Item: TIMER30_T30_OUTCR_WTIDKY  ------------------------------
+// SVD Line: 17041
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_WTIDKY
+//    <name> WTIDKY </name>
+//    <w> 
+//    <i> [Bits 31..16] WO (@ 0x40002420) Write Identification Key (0xe06c) </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((TIMER30_T30_OUTCR >> 16) & 0x0), ((TIMER30_T30_OUTCR = (TIMER30_T30_OUTCR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_POLB  -------------------------------
+// SVD Line: 17054
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_POLB
+//    <name> POLB </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40002420) PWM3nxB Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.15..15> POLB
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_POLA  -------------------------------
+// SVD Line: 17060
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_POLA
+//    <name> POLA </name>
+//    <rw> 
+//    <i> [Bit 14] RW (@ 0x40002420) PWM3nxA Output Polarity Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.14..14> POLA
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_PABOE  ------------------------------
+// SVD Line: 17066
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PABOE
+//    <name> PABOE </name>
+//    <rw> 
+//    <i> [Bit 13] RW (@ 0x40002420) PWM3nAB Output Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.13..13> PABOE
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_PBBOE  ------------------------------
+// SVD Line: 17072
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PBBOE
+//    <name> PBBOE </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x40002420) PWM3nBB Output Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.12..12> PBBOE
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_PCBOE  ------------------------------
+// SVD Line: 17078
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PCBOE
+//    <name> PCBOE </name>
+//    <rw> 
+//    <i> [Bit 11] RW (@ 0x40002420) PWM3nCB Output Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.11..11> PCBOE
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_PAAOE  ------------------------------
+// SVD Line: 17084
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PAAOE
+//    <name> PAAOE </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40002420) PWM3nAA Output Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.10..10> PAAOE
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_PBAOE  ------------------------------
+// SVD Line: 17090
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PBAOE
+//    <name> PBAOE </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40002420) PWM3nBA Output Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.9..9> PBAOE
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_PCAOE  ------------------------------
+// SVD Line: 17096
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PCAOE
+//    <name> PCAOE </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40002420) PWM3nCA Output Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.8..8> PCAOE
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_LVLAB  ------------------------------
+// SVD Line: 17102
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLAB
+//    <name> LVLAB </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40002420) Configure PWM3nAB Output when Disable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.6..6> LVLAB
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_LVLBB  ------------------------------
+// SVD Line: 17108
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLBB
+//    <name> LVLBB </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40002420) Configure PWM3nBB Output when Disable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.5..5> LVLBB
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_LVLCB  ------------------------------
+// SVD Line: 17114
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLCB
+//    <name> LVLCB </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40002420) Configure PWM3nCB Output when Disable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.4..4> LVLCB
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_LVLAA  ------------------------------
+// SVD Line: 17120
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLAA
+//    <name> LVLAA </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40002420) Configure PWM3nAA Output when Disable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.2..2> LVLAA
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_LVLBA  ------------------------------
+// SVD Line: 17126
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLBA
+//    <name> LVLBA </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40002420) Configure PWM3nBA Output when Disable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.1..1> LVLBA
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------  Field Item: TIMER30_T30_OUTCR_LVLCA  ------------------------------
+// SVD Line: 17132
+
+//  <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLCA
+//    <name> LVLCA </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40002420) Configure PWM3nCA Output when Disable </i>
+//    <check> 
+//      <loc> ( (unsigned int) TIMER30_T30_OUTCR ) </loc>
+//      <o.0..0> LVLCA
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Register RTree: TIMER30_T30_OUTCR  -------------------------------
+// SVD Line: 17031
+
+//  <rtree> SFDITEM_REG__TIMER30_T30_OUTCR
+//    <name> T30_OUTCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40002420) TIMER3n Output Control Register </i>
+//    <loc> ( (unsigned int)((TIMER30_T30_OUTCR >> 0) & 0xFFFFFFFF), ((TIMER30_T30_OUTCR = (TIMER30_T30_OUTCR & ~(0xFFFFFF77UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF77) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_WTIDKY </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_POLB </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_POLA </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PABOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PBBOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PCBOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PAAOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PBAOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_PCAOE </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLAB </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLBB </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLCB </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLAA </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLBA </item>
+//    <item> SFDITEM_FIELD__TIMER30_T30_OUTCR_LVLCA </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: TIMER30  ------------------------------------
+// SVD Line: 17012
+
+//  <view> TIMER30
+//    <name> TIMER30 </name>
+//    <item> SFDITEM_REG__TIMER30_CR </item>
+//    <item> SFDITEM_REG__TIMER30_PDR </item>
+//    <item> SFDITEM_REG__TIMER30_ADR </item>
+//    <item> SFDITEM_REG__TIMER30_BDR </item>
+//    <item> SFDITEM_REG__TIMER30_CDR </item>
+//    <item> SFDITEM_REG__TIMER30_CAPDR </item>
+//    <item> SFDITEM_REG__TIMER30_PREDR </item>
+//    <item> SFDITEM_REG__TIMER30_CNT </item>
+//    <item> SFDITEM_REG__TIMER30_OUTCR </item>
+//    <item> SFDITEM_REG__TIMER30_DLY </item>
+//    <item> SFDITEM_REG__TIMER30_INTCR </item>
+//    <item> SFDITEM_REG__TIMER30_INTFLAG </item>
+//    <item> SFDITEM_REG__TIMER30_HIZCR </item>
+//    <item> SFDITEM_REG__TIMER30_ADTCR </item>
+//    <item> SFDITEM_REG__TIMER30_ADTDR </item>
+//    <item> SFDITEM_REG__TIMER30_T30_OUTCR </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: ADC_CR  ---------------------------------
+// SVD Line: 17161
+
+unsigned int ADC_CR __AT (0x40003000);
+
+
+
+// --------------------------------  Field Item: ADC_CR_ADCEN  ------------------------------------
+// SVD Line: 17170
+
+//  <item> SFDITEM_FIELD__ADC_CR_ADCEN
+//    <name> ADCEN </name>
+//    <rw> 
+//    <i> [Bit 15] RW (@ 0x40003000) \nADC Module Enable\n0 : Disable = Disable ADC module operation.\n1 : Enable = Enable ADC module operation. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) ADC_CR ) </loc>
+//      <o.15..15> ADCEN
+//        <0=> 0: Disable = Disable ADC module operation.
+//        <1=> 1: Enable = Enable ADC module operation.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: ADC_CR_TRIG  ------------------------------------
+// SVD Line: 17188
+
+//  <item> SFDITEM_FIELD__ADC_CR_TRIG
+//    <name> TRIG </name>
+//    <rw> 
+//    <i> [Bits 13..11] RW (@ 0x40003000) \nADC Trigger Signal Selection\n0 : ADST = Select ADST.\n1 : TIMER10 = Select TIMER10 A-Match Signal.\n2 : TIMER11 = Select TIMER11 A-Match Signal.\n3 : TIMER12 = Select TIMER12 A-Match Signal.\n4 : TIMER30 = Select ADC Trigger Signal from TIMER30.\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) ADC_CR ) </loc>
+//      <o.13..11> TRIG
+//        <0=> 0: ADST = Select ADST.
+//        <1=> 1: TIMER10 = Select TIMER10 A-Match Signal.
+//        <2=> 2: TIMER11 = Select TIMER11 A-Match Signal.
+//        <3=> 3: TIMER12 = Select TIMER12 A-Match Signal.
+//        <4=> 4: TIMER30 = Select ADC Trigger Signal from TIMER30.
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: ADC_CR_REFSEL  -----------------------------------
+// SVD Line: 17221
+
+//  <item> SFDITEM_FIELD__ADC_CR_REFSEL
+//    <name> REFSEL </name>
+//    <rw> 
+//    <i> [Bit 10] RW (@ 0x40003000) \nADC Reference Selection\n0 : Vdd = Select analog power (VDD).\n1 : AVref = Select external reference (AVREF). </i>
+//    <combo> 
+//      <loc> ( (unsigned int) ADC_CR ) </loc>
+//      <o.10..10> REFSEL
+//        <0=> 0: Vdd = Select analog power (VDD).
+//        <1=> 1: AVref = Select external reference (AVREF).
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: ADC_CR_ADST  ------------------------------------
+// SVD Line: 17239
+
+//  <item> SFDITEM_FIELD__ADC_CR_ADST
+//    <name> ADST </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003000) \nADC Conversion Start\n0 : NoEffect = No effect.\n1 : Start = Trigger signal generation for conversion start. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) ADC_CR ) </loc>
+//      <o.8..8> ADST
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Start = Trigger signal generation for conversion start.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: ADC_CR_ADCIEN  -----------------------------------
+// SVD Line: 17257
+
+//  <item> SFDITEM_FIELD__ADC_CR_ADCIEN
+//    <name> ADCIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003000) \nADC Interrupt Enable\n0 : Disable = Disable ADC interrupt.\n1 : Enable = Enable ADC interrupt. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) ADC_CR ) </loc>
+//      <o.5..5> ADCIEN
+//        <0=> 0: Disable = Disable ADC interrupt.
+//        <1=> 1: Enable = Enable ADC interrupt.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: ADC_CR_ADCIFLAG  ----------------------------------
+// SVD Line: 17275
+
+//  <item> SFDITEM_FIELD__ADC_CR_ADCIFLAG
+//    <name> ADCIFLAG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003000) \nADC Interrupt Flag\n0 : NoRequest = No request occurred.\n1 : Request = Request occurred. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) ADC_CR ) </loc>
+//      <o.4..4> ADCIFLAG
+//        <0=> 0: NoRequest = No request occurred.
+//        <1=> 1: Request = Request occurred.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: ADC_CR_ADSEL  ------------------------------------
+// SVD Line: 17293
+
+//  <item> SFDITEM_FIELD__ADC_CR_ADSEL
+//    <name> ADSEL </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40003000) \nA/D Converter Channel Selection\n0 : AN0 = Select AN0.\n1 : AN1 = Select AN1.\n2 : AN2 = Select AN2.\n3 : AN3 = Select AN3.\n4 : AN4 = Select AN4.\n5 : AN5 = Select AN5.\n6 : AN6 = Select AN6.\n7 : AN7 = Select AN7.\n8 : AN8 = Select AN8.\n9 : AN9 = Select AN9.\n10 : AN10 = Select AN10.\n11 : AN11 = Select AN11\n12 : AN12 = Select AN12\n13 : AN13 = Select AN13\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) ADC_CR ) </loc>
+//      <o.3..0> ADSEL
+//        <0=> 0: AN0 = Select AN0.
+//        <1=> 1: AN1 = Select AN1.
+//        <2=> 2: AN2 = Select AN2.
+//        <3=> 3: AN3 = Select AN3.
+//        <4=> 4: AN4 = Select AN4.
+//        <5=> 5: AN5 = Select AN5.
+//        <6=> 6: AN6 = Select AN6.
+//        <7=> 7: AN7 = Select AN7.
+//        <8=> 8: AN8 = Select AN8.
+//        <9=> 9: AN9 = Select AN9.
+//        <10=> 10: AN10 = Select AN10.
+//        <11=> 11: AN11 = Select AN11
+//        <12=> 12: AN12 = Select AN12
+//        <13=> 13: AN13 = Select AN13
+//        <14=> 14: 
+//        <15=> 15: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: ADC_CR  -------------------------------------
+// SVD Line: 17161
+
+//  <rtree> SFDITEM_REG__ADC_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003000) A/D Converter Control Register </i>
+//    <loc> ( (unsigned int)((ADC_CR >> 0) & 0xFFFFFFFF), ((ADC_CR = (ADC_CR & ~(0xBD3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xBD3F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__ADC_CR_ADCEN </item>
+//    <item> SFDITEM_FIELD__ADC_CR_TRIG </item>
+//    <item> SFDITEM_FIELD__ADC_CR_REFSEL </item>
+//    <item> SFDITEM_FIELD__ADC_CR_ADST </item>
+//    <item> SFDITEM_FIELD__ADC_CR_ADCIEN </item>
+//    <item> SFDITEM_FIELD__ADC_CR_ADCIFLAG </item>
+//    <item> SFDITEM_FIELD__ADC_CR_ADSEL </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: ADC_DR  ---------------------------------
+// SVD Line: 17373
+
+unsigned int ADC_DR __AT (0x40003004);
+
+
+
+// --------------------------------  Field Item: ADC_DR_ADDATA  -----------------------------------
+// SVD Line: 17382
+
+//  <item> SFDITEM_FIELD__ADC_DR_ADDATA
+//    <name> ADDATA </name>
+//    <r> 
+//    <i> [Bits 11..0] RO (@ 0x40003004) A/D Converter Result Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((ADC_DR >> 0) & 0xFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: ADC_DR  -------------------------------------
+// SVD Line: 17373
+
+//  <rtree> SFDITEM_REG__ADC_DR
+//    <name> DR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40003004) A/D Converter Data Register </i>
+//    <loc> ( (unsigned int)((ADC_DR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__ADC_DR_ADDATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: ADC_PREDR  --------------------------------
+// SVD Line: 17390
+
+unsigned int ADC_PREDR __AT (0x40003008);
+
+
+
+// -------------------------------  Field Item: ADC_PREDR_PRED  -----------------------------------
+// SVD Line: 17399
+
+//  <item> SFDITEM_FIELD__ADC_PREDR_PRED
+//    <name> PRED </name>
+//    <rw> 
+//    <i> [Bits 4..0] RW (@ 0x40003008) A/D Converter Prescaler Data </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((ADC_PREDR >> 0) & 0x1F), ((ADC_PREDR = (ADC_PREDR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: ADC_PREDR  -----------------------------------
+// SVD Line: 17390
+
+//  <rtree> SFDITEM_REG__ADC_PREDR
+//    <name> PREDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003008) A/D Converter Prescaler Data Register </i>
+//    <loc> ( (unsigned int)((ADC_PREDR >> 0) & 0xFFFFFFFF), ((ADC_PREDR = (ADC_PREDR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__ADC_PREDR_PRED </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: ADC  --------------------------------------
+// SVD Line: 17142
+
+//  <view> ADC
+//    <name> ADC </name>
+//    <item> SFDITEM_REG__ADC_CR </item>
+//    <item> SFDITEM_REG__ADC_DR </item>
+//    <item> SFDITEM_REG__ADC_PREDR </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: USART1n_CR1  -------------------------------
+// SVD Line: 17423
+
+unsigned int USART1n_CR1 __AT (0x54000000);
+
+
+
+// -----------------------------  Field Item: USART1n_CR1_USTnMS  ---------------------------------
+// SVD Line: 17432
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_USTnMS
+//    <name> USTnMS </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x54000000) \nUSART1n Operation Mode Selection\n0 : Async = Asynchronous Mode (UART)\n1 : Sync = Synchronous Mode (USRT)\n2 : Reserved - do not use\n3 : SPI = SPI Mode </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.15..14> USTnMS
+//        <0=> 0: Async = Asynchronous Mode (UART)
+//        <1=> 1: Sync = Synchronous Mode (USRT)
+//        <2=> 2: 
+//        <3=> 3: SPI = SPI Mode
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR1_USTnP  ---------------------------------
+// SVD Line: 17455
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_USTnP
+//    <name> USTnP </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x54000000) \nSelects Parity Generation and Check method (only UART mode)\n0 : No = No Parity\n1 : Reserved - do not use\n2 : Even = Even Parity\n3 : Odd = Odd Parity </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.13..12> USTnP
+//        <0=> 0: No = No Parity
+//        <1=> 1: 
+//        <2=> 2: Even = Even Parity
+//        <3=> 3: Odd = Odd Parity
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR1_USTnS  ---------------------------------
+// SVD Line: 17478
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_USTnS
+//    <name> USTnS </name>
+//    <rw> 
+//    <i> [Bits 11..9] RW (@ 0x54000000) \nSelects the length of data bit in a frame when Asynchronous or Synchronous mode\n0 : 5bit = 5 bit\n1 : 6bit = 6 bit\n2 : 7bit = 7 bit\n3 : 8bit = 8 bit\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : 9bit = 9 bit </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.11..9> USTnS
+//        <0=> 0: 5bit = 5 bit
+//        <1=> 1: 6bit = 6 bit
+//        <2=> 2: 7bit = 7 bit
+//        <3=> 3: 8bit = 8 bit
+//        <4=> 4: 
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 9bit = 9 bit
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR1_ORDn  ----------------------------------
+// SVD Line: 17511
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_ORDn
+//    <name> ORDn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x54000000) \nSelects the first data bit to be transmitted (only SPI mode)\n0 : lsbFirst = LSB First\n1 : msbFirst = MSB First </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.8..8> ORDn
+//        <0=> 0: lsbFirst = LSB First
+//        <1=> 1: msbFirst = MSB First
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR1_CPOLn  ---------------------------------
+// SVD Line: 17529
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_CPOLn
+//    <name> CPOLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x54000000) \nSelects the Clock Polarity of ACK in Synchronous or SPI mode\n0 : IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge\n1 : IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.7..7> CPOLn
+//        <0=> 0: IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge
+//        <1=> 1: IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR1_CPHAn  ---------------------------------
+// SVD Line: 17547
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_CPHAn
+//    <name> CPHAn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x54000000) \nThe CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)\n0 : StartIdle = Start with idle state.\n1 : StartInverted = Start with inverted idle state. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.6..6> CPHAn
+//        <0=> 0: StartIdle = Start with idle state.
+//        <1=> 1: StartInverted = Start with inverted idle state.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR1_DRIEn  ---------------------------------
+// SVD Line: 17565
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_DRIEn
+//    <name> DRIEn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x54000000) Transmit Data Register Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.5..5> DRIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR1_TXCIEn  ---------------------------------
+// SVD Line: 17571
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_TXCIEn
+//    <name> TXCIEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x54000000) Transmit Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.4..4> TXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR1_RXCIEn  ---------------------------------
+// SVD Line: 17577
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_RXCIEn
+//    <name> RXCIEn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x54000000) Receive Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.3..3> RXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR1_WAKEIEn  --------------------------------
+// SVD Line: 17583
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_WAKEIEn
+//    <name> WAKEIEn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x54000000) Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.2..2> WAKEIEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR1_TXEn  ----------------------------------
+// SVD Line: 17589
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_TXEn
+//    <name> TXEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x54000000) Enable the transmitter unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.1..1> TXEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR1_RXEn  ----------------------------------
+// SVD Line: 17595
+
+//  <item> SFDITEM_FIELD__USART1n_CR1_RXEn
+//    <name> RXEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x54000000) Enable the receiver unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR1 ) </loc>
+//      <o.0..0> RXEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART1n_CR1  ----------------------------------
+// SVD Line: 17423
+
+//  <rtree> SFDITEM_REG__USART1n_CR1
+//    <name> CR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x54000000) USART1n Control Register 1 </i>
+//    <loc> ( (unsigned int)((USART1n_CR1 >> 0) & 0xFFFFFFFF), ((USART1n_CR1 = (USART1n_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART1n_CR1_USTnMS </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_USTnP </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_USTnS </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_ORDn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_CPOLn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_CPHAn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_DRIEn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_TXCIEn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_RXCIEn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_WAKEIEn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_TXEn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR1_RXEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART1n_CR2  -------------------------------
+// SVD Line: 17603
+
+unsigned int USART1n_CR2 __AT (0x54000004);
+
+
+
+// -----------------------------  Field Item: USART1n_CR2_USTnEN  ---------------------------------
+// SVD Line: 17612
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_USTnEN
+//    <name> USTnEN </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x54000004) Activate USART1n Block </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.9..9> USTnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR2_DBLSn  ---------------------------------
+// SVD Line: 17618
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_DBLSn
+//    <name> DBLSn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x54000004) Selects receiver sampling rate (only UART mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.8..8> DBLSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR2_MASTERn  --------------------------------
+// SVD Line: 17624
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_MASTERn
+//    <name> MASTERn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x54000004) Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.7..7> MASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR2_LOOPSn  ---------------------------------
+// SVD Line: 17630
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_LOOPSn
+//    <name> LOOPSn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x54000004) Control the Loop Back mode of USART1n for test mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.6..6> LOOPSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR2_DISSCKn  --------------------------------
+// SVD Line: 17636
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_DISSCKn
+//    <name> DISSCKn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x54000004) In synchronous mode operation, selects the waveform of SCK1n output </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.5..5> DISSCKn
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: USART1n_CR2_USTnSSEN  --------------------------------
+// SVD Line: 17642
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_USTnSSEN
+//    <name> USTnSSEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x54000004) This bit controls the SS1n pin operation (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.4..4> USTnSSEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_CR2_FXCHn  ---------------------------------
+// SVD Line: 17648
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_FXCHn
+//    <name> FXCHn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x54000004) SPI1n port function exchange control (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.3..3> FXCHn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR2_USTnSB  ---------------------------------
+// SVD Line: 17654
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_USTnSB
+//    <name> USTnSB </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x54000004) Selects the length of stop bit in Asynchronous or Synchronous mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.2..2> USTnSB
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR2_USTnTX8  --------------------------------
+// SVD Line: 17660
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_USTnTX8
+//    <name> USTnTX8 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x54000004) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.1..1> USTnTX8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART1n_CR2_USTnRX8  --------------------------------
+// SVD Line: 17666
+
+//  <item> SFDITEM_FIELD__USART1n_CR2_USTnRX8
+//    <name> USTnRX8 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x54000004) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_CR2 ) </loc>
+//      <o.0..0> USTnRX8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART1n_CR2  ----------------------------------
+// SVD Line: 17603
+
+//  <rtree> SFDITEM_REG__USART1n_CR2
+//    <name> CR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x54000004) USART1n Control Register 2 </i>
+//    <loc> ( (unsigned int)((USART1n_CR2 >> 0) & 0xFFFFFFFF), ((USART1n_CR2 = (USART1n_CR2 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART1n_CR2_USTnEN </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_DBLSn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_MASTERn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_LOOPSn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_DISSCKn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_USTnSSEN </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_FXCHn </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_USTnSB </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_USTnTX8 </item>
+//    <item> SFDITEM_FIELD__USART1n_CR2_USTnRX8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART1n_ST  -------------------------------
+// SVD Line: 17674
+
+unsigned int USART1n_ST __AT (0x5400000C);
+
+
+
+// -------------------------------  Field Item: USART1n_ST_DREn  ----------------------------------
+// SVD Line: 17683
+
+//  <item> SFDITEM_FIELD__USART1n_ST_DREn
+//    <name> DREn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x5400000C) Transmit Data Register Empty Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_ST ) </loc>
+//      <o.7..7> DREn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART1n_ST_TXCn  ----------------------------------
+// SVD Line: 17689
+
+//  <item> SFDITEM_FIELD__USART1n_ST_TXCn
+//    <name> TXCn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x5400000C) Transmit Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_ST ) </loc>
+//      <o.6..6> TXCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART1n_ST_RXCn  ----------------------------------
+// SVD Line: 17695
+
+//  <item> SFDITEM_FIELD__USART1n_ST_RXCn
+//    <name> RXCn </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x5400000C) Receive Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_ST ) </loc>
+//      <o.5..5> RXCn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART1n_ST_WAKEn  ----------------------------------
+// SVD Line: 17701
+
+//  <item> SFDITEM_FIELD__USART1n_ST_WAKEn
+//    <name> WAKEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x5400000C) Asynchronous Wake-Up Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_ST ) </loc>
+//      <o.4..4> WAKEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART1n_ST_DORn  ----------------------------------
+// SVD Line: 17707
+
+//  <item> SFDITEM_FIELD__USART1n_ST_DORn
+//    <name> DORn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x5400000C) This bit is set if data OverRun takes place </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_ST ) </loc>
+//      <o.2..2> DORn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART1n_ST_FEn  -----------------------------------
+// SVD Line: 17713
+
+//  <item> SFDITEM_FIELD__USART1n_ST_FEn
+//    <name> FEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x5400000C) This bit is set if the first stop bit of next character in the receive buffer is detected as '0' </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_ST ) </loc>
+//      <o.1..1> FEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART1n_ST_PEn  -----------------------------------
+// SVD Line: 17719
+
+//  <item> SFDITEM_FIELD__USART1n_ST_PEn
+//    <name> PEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x5400000C) This bit is set if the next character in the receive buffer has a Parity Error while parity is checked </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART1n_ST ) </loc>
+//      <o.0..0> PEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART1n_ST  -----------------------------------
+// SVD Line: 17674
+
+//  <rtree> SFDITEM_REG__USART1n_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x5400000C) USART1n Status Register </i>
+//    <loc> ( (unsigned int)((USART1n_ST >> 0) & 0xFFFFFFFF), ((USART1n_ST = (USART1n_ST & ~(0xD3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD3) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART1n_ST_DREn </item>
+//    <item> SFDITEM_FIELD__USART1n_ST_TXCn </item>
+//    <item> SFDITEM_FIELD__USART1n_ST_RXCn </item>
+//    <item> SFDITEM_FIELD__USART1n_ST_WAKEn </item>
+//    <item> SFDITEM_FIELD__USART1n_ST_DORn </item>
+//    <item> SFDITEM_FIELD__USART1n_ST_FEn </item>
+//    <item> SFDITEM_FIELD__USART1n_ST_PEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART1n_BDR  -------------------------------
+// SVD Line: 17727
+
+unsigned int USART1n_BDR __AT (0x54000010);
+
+
+
+// ------------------------------  Field Item: USART1n_BDR_BDATA  ---------------------------------
+// SVD Line: 17736
+
+//  <item> SFDITEM_FIELD__USART1n_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x54000010) The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((USART1n_BDR >> 0) & 0xFFF), ((USART1n_BDR = (USART1n_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART1n_BDR  ----------------------------------
+// SVD Line: 17727
+
+//  <rtree> SFDITEM_REG__USART1n_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x54000010) USART1n Baud Rate Generation Register </i>
+//    <loc> ( (unsigned int)((USART1n_BDR >> 0) & 0xFFFFFFFF), ((USART1n_BDR = (USART1n_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART1n_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART1n_DR  -------------------------------
+// SVD Line: 17744
+
+unsigned int USART1n_DR __AT (0x54000014);
+
+
+
+// -------------------------------  Field Item: USART1n_DR_DATA  ----------------------------------
+// SVD Line: 17753
+
+//  <item> SFDITEM_FIELD__USART1n_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x54000014) The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((USART1n_DR >> 0) & 0xFF), ((USART1n_DR = (USART1n_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART1n_DR  -----------------------------------
+// SVD Line: 17744
+
+//  <rtree> SFDITEM_REG__USART1n_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x54000014) USART1n Data Register </i>
+//    <loc> ( (unsigned int)((USART1n_DR >> 0) & 0xFFFFFFFF), ((USART1n_DR = (USART1n_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART1n_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: USART1n  ------------------------------------
+// SVD Line: 17409
+
+//  <view> USART1n
+//    <name> USART1n </name>
+//    <item> SFDITEM_REG__USART1n_CR1 </item>
+//    <item> SFDITEM_REG__USART1n_CR2 </item>
+//    <item> SFDITEM_REG__USART1n_ST </item>
+//    <item> SFDITEM_REG__USART1n_BDR </item>
+//    <item> SFDITEM_REG__USART1n_DR </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: USART10_CR1  -------------------------------
+// SVD Line: 17423
+
+unsigned int USART10_CR1 __AT (0x40003800);
+
+
+
+// -----------------------------  Field Item: USART10_CR1_USTnMS  ---------------------------------
+// SVD Line: 17432
+
+//  <item> SFDITEM_FIELD__USART10_CR1_USTnMS
+//    <name> USTnMS </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x40003800) \nUSART1n Operation Mode Selection\n0 : Async = Asynchronous Mode (UART)\n1 : Sync = Synchronous Mode (USRT)\n2 : Reserved - do not use\n3 : SPI = SPI Mode </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.15..14> USTnMS
+//        <0=> 0: Async = Asynchronous Mode (UART)
+//        <1=> 1: Sync = Synchronous Mode (USRT)
+//        <2=> 2: 
+//        <3=> 3: SPI = SPI Mode
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR1_USTnP  ---------------------------------
+// SVD Line: 17455
+
+//  <item> SFDITEM_FIELD__USART10_CR1_USTnP
+//    <name> USTnP </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40003800) \nSelects Parity Generation and Check method (only UART mode)\n0 : No = No Parity\n1 : Reserved - do not use\n2 : Even = Even Parity\n3 : Odd = Odd Parity </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.13..12> USTnP
+//        <0=> 0: No = No Parity
+//        <1=> 1: 
+//        <2=> 2: Even = Even Parity
+//        <3=> 3: Odd = Odd Parity
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR1_USTnS  ---------------------------------
+// SVD Line: 17478
+
+//  <item> SFDITEM_FIELD__USART10_CR1_USTnS
+//    <name> USTnS </name>
+//    <rw> 
+//    <i> [Bits 11..9] RW (@ 0x40003800) \nSelects the length of data bit in a frame when Asynchronous or Synchronous mode\n0 : 5bit = 5 bit\n1 : 6bit = 6 bit\n2 : 7bit = 7 bit\n3 : 8bit = 8 bit\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : 9bit = 9 bit </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.11..9> USTnS
+//        <0=> 0: 5bit = 5 bit
+//        <1=> 1: 6bit = 6 bit
+//        <2=> 2: 7bit = 7 bit
+//        <3=> 3: 8bit = 8 bit
+//        <4=> 4: 
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 9bit = 9 bit
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR1_ORDn  ----------------------------------
+// SVD Line: 17511
+
+//  <item> SFDITEM_FIELD__USART10_CR1_ORDn
+//    <name> ORDn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003800) \nSelects the first data bit to be transmitted (only SPI mode)\n0 : lsbFirst = LSB First\n1 : msbFirst = MSB First </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.8..8> ORDn
+//        <0=> 0: lsbFirst = LSB First
+//        <1=> 1: msbFirst = MSB First
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR1_CPOLn  ---------------------------------
+// SVD Line: 17529
+
+//  <item> SFDITEM_FIELD__USART10_CR1_CPOLn
+//    <name> CPOLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003800) \nSelects the Clock Polarity of ACK in Synchronous or SPI mode\n0 : IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge\n1 : IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.7..7> CPOLn
+//        <0=> 0: IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge
+//        <1=> 1: IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR1_CPHAn  ---------------------------------
+// SVD Line: 17547
+
+//  <item> SFDITEM_FIELD__USART10_CR1_CPHAn
+//    <name> CPHAn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003800) \nThe CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)\n0 : StartIdle = Start with idle state.\n1 : StartInverted = Start with inverted idle state. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.6..6> CPHAn
+//        <0=> 0: StartIdle = Start with idle state.
+//        <1=> 1: StartInverted = Start with inverted idle state.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR1_DRIEn  ---------------------------------
+// SVD Line: 17565
+
+//  <item> SFDITEM_FIELD__USART10_CR1_DRIEn
+//    <name> DRIEn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003800) Transmit Data Register Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.5..5> DRIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR1_TXCIEn  ---------------------------------
+// SVD Line: 17571
+
+//  <item> SFDITEM_FIELD__USART10_CR1_TXCIEn
+//    <name> TXCIEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003800) Transmit Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.4..4> TXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR1_RXCIEn  ---------------------------------
+// SVD Line: 17577
+
+//  <item> SFDITEM_FIELD__USART10_CR1_RXCIEn
+//    <name> RXCIEn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40003800) Receive Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.3..3> RXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR1_WAKEIEn  --------------------------------
+// SVD Line: 17583
+
+//  <item> SFDITEM_FIELD__USART10_CR1_WAKEIEn
+//    <name> WAKEIEn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40003800) Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.2..2> WAKEIEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR1_TXEn  ----------------------------------
+// SVD Line: 17589
+
+//  <item> SFDITEM_FIELD__USART10_CR1_TXEn
+//    <name> TXEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003800) Enable the transmitter unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.1..1> TXEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR1_RXEn  ----------------------------------
+// SVD Line: 17595
+
+//  <item> SFDITEM_FIELD__USART10_CR1_RXEn
+//    <name> RXEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003800) Enable the receiver unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR1 ) </loc>
+//      <o.0..0> RXEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART10_CR1  ----------------------------------
+// SVD Line: 17423
+
+//  <rtree> SFDITEM_REG__USART10_CR1
+//    <name> CR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003800) USART1n Control Register 1 </i>
+//    <loc> ( (unsigned int)((USART10_CR1 >> 0) & 0xFFFFFFFF), ((USART10_CR1 = (USART10_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART10_CR1_USTnMS </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_USTnP </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_USTnS </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_ORDn </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_CPOLn </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_CPHAn </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_DRIEn </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_TXCIEn </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_RXCIEn </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_WAKEIEn </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_TXEn </item>
+//    <item> SFDITEM_FIELD__USART10_CR1_RXEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART10_CR2  -------------------------------
+// SVD Line: 17603
+
+unsigned int USART10_CR2 __AT (0x40003804);
+
+
+
+// -----------------------------  Field Item: USART10_CR2_USTnEN  ---------------------------------
+// SVD Line: 17612
+
+//  <item> SFDITEM_FIELD__USART10_CR2_USTnEN
+//    <name> USTnEN </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40003804) Activate USART1n Block </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.9..9> USTnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR2_DBLSn  ---------------------------------
+// SVD Line: 17618
+
+//  <item> SFDITEM_FIELD__USART10_CR2_DBLSn
+//    <name> DBLSn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003804) Selects receiver sampling rate (only UART mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.8..8> DBLSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR2_MASTERn  --------------------------------
+// SVD Line: 17624
+
+//  <item> SFDITEM_FIELD__USART10_CR2_MASTERn
+//    <name> MASTERn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003804) Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.7..7> MASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR2_LOOPSn  ---------------------------------
+// SVD Line: 17630
+
+//  <item> SFDITEM_FIELD__USART10_CR2_LOOPSn
+//    <name> LOOPSn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003804) Control the Loop Back mode of USART1n for test mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.6..6> LOOPSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR2_DISSCKn  --------------------------------
+// SVD Line: 17636
+
+//  <item> SFDITEM_FIELD__USART10_CR2_DISSCKn
+//    <name> DISSCKn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003804) In synchronous mode operation, selects the waveform of SCK1n output </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.5..5> DISSCKn
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: USART10_CR2_USTnSSEN  --------------------------------
+// SVD Line: 17642
+
+//  <item> SFDITEM_FIELD__USART10_CR2_USTnSSEN
+//    <name> USTnSSEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003804) This bit controls the SS1n pin operation (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.4..4> USTnSSEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_CR2_FXCHn  ---------------------------------
+// SVD Line: 17648
+
+//  <item> SFDITEM_FIELD__USART10_CR2_FXCHn
+//    <name> FXCHn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40003804) SPI1n port function exchange control (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.3..3> FXCHn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR2_USTnSB  ---------------------------------
+// SVD Line: 17654
+
+//  <item> SFDITEM_FIELD__USART10_CR2_USTnSB
+//    <name> USTnSB </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40003804) Selects the length of stop bit in Asynchronous or Synchronous mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.2..2> USTnSB
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR2_USTnTX8  --------------------------------
+// SVD Line: 17660
+
+//  <item> SFDITEM_FIELD__USART10_CR2_USTnTX8
+//    <name> USTnTX8 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003804) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.1..1> USTnTX8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART10_CR2_USTnRX8  --------------------------------
+// SVD Line: 17666
+
+//  <item> SFDITEM_FIELD__USART10_CR2_USTnRX8
+//    <name> USTnRX8 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003804) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_CR2 ) </loc>
+//      <o.0..0> USTnRX8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART10_CR2  ----------------------------------
+// SVD Line: 17603
+
+//  <rtree> SFDITEM_REG__USART10_CR2
+//    <name> CR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003804) USART1n Control Register 2 </i>
+//    <loc> ( (unsigned int)((USART10_CR2 >> 0) & 0xFFFFFFFF), ((USART10_CR2 = (USART10_CR2 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART10_CR2_USTnEN </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_DBLSn </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_MASTERn </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_LOOPSn </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_DISSCKn </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_USTnSSEN </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_FXCHn </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_USTnSB </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_USTnTX8 </item>
+//    <item> SFDITEM_FIELD__USART10_CR2_USTnRX8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART10_ST  -------------------------------
+// SVD Line: 17674
+
+unsigned int USART10_ST __AT (0x4000380C);
+
+
+
+// -------------------------------  Field Item: USART10_ST_DREn  ----------------------------------
+// SVD Line: 17683
+
+//  <item> SFDITEM_FIELD__USART10_ST_DREn
+//    <name> DREn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x4000380C) Transmit Data Register Empty Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_ST ) </loc>
+//      <o.7..7> DREn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART10_ST_TXCn  ----------------------------------
+// SVD Line: 17689
+
+//  <item> SFDITEM_FIELD__USART10_ST_TXCn
+//    <name> TXCn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x4000380C) Transmit Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_ST ) </loc>
+//      <o.6..6> TXCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART10_ST_RXCn  ----------------------------------
+// SVD Line: 17695
+
+//  <item> SFDITEM_FIELD__USART10_ST_RXCn
+//    <name> RXCn </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x4000380C) Receive Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_ST ) </loc>
+//      <o.5..5> RXCn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART10_ST_WAKEn  ----------------------------------
+// SVD Line: 17701
+
+//  <item> SFDITEM_FIELD__USART10_ST_WAKEn
+//    <name> WAKEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x4000380C) Asynchronous Wake-Up Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_ST ) </loc>
+//      <o.4..4> WAKEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART10_ST_DORn  ----------------------------------
+// SVD Line: 17707
+
+//  <item> SFDITEM_FIELD__USART10_ST_DORn
+//    <name> DORn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x4000380C) This bit is set if data OverRun takes place </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_ST ) </loc>
+//      <o.2..2> DORn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART10_ST_FEn  -----------------------------------
+// SVD Line: 17713
+
+//  <item> SFDITEM_FIELD__USART10_ST_FEn
+//    <name> FEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x4000380C) This bit is set if the first stop bit of next character in the receive buffer is detected as '0' </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_ST ) </loc>
+//      <o.1..1> FEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART10_ST_PEn  -----------------------------------
+// SVD Line: 17719
+
+//  <item> SFDITEM_FIELD__USART10_ST_PEn
+//    <name> PEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x4000380C) This bit is set if the next character in the receive buffer has a Parity Error while parity is checked </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART10_ST ) </loc>
+//      <o.0..0> PEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART10_ST  -----------------------------------
+// SVD Line: 17674
+
+//  <rtree> SFDITEM_REG__USART10_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000380C) USART1n Status Register </i>
+//    <loc> ( (unsigned int)((USART10_ST >> 0) & 0xFFFFFFFF), ((USART10_ST = (USART10_ST & ~(0xD3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD3) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART10_ST_DREn </item>
+//    <item> SFDITEM_FIELD__USART10_ST_TXCn </item>
+//    <item> SFDITEM_FIELD__USART10_ST_RXCn </item>
+//    <item> SFDITEM_FIELD__USART10_ST_WAKEn </item>
+//    <item> SFDITEM_FIELD__USART10_ST_DORn </item>
+//    <item> SFDITEM_FIELD__USART10_ST_FEn </item>
+//    <item> SFDITEM_FIELD__USART10_ST_PEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART10_BDR  -------------------------------
+// SVD Line: 17727
+
+unsigned int USART10_BDR __AT (0x40003810);
+
+
+
+// ------------------------------  Field Item: USART10_BDR_BDATA  ---------------------------------
+// SVD Line: 17736
+
+//  <item> SFDITEM_FIELD__USART10_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40003810) The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((USART10_BDR >> 0) & 0xFFF), ((USART10_BDR = (USART10_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART10_BDR  ----------------------------------
+// SVD Line: 17727
+
+//  <rtree> SFDITEM_REG__USART10_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003810) USART1n Baud Rate Generation Register </i>
+//    <loc> ( (unsigned int)((USART10_BDR >> 0) & 0xFFFFFFFF), ((USART10_BDR = (USART10_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART10_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART10_DR  -------------------------------
+// SVD Line: 17744
+
+unsigned int USART10_DR __AT (0x40003814);
+
+
+
+// -------------------------------  Field Item: USART10_DR_DATA  ----------------------------------
+// SVD Line: 17753
+
+//  <item> SFDITEM_FIELD__USART10_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40003814) The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((USART10_DR >> 0) & 0xFF), ((USART10_DR = (USART10_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART10_DR  -----------------------------------
+// SVD Line: 17744
+
+//  <rtree> SFDITEM_REG__USART10_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003814) USART1n Data Register </i>
+//    <loc> ( (unsigned int)((USART10_DR >> 0) & 0xFFFFFFFF), ((USART10_DR = (USART10_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART10_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: USART10  ------------------------------------
+// SVD Line: 17763
+
+//  <view> USART10
+//    <name> USART10 </name>
+//    <item> SFDITEM_REG__USART10_CR1 </item>
+//    <item> SFDITEM_REG__USART10_CR2 </item>
+//    <item> SFDITEM_REG__USART10_ST </item>
+//    <item> SFDITEM_REG__USART10_BDR </item>
+//    <item> SFDITEM_REG__USART10_DR </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: USART11_CR1  -------------------------------
+// SVD Line: 17423
+
+unsigned int USART11_CR1 __AT (0x40003900);
+
+
+
+// -----------------------------  Field Item: USART11_CR1_USTnMS  ---------------------------------
+// SVD Line: 17432
+
+//  <item> SFDITEM_FIELD__USART11_CR1_USTnMS
+//    <name> USTnMS </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x40003900) \nUSART1n Operation Mode Selection\n0 : Async = Asynchronous Mode (UART)\n1 : Sync = Synchronous Mode (USRT)\n2 : Reserved - do not use\n3 : SPI = SPI Mode </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.15..14> USTnMS
+//        <0=> 0: Async = Asynchronous Mode (UART)
+//        <1=> 1: Sync = Synchronous Mode (USRT)
+//        <2=> 2: 
+//        <3=> 3: SPI = SPI Mode
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR1_USTnP  ---------------------------------
+// SVD Line: 17455
+
+//  <item> SFDITEM_FIELD__USART11_CR1_USTnP
+//    <name> USTnP </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40003900) \nSelects Parity Generation and Check method (only UART mode)\n0 : No = No Parity\n1 : Reserved - do not use\n2 : Even = Even Parity\n3 : Odd = Odd Parity </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.13..12> USTnP
+//        <0=> 0: No = No Parity
+//        <1=> 1: 
+//        <2=> 2: Even = Even Parity
+//        <3=> 3: Odd = Odd Parity
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR1_USTnS  ---------------------------------
+// SVD Line: 17478
+
+//  <item> SFDITEM_FIELD__USART11_CR1_USTnS
+//    <name> USTnS </name>
+//    <rw> 
+//    <i> [Bits 11..9] RW (@ 0x40003900) \nSelects the length of data bit in a frame when Asynchronous or Synchronous mode\n0 : 5bit = 5 bit\n1 : 6bit = 6 bit\n2 : 7bit = 7 bit\n3 : 8bit = 8 bit\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : 9bit = 9 bit </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.11..9> USTnS
+//        <0=> 0: 5bit = 5 bit
+//        <1=> 1: 6bit = 6 bit
+//        <2=> 2: 7bit = 7 bit
+//        <3=> 3: 8bit = 8 bit
+//        <4=> 4: 
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 9bit = 9 bit
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR1_ORDn  ----------------------------------
+// SVD Line: 17511
+
+//  <item> SFDITEM_FIELD__USART11_CR1_ORDn
+//    <name> ORDn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003900) \nSelects the first data bit to be transmitted (only SPI mode)\n0 : lsbFirst = LSB First\n1 : msbFirst = MSB First </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.8..8> ORDn
+//        <0=> 0: lsbFirst = LSB First
+//        <1=> 1: msbFirst = MSB First
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR1_CPOLn  ---------------------------------
+// SVD Line: 17529
+
+//  <item> SFDITEM_FIELD__USART11_CR1_CPOLn
+//    <name> CPOLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003900) \nSelects the Clock Polarity of ACK in Synchronous or SPI mode\n0 : IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge\n1 : IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.7..7> CPOLn
+//        <0=> 0: IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge
+//        <1=> 1: IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR1_CPHAn  ---------------------------------
+// SVD Line: 17547
+
+//  <item> SFDITEM_FIELD__USART11_CR1_CPHAn
+//    <name> CPHAn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003900) \nThe CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)\n0 : StartIdle = Start with idle state.\n1 : StartInverted = Start with inverted idle state. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.6..6> CPHAn
+//        <0=> 0: StartIdle = Start with idle state.
+//        <1=> 1: StartInverted = Start with inverted idle state.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR1_DRIEn  ---------------------------------
+// SVD Line: 17565
+
+//  <item> SFDITEM_FIELD__USART11_CR1_DRIEn
+//    <name> DRIEn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003900) Transmit Data Register Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.5..5> DRIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR1_TXCIEn  ---------------------------------
+// SVD Line: 17571
+
+//  <item> SFDITEM_FIELD__USART11_CR1_TXCIEn
+//    <name> TXCIEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003900) Transmit Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.4..4> TXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR1_RXCIEn  ---------------------------------
+// SVD Line: 17577
+
+//  <item> SFDITEM_FIELD__USART11_CR1_RXCIEn
+//    <name> RXCIEn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40003900) Receive Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.3..3> RXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR1_WAKEIEn  --------------------------------
+// SVD Line: 17583
+
+//  <item> SFDITEM_FIELD__USART11_CR1_WAKEIEn
+//    <name> WAKEIEn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40003900) Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.2..2> WAKEIEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR1_TXEn  ----------------------------------
+// SVD Line: 17589
+
+//  <item> SFDITEM_FIELD__USART11_CR1_TXEn
+//    <name> TXEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003900) Enable the transmitter unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.1..1> TXEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR1_RXEn  ----------------------------------
+// SVD Line: 17595
+
+//  <item> SFDITEM_FIELD__USART11_CR1_RXEn
+//    <name> RXEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003900) Enable the receiver unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR1 ) </loc>
+//      <o.0..0> RXEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART11_CR1  ----------------------------------
+// SVD Line: 17423
+
+//  <rtree> SFDITEM_REG__USART11_CR1
+//    <name> CR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003900) USART1n Control Register 1 </i>
+//    <loc> ( (unsigned int)((USART11_CR1 >> 0) & 0xFFFFFFFF), ((USART11_CR1 = (USART11_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART11_CR1_USTnMS </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_USTnP </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_USTnS </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_ORDn </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_CPOLn </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_CPHAn </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_DRIEn </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_TXCIEn </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_RXCIEn </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_WAKEIEn </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_TXEn </item>
+//    <item> SFDITEM_FIELD__USART11_CR1_RXEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART11_CR2  -------------------------------
+// SVD Line: 17603
+
+unsigned int USART11_CR2 __AT (0x40003904);
+
+
+
+// -----------------------------  Field Item: USART11_CR2_USTnEN  ---------------------------------
+// SVD Line: 17612
+
+//  <item> SFDITEM_FIELD__USART11_CR2_USTnEN
+//    <name> USTnEN </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40003904) Activate USART1n Block </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.9..9> USTnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR2_DBLSn  ---------------------------------
+// SVD Line: 17618
+
+//  <item> SFDITEM_FIELD__USART11_CR2_DBLSn
+//    <name> DBLSn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003904) Selects receiver sampling rate (only UART mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.8..8> DBLSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR2_MASTERn  --------------------------------
+// SVD Line: 17624
+
+//  <item> SFDITEM_FIELD__USART11_CR2_MASTERn
+//    <name> MASTERn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003904) Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.7..7> MASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR2_LOOPSn  ---------------------------------
+// SVD Line: 17630
+
+//  <item> SFDITEM_FIELD__USART11_CR2_LOOPSn
+//    <name> LOOPSn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003904) Control the Loop Back mode of USART1n for test mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.6..6> LOOPSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR2_DISSCKn  --------------------------------
+// SVD Line: 17636
+
+//  <item> SFDITEM_FIELD__USART11_CR2_DISSCKn
+//    <name> DISSCKn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003904) In synchronous mode operation, selects the waveform of SCK1n output </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.5..5> DISSCKn
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: USART11_CR2_USTnSSEN  --------------------------------
+// SVD Line: 17642
+
+//  <item> SFDITEM_FIELD__USART11_CR2_USTnSSEN
+//    <name> USTnSSEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003904) This bit controls the SS1n pin operation (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.4..4> USTnSSEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_CR2_FXCHn  ---------------------------------
+// SVD Line: 17648
+
+//  <item> SFDITEM_FIELD__USART11_CR2_FXCHn
+//    <name> FXCHn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40003904) SPI1n port function exchange control (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.3..3> FXCHn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR2_USTnSB  ---------------------------------
+// SVD Line: 17654
+
+//  <item> SFDITEM_FIELD__USART11_CR2_USTnSB
+//    <name> USTnSB </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40003904) Selects the length of stop bit in Asynchronous or Synchronous mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.2..2> USTnSB
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR2_USTnTX8  --------------------------------
+// SVD Line: 17660
+
+//  <item> SFDITEM_FIELD__USART11_CR2_USTnTX8
+//    <name> USTnTX8 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003904) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.1..1> USTnTX8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART11_CR2_USTnRX8  --------------------------------
+// SVD Line: 17666
+
+//  <item> SFDITEM_FIELD__USART11_CR2_USTnRX8
+//    <name> USTnRX8 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003904) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_CR2 ) </loc>
+//      <o.0..0> USTnRX8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART11_CR2  ----------------------------------
+// SVD Line: 17603
+
+//  <rtree> SFDITEM_REG__USART11_CR2
+//    <name> CR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003904) USART1n Control Register 2 </i>
+//    <loc> ( (unsigned int)((USART11_CR2 >> 0) & 0xFFFFFFFF), ((USART11_CR2 = (USART11_CR2 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART11_CR2_USTnEN </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_DBLSn </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_MASTERn </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_LOOPSn </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_DISSCKn </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_USTnSSEN </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_FXCHn </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_USTnSB </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_USTnTX8 </item>
+//    <item> SFDITEM_FIELD__USART11_CR2_USTnRX8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART11_ST  -------------------------------
+// SVD Line: 17674
+
+unsigned int USART11_ST __AT (0x4000390C);
+
+
+
+// -------------------------------  Field Item: USART11_ST_DREn  ----------------------------------
+// SVD Line: 17683
+
+//  <item> SFDITEM_FIELD__USART11_ST_DREn
+//    <name> DREn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x4000390C) Transmit Data Register Empty Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_ST ) </loc>
+//      <o.7..7> DREn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART11_ST_TXCn  ----------------------------------
+// SVD Line: 17689
+
+//  <item> SFDITEM_FIELD__USART11_ST_TXCn
+//    <name> TXCn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x4000390C) Transmit Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_ST ) </loc>
+//      <o.6..6> TXCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART11_ST_RXCn  ----------------------------------
+// SVD Line: 17695
+
+//  <item> SFDITEM_FIELD__USART11_ST_RXCn
+//    <name> RXCn </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x4000390C) Receive Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_ST ) </loc>
+//      <o.5..5> RXCn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART11_ST_WAKEn  ----------------------------------
+// SVD Line: 17701
+
+//  <item> SFDITEM_FIELD__USART11_ST_WAKEn
+//    <name> WAKEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x4000390C) Asynchronous Wake-Up Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_ST ) </loc>
+//      <o.4..4> WAKEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART11_ST_DORn  ----------------------------------
+// SVD Line: 17707
+
+//  <item> SFDITEM_FIELD__USART11_ST_DORn
+//    <name> DORn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x4000390C) This bit is set if data OverRun takes place </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_ST ) </loc>
+//      <o.2..2> DORn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART11_ST_FEn  -----------------------------------
+// SVD Line: 17713
+
+//  <item> SFDITEM_FIELD__USART11_ST_FEn
+//    <name> FEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x4000390C) This bit is set if the first stop bit of next character in the receive buffer is detected as '0' </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_ST ) </loc>
+//      <o.1..1> FEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART11_ST_PEn  -----------------------------------
+// SVD Line: 17719
+
+//  <item> SFDITEM_FIELD__USART11_ST_PEn
+//    <name> PEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x4000390C) This bit is set if the next character in the receive buffer has a Parity Error while parity is checked </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART11_ST ) </loc>
+//      <o.0..0> PEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART11_ST  -----------------------------------
+// SVD Line: 17674
+
+//  <rtree> SFDITEM_REG__USART11_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000390C) USART1n Status Register </i>
+//    <loc> ( (unsigned int)((USART11_ST >> 0) & 0xFFFFFFFF), ((USART11_ST = (USART11_ST & ~(0xD3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD3) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART11_ST_DREn </item>
+//    <item> SFDITEM_FIELD__USART11_ST_TXCn </item>
+//    <item> SFDITEM_FIELD__USART11_ST_RXCn </item>
+//    <item> SFDITEM_FIELD__USART11_ST_WAKEn </item>
+//    <item> SFDITEM_FIELD__USART11_ST_DORn </item>
+//    <item> SFDITEM_FIELD__USART11_ST_FEn </item>
+//    <item> SFDITEM_FIELD__USART11_ST_PEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART11_BDR  -------------------------------
+// SVD Line: 17727
+
+unsigned int USART11_BDR __AT (0x40003910);
+
+
+
+// ------------------------------  Field Item: USART11_BDR_BDATA  ---------------------------------
+// SVD Line: 17736
+
+//  <item> SFDITEM_FIELD__USART11_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40003910) The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((USART11_BDR >> 0) & 0xFFF), ((USART11_BDR = (USART11_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART11_BDR  ----------------------------------
+// SVD Line: 17727
+
+//  <rtree> SFDITEM_REG__USART11_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003910) USART1n Baud Rate Generation Register </i>
+//    <loc> ( (unsigned int)((USART11_BDR >> 0) & 0xFFFFFFFF), ((USART11_BDR = (USART11_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART11_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART11_DR  -------------------------------
+// SVD Line: 17744
+
+unsigned int USART11_DR __AT (0x40003914);
+
+
+
+// -------------------------------  Field Item: USART11_DR_DATA  ----------------------------------
+// SVD Line: 17753
+
+//  <item> SFDITEM_FIELD__USART11_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40003914) The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((USART11_DR >> 0) & 0xFF), ((USART11_DR = (USART11_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART11_DR  -----------------------------------
+// SVD Line: 17744
+
+//  <rtree> SFDITEM_REG__USART11_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003914) USART1n Data Register </i>
+//    <loc> ( (unsigned int)((USART11_DR >> 0) & 0xFFFFFFFF), ((USART11_DR = (USART11_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART11_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: USART11  ------------------------------------
+// SVD Line: 17782
+
+//  <view> USART11
+//    <name> USART11 </name>
+//    <item> SFDITEM_REG__USART11_CR1 </item>
+//    <item> SFDITEM_REG__USART11_CR2 </item>
+//    <item> SFDITEM_REG__USART11_ST </item>
+//    <item> SFDITEM_REG__USART11_BDR </item>
+//    <item> SFDITEM_REG__USART11_DR </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: USART12_CR1  -------------------------------
+// SVD Line: 17423
+
+unsigned int USART12_CR1 __AT (0x40003A00);
+
+
+
+// -----------------------------  Field Item: USART12_CR1_USTnMS  ---------------------------------
+// SVD Line: 17432
+
+//  <item> SFDITEM_FIELD__USART12_CR1_USTnMS
+//    <name> USTnMS </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x40003A00) \nUSART1n Operation Mode Selection\n0 : Async = Asynchronous Mode (UART)\n1 : Sync = Synchronous Mode (USRT)\n2 : Reserved - do not use\n3 : SPI = SPI Mode </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.15..14> USTnMS
+//        <0=> 0: Async = Asynchronous Mode (UART)
+//        <1=> 1: Sync = Synchronous Mode (USRT)
+//        <2=> 2: 
+//        <3=> 3: SPI = SPI Mode
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR1_USTnP  ---------------------------------
+// SVD Line: 17455
+
+//  <item> SFDITEM_FIELD__USART12_CR1_USTnP
+//    <name> USTnP </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40003A00) \nSelects Parity Generation and Check method (only UART mode)\n0 : No = No Parity\n1 : Reserved - do not use\n2 : Even = Even Parity\n3 : Odd = Odd Parity </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.13..12> USTnP
+//        <0=> 0: No = No Parity
+//        <1=> 1: 
+//        <2=> 2: Even = Even Parity
+//        <3=> 3: Odd = Odd Parity
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR1_USTnS  ---------------------------------
+// SVD Line: 17478
+
+//  <item> SFDITEM_FIELD__USART12_CR1_USTnS
+//    <name> USTnS </name>
+//    <rw> 
+//    <i> [Bits 11..9] RW (@ 0x40003A00) \nSelects the length of data bit in a frame when Asynchronous or Synchronous mode\n0 : 5bit = 5 bit\n1 : 6bit = 6 bit\n2 : 7bit = 7 bit\n3 : 8bit = 8 bit\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : 9bit = 9 bit </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.11..9> USTnS
+//        <0=> 0: 5bit = 5 bit
+//        <1=> 1: 6bit = 6 bit
+//        <2=> 2: 7bit = 7 bit
+//        <3=> 3: 8bit = 8 bit
+//        <4=> 4: 
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 9bit = 9 bit
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR1_ORDn  ----------------------------------
+// SVD Line: 17511
+
+//  <item> SFDITEM_FIELD__USART12_CR1_ORDn
+//    <name> ORDn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003A00) \nSelects the first data bit to be transmitted (only SPI mode)\n0 : lsbFirst = LSB First\n1 : msbFirst = MSB First </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.8..8> ORDn
+//        <0=> 0: lsbFirst = LSB First
+//        <1=> 1: msbFirst = MSB First
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR1_CPOLn  ---------------------------------
+// SVD Line: 17529
+
+//  <item> SFDITEM_FIELD__USART12_CR1_CPOLn
+//    <name> CPOLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003A00) \nSelects the Clock Polarity of ACK in Synchronous or SPI mode\n0 : IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge\n1 : IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.7..7> CPOLn
+//        <0=> 0: IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge
+//        <1=> 1: IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR1_CPHAn  ---------------------------------
+// SVD Line: 17547
+
+//  <item> SFDITEM_FIELD__USART12_CR1_CPHAn
+//    <name> CPHAn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003A00) \nThe CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)\n0 : StartIdle = Start with idle state.\n1 : StartInverted = Start with inverted idle state. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.6..6> CPHAn
+//        <0=> 0: StartIdle = Start with idle state.
+//        <1=> 1: StartInverted = Start with inverted idle state.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR1_DRIEn  ---------------------------------
+// SVD Line: 17565
+
+//  <item> SFDITEM_FIELD__USART12_CR1_DRIEn
+//    <name> DRIEn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003A00) Transmit Data Register Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.5..5> DRIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR1_TXCIEn  ---------------------------------
+// SVD Line: 17571
+
+//  <item> SFDITEM_FIELD__USART12_CR1_TXCIEn
+//    <name> TXCIEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003A00) Transmit Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.4..4> TXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR1_RXCIEn  ---------------------------------
+// SVD Line: 17577
+
+//  <item> SFDITEM_FIELD__USART12_CR1_RXCIEn
+//    <name> RXCIEn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40003A00) Receive Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.3..3> RXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR1_WAKEIEn  --------------------------------
+// SVD Line: 17583
+
+//  <item> SFDITEM_FIELD__USART12_CR1_WAKEIEn
+//    <name> WAKEIEn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40003A00) Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.2..2> WAKEIEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR1_TXEn  ----------------------------------
+// SVD Line: 17589
+
+//  <item> SFDITEM_FIELD__USART12_CR1_TXEn
+//    <name> TXEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003A00) Enable the transmitter unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.1..1> TXEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR1_RXEn  ----------------------------------
+// SVD Line: 17595
+
+//  <item> SFDITEM_FIELD__USART12_CR1_RXEn
+//    <name> RXEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003A00) Enable the receiver unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR1 ) </loc>
+//      <o.0..0> RXEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART12_CR1  ----------------------------------
+// SVD Line: 17423
+
+//  <rtree> SFDITEM_REG__USART12_CR1
+//    <name> CR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003A00) USART1n Control Register 1 </i>
+//    <loc> ( (unsigned int)((USART12_CR1 >> 0) & 0xFFFFFFFF), ((USART12_CR1 = (USART12_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART12_CR1_USTnMS </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_USTnP </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_USTnS </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_ORDn </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_CPOLn </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_CPHAn </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_DRIEn </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_TXCIEn </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_RXCIEn </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_WAKEIEn </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_TXEn </item>
+//    <item> SFDITEM_FIELD__USART12_CR1_RXEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART12_CR2  -------------------------------
+// SVD Line: 17603
+
+unsigned int USART12_CR2 __AT (0x40003A04);
+
+
+
+// -----------------------------  Field Item: USART12_CR2_USTnEN  ---------------------------------
+// SVD Line: 17612
+
+//  <item> SFDITEM_FIELD__USART12_CR2_USTnEN
+//    <name> USTnEN </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40003A04) Activate USART1n Block </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.9..9> USTnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR2_DBLSn  ---------------------------------
+// SVD Line: 17618
+
+//  <item> SFDITEM_FIELD__USART12_CR2_DBLSn
+//    <name> DBLSn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003A04) Selects receiver sampling rate (only UART mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.8..8> DBLSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR2_MASTERn  --------------------------------
+// SVD Line: 17624
+
+//  <item> SFDITEM_FIELD__USART12_CR2_MASTERn
+//    <name> MASTERn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003A04) Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.7..7> MASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR2_LOOPSn  ---------------------------------
+// SVD Line: 17630
+
+//  <item> SFDITEM_FIELD__USART12_CR2_LOOPSn
+//    <name> LOOPSn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003A04) Control the Loop Back mode of USART1n for test mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.6..6> LOOPSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR2_DISSCKn  --------------------------------
+// SVD Line: 17636
+
+//  <item> SFDITEM_FIELD__USART12_CR2_DISSCKn
+//    <name> DISSCKn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003A04) In synchronous mode operation, selects the waveform of SCK1n output </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.5..5> DISSCKn
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: USART12_CR2_USTnSSEN  --------------------------------
+// SVD Line: 17642
+
+//  <item> SFDITEM_FIELD__USART12_CR2_USTnSSEN
+//    <name> USTnSSEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003A04) This bit controls the SS1n pin operation (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.4..4> USTnSSEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_CR2_FXCHn  ---------------------------------
+// SVD Line: 17648
+
+//  <item> SFDITEM_FIELD__USART12_CR2_FXCHn
+//    <name> FXCHn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40003A04) SPI1n port function exchange control (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.3..3> FXCHn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR2_USTnSB  ---------------------------------
+// SVD Line: 17654
+
+//  <item> SFDITEM_FIELD__USART12_CR2_USTnSB
+//    <name> USTnSB </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40003A04) Selects the length of stop bit in Asynchronous or Synchronous mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.2..2> USTnSB
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR2_USTnTX8  --------------------------------
+// SVD Line: 17660
+
+//  <item> SFDITEM_FIELD__USART12_CR2_USTnTX8
+//    <name> USTnTX8 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003A04) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.1..1> USTnTX8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART12_CR2_USTnRX8  --------------------------------
+// SVD Line: 17666
+
+//  <item> SFDITEM_FIELD__USART12_CR2_USTnRX8
+//    <name> USTnRX8 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003A04) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_CR2 ) </loc>
+//      <o.0..0> USTnRX8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART12_CR2  ----------------------------------
+// SVD Line: 17603
+
+//  <rtree> SFDITEM_REG__USART12_CR2
+//    <name> CR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003A04) USART1n Control Register 2 </i>
+//    <loc> ( (unsigned int)((USART12_CR2 >> 0) & 0xFFFFFFFF), ((USART12_CR2 = (USART12_CR2 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART12_CR2_USTnEN </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_DBLSn </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_MASTERn </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_LOOPSn </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_DISSCKn </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_USTnSSEN </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_FXCHn </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_USTnSB </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_USTnTX8 </item>
+//    <item> SFDITEM_FIELD__USART12_CR2_USTnRX8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART12_ST  -------------------------------
+// SVD Line: 17674
+
+unsigned int USART12_ST __AT (0x40003A0C);
+
+
+
+// -------------------------------  Field Item: USART12_ST_DREn  ----------------------------------
+// SVD Line: 17683
+
+//  <item> SFDITEM_FIELD__USART12_ST_DREn
+//    <name> DREn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003A0C) Transmit Data Register Empty Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_ST ) </loc>
+//      <o.7..7> DREn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART12_ST_TXCn  ----------------------------------
+// SVD Line: 17689
+
+//  <item> SFDITEM_FIELD__USART12_ST_TXCn
+//    <name> TXCn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003A0C) Transmit Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_ST ) </loc>
+//      <o.6..6> TXCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART12_ST_RXCn  ----------------------------------
+// SVD Line: 17695
+
+//  <item> SFDITEM_FIELD__USART12_ST_RXCn
+//    <name> RXCn </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x40003A0C) Receive Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_ST ) </loc>
+//      <o.5..5> RXCn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART12_ST_WAKEn  ----------------------------------
+// SVD Line: 17701
+
+//  <item> SFDITEM_FIELD__USART12_ST_WAKEn
+//    <name> WAKEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003A0C) Asynchronous Wake-Up Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_ST ) </loc>
+//      <o.4..4> WAKEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART12_ST_DORn  ----------------------------------
+// SVD Line: 17707
+
+//  <item> SFDITEM_FIELD__USART12_ST_DORn
+//    <name> DORn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x40003A0C) This bit is set if data OverRun takes place </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_ST ) </loc>
+//      <o.2..2> DORn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART12_ST_FEn  -----------------------------------
+// SVD Line: 17713
+
+//  <item> SFDITEM_FIELD__USART12_ST_FEn
+//    <name> FEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003A0C) This bit is set if the first stop bit of next character in the receive buffer is detected as '0' </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_ST ) </loc>
+//      <o.1..1> FEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART12_ST_PEn  -----------------------------------
+// SVD Line: 17719
+
+//  <item> SFDITEM_FIELD__USART12_ST_PEn
+//    <name> PEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003A0C) This bit is set if the next character in the receive buffer has a Parity Error while parity is checked </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART12_ST ) </loc>
+//      <o.0..0> PEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART12_ST  -----------------------------------
+// SVD Line: 17674
+
+//  <rtree> SFDITEM_REG__USART12_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003A0C) USART1n Status Register </i>
+//    <loc> ( (unsigned int)((USART12_ST >> 0) & 0xFFFFFFFF), ((USART12_ST = (USART12_ST & ~(0xD3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD3) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART12_ST_DREn </item>
+//    <item> SFDITEM_FIELD__USART12_ST_TXCn </item>
+//    <item> SFDITEM_FIELD__USART12_ST_RXCn </item>
+//    <item> SFDITEM_FIELD__USART12_ST_WAKEn </item>
+//    <item> SFDITEM_FIELD__USART12_ST_DORn </item>
+//    <item> SFDITEM_FIELD__USART12_ST_FEn </item>
+//    <item> SFDITEM_FIELD__USART12_ST_PEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART12_BDR  -------------------------------
+// SVD Line: 17727
+
+unsigned int USART12_BDR __AT (0x40003A10);
+
+
+
+// ------------------------------  Field Item: USART12_BDR_BDATA  ---------------------------------
+// SVD Line: 17736
+
+//  <item> SFDITEM_FIELD__USART12_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40003A10) The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((USART12_BDR >> 0) & 0xFFF), ((USART12_BDR = (USART12_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART12_BDR  ----------------------------------
+// SVD Line: 17727
+
+//  <rtree> SFDITEM_REG__USART12_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003A10) USART1n Baud Rate Generation Register </i>
+//    <loc> ( (unsigned int)((USART12_BDR >> 0) & 0xFFFFFFFF), ((USART12_BDR = (USART12_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART12_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART12_DR  -------------------------------
+// SVD Line: 17744
+
+unsigned int USART12_DR __AT (0x40003A14);
+
+
+
+// -------------------------------  Field Item: USART12_DR_DATA  ----------------------------------
+// SVD Line: 17753
+
+//  <item> SFDITEM_FIELD__USART12_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40003A14) The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((USART12_DR >> 0) & 0xFF), ((USART12_DR = (USART12_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART12_DR  -----------------------------------
+// SVD Line: 17744
+
+//  <rtree> SFDITEM_REG__USART12_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003A14) USART1n Data Register </i>
+//    <loc> ( (unsigned int)((USART12_DR >> 0) & 0xFFFFFFFF), ((USART12_DR = (USART12_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART12_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: USART12  ------------------------------------
+// SVD Line: 17801
+
+//  <view> USART12
+//    <name> USART12 </name>
+//    <item> SFDITEM_REG__USART12_CR1 </item>
+//    <item> SFDITEM_REG__USART12_CR2 </item>
+//    <item> SFDITEM_REG__USART12_ST </item>
+//    <item> SFDITEM_REG__USART12_BDR </item>
+//    <item> SFDITEM_REG__USART12_DR </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: USART13_CR1  -------------------------------
+// SVD Line: 17423
+
+unsigned int USART13_CR1 __AT (0x40003B00);
+
+
+
+// -----------------------------  Field Item: USART13_CR1_USTnMS  ---------------------------------
+// SVD Line: 17432
+
+//  <item> SFDITEM_FIELD__USART13_CR1_USTnMS
+//    <name> USTnMS </name>
+//    <rw> 
+//    <i> [Bits 15..14] RW (@ 0x40003B00) \nUSART1n Operation Mode Selection\n0 : Async = Asynchronous Mode (UART)\n1 : Sync = Synchronous Mode (USRT)\n2 : Reserved - do not use\n3 : SPI = SPI Mode </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.15..14> USTnMS
+//        <0=> 0: Async = Asynchronous Mode (UART)
+//        <1=> 1: Sync = Synchronous Mode (USRT)
+//        <2=> 2: 
+//        <3=> 3: SPI = SPI Mode
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR1_USTnP  ---------------------------------
+// SVD Line: 17455
+
+//  <item> SFDITEM_FIELD__USART13_CR1_USTnP
+//    <name> USTnP </name>
+//    <rw> 
+//    <i> [Bits 13..12] RW (@ 0x40003B00) \nSelects Parity Generation and Check method (only UART mode)\n0 : No = No Parity\n1 : Reserved - do not use\n2 : Even = Even Parity\n3 : Odd = Odd Parity </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.13..12> USTnP
+//        <0=> 0: No = No Parity
+//        <1=> 1: 
+//        <2=> 2: Even = Even Parity
+//        <3=> 3: Odd = Odd Parity
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR1_USTnS  ---------------------------------
+// SVD Line: 17478
+
+//  <item> SFDITEM_FIELD__USART13_CR1_USTnS
+//    <name> USTnS </name>
+//    <rw> 
+//    <i> [Bits 11..9] RW (@ 0x40003B00) \nSelects the length of data bit in a frame when Asynchronous or Synchronous mode\n0 : 5bit = 5 bit\n1 : 6bit = 6 bit\n2 : 7bit = 7 bit\n3 : 8bit = 8 bit\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : 9bit = 9 bit </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.11..9> USTnS
+//        <0=> 0: 5bit = 5 bit
+//        <1=> 1: 6bit = 6 bit
+//        <2=> 2: 7bit = 7 bit
+//        <3=> 3: 8bit = 8 bit
+//        <4=> 4: 
+//        <5=> 5: 
+//        <6=> 6: 
+//        <7=> 7: 9bit = 9 bit
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR1_ORDn  ----------------------------------
+// SVD Line: 17511
+
+//  <item> SFDITEM_FIELD__USART13_CR1_ORDn
+//    <name> ORDn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003B00) \nSelects the first data bit to be transmitted (only SPI mode)\n0 : lsbFirst = LSB First\n1 : msbFirst = MSB First </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.8..8> ORDn
+//        <0=> 0: lsbFirst = LSB First
+//        <1=> 1: msbFirst = MSB First
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR1_CPOLn  ---------------------------------
+// SVD Line: 17529
+
+//  <item> SFDITEM_FIELD__USART13_CR1_CPOLn
+//    <name> CPOLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003B00) \nSelects the Clock Polarity of ACK in Synchronous or SPI mode\n0 : IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge\n1 : IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.7..7> CPOLn
+//        <0=> 0: IdleLow = TXD Change @Rising Edge, RXD Change @Falling Edge
+//        <1=> 1: IdleHigh = TXD Change @Falling Edge, RXD Change @Rising Edge
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR1_CPHAn  ---------------------------------
+// SVD Line: 17547
+
+//  <item> SFDITEM_FIELD__USART13_CR1_CPHAn
+//    <name> CPHAn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003B00) \nThe CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)\n0 : StartIdle = Start with idle state.\n1 : StartInverted = Start with inverted idle state. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.6..6> CPHAn
+//        <0=> 0: StartIdle = Start with idle state.
+//        <1=> 1: StartInverted = Start with inverted idle state.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR1_DRIEn  ---------------------------------
+// SVD Line: 17565
+
+//  <item> SFDITEM_FIELD__USART13_CR1_DRIEn
+//    <name> DRIEn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003B00) Transmit Data Register Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.5..5> DRIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR1_TXCIEn  ---------------------------------
+// SVD Line: 17571
+
+//  <item> SFDITEM_FIELD__USART13_CR1_TXCIEn
+//    <name> TXCIEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003B00) Transmit Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.4..4> TXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR1_RXCIEn  ---------------------------------
+// SVD Line: 17577
+
+//  <item> SFDITEM_FIELD__USART13_CR1_RXCIEn
+//    <name> RXCIEn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40003B00) Receive Complete Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.3..3> RXCIEn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR1_WAKEIEn  --------------------------------
+// SVD Line: 17583
+
+//  <item> SFDITEM_FIELD__USART13_CR1_WAKEIEn
+//    <name> WAKEIEn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40003B00) Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.2..2> WAKEIEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR1_TXEn  ----------------------------------
+// SVD Line: 17589
+
+//  <item> SFDITEM_FIELD__USART13_CR1_TXEn
+//    <name> TXEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003B00) Enable the transmitter unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.1..1> TXEn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR1_RXEn  ----------------------------------
+// SVD Line: 17595
+
+//  <item> SFDITEM_FIELD__USART13_CR1_RXEn
+//    <name> RXEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003B00) Enable the receiver unit. </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR1 ) </loc>
+//      <o.0..0> RXEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART13_CR1  ----------------------------------
+// SVD Line: 17423
+
+//  <rtree> SFDITEM_REG__USART13_CR1
+//    <name> CR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003B00) USART1n Control Register 1 </i>
+//    <loc> ( (unsigned int)((USART13_CR1 >> 0) & 0xFFFFFFFF), ((USART13_CR1 = (USART13_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART13_CR1_USTnMS </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_USTnP </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_USTnS </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_ORDn </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_CPOLn </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_CPHAn </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_DRIEn </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_TXCIEn </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_RXCIEn </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_WAKEIEn </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_TXEn </item>
+//    <item> SFDITEM_FIELD__USART13_CR1_RXEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART13_CR2  -------------------------------
+// SVD Line: 17603
+
+unsigned int USART13_CR2 __AT (0x40003B04);
+
+
+
+// -----------------------------  Field Item: USART13_CR2_USTnEN  ---------------------------------
+// SVD Line: 17612
+
+//  <item> SFDITEM_FIELD__USART13_CR2_USTnEN
+//    <name> USTnEN </name>
+//    <rw> 
+//    <i> [Bit 9] RW (@ 0x40003B04) Activate USART1n Block </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.9..9> USTnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR2_DBLSn  ---------------------------------
+// SVD Line: 17618
+
+//  <item> SFDITEM_FIELD__USART13_CR2_DBLSn
+//    <name> DBLSn </name>
+//    <rw> 
+//    <i> [Bit 8] RW (@ 0x40003B04) Selects receiver sampling rate (only UART mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.8..8> DBLSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR2_MASTERn  --------------------------------
+// SVD Line: 17624
+
+//  <item> SFDITEM_FIELD__USART13_CR2_MASTERn
+//    <name> MASTERn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003B04) Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.7..7> MASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR2_LOOPSn  ---------------------------------
+// SVD Line: 17630
+
+//  <item> SFDITEM_FIELD__USART13_CR2_LOOPSn
+//    <name> LOOPSn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003B04) Control the Loop Back mode of USART1n for test mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.6..6> LOOPSn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR2_DISSCKn  --------------------------------
+// SVD Line: 17636
+
+//  <item> SFDITEM_FIELD__USART13_CR2_DISSCKn
+//    <name> DISSCKn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40003B04) In synchronous mode operation, selects the waveform of SCK1n output </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.5..5> DISSCKn
+//    </check>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: USART13_CR2_USTnSSEN  --------------------------------
+// SVD Line: 17642
+
+//  <item> SFDITEM_FIELD__USART13_CR2_USTnSSEN
+//    <name> USTnSSEN </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003B04) This bit controls the SS1n pin operation (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.4..4> USTnSSEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_CR2_FXCHn  ---------------------------------
+// SVD Line: 17648
+
+//  <item> SFDITEM_FIELD__USART13_CR2_FXCHn
+//    <name> FXCHn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40003B04) SPI1n port function exchange control (only SPI mode) </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.3..3> FXCHn
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR2_USTnSB  ---------------------------------
+// SVD Line: 17654
+
+//  <item> SFDITEM_FIELD__USART13_CR2_USTnSB
+//    <name> USTnSB </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40003B04) Selects the length of stop bit in Asynchronous or Synchronous mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.2..2> USTnSB
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR2_USTnTX8  --------------------------------
+// SVD Line: 17660
+
+//  <item> SFDITEM_FIELD__USART13_CR2_USTnTX8
+//    <name> USTnTX8 </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003B04) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.1..1> USTnTX8
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: USART13_CR2_USTnRX8  --------------------------------
+// SVD Line: 17666
+
+//  <item> SFDITEM_FIELD__USART13_CR2_USTnRX8
+//    <name> USTnRX8 </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003B04) The ninth bit of data frame in Asynchronous or Synchronous mode of operation </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_CR2 ) </loc>
+//      <o.0..0> USTnRX8
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART13_CR2  ----------------------------------
+// SVD Line: 17603
+
+//  <rtree> SFDITEM_REG__USART13_CR2
+//    <name> CR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003B04) USART1n Control Register 2 </i>
+//    <loc> ( (unsigned int)((USART13_CR2 >> 0) & 0xFFFFFFFF), ((USART13_CR2 = (USART13_CR2 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART13_CR2_USTnEN </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_DBLSn </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_MASTERn </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_LOOPSn </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_DISSCKn </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_USTnSSEN </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_FXCHn </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_USTnSB </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_USTnTX8 </item>
+//    <item> SFDITEM_FIELD__USART13_CR2_USTnRX8 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART13_ST  -------------------------------
+// SVD Line: 17674
+
+unsigned int USART13_ST __AT (0x40003B0C);
+
+
+
+// -------------------------------  Field Item: USART13_ST_DREn  ----------------------------------
+// SVD Line: 17683
+
+//  <item> SFDITEM_FIELD__USART13_ST_DREn
+//    <name> DREn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40003B0C) Transmit Data Register Empty Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_ST ) </loc>
+//      <o.7..7> DREn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART13_ST_TXCn  ----------------------------------
+// SVD Line: 17689
+
+//  <item> SFDITEM_FIELD__USART13_ST_TXCn
+//    <name> TXCn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40003B0C) Transmit Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_ST ) </loc>
+//      <o.6..6> TXCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART13_ST_RXCn  ----------------------------------
+// SVD Line: 17695
+
+//  <item> SFDITEM_FIELD__USART13_ST_RXCn
+//    <name> RXCn </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x40003B0C) Receive Complete Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_ST ) </loc>
+//      <o.5..5> RXCn
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: USART13_ST_WAKEn  ----------------------------------
+// SVD Line: 17701
+
+//  <item> SFDITEM_FIELD__USART13_ST_WAKEn
+//    <name> WAKEn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40003B0C) Asynchronous Wake-Up Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_ST ) </loc>
+//      <o.4..4> WAKEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART13_ST_DORn  ----------------------------------
+// SVD Line: 17707
+
+//  <item> SFDITEM_FIELD__USART13_ST_DORn
+//    <name> DORn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x40003B0C) This bit is set if data OverRun takes place </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_ST ) </loc>
+//      <o.2..2> DORn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART13_ST_FEn  -----------------------------------
+// SVD Line: 17713
+
+//  <item> SFDITEM_FIELD__USART13_ST_FEn
+//    <name> FEn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40003B0C) This bit is set if the first stop bit of next character in the receive buffer is detected as '0' </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_ST ) </loc>
+//      <o.1..1> FEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: USART13_ST_PEn  -----------------------------------
+// SVD Line: 17719
+
+//  <item> SFDITEM_FIELD__USART13_ST_PEn
+//    <name> PEn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40003B0C) This bit is set if the next character in the receive buffer has a Parity Error while parity is checked </i>
+//    <check> 
+//      <loc> ( (unsigned int) USART13_ST ) </loc>
+//      <o.0..0> PEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART13_ST  -----------------------------------
+// SVD Line: 17674
+
+//  <rtree> SFDITEM_REG__USART13_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003B0C) USART1n Status Register </i>
+//    <loc> ( (unsigned int)((USART13_ST >> 0) & 0xFFFFFFFF), ((USART13_ST = (USART13_ST & ~(0xD3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD3) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART13_ST_DREn </item>
+//    <item> SFDITEM_FIELD__USART13_ST_TXCn </item>
+//    <item> SFDITEM_FIELD__USART13_ST_RXCn </item>
+//    <item> SFDITEM_FIELD__USART13_ST_WAKEn </item>
+//    <item> SFDITEM_FIELD__USART13_ST_DORn </item>
+//    <item> SFDITEM_FIELD__USART13_ST_FEn </item>
+//    <item> SFDITEM_FIELD__USART13_ST_PEn </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: USART13_BDR  -------------------------------
+// SVD Line: 17727
+
+unsigned int USART13_BDR __AT (0x40003B10);
+
+
+
+// ------------------------------  Field Item: USART13_BDR_BDATA  ---------------------------------
+// SVD Line: 17736
+
+//  <item> SFDITEM_FIELD__USART13_BDR_BDATA
+//    <name> BDATA </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40003B10) The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((USART13_BDR >> 0) & 0xFFF), ((USART13_BDR = (USART13_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART13_BDR  ----------------------------------
+// SVD Line: 17727
+
+//  <rtree> SFDITEM_REG__USART13_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003B10) USART1n Baud Rate Generation Register </i>
+//    <loc> ( (unsigned int)((USART13_BDR >> 0) & 0xFFFFFFFF), ((USART13_BDR = (USART13_BDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART13_BDR_BDATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: USART13_DR  -------------------------------
+// SVD Line: 17744
+
+unsigned int USART13_DR __AT (0x40003B14);
+
+
+
+// -------------------------------  Field Item: USART13_DR_DATA  ----------------------------------
+// SVD Line: 17753
+
+//  <item> SFDITEM_FIELD__USART13_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40003B14) The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((USART13_DR >> 0) & 0xFF), ((USART13_DR = (USART13_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: USART13_DR  -----------------------------------
+// SVD Line: 17744
+
+//  <rtree> SFDITEM_REG__USART13_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40003B14) USART1n Data Register </i>
+//    <loc> ( (unsigned int)((USART13_DR >> 0) & 0xFFFFFFFF), ((USART13_DR = (USART13_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__USART13_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// --------------------------------  Peripheral View: USART13  ------------------------------------
+// SVD Line: 17820
+
+//  <view> USART13
+//    <name> USART13 </name>
+//    <item> SFDITEM_REG__USART13_CR1 </item>
+//    <item> SFDITEM_REG__USART13_CR2 </item>
+//    <item> SFDITEM_REG__USART13_ST </item>
+//    <item> SFDITEM_REG__USART13_BDR </item>
+//    <item> SFDITEM_REG__USART13_DR </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_RBR  --------------------------------
+// SVD Line: 17853
+
+unsigned int UARTn_RBR __AT (0x55000000);
+
+
+
+// --------------------------------  Field Item: UARTn_RBR_RBR  -----------------------------------
+// SVD Line: 17862
+
+//  <item> SFDITEM_FIELD__UARTn_RBR_RBR
+//    <name> RBR </name>
+//    <r> 
+//    <i> [Bits 7..0] RO (@ 0x55000000) UARTn Receive Data Buffer </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UARTn_RBR >> 0) & 0xFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_RBR  -----------------------------------
+// SVD Line: 17853
+
+//  <rtree> SFDITEM_REG__UARTn_RBR
+//    <name> RBR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x55000000) UARTn Receive Data Buffer Register </i>
+//    <loc> ( (unsigned int)((UARTn_RBR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UARTn_RBR_RBR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_THR  --------------------------------
+// SVD Line: 17870
+
+unsigned int UARTn_THR __AT (0x55000000);
+
+
+
+// --------------------------------  Field Item: UARTn_THR_THR  -----------------------------------
+// SVD Line: 17879
+
+//  <item> SFDITEM_FIELD__UARTn_THR_THR
+//    <name> THR </name>
+//    <w> 
+//    <i> [Bits 7..0] WO (@ 0x55000000) UARTn Transmit Data Hold </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UARTn_THR >> 0) & 0x0), ((UARTn_THR = (UARTn_THR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_THR  -----------------------------------
+// SVD Line: 17870
+
+//  <rtree> SFDITEM_REG__UARTn_THR
+//    <name> THR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x55000000) UARTn Transmit Data Hold Register </i>
+//    <loc> ( (unsigned int)((UARTn_THR >> 0) & 0xFFFFFFFF), ((UARTn_THR = (UARTn_THR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UARTn_THR_THR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_IER  --------------------------------
+// SVD Line: 17887
+
+unsigned int UARTn_IER __AT (0x55000004);
+
+
+
+// -------------------------------  Field Item: UARTn_IER_TXEIE  ----------------------------------
+// SVD Line: 17896
+
+//  <item> SFDITEM_FIELD__UARTn_IER_TXEIE
+//    <name> TXEIE </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x55000004) Transmit Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_IER ) </loc>
+//      <o.3..3> TXEIE
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UARTn_IER_RLSIE  ----------------------------------
+// SVD Line: 17902
+
+//  <item> SFDITEM_FIELD__UARTn_IER_RLSIE
+//    <name> RLSIE </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x55000004) Receiver Line Status Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_IER ) </loc>
+//      <o.2..2> RLSIE
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UARTn_IER_THREIE  ----------------------------------
+// SVD Line: 17908
+
+//  <item> SFDITEM_FIELD__UARTn_IER_THREIE
+//    <name> THREIE </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x55000004) Transmit Holding Register Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_IER ) </loc>
+//      <o.1..1> THREIE
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UARTn_IER_DRIE  -----------------------------------
+// SVD Line: 17914
+
+//  <item> SFDITEM_FIELD__UARTn_IER_DRIE
+//    <name> DRIE </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x55000004) Data Receive Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_IER ) </loc>
+//      <o.0..0> DRIE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_IER  -----------------------------------
+// SVD Line: 17887
+
+//  <rtree> SFDITEM_REG__UARTn_IER
+//    <name> IER </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x55000004) UARTn Interrupt Enable Register </i>
+//    <loc> ( (unsigned int)((UARTn_IER >> 0) & 0xFFFFFFFF), ((UARTn_IER = (UARTn_IER & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UARTn_IER_TXEIE </item>
+//    <item> SFDITEM_FIELD__UARTn_IER_RLSIE </item>
+//    <item> SFDITEM_FIELD__UARTn_IER_THREIE </item>
+//    <item> SFDITEM_FIELD__UARTn_IER_DRIE </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_IIR  --------------------------------
+// SVD Line: 17922
+
+unsigned int UARTn_IIR __AT (0x55000008);
+
+
+
+// --------------------------------  Field Item: UARTn_IIR_TXE  -----------------------------------
+// SVD Line: 17931
+
+//  <item> SFDITEM_FIELD__UARTn_IIR_TXE
+//    <name> TXE </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x55000008) Transmit Complete Interrupt Source ID </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_IIR ) </loc>
+//      <o.4..4> TXE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UARTn_IIR_IID  -----------------------------------
+// SVD Line: 17937
+
+//  <item> SFDITEM_FIELD__UARTn_IIR_IID
+//    <name> IID </name>
+//    <r> 
+//    <i> [Bits 2..1] RO (@ 0x55000008) UARTn Interrupt ID </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UARTn_IIR >> 1) & 0x3) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UARTn_IIR_IPEN  -----------------------------------
+// SVD Line: 17943
+
+//  <item> SFDITEM_FIELD__UARTn_IIR_IPEN
+//    <name> IPEN </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x55000008) Interrupt Pending </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_IIR ) </loc>
+//      <o.0..0> IPEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_IIR  -----------------------------------
+// SVD Line: 17922
+
+//  <rtree> SFDITEM_REG__UARTn_IIR
+//    <name> IIR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x55000008) UARTn Interrupt ID Register </i>
+//    <loc> ( (unsigned int)((UARTn_IIR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UARTn_IIR_TXE </item>
+//    <item> SFDITEM_FIELD__UARTn_IIR_IID </item>
+//    <item> SFDITEM_FIELD__UARTn_IIR_IPEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_LCR  --------------------------------
+// SVD Line: 17951
+
+unsigned int UARTn_LCR __AT (0x5500000C);
+
+
+
+// -------------------------------  Field Item: UARTn_LCR_BREAK  ----------------------------------
+// SVD Line: 17960
+
+//  <item> SFDITEM_FIELD__UARTn_LCR_BREAK
+//    <name> BREAK </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x5500000C) Transfer Break Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LCR ) </loc>
+//      <o.6..6> BREAK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UARTn_LCR_STICKP  ----------------------------------
+// SVD Line: 17966
+
+//  <item> SFDITEM_FIELD__UARTn_LCR_STICKP
+//    <name> STICKP </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x5500000C) Force Parity </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LCR ) </loc>
+//      <o.5..5> STICKP
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UARTn_LCR_PARITY  ----------------------------------
+// SVD Line: 17972
+
+//  <item> SFDITEM_FIELD__UARTn_LCR_PARITY
+//    <name> PARITY </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x5500000C) Parity Mode and Parity Stuck Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LCR ) </loc>
+//      <o.4..4> PARITY
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UARTn_LCR_PEN  -----------------------------------
+// SVD Line: 17978
+
+//  <item> SFDITEM_FIELD__UARTn_LCR_PEN
+//    <name> PEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x5500000C) Parity Bit Transfer Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LCR ) </loc>
+//      <o.3..3> PEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UARTn_LCR_STOPBIT  ---------------------------------
+// SVD Line: 17984
+
+//  <item> SFDITEM_FIELD__UARTn_LCR_STOPBIT
+//    <name> STOPBIT </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x5500000C) Stop Bit Length Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LCR ) </loc>
+//      <o.2..2> STOPBIT
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UARTn_LCR_DLEN  -----------------------------------
+// SVD Line: 17990
+
+//  <item> SFDITEM_FIELD__UARTn_LCR_DLEN
+//    <name> DLEN </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x5500000C) Data Length Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UARTn_LCR >> 0) & 0x3), ((UARTn_LCR = (UARTn_LCR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_LCR  -----------------------------------
+// SVD Line: 17951
+
+//  <rtree> SFDITEM_REG__UARTn_LCR
+//    <name> LCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x5500000C) UARTn Line Control Register </i>
+//    <loc> ( (unsigned int)((UARTn_LCR >> 0) & 0xFFFFFFFF), ((UARTn_LCR = (UARTn_LCR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UARTn_LCR_BREAK </item>
+//    <item> SFDITEM_FIELD__UARTn_LCR_STICKP </item>
+//    <item> SFDITEM_FIELD__UARTn_LCR_PARITY </item>
+//    <item> SFDITEM_FIELD__UARTn_LCR_PEN </item>
+//    <item> SFDITEM_FIELD__UARTn_LCR_STOPBIT </item>
+//    <item> SFDITEM_FIELD__UARTn_LCR_DLEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_DCR  --------------------------------
+// SVD Line: 17998
+
+unsigned int UARTn_DCR __AT (0x55000010);
+
+
+
+// -------------------------------  Field Item: UARTn_DCR_LBON  -----------------------------------
+// SVD Line: 18007
+
+//  <item> SFDITEM_FIELD__UARTn_DCR_LBON
+//    <name> LBON </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x55000010) Local Loopback Test Mode Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_DCR ) </loc>
+//      <o.4..4> LBON
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UARTn_DCR_RXINV  ----------------------------------
+// SVD Line: 18013
+
+//  <item> SFDITEM_FIELD__UARTn_DCR_RXINV
+//    <name> RXINV </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x55000010) Receive Data Inversion Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_DCR ) </loc>
+//      <o.3..3> RXINV
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UARTn_DCR_TXINV  ----------------------------------
+// SVD Line: 18019
+
+//  <item> SFDITEM_FIELD__UARTn_DCR_TXINV
+//    <name> TXINV </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x55000010) Transmit Data Inversion Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_DCR ) </loc>
+//      <o.2..2> TXINV
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_DCR  -----------------------------------
+// SVD Line: 17998
+
+//  <rtree> SFDITEM_REG__UARTn_DCR
+//    <name> DCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x55000010) UARTn Data Control Register </i>
+//    <loc> ( (unsigned int)((UARTn_DCR >> 0) & 0xFFFFFFFF), ((UARTn_DCR = (UARTn_DCR & ~(0x1CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1C) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UARTn_DCR_LBON </item>
+//    <item> SFDITEM_FIELD__UARTn_DCR_RXINV </item>
+//    <item> SFDITEM_FIELD__UARTn_DCR_TXINV </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_LSR  --------------------------------
+// SVD Line: 18027
+
+unsigned int UARTn_LSR __AT (0x55000014);
+
+
+
+// -------------------------------  Field Item: UARTn_LSR_TEMT  -----------------------------------
+// SVD Line: 18036
+
+//  <item> SFDITEM_FIELD__UARTn_LSR_TEMT
+//    <name> TEMT </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x55000014) Transmit Register Empty </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LSR ) </loc>
+//      <o.6..6> TEMT
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UARTn_LSR_THRE  -----------------------------------
+// SVD Line: 18042
+
+//  <item> SFDITEM_FIELD__UARTn_LSR_THRE
+//    <name> THRE </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x55000014) Transmit Hold Register Empty </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LSR ) </loc>
+//      <o.5..5> THRE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UARTn_LSR_BI  ------------------------------------
+// SVD Line: 18048
+
+//  <item> SFDITEM_FIELD__UARTn_LSR_BI
+//    <name> BI </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x55000014) Break Condition Indication </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LSR ) </loc>
+//      <o.4..4> BI
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UARTn_LSR_FE  ------------------------------------
+// SVD Line: 18054
+
+//  <item> SFDITEM_FIELD__UARTn_LSR_FE
+//    <name> FE </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x55000014) Frame Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LSR ) </loc>
+//      <o.3..3> FE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UARTn_LSR_PE  ------------------------------------
+// SVD Line: 18060
+
+//  <item> SFDITEM_FIELD__UARTn_LSR_PE
+//    <name> PE </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x55000014) Parity Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LSR ) </loc>
+//      <o.2..2> PE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UARTn_LSR_OE  ------------------------------------
+// SVD Line: 18066
+
+//  <item> SFDITEM_FIELD__UARTn_LSR_OE
+//    <name> OE </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x55000014) Overrun Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LSR ) </loc>
+//      <o.1..1> OE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UARTn_LSR_DR  ------------------------------------
+// SVD Line: 18072
+
+//  <item> SFDITEM_FIELD__UARTn_LSR_DR
+//    <name> DR </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x55000014) Data Receive Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_LSR ) </loc>
+//      <o.0..0> DR
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_LSR  -----------------------------------
+// SVD Line: 18027
+
+//  <rtree> SFDITEM_REG__UARTn_LSR
+//    <name> LSR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x55000014) UARTn Line Status Register </i>
+//    <loc> ( (unsigned int)((UARTn_LSR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UARTn_LSR_TEMT </item>
+//    <item> SFDITEM_FIELD__UARTn_LSR_THRE </item>
+//    <item> SFDITEM_FIELD__UARTn_LSR_BI </item>
+//    <item> SFDITEM_FIELD__UARTn_LSR_FE </item>
+//    <item> SFDITEM_FIELD__UARTn_LSR_PE </item>
+//    <item> SFDITEM_FIELD__UARTn_LSR_OE </item>
+//    <item> SFDITEM_FIELD__UARTn_LSR_DR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_BDR  --------------------------------
+// SVD Line: 18080
+
+unsigned int UARTn_BDR __AT (0x55000020);
+
+
+
+// --------------------------------  Field Item: UARTn_BDR_BDR  -----------------------------------
+// SVD Line: 18089
+
+//  <item> SFDITEM_FIELD__UARTn_BDR_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x55000020) Baud Rate Divider Latch Value </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((UARTn_BDR >> 0) & 0xFFFF), ((UARTn_BDR = (UARTn_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_BDR  -----------------------------------
+// SVD Line: 18080
+
+//  <rtree> SFDITEM_REG__UARTn_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x55000020) UARTn Baud Rate Divisor Latch Register </i>
+//    <loc> ( (unsigned int)((UARTn_BDR >> 0) & 0xFFFFFFFF), ((UARTn_BDR = (UARTn_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UARTn_BDR_BDR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_BFR  --------------------------------
+// SVD Line: 18097
+
+unsigned int UARTn_BFR __AT (0x55000024);
+
+
+
+// --------------------------------  Field Item: UARTn_BFR_BFR  -----------------------------------
+// SVD Line: 18106
+
+//  <item> SFDITEM_FIELD__UARTn_BFR_BFR
+//    <name> BFR </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x55000024) Fraction Counter value </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UARTn_BFR >> 0) & 0xFF), ((UARTn_BFR = (UARTn_BFR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UARTn_BFR  -----------------------------------
+// SVD Line: 18097
+
+//  <rtree> SFDITEM_REG__UARTn_BFR
+//    <name> BFR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x55000024) UARTn Baud Rate Fractional Counter Value </i>
+//    <loc> ( (unsigned int)((UARTn_BFR >> 0) & 0xFFFFFFFF), ((UARTn_BFR = (UARTn_BFR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UARTn_BFR_BFR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UARTn_IDTR  -------------------------------
+// SVD Line: 18121
+
+unsigned int UARTn_IDTR __AT (0x55000030);
+
+
+
+// -------------------------------  Field Item: UARTn_IDTR_SMS  -----------------------------------
+// SVD Line: 18130
+
+//  <item> SFDITEM_FIELD__UARTn_IDTR_SMS
+//    <name> SMS </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x55000030) Start Bit Multi Sampling Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_IDTR ) </loc>
+//      <o.7..7> SMS
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UARTn_IDTR_DMS  -----------------------------------
+// SVD Line: 18136
+
+//  <item> SFDITEM_FIELD__UARTn_IDTR_DMS
+//    <name> DMS </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x55000030) Data Bit Multi Sampling Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UARTn_IDTR ) </loc>
+//      <o.6..6> DMS
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: UARTn_IDTR_WAITVAL  ---------------------------------
+// SVD Line: 18142
+
+//  <item> SFDITEM_FIELD__UARTn_IDTR_WAITVAL
+//    <name> WAITVAL </name>
+//    <rw> 
+//    <i> [Bits 2..0] RW (@ 0x55000030) Wait Time Value </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UARTn_IDTR >> 0) & 0x7), ((UARTn_IDTR = (UARTn_IDTR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: UARTn_IDTR  -----------------------------------
+// SVD Line: 18121
+
+//  <rtree> SFDITEM_REG__UARTn_IDTR
+//    <name> IDTR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x55000030) UARTn Inter-frame Delay Time Register </i>
+//    <loc> ( (unsigned int)((UARTn_IDTR >> 0) & 0xFFFFFFFF), ((UARTn_IDTR = (UARTn_IDTR & ~(0xC7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC7) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UARTn_IDTR_SMS </item>
+//    <item> SFDITEM_FIELD__UARTn_IDTR_DMS </item>
+//    <item> SFDITEM_FIELD__UARTn_IDTR_WAITVAL </item>
+//  </rtree>
+//  
+
+
+// ---------------------------------  Peripheral View: UARTn  -------------------------------------
+// SVD Line: 17839
+
+//  <view> UARTn
+//    <name> UARTn </name>
+//    <item> SFDITEM_REG__UARTn_RBR </item>
+//    <item> SFDITEM_REG__UARTn_THR </item>
+//    <item> SFDITEM_REG__UARTn_IER </item>
+//    <item> SFDITEM_REG__UARTn_IIR </item>
+//    <item> SFDITEM_REG__UARTn_LCR </item>
+//    <item> SFDITEM_REG__UARTn_DCR </item>
+//    <item> SFDITEM_REG__UARTn_LSR </item>
+//    <item> SFDITEM_REG__UARTn_BDR </item>
+//    <item> SFDITEM_REG__UARTn_BFR </item>
+//    <item> SFDITEM_REG__UARTn_IDTR </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_RBR  --------------------------------
+// SVD Line: 17853
+
+unsigned int UART0_RBR __AT (0x40004000);
+
+
+
+// --------------------------------  Field Item: UART0_RBR_RBR  -----------------------------------
+// SVD Line: 17862
+
+//  <item> SFDITEM_FIELD__UART0_RBR_RBR
+//    <name> RBR </name>
+//    <r> 
+//    <i> [Bits 7..0] RO (@ 0x40004000) UARTn Receive Data Buffer </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART0_RBR >> 0) & 0xFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_RBR  -----------------------------------
+// SVD Line: 17853
+
+//  <rtree> SFDITEM_REG__UART0_RBR
+//    <name> RBR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40004000) UARTn Receive Data Buffer Register </i>
+//    <loc> ( (unsigned int)((UART0_RBR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UART0_RBR_RBR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_THR  --------------------------------
+// SVD Line: 17870
+
+unsigned int UART0_THR __AT (0x40004000);
+
+
+
+// --------------------------------  Field Item: UART0_THR_THR  -----------------------------------
+// SVD Line: 17879
+
+//  <item> SFDITEM_FIELD__UART0_THR_THR
+//    <name> THR </name>
+//    <w> 
+//    <i> [Bits 7..0] WO (@ 0x40004000) UARTn Transmit Data Hold </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART0_THR >> 0) & 0x0), ((UART0_THR = (UART0_THR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_THR  -----------------------------------
+// SVD Line: 17870
+
+//  <rtree> SFDITEM_REG__UART0_THR
+//    <name> THR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x40004000) UARTn Transmit Data Hold Register </i>
+//    <loc> ( (unsigned int)((UART0_THR >> 0) & 0xFFFFFFFF), ((UART0_THR = (UART0_THR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART0_THR_THR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_IER  --------------------------------
+// SVD Line: 17887
+
+unsigned int UART0_IER __AT (0x40004004);
+
+
+
+// -------------------------------  Field Item: UART0_IER_TXEIE  ----------------------------------
+// SVD Line: 17896
+
+//  <item> SFDITEM_FIELD__UART0_IER_TXEIE
+//    <name> TXEIE </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004004) Transmit Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_IER ) </loc>
+//      <o.3..3> TXEIE
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART0_IER_RLSIE  ----------------------------------
+// SVD Line: 17902
+
+//  <item> SFDITEM_FIELD__UART0_IER_RLSIE
+//    <name> RLSIE </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40004004) Receiver Line Status Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_IER ) </loc>
+//      <o.2..2> RLSIE
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UART0_IER_THREIE  ----------------------------------
+// SVD Line: 17908
+
+//  <item> SFDITEM_FIELD__UART0_IER_THREIE
+//    <name> THREIE </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40004004) Transmit Holding Register Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_IER ) </loc>
+//      <o.1..1> THREIE
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART0_IER_DRIE  -----------------------------------
+// SVD Line: 17914
+
+//  <item> SFDITEM_FIELD__UART0_IER_DRIE
+//    <name> DRIE </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004004) Data Receive Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_IER ) </loc>
+//      <o.0..0> DRIE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_IER  -----------------------------------
+// SVD Line: 17887
+
+//  <rtree> SFDITEM_REG__UART0_IER
+//    <name> IER </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004004) UARTn Interrupt Enable Register </i>
+//    <loc> ( (unsigned int)((UART0_IER >> 0) & 0xFFFFFFFF), ((UART0_IER = (UART0_IER & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART0_IER_TXEIE </item>
+//    <item> SFDITEM_FIELD__UART0_IER_RLSIE </item>
+//    <item> SFDITEM_FIELD__UART0_IER_THREIE </item>
+//    <item> SFDITEM_FIELD__UART0_IER_DRIE </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_IIR  --------------------------------
+// SVD Line: 17922
+
+unsigned int UART0_IIR __AT (0x40004008);
+
+
+
+// --------------------------------  Field Item: UART0_IIR_TXE  -----------------------------------
+// SVD Line: 17931
+
+//  <item> SFDITEM_FIELD__UART0_IIR_TXE
+//    <name> TXE </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x40004008) Transmit Complete Interrupt Source ID </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_IIR ) </loc>
+//      <o.4..4> TXE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART0_IIR_IID  -----------------------------------
+// SVD Line: 17937
+
+//  <item> SFDITEM_FIELD__UART0_IIR_IID
+//    <name> IID </name>
+//    <r> 
+//    <i> [Bits 2..1] RO (@ 0x40004008) UARTn Interrupt ID </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART0_IIR >> 1) & 0x3) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART0_IIR_IPEN  -----------------------------------
+// SVD Line: 17943
+
+//  <item> SFDITEM_FIELD__UART0_IIR_IPEN
+//    <name> IPEN </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x40004008) Interrupt Pending </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_IIR ) </loc>
+//      <o.0..0> IPEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_IIR  -----------------------------------
+// SVD Line: 17922
+
+//  <rtree> SFDITEM_REG__UART0_IIR
+//    <name> IIR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40004008) UARTn Interrupt ID Register </i>
+//    <loc> ( (unsigned int)((UART0_IIR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UART0_IIR_TXE </item>
+//    <item> SFDITEM_FIELD__UART0_IIR_IID </item>
+//    <item> SFDITEM_FIELD__UART0_IIR_IPEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_LCR  --------------------------------
+// SVD Line: 17951
+
+unsigned int UART0_LCR __AT (0x4000400C);
+
+
+
+// -------------------------------  Field Item: UART0_LCR_BREAK  ----------------------------------
+// SVD Line: 17960
+
+//  <item> SFDITEM_FIELD__UART0_LCR_BREAK
+//    <name> BREAK </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x4000400C) Transfer Break Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LCR ) </loc>
+//      <o.6..6> BREAK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UART0_LCR_STICKP  ----------------------------------
+// SVD Line: 17966
+
+//  <item> SFDITEM_FIELD__UART0_LCR_STICKP
+//    <name> STICKP </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x4000400C) Force Parity </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LCR ) </loc>
+//      <o.5..5> STICKP
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UART0_LCR_PARITY  ----------------------------------
+// SVD Line: 17972
+
+//  <item> SFDITEM_FIELD__UART0_LCR_PARITY
+//    <name> PARITY </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x4000400C) Parity Mode and Parity Stuck Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LCR ) </loc>
+//      <o.4..4> PARITY
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART0_LCR_PEN  -----------------------------------
+// SVD Line: 17978
+
+//  <item> SFDITEM_FIELD__UART0_LCR_PEN
+//    <name> PEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x4000400C) Parity Bit Transfer Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LCR ) </loc>
+//      <o.3..3> PEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UART0_LCR_STOPBIT  ---------------------------------
+// SVD Line: 17984
+
+//  <item> SFDITEM_FIELD__UART0_LCR_STOPBIT
+//    <name> STOPBIT </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x4000400C) Stop Bit Length Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LCR ) </loc>
+//      <o.2..2> STOPBIT
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART0_LCR_DLEN  -----------------------------------
+// SVD Line: 17990
+
+//  <item> SFDITEM_FIELD__UART0_LCR_DLEN
+//    <name> DLEN </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x4000400C) Data Length Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART0_LCR >> 0) & 0x3), ((UART0_LCR = (UART0_LCR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_LCR  -----------------------------------
+// SVD Line: 17951
+
+//  <rtree> SFDITEM_REG__UART0_LCR
+//    <name> LCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000400C) UARTn Line Control Register </i>
+//    <loc> ( (unsigned int)((UART0_LCR >> 0) & 0xFFFFFFFF), ((UART0_LCR = (UART0_LCR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART0_LCR_BREAK </item>
+//    <item> SFDITEM_FIELD__UART0_LCR_STICKP </item>
+//    <item> SFDITEM_FIELD__UART0_LCR_PARITY </item>
+//    <item> SFDITEM_FIELD__UART0_LCR_PEN </item>
+//    <item> SFDITEM_FIELD__UART0_LCR_STOPBIT </item>
+//    <item> SFDITEM_FIELD__UART0_LCR_DLEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_DCR  --------------------------------
+// SVD Line: 17998
+
+unsigned int UART0_DCR __AT (0x40004010);
+
+
+
+// -------------------------------  Field Item: UART0_DCR_LBON  -----------------------------------
+// SVD Line: 18007
+
+//  <item> SFDITEM_FIELD__UART0_DCR_LBON
+//    <name> LBON </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40004010) Local Loopback Test Mode Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_DCR ) </loc>
+//      <o.4..4> LBON
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART0_DCR_RXINV  ----------------------------------
+// SVD Line: 18013
+
+//  <item> SFDITEM_FIELD__UART0_DCR_RXINV
+//    <name> RXINV </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004010) Receive Data Inversion Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_DCR ) </loc>
+//      <o.3..3> RXINV
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART0_DCR_TXINV  ----------------------------------
+// SVD Line: 18019
+
+//  <item> SFDITEM_FIELD__UART0_DCR_TXINV
+//    <name> TXINV </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40004010) Transmit Data Inversion Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_DCR ) </loc>
+//      <o.2..2> TXINV
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_DCR  -----------------------------------
+// SVD Line: 17998
+
+//  <rtree> SFDITEM_REG__UART0_DCR
+//    <name> DCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004010) UARTn Data Control Register </i>
+//    <loc> ( (unsigned int)((UART0_DCR >> 0) & 0xFFFFFFFF), ((UART0_DCR = (UART0_DCR & ~(0x1CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1C) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART0_DCR_LBON </item>
+//    <item> SFDITEM_FIELD__UART0_DCR_RXINV </item>
+//    <item> SFDITEM_FIELD__UART0_DCR_TXINV </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_LSR  --------------------------------
+// SVD Line: 18027
+
+unsigned int UART0_LSR __AT (0x40004014);
+
+
+
+// -------------------------------  Field Item: UART0_LSR_TEMT  -----------------------------------
+// SVD Line: 18036
+
+//  <item> SFDITEM_FIELD__UART0_LSR_TEMT
+//    <name> TEMT </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x40004014) Transmit Register Empty </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LSR ) </loc>
+//      <o.6..6> TEMT
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART0_LSR_THRE  -----------------------------------
+// SVD Line: 18042
+
+//  <item> SFDITEM_FIELD__UART0_LSR_THRE
+//    <name> THRE </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x40004014) Transmit Hold Register Empty </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LSR ) </loc>
+//      <o.5..5> THRE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART0_LSR_BI  ------------------------------------
+// SVD Line: 18048
+
+//  <item> SFDITEM_FIELD__UART0_LSR_BI
+//    <name> BI </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x40004014) Break Condition Indication </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LSR ) </loc>
+//      <o.4..4> BI
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART0_LSR_FE  ------------------------------------
+// SVD Line: 18054
+
+//  <item> SFDITEM_FIELD__UART0_LSR_FE
+//    <name> FE </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x40004014) Frame Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LSR ) </loc>
+//      <o.3..3> FE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART0_LSR_PE  ------------------------------------
+// SVD Line: 18060
+
+//  <item> SFDITEM_FIELD__UART0_LSR_PE
+//    <name> PE </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x40004014) Parity Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LSR ) </loc>
+//      <o.2..2> PE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART0_LSR_OE  ------------------------------------
+// SVD Line: 18066
+
+//  <item> SFDITEM_FIELD__UART0_LSR_OE
+//    <name> OE </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x40004014) Overrun Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LSR ) </loc>
+//      <o.1..1> OE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART0_LSR_DR  ------------------------------------
+// SVD Line: 18072
+
+//  <item> SFDITEM_FIELD__UART0_LSR_DR
+//    <name> DR </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x40004014) Data Receive Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_LSR ) </loc>
+//      <o.0..0> DR
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_LSR  -----------------------------------
+// SVD Line: 18027
+
+//  <rtree> SFDITEM_REG__UART0_LSR
+//    <name> LSR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40004014) UARTn Line Status Register </i>
+//    <loc> ( (unsigned int)((UART0_LSR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UART0_LSR_TEMT </item>
+//    <item> SFDITEM_FIELD__UART0_LSR_THRE </item>
+//    <item> SFDITEM_FIELD__UART0_LSR_BI </item>
+//    <item> SFDITEM_FIELD__UART0_LSR_FE </item>
+//    <item> SFDITEM_FIELD__UART0_LSR_PE </item>
+//    <item> SFDITEM_FIELD__UART0_LSR_OE </item>
+//    <item> SFDITEM_FIELD__UART0_LSR_DR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_BDR  --------------------------------
+// SVD Line: 18080
+
+unsigned int UART0_BDR __AT (0x40004020);
+
+
+
+// --------------------------------  Field Item: UART0_BDR_BDR  -----------------------------------
+// SVD Line: 18089
+
+//  <item> SFDITEM_FIELD__UART0_BDR_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40004020) Baud Rate Divider Latch Value </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((UART0_BDR >> 0) & 0xFFFF), ((UART0_BDR = (UART0_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_BDR  -----------------------------------
+// SVD Line: 18080
+
+//  <rtree> SFDITEM_REG__UART0_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004020) UARTn Baud Rate Divisor Latch Register </i>
+//    <loc> ( (unsigned int)((UART0_BDR >> 0) & 0xFFFFFFFF), ((UART0_BDR = (UART0_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART0_BDR_BDR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_BFR  --------------------------------
+// SVD Line: 18097
+
+unsigned int UART0_BFR __AT (0x40004024);
+
+
+
+// --------------------------------  Field Item: UART0_BFR_BFR  -----------------------------------
+// SVD Line: 18106
+
+//  <item> SFDITEM_FIELD__UART0_BFR_BFR
+//    <name> BFR </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40004024) Fraction Counter value </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART0_BFR >> 0) & 0xFF), ((UART0_BFR = (UART0_BFR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART0_BFR  -----------------------------------
+// SVD Line: 18097
+
+//  <rtree> SFDITEM_REG__UART0_BFR
+//    <name> BFR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004024) UARTn Baud Rate Fractional Counter Value </i>
+//    <loc> ( (unsigned int)((UART0_BFR >> 0) & 0xFFFFFFFF), ((UART0_BFR = (UART0_BFR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART0_BFR_BFR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART0_IDTR  -------------------------------
+// SVD Line: 18121
+
+unsigned int UART0_IDTR __AT (0x40004030);
+
+
+
+// -------------------------------  Field Item: UART0_IDTR_SMS  -----------------------------------
+// SVD Line: 18130
+
+//  <item> SFDITEM_FIELD__UART0_IDTR_SMS
+//    <name> SMS </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40004030) Start Bit Multi Sampling Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_IDTR ) </loc>
+//      <o.7..7> SMS
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART0_IDTR_DMS  -----------------------------------
+// SVD Line: 18136
+
+//  <item> SFDITEM_FIELD__UART0_IDTR_DMS
+//    <name> DMS </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40004030) Data Bit Multi Sampling Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART0_IDTR ) </loc>
+//      <o.6..6> DMS
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: UART0_IDTR_WAITVAL  ---------------------------------
+// SVD Line: 18142
+
+//  <item> SFDITEM_FIELD__UART0_IDTR_WAITVAL
+//    <name> WAITVAL </name>
+//    <rw> 
+//    <i> [Bits 2..0] RW (@ 0x40004030) Wait Time Value </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART0_IDTR >> 0) & 0x7), ((UART0_IDTR = (UART0_IDTR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: UART0_IDTR  -----------------------------------
+// SVD Line: 18121
+
+//  <rtree> SFDITEM_REG__UART0_IDTR
+//    <name> IDTR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004030) UARTn Inter-frame Delay Time Register </i>
+//    <loc> ( (unsigned int)((UART0_IDTR >> 0) & 0xFFFFFFFF), ((UART0_IDTR = (UART0_IDTR & ~(0xC7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC7) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART0_IDTR_SMS </item>
+//    <item> SFDITEM_FIELD__UART0_IDTR_DMS </item>
+//    <item> SFDITEM_FIELD__UART0_IDTR_WAITVAL </item>
+//  </rtree>
+//  
+
+
+// ---------------------------------  Peripheral View: UART0  -------------------------------------
+// SVD Line: 18152
+
+//  <view> UART0
+//    <name> UART0 </name>
+//    <item> SFDITEM_REG__UART0_RBR </item>
+//    <item> SFDITEM_REG__UART0_THR </item>
+//    <item> SFDITEM_REG__UART0_IER </item>
+//    <item> SFDITEM_REG__UART0_IIR </item>
+//    <item> SFDITEM_REG__UART0_LCR </item>
+//    <item> SFDITEM_REG__UART0_DCR </item>
+//    <item> SFDITEM_REG__UART0_LSR </item>
+//    <item> SFDITEM_REG__UART0_BDR </item>
+//    <item> SFDITEM_REG__UART0_BFR </item>
+//    <item> SFDITEM_REG__UART0_IDTR </item>
+//  </view>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_RBR  --------------------------------
+// SVD Line: 17853
+
+unsigned int UART1_RBR __AT (0x40004100);
+
+
+
+// --------------------------------  Field Item: UART1_RBR_RBR  -----------------------------------
+// SVD Line: 17862
+
+//  <item> SFDITEM_FIELD__UART1_RBR_RBR
+//    <name> RBR </name>
+//    <r> 
+//    <i> [Bits 7..0] RO (@ 0x40004100) UARTn Receive Data Buffer </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART1_RBR >> 0) & 0xFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_RBR  -----------------------------------
+// SVD Line: 17853
+
+//  <rtree> SFDITEM_REG__UART1_RBR
+//    <name> RBR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40004100) UARTn Receive Data Buffer Register </i>
+//    <loc> ( (unsigned int)((UART1_RBR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UART1_RBR_RBR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_THR  --------------------------------
+// SVD Line: 17870
+
+unsigned int UART1_THR __AT (0x40004100);
+
+
+
+// --------------------------------  Field Item: UART1_THR_THR  -----------------------------------
+// SVD Line: 17879
+
+//  <item> SFDITEM_FIELD__UART1_THR_THR
+//    <name> THR </name>
+//    <w> 
+//    <i> [Bits 7..0] WO (@ 0x40004100) UARTn Transmit Data Hold </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART1_THR >> 0) & 0x0), ((UART1_THR = (UART1_THR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_THR  -----------------------------------
+// SVD Line: 17870
+
+//  <rtree> SFDITEM_REG__UART1_THR
+//    <name> THR </name>
+//    <w> 
+//    <i> [Bits 31..0] WO (@ 0x40004100) UARTn Transmit Data Hold Register </i>
+//    <loc> ( (unsigned int)((UART1_THR >> 0) & 0xFFFFFFFF), ((UART1_THR = (UART1_THR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART1_THR_THR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_IER  --------------------------------
+// SVD Line: 17887
+
+unsigned int UART1_IER __AT (0x40004104);
+
+
+
+// -------------------------------  Field Item: UART1_IER_TXEIE  ----------------------------------
+// SVD Line: 17896
+
+//  <item> SFDITEM_FIELD__UART1_IER_TXEIE
+//    <name> TXEIE </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004104) Transmit Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_IER ) </loc>
+//      <o.3..3> TXEIE
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART1_IER_RLSIE  ----------------------------------
+// SVD Line: 17902
+
+//  <item> SFDITEM_FIELD__UART1_IER_RLSIE
+//    <name> RLSIE </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40004104) Receiver Line Status Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_IER ) </loc>
+//      <o.2..2> RLSIE
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UART1_IER_THREIE  ----------------------------------
+// SVD Line: 17908
+
+//  <item> SFDITEM_FIELD__UART1_IER_THREIE
+//    <name> THREIE </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40004104) Transmit Holding Register Empty Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_IER ) </loc>
+//      <o.1..1> THREIE
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART1_IER_DRIE  -----------------------------------
+// SVD Line: 17914
+
+//  <item> SFDITEM_FIELD__UART1_IER_DRIE
+//    <name> DRIE </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004104) Data Receive Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_IER ) </loc>
+//      <o.0..0> DRIE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_IER  -----------------------------------
+// SVD Line: 17887
+
+//  <rtree> SFDITEM_REG__UART1_IER
+//    <name> IER </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004104) UARTn Interrupt Enable Register </i>
+//    <loc> ( (unsigned int)((UART1_IER >> 0) & 0xFFFFFFFF), ((UART1_IER = (UART1_IER & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART1_IER_TXEIE </item>
+//    <item> SFDITEM_FIELD__UART1_IER_RLSIE </item>
+//    <item> SFDITEM_FIELD__UART1_IER_THREIE </item>
+//    <item> SFDITEM_FIELD__UART1_IER_DRIE </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_IIR  --------------------------------
+// SVD Line: 17922
+
+unsigned int UART1_IIR __AT (0x40004108);
+
+
+
+// --------------------------------  Field Item: UART1_IIR_TXE  -----------------------------------
+// SVD Line: 17931
+
+//  <item> SFDITEM_FIELD__UART1_IIR_TXE
+//    <name> TXE </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x40004108) Transmit Complete Interrupt Source ID </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_IIR ) </loc>
+//      <o.4..4> TXE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART1_IIR_IID  -----------------------------------
+// SVD Line: 17937
+
+//  <item> SFDITEM_FIELD__UART1_IIR_IID
+//    <name> IID </name>
+//    <r> 
+//    <i> [Bits 2..1] RO (@ 0x40004108) UARTn Interrupt ID </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART1_IIR >> 1) & 0x3) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART1_IIR_IPEN  -----------------------------------
+// SVD Line: 17943
+
+//  <item> SFDITEM_FIELD__UART1_IIR_IPEN
+//    <name> IPEN </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x40004108) Interrupt Pending </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_IIR ) </loc>
+//      <o.0..0> IPEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_IIR  -----------------------------------
+// SVD Line: 17922
+
+//  <rtree> SFDITEM_REG__UART1_IIR
+//    <name> IIR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40004108) UARTn Interrupt ID Register </i>
+//    <loc> ( (unsigned int)((UART1_IIR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UART1_IIR_TXE </item>
+//    <item> SFDITEM_FIELD__UART1_IIR_IID </item>
+//    <item> SFDITEM_FIELD__UART1_IIR_IPEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_LCR  --------------------------------
+// SVD Line: 17951
+
+unsigned int UART1_LCR __AT (0x4000410C);
+
+
+
+// -------------------------------  Field Item: UART1_LCR_BREAK  ----------------------------------
+// SVD Line: 17960
+
+//  <item> SFDITEM_FIELD__UART1_LCR_BREAK
+//    <name> BREAK </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x4000410C) Transfer Break Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LCR ) </loc>
+//      <o.6..6> BREAK
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UART1_LCR_STICKP  ----------------------------------
+// SVD Line: 17966
+
+//  <item> SFDITEM_FIELD__UART1_LCR_STICKP
+//    <name> STICKP </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x4000410C) Force Parity </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LCR ) </loc>
+//      <o.5..5> STICKP
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UART1_LCR_PARITY  ----------------------------------
+// SVD Line: 17972
+
+//  <item> SFDITEM_FIELD__UART1_LCR_PARITY
+//    <name> PARITY </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x4000410C) Parity Mode and Parity Stuck Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LCR ) </loc>
+//      <o.4..4> PARITY
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART1_LCR_PEN  -----------------------------------
+// SVD Line: 17978
+
+//  <item> SFDITEM_FIELD__UART1_LCR_PEN
+//    <name> PEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x4000410C) Parity Bit Transfer Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LCR ) </loc>
+//      <o.3..3> PEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: UART1_LCR_STOPBIT  ---------------------------------
+// SVD Line: 17984
+
+//  <item> SFDITEM_FIELD__UART1_LCR_STOPBIT
+//    <name> STOPBIT </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x4000410C) Stop Bit Length Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LCR ) </loc>
+//      <o.2..2> STOPBIT
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART1_LCR_DLEN  -----------------------------------
+// SVD Line: 17990
+
+//  <item> SFDITEM_FIELD__UART1_LCR_DLEN
+//    <name> DLEN </name>
+//    <rw> 
+//    <i> [Bits 1..0] RW (@ 0x4000410C) Data Length Selection </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART1_LCR >> 0) & 0x3), ((UART1_LCR = (UART1_LCR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_LCR  -----------------------------------
+// SVD Line: 17951
+
+//  <rtree> SFDITEM_REG__UART1_LCR
+//    <name> LCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000410C) UARTn Line Control Register </i>
+//    <loc> ( (unsigned int)((UART1_LCR >> 0) & 0xFFFFFFFF), ((UART1_LCR = (UART1_LCR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART1_LCR_BREAK </item>
+//    <item> SFDITEM_FIELD__UART1_LCR_STICKP </item>
+//    <item> SFDITEM_FIELD__UART1_LCR_PARITY </item>
+//    <item> SFDITEM_FIELD__UART1_LCR_PEN </item>
+//    <item> SFDITEM_FIELD__UART1_LCR_STOPBIT </item>
+//    <item> SFDITEM_FIELD__UART1_LCR_DLEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_DCR  --------------------------------
+// SVD Line: 17998
+
+unsigned int UART1_DCR __AT (0x40004110);
+
+
+
+// -------------------------------  Field Item: UART1_DCR_LBON  -----------------------------------
+// SVD Line: 18007
+
+//  <item> SFDITEM_FIELD__UART1_DCR_LBON
+//    <name> LBON </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40004110) Local Loopback Test Mode Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_DCR ) </loc>
+//      <o.4..4> LBON
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART1_DCR_RXINV  ----------------------------------
+// SVD Line: 18013
+
+//  <item> SFDITEM_FIELD__UART1_DCR_RXINV
+//    <name> RXINV </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004110) Receive Data Inversion Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_DCR ) </loc>
+//      <o.3..3> RXINV
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART1_DCR_TXINV  ----------------------------------
+// SVD Line: 18019
+
+//  <item> SFDITEM_FIELD__UART1_DCR_TXINV
+//    <name> TXINV </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40004110) Transmit Data Inversion Selection </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_DCR ) </loc>
+//      <o.2..2> TXINV
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_DCR  -----------------------------------
+// SVD Line: 17998
+
+//  <rtree> SFDITEM_REG__UART1_DCR
+//    <name> DCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004110) UARTn Data Control Register </i>
+//    <loc> ( (unsigned int)((UART1_DCR >> 0) & 0xFFFFFFFF), ((UART1_DCR = (UART1_DCR & ~(0x1CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1C) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART1_DCR_LBON </item>
+//    <item> SFDITEM_FIELD__UART1_DCR_RXINV </item>
+//    <item> SFDITEM_FIELD__UART1_DCR_TXINV </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_LSR  --------------------------------
+// SVD Line: 18027
+
+unsigned int UART1_LSR __AT (0x40004114);
+
+
+
+// -------------------------------  Field Item: UART1_LSR_TEMT  -----------------------------------
+// SVD Line: 18036
+
+//  <item> SFDITEM_FIELD__UART1_LSR_TEMT
+//    <name> TEMT </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x40004114) Transmit Register Empty </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LSR ) </loc>
+//      <o.6..6> TEMT
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART1_LSR_THRE  -----------------------------------
+// SVD Line: 18042
+
+//  <item> SFDITEM_FIELD__UART1_LSR_THRE
+//    <name> THRE </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x40004114) Transmit Hold Register Empty </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LSR ) </loc>
+//      <o.5..5> THRE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART1_LSR_BI  ------------------------------------
+// SVD Line: 18048
+
+//  <item> SFDITEM_FIELD__UART1_LSR_BI
+//    <name> BI </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x40004114) Break Condition Indication </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LSR ) </loc>
+//      <o.4..4> BI
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART1_LSR_FE  ------------------------------------
+// SVD Line: 18054
+
+//  <item> SFDITEM_FIELD__UART1_LSR_FE
+//    <name> FE </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x40004114) Frame Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LSR ) </loc>
+//      <o.3..3> FE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART1_LSR_PE  ------------------------------------
+// SVD Line: 18060
+
+//  <item> SFDITEM_FIELD__UART1_LSR_PE
+//    <name> PE </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x40004114) Parity Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LSR ) </loc>
+//      <o.2..2> PE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART1_LSR_OE  ------------------------------------
+// SVD Line: 18066
+
+//  <item> SFDITEM_FIELD__UART1_LSR_OE
+//    <name> OE </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x40004114) Overrun Error Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LSR ) </loc>
+//      <o.1..1> OE
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: UART1_LSR_DR  ------------------------------------
+// SVD Line: 18072
+
+//  <item> SFDITEM_FIELD__UART1_LSR_DR
+//    <name> DR </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x40004114) Data Receive Indicator </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_LSR ) </loc>
+//      <o.0..0> DR
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_LSR  -----------------------------------
+// SVD Line: 18027
+
+//  <rtree> SFDITEM_REG__UART1_LSR
+//    <name> LSR </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x40004114) UARTn Line Status Register </i>
+//    <loc> ( (unsigned int)((UART1_LSR >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__UART1_LSR_TEMT </item>
+//    <item> SFDITEM_FIELD__UART1_LSR_THRE </item>
+//    <item> SFDITEM_FIELD__UART1_LSR_BI </item>
+//    <item> SFDITEM_FIELD__UART1_LSR_FE </item>
+//    <item> SFDITEM_FIELD__UART1_LSR_PE </item>
+//    <item> SFDITEM_FIELD__UART1_LSR_OE </item>
+//    <item> SFDITEM_FIELD__UART1_LSR_DR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_BDR  --------------------------------
+// SVD Line: 18080
+
+unsigned int UART1_BDR __AT (0x40004120);
+
+
+
+// --------------------------------  Field Item: UART1_BDR_BDR  -----------------------------------
+// SVD Line: 18089
+
+//  <item> SFDITEM_FIELD__UART1_BDR_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x40004120) Baud Rate Divider Latch Value </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((UART1_BDR >> 0) & 0xFFFF), ((UART1_BDR = (UART1_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_BDR  -----------------------------------
+// SVD Line: 18080
+
+//  <rtree> SFDITEM_REG__UART1_BDR
+//    <name> BDR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004120) UARTn Baud Rate Divisor Latch Register </i>
+//    <loc> ( (unsigned int)((UART1_BDR >> 0) & 0xFFFFFFFF), ((UART1_BDR = (UART1_BDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART1_BDR_BDR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_BFR  --------------------------------
+// SVD Line: 18097
+
+unsigned int UART1_BFR __AT (0x40004124);
+
+
+
+// --------------------------------  Field Item: UART1_BFR_BFR  -----------------------------------
+// SVD Line: 18106
+
+//  <item> SFDITEM_FIELD__UART1_BFR_BFR
+//    <name> BFR </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40004124) Fraction Counter value </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART1_BFR >> 0) & 0xFF), ((UART1_BFR = (UART1_BFR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: UART1_BFR  -----------------------------------
+// SVD Line: 18097
+
+//  <rtree> SFDITEM_REG__UART1_BFR
+//    <name> BFR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004124) UARTn Baud Rate Fractional Counter Value </i>
+//    <loc> ( (unsigned int)((UART1_BFR >> 0) & 0xFFFFFFFF), ((UART1_BFR = (UART1_BFR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART1_BFR_BFR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: UART1_IDTR  -------------------------------
+// SVD Line: 18121
+
+unsigned int UART1_IDTR __AT (0x40004130);
+
+
+
+// -------------------------------  Field Item: UART1_IDTR_SMS  -----------------------------------
+// SVD Line: 18130
+
+//  <item> SFDITEM_FIELD__UART1_IDTR_SMS
+//    <name> SMS </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40004130) Start Bit Multi Sampling Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_IDTR ) </loc>
+//      <o.7..7> SMS
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: UART1_IDTR_DMS  -----------------------------------
+// SVD Line: 18136
+
+//  <item> SFDITEM_FIELD__UART1_IDTR_DMS
+//    <name> DMS </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40004130) Data Bit Multi Sampling Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) UART1_IDTR ) </loc>
+//      <o.6..6> DMS
+//    </check>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: UART1_IDTR_WAITVAL  ---------------------------------
+// SVD Line: 18142
+
+//  <item> SFDITEM_FIELD__UART1_IDTR_WAITVAL
+//    <name> WAITVAL </name>
+//    <rw> 
+//    <i> [Bits 2..0] RW (@ 0x40004130) Wait Time Value </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((UART1_IDTR >> 0) & 0x7), ((UART1_IDTR = (UART1_IDTR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: UART1_IDTR  -----------------------------------
+// SVD Line: 18121
+
+//  <rtree> SFDITEM_REG__UART1_IDTR
+//    <name> IDTR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004130) UARTn Inter-frame Delay Time Register </i>
+//    <loc> ( (unsigned int)((UART1_IDTR >> 0) & 0xFFFFFFFF), ((UART1_IDTR = (UART1_IDTR & ~(0xC7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC7) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__UART1_IDTR_SMS </item>
+//    <item> SFDITEM_FIELD__UART1_IDTR_DMS </item>
+//    <item> SFDITEM_FIELD__UART1_IDTR_WAITVAL </item>
+//  </rtree>
+//  
+
+
+// ---------------------------------  Peripheral View: UART1  -------------------------------------
+// SVD Line: 18171
+
+//  <view> UART1
+//    <name> UART1 </name>
+//    <item> SFDITEM_REG__UART1_RBR </item>
+//    <item> SFDITEM_REG__UART1_THR </item>
+//    <item> SFDITEM_REG__UART1_IER </item>
+//    <item> SFDITEM_REG__UART1_IIR </item>
+//    <item> SFDITEM_REG__UART1_LCR </item>
+//    <item> SFDITEM_REG__UART1_DCR </item>
+//    <item> SFDITEM_REG__UART1_LSR </item>
+//    <item> SFDITEM_REG__UART1_BDR </item>
+//    <item> SFDITEM_REG__UART1_BFR </item>
+//    <item> SFDITEM_REG__UART1_IDTR </item>
+//  </view>
+//  
+
+
+// -----------------------------  Register Item Address: I2Cn_CR  ---------------------------------
+// SVD Line: 18204
+
+unsigned int I2Cn_CR __AT (0x56000000);
+
+
+
+// -------------------------------  Field Item: I2Cn_CR_I2CnEN  -----------------------------------
+// SVD Line: 18213
+
+//  <item> SFDITEM_FIELD__I2Cn_CR_I2CnEN
+//    <name> I2CnEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x56000000) Activate I2Cn Block by supplying </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_CR ) </loc>
+//      <o.7..7> I2CnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2Cn_CR_TXDLYENBn  ---------------------------------
+// SVD Line: 18219
+
+//  <item> SFDITEM_FIELD__I2Cn_CR_TXDLYENBn
+//    <name> TXDLYENBn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x56000000) SDHR Register Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_CR ) </loc>
+//      <o.6..6> TXDLYENBn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2Cn_CR_I2CnIEN  ----------------------------------
+// SVD Line: 18225
+
+//  <item> SFDITEM_FIELD__I2Cn_CR_I2CnIEN
+//    <name> I2CnIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x56000000) I2Cn Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_CR ) </loc>
+//      <o.5..5> I2CnIEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2Cn_CR_I2CnIFLAG  ---------------------------------
+// SVD Line: 18231
+
+//  <item> SFDITEM_FIELD__I2Cn_CR_I2CnIFLAG
+//    <name> I2CnIFLAG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x56000000) I2Cn Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_CR ) </loc>
+//      <o.4..4> I2CnIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2Cn_CR_ACKnEN  -----------------------------------
+// SVD Line: 18237
+
+//  <item> SFDITEM_FIELD__I2Cn_CR_ACKnEN
+//    <name> ACKnEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x56000000) Controls ACK signal generation at ninth SCL period </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_CR ) </loc>
+//      <o.3..3> ACKnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2Cn_CR_IMASTERn  ----------------------------------
+// SVD Line: 18243
+
+//  <item> SFDITEM_FIELD__I2Cn_CR_IMASTERn
+//    <name> IMASTERn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x56000000) Represent Operation Mode of I2Cn </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_CR ) </loc>
+//      <o.2..2> IMASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2Cn_CR_STOPCn  -----------------------------------
+// SVD Line: 18249
+
+//  <item> SFDITEM_FIELD__I2Cn_CR_STOPCn
+//    <name> STOPCn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x56000000) STOP Condition Generation when I2Cn is master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_CR ) </loc>
+//      <o.1..1> STOPCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2Cn_CR_STARTCn  ----------------------------------
+// SVD Line: 18255
+
+//  <item> SFDITEM_FIELD__I2Cn_CR_STARTCn
+//    <name> STARTCn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x56000000) START Condition Generation when I2Cn is master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_CR ) </loc>
+//      <o.0..0> STARTCn
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2Cn_CR  ------------------------------------
+// SVD Line: 18204
+
+//  <rtree> SFDITEM_REG__I2Cn_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x56000000) I2Cn Control Register </i>
+//    <loc> ( (unsigned int)((I2Cn_CR >> 0) & 0xFFFFFFFF), ((I2Cn_CR = (I2Cn_CR & ~(0xFBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2Cn_CR_I2CnEN </item>
+//    <item> SFDITEM_FIELD__I2Cn_CR_TXDLYENBn </item>
+//    <item> SFDITEM_FIELD__I2Cn_CR_I2CnIEN </item>
+//    <item> SFDITEM_FIELD__I2Cn_CR_I2CnIFLAG </item>
+//    <item> SFDITEM_FIELD__I2Cn_CR_ACKnEN </item>
+//    <item> SFDITEM_FIELD__I2Cn_CR_IMASTERn </item>
+//    <item> SFDITEM_FIELD__I2Cn_CR_STOPCn </item>
+//    <item> SFDITEM_FIELD__I2Cn_CR_STARTCn </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: I2Cn_ST  ---------------------------------
+// SVD Line: 18263
+
+unsigned int I2Cn_ST __AT (0x56000004);
+
+
+
+// -------------------------------  Field Item: I2Cn_ST_GCALLn  -----------------------------------
+// SVD Line: 18272
+
+//  <item> SFDITEM_FIELD__I2Cn_ST_GCALLn
+//    <name> GCALLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x56000004) This bit has different meaning depending on whether I2C is master or slave.  When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.  When I2C is a slave, this bit is used to indicate general call. </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_ST ) </loc>
+//      <o.7..7> GCALLn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2Cn_ST_TENDn  -----------------------------------
+// SVD Line: 18282
+
+//  <item> SFDITEM_FIELD__I2Cn_ST_TENDn
+//    <name> TENDn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x56000004) This bit is set when 1-byte of data is transferred completely </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_ST ) </loc>
+//      <o.6..6> TENDn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2Cn_ST_STOPDn  -----------------------------------
+// SVD Line: 18288
+
+//  <item> SFDITEM_FIELD__I2Cn_ST_STOPDn
+//    <name> STOPDn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x56000004) This bit is set when a STOP condition is detected </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_ST ) </loc>
+//      <o.5..5> STOPDn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2Cn_ST_SSELn  -----------------------------------
+// SVD Line: 18294
+
+//  <item> SFDITEM_FIELD__I2Cn_ST_SSELn
+//    <name> SSELn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x56000004) This bit is set when I2C is addressed by other master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_ST ) </loc>
+//      <o.4..4> SSELn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2Cn_ST_MLOSTn  -----------------------------------
+// SVD Line: 18300
+
+//  <item> SFDITEM_FIELD__I2Cn_ST_MLOSTn
+//    <name> MLOSTn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x56000004) This bit represents the result of bus arbitration in master mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_ST ) </loc>
+//      <o.3..3> MLOSTn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2Cn_ST_BUSYn  -----------------------------------
+// SVD Line: 18306
+
+//  <item> SFDITEM_FIELD__I2Cn_ST_BUSYn
+//    <name> BUSYn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x56000004) This bit reflects bus status </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_ST ) </loc>
+//      <o.2..2> BUSYn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2Cn_ST_TMODEn  -----------------------------------
+// SVD Line: 18312
+
+//  <item> SFDITEM_FIELD__I2Cn_ST_TMODEn
+//    <name> TMODEn </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x56000004) This bit is used to indicate whether I2C is transmitter or receiver </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_ST ) </loc>
+//      <o.1..1> TMODEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2Cn_ST_RXACKn  -----------------------------------
+// SVD Line: 18318
+
+//  <item> SFDITEM_FIELD__I2Cn_ST_RXACKn
+//    <name> RXACKn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x56000004) This bit shows the state of ACK signal </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_ST ) </loc>
+//      <o.0..0> RXACKn
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2Cn_ST  ------------------------------------
+// SVD Line: 18263
+
+//  <rtree> SFDITEM_REG__I2Cn_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x56000004) I2Cn Status Register </i>
+//    <loc> ( (unsigned int)((I2Cn_ST >> 0) & 0xFFFFFFFF), ((I2Cn_ST = (I2Cn_ST & ~(0xFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFD) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2Cn_ST_GCALLn </item>
+//    <item> SFDITEM_FIELD__I2Cn_ST_TENDn </item>
+//    <item> SFDITEM_FIELD__I2Cn_ST_STOPDn </item>
+//    <item> SFDITEM_FIELD__I2Cn_ST_SSELn </item>
+//    <item> SFDITEM_FIELD__I2Cn_ST_MLOSTn </item>
+//    <item> SFDITEM_FIELD__I2Cn_ST_BUSYn </item>
+//    <item> SFDITEM_FIELD__I2Cn_ST_TMODEn </item>
+//    <item> SFDITEM_FIELD__I2Cn_ST_RXACKn </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2Cn_SAR1  --------------------------------
+// SVD Line: 18326
+
+unsigned int I2Cn_SAR1 __AT (0x56000008);
+
+
+
+// -------------------------------  Field Item: I2Cn_SAR1_SLAn  -----------------------------------
+// SVD Line: 18335
+
+//  <item> SFDITEM_FIELD__I2Cn_SAR1_SLAn
+//    <name> SLAn </name>
+//    <rw> 
+//    <i> [Bits 7..1] RW (@ 0x56000008) These bits configure the slave address 1 in slave mode </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2Cn_SAR1 >> 1) & 0x7F), ((I2Cn_SAR1 = (I2Cn_SAR1 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: I2Cn_SAR1_GCALLnEN  ---------------------------------
+// SVD Line: 18341
+
+//  <item> SFDITEM_FIELD__I2Cn_SAR1_GCALLnEN
+//    <name> GCALLnEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x56000008) This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_SAR1 ) </loc>
+//      <o.0..0> GCALLnEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2Cn_SAR1  -----------------------------------
+// SVD Line: 18326
+
+//  <rtree> SFDITEM_REG__I2Cn_SAR1
+//    <name> SAR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x56000008) I2Cn Slave Address Register 1 </i>
+//    <loc> ( (unsigned int)((I2Cn_SAR1 >> 0) & 0xFFFFFFFF), ((I2Cn_SAR1 = (I2Cn_SAR1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2Cn_SAR1_SLAn </item>
+//    <item> SFDITEM_FIELD__I2Cn_SAR1_GCALLnEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2Cn_SAR2  --------------------------------
+// SVD Line: 18349
+
+unsigned int I2Cn_SAR2 __AT (0x5600000C);
+
+
+
+// -------------------------------  Field Item: I2Cn_SAR2_SLAn  -----------------------------------
+// SVD Line: 18358
+
+//  <item> SFDITEM_FIELD__I2Cn_SAR2_SLAn
+//    <name> SLAn </name>
+//    <rw> 
+//    <i> [Bits 7..1] RW (@ 0x5600000C) These bits configure the slave address 2 in slave mode </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2Cn_SAR2 >> 1) & 0x7F), ((I2Cn_SAR2 = (I2Cn_SAR2 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: I2Cn_SAR2_GCALLnEN  ---------------------------------
+// SVD Line: 18364
+
+//  <item> SFDITEM_FIELD__I2Cn_SAR2_GCALLnEN
+//    <name> GCALLnEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x5600000C) This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2Cn_SAR2 ) </loc>
+//      <o.0..0> GCALLnEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2Cn_SAR2  -----------------------------------
+// SVD Line: 18349
+
+//  <rtree> SFDITEM_REG__I2Cn_SAR2
+//    <name> SAR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x5600000C) I2Cn Slave Address Register 2 </i>
+//    <loc> ( (unsigned int)((I2Cn_SAR2 >> 0) & 0xFFFFFFFF), ((I2Cn_SAR2 = (I2Cn_SAR2 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2Cn_SAR2_SLAn </item>
+//    <item> SFDITEM_FIELD__I2Cn_SAR2_GCALLnEN </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: I2Cn_DR  ---------------------------------
+// SVD Line: 18372
+
+unsigned int I2Cn_DR __AT (0x56000010);
+
+
+
+// --------------------------------  Field Item: I2Cn_DR_DATA  ------------------------------------
+// SVD Line: 18381
+
+//  <item> SFDITEM_FIELD__I2Cn_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x56000010) The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2Cn_DR >> 0) & 0xFF), ((I2Cn_DR = (I2Cn_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2Cn_DR  ------------------------------------
+// SVD Line: 18372
+
+//  <rtree> SFDITEM_REG__I2Cn_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x56000010) I2Cn Data Register </i>
+//    <loc> ( (unsigned int)((I2Cn_DR >> 0) & 0xFFFFFFFF), ((I2Cn_DR = (I2Cn_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2Cn_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2Cn_SDHR  --------------------------------
+// SVD Line: 18389
+
+unsigned int I2Cn_SDHR __AT (0x56000014);
+
+
+
+// -------------------------------  Field Item: I2Cn_SDHR_HLDT  -----------------------------------
+// SVD Line: 18398
+
+//  <item> SFDITEM_FIELD__I2Cn_SDHR_HLDT
+//    <name> HLDT </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x56000014) This register is used to control SDA output timing from the falling edge of SCL </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2Cn_SDHR >> 0) & 0xFFF), ((I2Cn_SDHR = (I2Cn_SDHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2Cn_SDHR  -----------------------------------
+// SVD Line: 18389
+
+//  <rtree> SFDITEM_REG__I2Cn_SDHR
+//    <name> SDHR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x56000014) I2Cn SDA Hold Time Register </i>
+//    <loc> ( (unsigned int)((I2Cn_SDHR >> 0) & 0xFFFFFFFF), ((I2Cn_SDHR = (I2Cn_SDHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2Cn_SDHR_HLDT </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2Cn_SCLR  --------------------------------
+// SVD Line: 18406
+
+unsigned int I2Cn_SCLR __AT (0x56000018);
+
+
+
+// -------------------------------  Field Item: I2Cn_SCLR_SCLL  -----------------------------------
+// SVD Line: 18415
+
+//  <item> SFDITEM_FIELD__I2Cn_SCLR_SCLL
+//    <name> SCLL </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x56000018) This register defines the low period of SCL in master mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2Cn_SCLR >> 0) & 0xFFF), ((I2Cn_SCLR = (I2Cn_SCLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2Cn_SCLR  -----------------------------------
+// SVD Line: 18406
+
+//  <rtree> SFDITEM_REG__I2Cn_SCLR
+//    <name> SCLR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x56000018) I2Cn SCL Low Period Register </i>
+//    <loc> ( (unsigned int)((I2Cn_SCLR >> 0) & 0xFFFFFFFF), ((I2Cn_SCLR = (I2Cn_SCLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2Cn_SCLR_SCLL </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2Cn_SCHR  --------------------------------
+// SVD Line: 18423
+
+unsigned int I2Cn_SCHR __AT (0x5600001C);
+
+
+
+// -------------------------------  Field Item: I2Cn_SCHR_SCLH  -----------------------------------
+// SVD Line: 18432
+
+//  <item> SFDITEM_FIELD__I2Cn_SCHR_SCLH
+//    <name> SCLH </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x5600001C) This register defines the high period of SCL in master mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2Cn_SCHR >> 0) & 0xFFF), ((I2Cn_SCHR = (I2Cn_SCHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2Cn_SCHR  -----------------------------------
+// SVD Line: 18423
+
+//  <rtree> SFDITEM_REG__I2Cn_SCHR
+//    <name> SCHR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x5600001C) I2Cn SCL High Period Register </i>
+//    <loc> ( (unsigned int)((I2Cn_SCHR >> 0) & 0xFFFFFFFF), ((I2Cn_SCHR = (I2Cn_SCHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2Cn_SCHR_SCLH </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: I2Cn  -------------------------------------
+// SVD Line: 18190
+
+//  <view> I2Cn
+//    <name> I2Cn </name>
+//    <item> SFDITEM_REG__I2Cn_CR </item>
+//    <item> SFDITEM_REG__I2Cn_ST </item>
+//    <item> SFDITEM_REG__I2Cn_SAR1 </item>
+//    <item> SFDITEM_REG__I2Cn_SAR2 </item>
+//    <item> SFDITEM_REG__I2Cn_DR </item>
+//    <item> SFDITEM_REG__I2Cn_SDHR </item>
+//    <item> SFDITEM_REG__I2Cn_SCLR </item>
+//    <item> SFDITEM_REG__I2Cn_SCHR </item>
+//  </view>
+//  
+
+
+// -----------------------------  Register Item Address: I2C0_CR  ---------------------------------
+// SVD Line: 18204
+
+unsigned int I2C0_CR __AT (0x40004800);
+
+
+
+// -------------------------------  Field Item: I2C0_CR_I2CnEN  -----------------------------------
+// SVD Line: 18213
+
+//  <item> SFDITEM_FIELD__I2C0_CR_I2CnEN
+//    <name> I2CnEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40004800) Activate I2Cn Block by supplying </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_CR ) </loc>
+//      <o.7..7> I2CnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C0_CR_TXDLYENBn  ---------------------------------
+// SVD Line: 18219
+
+//  <item> SFDITEM_FIELD__I2C0_CR_TXDLYENBn
+//    <name> TXDLYENBn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40004800) SDHR Register Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_CR ) </loc>
+//      <o.6..6> TXDLYENBn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C0_CR_I2CnIEN  ----------------------------------
+// SVD Line: 18225
+
+//  <item> SFDITEM_FIELD__I2C0_CR_I2CnIEN
+//    <name> I2CnIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40004800) I2Cn Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_CR ) </loc>
+//      <o.5..5> I2CnIEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C0_CR_I2CnIFLAG  ---------------------------------
+// SVD Line: 18231
+
+//  <item> SFDITEM_FIELD__I2C0_CR_I2CnIFLAG
+//    <name> I2CnIFLAG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40004800) I2Cn Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_CR ) </loc>
+//      <o.4..4> I2CnIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C0_CR_ACKnEN  -----------------------------------
+// SVD Line: 18237
+
+//  <item> SFDITEM_FIELD__I2C0_CR_ACKnEN
+//    <name> ACKnEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004800) Controls ACK signal generation at ninth SCL period </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_CR ) </loc>
+//      <o.3..3> ACKnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C0_CR_IMASTERn  ----------------------------------
+// SVD Line: 18243
+
+//  <item> SFDITEM_FIELD__I2C0_CR_IMASTERn
+//    <name> IMASTERn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x40004800) Represent Operation Mode of I2Cn </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_CR ) </loc>
+//      <o.2..2> IMASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C0_CR_STOPCn  -----------------------------------
+// SVD Line: 18249
+
+//  <item> SFDITEM_FIELD__I2C0_CR_STOPCn
+//    <name> STOPCn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40004800) STOP Condition Generation when I2Cn is master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_CR ) </loc>
+//      <o.1..1> STOPCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C0_CR_STARTCn  ----------------------------------
+// SVD Line: 18255
+
+//  <item> SFDITEM_FIELD__I2C0_CR_STARTCn
+//    <name> STARTCn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004800) START Condition Generation when I2Cn is master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_CR ) </loc>
+//      <o.0..0> STARTCn
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C0_CR  ------------------------------------
+// SVD Line: 18204
+
+//  <rtree> SFDITEM_REG__I2C0_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004800) I2Cn Control Register </i>
+//    <loc> ( (unsigned int)((I2C0_CR >> 0) & 0xFFFFFFFF), ((I2C0_CR = (I2C0_CR & ~(0xFBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C0_CR_I2CnEN </item>
+//    <item> SFDITEM_FIELD__I2C0_CR_TXDLYENBn </item>
+//    <item> SFDITEM_FIELD__I2C0_CR_I2CnIEN </item>
+//    <item> SFDITEM_FIELD__I2C0_CR_I2CnIFLAG </item>
+//    <item> SFDITEM_FIELD__I2C0_CR_ACKnEN </item>
+//    <item> SFDITEM_FIELD__I2C0_CR_IMASTERn </item>
+//    <item> SFDITEM_FIELD__I2C0_CR_STOPCn </item>
+//    <item> SFDITEM_FIELD__I2C0_CR_STARTCn </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: I2C0_ST  ---------------------------------
+// SVD Line: 18263
+
+unsigned int I2C0_ST __AT (0x40004804);
+
+
+
+// -------------------------------  Field Item: I2C0_ST_GCALLn  -----------------------------------
+// SVD Line: 18272
+
+//  <item> SFDITEM_FIELD__I2C0_ST_GCALLn
+//    <name> GCALLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40004804) This bit has different meaning depending on whether I2C is master or slave.  When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.  When I2C is a slave, this bit is used to indicate general call. </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_ST ) </loc>
+//      <o.7..7> GCALLn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C0_ST_TENDn  -----------------------------------
+// SVD Line: 18282
+
+//  <item> SFDITEM_FIELD__I2C0_ST_TENDn
+//    <name> TENDn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40004804) This bit is set when 1-byte of data is transferred completely </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_ST ) </loc>
+//      <o.6..6> TENDn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C0_ST_STOPDn  -----------------------------------
+// SVD Line: 18288
+
+//  <item> SFDITEM_FIELD__I2C0_ST_STOPDn
+//    <name> STOPDn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40004804) This bit is set when a STOP condition is detected </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_ST ) </loc>
+//      <o.5..5> STOPDn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C0_ST_SSELn  -----------------------------------
+// SVD Line: 18294
+
+//  <item> SFDITEM_FIELD__I2C0_ST_SSELn
+//    <name> SSELn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40004804) This bit is set when I2C is addressed by other master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_ST ) </loc>
+//      <o.4..4> SSELn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C0_ST_MLOSTn  -----------------------------------
+// SVD Line: 18300
+
+//  <item> SFDITEM_FIELD__I2C0_ST_MLOSTn
+//    <name> MLOSTn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004804) This bit represents the result of bus arbitration in master mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_ST ) </loc>
+//      <o.3..3> MLOSTn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C0_ST_BUSYn  -----------------------------------
+// SVD Line: 18306
+
+//  <item> SFDITEM_FIELD__I2C0_ST_BUSYn
+//    <name> BUSYn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40004804) This bit reflects bus status </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_ST ) </loc>
+//      <o.2..2> BUSYn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C0_ST_TMODEn  -----------------------------------
+// SVD Line: 18312
+
+//  <item> SFDITEM_FIELD__I2C0_ST_TMODEn
+//    <name> TMODEn </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x40004804) This bit is used to indicate whether I2C is transmitter or receiver </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_ST ) </loc>
+//      <o.1..1> TMODEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C0_ST_RXACKn  -----------------------------------
+// SVD Line: 18318
+
+//  <item> SFDITEM_FIELD__I2C0_ST_RXACKn
+//    <name> RXACKn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004804) This bit shows the state of ACK signal </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_ST ) </loc>
+//      <o.0..0> RXACKn
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C0_ST  ------------------------------------
+// SVD Line: 18263
+
+//  <rtree> SFDITEM_REG__I2C0_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004804) I2Cn Status Register </i>
+//    <loc> ( (unsigned int)((I2C0_ST >> 0) & 0xFFFFFFFF), ((I2C0_ST = (I2C0_ST & ~(0xFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFD) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C0_ST_GCALLn </item>
+//    <item> SFDITEM_FIELD__I2C0_ST_TENDn </item>
+//    <item> SFDITEM_FIELD__I2C0_ST_STOPDn </item>
+//    <item> SFDITEM_FIELD__I2C0_ST_SSELn </item>
+//    <item> SFDITEM_FIELD__I2C0_ST_MLOSTn </item>
+//    <item> SFDITEM_FIELD__I2C0_ST_BUSYn </item>
+//    <item> SFDITEM_FIELD__I2C0_ST_TMODEn </item>
+//    <item> SFDITEM_FIELD__I2C0_ST_RXACKn </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C0_SAR1  --------------------------------
+// SVD Line: 18326
+
+unsigned int I2C0_SAR1 __AT (0x40004808);
+
+
+
+// -------------------------------  Field Item: I2C0_SAR1_SLAn  -----------------------------------
+// SVD Line: 18335
+
+//  <item> SFDITEM_FIELD__I2C0_SAR1_SLAn
+//    <name> SLAn </name>
+//    <rw> 
+//    <i> [Bits 7..1] RW (@ 0x40004808) These bits configure the slave address 1 in slave mode </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C0_SAR1 >> 1) & 0x7F), ((I2C0_SAR1 = (I2C0_SAR1 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: I2C0_SAR1_GCALLnEN  ---------------------------------
+// SVD Line: 18341
+
+//  <item> SFDITEM_FIELD__I2C0_SAR1_GCALLnEN
+//    <name> GCALLnEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004808) This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_SAR1 ) </loc>
+//      <o.0..0> GCALLnEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C0_SAR1  -----------------------------------
+// SVD Line: 18326
+
+//  <rtree> SFDITEM_REG__I2C0_SAR1
+//    <name> SAR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004808) I2Cn Slave Address Register 1 </i>
+//    <loc> ( (unsigned int)((I2C0_SAR1 >> 0) & 0xFFFFFFFF), ((I2C0_SAR1 = (I2C0_SAR1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C0_SAR1_SLAn </item>
+//    <item> SFDITEM_FIELD__I2C0_SAR1_GCALLnEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C0_SAR2  --------------------------------
+// SVD Line: 18349
+
+unsigned int I2C0_SAR2 __AT (0x4000480C);
+
+
+
+// -------------------------------  Field Item: I2C0_SAR2_SLAn  -----------------------------------
+// SVD Line: 18358
+
+//  <item> SFDITEM_FIELD__I2C0_SAR2_SLAn
+//    <name> SLAn </name>
+//    <rw> 
+//    <i> [Bits 7..1] RW (@ 0x4000480C) These bits configure the slave address 2 in slave mode </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C0_SAR2 >> 1) & 0x7F), ((I2C0_SAR2 = (I2C0_SAR2 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: I2C0_SAR2_GCALLnEN  ---------------------------------
+// SVD Line: 18364
+
+//  <item> SFDITEM_FIELD__I2C0_SAR2_GCALLnEN
+//    <name> GCALLnEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x4000480C) This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C0_SAR2 ) </loc>
+//      <o.0..0> GCALLnEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C0_SAR2  -----------------------------------
+// SVD Line: 18349
+
+//  <rtree> SFDITEM_REG__I2C0_SAR2
+//    <name> SAR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000480C) I2Cn Slave Address Register 2 </i>
+//    <loc> ( (unsigned int)((I2C0_SAR2 >> 0) & 0xFFFFFFFF), ((I2C0_SAR2 = (I2C0_SAR2 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C0_SAR2_SLAn </item>
+//    <item> SFDITEM_FIELD__I2C0_SAR2_GCALLnEN </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: I2C0_DR  ---------------------------------
+// SVD Line: 18372
+
+unsigned int I2C0_DR __AT (0x40004810);
+
+
+
+// --------------------------------  Field Item: I2C0_DR_DATA  ------------------------------------
+// SVD Line: 18381
+
+//  <item> SFDITEM_FIELD__I2C0_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40004810) The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C0_DR >> 0) & 0xFF), ((I2C0_DR = (I2C0_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C0_DR  ------------------------------------
+// SVD Line: 18372
+
+//  <rtree> SFDITEM_REG__I2C0_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004810) I2Cn Data Register </i>
+//    <loc> ( (unsigned int)((I2C0_DR >> 0) & 0xFFFFFFFF), ((I2C0_DR = (I2C0_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C0_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C0_SDHR  --------------------------------
+// SVD Line: 18389
+
+unsigned int I2C0_SDHR __AT (0x40004814);
+
+
+
+// -------------------------------  Field Item: I2C0_SDHR_HLDT  -----------------------------------
+// SVD Line: 18398
+
+//  <item> SFDITEM_FIELD__I2C0_SDHR_HLDT
+//    <name> HLDT </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40004814) This register is used to control SDA output timing from the falling edge of SCL </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C0_SDHR >> 0) & 0xFFF), ((I2C0_SDHR = (I2C0_SDHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C0_SDHR  -----------------------------------
+// SVD Line: 18389
+
+//  <rtree> SFDITEM_REG__I2C0_SDHR
+//    <name> SDHR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004814) I2Cn SDA Hold Time Register </i>
+//    <loc> ( (unsigned int)((I2C0_SDHR >> 0) & 0xFFFFFFFF), ((I2C0_SDHR = (I2C0_SDHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C0_SDHR_HLDT </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C0_SCLR  --------------------------------
+// SVD Line: 18406
+
+unsigned int I2C0_SCLR __AT (0x40004818);
+
+
+
+// -------------------------------  Field Item: I2C0_SCLR_SCLL  -----------------------------------
+// SVD Line: 18415
+
+//  <item> SFDITEM_FIELD__I2C0_SCLR_SCLL
+//    <name> SCLL </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40004818) This register defines the low period of SCL in master mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C0_SCLR >> 0) & 0xFFF), ((I2C0_SCLR = (I2C0_SCLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C0_SCLR  -----------------------------------
+// SVD Line: 18406
+
+//  <rtree> SFDITEM_REG__I2C0_SCLR
+//    <name> SCLR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004818) I2Cn SCL Low Period Register </i>
+//    <loc> ( (unsigned int)((I2C0_SCLR >> 0) & 0xFFFFFFFF), ((I2C0_SCLR = (I2C0_SCLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C0_SCLR_SCLL </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C0_SCHR  --------------------------------
+// SVD Line: 18423
+
+unsigned int I2C0_SCHR __AT (0x4000481C);
+
+
+
+// -------------------------------  Field Item: I2C0_SCHR_SCLH  -----------------------------------
+// SVD Line: 18432
+
+//  <item> SFDITEM_FIELD__I2C0_SCHR_SCLH
+//    <name> SCLH </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x4000481C) This register defines the high period of SCL in master mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C0_SCHR >> 0) & 0xFFF), ((I2C0_SCHR = (I2C0_SCHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C0_SCHR  -----------------------------------
+// SVD Line: 18423
+
+//  <rtree> SFDITEM_REG__I2C0_SCHR
+//    <name> SCHR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000481C) I2Cn SCL High Period Register </i>
+//    <loc> ( (unsigned int)((I2C0_SCHR >> 0) & 0xFFFFFFFF), ((I2C0_SCHR = (I2C0_SCHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C0_SCHR_SCLH </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: I2C0  -------------------------------------
+// SVD Line: 18442
+
+//  <view> I2C0
+//    <name> I2C0 </name>
+//    <item> SFDITEM_REG__I2C0_CR </item>
+//    <item> SFDITEM_REG__I2C0_ST </item>
+//    <item> SFDITEM_REG__I2C0_SAR1 </item>
+//    <item> SFDITEM_REG__I2C0_SAR2 </item>
+//    <item> SFDITEM_REG__I2C0_DR </item>
+//    <item> SFDITEM_REG__I2C0_SDHR </item>
+//    <item> SFDITEM_REG__I2C0_SCLR </item>
+//    <item> SFDITEM_REG__I2C0_SCHR </item>
+//  </view>
+//  
+
+
+// -----------------------------  Register Item Address: I2C1_CR  ---------------------------------
+// SVD Line: 18204
+
+unsigned int I2C1_CR __AT (0x40004900);
+
+
+
+// -------------------------------  Field Item: I2C1_CR_I2CnEN  -----------------------------------
+// SVD Line: 18213
+
+//  <item> SFDITEM_FIELD__I2C1_CR_I2CnEN
+//    <name> I2CnEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40004900) Activate I2Cn Block by supplying </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_CR ) </loc>
+//      <o.7..7> I2CnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C1_CR_TXDLYENBn  ---------------------------------
+// SVD Line: 18219
+
+//  <item> SFDITEM_FIELD__I2C1_CR_TXDLYENBn
+//    <name> TXDLYENBn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40004900) SDHR Register Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_CR ) </loc>
+//      <o.6..6> TXDLYENBn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C1_CR_I2CnIEN  ----------------------------------
+// SVD Line: 18225
+
+//  <item> SFDITEM_FIELD__I2C1_CR_I2CnIEN
+//    <name> I2CnIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40004900) I2Cn Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_CR ) </loc>
+//      <o.5..5> I2CnIEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C1_CR_I2CnIFLAG  ---------------------------------
+// SVD Line: 18231
+
+//  <item> SFDITEM_FIELD__I2C1_CR_I2CnIFLAG
+//    <name> I2CnIFLAG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40004900) I2Cn Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_CR ) </loc>
+//      <o.4..4> I2CnIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C1_CR_ACKnEN  -----------------------------------
+// SVD Line: 18237
+
+//  <item> SFDITEM_FIELD__I2C1_CR_ACKnEN
+//    <name> ACKnEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004900) Controls ACK signal generation at ninth SCL period </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_CR ) </loc>
+//      <o.3..3> ACKnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C1_CR_IMASTERn  ----------------------------------
+// SVD Line: 18243
+
+//  <item> SFDITEM_FIELD__I2C1_CR_IMASTERn
+//    <name> IMASTERn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x40004900) Represent Operation Mode of I2Cn </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_CR ) </loc>
+//      <o.2..2> IMASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C1_CR_STOPCn  -----------------------------------
+// SVD Line: 18249
+
+//  <item> SFDITEM_FIELD__I2C1_CR_STOPCn
+//    <name> STOPCn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40004900) STOP Condition Generation when I2Cn is master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_CR ) </loc>
+//      <o.1..1> STOPCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C1_CR_STARTCn  ----------------------------------
+// SVD Line: 18255
+
+//  <item> SFDITEM_FIELD__I2C1_CR_STARTCn
+//    <name> STARTCn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004900) START Condition Generation when I2Cn is master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_CR ) </loc>
+//      <o.0..0> STARTCn
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C1_CR  ------------------------------------
+// SVD Line: 18204
+
+//  <rtree> SFDITEM_REG__I2C1_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004900) I2Cn Control Register </i>
+//    <loc> ( (unsigned int)((I2C1_CR >> 0) & 0xFFFFFFFF), ((I2C1_CR = (I2C1_CR & ~(0xFBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C1_CR_I2CnEN </item>
+//    <item> SFDITEM_FIELD__I2C1_CR_TXDLYENBn </item>
+//    <item> SFDITEM_FIELD__I2C1_CR_I2CnIEN </item>
+//    <item> SFDITEM_FIELD__I2C1_CR_I2CnIFLAG </item>
+//    <item> SFDITEM_FIELD__I2C1_CR_ACKnEN </item>
+//    <item> SFDITEM_FIELD__I2C1_CR_IMASTERn </item>
+//    <item> SFDITEM_FIELD__I2C1_CR_STOPCn </item>
+//    <item> SFDITEM_FIELD__I2C1_CR_STARTCn </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: I2C1_ST  ---------------------------------
+// SVD Line: 18263
+
+unsigned int I2C1_ST __AT (0x40004904);
+
+
+
+// -------------------------------  Field Item: I2C1_ST_GCALLn  -----------------------------------
+// SVD Line: 18272
+
+//  <item> SFDITEM_FIELD__I2C1_ST_GCALLn
+//    <name> GCALLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40004904) This bit has different meaning depending on whether I2C is master or slave.  When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.  When I2C is a slave, this bit is used to indicate general call. </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_ST ) </loc>
+//      <o.7..7> GCALLn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C1_ST_TENDn  -----------------------------------
+// SVD Line: 18282
+
+//  <item> SFDITEM_FIELD__I2C1_ST_TENDn
+//    <name> TENDn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40004904) This bit is set when 1-byte of data is transferred completely </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_ST ) </loc>
+//      <o.6..6> TENDn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C1_ST_STOPDn  -----------------------------------
+// SVD Line: 18288
+
+//  <item> SFDITEM_FIELD__I2C1_ST_STOPDn
+//    <name> STOPDn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40004904) This bit is set when a STOP condition is detected </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_ST ) </loc>
+//      <o.5..5> STOPDn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C1_ST_SSELn  -----------------------------------
+// SVD Line: 18294
+
+//  <item> SFDITEM_FIELD__I2C1_ST_SSELn
+//    <name> SSELn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40004904) This bit is set when I2C is addressed by other master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_ST ) </loc>
+//      <o.4..4> SSELn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C1_ST_MLOSTn  -----------------------------------
+// SVD Line: 18300
+
+//  <item> SFDITEM_FIELD__I2C1_ST_MLOSTn
+//    <name> MLOSTn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004904) This bit represents the result of bus arbitration in master mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_ST ) </loc>
+//      <o.3..3> MLOSTn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C1_ST_BUSYn  -----------------------------------
+// SVD Line: 18306
+
+//  <item> SFDITEM_FIELD__I2C1_ST_BUSYn
+//    <name> BUSYn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40004904) This bit reflects bus status </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_ST ) </loc>
+//      <o.2..2> BUSYn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C1_ST_TMODEn  -----------------------------------
+// SVD Line: 18312
+
+//  <item> SFDITEM_FIELD__I2C1_ST_TMODEn
+//    <name> TMODEn </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x40004904) This bit is used to indicate whether I2C is transmitter or receiver </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_ST ) </loc>
+//      <o.1..1> TMODEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C1_ST_RXACKn  -----------------------------------
+// SVD Line: 18318
+
+//  <item> SFDITEM_FIELD__I2C1_ST_RXACKn
+//    <name> RXACKn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004904) This bit shows the state of ACK signal </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_ST ) </loc>
+//      <o.0..0> RXACKn
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C1_ST  ------------------------------------
+// SVD Line: 18263
+
+//  <rtree> SFDITEM_REG__I2C1_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004904) I2Cn Status Register </i>
+//    <loc> ( (unsigned int)((I2C1_ST >> 0) & 0xFFFFFFFF), ((I2C1_ST = (I2C1_ST & ~(0xFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFD) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C1_ST_GCALLn </item>
+//    <item> SFDITEM_FIELD__I2C1_ST_TENDn </item>
+//    <item> SFDITEM_FIELD__I2C1_ST_STOPDn </item>
+//    <item> SFDITEM_FIELD__I2C1_ST_SSELn </item>
+//    <item> SFDITEM_FIELD__I2C1_ST_MLOSTn </item>
+//    <item> SFDITEM_FIELD__I2C1_ST_BUSYn </item>
+//    <item> SFDITEM_FIELD__I2C1_ST_TMODEn </item>
+//    <item> SFDITEM_FIELD__I2C1_ST_RXACKn </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C1_SAR1  --------------------------------
+// SVD Line: 18326
+
+unsigned int I2C1_SAR1 __AT (0x40004908);
+
+
+
+// -------------------------------  Field Item: I2C1_SAR1_SLAn  -----------------------------------
+// SVD Line: 18335
+
+//  <item> SFDITEM_FIELD__I2C1_SAR1_SLAn
+//    <name> SLAn </name>
+//    <rw> 
+//    <i> [Bits 7..1] RW (@ 0x40004908) These bits configure the slave address 1 in slave mode </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C1_SAR1 >> 1) & 0x7F), ((I2C1_SAR1 = (I2C1_SAR1 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: I2C1_SAR1_GCALLnEN  ---------------------------------
+// SVD Line: 18341
+
+//  <item> SFDITEM_FIELD__I2C1_SAR1_GCALLnEN
+//    <name> GCALLnEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004908) This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_SAR1 ) </loc>
+//      <o.0..0> GCALLnEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C1_SAR1  -----------------------------------
+// SVD Line: 18326
+
+//  <rtree> SFDITEM_REG__I2C1_SAR1
+//    <name> SAR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004908) I2Cn Slave Address Register 1 </i>
+//    <loc> ( (unsigned int)((I2C1_SAR1 >> 0) & 0xFFFFFFFF), ((I2C1_SAR1 = (I2C1_SAR1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C1_SAR1_SLAn </item>
+//    <item> SFDITEM_FIELD__I2C1_SAR1_GCALLnEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C1_SAR2  --------------------------------
+// SVD Line: 18349
+
+unsigned int I2C1_SAR2 __AT (0x4000490C);
+
+
+
+// -------------------------------  Field Item: I2C1_SAR2_SLAn  -----------------------------------
+// SVD Line: 18358
+
+//  <item> SFDITEM_FIELD__I2C1_SAR2_SLAn
+//    <name> SLAn </name>
+//    <rw> 
+//    <i> [Bits 7..1] RW (@ 0x4000490C) These bits configure the slave address 2 in slave mode </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C1_SAR2 >> 1) & 0x7F), ((I2C1_SAR2 = (I2C1_SAR2 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: I2C1_SAR2_GCALLnEN  ---------------------------------
+// SVD Line: 18364
+
+//  <item> SFDITEM_FIELD__I2C1_SAR2_GCALLnEN
+//    <name> GCALLnEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x4000490C) This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C1_SAR2 ) </loc>
+//      <o.0..0> GCALLnEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C1_SAR2  -----------------------------------
+// SVD Line: 18349
+
+//  <rtree> SFDITEM_REG__I2C1_SAR2
+//    <name> SAR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000490C) I2Cn Slave Address Register 2 </i>
+//    <loc> ( (unsigned int)((I2C1_SAR2 >> 0) & 0xFFFFFFFF), ((I2C1_SAR2 = (I2C1_SAR2 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C1_SAR2_SLAn </item>
+//    <item> SFDITEM_FIELD__I2C1_SAR2_GCALLnEN </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: I2C1_DR  ---------------------------------
+// SVD Line: 18372
+
+unsigned int I2C1_DR __AT (0x40004910);
+
+
+
+// --------------------------------  Field Item: I2C1_DR_DATA  ------------------------------------
+// SVD Line: 18381
+
+//  <item> SFDITEM_FIELD__I2C1_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40004910) The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C1_DR >> 0) & 0xFF), ((I2C1_DR = (I2C1_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C1_DR  ------------------------------------
+// SVD Line: 18372
+
+//  <rtree> SFDITEM_REG__I2C1_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004910) I2Cn Data Register </i>
+//    <loc> ( (unsigned int)((I2C1_DR >> 0) & 0xFFFFFFFF), ((I2C1_DR = (I2C1_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C1_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C1_SDHR  --------------------------------
+// SVD Line: 18389
+
+unsigned int I2C1_SDHR __AT (0x40004914);
+
+
+
+// -------------------------------  Field Item: I2C1_SDHR_HLDT  -----------------------------------
+// SVD Line: 18398
+
+//  <item> SFDITEM_FIELD__I2C1_SDHR_HLDT
+//    <name> HLDT </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40004914) This register is used to control SDA output timing from the falling edge of SCL </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C1_SDHR >> 0) & 0xFFF), ((I2C1_SDHR = (I2C1_SDHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C1_SDHR  -----------------------------------
+// SVD Line: 18389
+
+//  <rtree> SFDITEM_REG__I2C1_SDHR
+//    <name> SDHR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004914) I2Cn SDA Hold Time Register </i>
+//    <loc> ( (unsigned int)((I2C1_SDHR >> 0) & 0xFFFFFFFF), ((I2C1_SDHR = (I2C1_SDHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C1_SDHR_HLDT </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C1_SCLR  --------------------------------
+// SVD Line: 18406
+
+unsigned int I2C1_SCLR __AT (0x40004918);
+
+
+
+// -------------------------------  Field Item: I2C1_SCLR_SCLL  -----------------------------------
+// SVD Line: 18415
+
+//  <item> SFDITEM_FIELD__I2C1_SCLR_SCLL
+//    <name> SCLL </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40004918) This register defines the low period of SCL in master mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C1_SCLR >> 0) & 0xFFF), ((I2C1_SCLR = (I2C1_SCLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C1_SCLR  -----------------------------------
+// SVD Line: 18406
+
+//  <rtree> SFDITEM_REG__I2C1_SCLR
+//    <name> SCLR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004918) I2Cn SCL Low Period Register </i>
+//    <loc> ( (unsigned int)((I2C1_SCLR >> 0) & 0xFFFFFFFF), ((I2C1_SCLR = (I2C1_SCLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C1_SCLR_SCLL </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C1_SCHR  --------------------------------
+// SVD Line: 18423
+
+unsigned int I2C1_SCHR __AT (0x4000491C);
+
+
+
+// -------------------------------  Field Item: I2C1_SCHR_SCLH  -----------------------------------
+// SVD Line: 18432
+
+//  <item> SFDITEM_FIELD__I2C1_SCHR_SCLH
+//    <name> SCLH </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x4000491C) This register defines the high period of SCL in master mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C1_SCHR >> 0) & 0xFFF), ((I2C1_SCHR = (I2C1_SCHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C1_SCHR  -----------------------------------
+// SVD Line: 18423
+
+//  <rtree> SFDITEM_REG__I2C1_SCHR
+//    <name> SCHR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x4000491C) I2Cn SCL High Period Register </i>
+//    <loc> ( (unsigned int)((I2C1_SCHR >> 0) & 0xFFFFFFFF), ((I2C1_SCHR = (I2C1_SCHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C1_SCHR_SCLH </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: I2C1  -------------------------------------
+// SVD Line: 18461
+
+//  <view> I2C1
+//    <name> I2C1 </name>
+//    <item> SFDITEM_REG__I2C1_CR </item>
+//    <item> SFDITEM_REG__I2C1_ST </item>
+//    <item> SFDITEM_REG__I2C1_SAR1 </item>
+//    <item> SFDITEM_REG__I2C1_SAR2 </item>
+//    <item> SFDITEM_REG__I2C1_DR </item>
+//    <item> SFDITEM_REG__I2C1_SDHR </item>
+//    <item> SFDITEM_REG__I2C1_SCLR </item>
+//    <item> SFDITEM_REG__I2C1_SCHR </item>
+//  </view>
+//  
+
+
+// -----------------------------  Register Item Address: I2C2_CR  ---------------------------------
+// SVD Line: 18204
+
+unsigned int I2C2_CR __AT (0x40004A00);
+
+
+
+// -------------------------------  Field Item: I2C2_CR_I2CnEN  -----------------------------------
+// SVD Line: 18213
+
+//  <item> SFDITEM_FIELD__I2C2_CR_I2CnEN
+//    <name> I2CnEN </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40004A00) Activate I2Cn Block by supplying </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_CR ) </loc>
+//      <o.7..7> I2CnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C2_CR_TXDLYENBn  ---------------------------------
+// SVD Line: 18219
+
+//  <item> SFDITEM_FIELD__I2C2_CR_TXDLYENBn
+//    <name> TXDLYENBn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40004A00) SDHR Register Control </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_CR ) </loc>
+//      <o.6..6> TXDLYENBn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C2_CR_I2CnIEN  ----------------------------------
+// SVD Line: 18225
+
+//  <item> SFDITEM_FIELD__I2C2_CR_I2CnIEN
+//    <name> I2CnIEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40004A00) I2Cn Interrupt Enable </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_CR ) </loc>
+//      <o.5..5> I2CnIEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C2_CR_I2CnIFLAG  ---------------------------------
+// SVD Line: 18231
+
+//  <item> SFDITEM_FIELD__I2C2_CR_I2CnIFLAG
+//    <name> I2CnIFLAG </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40004A00) I2Cn Interrupt Flag </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_CR ) </loc>
+//      <o.4..4> I2CnIFLAG
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C2_CR_ACKnEN  -----------------------------------
+// SVD Line: 18237
+
+//  <item> SFDITEM_FIELD__I2C2_CR_ACKnEN
+//    <name> ACKnEN </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004A00) Controls ACK signal generation at ninth SCL period </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_CR ) </loc>
+//      <o.3..3> ACKnEN
+//    </check>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: I2C2_CR_IMASTERn  ----------------------------------
+// SVD Line: 18243
+
+//  <item> SFDITEM_FIELD__I2C2_CR_IMASTERn
+//    <name> IMASTERn </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x40004A00) Represent Operation Mode of I2Cn </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_CR ) </loc>
+//      <o.2..2> IMASTERn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C2_CR_STOPCn  -----------------------------------
+// SVD Line: 18249
+
+//  <item> SFDITEM_FIELD__I2C2_CR_STOPCn
+//    <name> STOPCn </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x40004A00) STOP Condition Generation when I2Cn is master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_CR ) </loc>
+//      <o.1..1> STOPCn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C2_CR_STARTCn  ----------------------------------
+// SVD Line: 18255
+
+//  <item> SFDITEM_FIELD__I2C2_CR_STARTCn
+//    <name> STARTCn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004A00) START Condition Generation when I2Cn is master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_CR ) </loc>
+//      <o.0..0> STARTCn
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C2_CR  ------------------------------------
+// SVD Line: 18204
+
+//  <rtree> SFDITEM_REG__I2C2_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004A00) I2Cn Control Register </i>
+//    <loc> ( (unsigned int)((I2C2_CR >> 0) & 0xFFFFFFFF), ((I2C2_CR = (I2C2_CR & ~(0xFBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C2_CR_I2CnEN </item>
+//    <item> SFDITEM_FIELD__I2C2_CR_TXDLYENBn </item>
+//    <item> SFDITEM_FIELD__I2C2_CR_I2CnIEN </item>
+//    <item> SFDITEM_FIELD__I2C2_CR_I2CnIFLAG </item>
+//    <item> SFDITEM_FIELD__I2C2_CR_ACKnEN </item>
+//    <item> SFDITEM_FIELD__I2C2_CR_IMASTERn </item>
+//    <item> SFDITEM_FIELD__I2C2_CR_STOPCn </item>
+//    <item> SFDITEM_FIELD__I2C2_CR_STARTCn </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: I2C2_ST  ---------------------------------
+// SVD Line: 18263
+
+unsigned int I2C2_ST __AT (0x40004A04);
+
+
+
+// -------------------------------  Field Item: I2C2_ST_GCALLn  -----------------------------------
+// SVD Line: 18272
+
+//  <item> SFDITEM_FIELD__I2C2_ST_GCALLn
+//    <name> GCALLn </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x40004A04) This bit has different meaning depending on whether I2C is master or slave.  When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.  When I2C is a slave, this bit is used to indicate general call. </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_ST ) </loc>
+//      <o.7..7> GCALLn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C2_ST_TENDn  -----------------------------------
+// SVD Line: 18282
+
+//  <item> SFDITEM_FIELD__I2C2_ST_TENDn
+//    <name> TENDn </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x40004A04) This bit is set when 1-byte of data is transferred completely </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_ST ) </loc>
+//      <o.6..6> TENDn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C2_ST_STOPDn  -----------------------------------
+// SVD Line: 18288
+
+//  <item> SFDITEM_FIELD__I2C2_ST_STOPDn
+//    <name> STOPDn </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40004A04) This bit is set when a STOP condition is detected </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_ST ) </loc>
+//      <o.5..5> STOPDn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C2_ST_SSELn  -----------------------------------
+// SVD Line: 18294
+
+//  <item> SFDITEM_FIELD__I2C2_ST_SSELn
+//    <name> SSELn </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x40004A04) This bit is set when I2C is addressed by other master </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_ST ) </loc>
+//      <o.4..4> SSELn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C2_ST_MLOSTn  -----------------------------------
+// SVD Line: 18300
+
+//  <item> SFDITEM_FIELD__I2C2_ST_MLOSTn
+//    <name> MLOSTn </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x40004A04) This bit represents the result of bus arbitration in master mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_ST ) </loc>
+//      <o.3..3> MLOSTn
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: I2C2_ST_BUSYn  -----------------------------------
+// SVD Line: 18306
+
+//  <item> SFDITEM_FIELD__I2C2_ST_BUSYn
+//    <name> BUSYn </name>
+//    <rw> 
+//    <i> [Bit 2] RW (@ 0x40004A04) This bit reflects bus status </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_ST ) </loc>
+//      <o.2..2> BUSYn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C2_ST_TMODEn  -----------------------------------
+// SVD Line: 18312
+
+//  <item> SFDITEM_FIELD__I2C2_ST_TMODEn
+//    <name> TMODEn </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x40004A04) This bit is used to indicate whether I2C is transmitter or receiver </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_ST ) </loc>
+//      <o.1..1> TMODEn
+//    </check>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: I2C2_ST_RXACKn  -----------------------------------
+// SVD Line: 18318
+
+//  <item> SFDITEM_FIELD__I2C2_ST_RXACKn
+//    <name> RXACKn </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004A04) This bit shows the state of ACK signal </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_ST ) </loc>
+//      <o.0..0> RXACKn
+//    </check>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C2_ST  ------------------------------------
+// SVD Line: 18263
+
+//  <rtree> SFDITEM_REG__I2C2_ST
+//    <name> ST </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004A04) I2Cn Status Register </i>
+//    <loc> ( (unsigned int)((I2C2_ST >> 0) & 0xFFFFFFFF), ((I2C2_ST = (I2C2_ST & ~(0xFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFD) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C2_ST_GCALLn </item>
+//    <item> SFDITEM_FIELD__I2C2_ST_TENDn </item>
+//    <item> SFDITEM_FIELD__I2C2_ST_STOPDn </item>
+//    <item> SFDITEM_FIELD__I2C2_ST_SSELn </item>
+//    <item> SFDITEM_FIELD__I2C2_ST_MLOSTn </item>
+//    <item> SFDITEM_FIELD__I2C2_ST_BUSYn </item>
+//    <item> SFDITEM_FIELD__I2C2_ST_TMODEn </item>
+//    <item> SFDITEM_FIELD__I2C2_ST_RXACKn </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C2_SAR1  --------------------------------
+// SVD Line: 18326
+
+unsigned int I2C2_SAR1 __AT (0x40004A08);
+
+
+
+// -------------------------------  Field Item: I2C2_SAR1_SLAn  -----------------------------------
+// SVD Line: 18335
+
+//  <item> SFDITEM_FIELD__I2C2_SAR1_SLAn
+//    <name> SLAn </name>
+//    <rw> 
+//    <i> [Bits 7..1] RW (@ 0x40004A08) These bits configure the slave address 1 in slave mode </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C2_SAR1 >> 1) & 0x7F), ((I2C2_SAR1 = (I2C2_SAR1 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: I2C2_SAR1_GCALLnEN  ---------------------------------
+// SVD Line: 18341
+
+//  <item> SFDITEM_FIELD__I2C2_SAR1_GCALLnEN
+//    <name> GCALLnEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004A08) This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_SAR1 ) </loc>
+//      <o.0..0> GCALLnEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C2_SAR1  -----------------------------------
+// SVD Line: 18326
+
+//  <rtree> SFDITEM_REG__I2C2_SAR1
+//    <name> SAR1 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004A08) I2Cn Slave Address Register 1 </i>
+//    <loc> ( (unsigned int)((I2C2_SAR1 >> 0) & 0xFFFFFFFF), ((I2C2_SAR1 = (I2C2_SAR1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C2_SAR1_SLAn </item>
+//    <item> SFDITEM_FIELD__I2C2_SAR1_GCALLnEN </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C2_SAR2  --------------------------------
+// SVD Line: 18349
+
+unsigned int I2C2_SAR2 __AT (0x40004A0C);
+
+
+
+// -------------------------------  Field Item: I2C2_SAR2_SLAn  -----------------------------------
+// SVD Line: 18358
+
+//  <item> SFDITEM_FIELD__I2C2_SAR2_SLAn
+//    <name> SLAn </name>
+//    <rw> 
+//    <i> [Bits 7..1] RW (@ 0x40004A0C) These bits configure the slave address 2 in slave mode </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C2_SAR2 >> 1) & 0x7F), ((I2C2_SAR2 = (I2C2_SAR2 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: I2C2_SAR2_GCALLnEN  ---------------------------------
+// SVD Line: 18364
+
+//  <item> SFDITEM_FIELD__I2C2_SAR2_GCALLnEN
+//    <name> GCALLnEN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40004A0C) This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode </i>
+//    <check> 
+//      <loc> ( (unsigned int) I2C2_SAR2 ) </loc>
+//      <o.0..0> GCALLnEN
+//    </check>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C2_SAR2  -----------------------------------
+// SVD Line: 18349
+
+//  <rtree> SFDITEM_REG__I2C2_SAR2
+//    <name> SAR2 </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004A0C) I2Cn Slave Address Register 2 </i>
+//    <loc> ( (unsigned int)((I2C2_SAR2 >> 0) & 0xFFFFFFFF), ((I2C2_SAR2 = (I2C2_SAR2 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C2_SAR2_SLAn </item>
+//    <item> SFDITEM_FIELD__I2C2_SAR2_GCALLnEN </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: I2C2_DR  ---------------------------------
+// SVD Line: 18372
+
+unsigned int I2C2_DR __AT (0x40004A10);
+
+
+
+// --------------------------------  Field Item: I2C2_DR_DATA  ------------------------------------
+// SVD Line: 18381
+
+//  <item> SFDITEM_FIELD__I2C2_DR_DATA
+//    <name> DATA </name>
+//    <rw> 
+//    <i> [Bits 7..0] RW (@ 0x40004A10) The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((I2C2_DR >> 0) & 0xFF), ((I2C2_DR = (I2C2_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: I2C2_DR  ------------------------------------
+// SVD Line: 18372
+
+//  <rtree> SFDITEM_REG__I2C2_DR
+//    <name> DR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004A10) I2Cn Data Register </i>
+//    <loc> ( (unsigned int)((I2C2_DR >> 0) & 0xFFFFFFFF), ((I2C2_DR = (I2C2_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C2_DR_DATA </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C2_SDHR  --------------------------------
+// SVD Line: 18389
+
+unsigned int I2C2_SDHR __AT (0x40004A14);
+
+
+
+// -------------------------------  Field Item: I2C2_SDHR_HLDT  -----------------------------------
+// SVD Line: 18398
+
+//  <item> SFDITEM_FIELD__I2C2_SDHR_HLDT
+//    <name> HLDT </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40004A14) This register is used to control SDA output timing from the falling edge of SCL </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C2_SDHR >> 0) & 0xFFF), ((I2C2_SDHR = (I2C2_SDHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C2_SDHR  -----------------------------------
+// SVD Line: 18389
+
+//  <rtree> SFDITEM_REG__I2C2_SDHR
+//    <name> SDHR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004A14) I2Cn SDA Hold Time Register </i>
+//    <loc> ( (unsigned int)((I2C2_SDHR >> 0) & 0xFFFFFFFF), ((I2C2_SDHR = (I2C2_SDHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C2_SDHR_HLDT </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C2_SCLR  --------------------------------
+// SVD Line: 18406
+
+unsigned int I2C2_SCLR __AT (0x40004A18);
+
+
+
+// -------------------------------  Field Item: I2C2_SCLR_SCLL  -----------------------------------
+// SVD Line: 18415
+
+//  <item> SFDITEM_FIELD__I2C2_SCLR_SCLL
+//    <name> SCLL </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40004A18) This register defines the low period of SCL in master mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C2_SCLR >> 0) & 0xFFF), ((I2C2_SCLR = (I2C2_SCLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C2_SCLR  -----------------------------------
+// SVD Line: 18406
+
+//  <rtree> SFDITEM_REG__I2C2_SCLR
+//    <name> SCLR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004A18) I2Cn SCL Low Period Register </i>
+//    <loc> ( (unsigned int)((I2C2_SCLR >> 0) & 0xFFFFFFFF), ((I2C2_SCLR = (I2C2_SCLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C2_SCLR_SCLL </item>
+//  </rtree>
+//  
+
+
+// ----------------------------  Register Item Address: I2C2_SCHR  --------------------------------
+// SVD Line: 18423
+
+unsigned int I2C2_SCHR __AT (0x40004A1C);
+
+
+
+// -------------------------------  Field Item: I2C2_SCHR_SCLH  -----------------------------------
+// SVD Line: 18432
+
+//  <item> SFDITEM_FIELD__I2C2_SCHR_SCLH
+//    <name> SCLH </name>
+//    <rw> 
+//    <i> [Bits 11..0] RW (@ 0x40004A1C) This register defines the high period of SCL in master mode </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((I2C2_SCHR >> 0) & 0xFFF), ((I2C2_SCHR = (I2C2_SCHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: I2C2_SCHR  -----------------------------------
+// SVD Line: 18423
+
+//  <rtree> SFDITEM_REG__I2C2_SCHR
+//    <name> SCHR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40004A1C) I2Cn SCL High Period Register </i>
+//    <loc> ( (unsigned int)((I2C2_SCHR >> 0) & 0xFFFFFFFF), ((I2C2_SCHR = (I2C2_SCHR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__I2C2_SCHR_SCLH </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: I2C2  -------------------------------------
+// SVD Line: 18480
+
+//  <view> I2C2
+//    <name> I2C2 </name>
+//    <item> SFDITEM_REG__I2C2_CR </item>
+//    <item> SFDITEM_REG__I2C2_ST </item>
+//    <item> SFDITEM_REG__I2C2_SAR1 </item>
+//    <item> SFDITEM_REG__I2C2_SAR2 </item>
+//    <item> SFDITEM_REG__I2C2_DR </item>
+//    <item> SFDITEM_REG__I2C2_SDHR </item>
+//    <item> SFDITEM_REG__I2C2_SCLR </item>
+//    <item> SFDITEM_REG__I2C2_SCHR </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: LCD_CR  ---------------------------------
+// SVD Line: 18513
+
+unsigned int LCD_CR __AT (0x40005000);
+
+
+
+// --------------------------------  Field Item: LCD_CR_IRSEL  ------------------------------------
+// SVD Line: 18522
+
+//  <item> SFDITEM_FIELD__LCD_CR_IRSEL
+//    <name> IRSEL </name>
+//    <rw> 
+//    <i> [Bits 7..6] RW (@ 0x40005000) \nInternal LCD Bias Dividing Resistor Selection\n0 : RLCD3 = RLCD3: 105/105/80[kohm] @(1/2)/(1/3)/(1/4) bias\n1 : RLCD1 = RLCD1: 10/10/10[kohm] @(1/2)/(1/3)/(1/4) bias\n2 : RLCD2 = RLCD2: 66/66/50[kohm] @(1/2)/(1/3)/(1/4) bias\n3 : RLCD4 = RLCD4: 320/320/240[kohm] @(1/2)/(1/3)/(1/4) bias </i>
+//    <combo> 
+//      <loc> ( (unsigned int) LCD_CR ) </loc>
+//      <o.7..6> IRSEL
+//        <0=> 0: RLCD3 = RLCD3: 105/105/80[kohm] @(1/2)/(1/3)/(1/4) bias
+//        <1=> 1: RLCD1 = RLCD1: 10/10/10[kohm] @(1/2)/(1/3)/(1/4) bias
+//        <2=> 2: RLCD2 = RLCD2: 66/66/50[kohm] @(1/2)/(1/3)/(1/4) bias
+//        <3=> 3: RLCD4 = RLCD4: 320/320/240[kohm] @(1/2)/(1/3)/(1/4) bias
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: LCD_CR_DBS  -------------------------------------
+// SVD Line: 18550
+
+//  <item> SFDITEM_FIELD__LCD_CR_DBS
+//    <name> DBS </name>
+//    <rw> 
+//    <i> [Bits 5..3] RW (@ 0x40005000) \nLCD Duty and Bias Selection\n0 : Duty8Bias4 = 1/8 duty, 1/4 bias\n1 : Duty6Bias4 = 1/6 duty, 1/4 bias\n2 : Duty5Bias3 = 1/5 duty, 1/3 bias\n3 : Duty4Bias3 = 1/4 duty, 1/3 bias\n4 : Duty3Bias3 = 1/3 duty, 1/3 bias\n5 : Duty3Bias2 = 1/3 duty, 1/2 bias\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
+//    <combo> 
+//      <loc> ( (unsigned int) LCD_CR ) </loc>
+//      <o.5..3> DBS
+//        <0=> 0: Duty8Bias4 = 1/8 duty, 1/4 bias
+//        <1=> 1: Duty6Bias4 = 1/6 duty, 1/4 bias
+//        <2=> 2: Duty5Bias3 = 1/5 duty, 1/3 bias
+//        <3=> 3: Duty4Bias3 = 1/4 duty, 1/3 bias
+//        <4=> 4: Duty3Bias3 = 1/3 duty, 1/3 bias
+//        <5=> 5: Duty3Bias2 = 1/3 duty, 1/2 bias
+//        <6=> 6: 
+//        <7=> 7: 
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: LCD_CR_LCLK  ------------------------------------
+// SVD Line: 18588
+
+//  <item> SFDITEM_FIELD__LCD_CR_LCLK
+//    <name> LCLK </name>
+//    <rw> 
+//    <i> [Bits 2..1] RW (@ 0x40005000) \nLCD Clock Selection (When fLCD = 32.768kHz)\n0 : fLCD256 = 128Hz\n1 : fLCD128 = 256Hz\n2 : fLCD64 = 512Hz\n3 : fLCD32 = 1024Hz </i>
+//    <combo> 
+//      <loc> ( (unsigned int) LCD_CR ) </loc>
+//      <o.2..1> LCLK
+//        <0=> 0: fLCD256 = 128Hz
+//        <1=> 1: fLCD128 = 256Hz
+//        <2=> 2: fLCD64 = 512Hz
+//        <3=> 3: fLCD32 = 1024Hz
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Field Item: LCD_CR_DISP  ------------------------------------
+// SVD Line: 18616
+
+//  <item> SFDITEM_FIELD__LCD_CR_DISP
+//    <name> DISP </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x40005000) \nLCD Display Control\n0 : Off = Display off\n1 : On = Normal display on </i>
+//    <combo> 
+//      <loc> ( (unsigned int) LCD_CR ) </loc>
+//      <o.0..0> DISP
+//        <0=> 0: Off = Display off
+//        <1=> 1: On = Normal display on
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: LCD_CR  -------------------------------------
+// SVD Line: 18513
+
+//  <rtree> SFDITEM_REG__LCD_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40005000) LCD Driver Control Register </i>
+//    <loc> ( (unsigned int)((LCD_CR >> 0) & 0xFFFFFFFF), ((LCD_CR = (LCD_CR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__LCD_CR_IRSEL </item>
+//    <item> SFDITEM_FIELD__LCD_CR_DBS </item>
+//    <item> SFDITEM_FIELD__LCD_CR_LCLK </item>
+//    <item> SFDITEM_FIELD__LCD_CR_DISP </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_BCCR  --------------------------------
+// SVD Line: 18636
+
+unsigned int LCD_BCCR __AT (0x40005004);
+
+
+
+// -------------------------------  Field Item: LCD_BCCR_LCDABC  ----------------------------------
+// SVD Line: 18645
+
+//  <item> SFDITEM_FIELD__LCD_BCCR_LCDABC
+//    <name> LCDABC </name>
+//    <rw> 
+//    <i> [Bit 12] RW (@ 0x40005004) \nLCD Automatic Bias Control\n0 : Off = LCD automatic bias is off\n1 : On = LCD automatic bias is on </i>
+//    <combo> 
+//      <loc> ( (unsigned int) LCD_BCCR ) </loc>
+//      <o.12..12> LCDABC
+//        <0=> 0: Off = LCD automatic bias is off
+//        <1=> 1: On = LCD automatic bias is on
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: LCD_BCCR_BMSEL  -----------------------------------
+// SVD Line: 18663
+
+//  <item> SFDITEM_FIELD__LCD_BCCR_BMSEL
+//    <name> BMSEL </name>
+//    <rw> 
+//    <i> [Bits 10..8] RW (@ 0x40005004) \n'Bias Mode A' Time Selection\n0 : BMA1Clk = 'Bias Mode A' for 1-clock of fLCD\n1 : BMA2Clk = 'Bias Mode A' for 2-clock of fLCD\n2 : BMA3Clk = 'Bias Mode A' for 3-clock of fLCD\n3 : BMA4Clk = 'Bias Mode A' for 4-clock of fLCD\n4 : BMA5Clk = 'Bias Mode A' for 5-clock of fLCD\n5 : BMA6Clk = 'Bias Mode A' for 6-clock of fLCD\n6 : BMA7Clk = 'Bias Mode A' for 7-clock of fLCD\n7 : BMA8Clk = 'Bias Mode A' for 8-clock of fLCD </i>
+//    <combo> 
+//      <loc> ( (unsigned int) LCD_BCCR ) </loc>
+//      <o.10..8> BMSEL
+//        <0=> 0: BMA1Clk = 'Bias Mode A' for 1-clock of fLCD
+//        <1=> 1: BMA2Clk = 'Bias Mode A' for 2-clock of fLCD
+//        <2=> 2: BMA3Clk = 'Bias Mode A' for 3-clock of fLCD
+//        <3=> 3: BMA4Clk = 'Bias Mode A' for 4-clock of fLCD
+//        <4=> 4: BMA5Clk = 'Bias Mode A' for 5-clock of fLCD
+//        <5=> 5: BMA6Clk = 'Bias Mode A' for 6-clock of fLCD
+//        <6=> 6: BMA7Clk = 'Bias Mode A' for 7-clock of fLCD
+//        <7=> 7: BMA8Clk = 'Bias Mode A' for 8-clock of fLCD
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: LCD_BCCR_LCTEN  -----------------------------------
+// SVD Line: 18711
+
+//  <item> SFDITEM_FIELD__LCD_BCCR_LCTEN
+//    <name> LCTEN </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x40005004) \nLCD Driver Contrast Control\n0 : Disable = Disable LCD driver contrast.\n1 : Enable = Enable LCD driver contrast. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) LCD_BCCR ) </loc>
+//      <o.5..5> LCTEN
+//        <0=> 0: Disable = Disable LCD driver contrast.
+//        <1=> 1: Enable = Enable LCD driver contrast.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: LCD_BCCR_VLCD  -----------------------------------
+// SVD Line: 18729
+
+//  <item> SFDITEM_FIELD__LCD_BCCR_VLCD
+//    <name> VLCD </name>
+//    <rw> 
+//    <i> [Bits 3..0] RW (@ 0x40005004) \nVLC0 Voltage Control when the contrast is enabled\n0 : Step0 = VDD x 16/31 Step\n1 : Step1 = VDD x 16/30 Step\n2 : Step2 = VDD x 16/29 Step\n3 : Step3 = VDD x 16/28 Step\n4 : Step4 = VDD x 16/27 Step\n5 : Step5 = VDD x 16/26 Step\n6 : Step6 = VDD x 16/25 Step\n7 : Step7 = VDD x 16/24 Step\n8 : Step8 = VDD x 16/23 Step\n9 : Step9 = VDD x 16/22 Step\n10 : Step10 = VDD x 16/21 Step\n11 : Step11 = VDD x 16/20 Step\n12 : Step12 = VDD x 16/19 Step\n13 : Step13 = VDD x 16/18 Step\n14 : Step14 = VDD x 16/17 Step\n15 : Step15 = VDD x 16/16 Step </i>
+//    <combo> 
+//      <loc> ( (unsigned int) LCD_BCCR ) </loc>
+//      <o.3..0> VLCD
+//        <0=> 0: Step0 = VDD x 16/31 Step
+//        <1=> 1: Step1 = VDD x 16/30 Step
+//        <2=> 2: Step2 = VDD x 16/29 Step
+//        <3=> 3: Step3 = VDD x 16/28 Step
+//        <4=> 4: Step4 = VDD x 16/27 Step
+//        <5=> 5: Step5 = VDD x 16/26 Step
+//        <6=> 6: Step6 = VDD x 16/25 Step
+//        <7=> 7: Step7 = VDD x 16/24 Step
+//        <8=> 8: Step8 = VDD x 16/23 Step
+//        <9=> 9: Step9 = VDD x 16/22 Step
+//        <10=> 10: Step10 = VDD x 16/21 Step
+//        <11=> 11: Step11 = VDD x 16/20 Step
+//        <12=> 12: Step12 = VDD x 16/19 Step
+//        <13=> 13: Step13 = VDD x 16/18 Step
+//        <14=> 14: Step14 = VDD x 16/17 Step
+//        <15=> 15: Step15 = VDD x 16/16 Step
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: LCD_BCCR  ------------------------------------
+// SVD Line: 18636
+
+//  <rtree> SFDITEM_REG__LCD_BCCR
+//    <name> BCCR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x40005004) LCD Automatic Bias and Contrast Control Register </i>
+//    <loc> ( (unsigned int)((LCD_BCCR >> 0) & 0xFFFFFFFF), ((LCD_BCCR = (LCD_BCCR & ~(0x172FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x172F) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__LCD_BCCR_LCDABC </item>
+//    <item> SFDITEM_FIELD__LCD_BCCR_BMSEL </item>
+//    <item> SFDITEM_FIELD__LCD_BCCR_LCTEN </item>
+//    <item> SFDITEM_FIELD__LCD_BCCR_VLCD </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR0  ---------------------------------
+// SVD Line: 18819
+
+unsigned char LCD_DR0 __AT (0x40005010);
+
+
+
+// ---------------------------------  Register Item: LCD_DR0  -------------------------------------
+// SVD Line: 18819
+
+//  <item> SFDITEM_REG__LCD_DR0
+//    <name> DR0 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005010) LCD Display Data Register 0 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR0 >> 0) & 0xFFFFFFFF), ((LCD_DR0 = (LCD_DR0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR1  ---------------------------------
+// SVD Line: 18827
+
+unsigned char LCD_DR1 __AT (0x40005011);
+
+
+
+// ---------------------------------  Register Item: LCD_DR1  -------------------------------------
+// SVD Line: 18827
+
+//  <item> SFDITEM_REG__LCD_DR1
+//    <name> DR1 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005011) LCD Display Data Register 1 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR1 >> 0) & 0xFFFFFFFF), ((LCD_DR1 = (LCD_DR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR2  ---------------------------------
+// SVD Line: 18835
+
+unsigned char LCD_DR2 __AT (0x40005012);
+
+
+
+// ---------------------------------  Register Item: LCD_DR2  -------------------------------------
+// SVD Line: 18835
+
+//  <item> SFDITEM_REG__LCD_DR2
+//    <name> DR2 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005012) LCD Display Data Register 2 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR2 >> 0) & 0xFFFFFFFF), ((LCD_DR2 = (LCD_DR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR3  ---------------------------------
+// SVD Line: 18843
+
+unsigned char LCD_DR3 __AT (0x40005013);
+
+
+
+// ---------------------------------  Register Item: LCD_DR3  -------------------------------------
+// SVD Line: 18843
+
+//  <item> SFDITEM_REG__LCD_DR3
+//    <name> DR3 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005013) LCD Display Data Register 3 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR3 >> 0) & 0xFFFFFFFF), ((LCD_DR3 = (LCD_DR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR4  ---------------------------------
+// SVD Line: 18851
+
+unsigned char LCD_DR4 __AT (0x40005014);
+
+
+
+// ---------------------------------  Register Item: LCD_DR4  -------------------------------------
+// SVD Line: 18851
+
+//  <item> SFDITEM_REG__LCD_DR4
+//    <name> DR4 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005014) LCD Display Data Register 4 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR4 >> 0) & 0xFFFFFFFF), ((LCD_DR4 = (LCD_DR4 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR5  ---------------------------------
+// SVD Line: 18859
+
+unsigned char LCD_DR5 __AT (0x40005015);
+
+
+
+// ---------------------------------  Register Item: LCD_DR5  -------------------------------------
+// SVD Line: 18859
+
+//  <item> SFDITEM_REG__LCD_DR5
+//    <name> DR5 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005015) LCD Display Data Register 5 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR5 >> 0) & 0xFFFFFFFF), ((LCD_DR5 = (LCD_DR5 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR6  ---------------------------------
+// SVD Line: 18867
+
+unsigned char LCD_DR6 __AT (0x40005016);
+
+
+
+// ---------------------------------  Register Item: LCD_DR6  -------------------------------------
+// SVD Line: 18867
+
+//  <item> SFDITEM_REG__LCD_DR6
+//    <name> DR6 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005016) LCD Display Data Register 6 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR6 >> 0) & 0xFFFFFFFF), ((LCD_DR6 = (LCD_DR6 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR7  ---------------------------------
+// SVD Line: 18875
+
+unsigned char LCD_DR7 __AT (0x40005017);
+
+
+
+// ---------------------------------  Register Item: LCD_DR7  -------------------------------------
+// SVD Line: 18875
+
+//  <item> SFDITEM_REG__LCD_DR7
+//    <name> DR7 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005017) LCD Display Data Register 7 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR7 >> 0) & 0xFFFFFFFF), ((LCD_DR7 = (LCD_DR7 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR8  ---------------------------------
+// SVD Line: 18883
+
+unsigned char LCD_DR8 __AT (0x40005018);
+
+
+
+// ---------------------------------  Register Item: LCD_DR8  -------------------------------------
+// SVD Line: 18883
+
+//  <item> SFDITEM_REG__LCD_DR8
+//    <name> DR8 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005018) LCD Display Data Register 8 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR8 >> 0) & 0xFFFFFFFF), ((LCD_DR8 = (LCD_DR8 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR9  ---------------------------------
+// SVD Line: 18891
+
+unsigned char LCD_DR9 __AT (0x40005019);
+
+
+
+// ---------------------------------  Register Item: LCD_DR9  -------------------------------------
+// SVD Line: 18891
+
+//  <item> SFDITEM_REG__LCD_DR9
+//    <name> DR9 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005019) LCD Display Data Register 9 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR9 >> 0) & 0xFFFFFFFF), ((LCD_DR9 = (LCD_DR9 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR10  --------------------------------
+// SVD Line: 18899
+
+unsigned char LCD_DR10 __AT (0x4000501A);
+
+
+
+// ---------------------------------  Register Item: LCD_DR10  ------------------------------------
+// SVD Line: 18899
+
+//  <item> SFDITEM_REG__LCD_DR10
+//    <name> DR10 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000501A) LCD Display Data Register 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR10 >> 0) & 0xFFFFFFFF), ((LCD_DR10 = (LCD_DR10 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR11  --------------------------------
+// SVD Line: 18907
+
+unsigned char LCD_DR11 __AT (0x4000501B);
+
+
+
+// ---------------------------------  Register Item: LCD_DR11  ------------------------------------
+// SVD Line: 18907
+
+//  <item> SFDITEM_REG__LCD_DR11
+//    <name> DR11 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000501B) LCD Display Data Register 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR11 >> 0) & 0xFFFFFFFF), ((LCD_DR11 = (LCD_DR11 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR12  --------------------------------
+// SVD Line: 18915
+
+unsigned char LCD_DR12 __AT (0x4000501C);
+
+
+
+// ---------------------------------  Register Item: LCD_DR12  ------------------------------------
+// SVD Line: 18915
+
+//  <item> SFDITEM_REG__LCD_DR12
+//    <name> DR12 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000501C) LCD Display Data Register 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR12 >> 0) & 0xFFFFFFFF), ((LCD_DR12 = (LCD_DR12 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR13  --------------------------------
+// SVD Line: 18923
+
+unsigned char LCD_DR13 __AT (0x4000501D);
+
+
+
+// ---------------------------------  Register Item: LCD_DR13  ------------------------------------
+// SVD Line: 18923
+
+//  <item> SFDITEM_REG__LCD_DR13
+//    <name> DR13 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000501D) LCD Display Data Register 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR13 >> 0) & 0xFFFFFFFF), ((LCD_DR13 = (LCD_DR13 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR14  --------------------------------
+// SVD Line: 18931
+
+unsigned char LCD_DR14 __AT (0x4000501E);
+
+
+
+// ---------------------------------  Register Item: LCD_DR14  ------------------------------------
+// SVD Line: 18931
+
+//  <item> SFDITEM_REG__LCD_DR14
+//    <name> DR14 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000501E) LCD Display Data Register 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR14 >> 0) & 0xFFFFFFFF), ((LCD_DR14 = (LCD_DR14 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR15  --------------------------------
+// SVD Line: 18939
+
+unsigned char LCD_DR15 __AT (0x4000501F);
+
+
+
+// ---------------------------------  Register Item: LCD_DR15  ------------------------------------
+// SVD Line: 18939
+
+//  <item> SFDITEM_REG__LCD_DR15
+//    <name> DR15 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000501F) LCD Display Data Register 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR15 >> 0) & 0xFFFFFFFF), ((LCD_DR15 = (LCD_DR15 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR16  --------------------------------
+// SVD Line: 18947
+
+unsigned char LCD_DR16 __AT (0x40005020);
+
+
+
+// ---------------------------------  Register Item: LCD_DR16  ------------------------------------
+// SVD Line: 18947
+
+//  <item> SFDITEM_REG__LCD_DR16
+//    <name> DR16 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005020) LCD Display Data Register 16 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR16 >> 0) & 0xFFFFFFFF), ((LCD_DR16 = (LCD_DR16 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR17  --------------------------------
+// SVD Line: 18955
+
+unsigned char LCD_DR17 __AT (0x40005021);
+
+
+
+// ---------------------------------  Register Item: LCD_DR17  ------------------------------------
+// SVD Line: 18955
+
+//  <item> SFDITEM_REG__LCD_DR17
+//    <name> DR17 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005021) LCD Display Data Register 17 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR17 >> 0) & 0xFFFFFFFF), ((LCD_DR17 = (LCD_DR17 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR18  --------------------------------
+// SVD Line: 18963
+
+unsigned char LCD_DR18 __AT (0x40005022);
+
+
+
+// ---------------------------------  Register Item: LCD_DR18  ------------------------------------
+// SVD Line: 18963
+
+//  <item> SFDITEM_REG__LCD_DR18
+//    <name> DR18 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005022) LCD Display Data Register 18 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR18 >> 0) & 0xFFFFFFFF), ((LCD_DR18 = (LCD_DR18 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR19  --------------------------------
+// SVD Line: 18971
+
+unsigned char LCD_DR19 __AT (0x40005023);
+
+
+
+// ---------------------------------  Register Item: LCD_DR19  ------------------------------------
+// SVD Line: 18971
+
+//  <item> SFDITEM_REG__LCD_DR19
+//    <name> DR19 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005023) LCD Display Data Register 19 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR19 >> 0) & 0xFFFFFFFF), ((LCD_DR19 = (LCD_DR19 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR20  --------------------------------
+// SVD Line: 18979
+
+unsigned char LCD_DR20 __AT (0x40005024);
+
+
+
+// ---------------------------------  Register Item: LCD_DR20  ------------------------------------
+// SVD Line: 18979
+
+//  <item> SFDITEM_REG__LCD_DR20
+//    <name> DR20 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005024) LCD Display Data Register 20 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR20 >> 0) & 0xFFFFFFFF), ((LCD_DR20 = (LCD_DR20 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR21  --------------------------------
+// SVD Line: 18987
+
+unsigned char LCD_DR21 __AT (0x40005025);
+
+
+
+// ---------------------------------  Register Item: LCD_DR21  ------------------------------------
+// SVD Line: 18987
+
+//  <item> SFDITEM_REG__LCD_DR21
+//    <name> DR21 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005025) LCD Display Data Register 21 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR21 >> 0) & 0xFFFFFFFF), ((LCD_DR21 = (LCD_DR21 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR22  --------------------------------
+// SVD Line: 18995
+
+unsigned char LCD_DR22 __AT (0x40005026);
+
+
+
+// ---------------------------------  Register Item: LCD_DR22  ------------------------------------
+// SVD Line: 18995
+
+//  <item> SFDITEM_REG__LCD_DR22
+//    <name> DR22 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005026) LCD Display Data Register 22 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR22 >> 0) & 0xFFFFFFFF), ((LCD_DR22 = (LCD_DR22 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR23  --------------------------------
+// SVD Line: 19003
+
+unsigned char LCD_DR23 __AT (0x40005027);
+
+
+
+// ---------------------------------  Register Item: LCD_DR23  ------------------------------------
+// SVD Line: 19003
+
+//  <item> SFDITEM_REG__LCD_DR23
+//    <name> DR23 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005027) LCD Display Data Register 23 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR23 >> 0) & 0xFFFFFFFF), ((LCD_DR23 = (LCD_DR23 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR24  --------------------------------
+// SVD Line: 19011
+
+unsigned char LCD_DR24 __AT (0x40005028);
+
+
+
+// ---------------------------------  Register Item: LCD_DR24  ------------------------------------
+// SVD Line: 19011
+
+//  <item> SFDITEM_REG__LCD_DR24
+//    <name> DR24 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005028) LCD Display Data Register 24 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR24 >> 0) & 0xFFFFFFFF), ((LCD_DR24 = (LCD_DR24 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR25  --------------------------------
+// SVD Line: 19019
+
+unsigned char LCD_DR25 __AT (0x40005029);
+
+
+
+// ---------------------------------  Register Item: LCD_DR25  ------------------------------------
+// SVD Line: 19019
+
+//  <item> SFDITEM_REG__LCD_DR25
+//    <name> DR25 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005029) LCD Display Data Register 25 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR25 >> 0) & 0xFFFFFFFF), ((LCD_DR25 = (LCD_DR25 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR26  --------------------------------
+// SVD Line: 19027
+
+unsigned char LCD_DR26 __AT (0x4000502A);
+
+
+
+// ---------------------------------  Register Item: LCD_DR26  ------------------------------------
+// SVD Line: 19027
+
+//  <item> SFDITEM_REG__LCD_DR26
+//    <name> DR26 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000502A) LCD Display Data Register 26 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR26 >> 0) & 0xFFFFFFFF), ((LCD_DR26 = (LCD_DR26 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR27  --------------------------------
+// SVD Line: 19035
+
+unsigned char LCD_DR27 __AT (0x4000502B);
+
+
+
+// ---------------------------------  Register Item: LCD_DR27  ------------------------------------
+// SVD Line: 19035
+
+//  <item> SFDITEM_REG__LCD_DR27
+//    <name> DR27 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000502B) LCD Display Data Register 27 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR27 >> 0) & 0xFFFFFFFF), ((LCD_DR27 = (LCD_DR27 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR28  --------------------------------
+// SVD Line: 19043
+
+unsigned char LCD_DR28 __AT (0x4000502C);
+
+
+
+// ---------------------------------  Register Item: LCD_DR28  ------------------------------------
+// SVD Line: 19043
+
+//  <item> SFDITEM_REG__LCD_DR28
+//    <name> DR28 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000502C) LCD Display Data Register 28 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR28 >> 0) & 0xFFFFFFFF), ((LCD_DR28 = (LCD_DR28 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR29  --------------------------------
+// SVD Line: 19051
+
+unsigned char LCD_DR29 __AT (0x4000502D);
+
+
+
+// ---------------------------------  Register Item: LCD_DR29  ------------------------------------
+// SVD Line: 19051
+
+//  <item> SFDITEM_REG__LCD_DR29
+//    <name> DR29 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000502D) LCD Display Data Register 29 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR29 >> 0) & 0xFFFFFFFF), ((LCD_DR29 = (LCD_DR29 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR30  --------------------------------
+// SVD Line: 19059
+
+unsigned char LCD_DR30 __AT (0x4000502E);
+
+
+
+// ---------------------------------  Register Item: LCD_DR30  ------------------------------------
+// SVD Line: 19059
+
+//  <item> SFDITEM_REG__LCD_DR30
+//    <name> DR30 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000502E) LCD Display Data Register 30 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR30 >> 0) & 0xFFFFFFFF), ((LCD_DR30 = (LCD_DR30 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR31  --------------------------------
+// SVD Line: 19067
+
+unsigned char LCD_DR31 __AT (0x4000502F);
+
+
+
+// ---------------------------------  Register Item: LCD_DR31  ------------------------------------
+// SVD Line: 19067
+
+//  <item> SFDITEM_REG__LCD_DR31
+//    <name> DR31 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000502F) LCD Display Data Register 31 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR31 >> 0) & 0xFFFFFFFF), ((LCD_DR31 = (LCD_DR31 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR32  --------------------------------
+// SVD Line: 19075
+
+unsigned char LCD_DR32 __AT (0x40005030);
+
+
+
+// ---------------------------------  Register Item: LCD_DR32  ------------------------------------
+// SVD Line: 19075
+
+//  <item> SFDITEM_REG__LCD_DR32
+//    <name> DR32 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005030) LCD Display Data Register 32 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR32 >> 0) & 0xFFFFFFFF), ((LCD_DR32 = (LCD_DR32 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR33  --------------------------------
+// SVD Line: 19083
+
+unsigned char LCD_DR33 __AT (0x40005031);
+
+
+
+// ---------------------------------  Register Item: LCD_DR33  ------------------------------------
+// SVD Line: 19083
+
+//  <item> SFDITEM_REG__LCD_DR33
+//    <name> DR33 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005031) LCD Display Data Register 33 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR33 >> 0) & 0xFFFFFFFF), ((LCD_DR33 = (LCD_DR33 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR34  --------------------------------
+// SVD Line: 19091
+
+unsigned char LCD_DR34 __AT (0x40005032);
+
+
+
+// ---------------------------------  Register Item: LCD_DR34  ------------------------------------
+// SVD Line: 19091
+
+//  <item> SFDITEM_REG__LCD_DR34
+//    <name> DR34 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005032) LCD Display Data Register 34 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR34 >> 0) & 0xFFFFFFFF), ((LCD_DR34 = (LCD_DR34 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR35  --------------------------------
+// SVD Line: 19099
+
+unsigned char LCD_DR35 __AT (0x40005033);
+
+
+
+// ---------------------------------  Register Item: LCD_DR35  ------------------------------------
+// SVD Line: 19099
+
+//  <item> SFDITEM_REG__LCD_DR35
+//    <name> DR35 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005033) LCD Display Data Register 35 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR35 >> 0) & 0xFFFFFFFF), ((LCD_DR35 = (LCD_DR35 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR36  --------------------------------
+// SVD Line: 19107
+
+unsigned char LCD_DR36 __AT (0x40005034);
+
+
+
+// ---------------------------------  Register Item: LCD_DR36  ------------------------------------
+// SVD Line: 19107
+
+//  <item> SFDITEM_REG__LCD_DR36
+//    <name> DR36 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005034) LCD Display Data Register 36 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR36 >> 0) & 0xFFFFFFFF), ((LCD_DR36 = (LCD_DR36 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR37  --------------------------------
+// SVD Line: 19115
+
+unsigned char LCD_DR37 __AT (0x40005035);
+
+
+
+// ---------------------------------  Register Item: LCD_DR37  ------------------------------------
+// SVD Line: 19115
+
+//  <item> SFDITEM_REG__LCD_DR37
+//    <name> DR37 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005035) LCD Display Data Register 37 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR37 >> 0) & 0xFFFFFFFF), ((LCD_DR37 = (LCD_DR37 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR38  --------------------------------
+// SVD Line: 19123
+
+unsigned char LCD_DR38 __AT (0x40005036);
+
+
+
+// ---------------------------------  Register Item: LCD_DR38  ------------------------------------
+// SVD Line: 19123
+
+//  <item> SFDITEM_REG__LCD_DR38
+//    <name> DR38 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005036) LCD Display Data Register 38 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR38 >> 0) & 0xFFFFFFFF), ((LCD_DR38 = (LCD_DR38 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR39  --------------------------------
+// SVD Line: 19131
+
+unsigned char LCD_DR39 __AT (0x40005037);
+
+
+
+// ---------------------------------  Register Item: LCD_DR39  ------------------------------------
+// SVD Line: 19131
+
+//  <item> SFDITEM_REG__LCD_DR39
+//    <name> DR39 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005037) LCD Display Data Register 39 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR39 >> 0) & 0xFFFFFFFF), ((LCD_DR39 = (LCD_DR39 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR40  --------------------------------
+// SVD Line: 19139
+
+unsigned char LCD_DR40 __AT (0x40005038);
+
+
+
+// ---------------------------------  Register Item: LCD_DR40  ------------------------------------
+// SVD Line: 19139
+
+//  <item> SFDITEM_REG__LCD_DR40
+//    <name> DR40 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005038) LCD Display Data Register 40 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR40 >> 0) & 0xFFFFFFFF), ((LCD_DR40 = (LCD_DR40 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR41  --------------------------------
+// SVD Line: 19147
+
+unsigned char LCD_DR41 __AT (0x40005039);
+
+
+
+// ---------------------------------  Register Item: LCD_DR41  ------------------------------------
+// SVD Line: 19147
+
+//  <item> SFDITEM_REG__LCD_DR41
+//    <name> DR41 </name>
+//    <i> [Bits 7..0] RW (@ 0x40005039) LCD Display Data Register 41 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR41 >> 0) & 0xFFFFFFFF), ((LCD_DR41 = (LCD_DR41 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR42  --------------------------------
+// SVD Line: 19155
+
+unsigned char LCD_DR42 __AT (0x4000503A);
+
+
+
+// ---------------------------------  Register Item: LCD_DR42  ------------------------------------
+// SVD Line: 19155
+
+//  <item> SFDITEM_REG__LCD_DR42
+//    <name> DR42 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000503A) LCD Display Data Register 42 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR42 >> 0) & 0xFFFFFFFF), ((LCD_DR42 = (LCD_DR42 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Register Item Address: LCD_DR43  --------------------------------
+// SVD Line: 19163
+
+unsigned char LCD_DR43 __AT (0x4000503B);
+
+
+
+// ---------------------------------  Register Item: LCD_DR43  ------------------------------------
+// SVD Line: 19163
+
+//  <item> SFDITEM_REG__LCD_DR43
+//    <name> DR43 </name>
+//    <i> [Bits 7..0] RW (@ 0x4000503B) LCD Display Data Register 43 </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((LCD_DR43 >> 0) & 0xFFFFFFFF), ((LCD_DR43 = (LCD_DR43 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------------  Peripheral View: LCD  --------------------------------------
+// SVD Line: 18499
+
+//  <view> LCD
+//    <name> LCD </name>
+//    <item> SFDITEM_REG__LCD_CR </item>
+//    <item> SFDITEM_REG__LCD_BCCR </item>
+//    <item> SFDITEM_REG__LCD_DR0 </item>
+//    <item> SFDITEM_REG__LCD_DR1 </item>
+//    <item> SFDITEM_REG__LCD_DR2 </item>
+//    <item> SFDITEM_REG__LCD_DR3 </item>
+//    <item> SFDITEM_REG__LCD_DR4 </item>
+//    <item> SFDITEM_REG__LCD_DR5 </item>
+//    <item> SFDITEM_REG__LCD_DR6 </item>
+//    <item> SFDITEM_REG__LCD_DR7 </item>
+//    <item> SFDITEM_REG__LCD_DR8 </item>
+//    <item> SFDITEM_REG__LCD_DR9 </item>
+//    <item> SFDITEM_REG__LCD_DR10 </item>
+//    <item> SFDITEM_REG__LCD_DR11 </item>
+//    <item> SFDITEM_REG__LCD_DR12 </item>
+//    <item> SFDITEM_REG__LCD_DR13 </item>
+//    <item> SFDITEM_REG__LCD_DR14 </item>
+//    <item> SFDITEM_REG__LCD_DR15 </item>
+//    <item> SFDITEM_REG__LCD_DR16 </item>
+//    <item> SFDITEM_REG__LCD_DR17 </item>
+//    <item> SFDITEM_REG__LCD_DR18 </item>
+//    <item> SFDITEM_REG__LCD_DR19 </item>
+//    <item> SFDITEM_REG__LCD_DR20 </item>
+//    <item> SFDITEM_REG__LCD_DR21 </item>
+//    <item> SFDITEM_REG__LCD_DR22 </item>
+//    <item> SFDITEM_REG__LCD_DR23 </item>
+//    <item> SFDITEM_REG__LCD_DR24 </item>
+//    <item> SFDITEM_REG__LCD_DR25 </item>
+//    <item> SFDITEM_REG__LCD_DR26 </item>
+//    <item> SFDITEM_REG__LCD_DR27 </item>
+//    <item> SFDITEM_REG__LCD_DR28 </item>
+//    <item> SFDITEM_REG__LCD_DR29 </item>
+//    <item> SFDITEM_REG__LCD_DR30 </item>
+//    <item> SFDITEM_REG__LCD_DR31 </item>
+//    <item> SFDITEM_REG__LCD_DR32 </item>
+//    <item> SFDITEM_REG__LCD_DR33 </item>
+//    <item> SFDITEM_REG__LCD_DR34 </item>
+//    <item> SFDITEM_REG__LCD_DR35 </item>
+//    <item> SFDITEM_REG__LCD_DR36 </item>
+//    <item> SFDITEM_REG__LCD_DR37 </item>
+//    <item> SFDITEM_REG__LCD_DR38 </item>
+//    <item> SFDITEM_REG__LCD_DR39 </item>
+//    <item> SFDITEM_REG__LCD_DR40 </item>
+//    <item> SFDITEM_REG__LCD_DR41 </item>
+//    <item> SFDITEM_REG__LCD_DR42 </item>
+//    <item> SFDITEM_REG__LCD_DR43 </item>
+//  </view>
+//  
+
+
+// ------------------------------  Register Item Address: CRC_CR  ---------------------------------
+// SVD Line: 19187
+
+unsigned int CRC_CR __AT (0x30001000);
+
+
+
+// ---------------------------------  Field Item: CRC_CR_MODS  ------------------------------------
+// SVD Line: 19196
+
+//  <item> SFDITEM_FIELD__CRC_CR_MODS
+//    <name> MODS </name>
+//    <rw> 
+//    <i> [Bit 7] RW (@ 0x30001000) \nUser/Auto Mode Selection\n0 : UserMode = User Mode (Calculate every data written to the CRC_IN register)\n1 : AutoMode = Auto Mode (Calculate till CRC_SADR == CRC_EADR) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) CRC_CR ) </loc>
+//      <o.7..7> MODS
+//        <0=> 0: UserMode = User Mode (Calculate every data written to the CRC_IN register)
+//        <1=> 1: AutoMode = Auto Mode (Calculate till CRC_SADR == CRC_EADR)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: CRC_CR_RLTCLR  -----------------------------------
+// SVD Line: 19214
+
+//  <item> SFDITEM_FIELD__CRC_CR_RLTCLR
+//    <name> RLTCLR </name>
+//    <rw> 
+//    <i> [Bit 6] RW (@ 0x30001000) \nCRC/Checksum Result Data Register (CRCRLT) Initialization\n0 : NoEffect = No effect.\n1 : Init = Initialize the CRC_RLT register with the value of CRC_INIT. (This bit is automatically cleared to '0' after operation.) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) CRC_CR ) </loc>
+//      <o.6..6> RLTCLR
+//        <0=> 0: NoEffect = No effect.
+//        <1=> 1: Init = Initialize the CRC_RLT register with the value of CRC_INIT. (This bit is automatically cleared to '0' after operation.)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: CRC_CR_MDSEL  ------------------------------------
+// SVD Line: 19232
+
+//  <item> SFDITEM_FIELD__CRC_CR_MDSEL
+//    <name> MDSEL </name>
+//    <rw> 
+//    <i> [Bit 5] RW (@ 0x30001000) \nCRC/Checksum Selection\n0 : CRC = Select CRC.\n1 : Checksum = Select Checksum. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) CRC_CR ) </loc>
+//      <o.5..5> MDSEL
+//        <0=> 0: CRC = Select CRC.
+//        <1=> 1: Checksum = Select Checksum.
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: CRC_CR_POLYS  ------------------------------------
+// SVD Line: 19250
+
+//  <item> SFDITEM_FIELD__CRC_CR_POLYS
+//    <name> POLYS </name>
+//    <rw> 
+//    <i> [Bit 4] RW (@ 0x30001000) \nPolynomial Selection (CRC only)\n0 : CRC16_CCITT = CRC16-CCITT (G1(x) = x16 + x12 + x5 + 1)\n1 : CRC16 = CRC16 (G2(x) = x16 + x15 + x2 + 1) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) CRC_CR ) </loc>
+//      <o.4..4> POLYS
+//        <0=> 0: CRC16_CCITT = CRC16-CCITT (G1(x) = x16 + x12 + x5 + 1)
+//        <1=> 1: CRC16 = CRC16 (G2(x) = x16 + x15 + x2 + 1)
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: CRC_CR_SARINC  -----------------------------------
+// SVD Line: 19268
+
+//  <item> SFDITEM_FIELD__CRC_CR_SARINC
+//    <name> SARINC </name>
+//    <rw> 
+//    <i> [Bit 3] RW (@ 0x30001000) \nCRC/Checksum Start Address Auto Increment Control (User mode only)\n0 : Disable = No effect.\n1 : Enable = The CRC/Checksum start address register is incremented as the selected input size every writing to the CRC_IN register. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) CRC_CR ) </loc>
+//      <o.3..3> SARINC
+//        <0=> 0: Disable = No effect.
+//        <1=> 1: Enable = The CRC/Checksum start address register is incremented as the selected input size every writing to the CRC_IN register.
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Field Item: CRC_CR_FIRSTBS  -----------------------------------
+// SVD Line: 19286
+
+//  <item> SFDITEM_FIELD__CRC_CR_FIRSTBS
+//    <name> FIRSTBS </name>
+//    <rw> 
+//    <i> [Bit 1] RW (@ 0x30001000) \nFirst Shifted-in Selection (CRC only)\n0 : msbFirst = msb first\n1 : lsbFirst = lsb first </i>
+//    <combo> 
+//      <loc> ( (unsigned int) CRC_CR ) </loc>
+//      <o.1..1> FIRSTBS
+//        <0=> 0: msbFirst = msb first
+//        <1=> 1: lsbFirst = lsb first
+//    </combo>
+//  </item>
+//  
+
+
+// --------------------------------  Field Item: CRC_CR_CRCRUN  -----------------------------------
+// SVD Line: 19304
+
+//  <item> SFDITEM_FIELD__CRC_CR_CRCRUN
+//    <name> CRCRUN </name>
+//    <rw> 
+//    <i> [Bit 0] RW (@ 0x30001000) \nCRC/Checksum Start Control and Busy\n0 : Stop = Not busy. The CRC operation can be finished by writing '0' to this bit while running.\n1 : Start = Start CRC operation. This bit is automatically cleared to '0' when the value of CRC_SADR register reaches the value of CRC_EADR register. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) CRC_CR ) </loc>
+//      <o.0..0> CRCRUN
+//        <0=> 0: Stop = Not busy. The CRC operation can be finished by writing '0' to this bit while running.
+//        <1=> 1: Start = Start CRC operation. This bit is automatically cleared to '0' when the value of CRC_SADR register reaches the value of CRC_EADR register.
+//    </combo>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: CRC_CR  -------------------------------------
+// SVD Line: 19187
+
+//  <rtree> SFDITEM_REG__CRC_CR
+//    <name> CR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30001000) CRC/Checksum Control Register </i>
+//    <loc> ( (unsigned int)((CRC_CR >> 0) & 0xFFFFFFFF), ((CRC_CR = (CRC_CR & ~(0xFBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__CRC_CR_MODS </item>
+//    <item> SFDITEM_FIELD__CRC_CR_RLTCLR </item>
+//    <item> SFDITEM_FIELD__CRC_CR_MDSEL </item>
+//    <item> SFDITEM_FIELD__CRC_CR_POLYS </item>
+//    <item> SFDITEM_FIELD__CRC_CR_SARINC </item>
+//    <item> SFDITEM_FIELD__CRC_CR_FIRSTBS </item>
+//    <item> SFDITEM_FIELD__CRC_CR_CRCRUN </item>
+//  </rtree>
+//  
+
+
+// ------------------------------  Register Item Address: CRC_IN  ---------------------------------
+// SVD Line: 19324
+
+unsigned int CRC_IN __AT (0x30001004);
+
+
+
+// --------------------------------  Field Item: CRC_IN_INDATA  -----------------------------------
+// SVD Line: 19333
+
+//  <item> SFDITEM_FIELD__CRC_IN_INDATA
+//    <name> INDATA </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30001004) CRC Input Data </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((CRC_IN >> 0) & 0xFFFFFFFF), ((CRC_IN = (CRC_IN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: CRC_IN  -------------------------------------
+// SVD Line: 19324
+
+//  <rtree> SFDITEM_REG__CRC_IN
+//    <name> IN </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30001004) CRC/Checksum Input Data Register </i>
+//    <loc> ( (unsigned int)((CRC_IN >> 0) & 0xFFFFFFFF), ((CRC_IN = (CRC_IN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__CRC_IN_INDATA </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: CRC_RLT  ---------------------------------
+// SVD Line: 19341
+
+unsigned int CRC_RLT __AT (0x30001008);
+
+
+
+// -------------------------------  Field Item: CRC_RLT_RLTDATA  ----------------------------------
+// SVD Line: 19350
+
+//  <item> SFDITEM_FIELD__CRC_RLT_RLTDATA
+//    <name> RLTDATA </name>
+//    <r> 
+//    <i> [Bits 15..0] RO (@ 0x30001008) CRC Result Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((CRC_RLT >> 0) & 0xFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------------  Register RTree: CRC_RLT  ------------------------------------
+// SVD Line: 19341
+
+//  <rtree> SFDITEM_REG__CRC_RLT
+//    <name> RLT </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x30001008) CRC/Checksum Result Data Register </i>
+//    <loc> ( (unsigned int)((CRC_RLT >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__CRC_RLT_RLTDATA </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: CRC_INIT  --------------------------------
+// SVD Line: 19358
+
+unsigned int CRC_INIT __AT (0x3000100C);
+
+
+
+// ------------------------------  Field Item: CRC_INIT_INIDATA  ----------------------------------
+// SVD Line: 19367
+
+//  <item> SFDITEM_FIELD__CRC_INIT_INIDATA
+//    <name> INIDATA </name>
+//    <rw> 
+//    <i> [Bits 15..0] RW (@ 0x3000100C) CRC Initial Data </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((CRC_INIT >> 0) & 0xFFFF), ((CRC_INIT = (CRC_INIT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: CRC_INIT  ------------------------------------
+// SVD Line: 19358
+
+//  <rtree> SFDITEM_REG__CRC_INIT
+//    <name> INIT </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x3000100C) CRC/Checksum Initial Data Register </i>
+//    <loc> ( (unsigned int)((CRC_INIT >> 0) & 0xFFFFFFFF), ((CRC_INIT = (CRC_INIT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__CRC_INIT_INIDATA </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: CRC_SADR  --------------------------------
+// SVD Line: 19375
+
+unsigned int CRC_SADR __AT (0x30001010);
+
+
+
+// --------------------------------  Field Item: CRC_SADR_SADR  -----------------------------------
+// SVD Line: 19384
+
+//  <item> SFDITEM_FIELD__CRC_SADR_SADR
+//    <name> SADR </name>
+//    <rw> 
+//    <i> [Bits 31..2] RW (@ 0x30001010) CRC Start Address </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((CRC_SADR >> 2) & 0x3FFFFFFF), ((CRC_SADR = (CRC_SADR & ~(0x3FFFFFFFUL << 2 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFFF) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: CRC_SADR  ------------------------------------
+// SVD Line: 19375
+
+//  <rtree> SFDITEM_REG__CRC_SADR
+//    <name> SADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30001010) CRC/Checksum Start Address Register </i>
+//    <loc> ( (unsigned int)((CRC_SADR >> 0) & 0xFFFFFFFF), ((CRC_SADR = (CRC_SADR & ~(0xFFFFFFFCUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFC) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__CRC_SADR_SADR </item>
+//  </rtree>
+//  
+
+
+// -----------------------------  Register Item Address: CRC_EADR  --------------------------------
+// SVD Line: 19392
+
+unsigned int CRC_EADR __AT (0x30001014);
+
+
+
+// --------------------------------  Field Item: CRC_EADR_EADR  -----------------------------------
+// SVD Line: 19401
+
+//  <item> SFDITEM_FIELD__CRC_EADR_EADR
+//    <name> EADR </name>
+//    <rw> 
+//    <i> [Bits 31..2] RW (@ 0x30001014) CRC End Address </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((CRC_EADR >> 2) & 0x3FFFFFFF), ((CRC_EADR = (CRC_EADR & ~(0x3FFFFFFFUL << 2 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFFF) << 2 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------------  Register RTree: CRC_EADR  ------------------------------------
+// SVD Line: 19392
+
+//  <rtree> SFDITEM_REG__CRC_EADR
+//    <name> EADR </name>
+//    <rw> 
+//    <i> [Bits 31..0] RW (@ 0x30001014) CRC/Checksum End Address Register </i>
+//    <loc> ( (unsigned int)((CRC_EADR >> 0) & 0xFFFFFFFF), ((CRC_EADR = (CRC_EADR & ~(0xFFFFFFFCUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFC) << 0 ) ) )) </loc>
+//    <item> SFDITEM_FIELD__CRC_EADR_EADR </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: CRC  --------------------------------------
+// SVD Line: 19173
+
+//  <view> CRC
+//    <name> CRC </name>
+//    <item> SFDITEM_REG__CRC_CR </item>
+//    <item> SFDITEM_REG__CRC_IN </item>
+//    <item> SFDITEM_REG__CRC_RLT </item>
+//    <item> SFDITEM_REG__CRC_INIT </item>
+//    <item> SFDITEM_REG__CRC_SADR </item>
+//    <item> SFDITEM_REG__CRC_EADR </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM00  -------------------------------
+// SVD Line: 19425
+
+unsigned int COA0_TRIM00 __AT (0x1FFFF000);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM00  -----------------------------------
+// SVD Line: 19425
+
+//  <item> SFDITEM_REG__COA0_TRIM00
+//    <name> TRIM00 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF000) System Related Trim Value 00 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM00 >> 0) & 0xFFFFFFFF), ((COA0_TRIM00 = (COA0_TRIM00 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM01  -------------------------------
+// SVD Line: 19434
+
+unsigned int COA0_TRIM01 __AT (0x1FFFF004);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM01  -----------------------------------
+// SVD Line: 19434
+
+//  <item> SFDITEM_REG__COA0_TRIM01
+//    <name> TRIM01 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF004) System Related Trim Value 01 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM01 >> 0) & 0xFFFFFFFF), ((COA0_TRIM01 = (COA0_TRIM01 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM02  -------------------------------
+// SVD Line: 19442
+
+unsigned int COA0_TRIM02 __AT (0x1FFFF008);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM02  -----------------------------------
+// SVD Line: 19442
+
+//  <item> SFDITEM_REG__COA0_TRIM02
+//    <name> TRIM02 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF008) System Related Trim Value 02 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM02 >> 0) & 0xFFFFFFFF), ((COA0_TRIM02 = (COA0_TRIM02 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM03  -------------------------------
+// SVD Line: 19450
+
+unsigned int COA0_TRIM03 __AT (0x1FFFF00C);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM03  -----------------------------------
+// SVD Line: 19450
+
+//  <item> SFDITEM_REG__COA0_TRIM03
+//    <name> TRIM03 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF00C) System Related Trim Value 03 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM03 >> 0) & 0xFFFFFFFF), ((COA0_TRIM03 = (COA0_TRIM03 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM04  -------------------------------
+// SVD Line: 19458
+
+unsigned int COA0_TRIM04 __AT (0x1FFFF010);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM04  -----------------------------------
+// SVD Line: 19458
+
+//  <item> SFDITEM_REG__COA0_TRIM04
+//    <name> TRIM04 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF010) System Related Trim Value 04 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM04 >> 0) & 0xFFFFFFFF), ((COA0_TRIM04 = (COA0_TRIM04 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM05  -------------------------------
+// SVD Line: 19466
+
+unsigned int COA0_TRIM05 __AT (0x1FFFF014);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM05  -----------------------------------
+// SVD Line: 19466
+
+//  <item> SFDITEM_REG__COA0_TRIM05
+//    <name> TRIM05 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF014) System Related Trim Value 05 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM05 >> 0) & 0xFFFFFFFF), ((COA0_TRIM05 = (COA0_TRIM05 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM06  -------------------------------
+// SVD Line: 19474
+
+unsigned int COA0_TRIM06 __AT (0x1FFFF018);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM06  -----------------------------------
+// SVD Line: 19474
+
+//  <item> SFDITEM_REG__COA0_TRIM06
+//    <name> TRIM06 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF018) System Related Trim Value 06 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM06 >> 0) & 0xFFFFFFFF), ((COA0_TRIM06 = (COA0_TRIM06 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM07  -------------------------------
+// SVD Line: 19482
+
+unsigned int COA0_TRIM07 __AT (0x1FFFF01C);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM07  -----------------------------------
+// SVD Line: 19482
+
+//  <item> SFDITEM_REG__COA0_TRIM07
+//    <name> TRIM07 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF01C) System Related Trim Value 07 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM07 >> 0) & 0xFFFFFFFF), ((COA0_TRIM07 = (COA0_TRIM07 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM08  -------------------------------
+// SVD Line: 19490
+
+unsigned int COA0_TRIM08 __AT (0x1FFFF020);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM08  -----------------------------------
+// SVD Line: 19490
+
+//  <item> SFDITEM_REG__COA0_TRIM08
+//    <name> TRIM08 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF020) System Related Trim Value 08 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM08 >> 0) & 0xFFFFFFFF), ((COA0_TRIM08 = (COA0_TRIM08 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM09  -------------------------------
+// SVD Line: 19498
+
+unsigned int COA0_TRIM09 __AT (0x1FFFF024);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM09  -----------------------------------
+// SVD Line: 19498
+
+//  <item> SFDITEM_REG__COA0_TRIM09
+//    <name> TRIM09 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF024) System Related Trim Value 09 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM09 >> 0) & 0xFFFFFFFF), ((COA0_TRIM09 = (COA0_TRIM09 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM10  -------------------------------
+// SVD Line: 19506
+
+unsigned int COA0_TRIM10 __AT (0x1FFFF028);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM10  -----------------------------------
+// SVD Line: 19506
+
+//  <item> SFDITEM_REG__COA0_TRIM10
+//    <name> TRIM10 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF028) System Related Trim Value 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM10 >> 0) & 0xFFFFFFFF), ((COA0_TRIM10 = (COA0_TRIM10 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM11  -------------------------------
+// SVD Line: 19514
+
+unsigned int COA0_TRIM11 __AT (0x1FFFF02C);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM11  -----------------------------------
+// SVD Line: 19514
+
+//  <item> SFDITEM_REG__COA0_TRIM11
+//    <name> TRIM11 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF02C) System Related Trim Value 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM11 >> 0) & 0xFFFFFFFF), ((COA0_TRIM11 = (COA0_TRIM11 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM12  -------------------------------
+// SVD Line: 19522
+
+unsigned int COA0_TRIM12 __AT (0x1FFFF030);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM12  -----------------------------------
+// SVD Line: 19522
+
+//  <item> SFDITEM_REG__COA0_TRIM12
+//    <name> TRIM12 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF030) System Related Trim Value 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM12 >> 0) & 0xFFFFFFFF), ((COA0_TRIM12 = (COA0_TRIM12 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM13  -------------------------------
+// SVD Line: 19530
+
+unsigned int COA0_TRIM13 __AT (0x1FFFF034);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM13  -----------------------------------
+// SVD Line: 19530
+
+//  <item> SFDITEM_REG__COA0_TRIM13
+//    <name> TRIM13 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF034) System Related Trim Value 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM13 >> 0) & 0xFFFFFFFF), ((COA0_TRIM13 = (COA0_TRIM13 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM14  -------------------------------
+// SVD Line: 19538
+
+unsigned int COA0_TRIM14 __AT (0x1FFFF038);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM14  -----------------------------------
+// SVD Line: 19538
+
+//  <item> SFDITEM_REG__COA0_TRIM14
+//    <name> TRIM14 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF038) System Related Trim Value 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM14 >> 0) & 0xFFFFFFFF), ((COA0_TRIM14 = (COA0_TRIM14 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM15  -------------------------------
+// SVD Line: 19546
+
+unsigned int COA0_TRIM15 __AT (0x1FFFF03C);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM15  -----------------------------------
+// SVD Line: 19546
+
+//  <item> SFDITEM_REG__COA0_TRIM15
+//    <name> TRIM15 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF03C) System Related Trim Value 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM15 >> 0) & 0xFFFFFFFF), ((COA0_TRIM15 = (COA0_TRIM15 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM16  -------------------------------
+// SVD Line: 19554
+
+unsigned int COA0_TRIM16 __AT (0x1FFFF040);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM16  -----------------------------------
+// SVD Line: 19554
+
+//  <item> SFDITEM_REG__COA0_TRIM16
+//    <name> TRIM16 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF040) System Related Trim Value 16 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM16 >> 0) & 0xFFFFFFFF), ((COA0_TRIM16 = (COA0_TRIM16 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM17  -------------------------------
+// SVD Line: 19562
+
+unsigned int COA0_TRIM17 __AT (0x1FFFF044);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM17  -----------------------------------
+// SVD Line: 19562
+
+//  <item> SFDITEM_REG__COA0_TRIM17
+//    <name> TRIM17 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF044) System Related Trim Value 17 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM17 >> 0) & 0xFFFFFFFF), ((COA0_TRIM17 = (COA0_TRIM17 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM18  -------------------------------
+// SVD Line: 19570
+
+unsigned int COA0_TRIM18 __AT (0x1FFFF048);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM18  -----------------------------------
+// SVD Line: 19570
+
+//  <item> SFDITEM_REG__COA0_TRIM18
+//    <name> TRIM18 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF048) System Related Trim Value 18 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM18 >> 0) & 0xFFFFFFFF), ((COA0_TRIM18 = (COA0_TRIM18 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM19  -------------------------------
+// SVD Line: 19578
+
+unsigned int COA0_TRIM19 __AT (0x1FFFF04C);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM19  -----------------------------------
+// SVD Line: 19578
+
+//  <item> SFDITEM_REG__COA0_TRIM19
+//    <name> TRIM19 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF04C) System Related Trim Value 19 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM19 >> 0) & 0xFFFFFFFF), ((COA0_TRIM19 = (COA0_TRIM19 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ------------------------  Register Item Address: COA0_CONF_MF1CNFIG  ---------------------------
+// SVD Line: 19586
+
+unsigned int COA0_CONF_MF1CNFIG __AT (0x1FFFF050);
+
+
+
+// --------------------------  Field Item: COA0_CONF_MF1CNFIG_XYCDN  ------------------------------
+// SVD Line: 19594
+
+//  <item> SFDITEM_FIELD__COA0_CONF_MF1CNFIG_XYCDN
+//    <name> XYCDN </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF050) X and Y Coordinates </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_CONF_MF1CNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register RTree: COA0_CONF_MF1CNFIG  -------------------------------
+// SVD Line: 19586
+
+//  <rtree> SFDITEM_REG__COA0_CONF_MF1CNFIG
+//    <name> CONF_MF1CNFIG </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF050) Manufacture Information 1 </i>
+//    <loc> ( (unsigned int)((COA0_CONF_MF1CNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA0_CONF_MF1CNFIG_XYCDN </item>
+//  </rtree>
+//  
+
+
+// ------------------------  Register Item Address: COA0_CONF_MF2CNFIG  ---------------------------
+// SVD Line: 19602
+
+unsigned int COA0_CONF_MF2CNFIG __AT (0x1FFFF054);
+
+
+
+// --------------------------  Field Item: COA0_CONF_MF2CNFIG_LOTNO  ------------------------------
+// SVD Line: 19610
+
+//  <item> SFDITEM_FIELD__COA0_CONF_MF2CNFIG_LOTNO
+//    <name> LOTNO </name>
+//    <r> 
+//    <i> [Bits 31..8] RO (@ 0x1FFFF054) Lot Number [23:0] </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_CONF_MF2CNFIG >> 8) & 0xFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// --------------------------  Field Item: COA0_CONF_MF2CNFIG_WAFNO  ------------------------------
+// SVD Line: 19616
+
+//  <item> SFDITEM_FIELD__COA0_CONF_MF2CNFIG_WAFNO
+//    <name> WAFNO </name>
+//    <r> 
+//    <i> [Bits 7..0] RO (@ 0x1FFFF054) Wafer Number </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((COA0_CONF_MF2CNFIG >> 0) & 0xFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register RTree: COA0_CONF_MF2CNFIG  -------------------------------
+// SVD Line: 19602
+
+//  <rtree> SFDITEM_REG__COA0_CONF_MF2CNFIG
+//    <name> CONF_MF2CNFIG </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF054) Manufacture Information 2 </i>
+//    <loc> ( (unsigned int)((COA0_CONF_MF2CNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA0_CONF_MF2CNFIG_LOTNO </item>
+//    <item> SFDITEM_FIELD__COA0_CONF_MF2CNFIG_WAFNO </item>
+//  </rtree>
+//  
+
+
+// ------------------------  Register Item Address: COA0_CONF_MF3CNFIG  ---------------------------
+// SVD Line: 19624
+
+unsigned int COA0_CONF_MF3CNFIG __AT (0x1FFFF058);
+
+
+
+// --------------------------  Field Item: COA0_CONF_MF3CNFIG_LOTNO  ------------------------------
+// SVD Line: 19632
+
+//  <item> SFDITEM_FIELD__COA0_CONF_MF3CNFIG_LOTNO
+//    <name> LOTNO </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF058) Lot Number [55:24] </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_CONF_MF3CNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register RTree: COA0_CONF_MF3CNFIG  -------------------------------
+// SVD Line: 19624
+
+//  <rtree> SFDITEM_REG__COA0_CONF_MF3CNFIG
+//    <name> CONF_MF3CNFIG </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF058) Manufacture Information 3 </i>
+//    <loc> ( (unsigned int)((COA0_CONF_MF3CNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA0_CONF_MF3CNFIG_LOTNO </item>
+//  </rtree>
+//  
+
+
+// ------------------------  Register Item Address: COA0_CONF_MF4CNFIG  ---------------------------
+// SVD Line: 19640
+
+unsigned int COA0_CONF_MF4CNFIG __AT (0x1FFFF05C);
+
+
+
+// --------------------------  Field Item: COA0_CONF_MF4CNFIG_LOTNO  ------------------------------
+// SVD Line: 19648
+
+//  <item> SFDITEM_FIELD__COA0_CONF_MF4CNFIG_LOTNO
+//    <name> LOTNO </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF05C) Lot Number [87:56] </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_CONF_MF4CNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register RTree: COA0_CONF_MF4CNFIG  -------------------------------
+// SVD Line: 19640
+
+//  <rtree> SFDITEM_REG__COA0_CONF_MF4CNFIG
+//    <name> CONF_MF4CNFIG </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF05C) Manufacture Information 4 </i>
+//    <loc> ( (unsigned int)((COA0_CONF_MF4CNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA0_CONF_MF4CNFIG_LOTNO </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM24  -------------------------------
+// SVD Line: 19656
+
+unsigned int COA0_TRIM24 __AT (0x1FFFF060);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM24  -----------------------------------
+// SVD Line: 19656
+
+//  <item> SFDITEM_REG__COA0_TRIM24
+//    <name> TRIM24 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF060) System Related Trim Value 24 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM24 >> 0) & 0xFFFFFFFF), ((COA0_TRIM24 = (COA0_TRIM24 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM25  -------------------------------
+// SVD Line: 19664
+
+unsigned int COA0_TRIM25 __AT (0x1FFFF064);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM25  -----------------------------------
+// SVD Line: 19664
+
+//  <item> SFDITEM_REG__COA0_TRIM25
+//    <name> TRIM25 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF064) System Related Trim Value 25 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM25 >> 0) & 0xFFFFFFFF), ((COA0_TRIM25 = (COA0_TRIM25 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM26  -------------------------------
+// SVD Line: 19672
+
+unsigned int COA0_TRIM26 __AT (0x1FFFF068);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM26  -----------------------------------
+// SVD Line: 19672
+
+//  <item> SFDITEM_REG__COA0_TRIM26
+//    <name> TRIM26 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF068) System Related Trim Value 26 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM26 >> 0) & 0xFFFFFFFF), ((COA0_TRIM26 = (COA0_TRIM26 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM27  -------------------------------
+// SVD Line: 19680
+
+unsigned int COA0_TRIM27 __AT (0x1FFFF06C);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM27  -----------------------------------
+// SVD Line: 19680
+
+//  <item> SFDITEM_REG__COA0_TRIM27
+//    <name> TRIM27 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF06C) System Related Trim Value 27 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM27 >> 0) & 0xFFFFFFFF), ((COA0_TRIM27 = (COA0_TRIM27 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM28  -------------------------------
+// SVD Line: 19688
+
+unsigned int COA0_TRIM28 __AT (0x1FFFF070);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM28  -----------------------------------
+// SVD Line: 19688
+
+//  <item> SFDITEM_REG__COA0_TRIM28
+//    <name> TRIM28 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF070) System Related Trim Value 28 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM28 >> 0) & 0xFFFFFFFF), ((COA0_TRIM28 = (COA0_TRIM28 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM29  -------------------------------
+// SVD Line: 19696
+
+unsigned int COA0_TRIM29 __AT (0x1FFFF074);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM29  -----------------------------------
+// SVD Line: 19696
+
+//  <item> SFDITEM_REG__COA0_TRIM29
+//    <name> TRIM29 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF074) System Related Trim Value 29 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM29 >> 0) & 0xFFFFFFFF), ((COA0_TRIM29 = (COA0_TRIM29 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM30  -------------------------------
+// SVD Line: 19704
+
+unsigned int COA0_TRIM30 __AT (0x1FFFF078);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM30  -----------------------------------
+// SVD Line: 19704
+
+//  <item> SFDITEM_REG__COA0_TRIM30
+//    <name> TRIM30 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF078) System Related Trim Value 30 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM30 >> 0) & 0xFFFFFFFF), ((COA0_TRIM30 = (COA0_TRIM30 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA0_TRIM31  -------------------------------
+// SVD Line: 19712
+
+unsigned int COA0_TRIM31 __AT (0x1FFFF07C);
+
+
+
+// -------------------------------  Register Item: COA0_TRIM31  -----------------------------------
+// SVD Line: 19712
+
+//  <item> SFDITEM_REG__COA0_TRIM31
+//    <name> TRIM31 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF07C) System Related Trim Value 31 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA0_TRIM31 >> 0) & 0xFFFFFFFF), ((COA0_TRIM31 = (COA0_TRIM31 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------------  Peripheral View: COA0  -------------------------------------
+// SVD Line: 19411
+
+//  <view> COA0
+//    <name> COA0 </name>
+//    <item> SFDITEM_REG__COA0_TRIM00 </item>
+//    <item> SFDITEM_REG__COA0_TRIM01 </item>
+//    <item> SFDITEM_REG__COA0_TRIM02 </item>
+//    <item> SFDITEM_REG__COA0_TRIM03 </item>
+//    <item> SFDITEM_REG__COA0_TRIM04 </item>
+//    <item> SFDITEM_REG__COA0_TRIM05 </item>
+//    <item> SFDITEM_REG__COA0_TRIM06 </item>
+//    <item> SFDITEM_REG__COA0_TRIM07 </item>
+//    <item> SFDITEM_REG__COA0_TRIM08 </item>
+//    <item> SFDITEM_REG__COA0_TRIM09 </item>
+//    <item> SFDITEM_REG__COA0_TRIM10 </item>
+//    <item> SFDITEM_REG__COA0_TRIM11 </item>
+//    <item> SFDITEM_REG__COA0_TRIM12 </item>
+//    <item> SFDITEM_REG__COA0_TRIM13 </item>
+//    <item> SFDITEM_REG__COA0_TRIM14 </item>
+//    <item> SFDITEM_REG__COA0_TRIM15 </item>
+//    <item> SFDITEM_REG__COA0_TRIM16 </item>
+//    <item> SFDITEM_REG__COA0_TRIM17 </item>
+//    <item> SFDITEM_REG__COA0_TRIM18 </item>
+//    <item> SFDITEM_REG__COA0_TRIM19 </item>
+//    <item> SFDITEM_REG__COA0_CONF_MF1CNFIG </item>
+//    <item> SFDITEM_REG__COA0_CONF_MF2CNFIG </item>
+//    <item> SFDITEM_REG__COA0_CONF_MF3CNFIG </item>
+//    <item> SFDITEM_REG__COA0_CONF_MF4CNFIG </item>
+//    <item> SFDITEM_REG__COA0_TRIM24 </item>
+//    <item> SFDITEM_REG__COA0_TRIM25 </item>
+//    <item> SFDITEM_REG__COA0_TRIM26 </item>
+//    <item> SFDITEM_REG__COA0_TRIM27 </item>
+//    <item> SFDITEM_REG__COA0_TRIM28 </item>
+//    <item> SFDITEM_REG__COA0_TRIM29 </item>
+//    <item> SFDITEM_REG__COA0_TRIM30 </item>
+//    <item> SFDITEM_REG__COA0_TRIM31 </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: COA1_RPCNFIG  ------------------------------
+// SVD Line: 19736
+
+unsigned int COA1_RPCNFIG __AT (0x1FFFF200);
+
+
+
+// -----------------------------  Field Item: COA1_RPCNFIG_WTIDKY  --------------------------------
+// SVD Line: 19745
+
+//  <item> SFDITEM_FIELD__COA1_RPCNFIG_WTIDKY
+//    <name> WTIDKY </name>
+//    <r> 
+//    <i> [Bits 31..4] RO (@ 0x1FFFF200) Write Identification Key (0x69c8a27) </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA1_RPCNFIG >> 4) & 0xFFFFFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_RPCNFIG_READP  ---------------------------------
+// SVD Line: 19758
+
+//  <item> SFDITEM_FIELD__COA1_RPCNFIG_READP
+//    <name> READP </name>
+//    <r> 
+//    <i> [Bits 1..0] RO (@ 0x1FFFF200) \nRead Protection for Flash Memory Area\n0 : Level2 = 1. Not readable/erasable/writable by 'Debug' / 'Instruction from RAM'  2. Bulk erasable only by 'Instruction from RAM' / 'Debug'  3. Readable/erasable/writable by 'Instruction from Flash Memory'\n1 : Reserved - do not use\n2 : Level1 = 1. Not readable/erasable/writable by 'Debug'  2. Bulk erasable only by 'Debug'  3. Readable/erasable/writable by 'Instruction from Flash Memory and RAM'\n3 : Level0 = No restriction for read/erase/write. </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_RPCNFIG ) </loc>
+//      <o.1..0> READP
+//        <0=> 0: Level2 = 1. Not readable/erasable/writable by 'Debug' / 'Instruction from RAM'  2. Bulk erasable only by 'Instruction from RAM' / 'Debug'  3. Readable/erasable/writable by 'Instruction from Flash Memory'
+//        <1=> 1: 
+//        <2=> 2: Level1 = 1. Not readable/erasable/writable by 'Debug'  2. Bulk erasable only by 'Debug'  3. Readable/erasable/writable by 'Instruction from Flash Memory and RAM'
+//        <3=> 3: Level0 = No restriction for read/erase/write.
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: COA1_RPCNFIG  ----------------------------------
+// SVD Line: 19736
+
+//  <rtree> SFDITEM_REG__COA1_RPCNFIG
+//    <name> RPCNFIG </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF200) Configuration for Read Protection </i>
+//    <loc> ( (unsigned int)((COA1_RPCNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA1_RPCNFIG_WTIDKY </item>
+//    <item> SFDITEM_FIELD__COA1_RPCNFIG_READP </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: COA1_WDTCNFIG  ------------------------------
+// SVD Line: 19791
+
+unsigned int COA1_WDTCNFIG __AT (0x1FFFF20C);
+
+
+
+// -----------------------------  Field Item: COA1_WDTCNFIG_WRCMF  --------------------------------
+// SVD Line: 19800
+
+//  <item> SFDITEM_FIELD__COA1_WDTCNFIG_WRCMF
+//    <name> WRCMF </name>
+//    <r> 
+//    <i> [Bits 15..4] RO (@ 0x1FFFF20C) Watch-Dog Timer RC Oscillator Master Configuration </i>
+//    <edit> 
+//      <loc> ( (unsigned short)((COA1_WDTCNFIG >> 4) & 0xFFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: COA1_WDTCNFIG_WCLKMF  --------------------------------
+// SVD Line: 19823
+
+//  <item> SFDITEM_FIELD__COA1_WDTCNFIG_WCLKMF
+//    <name> WCLKMF </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x1FFFF20C) \nWatch-Dog Timer Clock Selection Master Configuration\n0 : BySW = By S/W (PPCLKSR Register)\n1 : AlwaysWDTRC = Always WDTRC </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_WDTCNFIG ) </loc>
+//      <o.2..2> WCLKMF
+//        <0=> 0: BySW = By S/W (PPCLKSR Register)
+//        <1=> 1: AlwaysWDTRC = Always WDTRC
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: COA1_WDTCNFIG_WRSTMF  --------------------------------
+// SVD Line: 19841
+
+//  <item> SFDITEM_FIELD__COA1_WDTCNFIG_WRSTMF
+//    <name> WRSTMF </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x1FFFF20C) \nWatch-Dog Timer Reset Enable Master Configuration\n0 : AlwaysEnable = Always Enable\n1 : BySW = By S/W (WDTCR Register) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_WDTCNFIG ) </loc>
+//      <o.1..1> WRSTMF
+//        <0=> 0: AlwaysEnable = Always Enable
+//        <1=> 1: BySW = By S/W (WDTCR Register)
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: COA1_WDTCNFIG_WCNTMF  --------------------------------
+// SVD Line: 19859
+
+//  <item> SFDITEM_FIELD__COA1_WDTCNFIG_WCNTMF
+//    <name> WCNTMF </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x1FFFF20C) \nWatch-Dog Timer Counter Enable Master Configuration\n0 : AlwaysEnable = Always Enable\n1 : BySW = By S/W (WDTCR Register) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_WDTCNFIG ) </loc>
+//      <o.0..0> WCNTMF
+//        <0=> 0: AlwaysEnable = Always Enable
+//        <1=> 1: BySW = By S/W (WDTCR Register)
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: COA1_WDTCNFIG  ---------------------------------
+// SVD Line: 19791
+
+//  <rtree> SFDITEM_REG__COA1_WDTCNFIG
+//    <name> WDTCNFIG </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF20C) Configuration for Watch-Dog Timer </i>
+//    <loc> ( (unsigned int)((COA1_WDTCNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA1_WDTCNFIG_WRCMF </item>
+//    <item> SFDITEM_FIELD__COA1_WDTCNFIG_WCLKMF </item>
+//    <item> SFDITEM_FIELD__COA1_WDTCNFIG_WRSTMF </item>
+//    <item> SFDITEM_FIELD__COA1_WDTCNFIG_WCNTMF </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: COA1_LVRCNFIG  ------------------------------
+// SVD Line: 19879
+
+unsigned int COA1_LVRCNFIG __AT (0x1FFFF210);
+
+
+
+// ----------------------------  Field Item: COA1_LVRCNFIG_LVRENM  --------------------------------
+// SVD Line: 19888
+
+//  <item> SFDITEM_FIELD__COA1_LVRCNFIG_LVRENM
+//    <name> LVRENM </name>
+//    <r> 
+//    <i> [Bits 15..8] RO (@ 0x1FFFF210) LVR Reset Operation Control Master Configuration </i>
+//    <edit> 
+//      <loc> ( (unsigned char)((COA1_LVRCNFIG >> 8) & 0xFF) ) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_LVRCNFIG_LVRVS  --------------------------------
+// SVD Line: 19906
+
+//  <item> SFDITEM_FIELD__COA1_LVRCNFIG_LVRVS
+//    <name> LVRVS </name>
+//    <r> 
+//    <i> [Bits 3..0] RO (@ 0x1FFFF210) \nLVR Voltage Selection\n0 : 4p55 = 4.55V\n1 : 4p25V = 4.25V\n2 : 3p99V = 3.99V\n3 : 3p75V = 3.75V\n4 : 3p55V = 3.55V\n5 : 3p20V = 3.20V\n6 : 3p04V = 3.04V\n7 : 2p67V = 2.67V\n8 : 2p46V = 2.46V\n9 : 2p28V = 2.28V\n10 : 2p13V = 2.13V\n11 : 2p00V = 2.00V\n12 : DNW12 = Do not write.\n13 : DNW13 = Do not write.\n14 : DNW14 = Do not write.\n15 : 1p62V = 1.62V </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_LVRCNFIG ) </loc>
+//      <o.3..0> LVRVS
+//        <0=> 0: 4p55 = 4.55V
+//        <1=> 1: 4p25V = 4.25V
+//        <2=> 2: 3p99V = 3.99V
+//        <3=> 3: 3p75V = 3.75V
+//        <4=> 4: 3p55V = 3.55V
+//        <5=> 5: 3p20V = 3.20V
+//        <6=> 6: 3p04V = 3.04V
+//        <7=> 7: 2p67V = 2.67V
+//        <8=> 8: 2p46V = 2.46V
+//        <9=> 9: 2p28V = 2.28V
+//        <10=> 10: 2p13V = 2.13V
+//        <11=> 11: 2p00V = 2.00V
+//        <12=> 12: DNW12 = Do not write.
+//        <13=> 13: DNW13 = Do not write.
+//        <14=> 14: DNW14 = Do not write.
+//        <15=> 15: 1p62V = 1.62V
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Register RTree: COA1_LVRCNFIG  ---------------------------------
+// SVD Line: 19879
+
+//  <rtree> SFDITEM_REG__COA1_LVRCNFIG
+//    <name> LVRCNFIG </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF210) Configuration for Low Voltage Reset </i>
+//    <loc> ( (unsigned int)((COA1_LVRCNFIG >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA1_LVRCNFIG_LVRENM </item>
+//    <item> SFDITEM_FIELD__COA1_LVRCNFIG_LVRVS </item>
+//  </rtree>
+//  
+
+
+// --------------------------  Register Item Address: COA1_CNFIGWTP1  -----------------------------
+// SVD Line: 19996
+
+unsigned int COA1_CNFIGWTP1 __AT (0x1FFFF214);
+
+
+
+// ----------------------------  Field Item: COA1_CNFIGWTP1_CP3WP  --------------------------------
+// SVD Line: 20005
+
+//  <item> SFDITEM_FIELD__COA1_CNFIGWTP1_CP3WP
+//    <name> CP3WP </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x1FFFF214) \nConfigure Option Page 3 Erase/Write Protection\n0 : Enable = Enable protection. (Not erasable/writable by instruction)\n1 : Disable = Disable protection. (Erasable/writable by instruction) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_CNFIGWTP1 ) </loc>
+//      <o.2..2> CP3WP
+//        <0=> 0: Enable = Enable protection. (Not erasable/writable by instruction)
+//        <1=> 1: Disable = Disable protection. (Erasable/writable by instruction)
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: COA1_CNFIGWTP1_CP2WP  --------------------------------
+// SVD Line: 20023
+
+//  <item> SFDITEM_FIELD__COA1_CNFIGWTP1_CP2WP
+//    <name> CP2WP </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x1FFFF214) \nConfigure Option Page 2 Erase/Write Protection\n0 : Enable = Enable protection. (Not erasable/writable by instruction)\n1 : Disable = Disable protection. (Erasable/writable by instruction) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_CNFIGWTP1 ) </loc>
+//      <o.1..1> CP2WP
+//        <0=> 0: Enable = Enable protection. (Not erasable/writable by instruction)
+//        <1=> 1: Disable = Disable protection. (Erasable/writable by instruction)
+//    </combo>
+//  </item>
+//  
+
+
+// ----------------------------  Field Item: COA1_CNFIGWTP1_CP1WP  --------------------------------
+// SVD Line: 20041
+
+//  <item> SFDITEM_FIELD__COA1_CNFIGWTP1_CP1WP
+//    <name> CP1WP </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x1FFFF214) \nConfigure Option Page 1 Erase/Write Protection\n0 : Enable = Enable protection. (Not erasable/writable by instruction)\n1 : Disable = Disable protection. (Erasable/writable by instruction) </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_CNFIGWTP1 ) </loc>
+//      <o.0..0> CP1WP
+//        <0=> 0: Enable = Enable protection. (Not erasable/writable by instruction)
+//        <1=> 1: Disable = Disable protection. (Erasable/writable by instruction)
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Register RTree: COA1_CNFIGWTP1  ---------------------------------
+// SVD Line: 19996
+
+//  <rtree> SFDITEM_REG__COA1_CNFIGWTP1
+//    <name> CNFIGWTP1 </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF214) Erase/Write Protection for Configure Option Page 1/2/3 </i>
+//    <loc> ( (unsigned int)((COA1_CNFIGWTP1 >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA1_CNFIGWTP1_CP3WP </item>
+//    <item> SFDITEM_FIELD__COA1_CNFIGWTP1_CP2WP </item>
+//    <item> SFDITEM_FIELD__COA1_CNFIGWTP1_CP1WP </item>
+//  </rtree>
+//  
+
+
+// ---------------------------  Register Item Address: COA1_FMWTP1  -------------------------------
+// SVD Line: 20061
+
+unsigned int COA1_FMWTP1 __AT (0x1FFFF240);
+
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP31  ---------------------------------
+// SVD Line: 20069
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP31
+//    <name> SWTP31 </name>
+//    <r> 
+//    <i> [Bit 31] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 31\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.31..31> SWTP31
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP30  ---------------------------------
+// SVD Line: 20087
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP30
+//    <name> SWTP30 </name>
+//    <r> 
+//    <i> [Bit 30] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 30\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.30..30> SWTP30
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP29  ---------------------------------
+// SVD Line: 20105
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP29
+//    <name> SWTP29 </name>
+//    <r> 
+//    <i> [Bit 29] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 29\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.29..29> SWTP29
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP28  ---------------------------------
+// SVD Line: 20123
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP28
+//    <name> SWTP28 </name>
+//    <r> 
+//    <i> [Bit 28] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 28\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.28..28> SWTP28
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP27  ---------------------------------
+// SVD Line: 20141
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP27
+//    <name> SWTP27 </name>
+//    <r> 
+//    <i> [Bit 27] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 27\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.27..27> SWTP27
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP26  ---------------------------------
+// SVD Line: 20159
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP26
+//    <name> SWTP26 </name>
+//    <r> 
+//    <i> [Bit 26] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 26\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.26..26> SWTP26
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP25  ---------------------------------
+// SVD Line: 20177
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP25
+//    <name> SWTP25 </name>
+//    <r> 
+//    <i> [Bit 25] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 25\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.25..25> SWTP25
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP24  ---------------------------------
+// SVD Line: 20195
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP24
+//    <name> SWTP24 </name>
+//    <r> 
+//    <i> [Bit 24] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 24\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.24..24> SWTP24
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP23  ---------------------------------
+// SVD Line: 20213
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP23
+//    <name> SWTP23 </name>
+//    <r> 
+//    <i> [Bit 23] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 23\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.23..23> SWTP23
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP22  ---------------------------------
+// SVD Line: 20231
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP22
+//    <name> SWTP22 </name>
+//    <r> 
+//    <i> [Bit 22] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 22\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.22..22> SWTP22
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP21  ---------------------------------
+// SVD Line: 20249
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP21
+//    <name> SWTP21 </name>
+//    <r> 
+//    <i> [Bit 21] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 21\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.21..21> SWTP21
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP20  ---------------------------------
+// SVD Line: 20267
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP20
+//    <name> SWTP20 </name>
+//    <r> 
+//    <i> [Bit 20] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 20\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.20..20> SWTP20
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP19  ---------------------------------
+// SVD Line: 20285
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP19
+//    <name> SWTP19 </name>
+//    <r> 
+//    <i> [Bit 19] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 19\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.19..19> SWTP19
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP18  ---------------------------------
+// SVD Line: 20303
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP18
+//    <name> SWTP18 </name>
+//    <r> 
+//    <i> [Bit 18] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 18\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.18..18> SWTP18
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP17  ---------------------------------
+// SVD Line: 20321
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP17
+//    <name> SWTP17 </name>
+//    <r> 
+//    <i> [Bit 17] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 17\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.17..17> SWTP17
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP16  ---------------------------------
+// SVD Line: 20339
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP16
+//    <name> SWTP16 </name>
+//    <r> 
+//    <i> [Bit 16] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 16\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.16..16> SWTP16
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP15  ---------------------------------
+// SVD Line: 20357
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP15
+//    <name> SWTP15 </name>
+//    <r> 
+//    <i> [Bit 15] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 15\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.15..15> SWTP15
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP14  ---------------------------------
+// SVD Line: 20375
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP14
+//    <name> SWTP14 </name>
+//    <r> 
+//    <i> [Bit 14] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 14\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.14..14> SWTP14
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP13  ---------------------------------
+// SVD Line: 20393
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP13
+//    <name> SWTP13 </name>
+//    <r> 
+//    <i> [Bit 13] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 13\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.13..13> SWTP13
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP12  ---------------------------------
+// SVD Line: 20411
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP12
+//    <name> SWTP12 </name>
+//    <r> 
+//    <i> [Bit 12] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 12\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.12..12> SWTP12
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP11  ---------------------------------
+// SVD Line: 20429
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP11
+//    <name> SWTP11 </name>
+//    <r> 
+//    <i> [Bit 11] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 11\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.11..11> SWTP11
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -----------------------------  Field Item: COA1_FMWTP1_SWTP10  ---------------------------------
+// SVD Line: 20447
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP10
+//    <name> SWTP10 </name>
+//    <r> 
+//    <i> [Bit 10] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 10\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.10..10> SWTP10
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP9  ---------------------------------
+// SVD Line: 20465
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP9
+//    <name> SWTP9 </name>
+//    <r> 
+//    <i> [Bit 9] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 9\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.9..9> SWTP9
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP8  ---------------------------------
+// SVD Line: 20483
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP8
+//    <name> SWTP8 </name>
+//    <r> 
+//    <i> [Bit 8] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 8\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.8..8> SWTP8
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP7  ---------------------------------
+// SVD Line: 20501
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP7
+//    <name> SWTP7 </name>
+//    <r> 
+//    <i> [Bit 7] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 7\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.7..7> SWTP7
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP6  ---------------------------------
+// SVD Line: 20519
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP6
+//    <name> SWTP6 </name>
+//    <r> 
+//    <i> [Bit 6] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 6\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.6..6> SWTP6
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP5  ---------------------------------
+// SVD Line: 20537
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP5
+//    <name> SWTP5 </name>
+//    <r> 
+//    <i> [Bit 5] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 5\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.5..5> SWTP5
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP4  ---------------------------------
+// SVD Line: 20555
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP4
+//    <name> SWTP4 </name>
+//    <r> 
+//    <i> [Bit 4] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 4\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.4..4> SWTP4
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP3  ---------------------------------
+// SVD Line: 20573
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP3
+//    <name> SWTP3 </name>
+//    <r> 
+//    <i> [Bit 3] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 3\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.3..3> SWTP3
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP2  ---------------------------------
+// SVD Line: 20591
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP2
+//    <name> SWTP2 </name>
+//    <r> 
+//    <i> [Bit 2] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 2\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.2..2> SWTP2
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP1  ---------------------------------
+// SVD Line: 20609
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP1
+//    <name> SWTP1 </name>
+//    <r> 
+//    <i> [Bit 1] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 1\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.1..1> SWTP1
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// ------------------------------  Field Item: COA1_FMWTP1_SWTP0  ---------------------------------
+// SVD Line: 20627
+
+//  <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP0
+//    <name> SWTP0 </name>
+//    <r> 
+//    <i> [Bit 0] RO (@ 0x1FFFF240) \nFlash Memory Erase/Write Protection 0\n0 : Enable = Protect 'flash memory sector n erase/write'\n1 : Disable = Permit 'flash memory sector n erase/write' </i>
+//    <combo> 
+//      <loc> ( (unsigned int) COA1_FMWTP1 ) </loc>
+//      <o.0..0> SWTP0
+//        <0=> 0: Enable = Protect 'flash memory sector n erase/write'
+//        <1=> 1: Disable = Permit 'flash memory sector n erase/write'
+//    </combo>
+//  </item>
+//  
+
+
+// -------------------------------  Register RTree: COA1_FMWTP1  ----------------------------------
+// SVD Line: 20061
+
+//  <rtree> SFDITEM_REG__COA1_FMWTP1
+//    <name> FMWTP1 </name>
+//    <r> 
+//    <i> [Bits 31..0] RO (@ 0x1FFFF240) Erase/Write Protection for Flash Memory </i>
+//    <loc> ( (unsigned int)((COA1_FMWTP1 >> 0) & 0xFFFFFFFF) ) </loc>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP31 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP30 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP29 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP28 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP27 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP26 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP25 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP24 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP23 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP22 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP21 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP20 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP19 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP18 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP17 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP16 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP15 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP14 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP13 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP12 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP11 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP10 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP9 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP8 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP7 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP6 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP5 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP4 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP3 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP2 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP1 </item>
+//    <item> SFDITEM_FIELD__COA1_FMWTP1_SWTP0 </item>
+//  </rtree>
+//  
+
+
+// ----------------------------------  Peripheral View: COA1  -------------------------------------
+// SVD Line: 19722
+
+//  <view> COA1
+//    <name> COA1 </name>
+//    <item> SFDITEM_REG__COA1_RPCNFIG </item>
+//    <item> SFDITEM_REG__COA1_WDTCNFIG </item>
+//    <item> SFDITEM_REG__COA1_LVRCNFIG </item>
+//    <item> SFDITEM_REG__COA1_CNFIGWTP1 </item>
+//    <item> SFDITEM_REG__COA1_FMWTP1 </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA00  ------------------------------
+// SVD Line: 20663
+
+unsigned int COA2_UDATA00 __AT (0x1FFFF400);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA00  ----------------------------------
+// SVD Line: 20663
+
+//  <item> SFDITEM_REG__COA2_UDATA00
+//    <name> UDATA00 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF400) User Data 00 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA00 >> 0) & 0xFFFFFFFF), ((COA2_UDATA00 = (COA2_UDATA00 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA01  ------------------------------
+// SVD Line: 20671
+
+unsigned int COA2_UDATA01 __AT (0x1FFFF404);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA01  ----------------------------------
+// SVD Line: 20671
+
+//  <item> SFDITEM_REG__COA2_UDATA01
+//    <name> UDATA01 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF404) User Data 01 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA01 >> 0) & 0xFFFFFFFF), ((COA2_UDATA01 = (COA2_UDATA01 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA02  ------------------------------
+// SVD Line: 20679
+
+unsigned int COA2_UDATA02 __AT (0x1FFFF408);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA02  ----------------------------------
+// SVD Line: 20679
+
+//  <item> SFDITEM_REG__COA2_UDATA02
+//    <name> UDATA02 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF408) User Data 02 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA02 >> 0) & 0xFFFFFFFF), ((COA2_UDATA02 = (COA2_UDATA02 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA03  ------------------------------
+// SVD Line: 20687
+
+unsigned int COA2_UDATA03 __AT (0x1FFFF40C);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA03  ----------------------------------
+// SVD Line: 20687
+
+//  <item> SFDITEM_REG__COA2_UDATA03
+//    <name> UDATA03 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF40C) User Data 03 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA03 >> 0) & 0xFFFFFFFF), ((COA2_UDATA03 = (COA2_UDATA03 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA04  ------------------------------
+// SVD Line: 20695
+
+unsigned int COA2_UDATA04 __AT (0x1FFFF410);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA04  ----------------------------------
+// SVD Line: 20695
+
+//  <item> SFDITEM_REG__COA2_UDATA04
+//    <name> UDATA04 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF410) User Data 04 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA04 >> 0) & 0xFFFFFFFF), ((COA2_UDATA04 = (COA2_UDATA04 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA05  ------------------------------
+// SVD Line: 20703
+
+unsigned int COA2_UDATA05 __AT (0x1FFFF414);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA05  ----------------------------------
+// SVD Line: 20703
+
+//  <item> SFDITEM_REG__COA2_UDATA05
+//    <name> UDATA05 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF414) User Data 05 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA05 >> 0) & 0xFFFFFFFF), ((COA2_UDATA05 = (COA2_UDATA05 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA06  ------------------------------
+// SVD Line: 20711
+
+unsigned int COA2_UDATA06 __AT (0x1FFFF418);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA06  ----------------------------------
+// SVD Line: 20711
+
+//  <item> SFDITEM_REG__COA2_UDATA06
+//    <name> UDATA06 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF418) User Data 06 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA06 >> 0) & 0xFFFFFFFF), ((COA2_UDATA06 = (COA2_UDATA06 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA07  ------------------------------
+// SVD Line: 20719
+
+unsigned int COA2_UDATA07 __AT (0x1FFFF41C);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA07  ----------------------------------
+// SVD Line: 20719
+
+//  <item> SFDITEM_REG__COA2_UDATA07
+//    <name> UDATA07 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF41C) User Data 07 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA07 >> 0) & 0xFFFFFFFF), ((COA2_UDATA07 = (COA2_UDATA07 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA08  ------------------------------
+// SVD Line: 20727
+
+unsigned int COA2_UDATA08 __AT (0x1FFFF420);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA08  ----------------------------------
+// SVD Line: 20727
+
+//  <item> SFDITEM_REG__COA2_UDATA08
+//    <name> UDATA08 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF420) User Data 08 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA08 >> 0) & 0xFFFFFFFF), ((COA2_UDATA08 = (COA2_UDATA08 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA09  ------------------------------
+// SVD Line: 20735
+
+unsigned int COA2_UDATA09 __AT (0x1FFFF424);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA09  ----------------------------------
+// SVD Line: 20735
+
+//  <item> SFDITEM_REG__COA2_UDATA09
+//    <name> UDATA09 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF424) User Data 09 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA09 >> 0) & 0xFFFFFFFF), ((COA2_UDATA09 = (COA2_UDATA09 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA10  ------------------------------
+// SVD Line: 20743
+
+unsigned int COA2_UDATA10 __AT (0x1FFFF428);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA10  ----------------------------------
+// SVD Line: 20743
+
+//  <item> SFDITEM_REG__COA2_UDATA10
+//    <name> UDATA10 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF428) User Data 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA10 >> 0) & 0xFFFFFFFF), ((COA2_UDATA10 = (COA2_UDATA10 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA11  ------------------------------
+// SVD Line: 20751
+
+unsigned int COA2_UDATA11 __AT (0x1FFFF42C);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA11  ----------------------------------
+// SVD Line: 20751
+
+//  <item> SFDITEM_REG__COA2_UDATA11
+//    <name> UDATA11 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF42C) User Data 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA11 >> 0) & 0xFFFFFFFF), ((COA2_UDATA11 = (COA2_UDATA11 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA12  ------------------------------
+// SVD Line: 20759
+
+unsigned int COA2_UDATA12 __AT (0x1FFFF430);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA12  ----------------------------------
+// SVD Line: 20759
+
+//  <item> SFDITEM_REG__COA2_UDATA12
+//    <name> UDATA12 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF430) User Data 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA12 >> 0) & 0xFFFFFFFF), ((COA2_UDATA12 = (COA2_UDATA12 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA13  ------------------------------
+// SVD Line: 20767
+
+unsigned int COA2_UDATA13 __AT (0x1FFFF434);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA13  ----------------------------------
+// SVD Line: 20767
+
+//  <item> SFDITEM_REG__COA2_UDATA13
+//    <name> UDATA13 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF434) User Data 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA13 >> 0) & 0xFFFFFFFF), ((COA2_UDATA13 = (COA2_UDATA13 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA14  ------------------------------
+// SVD Line: 20775
+
+unsigned int COA2_UDATA14 __AT (0x1FFFF438);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA14  ----------------------------------
+// SVD Line: 20775
+
+//  <item> SFDITEM_REG__COA2_UDATA14
+//    <name> UDATA14 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF438) User Data 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA14 >> 0) & 0xFFFFFFFF), ((COA2_UDATA14 = (COA2_UDATA14 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA15  ------------------------------
+// SVD Line: 20783
+
+unsigned int COA2_UDATA15 __AT (0x1FFFF43C);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA15  ----------------------------------
+// SVD Line: 20783
+
+//  <item> SFDITEM_REG__COA2_UDATA15
+//    <name> UDATA15 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF43C) User Data 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA15 >> 0) & 0xFFFFFFFF), ((COA2_UDATA15 = (COA2_UDATA15 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA16  ------------------------------
+// SVD Line: 20791
+
+unsigned int COA2_UDATA16 __AT (0x1FFFF440);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA16  ----------------------------------
+// SVD Line: 20791
+
+//  <item> SFDITEM_REG__COA2_UDATA16
+//    <name> UDATA16 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF440) User Data 16 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA16 >> 0) & 0xFFFFFFFF), ((COA2_UDATA16 = (COA2_UDATA16 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA17  ------------------------------
+// SVD Line: 20799
+
+unsigned int COA2_UDATA17 __AT (0x1FFFF444);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA17  ----------------------------------
+// SVD Line: 20799
+
+//  <item> SFDITEM_REG__COA2_UDATA17
+//    <name> UDATA17 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF444) User Data 17 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA17 >> 0) & 0xFFFFFFFF), ((COA2_UDATA17 = (COA2_UDATA17 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA18  ------------------------------
+// SVD Line: 20807
+
+unsigned int COA2_UDATA18 __AT (0x1FFFF448);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA18  ----------------------------------
+// SVD Line: 20807
+
+//  <item> SFDITEM_REG__COA2_UDATA18
+//    <name> UDATA18 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF448) User Data 18 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA18 >> 0) & 0xFFFFFFFF), ((COA2_UDATA18 = (COA2_UDATA18 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA19  ------------------------------
+// SVD Line: 20815
+
+unsigned int COA2_UDATA19 __AT (0x1FFFF44C);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA19  ----------------------------------
+// SVD Line: 20815
+
+//  <item> SFDITEM_REG__COA2_UDATA19
+//    <name> UDATA19 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF44C) User Data 19 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA19 >> 0) & 0xFFFFFFFF), ((COA2_UDATA19 = (COA2_UDATA19 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA20  ------------------------------
+// SVD Line: 20823
+
+unsigned int COA2_UDATA20 __AT (0x1FFFF450);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA20  ----------------------------------
+// SVD Line: 20823
+
+//  <item> SFDITEM_REG__COA2_UDATA20
+//    <name> UDATA20 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF450) User Data 20 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA20 >> 0) & 0xFFFFFFFF), ((COA2_UDATA20 = (COA2_UDATA20 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA21  ------------------------------
+// SVD Line: 20831
+
+unsigned int COA2_UDATA21 __AT (0x1FFFF454);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA21  ----------------------------------
+// SVD Line: 20831
+
+//  <item> SFDITEM_REG__COA2_UDATA21
+//    <name> UDATA21 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF454) User Data 21 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA21 >> 0) & 0xFFFFFFFF), ((COA2_UDATA21 = (COA2_UDATA21 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA22  ------------------------------
+// SVD Line: 20839
+
+unsigned int COA2_UDATA22 __AT (0x1FFFF458);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA22  ----------------------------------
+// SVD Line: 20839
+
+//  <item> SFDITEM_REG__COA2_UDATA22
+//    <name> UDATA22 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF458) User Data 22 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA22 >> 0) & 0xFFFFFFFF), ((COA2_UDATA22 = (COA2_UDATA22 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA23  ------------------------------
+// SVD Line: 20847
+
+unsigned int COA2_UDATA23 __AT (0x1FFFF45C);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA23  ----------------------------------
+// SVD Line: 20847
+
+//  <item> SFDITEM_REG__COA2_UDATA23
+//    <name> UDATA23 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF45C) User Data 23 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA23 >> 0) & 0xFFFFFFFF), ((COA2_UDATA23 = (COA2_UDATA23 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA24  ------------------------------
+// SVD Line: 20855
+
+unsigned int COA2_UDATA24 __AT (0x1FFFF460);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA24  ----------------------------------
+// SVD Line: 20855
+
+//  <item> SFDITEM_REG__COA2_UDATA24
+//    <name> UDATA24 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF460) User Data 24 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA24 >> 0) & 0xFFFFFFFF), ((COA2_UDATA24 = (COA2_UDATA24 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA25  ------------------------------
+// SVD Line: 20863
+
+unsigned int COA2_UDATA25 __AT (0x1FFFF464);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA25  ----------------------------------
+// SVD Line: 20863
+
+//  <item> SFDITEM_REG__COA2_UDATA25
+//    <name> UDATA25 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF464) User Data 25 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA25 >> 0) & 0xFFFFFFFF), ((COA2_UDATA25 = (COA2_UDATA25 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA26  ------------------------------
+// SVD Line: 20871
+
+unsigned int COA2_UDATA26 __AT (0x1FFFF468);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA26  ----------------------------------
+// SVD Line: 20871
+
+//  <item> SFDITEM_REG__COA2_UDATA26
+//    <name> UDATA26 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF468) User Data 26 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA26 >> 0) & 0xFFFFFFFF), ((COA2_UDATA26 = (COA2_UDATA26 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA27  ------------------------------
+// SVD Line: 20879
+
+unsigned int COA2_UDATA27 __AT (0x1FFFF46C);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA27  ----------------------------------
+// SVD Line: 20879
+
+//  <item> SFDITEM_REG__COA2_UDATA27
+//    <name> UDATA27 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF46C) User Data 27 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA27 >> 0) & 0xFFFFFFFF), ((COA2_UDATA27 = (COA2_UDATA27 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA28  ------------------------------
+// SVD Line: 20887
+
+unsigned int COA2_UDATA28 __AT (0x1FFFF470);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA28  ----------------------------------
+// SVD Line: 20887
+
+//  <item> SFDITEM_REG__COA2_UDATA28
+//    <name> UDATA28 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF470) User Data 28 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA28 >> 0) & 0xFFFFFFFF), ((COA2_UDATA28 = (COA2_UDATA28 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA29  ------------------------------
+// SVD Line: 20895
+
+unsigned int COA2_UDATA29 __AT (0x1FFFF474);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA29  ----------------------------------
+// SVD Line: 20895
+
+//  <item> SFDITEM_REG__COA2_UDATA29
+//    <name> UDATA29 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF474) User Data 29 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA29 >> 0) & 0xFFFFFFFF), ((COA2_UDATA29 = (COA2_UDATA29 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA30  ------------------------------
+// SVD Line: 20903
+
+unsigned int COA2_UDATA30 __AT (0x1FFFF478);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA30  ----------------------------------
+// SVD Line: 20903
+
+//  <item> SFDITEM_REG__COA2_UDATA30
+//    <name> UDATA30 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF478) User Data 30 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA30 >> 0) & 0xFFFFFFFF), ((COA2_UDATA30 = (COA2_UDATA30 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA2_UDATA31  ------------------------------
+// SVD Line: 20911
+
+unsigned int COA2_UDATA31 __AT (0x1FFFF47C);
+
+
+
+// -------------------------------  Register Item: COA2_UDATA31  ----------------------------------
+// SVD Line: 20911
+
+//  <item> SFDITEM_REG__COA2_UDATA31
+//    <name> UDATA31 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF47C) User Data 31 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA2_UDATA31 >> 0) & 0xFFFFFFFF), ((COA2_UDATA31 = (COA2_UDATA31 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------------  Peripheral View: COA2  -------------------------------------
+// SVD Line: 20649
+
+//  <view> COA2
+//    <name> COA2 </name>
+//    <item> SFDITEM_REG__COA2_UDATA00 </item>
+//    <item> SFDITEM_REG__COA2_UDATA01 </item>
+//    <item> SFDITEM_REG__COA2_UDATA02 </item>
+//    <item> SFDITEM_REG__COA2_UDATA03 </item>
+//    <item> SFDITEM_REG__COA2_UDATA04 </item>
+//    <item> SFDITEM_REG__COA2_UDATA05 </item>
+//    <item> SFDITEM_REG__COA2_UDATA06 </item>
+//    <item> SFDITEM_REG__COA2_UDATA07 </item>
+//    <item> SFDITEM_REG__COA2_UDATA08 </item>
+//    <item> SFDITEM_REG__COA2_UDATA09 </item>
+//    <item> SFDITEM_REG__COA2_UDATA10 </item>
+//    <item> SFDITEM_REG__COA2_UDATA11 </item>
+//    <item> SFDITEM_REG__COA2_UDATA12 </item>
+//    <item> SFDITEM_REG__COA2_UDATA13 </item>
+//    <item> SFDITEM_REG__COA2_UDATA14 </item>
+//    <item> SFDITEM_REG__COA2_UDATA15 </item>
+//    <item> SFDITEM_REG__COA2_UDATA16 </item>
+//    <item> SFDITEM_REG__COA2_UDATA17 </item>
+//    <item> SFDITEM_REG__COA2_UDATA18 </item>
+//    <item> SFDITEM_REG__COA2_UDATA19 </item>
+//    <item> SFDITEM_REG__COA2_UDATA20 </item>
+//    <item> SFDITEM_REG__COA2_UDATA21 </item>
+//    <item> SFDITEM_REG__COA2_UDATA22 </item>
+//    <item> SFDITEM_REG__COA2_UDATA23 </item>
+//    <item> SFDITEM_REG__COA2_UDATA24 </item>
+//    <item> SFDITEM_REG__COA2_UDATA25 </item>
+//    <item> SFDITEM_REG__COA2_UDATA26 </item>
+//    <item> SFDITEM_REG__COA2_UDATA27 </item>
+//    <item> SFDITEM_REG__COA2_UDATA28 </item>
+//    <item> SFDITEM_REG__COA2_UDATA29 </item>
+//    <item> SFDITEM_REG__COA2_UDATA30 </item>
+//    <item> SFDITEM_REG__COA2_UDATA31 </item>
+//  </view>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA00  ------------------------------
+// SVD Line: 20935
+
+unsigned int COA3_UDATA00 __AT (0x1FFFF600);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA00  ----------------------------------
+// SVD Line: 20935
+
+//  <item> SFDITEM_REG__COA3_UDATA00
+//    <name> UDATA00 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF600) User Data 00 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA00 >> 0) & 0xFFFFFFFF), ((COA3_UDATA00 = (COA3_UDATA00 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA01  ------------------------------
+// SVD Line: 20943
+
+unsigned int COA3_UDATA01 __AT (0x1FFFF604);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA01  ----------------------------------
+// SVD Line: 20943
+
+//  <item> SFDITEM_REG__COA3_UDATA01
+//    <name> UDATA01 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF604) User Data 01 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA01 >> 0) & 0xFFFFFFFF), ((COA3_UDATA01 = (COA3_UDATA01 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA02  ------------------------------
+// SVD Line: 20951
+
+unsigned int COA3_UDATA02 __AT (0x1FFFF608);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA02  ----------------------------------
+// SVD Line: 20951
+
+//  <item> SFDITEM_REG__COA3_UDATA02
+//    <name> UDATA02 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF608) User Data 02 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA02 >> 0) & 0xFFFFFFFF), ((COA3_UDATA02 = (COA3_UDATA02 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA03  ------------------------------
+// SVD Line: 20959
+
+unsigned int COA3_UDATA03 __AT (0x1FFFF60C);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA03  ----------------------------------
+// SVD Line: 20959
+
+//  <item> SFDITEM_REG__COA3_UDATA03
+//    <name> UDATA03 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF60C) User Data 03 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA03 >> 0) & 0xFFFFFFFF), ((COA3_UDATA03 = (COA3_UDATA03 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA04  ------------------------------
+// SVD Line: 20967
+
+unsigned int COA3_UDATA04 __AT (0x1FFFF610);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA04  ----------------------------------
+// SVD Line: 20967
+
+//  <item> SFDITEM_REG__COA3_UDATA04
+//    <name> UDATA04 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF610) User Data 04 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA04 >> 0) & 0xFFFFFFFF), ((COA3_UDATA04 = (COA3_UDATA04 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA05  ------------------------------
+// SVD Line: 20975
+
+unsigned int COA3_UDATA05 __AT (0x1FFFF614);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA05  ----------------------------------
+// SVD Line: 20975
+
+//  <item> SFDITEM_REG__COA3_UDATA05
+//    <name> UDATA05 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF614) User Data 05 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA05 >> 0) & 0xFFFFFFFF), ((COA3_UDATA05 = (COA3_UDATA05 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA06  ------------------------------
+// SVD Line: 20983
+
+unsigned int COA3_UDATA06 __AT (0x1FFFF618);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA06  ----------------------------------
+// SVD Line: 20983
+
+//  <item> SFDITEM_REG__COA3_UDATA06
+//    <name> UDATA06 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF618) User Data 06 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA06 >> 0) & 0xFFFFFFFF), ((COA3_UDATA06 = (COA3_UDATA06 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA07  ------------------------------
+// SVD Line: 20991
+
+unsigned int COA3_UDATA07 __AT (0x1FFFF61C);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA07  ----------------------------------
+// SVD Line: 20991
+
+//  <item> SFDITEM_REG__COA3_UDATA07
+//    <name> UDATA07 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF61C) User Data 07 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA07 >> 0) & 0xFFFFFFFF), ((COA3_UDATA07 = (COA3_UDATA07 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA08  ------------------------------
+// SVD Line: 20999
+
+unsigned int COA3_UDATA08 __AT (0x1FFFF620);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA08  ----------------------------------
+// SVD Line: 20999
+
+//  <item> SFDITEM_REG__COA3_UDATA08
+//    <name> UDATA08 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF620) User Data 08 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA08 >> 0) & 0xFFFFFFFF), ((COA3_UDATA08 = (COA3_UDATA08 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA09  ------------------------------
+// SVD Line: 21007
+
+unsigned int COA3_UDATA09 __AT (0x1FFFF624);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA09  ----------------------------------
+// SVD Line: 21007
+
+//  <item> SFDITEM_REG__COA3_UDATA09
+//    <name> UDATA09 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF624) User Data 09 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA09 >> 0) & 0xFFFFFFFF), ((COA3_UDATA09 = (COA3_UDATA09 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA10  ------------------------------
+// SVD Line: 21015
+
+unsigned int COA3_UDATA10 __AT (0x1FFFF628);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA10  ----------------------------------
+// SVD Line: 21015
+
+//  <item> SFDITEM_REG__COA3_UDATA10
+//    <name> UDATA10 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF628) User Data 10 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA10 >> 0) & 0xFFFFFFFF), ((COA3_UDATA10 = (COA3_UDATA10 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA11  ------------------------------
+// SVD Line: 21023
+
+unsigned int COA3_UDATA11 __AT (0x1FFFF62C);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA11  ----------------------------------
+// SVD Line: 21023
+
+//  <item> SFDITEM_REG__COA3_UDATA11
+//    <name> UDATA11 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF62C) User Data 11 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA11 >> 0) & 0xFFFFFFFF), ((COA3_UDATA11 = (COA3_UDATA11 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA12  ------------------------------
+// SVD Line: 21031
+
+unsigned int COA3_UDATA12 __AT (0x1FFFF630);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA12  ----------------------------------
+// SVD Line: 21031
+
+//  <item> SFDITEM_REG__COA3_UDATA12
+//    <name> UDATA12 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF630) User Data 12 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA12 >> 0) & 0xFFFFFFFF), ((COA3_UDATA12 = (COA3_UDATA12 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA13  ------------------------------
+// SVD Line: 21039
+
+unsigned int COA3_UDATA13 __AT (0x1FFFF634);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA13  ----------------------------------
+// SVD Line: 21039
+
+//  <item> SFDITEM_REG__COA3_UDATA13
+//    <name> UDATA13 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF634) User Data 13 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA13 >> 0) & 0xFFFFFFFF), ((COA3_UDATA13 = (COA3_UDATA13 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA14  ------------------------------
+// SVD Line: 21047
+
+unsigned int COA3_UDATA14 __AT (0x1FFFF638);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA14  ----------------------------------
+// SVD Line: 21047
+
+//  <item> SFDITEM_REG__COA3_UDATA14
+//    <name> UDATA14 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF638) User Data 14 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA14 >> 0) & 0xFFFFFFFF), ((COA3_UDATA14 = (COA3_UDATA14 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA15  ------------------------------
+// SVD Line: 21055
+
+unsigned int COA3_UDATA15 __AT (0x1FFFF63C);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA15  ----------------------------------
+// SVD Line: 21055
+
+//  <item> SFDITEM_REG__COA3_UDATA15
+//    <name> UDATA15 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF63C) User Data 15 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA15 >> 0) & 0xFFFFFFFF), ((COA3_UDATA15 = (COA3_UDATA15 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA16  ------------------------------
+// SVD Line: 21063
+
+unsigned int COA3_UDATA16 __AT (0x1FFFF640);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA16  ----------------------------------
+// SVD Line: 21063
+
+//  <item> SFDITEM_REG__COA3_UDATA16
+//    <name> UDATA16 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF640) User Data 16 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA16 >> 0) & 0xFFFFFFFF), ((COA3_UDATA16 = (COA3_UDATA16 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA17  ------------------------------
+// SVD Line: 21071
+
+unsigned int COA3_UDATA17 __AT (0x1FFFF644);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA17  ----------------------------------
+// SVD Line: 21071
+
+//  <item> SFDITEM_REG__COA3_UDATA17
+//    <name> UDATA17 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF644) User Data 17 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA17 >> 0) & 0xFFFFFFFF), ((COA3_UDATA17 = (COA3_UDATA17 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA18  ------------------------------
+// SVD Line: 21079
+
+unsigned int COA3_UDATA18 __AT (0x1FFFF648);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA18  ----------------------------------
+// SVD Line: 21079
+
+//  <item> SFDITEM_REG__COA3_UDATA18
+//    <name> UDATA18 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF648) User Data 18 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA18 >> 0) & 0xFFFFFFFF), ((COA3_UDATA18 = (COA3_UDATA18 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA19  ------------------------------
+// SVD Line: 21087
+
+unsigned int COA3_UDATA19 __AT (0x1FFFF64C);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA19  ----------------------------------
+// SVD Line: 21087
+
+//  <item> SFDITEM_REG__COA3_UDATA19
+//    <name> UDATA19 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF64C) User Data 19 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA19 >> 0) & 0xFFFFFFFF), ((COA3_UDATA19 = (COA3_UDATA19 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA20  ------------------------------
+// SVD Line: 21095
+
+unsigned int COA3_UDATA20 __AT (0x1FFFF650);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA20  ----------------------------------
+// SVD Line: 21095
+
+//  <item> SFDITEM_REG__COA3_UDATA20
+//    <name> UDATA20 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF650) User Data 20 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA20 >> 0) & 0xFFFFFFFF), ((COA3_UDATA20 = (COA3_UDATA20 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA21  ------------------------------
+// SVD Line: 21103
+
+unsigned int COA3_UDATA21 __AT (0x1FFFF654);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA21  ----------------------------------
+// SVD Line: 21103
+
+//  <item> SFDITEM_REG__COA3_UDATA21
+//    <name> UDATA21 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF654) User Data 21 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA21 >> 0) & 0xFFFFFFFF), ((COA3_UDATA21 = (COA3_UDATA21 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA22  ------------------------------
+// SVD Line: 21111
+
+unsigned int COA3_UDATA22 __AT (0x1FFFF658);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA22  ----------------------------------
+// SVD Line: 21111
+
+//  <item> SFDITEM_REG__COA3_UDATA22
+//    <name> UDATA22 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF658) User Data 22 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA22 >> 0) & 0xFFFFFFFF), ((COA3_UDATA22 = (COA3_UDATA22 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA23  ------------------------------
+// SVD Line: 21119
+
+unsigned int COA3_UDATA23 __AT (0x1FFFF65C);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA23  ----------------------------------
+// SVD Line: 21119
+
+//  <item> SFDITEM_REG__COA3_UDATA23
+//    <name> UDATA23 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF65C) User Data 23 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA23 >> 0) & 0xFFFFFFFF), ((COA3_UDATA23 = (COA3_UDATA23 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA24  ------------------------------
+// SVD Line: 21127
+
+unsigned int COA3_UDATA24 __AT (0x1FFFF660);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA24  ----------------------------------
+// SVD Line: 21127
+
+//  <item> SFDITEM_REG__COA3_UDATA24
+//    <name> UDATA24 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF660) User Data 24 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA24 >> 0) & 0xFFFFFFFF), ((COA3_UDATA24 = (COA3_UDATA24 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA25  ------------------------------
+// SVD Line: 21135
+
+unsigned int COA3_UDATA25 __AT (0x1FFFF664);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA25  ----------------------------------
+// SVD Line: 21135
+
+//  <item> SFDITEM_REG__COA3_UDATA25
+//    <name> UDATA25 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF664) User Data 25 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA25 >> 0) & 0xFFFFFFFF), ((COA3_UDATA25 = (COA3_UDATA25 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA26  ------------------------------
+// SVD Line: 21143
+
+unsigned int COA3_UDATA26 __AT (0x1FFFF668);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA26  ----------------------------------
+// SVD Line: 21143
+
+//  <item> SFDITEM_REG__COA3_UDATA26
+//    <name> UDATA26 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF668) User Data 26 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA26 >> 0) & 0xFFFFFFFF), ((COA3_UDATA26 = (COA3_UDATA26 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA27  ------------------------------
+// SVD Line: 21151
+
+unsigned int COA3_UDATA27 __AT (0x1FFFF66C);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA27  ----------------------------------
+// SVD Line: 21151
+
+//  <item> SFDITEM_REG__COA3_UDATA27
+//    <name> UDATA27 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF66C) User Data 27 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA27 >> 0) & 0xFFFFFFFF), ((COA3_UDATA27 = (COA3_UDATA27 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA28  ------------------------------
+// SVD Line: 21159
+
+unsigned int COA3_UDATA28 __AT (0x1FFFF670);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA28  ----------------------------------
+// SVD Line: 21159
+
+//  <item> SFDITEM_REG__COA3_UDATA28
+//    <name> UDATA28 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF670) User Data 28 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA28 >> 0) & 0xFFFFFFFF), ((COA3_UDATA28 = (COA3_UDATA28 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA29  ------------------------------
+// SVD Line: 21167
+
+unsigned int COA3_UDATA29 __AT (0x1FFFF674);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA29  ----------------------------------
+// SVD Line: 21167
+
+//  <item> SFDITEM_REG__COA3_UDATA29
+//    <name> UDATA29 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF674) User Data 29 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA29 >> 0) & 0xFFFFFFFF), ((COA3_UDATA29 = (COA3_UDATA29 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA30  ------------------------------
+// SVD Line: 21175
+
+unsigned int COA3_UDATA30 __AT (0x1FFFF678);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA30  ----------------------------------
+// SVD Line: 21175
+
+//  <item> SFDITEM_REG__COA3_UDATA30
+//    <name> UDATA30 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF678) User Data 30 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA30 >> 0) & 0xFFFFFFFF), ((COA3_UDATA30 = (COA3_UDATA30 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ---------------------------  Register Item Address: COA3_UDATA31  ------------------------------
+// SVD Line: 21183
+
+unsigned int COA3_UDATA31 __AT (0x1FFFF67C);
+
+
+
+// -------------------------------  Register Item: COA3_UDATA31  ----------------------------------
+// SVD Line: 21183
+
+//  <item> SFDITEM_REG__COA3_UDATA31
+//    <name> UDATA31 </name>
+//    <i> [Bits 31..0] RO (@ 0x1FFFF67C) User Data 31 </i>
+//    <edit> 
+//      <loc> ( (unsigned int)((COA3_UDATA31 >> 0) & 0xFFFFFFFF), ((COA3_UDATA31 = (COA3_UDATA31 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
+//    </edit>
+//  </item>
+//  
+
+
+// ----------------------------------  Peripheral View: COA3  -------------------------------------
+// SVD Line: 20921
+
+//  <view> COA3
+//    <name> COA3 </name>
+//    <item> SFDITEM_REG__COA3_UDATA00 </item>
+//    <item> SFDITEM_REG__COA3_UDATA01 </item>
+//    <item> SFDITEM_REG__COA3_UDATA02 </item>
+//    <item> SFDITEM_REG__COA3_UDATA03 </item>
+//    <item> SFDITEM_REG__COA3_UDATA04 </item>
+//    <item> SFDITEM_REG__COA3_UDATA05 </item>
+//    <item> SFDITEM_REG__COA3_UDATA06 </item>
+//    <item> SFDITEM_REG__COA3_UDATA07 </item>
+//    <item> SFDITEM_REG__COA3_UDATA08 </item>
+//    <item> SFDITEM_REG__COA3_UDATA09 </item>
+//    <item> SFDITEM_REG__COA3_UDATA10 </item>
+//    <item> SFDITEM_REG__COA3_UDATA11 </item>
+//    <item> SFDITEM_REG__COA3_UDATA12 </item>
+//    <item> SFDITEM_REG__COA3_UDATA13 </item>
+//    <item> SFDITEM_REG__COA3_UDATA14 </item>
+//    <item> SFDITEM_REG__COA3_UDATA15 </item>
+//    <item> SFDITEM_REG__COA3_UDATA16 </item>
+//    <item> SFDITEM_REG__COA3_UDATA17 </item>
+//    <item> SFDITEM_REG__COA3_UDATA18 </item>
+//    <item> SFDITEM_REG__COA3_UDATA19 </item>
+//    <item> SFDITEM_REG__COA3_UDATA20 </item>
+//    <item> SFDITEM_REG__COA3_UDATA21 </item>
+//    <item> SFDITEM_REG__COA3_UDATA22 </item>
+//    <item> SFDITEM_REG__COA3_UDATA23 </item>
+//    <item> SFDITEM_REG__COA3_UDATA24 </item>
+//    <item> SFDITEM_REG__COA3_UDATA25 </item>
+//    <item> SFDITEM_REG__COA3_UDATA26 </item>
+//    <item> SFDITEM_REG__COA3_UDATA27 </item>
+//    <item> SFDITEM_REG__COA3_UDATA28 </item>
+//    <item> SFDITEM_REG__COA3_UDATA29 </item>
+//    <item> SFDITEM_REG__COA3_UDATA30 </item>
+//    <item> SFDITEM_REG__COA3_UDATA31 </item>
+//  </view>
+//  
+
+
+// ------------------------------   IRQ Num definition: A31G12x  ----------------------------------
+// SVD Line: 33
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                              Interrupt Number Definition                             -----
+// ------------------------------------------------------------------------------------------------
+
+
+
+// ------------------------  ARM Cortex-M0+ Specific Interrupt Numbers  ---------------------------
+
+//  <qitem> Reset_IRQ
+//    <name> Reset </name>
+//    <i> Reset Vector, invoked on Power up and warm reset </i>
+//    <loc> 1 </loc>
+//  </qitem>
+//  
+//  <qitem> NonMaskableInt_IRQ
+//    <name> NonMaskableInt </name>
+//    <i> Non maskable Interrupt, cannot be stopped or preempted </i>
+//    <loc> 2 </loc>
+//  </qitem>
+//  
+//  <qitem> HardFault_IRQ
+//    <name> HardFault </name>
+//    <i> Hard Fault, all classes of Fault </i>
+//    <loc> 3 </loc>
+//  </qitem>
+//  
+//  <qitem> SVCall_IRQ
+//    <name> SVCall </name>
+//    <i> System Service Call via SVC instruction </i>
+//    <loc> 11 </loc>
+//  </qitem>
+//  
+//  <qitem> PendSV_IRQ
+//    <name> PendSV </name>
+//    <i> Pendable request for system service </i>
+//    <loc> 14 </loc>
+//  </qitem>
+//  
+//  <qitem> SysTick_IRQ
+//    <name> SysTick </name>
+//    <i> System Tick Timer </i>
+//    <loc> 15 </loc>
+//  </qitem>
+//  
+
+
+// ---------------------------  A31G12x Specific Interrupt Numbers  -------------------------------
+
+//  <qitem> LVI_IRQ
+//    <name> LVI </name>
+//    <i> LVI Interrupt </i>
+//    <loc> 16 </loc>
+//  </qitem>
+//  
+//  <qitem> WUT_IRQ
+//    <name> WUT </name>
+//    <i> WUT Interrupt </i>
+//    <loc> 17 </loc>
+//  </qitem>
+//  
+//  <qitem> WDT_IRQ
+//    <name> WDT </name>
+//    <i> WDT Interrupt </i>
+//    <loc> 18 </loc>
+//  </qitem>
+//  
+//  <qitem> EINT0_IRQ
+//    <name> EINT0 </name>
+//    <i> EINT0 Interrupt </i>
+//    <loc> 19 </loc>
+//  </qitem>
+//  
+//  <qitem> EINT1_IRQ
+//    <name> EINT1 </name>
+//    <i> EINT1 Interrupt </i>
+//    <loc> 20 </loc>
+//  </qitem>
+//  
+//  <qitem> EINT2_IRQ
+//    <name> EINT2 </name>
+//    <i> EINT2 Interrupt </i>
+//    <loc> 21 </loc>
+//  </qitem>
+//  
+//  <qitem> EINT3_IRQ
+//    <name> EINT3 </name>
+//    <i> EINT3 Interrupt </i>
+//    <loc> 22 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER10_IRQ
+//    <name> TIMER10 </name>
+//    <i> TIMER10 Interrupt </i>
+//    <loc> 23 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER11_IRQ
+//    <name> TIMER11 </name>
+//    <i> TIMER11 Interrupt </i>
+//    <loc> 24 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER12_IRQ
+//    <name> TIMER12 </name>
+//    <i> TIMER12 Interrupt </i>
+//    <loc> 25 </loc>
+//  </qitem>
+//  
+//  <qitem> I2C0_IRQ
+//    <name> I2C0 </name>
+//    <i> I2C0 Interrupt </i>
+//    <loc> 26 </loc>
+//  </qitem>
+//  
+//  <qitem> USART10_IRQ
+//    <name> USART10 </name>
+//    <i> USART10 Interrupt </i>
+//    <loc> 27 </loc>
+//  </qitem>
+//  
+//  <qitem> WT_IRQ
+//    <name> WT </name>
+//    <i> WT Interrupt </i>
+//    <loc> 28 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER30_IRQ
+//    <name> TIMER30 </name>
+//    <i> TIMER30 Interrupt </i>
+//    <loc> 29 </loc>
+//  </qitem>
+//  
+//  <qitem> I2C1_IRQ
+//    <name> I2C1 </name>
+//    <i> I2C1 Interrupt </i>
+//    <loc> 30 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER20_IRQ
+//    <name> TIMER20 </name>
+//    <i> TIMER20 Interrupt </i>
+//    <loc> 31 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER21_IRQ
+//    <name> TIMER21 </name>
+//    <i> TIMER21 Interrupt </i>
+//    <loc> 32 </loc>
+//  </qitem>
+//  
+//  <qitem> USART11_IRQ
+//    <name> USART11 </name>
+//    <i> USART11 Interrupt </i>
+//    <loc> 33 </loc>
+//  </qitem>
+//  
+//  <qitem> ADC_IRQ
+//    <name> ADC </name>
+//    <i> ADC Interrupt </i>
+//    <loc> 34 </loc>
+//  </qitem>
+//  
+//  <qitem> UART0_IRQ
+//    <name> UART0 </name>
+//    <i> UART0 Interrupt </i>
+//    <loc> 35 </loc>
+//  </qitem>
+//  
+//  <qitem> UART1_IRQ
+//    <name> UART1 </name>
+//    <i> UART1 Interrupt </i>
+//    <loc> 36 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER13_IRQ
+//    <name> TIMER13 </name>
+//    <i> TIMER13 Interrupt </i>
+//    <loc> 37 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER14_IRQ
+//    <name> TIMER14 </name>
+//    <i> TIMER14 Interrupt </i>
+//    <loc> 38 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER15_IRQ
+//    <name> TIMER15 </name>
+//    <i> TIMER15 Interrupt </i>
+//    <loc> 39 </loc>
+//  </qitem>
+//  
+//  <qitem> TIMER16_IRQ
+//    <name> TIMER16 </name>
+//    <i> TIMER16 Interrupt </i>
+//    <loc> 40 </loc>
+//  </qitem>
+//  
+//  <qitem> I2C2_IRQ
+//    <name> I2C2 </name>
+//    <i> I2C2 Interrupt </i>
+//    <loc> 41 </loc>
+//  </qitem>
+//  
+//  <qitem> USART12_IRQ
+//    <name> USART12 </name>
+//    <i> USART12 Interrupt </i>
+//    <loc> 42 </loc>
+//  </qitem>
+//  
+//  <qitem> USART13_IRQ
+//    <name> USART13 </name>
+//    <i> USART13 Interrupt </i>
+//    <loc> 43 </loc>
+//  </qitem>
+//  
+//  <irqtable> A31G12x_IRQTable
+//    <name> A31G12x Interrupt Table </name>
+//    <nvicPrioBits> 2 </nvicPrioBits>
+//    <qitem> Reset_IRQ </qitem>
+//    <qitem> NonMaskableInt_IRQ </qitem>
+//    <qitem> HardFault_IRQ </qitem>
+//    <qitem> SVCall_IRQ </qitem>
+//    <qitem> PendSV_IRQ </qitem>
+//    <qitem> SysTick_IRQ </qitem>
+//    <qitem> LVI_IRQ </qitem>
+//    <qitem> WUT_IRQ </qitem>
+//    <qitem> WDT_IRQ </qitem>
+//    <qitem> EINT0_IRQ </qitem>
+//    <qitem> EINT1_IRQ </qitem>
+//    <qitem> EINT2_IRQ </qitem>
+//    <qitem> EINT3_IRQ </qitem>
+//    <qitem> TIMER10_IRQ </qitem>
+//    <qitem> TIMER11_IRQ </qitem>
+//    <qitem> TIMER12_IRQ </qitem>
+//    <qitem> I2C0_IRQ </qitem>
+//    <qitem> USART10_IRQ </qitem>
+//    <qitem> WT_IRQ </qitem>
+//    <qitem> TIMER30_IRQ </qitem>
+//    <qitem> I2C1_IRQ </qitem>
+//    <qitem> TIMER20_IRQ </qitem>
+//    <qitem> TIMER21_IRQ </qitem>
+//    <qitem> USART11_IRQ </qitem>
+//    <qitem> ADC_IRQ </qitem>
+//    <qitem> UART0_IRQ </qitem>
+//    <qitem> UART1_IRQ </qitem>
+//    <qitem> TIMER13_IRQ </qitem>
+//    <qitem> TIMER14_IRQ </qitem>
+//    <qitem> TIMER15_IRQ </qitem>
+//    <qitem> TIMER16_IRQ </qitem>
+//    <qitem> I2C2_IRQ </qitem>
+//    <qitem> USART12_IRQ </qitem>
+//    <qitem> USART13_IRQ </qitem>
+//  </irqtable>
+
+
+// -------------------------------------   Menu: A31G12x  -----------------------------------------
+// SVD Line: 33
+
+
+
+// -------------------------------  Peripheral Menu: 'A31G12x'  -----------------------------------
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       Main Menu                                      -----
+// ------------------------------------------------------------------------------------------------
+
+//  <b> A/D Converter
+//    <m> ADC </m>
+//  </b>
+//  
+//  <b> CRC & Checksum
+//    <m> CRC </m>
+//  </b>
+//  
+//  <b> Configuration Option Area
+//    <m> COA0 </m>
+//    <m> COA1 </m>
+//    <m> COA2 </m>
+//    <m> COA3 </m>
+//  </b>
+//  
+//  <b> Flash Memory Controller
+//    <m> FMC </m>
+//  </b>
+//  
+//  <b> I2C
+//    <m> I2C0 </m>
+//    <m> I2C1 </m>
+//    <m> I2C2 </m>
+//    <m> I2Cn </m>
+//  </b>
+//  
+//  <b> Interrupt Controller
+//    <m> INTC </m>
+//  </b>
+//  
+//  <b> LCD Driver
+//    <m> LCD </m>
+//  </b>
+//  
+//  <b> PCU & GPIO
+//    <m> PA </m>
+//    <m> PB </m>
+//    <m> PC </m>
+//    <m> PD </m>
+//    <m> PE </m>
+//    <m> PF </m>
+//    <m> Pn </m>
+//  </b>
+//  
+//  <b> SCU
+//    <m> SCUCC </m>
+//    <m> SCUCG </m>
+//    <m> SCULV </m>
+//  </b>
+//  
+//  <b> Timer/Counter
+//    <m> TIMER1n </m>
+//    <m> TIMER2n </m>
+//    <m> TIMER3n </m>
+//    <m> TIMER10 </m>
+//    <m> TIMER11 </m>
+//    <m> TIMER12 </m>
+//    <m> TIMER13 </m>
+//    <m> TIMER14 </m>
+//    <m> TIMER15 </m>
+//    <m> TIMER16 </m>
+//    <m> TIMER20 </m>
+//    <m> TIMER21 </m>
+//    <m> TIMER30 </m>
+//  </b>
+//  
+//  <b> UART
+//    <m> UART0 </m>
+//    <m> UART1 </m>
+//    <m> UARTn </m>
+//  </b>
+//  
+//  <b> USART & SPI
+//    <m> USART1n </m>
+//    <m> USART10 </m>
+//    <m> USART11 </m>
+//    <m> USART12 </m>
+//    <m> USART13 </m>
+//  </b>
+//  
+//  <b> Watch Timer
+//    <m> WT </m>
+//  </b>
+//  
+//  <b> Watch-Dog Timer
+//    <m> WDT </m>
+//  </b>
+//  
diff --git a/Project/SDK_V2_5_0/Debugging_Info/A31G12x.svd b/Project/SDK_V2_5_0/Debugging_Info/A31G12x.svd
new file mode 100644
index 0000000..45b89d4
--- /dev/null
+++ b/Project/SDK_V2_5_0/Debugging_Info/A31G12x.svd
@@ -0,0 +1,21194 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!-- File naming: <vendor>_<part/series name>.svd -->
+<!--
+  Copyright (C) 2012 ARM Limited. All rights reserved.
+
+  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+           This is a description of a none-existent and incomplete device
+		   for demonstration purposes only.
+		   
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used 
+     to endorse or promote products derived from this software without 
+     specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
+ -->
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>VENDOR ABOV Semiconductor Co., Ltd.</vendor>
+  <!-- device vendor name -->
+  <vendorID>ABOV</vendorID>
+  <!-- device vendor short name -->
+  <name>A31G12x</name>
+  <!-- name of part-->
+  <series>A31G12x</series>
+  <!-- device series the device belongs to -->
+  <version>1.0</version>
+  <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+  <description>ARM 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 40MHz, etc. </description>
+  <licenseText>
+    <!-- this license text will appear in header file. \n force line breaks -->
+    ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+    processor based microcontroller, but can be equally used for other\n
+    suitable  processor architectures. This file can be freely distributed.\n
+    Modifications to this file shall be clearly marked.\n
+    \n
+    THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+  </licenseText>
+  <cpu>
+    <!-- details about the cpu embedded in the device -->
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>8</addressUnitBits>
+  <!-- byte addressable memory -->
+  <width>32</width>
+  <!-- bus width is 32 bits -->
+  <!-- default settings implicitly inherited by subsequent sections -->
+  <size>32</size>
+  <!-- this is the default size (number of bits) of all peripherals and register that do not define "size" themselves -->
+  <access>read-write</access>
+  <!-- default access permission for all subsequent registers -->
+  <resetValue>0x0</resetValue>
+  <!-- by default all bits of the registers are initialized to 0 on reset -->
+  <resetMask>0xffffffff</resetMask>
+  <!-- by default all 32Bits of the registers are used -->
+  <peripherals>
+    <peripheral>
+      <name>INTC</name>
+      <version>1.0</version>
+      <description>Interrupt Controller</description>
+      <groupName>Interrupt Controller</groupName>
+      <baseAddress>0x40001000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x500</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EINT0</name>
+        <description>EINT0 Interrupt</description>
+        <value>03</value>
+      </interrupt>
+      <interrupt>
+        <name>EINT1</name>
+        <description>EINT1 Interrupt</description>
+        <value>04</value>
+      </interrupt>
+      <interrupt>
+        <name>EINT2</name>
+        <description>EINT2 Interrupt</description>
+        <value>05</value>
+      </interrupt>
+      <interrupt>
+        <name>EINT3</name>
+        <description>EINT3 Interrupt</description>
+        <value>06</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PBTRIG</name>
+          <description>Port B Interrupt Trigger Selection Register</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ITRIG11</name>
+              <description>Port B Interrupt Trigger Selection 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG10</name>
+              <description>Port B Interrupt Trigger Selection 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG9</name>
+              <description>Port B Interrupt Trigger Selection 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG8</name>
+              <description>Port B Interrupt Trigger Selection 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG7</name>
+              <description>Port B Interrupt Trigger Selection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG6</name>
+              <description>Port B Interrupt Trigger Selection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG5</name>
+              <description>Port B Interrupt Trigger Selection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG4</name>
+              <description>Port B Interrupt Trigger Selection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG3</name>
+              <description>Port B Interrupt Trigger Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG2</name>
+              <description>Port B Interrupt Trigger Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG1</name>
+              <description>Port B Interrupt Trigger Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG0</name>
+              <description>Port B Interrupt Trigger Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCTRIG</name>
+          <description>Port C Interrupt Trigger Selection Register</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ITRIG3</name>
+              <description>Port C Interrupt Trigger Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG2</name>
+              <description>Port C Interrupt Trigger Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG1</name>
+              <description>Port C Interrupt Trigger Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG0</name>
+              <description>Port C Interrupt Trigger Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PETRIG</name>
+          <description>Port E Interrupt Trigger Selection Register</description>
+          <addressOffset>0x010</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ITRIG3</name>
+              <description>Port E Interrupt Trigger Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG2</name>
+              <description>Port E Interrupt Trigger Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG1</name>
+              <description>Port E Interrupt Trigger Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ITRIG0</name>
+              <description>Port E Interrupt Trigger Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Edge</name>
+                  <description>Edge trigger interrupt</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level</name>
+                  <description>Level trigger interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PBCR</name>
+          <description>Port B Interrupt Control Register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>INTCTL11</name>
+              <description>Port B Interrupt Control 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL10</name>
+              <description>Port B Interrupt Control 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL9</name>
+              <description>Port B Interrupt Control 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL8</name>
+              <description>Port B Interrupt Control 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL7</name>
+              <description>Port B Interrupt Control 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL6</name>
+              <description>Port B Interrupt Control 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL5</name>
+              <description>Port B Interrupt Control 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL4</name>
+              <description>Port B Interrupt Control 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL3</name>
+              <description>Port B Interrupt Control 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL2</name>
+              <description>Port B Interrupt Control 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL1</name>
+              <description>Port B Interrupt Control 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL0</name>
+              <description>Port B Interrupt Control 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCCR</name>
+          <description>Port C Interrupt Control Register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>INTCTL3</name>
+              <description>Port C Interrupt Control 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL2</name>
+              <description>Port C Interrupt Control 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL1</name>
+              <description>Port C Interrupt Control 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL0</name>
+              <description>Port C Interrupt Control 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PECR</name>
+          <description>Port E Interrupt Control Register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>INTCTL3</name>
+              <description>Port E Interrupt Control 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL2</name>
+              <description>Port E Interrupt Control 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL1</name>
+              <description>Port E Interrupt Control 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTCTL0</name>
+              <description>Port E Interrupt Control 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable external interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FallingEdgeLowLevel</name>
+                  <description>Interrupt on falling edge or on low level</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdgeHighLevel</name>
+                  <description>Interrupt on rising edge or on high level</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdgeNoLevel</name>
+                  <description>Interrupt on both falling and rising edge, No level interrupt</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PBFLAG</name>
+          <description>Port B Interrupt Flag Register</description>
+          <addressOffset>0x204</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>FLAG11</name>
+              <description>Port B Interrupt Flag 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG10</name>
+              <description>Port B Interrupt Flag 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG9</name>
+              <description>Port B Interrupt Flag 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG8</name>
+              <description>Port B Interrupt Flag 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG7</name>
+              <description>Port B Interrupt Flag 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG6</name>
+              <description>Port B Interrupt Flag 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG5</name>
+              <description>Port B Interrupt Flag 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG4</name>
+              <description>Port B Interrupt Flag 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG3</name>
+              <description>Port B Interrupt Flag 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG2</name>
+              <description>Port B Interrupt Flag 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG1</name>
+              <description>Port B Interrupt Flag 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG0</name>
+              <description>Port B Interrupt Flag 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCFLAG</name>
+          <description>Port C Interrupt Flag Register</description>
+          <addressOffset>0x208</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>FLAG3</name>
+              <description>Port C Interrupt Flag 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG2</name>
+              <description>Port C Interrupt Flag 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG1</name>
+              <description>Port C Interrupt Flag 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG0</name>
+              <description>Port C Interrupt Flag 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PEFLAG</name>
+          <description>Port E Interrupt Flag Register</description>
+          <addressOffset>0x210</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>FLAG3</name>
+              <description>Port E Interrupt Flag 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG2</name>
+              <description>Port E Interrupt Flag 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG1</name>
+              <description>Port E Interrupt Flag 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FLAG0</name>
+              <description>Port E Interrupt Flag 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EINT0CONF1</name>
+          <description>External Interrupt 0 Configuration Register 1</description>
+          <addressOffset>0x300</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CONF7</name>
+              <description>External Interrupt 0 Configuration 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF6</name>
+              <description>External Interrupt 0 Configuration 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF5</name>
+              <description>External Interrupt 0 Configuration 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF4</name>
+              <description>External Interrupt 0 Configuration 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF3</name>
+              <description>External Interrupt 0 Configuration 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF2</name>
+              <description>External Interrupt 0 Configuration 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF1</name>
+              <description>External Interrupt 0 Configuration 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF0</name>
+              <description>External Interrupt 0 Configuration 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EINT1CONF1</name>
+          <description>External Interrupt 1 Configuration Register 1</description>
+          <addressOffset>0x304</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CONF7</name>
+              <description>External Interrupt 1 Configuration 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF6</name>
+              <description>External Interrupt 1 Configuration 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF5</name>
+              <description>External Interrupt 1 Configuration 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF4</name>
+              <description>External Interrupt 1 Configuration 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF3</name>
+              <description>External Interrupt 1 Configuration 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF2</name>
+              <description>External Interrupt 1 Configuration 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF1</name>
+              <description>External Interrupt 1 Configuration 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF0</name>
+              <description>External Interrupt 1 Configuration 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EINT2CONF1</name>
+          <description>External Interrupt 2 Configuration Register 1</description>
+          <addressOffset>0x308</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CONF7</name>
+              <description>External Interrupt 2 Configuration 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF6</name>
+              <description>External Interrupt 2 Configuration 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF5</name>
+              <description>External Interrupt 2 Configuration 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF4</name>
+              <description>External Interrupt 2 Configuration 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF3</name>
+              <description>External Interrupt 2 Configuration 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF2</name>
+              <description>External Interrupt 2 Configuration 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF1</name>
+              <description>External Interrupt 2 Configuration 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF0</name>
+              <description>External Interrupt 2 Configuration 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EINT3CONF1</name>
+          <description>External Interrupt 3 Configuration Register 1</description>
+          <addressOffset>0x30c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CONF7</name>
+              <description>External Interrupt 3 Configuration 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF6</name>
+              <description>External Interrupt 3 Configuration 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF5</name>
+              <description>External Interrupt 3 Configuration 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF4</name>
+              <description>External Interrupt 3 Configuration 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF3</name>
+              <description>External Interrupt 3 Configuration 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF2</name>
+              <description>External Interrupt 3 Configuration 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF1</name>
+              <description>External Interrupt 3 Configuration 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF0</name>
+              <description>External Interrupt 3 Configuration 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EINT0CONF2</name>
+          <description>External Interrupt 0 Configuration Register 2</description>
+          <addressOffset>0x310</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CONF11</name>
+              <description>External Interrupt 0 Configuration 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF10</name>
+              <description>External Interrupt 0 Configuration 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF9</name>
+              <description>External Interrupt 0 Configuration 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF8</name>
+              <description>External Interrupt 0 Configuration 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EINT1CONF2</name>
+          <description>External Interrupt 1 Configuration Register 2</description>
+          <addressOffset>0x314</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CONF11</name>
+              <description>External Interrupt 1 Configuration 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF10</name>
+              <description>External Interrupt 1 Configuration 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF9</name>
+              <description>External Interrupt 1 Configuration 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF8</name>
+              <description>External Interrupt 1 Configuration 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EINT2CONF2</name>
+          <description>External Interrupt 2 Configuration Register 2</description>
+          <addressOffset>0x318</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CONF11</name>
+              <description>External Interrupt 2 Configuration 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF10</name>
+              <description>External Interrupt 2 Configuration 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF9</name>
+              <description>External Interrupt 2 Configuration 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF8</name>
+              <description>External Interrupt 2 Configuration 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EINT3CONF2</name>
+          <description>External Interrupt 3 Configuration Register 2</description>
+          <addressOffset>0x31c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CONF11</name>
+              <description>External Interrupt 3 Configuration 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF10</name>
+              <description>External Interrupt 3 Configuration 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF9</name>
+              <description>External Interrupt 3 Configuration 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CONF8</name>
+              <description>External Interrupt 3 Configuration 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PA</name>
+                  <description>Select PA.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PB</name>
+                  <description>Select PB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PC</name>
+                  <description>Select PC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PD</name>
+                  <description>Select PD.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PE</name>
+                  <description>Select PE.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PF</name>
+                  <description>Select PF.</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MSK</name>
+          <description>Interrupt Source Mask Register</description>
+          <addressOffset>0x400</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>IMSK31_NULL</name>
+              <description>Interrupt Source Mask 31 (RSVD)</description>
+              <bitRange>[31:31]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK30_NULL</name>
+              <description>Interrupt Source Mask 30 (RSVD)</description>
+              <bitRange>[30:30]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK29_NULL</name>
+              <description>Interrupt Source Mask 29 (RSVD)</description>
+              <bitRange>[29:29]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK28_NULL</name>
+              <description>Interrupt Source Mask 28 (RSVD)</description>
+              <bitRange>[28:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK27_USART13</name>
+              <description>Interrupt Source Mask 27 (USART13)</description>
+              <bitRange>[27:27]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK26_USART12</name>
+              <description>Interrupt Source Mask 26 (USART12)</description>
+              <bitRange>[26:26]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK25_I2C2</name>
+              <description>Interrupt Source Mask 25 (I2C2)</description>
+              <bitRange>[25:25]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK24_TIMER16</name>
+              <description>Interrupt Source Mask 24 (TIMER16)</description>
+              <bitRange>[24:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK23_TIMER15</name>
+              <description>Interrupt Source Mask 23 (TIMER15)</description>
+              <bitRange>[23:23]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK22_TIMER14</name>
+              <description>Interrupt Source Mask 22 (TIMER14)</description>
+              <bitRange>[22:22]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK21_TIMER13</name>
+              <description>Interrupt Source Mask 21 (TIMER13)</description>
+              <bitRange>[21:21]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK20_UART1</name>
+              <description>Interrupt Source Mask 20 (UART1)</description>
+              <bitRange>[20:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK19_UART0</name>
+              <description>Interrupt Source Mask 19 (UART0)</description>
+              <bitRange>[19:19]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK18_ADC</name>
+              <description>Interrupt Source Mask 18 (ADC)</description>
+              <bitRange>[18:18]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK17_USART11</name>
+              <description>Interrupt Source Mask 17 (USART11)</description>
+              <bitRange>[17:17]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK16_TIMER21</name>
+              <description>Interrupt Source Mask 16 (TIMER21)</description>
+              <bitRange>[16:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK15_TIMER20</name>
+              <description>Interrupt Source Mask 15 (TIMER20)</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK14_I2C1</name>
+              <description>Interrupt Source Mask 14 (I2C1)</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK13_TIMER30</name>
+              <description>Interrupt Source Mask 13 (TIMER30)</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK12_WT</name>
+              <description>Interrupt Source Mask 12 (WT)</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK11_USART10</name>
+              <description>Interrupt Source Mask 11 (USART10)</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK10_I2C0</name>
+              <description>Interrupt Source Mask 10 (I2C0)</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK9_TIMER12</name>
+              <description>Interrupt Source Mask 9 (TIMER12)</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK8_TIMER11</name>
+              <description>Interrupt Source Mask 8 (TIMER11)</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK7_TIMER10</name>
+              <description>Interrupt Source Mask 7 (TIMER10)</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK6_EINT3</name>
+              <description>Interrupt Source Mask 6 (EINT3)</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK5_EINT2</name>
+              <description>Interrupt Source Mask 5 (EINT2)</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK4_EINT1</name>
+              <description>Interrupt Source Mask 4 (EINT1)</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK3_EINT0</name>
+              <description>Interrupt Source Mask 3 (EINT0)</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK2_WDT</name>
+              <description>Interrupt Source Mask 2 (WDT)</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK1_WUT</name>
+              <description>Interrupt Source Mask 1 (WUT)</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>IMSK0_LVI</name>
+              <description>Interrupt Source Mask 0 (LVI)</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask Interrupt Source</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask Interrupt Source</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SCUCC</name>
+      <version>1.0</version>
+      <description>System Control Unit: Chip Configuration</description>
+      <groupName>SCU</groupName>
+      <baseAddress>0x4000f000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WUT</name>
+        <description>WUT Interrupt</description>
+        <value>01</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>VENDORID</name>
+          <description>Vendor Identification Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x41424f56</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>VENDID</name>
+              <description>Vendor Identification</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHIPID</name>
+          <description>Chip Identification Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x4d31f002</resetValue>
+          <resetMask>0xfffffff0</resetMask>
+          <fields>
+            <field>
+              <name>CHIPID</name>
+              <description>Chip Identification</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REVNR</name>
+          <description>Revision Number Register</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffff00</resetMask>
+          <fields>
+            <field>
+              <name>REVNO</name>
+              <description>Chip Revision Number</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PMREMAP</name>
+          <description>Program Memory Remap Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0xe2f1)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0xe2f1)</description>
+                  <value>0xe2f1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>nPMREM</name>
+              <description>Write Complement Key</description>
+              <bitRange>[15:08]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>BootROM</name>
+                  <description>Boot ROM is re-mapped to address 0x0. (0x96)</description>
+                  <value>0x96</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FlashMemory</name>
+                  <description>Flash Memory is re-mapped to address 0x0.</description>
+                  <value>0x00</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMREM</name>
+              <description>Program Memory Remap</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>BootROM</name>
+                  <description>Boot ROM is re-mapped to address 0x0. (0x69)</description>
+                  <value>0x69</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FlashMemory</name>
+                  <description>Flash Memory is re-mapped to address 0x0.</description>
+                  <value>0x00</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BTPSCR</name>
+          <description>Boot Pin Status and Control Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x40</resetValue>
+          <resetMask>0xffffffde</resetMask>
+          <fields>
+            <field>
+              <name>BFIND</name>
+              <description>BOOT Pin Function Indicator</description>
+              <bitRange>[06:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PORorEXTR</name>
+                  <description>Check the BOOT pin when a system reset occurs by nRESET including POR.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>POR</name>
+                  <description>Check the BOOT pin when a system reset occurs only by POR.</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BTPSTA</name>
+              <description>BOOT Pin Status</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Low</name>
+                  <description>The BOOT pin is low level.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>High</name>
+                  <description>The BOOT pin is high level.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSTSSR</name>
+          <description>Reset Source Status Register</description>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffc0</resetMask>
+          <fields>
+            <field>
+              <name>MONSTA</name>
+              <description>Clock Monitoring Reset Status</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NotDetected</name>
+                  <description>Not detected.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Detected</name>
+                  <description>CMR was detected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWSTA</name>
+              <description>Software Reset Status</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NotDetected</name>
+                  <description>Not detected.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Detected</name>
+                  <description>SWR was detected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTSTA</name>
+              <description>External Pin Reset Status</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NotDetected</name>
+                  <description>Not detected.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Detected</name>
+                  <description>EXTR was detected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDTSTA</name>
+              <description>Watch-Dog Timer Reset Status</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NotDetected</name>
+                  <description>Not detected.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Detected</name>
+                  <description>WDTR was detected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVRSTA</name>
+              <description>LVR Reset Status</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NotDetected</name>
+                  <description>Not detected.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Detected</name>
+                  <description>LVR was detected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PORSTA</name>
+              <description>POR Reset Status</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NotDetected</name>
+                  <description>Not detected.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Detected</name>
+                  <description>POR was detected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMISRCR</name>
+          <description>NMI Source Selection Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>NMICON</name>
+              <description>Non-Maskable Interrupt (NMI) Control</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable NMI.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable NMI.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MONINT</name>
+              <description>Clock Monitoring Interrupt Selection</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NotSelect</name>
+                  <description>Non-select clock monitoring interrupt for NMI source.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Select</name>
+                  <description>Select clock monitoring interrupt for NMI source.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMISRC</name>
+              <description>Non-Maskable Interrupt Source Selection</description>
+              <bitRange>[04:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWRSTR</name>
+          <description>Software Reset Register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0x9eb3)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0x9eb3)</description>
+                  <value>0x9eb3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset (System Reset)</description>
+              <bitRange>[07:00]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Generate</name>
+                  <description>A software reset will be generated for all peripheral and core. (0x2d)</description>
+                  <value>0x2d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0x00</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRSTVR</name>
+          <description>System Reset Validation Register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x55</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>VALID</name>
+              <description>System Reset Validation</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WUTCR</name>
+          <description>Wake-Up Timer Control Register</description>
+          <addressOffset>0x2c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WUTIEN</name>
+              <description>Wake-Up Timer Interrupt Enable</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable Wake-Up Timer interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable Wake-Up Timer interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTRLD</name>
+              <description>Counter Reload</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload</name>
+                  <description>Reload data to counter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WUTIFLAG</name>
+              <description>Wake-Up Timer Interrupt Flag</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WUTDR</name>
+          <description>Wake-Up Timer Data Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x138</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WUTDATA</name>
+              <description>Wake-Up Timer Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIRCTRM</name>
+          <description>High Frequency Internal RC Trim Register (HIRCNFIG)</description>
+          <addressOffset>0xa8</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffff00</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0xa6b5)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0xa6b5)</description>
+                  <value>0xa6b5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>nTRMH</name>
+              <description>Write Complement Key</description>
+              <bitRange>[15:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTRMH</name>
+              <description>Factory HIRC Coarse Trim</description>
+              <bitRange>[07:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FTRMH</name>
+              <description>Factory HIRC Fine Trim</description>
+              <bitRange>[04:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTRCTRM</name>
+          <description>Watch-Dog Timer RC Trim Register (WDTRCNFIG)</description>
+          <addressOffset>0xac</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffff08</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0x4c3d)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0x4c3d)</description>
+                  <value>0x4c3d</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>nTRMW</name>
+              <description>Write Complement Key</description>
+              <bitRange>[15:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTRMW</name>
+              <description>Factory WDTRC Coarse Trim</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FTRMW</name>
+              <description>Factory WDTRC Fine Trim</description>
+              <bitRange>[02:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SCUCG</name>
+      <version>1.0</version>
+      <description>System Control Unit: Clock Generation</description>
+      <groupName>SCU</groupName>
+      <baseAddress>0x40001800</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCCR</name>
+          <description>System Clock Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0x570a)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0x570a)</description>
+                  <value>0x570a</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCLKSEL</name>
+              <description>Main Clock Selection, MCLK</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>HIRC</name>
+                  <description>High Frequency Internal RC Oscillator (40MHz), HIRC</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XMOSC</name>
+                  <description>External Main Oscillator (2 - 40MHz), XMOSC</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XSOSC</name>
+                  <description>External Sub Oscillator (32.768kHz), XSOSC</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDTRC</name>
+                  <description>Internal Watch-Dog Timer RC Oscillator (40kHz), WDTRC</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKSRCR</name>
+          <description>Clock Source Control Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xc</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0xa507)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0xa507)</description>
+                  <value>0xa507</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HIRCSEL</name>
+              <description>HIRC Frequency Selection</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>HIRC1</name>
+                  <description>40MHz HIRC</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIRC2</name>
+                  <description>20MHz HIRC</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIRC4</name>
+                  <description>10MHz HIRC</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIRC8</name>
+                  <description>5MHz HIRC</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>XMFRNG</name>
+              <description>Main Oscillator Type and Frequency Range Selection</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Xtal</name>
+                  <description>X-tal for XMOSC, 2 to 16MHz</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clock</name>
+                  <description>External Clock for XMOSC, 2MHz to 40MHz</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDTRCEN</name>
+              <description>WDTRC Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable WDTRC.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable WDTRC.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HIRCEN</name>
+              <description>HIRC Enable</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable HIRC.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable HIRC.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>XMOSCEN</name>
+              <description>XMOSC Enable</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable XMOSC.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable XMOSC.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>XSOSCEN</name>
+              <description>XSOSC Enable</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable XSOSC.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable XSOSC.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCDIVR1</name>
+          <description>System Clock Divide Register 1</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WLDIV</name>
+              <description>Clock Divide for Watch Timer and LCD Driver, Divider 2</description>
+              <bitRange>[06:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MCLK64</name>
+                  <description>MCLK/64</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCLK128</name>
+                  <description>MCLK/128</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCLK256</name>
+                  <description>MCLK/256</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCLK512</name>
+                  <description>MCLK/512</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCLK1024</name>
+                  <description>MCLK/1024</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HDIV</name>
+              <description>Clock Divide for HCLK, Divider 0</description>
+              <bitRange>[02:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MCLK16</name>
+                  <description>MCLK/16</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCLK8</name>
+                  <description>MCLK/8</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCLK4</name>
+                  <description>MCLK/4</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCLK2</name>
+                  <description>MCLK/2</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCLK1</name>
+                  <description>MCLK/1</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCDIVR2</name>
+          <description>System Clock Divide Register 2</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>SYSTDIV</name>
+              <description>Clock Divide for SysTick Timer, Divider 3</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>HCLK1</name>
+                  <description>HCLK/1</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK2</name>
+                  <description>HCLK/2</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK4</name>
+                  <description>HCLK/4</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK8</name>
+                  <description>HCLK/8</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PDIV</name>
+              <description>Clock Divide for PCLK, Divider 1</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>HCLK1</name>
+                  <description>HCLK/1</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK2</name>
+                  <description>HCLK/2</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK4</name>
+                  <description>HCLK/4</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK8</name>
+                  <description>HCLK/8</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKOCR</name>
+          <description>Clock Output Control Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CLKOEN</name>
+              <description>Clock Output Enable</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock output.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock output.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POLSEL</name>
+              <description>Clock Output Polarity Selection when Disable</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Low</name>
+                  <description>Low level during disable</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>High</name>
+                  <description>High level during disable</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKODIV</name>
+              <description>Output Clock Divide, Divider 4</description>
+              <bitRange>[05:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SelectedClock1</name>
+                  <description>Selected Clock/1</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SelectedClock2</name>
+                  <description>Selected Clock/2</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SelectedClock4</name>
+                  <description>Selected Clock/4</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SelectedClock8</name>
+                  <description>Selected Clock/8</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SelectedClock16</name>
+                  <description>Selected Clock/16</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SelectedClock32</name>
+                  <description>Selected Clock/32</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SelectedClock64</name>
+                  <description>Selected Clock/64</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SelectedClock128</name>
+                  <description>Selected Clock/128</description>
+                  <value>7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKOS</name>
+              <description>Clock Output Selection</description>
+              <bitRange>[02:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MCLK</name>
+                  <description>Select MCLK.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDTRC</name>
+                  <description>Select WDTRC.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIRC</name>
+                  <description>Select HIRC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK</name>
+                  <description>Select HCLK.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PCLK</name>
+                  <description>Select PCLK.</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMONCR</name>
+          <description>Clock Monitoring Control Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MONEN</name>
+              <description>Clock Monitoring Enable</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock monitoring.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock monitoring.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MACTS</name>
+              <description>Clock Monitoring Action Selection</description>
+              <bitRange>[06:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FlagChk</name>
+                  <description>No action by clock monitoring, but flags will be set/cleared on condition</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RstGen</name>
+                  <description>Reset generation by clock monitoring</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SysClkChg</name>
+                  <description>The system clock will be changed to the WDTRC regardless of MCLKSEL[1:0] bits of system clock control register (SCU_SCCR) only when the MCLK is selected for monitoring</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MONFLAG</name>
+              <description>Clock Monitoring Result Flag</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NotReady</name>
+                  <description>The clock to be monitored is not ready</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Ready</name>
+                  <description>The clock to be monitored is ready</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMINTFG</name>
+              <description>Clock Monitoring Interrupt Flag</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MONCS</name>
+              <description>Monitored Clock Selection</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MCLK</name>
+                  <description>Select MCLK.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIRC</name>
+                  <description>Select HIRC.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XMOSC</name>
+                  <description>Select XMOSC.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XSOSC</name>
+                  <description>Select XSOSC.</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PPCLKEN1</name>
+          <description>Peripheral Clock Enable Register 1</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T21CLKE</name>
+              <description>TIMER21 Clock Enable</description>
+              <bitRange>[21:21]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T20CLKE</name>
+              <description>TIMER20 Clock Enable</description>
+              <bitRange>[20:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T30CLKE</name>
+              <description>TIMER30 Clock Enable</description>
+              <bitRange>[19:19]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T12CLKE</name>
+              <description>TIMER12 Clock Enable</description>
+              <bitRange>[18:18]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T11CLKE</name>
+              <description>TIMER11 Clock Enable</description>
+              <bitRange>[17:17]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T10CLKE</name>
+              <description>TIMER10 Clock Enable</description>
+              <bitRange>[16:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T16CLKE</name>
+              <description>TIMER16 Clock Enable</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T15CLKE</name>
+              <description>TIMER15 Clock Enable</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T14CLKE</name>
+              <description>TIMER14 Clock Enable</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T13CLKE</name>
+              <description>TIMER13 Clock Enable</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PFCLKE</name>
+              <description>Port F Clock Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PECLKE</name>
+              <description>Port E Clock Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PDCLKE</name>
+              <description>Port D Clock Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PCCLKE</name>
+              <description>Port C Clock Enable</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PBCLKE</name>
+              <description>Port B Clock Enable</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PACLKE</name>
+              <description>Port A Clock Enable</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PPCLKEN2</name>
+          <description>Peripheral Clock Enable Register 2</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x20000</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>FMCLKE</name>
+              <description>FMC (Flash Memory Controller) Clock Enable</description>
+              <bitRange>[19:19]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVICLKE</name>
+              <description>LVI (Low Voltage Indicator) Clock Enable</description>
+              <bitRange>[18:18]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDTCLKE</name>
+              <description>WDT (Watch-Dog Timer) Clock Enable</description>
+              <bitRange>[17:17]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WTCLKE</name>
+              <description>WT (Watch Timer) Clock Enable</description>
+              <bitRange>[16:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LCDCLKE</name>
+              <description>LCD (LCD Driver) Clock Enable</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCLKE</name>
+              <description>CRC (Cyclic Redundancy Check) Clock Enable</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADCLKE</name>
+              <description>ADC (Analog to Digital Converter) Clock Enable</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>I2C2CLKE</name>
+              <description>I2C2 (Inter-IC) Clock Enable</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>I2C1CLKE</name>
+              <description>I2C1 (Inter-IC) Clock Enable</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>I2C0CLKE</name>
+              <description>I2C0 (Inter-IC) Clock Enable</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UST13CLKE</name>
+              <description>USART13 Clock Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UST12CLKE</name>
+              <description>USART12 Clock Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UT1CLKE</name>
+              <description>UART1 Clock Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UT0CLKE</name>
+              <description>UART0 Clock Enable</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UST11CLKE</name>
+              <description>USART11 Clock Enable</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UST10CLKE</name>
+              <description>USART10 Clock Enable</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PPCLKSR</name>
+          <description>Peripheral Clock Selection Register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T20CLK</name>
+              <description>TIMER20 Clock Selection</description>
+              <bitRange>[20:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>XSOSC</name>
+                  <description>XSOSC clock</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PCLK</name>
+                  <description>PCLK clock</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T30CLK</name>
+              <description>TIMER30 Clock Selection</description>
+              <bitRange>[17:17]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MCLK</name>
+                  <description>MCLK clock</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PCLK</name>
+                  <description>PCLK clock</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LCDCLK</name>
+              <description>LCD (LCD Driver) Clock Selection</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DividedMCLK</name>
+                  <description>A clock of the MCLK which is divided by divider 2</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XSOSC</name>
+                  <description>XSOSC clock</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDTRC</name>
+                  <description>WDTRC clock</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WTCLK</name>
+              <description>WT (Watch Timer) Clock Selection</description>
+              <bitRange>[04:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DividedMCLK</name>
+                  <description>A clock of the MCLK which is divided by divider 2</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XSOSC</name>
+                  <description>XSOSC clock</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDTRC</name>
+                  <description>WDTRC clock</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDTCLK</name>
+              <description>WDT (Watch-Dog Timer) Clock Selection</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>WDTRC</name>
+                  <description>WDTRC clock</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PCLK</name>
+                  <description>PCLK clock</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PPRST1</name>
+          <description>Peripheral Reset Register 1</description>
+          <addressOffset>0x60</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T21RST</name>
+              <description>TIMER21 Reset</description>
+              <bitRange>[21:21]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T20RST</name>
+              <description>TIMER20 Reset</description>
+              <bitRange>[20:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T30RST</name>
+              <description>TIMER30 Reset</description>
+              <bitRange>[19:19]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T12RST</name>
+              <description>TIMER12 Reset</description>
+              <bitRange>[18:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T11RST</name>
+              <description>TIMER11 Reset</description>
+              <bitRange>[17:17]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T10RST</name>
+              <description>TIMER10 Reset</description>
+              <bitRange>[16:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T16RST</name>
+              <description>TIMER16 Reset</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T15RST</name>
+              <description>TIMER15 Reset</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T14RST</name>
+              <description>TIMER14 Reset</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T13RST</name>
+              <description>TIMER13 Reset</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PFRST</name>
+              <description>Port F Reset</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERST</name>
+              <description>Port E Reset</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDRST</name>
+              <description>Port D Reset</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCRST</name>
+              <description>Port C Reset</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBRST</name>
+              <description>Port B Reset</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARST</name>
+              <description>Port A Reset</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PPRST2</name>
+          <description>Peripheral Reset Register 2</description>
+          <addressOffset>0x64</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>FMCRST</name>
+              <description>FMC (Flash Memory Controller) Reset</description>
+              <bitRange>[19:19]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LVIRST</name>
+              <description>LVI (Low Voltage Indicator) Reset</description>
+              <bitRange>[18:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WTRST</name>
+              <description>WT (Watch Timer) Reset</description>
+              <bitRange>[16:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCDRST</name>
+              <description>LCD (LCD Driver) Reset</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRRST</name>
+              <description>CRC (Cyclic Redundancy Check) Reset</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADRST</name>
+              <description>ADC (Analog to Digital Converter) Reset</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C2RST</name>
+              <description>I2C2 (Inter-IC) Reset</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C1RST</name>
+              <description>I2C1 (Inter-IC) Reset</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C0RST</name>
+              <description>I2C0 (Inter-IC) Reset</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UST13RST</name>
+              <description>USART13 Reset</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UST12RST</name>
+              <description>USART12 Reset</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1RST</name>
+              <description>UART1 Reset</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0RST</name>
+              <description>UART0 Reset</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UST11RST</name>
+              <description>USART11 Reset</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UST10RST</name>
+              <description>USART10 Reset</description>
+              <bitRange>[00:00]</bitRange>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTFLSR</name>
+          <description>X-tal Filter Selection Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x5</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0x9b37)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0x9b37)</description>
+                  <value>0x9b37</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>XRNS</name>
+              <description>External Main Oscillator Filter Selection</description>
+              <bitRange>[02:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>LE4p5MHz</name>
+                  <description>x-tal LE 4.5MHz</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LE6p5MHz</name>
+                  <description>4.5MHz GT x-tal LE 6.5MHz</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LE8p5MHz</name>
+                  <description>6.5MHz GT x-tal LE 8.5MHz</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LE10p5MHz</name>
+                  <description>8.5MHz GT x-tal LE 10.5MHz</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LE12p5MHz</name>
+                  <description>10.5MHz GT x-tal LE 12.5MHz</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LE16p5MHz</name>
+                  <description>12.5MHz GT x-tal LE 16.5MHz</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SCULV</name>
+      <version>1.0</version>
+      <description>System Control Unit: LVI and LVR</description>
+      <groupName>SCU</groupName>
+      <baseAddress>0x40005100</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LVI</name>
+        <description>LVI Interrupt</description>
+        <value>00</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>LVICR</name>
+          <description>Low Voltage Indicator Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>LVIEN</name>
+              <description>LVI Enable</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable low voltage indicator.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable low voltage indicator.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVINTEN</name>
+              <description>LVI Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable low voltage indicator interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable low voltage indicator interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVIFLAG</name>
+              <description>LVI Interrupt Flag</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVIVS</name>
+              <description>LVI Voltage Selection</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DNW3</name>
+                  <description>Do not write.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p00V</name>
+                  <description>2.00V</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p13V</name>
+                  <description>2.13V</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p28V</name>
+                  <description>2.28V</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p46V</name>
+                  <description>2.46V</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p67V</name>
+                  <description>2.67V</description>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p04V</name>
+                  <description>3.04V</description>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p20V</name>
+                  <description>3.20V</description>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p55V</name>
+                  <description>3.55V</description>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p75V</name>
+                  <description>3.75V</description>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p99V</name>
+                  <description>3.99V</description>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4p25V</name>
+                  <description>4.25V</description>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4p55V</name>
+                  <description>4.55V</description>
+                  <value>15</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LVRCR</name>
+          <description>Low Voltage Reset Control Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>LVREN</name>
+              <description>LVR Enable</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable low voltage reset. (0x55)</description>
+                  <value>0x55</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable low voltage reset.</description>
+                  <value>0x00</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>Pn</name>
+      <version>1.0</version>
+      <description>Port Control Unit &amp; GPIO Port n</description>
+      <groupName>PCU &amp; GPIO</groupName>
+      <baseAddress>0x50000000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>MOD</name>
+          <description>Port n Mode Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MODE15</name>
+              <description>Port n Mode Selection 15</description>
+              <bitRange>[31:30]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE14</name>
+              <description>Port n Mode Selection 14</description>
+              <bitRange>[29:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE13</name>
+              <description>Port n Mode Selection 13</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE12</name>
+              <description>Port n Mode Selection 12</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE11</name>
+              <description>Port n Mode Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE10</name>
+              <description>Port n Mode Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE9</name>
+              <description>Port n Mode Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE8</name>
+              <description>Port n Mode Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE7</name>
+              <description>Port n Mode Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE6</name>
+              <description>Port n Mode Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE5</name>
+              <description>Port n Mode Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE4</name>
+              <description>Port n Mode Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE3</name>
+              <description>Port n Mode Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE2</name>
+              <description>Port n Mode Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE1</name>
+              <description>Port n Mode Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MODE0</name>
+              <description>Port n Mode Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Input</name>
+                  <description>Input Mode</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Output</name>
+                  <description>Output Mode</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Alternative</name>
+                  <description>Alternative Function Mode</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TYP</name>
+          <description>Port n Output Type Selection Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TYP15</name>
+              <description>Port n Output Type Selection 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP14</name>
+              <description>Port n Output Type Selection 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP13</name>
+              <description>Port n Output Type Selection 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP12</name>
+              <description>Port n Output Type Selection 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP11</name>
+              <description>Port n Output Type Selection 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP10</name>
+              <description>Port n Output Type Selection 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP9</name>
+              <description>Port n Output Type Selection 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP8</name>
+              <description>Port n Output Type Selection 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP7</name>
+              <description>Port n Output Type Selection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP6</name>
+              <description>Port n Output Type Selection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP5</name>
+              <description>Port n Output Type Selection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP4</name>
+              <description>Port n Output Type Selection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP3</name>
+              <description>Port n Output Type Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP2</name>
+              <description>Port n Output Type Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP1</name>
+              <description>Port n Output Type Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TYP0</name>
+              <description>Port n Output Type Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PushPull</name>
+                  <description>Push-Pull Output</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OpenDrain</name>
+                  <description>Open-Drain Output</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AFSR1</name>
+          <description>Port n Alternative Function Selection Register 1</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR7</name>
+              <description>Port n Alternative Function Selection 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR6</name>
+              <description>Port n Alternative Function Selection 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR5</name>
+              <description>Port n Alternative Function Selection 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR4</name>
+              <description>Port n Alternative Function Selection 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR3</name>
+              <description>Port n Alternative Function Selection 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR2</name>
+              <description>Port n Alternative Function Selection 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR1</name>
+              <description>Port n Alternative Function Selection 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR0</name>
+              <description>Port n Alternative Function Selection 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AFSR2</name>
+          <description>Port n Alternative Function Selection Register 2</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR15</name>
+              <description>Port n Alternative Function Selection 15</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR14</name>
+              <description>Port n Alternative Function Selection 14</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR13</name>
+              <description>Port n Alternative Function Selection 13</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR12</name>
+              <description>Port n Alternative Function Selection 12</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR11</name>
+              <description>Port n Alternative Function Selection 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR10</name>
+              <description>Port n Alternative Function Selection 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR9</name>
+              <description>Port n Alternative Function Selection 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AFSR8</name>
+              <description>Port n Alternative Function Selection 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AF0</name>
+                  <description>Alternative Function 0 (AF0)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF1</name>
+                  <description>Alternative Function 1 (AF1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF2</name>
+                  <description>Alternative Function 2 (AF2)</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF3</name>
+                  <description>Alternative Function 3 (AF3)</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AF4</name>
+                  <description>Alternative Function 4 (AF4)</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PUPD</name>
+          <description>Port n Pull-Up/Down Resistor Selection Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PUPD15</name>
+              <description>Port n Pull-Up/Down Resistor Selection 15</description>
+              <bitRange>[31:30]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD14</name>
+              <description>Port n Pull-Up/Down Resistor Selection 14</description>
+              <bitRange>[29:28]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD13</name>
+              <description>Port n Pull-Up/Down Resistor Selection 13</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD12</name>
+              <description>Port n Pull-Up/Down Resistor Selection 12</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD11</name>
+              <description>Port n Pull-Up/Down Resistor Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD10</name>
+              <description>Port n Pull-Up/Down Resistor Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD9</name>
+              <description>Port n Pull-Up/Down Resistor Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD8</name>
+              <description>Port n Pull-Up/Down Resistor Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD7</name>
+              <description>Port n Pull-Up/Down Resistor Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD6</name>
+              <description>Port n Pull-Up/Down Resistor Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD5</name>
+              <description>Port n Pull-Up/Down Resistor Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD4</name>
+              <description>Port n Pull-Up/Down Resistor Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD3</name>
+              <description>Port n Pull-Up/Down Resistor Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD2</name>
+              <description>Port n Pull-Up/Down Resistor Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD1</name>
+              <description>Port n Pull-Up/Down Resistor Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PUPD0</name>
+              <description>Port n Pull-Up/Down Resistor Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable pull-up/down resistor.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePU</name>
+                  <description>Enable pull-up resistor.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EnablePD</name>
+                  <description>Enable pull-down resistor.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INDR</name>
+          <description>Port n Input Data Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffff0000</resetMask>
+          <fields>
+            <field>
+              <name>INDR15</name>
+              <description>Port n Input Data 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR14</name>
+              <description>Port n Input Data 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR13</name>
+              <description>Port n Input Data 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR12</name>
+              <description>Port n Input Data 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR11</name>
+              <description>Port n Input Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR10</name>
+              <description>Port n Input Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR9</name>
+              <description>Port n Input Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR8</name>
+              <description>Port n Input Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR7</name>
+              <description>Port n Input Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR6</name>
+              <description>Port n Input Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR5</name>
+              <description>Port n Input Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR4</name>
+              <description>Port n Input Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR3</name>
+              <description>Port n Input Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR2</name>
+              <description>Port n Input Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR1</name>
+              <description>Port n Input Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR0</name>
+              <description>Port n Input Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTDR</name>
+          <description>Port n Output Data Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDR15</name>
+              <description>Port n Output Data 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR14</name>
+              <description>Port n Output Data 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR13</name>
+              <description>Port n Output Data 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR12</name>
+              <description>Port n Output Data 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR11</name>
+              <description>Port n Output Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR10</name>
+              <description>Port n Output Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR9</name>
+              <description>Port n Output Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR8</name>
+              <description>Port n Output Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR7</name>
+              <description>Port n Output Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR6</name>
+              <description>Port n Output Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR5</name>
+              <description>Port n Output Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR4</name>
+              <description>Port n Output Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR3</name>
+              <description>Port n Output Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR2</name>
+              <description>Port n Output Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR1</name>
+              <description>Port n Output Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR0</name>
+              <description>Port n Output Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BSR</name>
+          <description>Port n Output Bit Set Register</description>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BSR15</name>
+              <description>Port n Output Bit Set 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR14</name>
+              <description>Port n Output Bit Set 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR13</name>
+              <description>Port n Output Bit Set 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR12</name>
+              <description>Port n Output Bit Set 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR11</name>
+              <description>Port n Output Bit Set 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR10</name>
+              <description>Port n Output Bit Set 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR9</name>
+              <description>Port n Output Bit Set 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR8</name>
+              <description>Port n Output Bit Set 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR7</name>
+              <description>Port n Output Bit Set 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR6</name>
+              <description>Port n Output Bit Set 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR5</name>
+              <description>Port n Output Bit Set 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR4</name>
+              <description>Port n Output Bit Set 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR3</name>
+              <description>Port n Output Bit Set 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR2</name>
+              <description>Port n Output Bit Set 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR1</name>
+              <description>Port n Output Bit Set 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BSR0</name>
+              <description>Port n Output Bit Set 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Set</name>
+                  <description>Set the corresponding OUTDRx bit (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BCR</name>
+          <description>Port n Output Bit Clear Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BCR15</name>
+              <description>Port n Output Bit Clear 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR14</name>
+              <description>Port n Output Bit Clear 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR13</name>
+              <description>Port n Output Bit Clear 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR12</name>
+              <description>Port n Output Bit Clear 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR11</name>
+              <description>Port n Output Bit Clear 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR10</name>
+              <description>Port n Output Bit Clear 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR9</name>
+              <description>Port n Output Bit Clear 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR8</name>
+              <description>Port n Output Bit Clear 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR7</name>
+              <description>Port n Output Bit Clear 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR6</name>
+              <description>Port n Output Bit Clear 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR5</name>
+              <description>Port n Output Bit Clear 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR4</name>
+              <description>Port n Output Bit Clear 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR3</name>
+              <description>Port n Output Bit Clear 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR2</name>
+              <description>Port n Output Bit Clear 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR1</name>
+              <description>Port n Output Bit Clear 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BCR0</name>
+              <description>Port n Output Bit Clear 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the corresponding OUTDRx bit. (Automatically cleared to 0.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTDMSK</name>
+          <description>Port n Output Data Mask Register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDMSK15</name>
+              <description>Port n Output Data Mask 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK14</name>
+              <description>Port n Output Data Mask 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK13</name>
+              <description>Port n Output Data Mask 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK12</name>
+              <description>Port n Output Data Mask 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK11</name>
+              <description>Port n Output Data Mask 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK10</name>
+              <description>Port n Output Data Mask 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK9</name>
+              <description>Port n Output Data Mask 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK8</name>
+              <description>Port n Output Data Mask 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK7</name>
+              <description>Port n Output Data Mask 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK6</name>
+              <description>Port n Output Data Mask 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK5</name>
+              <description>Port n Output Data Mask 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK4</name>
+              <description>Port n Output Data Mask 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK3</name>
+              <description>Port n Output Data Mask 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK2</name>
+              <description>Port n Output Data Mask 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK1</name>
+              <description>Port n Output Data Mask 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OUTDMSK0</name>
+              <description>Port n Output Data Mask 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Unmask</name>
+                  <description>Unmask. The corresponding OUTDRx bit can be changed.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Mask</name>
+                  <description>Mask. The corresponding OUTDRx bit is protected.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBCR</name>
+          <description>Port n Debounce Control Register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DBCLK</name>
+              <description>Port n Debounce Filter Sampling Clock Selection</description>
+              <bitRange>[18:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>HCLK1</name>
+                  <description>HCLK/1</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK4</name>
+                  <description>HCLK/4</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK16</name>
+                  <description>HCLK/16</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK64</name>
+                  <description>HCLK/64</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK256</name>
+                  <description>HCLK/256</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HCLK1024</name>
+                  <description>HCLK/1024</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN11</name>
+              <description>Port n Debounce Enable 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN10</name>
+              <description>Port n Debounce Enable 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN9</name>
+              <description>Port n Debounce Enable 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN8</name>
+              <description>Port n Debounce Enable 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN7</name>
+              <description>Port n Debounce Enable 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN6</name>
+              <description>Port n Debounce Enable 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN5</name>
+              <description>Port n Debounce Enable 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN4</name>
+              <description>Port n Debounce Enable 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN3</name>
+              <description>Port n Debounce Enable 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN2</name>
+              <description>Port n Debounce Enable 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN1</name>
+              <description>Port n Debounce Enable 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBEN0</name>
+              <description>Port n Debounce Enable 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable debounce filter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable debounce filter.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="Pn">
+      <name>PA</name>
+      <version>1.0</version>
+      <description>Port Control Unit &amp; GPIO Port A</description>
+      <groupName>PCU &amp; GPIO</groupName>
+      <baseAddress>0x30000000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PA_MOD</name>
+          <description>Port n Mode Register</description>
+          <alternateRegister>MOD</alternateRegister>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MODE11</name>
+              <description>Port n Mode Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE10</name>
+              <description>Port n Mode Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE9</name>
+              <description>Port n Mode Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE8</name>
+              <description>Port n Mode Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE7</name>
+              <description>Port n Mode Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE6</name>
+              <description>Port n Mode Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE5</name>
+              <description>Port n Mode Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE4</name>
+              <description>Port n Mode Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE3</name>
+              <description>Port n Mode Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE2</name>
+              <description>Port n Mode Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE1</name>
+              <description>Port n Mode Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE0</name>
+              <description>Port n Mode Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_TYP</name>
+          <description>Port n Output Type Selection Register</description>
+          <alternateRegister>TYP</alternateRegister>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TYP11</name>
+              <description>Port n Output Type Selection 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP10</name>
+              <description>Port n Output Type Selection 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP9</name>
+              <description>Port n Output Type Selection 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP8</name>
+              <description>Port n Output Type Selection 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP7</name>
+              <description>Port n Output Type Selection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP6</name>
+              <description>Port n Output Type Selection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP5</name>
+              <description>Port n Output Type Selection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP4</name>
+              <description>Port n Output Type Selection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP3</name>
+              <description>Port n Output Type Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP2</name>
+              <description>Port n Output Type Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP1</name>
+              <description>Port n Output Type Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP0</name>
+              <description>Port n Output Type Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_AFSR1</name>
+          <description>Port n Alternative Function Selection Register 1</description>
+          <alternateRegister>AFSR1</alternateRegister>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR7</name>
+              <description>Port n Alternative Function Selection 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR6</name>
+              <description>Port n Alternative Function Selection 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR5</name>
+              <description>Port n Alternative Function Selection 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR4</name>
+              <description>Port n Alternative Function Selection 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR3</name>
+              <description>Port n Alternative Function Selection 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR2</name>
+              <description>Port n Alternative Function Selection 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR1</name>
+              <description>Port n Alternative Function Selection 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR0</name>
+              <description>Port n Alternative Function Selection 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_AFSR2</name>
+          <description>Port n Alternative Function Selection Register 2</description>
+          <alternateRegister>AFSR2</alternateRegister>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR11</name>
+              <description>Port n Alternative Function Selection 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR10</name>
+              <description>Port n Alternative Function Selection 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR9</name>
+              <description>Port n Alternative Function Selection 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR8</name>
+              <description>Port n Alternative Function Selection 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_PUPD</name>
+          <description>Port n Pull-Up/Down Resistor Selection Register</description>
+          <alternateRegister>PUPD</alternateRegister>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PUPD11</name>
+              <description>Port n Pull-Up/Down Resistor Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD10</name>
+              <description>Port n Pull-Up/Down Resistor Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD9</name>
+              <description>Port n Pull-Up/Down Resistor Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD8</name>
+              <description>Port n Pull-Up/Down Resistor Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD7</name>
+              <description>Port n Pull-Up/Down Resistor Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD6</name>
+              <description>Port n Pull-Up/Down Resistor Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD5</name>
+              <description>Port n Pull-Up/Down Resistor Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD4</name>
+              <description>Port n Pull-Up/Down Resistor Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD3</name>
+              <description>Port n Pull-Up/Down Resistor Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD2</name>
+              <description>Port n Pull-Up/Down Resistor Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD1</name>
+              <description>Port n Pull-Up/Down Resistor Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD0</name>
+              <description>Port n Pull-Up/Down Resistor Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_INDR</name>
+          <description>Port n Input Data Register</description>
+          <alternateRegister>INDR</alternateRegister>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xfffff000</resetMask>
+          <fields>
+            <field>
+              <name>INDR11</name>
+              <description>Port n Input Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR10</name>
+              <description>Port n Input Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR9</name>
+              <description>Port n Input Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR8</name>
+              <description>Port n Input Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR7</name>
+              <description>Port n Input Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR6</name>
+              <description>Port n Input Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR5</name>
+              <description>Port n Input Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR4</name>
+              <description>Port n Input Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR3</name>
+              <description>Port n Input Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR2</name>
+              <description>Port n Input Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR1</name>
+              <description>Port n Input Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR0</name>
+              <description>Port n Input Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_OUTDR</name>
+          <description>Port n Output Data Register</description>
+          <alternateRegister>OUTDR</alternateRegister>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDR11</name>
+              <description>Port n Output Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR10</name>
+              <description>Port n Output Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR9</name>
+              <description>Port n Output Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR8</name>
+              <description>Port n Output Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR7</name>
+              <description>Port n Output Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR6</name>
+              <description>Port n Output Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR5</name>
+              <description>Port n Output Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR4</name>
+              <description>Port n Output Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR3</name>
+              <description>Port n Output Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR2</name>
+              <description>Port n Output Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR1</name>
+              <description>Port n Output Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR0</name>
+              <description>Port n Output Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_BSR</name>
+          <description>Port n Output Bit Set Register</description>
+          <alternateRegister>BSR</alternateRegister>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BSR11</name>
+              <description>Port n Output Bit Set 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR10</name>
+              <description>Port n Output Bit Set 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR9</name>
+              <description>Port n Output Bit Set 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR8</name>
+              <description>Port n Output Bit Set 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR7</name>
+              <description>Port n Output Bit Set 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR6</name>
+              <description>Port n Output Bit Set 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR5</name>
+              <description>Port n Output Bit Set 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR4</name>
+              <description>Port n Output Bit Set 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR3</name>
+              <description>Port n Output Bit Set 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR2</name>
+              <description>Port n Output Bit Set 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR1</name>
+              <description>Port n Output Bit Set 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR0</name>
+              <description>Port n Output Bit Set 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_BCR</name>
+          <description>Port n Output Bit Clear Register</description>
+          <alternateRegister>BCR</alternateRegister>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BCR11</name>
+              <description>Port n Output Bit Clear 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR10</name>
+              <description>Port n Output Bit Clear 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR9</name>
+              <description>Port n Output Bit Clear 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR8</name>
+              <description>Port n Output Bit Clear 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR7</name>
+              <description>Port n Output Bit Clear 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR6</name>
+              <description>Port n Output Bit Clear 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR5</name>
+              <description>Port n Output Bit Clear 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR4</name>
+              <description>Port n Output Bit Clear 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR3</name>
+              <description>Port n Output Bit Clear 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR2</name>
+              <description>Port n Output Bit Clear 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR1</name>
+              <description>Port n Output Bit Clear 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR0</name>
+              <description>Port n Output Bit Clear 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PA_OUTDMSK</name>
+          <description>Port n Output Data Mask Register</description>
+          <alternateRegister>OUTDMSK</alternateRegister>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDMSK11</name>
+              <description>Port n Output Data Mask 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK10</name>
+              <description>Port n Output Data Mask 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK9</name>
+              <description>Port n Output Data Mask 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK8</name>
+              <description>Port n Output Data Mask 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK7</name>
+              <description>Port n Output Data Mask 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK6</name>
+              <description>Port n Output Data Mask 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK5</name>
+              <description>Port n Output Data Mask 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK4</name>
+              <description>Port n Output Data Mask 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK3</name>
+              <description>Port n Output Data Mask 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK2</name>
+              <description>Port n Output Data Mask 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK1</name>
+              <description>Port n Output Data Mask 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK0</name>
+              <description>Port n Output Data Mask 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="Pn">
+      <name>PB</name>
+      <version>1.0</version>
+      <description>Port Control Unit &amp; GPIO Port B</description>
+      <groupName>PCU &amp; GPIO</groupName>
+      <baseAddress>0x30000100</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PB_MOD</name>
+          <description>Port n Mode Register</description>
+          <alternateRegister>MOD</alternateRegister>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MODE15</name>
+              <description>Port n Mode Selection 15</description>
+              <bitRange>[31:30]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE14</name>
+              <description>Port n Mode Selection 14</description>
+              <bitRange>[29:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE13</name>
+              <description>Port n Mode Selection 13</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE12</name>
+              <description>Port n Mode Selection 12</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE11</name>
+              <description>Port n Mode Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE10</name>
+              <description>Port n Mode Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE9</name>
+              <description>Port n Mode Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE8</name>
+              <description>Port n Mode Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE7</name>
+              <description>Port n Mode Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE6</name>
+              <description>Port n Mode Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE5</name>
+              <description>Port n Mode Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE4</name>
+              <description>Port n Mode Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE3</name>
+              <description>Port n Mode Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE2</name>
+              <description>Port n Mode Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE1</name>
+              <description>Port n Mode Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE0</name>
+              <description>Port n Mode Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_TYP</name>
+          <description>Port n Output Type Selection Register</description>
+          <alternateRegister>TYP</alternateRegister>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TYP15</name>
+              <description>Port n Output Type Selection 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP14</name>
+              <description>Port n Output Type Selection 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP13</name>
+              <description>Port n Output Type Selection 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP12</name>
+              <description>Port n Output Type Selection 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP11</name>
+              <description>Port n Output Type Selection 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP10</name>
+              <description>Port n Output Type Selection 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP9</name>
+              <description>Port n Output Type Selection 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP8</name>
+              <description>Port n Output Type Selection 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP7</name>
+              <description>Port n Output Type Selection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP6</name>
+              <description>Port n Output Type Selection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP5</name>
+              <description>Port n Output Type Selection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP4</name>
+              <description>Port n Output Type Selection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP3</name>
+              <description>Port n Output Type Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP2</name>
+              <description>Port n Output Type Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP1</name>
+              <description>Port n Output Type Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP0</name>
+              <description>Port n Output Type Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_AFSR1</name>
+          <description>Port n Alternative Function Selection Register 1</description>
+          <alternateRegister>AFSR1</alternateRegister>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR7</name>
+              <description>Port n Alternative Function Selection 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR6</name>
+              <description>Port n Alternative Function Selection 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR5</name>
+              <description>Port n Alternative Function Selection 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR4</name>
+              <description>Port n Alternative Function Selection 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR3</name>
+              <description>Port n Alternative Function Selection 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR2</name>
+              <description>Port n Alternative Function Selection 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR1</name>
+              <description>Port n Alternative Function Selection 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR0</name>
+              <description>Port n Alternative Function Selection 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_AFSR2</name>
+          <description>Port n Alternative Function Selection Register 2</description>
+          <alternateRegister>AFSR2</alternateRegister>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR15</name>
+              <description>Port n Alternative Function Selection 15</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR14</name>
+              <description>Port n Alternative Function Selection 14</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR13</name>
+              <description>Port n Alternative Function Selection 13</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR12</name>
+              <description>Port n Alternative Function Selection 12</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR11</name>
+              <description>Port n Alternative Function Selection 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR10</name>
+              <description>Port n Alternative Function Selection 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR9</name>
+              <description>Port n Alternative Function Selection 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR8</name>
+              <description>Port n Alternative Function Selection 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_PUPD</name>
+          <description>Port n Pull-Up/Down Resistor Selection Register</description>
+          <alternateRegister>PUPD</alternateRegister>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PUPD15</name>
+              <description>Port n Pull-Up/Down Resistor Selection 15</description>
+              <bitRange>[31:30]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD14</name>
+              <description>Port n Pull-Up/Down Resistor Selection 14</description>
+              <bitRange>[29:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD13</name>
+              <description>Port n Pull-Up/Down Resistor Selection 13</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD12</name>
+              <description>Port n Pull-Up/Down Resistor Selection 12</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD11</name>
+              <description>Port n Pull-Up/Down Resistor Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD10</name>
+              <description>Port n Pull-Up/Down Resistor Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD9</name>
+              <description>Port n Pull-Up/Down Resistor Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD8</name>
+              <description>Port n Pull-Up/Down Resistor Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD7</name>
+              <description>Port n Pull-Up/Down Resistor Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD6</name>
+              <description>Port n Pull-Up/Down Resistor Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD5</name>
+              <description>Port n Pull-Up/Down Resistor Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD4</name>
+              <description>Port n Pull-Up/Down Resistor Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD3</name>
+              <description>Port n Pull-Up/Down Resistor Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD2</name>
+              <description>Port n Pull-Up/Down Resistor Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD1</name>
+              <description>Port n Pull-Up/Down Resistor Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD0</name>
+              <description>Port n Pull-Up/Down Resistor Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_INDR</name>
+          <description>Port n Input Data Register</description>
+          <alternateRegister>INDR</alternateRegister>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffff0000</resetMask>
+          <fields>
+            <field>
+              <name>INDR15</name>
+              <description>Port n Input Data 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR14</name>
+              <description>Port n Input Data 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR13</name>
+              <description>Port n Input Data 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR12</name>
+              <description>Port n Input Data 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR11</name>
+              <description>Port n Input Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR10</name>
+              <description>Port n Input Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR9</name>
+              <description>Port n Input Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR8</name>
+              <description>Port n Input Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR7</name>
+              <description>Port n Input Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR6</name>
+              <description>Port n Input Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR5</name>
+              <description>Port n Input Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR4</name>
+              <description>Port n Input Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR3</name>
+              <description>Port n Input Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR2</name>
+              <description>Port n Input Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR1</name>
+              <description>Port n Input Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR0</name>
+              <description>Port n Input Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_OUTDR</name>
+          <description>Port n Output Data Register</description>
+          <alternateRegister>OUTDR</alternateRegister>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDR15</name>
+              <description>Port n Output Data 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR14</name>
+              <description>Port n Output Data 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR13</name>
+              <description>Port n Output Data 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR12</name>
+              <description>Port n Output Data 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR11</name>
+              <description>Port n Output Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR10</name>
+              <description>Port n Output Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR9</name>
+              <description>Port n Output Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR8</name>
+              <description>Port n Output Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR7</name>
+              <description>Port n Output Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR6</name>
+              <description>Port n Output Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR5</name>
+              <description>Port n Output Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR4</name>
+              <description>Port n Output Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR3</name>
+              <description>Port n Output Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR2</name>
+              <description>Port n Output Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR1</name>
+              <description>Port n Output Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR0</name>
+              <description>Port n Output Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_BSR</name>
+          <description>Port n Output Bit Set Register</description>
+          <alternateRegister>BSR</alternateRegister>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BSR15</name>
+              <description>Port n Output Bit Set 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR14</name>
+              <description>Port n Output Bit Set 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR13</name>
+              <description>Port n Output Bit Set 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR12</name>
+              <description>Port n Output Bit Set 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR11</name>
+              <description>Port n Output Bit Set 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR10</name>
+              <description>Port n Output Bit Set 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR9</name>
+              <description>Port n Output Bit Set 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR8</name>
+              <description>Port n Output Bit Set 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR7</name>
+              <description>Port n Output Bit Set 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR6</name>
+              <description>Port n Output Bit Set 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR5</name>
+              <description>Port n Output Bit Set 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR4</name>
+              <description>Port n Output Bit Set 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR3</name>
+              <description>Port n Output Bit Set 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR2</name>
+              <description>Port n Output Bit Set 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR1</name>
+              <description>Port n Output Bit Set 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR0</name>
+              <description>Port n Output Bit Set 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_BCR</name>
+          <description>Port n Output Bit Clear Register</description>
+          <alternateRegister>BCR</alternateRegister>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BCR15</name>
+              <description>Port n Output Bit Clear 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR14</name>
+              <description>Port n Output Bit Clear 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR13</name>
+              <description>Port n Output Bit Clear 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR12</name>
+              <description>Port n Output Bit Clear 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR11</name>
+              <description>Port n Output Bit Clear 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR10</name>
+              <description>Port n Output Bit Clear 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR9</name>
+              <description>Port n Output Bit Clear 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR8</name>
+              <description>Port n Output Bit Clear 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR7</name>
+              <description>Port n Output Bit Clear 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR6</name>
+              <description>Port n Output Bit Clear 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR5</name>
+              <description>Port n Output Bit Clear 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR4</name>
+              <description>Port n Output Bit Clear 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR3</name>
+              <description>Port n Output Bit Clear 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR2</name>
+              <description>Port n Output Bit Clear 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR1</name>
+              <description>Port n Output Bit Clear 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR0</name>
+              <description>Port n Output Bit Clear 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_OUTDMSK</name>
+          <description>Port n Output Data Mask Register</description>
+          <alternateRegister>OUTDMSK</alternateRegister>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDMSK15</name>
+              <description>Port n Output Data Mask 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK14</name>
+              <description>Port n Output Data Mask 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK13</name>
+              <description>Port n Output Data Mask 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK12</name>
+              <description>Port n Output Data Mask 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK11</name>
+              <description>Port n Output Data Mask 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK10</name>
+              <description>Port n Output Data Mask 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK9</name>
+              <description>Port n Output Data Mask 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK8</name>
+              <description>Port n Output Data Mask 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK7</name>
+              <description>Port n Output Data Mask 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK6</name>
+              <description>Port n Output Data Mask 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK5</name>
+              <description>Port n Output Data Mask 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK4</name>
+              <description>Port n Output Data Mask 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK3</name>
+              <description>Port n Output Data Mask 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK2</name>
+              <description>Port n Output Data Mask 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK1</name>
+              <description>Port n Output Data Mask 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK0</name>
+              <description>Port n Output Data Mask 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PB_DBCR</name>
+          <description>Port n Debounce Control Register</description>
+          <alternateRegister>DBCR</alternateRegister>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DBCLK</name>
+              <description>Port n Debounce Filter Sampling Clock Selection</description>
+              <bitRange>[18:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN11</name>
+              <description>Port n Debounce Enable 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN10</name>
+              <description>Port n Debounce Enable 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN9</name>
+              <description>Port n Debounce Enable 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN8</name>
+              <description>Port n Debounce Enable 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN7</name>
+              <description>Port n Debounce Enable 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN6</name>
+              <description>Port n Debounce Enable 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN5</name>
+              <description>Port n Debounce Enable 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN4</name>
+              <description>Port n Debounce Enable 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN3</name>
+              <description>Port n Debounce Enable 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN2</name>
+              <description>Port n Debounce Enable 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN1</name>
+              <description>Port n Debounce Enable 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN0</name>
+              <description>Port n Debounce Enable 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="Pn">
+      <name>PC</name>
+      <version>1.0</version>
+      <description>Port Control Unit &amp; GPIO Port C</description>
+      <groupName>PCU &amp; GPIO</groupName>
+      <baseAddress>0x30000200</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PC_MOD</name>
+          <description>Port n Mode Register</description>
+          <alternateRegister>MOD</alternateRegister>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MODE12</name>
+              <description>Port n Mode Selection 12</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE11</name>
+              <description>Port n Mode Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE10</name>
+              <description>Port n Mode Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE9</name>
+              <description>Port n Mode Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE8</name>
+              <description>Port n Mode Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE7</name>
+              <description>Port n Mode Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE6</name>
+              <description>Port n Mode Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE5</name>
+              <description>Port n Mode Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE4</name>
+              <description>Port n Mode Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE3</name>
+              <description>Port n Mode Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE2</name>
+              <description>Port n Mode Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE1</name>
+              <description>Port n Mode Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE0</name>
+              <description>Port n Mode Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_TYP</name>
+          <description>Port n Output Type Selection Register</description>
+          <alternateRegister>TYP</alternateRegister>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TYP12</name>
+              <description>Port n Output Type Selection 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP11</name>
+              <description>Port n Output Type Selection 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP10</name>
+              <description>Port n Output Type Selection 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP9</name>
+              <description>Port n Output Type Selection 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP8</name>
+              <description>Port n Output Type Selection 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP7</name>
+              <description>Port n Output Type Selection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP6</name>
+              <description>Port n Output Type Selection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP5</name>
+              <description>Port n Output Type Selection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP4</name>
+              <description>Port n Output Type Selection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP3</name>
+              <description>Port n Output Type Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP2</name>
+              <description>Port n Output Type Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP1</name>
+              <description>Port n Output Type Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP0</name>
+              <description>Port n Output Type Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_AFSR1</name>
+          <description>Port n Alternative Function Selection Register 1</description>
+          <alternateRegister>AFSR1</alternateRegister>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR7</name>
+              <description>Port n Alternative Function Selection 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR6</name>
+              <description>Port n Alternative Function Selection 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR5</name>
+              <description>Port n Alternative Function Selection 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR4</name>
+              <description>Port n Alternative Function Selection 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR3</name>
+              <description>Port n Alternative Function Selection 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR2</name>
+              <description>Port n Alternative Function Selection 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR1</name>
+              <description>Port n Alternative Function Selection 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR0</name>
+              <description>Port n Alternative Function Selection 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_AFSR2</name>
+          <description>Port n Alternative Function Selection Register 2</description>
+          <alternateRegister>AFSR2</alternateRegister>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR12</name>
+              <description>Port n Alternative Function Selection 12</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR11</name>
+              <description>Port n Alternative Function Selection 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR10</name>
+              <description>Port n Alternative Function Selection 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR9</name>
+              <description>Port n Alternative Function Selection 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR8</name>
+              <description>Port n Alternative Function Selection 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_PUPD</name>
+          <description>Port n Pull-Up/Down Resistor Selection Register</description>
+          <alternateRegister>PUPD</alternateRegister>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PUPD12</name>
+              <description>Port n Pull-Up/Down Resistor Selection 12</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD11</name>
+              <description>Port n Pull-Up/Down Resistor Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD10</name>
+              <description>Port n Pull-Up/Down Resistor Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD9</name>
+              <description>Port n Pull-Up/Down Resistor Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD8</name>
+              <description>Port n Pull-Up/Down Resistor Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD7</name>
+              <description>Port n Pull-Up/Down Resistor Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD6</name>
+              <description>Port n Pull-Up/Down Resistor Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD5</name>
+              <description>Port n Pull-Up/Down Resistor Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD4</name>
+              <description>Port n Pull-Up/Down Resistor Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD3</name>
+              <description>Port n Pull-Up/Down Resistor Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD2</name>
+              <description>Port n Pull-Up/Down Resistor Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD1</name>
+              <description>Port n Pull-Up/Down Resistor Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD0</name>
+              <description>Port n Pull-Up/Down Resistor Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_INDR</name>
+          <description>Port n Input Data Register</description>
+          <alternateRegister>INDR</alternateRegister>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffe000</resetMask>
+          <fields>
+            <field>
+              <name>INDR12</name>
+              <description>Port n Input Data 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR11</name>
+              <description>Port n Input Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR10</name>
+              <description>Port n Input Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR9</name>
+              <description>Port n Input Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR8</name>
+              <description>Port n Input Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR7</name>
+              <description>Port n Input Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR6</name>
+              <description>Port n Input Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR5</name>
+              <description>Port n Input Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR4</name>
+              <description>Port n Input Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR3</name>
+              <description>Port n Input Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR2</name>
+              <description>Port n Input Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR1</name>
+              <description>Port n Input Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR0</name>
+              <description>Port n Input Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_OUTDR</name>
+          <description>Port n Output Data Register</description>
+          <alternateRegister>OUTDR</alternateRegister>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDR12</name>
+              <description>Port n Output Data 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR11</name>
+              <description>Port n Output Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR10</name>
+              <description>Port n Output Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR9</name>
+              <description>Port n Output Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR8</name>
+              <description>Port n Output Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR7</name>
+              <description>Port n Output Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR6</name>
+              <description>Port n Output Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR5</name>
+              <description>Port n Output Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR4</name>
+              <description>Port n Output Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR3</name>
+              <description>Port n Output Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR2</name>
+              <description>Port n Output Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR1</name>
+              <description>Port n Output Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR0</name>
+              <description>Port n Output Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_BSR</name>
+          <description>Port n Output Bit Set Register</description>
+          <alternateRegister>BSR</alternateRegister>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BSR12</name>
+              <description>Port n Output Bit Set 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR11</name>
+              <description>Port n Output Bit Set 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR10</name>
+              <description>Port n Output Bit Set 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR9</name>
+              <description>Port n Output Bit Set 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR8</name>
+              <description>Port n Output Bit Set 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR7</name>
+              <description>Port n Output Bit Set 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR6</name>
+              <description>Port n Output Bit Set 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR5</name>
+              <description>Port n Output Bit Set 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR4</name>
+              <description>Port n Output Bit Set 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR3</name>
+              <description>Port n Output Bit Set 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR2</name>
+              <description>Port n Output Bit Set 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR1</name>
+              <description>Port n Output Bit Set 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR0</name>
+              <description>Port n Output Bit Set 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_BCR</name>
+          <description>Port n Output Bit Clear Register</description>
+          <alternateRegister>BCR</alternateRegister>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BCR12</name>
+              <description>Port n Output Bit Clear 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR11</name>
+              <description>Port n Output Bit Clear 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR10</name>
+              <description>Port n Output Bit Clear 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR9</name>
+              <description>Port n Output Bit Clear 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR8</name>
+              <description>Port n Output Bit Clear 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR7</name>
+              <description>Port n Output Bit Clear 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR6</name>
+              <description>Port n Output Bit Clear 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR5</name>
+              <description>Port n Output Bit Clear 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR4</name>
+              <description>Port n Output Bit Clear 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR3</name>
+              <description>Port n Output Bit Clear 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR2</name>
+              <description>Port n Output Bit Clear 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR1</name>
+              <description>Port n Output Bit Clear 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR0</name>
+              <description>Port n Output Bit Clear 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_OUTDMSK</name>
+          <description>Port n Output Data Mask Register</description>
+          <alternateRegister>OUTDMSK</alternateRegister>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDMSK12</name>
+              <description>Port n Output Data Mask 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK11</name>
+              <description>Port n Output Data Mask 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK10</name>
+              <description>Port n Output Data Mask 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK9</name>
+              <description>Port n Output Data Mask 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK8</name>
+              <description>Port n Output Data Mask 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK7</name>
+              <description>Port n Output Data Mask 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK6</name>
+              <description>Port n Output Data Mask 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK5</name>
+              <description>Port n Output Data Mask 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK4</name>
+              <description>Port n Output Data Mask 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK3</name>
+              <description>Port n Output Data Mask 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK2</name>
+              <description>Port n Output Data Mask 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK1</name>
+              <description>Port n Output Data Mask 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK0</name>
+              <description>Port n Output Data Mask 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PC_DBCR</name>
+          <description>Port n Debounce Control Register</description>
+          <alternateRegister>DBCR</alternateRegister>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DBCLK</name>
+              <description>Port n Debounce Filter Sampling Clock Selection</description>
+              <bitRange>[18:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN3</name>
+              <description>Port n Debounce Enable 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN2</name>
+              <description>Port n Debounce Enable 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN1</name>
+              <description>Port n Debounce Enable 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN0</name>
+              <description>Port n Debounce Enable 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="Pn">
+      <name>PD</name>
+      <version>1.0</version>
+      <description>Port Control Unit &amp; GPIO Port D</description>
+      <groupName>PCU &amp; GPIO</groupName>
+      <baseAddress>0x30000300</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PD_MOD</name>
+          <description>Port n Mode Register</description>
+          <alternateRegister>MOD</alternateRegister>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MODE7</name>
+              <description>Port n Mode Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE6</name>
+              <description>Port n Mode Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE5</name>
+              <description>Port n Mode Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE4</name>
+              <description>Port n Mode Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE3</name>
+              <description>Port n Mode Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE2</name>
+              <description>Port n Mode Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE1</name>
+              <description>Port n Mode Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE0</name>
+              <description>Port n Mode Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_TYP</name>
+          <description>Port n Output Type Selection Register</description>
+          <alternateRegister>TYP</alternateRegister>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TYP7</name>
+              <description>Port n Output Type Selection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP6</name>
+              <description>Port n Output Type Selection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP5</name>
+              <description>Port n Output Type Selection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP4</name>
+              <description>Port n Output Type Selection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP3</name>
+              <description>Port n Output Type Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP2</name>
+              <description>Port n Output Type Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP1</name>
+              <description>Port n Output Type Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP0</name>
+              <description>Port n Output Type Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_AFSR1</name>
+          <description>Port n Alternative Function Selection Register 1</description>
+          <alternateRegister>AFSR1</alternateRegister>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR7</name>
+              <description>Port n Alternative Function Selection 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR6</name>
+              <description>Port n Alternative Function Selection 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR5</name>
+              <description>Port n Alternative Function Selection 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR4</name>
+              <description>Port n Alternative Function Selection 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR3</name>
+              <description>Port n Alternative Function Selection 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR2</name>
+              <description>Port n Alternative Function Selection 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR1</name>
+              <description>Port n Alternative Function Selection 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR0</name>
+              <description>Port n Alternative Function Selection 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_AFSR2</name>
+          <description>Port n Alternative Function Selection Register 2</description>
+          <alternateRegister>AFSR2</alternateRegister>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+        </register>
+        <register>
+          <name>PD_PUPD</name>
+          <description>Port n Pull-Up/Down Resistor Selection Register</description>
+          <alternateRegister>PUPD</alternateRegister>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PUPD7</name>
+              <description>Port n Pull-Up/Down Resistor Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD6</name>
+              <description>Port n Pull-Up/Down Resistor Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD5</name>
+              <description>Port n Pull-Up/Down Resistor Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD4</name>
+              <description>Port n Pull-Up/Down Resistor Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD3</name>
+              <description>Port n Pull-Up/Down Resistor Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD2</name>
+              <description>Port n Pull-Up/Down Resistor Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD1</name>
+              <description>Port n Pull-Up/Down Resistor Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD0</name>
+              <description>Port n Pull-Up/Down Resistor Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_INDR</name>
+          <description>Port n Input Data Register</description>
+          <alternateRegister>INDR</alternateRegister>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffff00</resetMask>
+          <fields>
+            <field>
+              <name>INDR7</name>
+              <description>Port n Input Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR6</name>
+              <description>Port n Input Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR5</name>
+              <description>Port n Input Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR4</name>
+              <description>Port n Input Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR3</name>
+              <description>Port n Input Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR2</name>
+              <description>Port n Input Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR1</name>
+              <description>Port n Input Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR0</name>
+              <description>Port n Input Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_OUTDR</name>
+          <description>Port n Output Data Register</description>
+          <alternateRegister>OUTDR</alternateRegister>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDR7</name>
+              <description>Port n Output Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR6</name>
+              <description>Port n Output Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR5</name>
+              <description>Port n Output Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR4</name>
+              <description>Port n Output Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR3</name>
+              <description>Port n Output Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR2</name>
+              <description>Port n Output Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR1</name>
+              <description>Port n Output Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR0</name>
+              <description>Port n Output Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_BSR</name>
+          <description>Port n Output Bit Set Register</description>
+          <alternateRegister>BSR</alternateRegister>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BSR7</name>
+              <description>Port n Output Bit Set 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR6</name>
+              <description>Port n Output Bit Set 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR5</name>
+              <description>Port n Output Bit Set 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR4</name>
+              <description>Port n Output Bit Set 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR3</name>
+              <description>Port n Output Bit Set 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR2</name>
+              <description>Port n Output Bit Set 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR1</name>
+              <description>Port n Output Bit Set 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR0</name>
+              <description>Port n Output Bit Set 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_BCR</name>
+          <description>Port n Output Bit Clear Register</description>
+          <alternateRegister>BCR</alternateRegister>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BCR7</name>
+              <description>Port n Output Bit Clear 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR6</name>
+              <description>Port n Output Bit Clear 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR5</name>
+              <description>Port n Output Bit Clear 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR4</name>
+              <description>Port n Output Bit Clear 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR3</name>
+              <description>Port n Output Bit Clear 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR2</name>
+              <description>Port n Output Bit Clear 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR1</name>
+              <description>Port n Output Bit Clear 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR0</name>
+              <description>Port n Output Bit Clear 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_OUTDMSK</name>
+          <description>Port n Output Data Mask Register</description>
+          <alternateRegister>OUTDMSK</alternateRegister>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDMSK7</name>
+              <description>Port n Output Data Mask 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK6</name>
+              <description>Port n Output Data Mask 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK5</name>
+              <description>Port n Output Data Mask 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK4</name>
+              <description>Port n Output Data Mask 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK3</name>
+              <description>Port n Output Data Mask 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK2</name>
+              <description>Port n Output Data Mask 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK1</name>
+              <description>Port n Output Data Mask 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK0</name>
+              <description>Port n Output Data Mask 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="Pn">
+      <name>PE</name>
+      <version>1.0</version>
+      <description>Port Control Unit &amp; GPIO Port E</description>
+      <groupName>PCU &amp; GPIO</groupName>
+      <baseAddress>0x30000400</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PE_MOD</name>
+          <description>Port n Mode Register</description>
+          <alternateRegister>MOD</alternateRegister>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MODE15</name>
+              <description>Port n Mode Selection 15</description>
+              <bitRange>[31:30]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE14</name>
+              <description>Port n Mode Selection 14</description>
+              <bitRange>[29:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE13</name>
+              <description>Port n Mode Selection 13</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE12</name>
+              <description>Port n Mode Selection 12</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE11</name>
+              <description>Port n Mode Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE10</name>
+              <description>Port n Mode Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE9</name>
+              <description>Port n Mode Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE8</name>
+              <description>Port n Mode Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE7</name>
+              <description>Port n Mode Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE6</name>
+              <description>Port n Mode Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE5</name>
+              <description>Port n Mode Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE4</name>
+              <description>Port n Mode Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE3</name>
+              <description>Port n Mode Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE2</name>
+              <description>Port n Mode Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE1</name>
+              <description>Port n Mode Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE0</name>
+              <description>Port n Mode Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_TYP</name>
+          <description>Port n Output Type Selection Register</description>
+          <alternateRegister>TYP</alternateRegister>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TYP15</name>
+              <description>Port n Output Type Selection 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP14</name>
+              <description>Port n Output Type Selection 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP13</name>
+              <description>Port n Output Type Selection 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP12</name>
+              <description>Port n Output Type Selection 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP11</name>
+              <description>Port n Output Type Selection 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP10</name>
+              <description>Port n Output Type Selection 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP9</name>
+              <description>Port n Output Type Selection 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP8</name>
+              <description>Port n Output Type Selection 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP7</name>
+              <description>Port n Output Type Selection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP6</name>
+              <description>Port n Output Type Selection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP5</name>
+              <description>Port n Output Type Selection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP4</name>
+              <description>Port n Output Type Selection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP3</name>
+              <description>Port n Output Type Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP2</name>
+              <description>Port n Output Type Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP1</name>
+              <description>Port n Output Type Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP0</name>
+              <description>Port n Output Type Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_AFSR1</name>
+          <description>Port n Alternative Function Selection Register 1</description>
+          <alternateRegister>AFSR1</alternateRegister>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR7</name>
+              <description>Port n Alternative Function Selection 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR6</name>
+              <description>Port n Alternative Function Selection 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR5</name>
+              <description>Port n Alternative Function Selection 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR4</name>
+              <description>Port n Alternative Function Selection 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR3</name>
+              <description>Port n Alternative Function Selection 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR2</name>
+              <description>Port n Alternative Function Selection 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR1</name>
+              <description>Port n Alternative Function Selection 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR0</name>
+              <description>Port n Alternative Function Selection 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_AFSR2</name>
+          <description>Port n Alternative Function Selection Register 2</description>
+          <alternateRegister>AFSR2</alternateRegister>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR15</name>
+              <description>Port n Alternative Function Selection 15</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR14</name>
+              <description>Port n Alternative Function Selection 14</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR13</name>
+              <description>Port n Alternative Function Selection 13</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR12</name>
+              <description>Port n Alternative Function Selection 12</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR11</name>
+              <description>Port n Alternative Function Selection 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR10</name>
+              <description>Port n Alternative Function Selection 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR9</name>
+              <description>Port n Alternative Function Selection 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR8</name>
+              <description>Port n Alternative Function Selection 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_PUPD</name>
+          <description>Port n Pull-Up/Down Resistor Selection Register</description>
+          <alternateRegister>PUPD</alternateRegister>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PUPD15</name>
+              <description>Port n Pull-Up/Down Resistor Selection 15</description>
+              <bitRange>[31:30]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD14</name>
+              <description>Port n Pull-Up/Down Resistor Selection 14</description>
+              <bitRange>[29:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD13</name>
+              <description>Port n Pull-Up/Down Resistor Selection 13</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD12</name>
+              <description>Port n Pull-Up/Down Resistor Selection 12</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD11</name>
+              <description>Port n Pull-Up/Down Resistor Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD10</name>
+              <description>Port n Pull-Up/Down Resistor Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD9</name>
+              <description>Port n Pull-Up/Down Resistor Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD8</name>
+              <description>Port n Pull-Up/Down Resistor Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD7</name>
+              <description>Port n Pull-Up/Down Resistor Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD6</name>
+              <description>Port n Pull-Up/Down Resistor Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD5</name>
+              <description>Port n Pull-Up/Down Resistor Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD4</name>
+              <description>Port n Pull-Up/Down Resistor Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD3</name>
+              <description>Port n Pull-Up/Down Resistor Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD2</name>
+              <description>Port n Pull-Up/Down Resistor Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD1</name>
+              <description>Port n Pull-Up/Down Resistor Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD0</name>
+              <description>Port n Pull-Up/Down Resistor Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_INDR</name>
+          <description>Port n Input Data Register</description>
+          <alternateRegister>INDR</alternateRegister>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffff0000</resetMask>
+          <fields>
+            <field>
+              <name>INDR15</name>
+              <description>Port n Input Data 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR14</name>
+              <description>Port n Input Data 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR13</name>
+              <description>Port n Input Data 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR12</name>
+              <description>Port n Input Data 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR11</name>
+              <description>Port n Input Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR10</name>
+              <description>Port n Input Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR9</name>
+              <description>Port n Input Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR8</name>
+              <description>Port n Input Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR7</name>
+              <description>Port n Input Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR6</name>
+              <description>Port n Input Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR5</name>
+              <description>Port n Input Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR4</name>
+              <description>Port n Input Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR3</name>
+              <description>Port n Input Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR2</name>
+              <description>Port n Input Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR1</name>
+              <description>Port n Input Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR0</name>
+              <description>Port n Input Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_OUTDR</name>
+          <description>Port n Output Data Register</description>
+          <alternateRegister>OUTDR</alternateRegister>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDR15</name>
+              <description>Port n Output Data 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR14</name>
+              <description>Port n Output Data 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR13</name>
+              <description>Port n Output Data 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR12</name>
+              <description>Port n Output Data 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR11</name>
+              <description>Port n Output Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR10</name>
+              <description>Port n Output Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR9</name>
+              <description>Port n Output Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR8</name>
+              <description>Port n Output Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR7</name>
+              <description>Port n Output Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR6</name>
+              <description>Port n Output Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR5</name>
+              <description>Port n Output Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR4</name>
+              <description>Port n Output Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR3</name>
+              <description>Port n Output Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR2</name>
+              <description>Port n Output Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR1</name>
+              <description>Port n Output Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR0</name>
+              <description>Port n Output Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_BSR</name>
+          <description>Port n Output Bit Set Register</description>
+          <alternateRegister>BSR</alternateRegister>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BSR15</name>
+              <description>Port n Output Bit Set 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR14</name>
+              <description>Port n Output Bit Set 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR13</name>
+              <description>Port n Output Bit Set 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR12</name>
+              <description>Port n Output Bit Set 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR11</name>
+              <description>Port n Output Bit Set 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR10</name>
+              <description>Port n Output Bit Set 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR9</name>
+              <description>Port n Output Bit Set 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR8</name>
+              <description>Port n Output Bit Set 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR7</name>
+              <description>Port n Output Bit Set 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR6</name>
+              <description>Port n Output Bit Set 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR5</name>
+              <description>Port n Output Bit Set 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR4</name>
+              <description>Port n Output Bit Set 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR3</name>
+              <description>Port n Output Bit Set 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR2</name>
+              <description>Port n Output Bit Set 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR1</name>
+              <description>Port n Output Bit Set 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR0</name>
+              <description>Port n Output Bit Set 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_BCR</name>
+          <description>Port n Output Bit Clear Register</description>
+          <alternateRegister>BCR</alternateRegister>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BCR15</name>
+              <description>Port n Output Bit Clear 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR14</name>
+              <description>Port n Output Bit Clear 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR13</name>
+              <description>Port n Output Bit Clear 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR12</name>
+              <description>Port n Output Bit Clear 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR11</name>
+              <description>Port n Output Bit Clear 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR10</name>
+              <description>Port n Output Bit Clear 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR9</name>
+              <description>Port n Output Bit Clear 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR8</name>
+              <description>Port n Output Bit Clear 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR7</name>
+              <description>Port n Output Bit Clear 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR6</name>
+              <description>Port n Output Bit Clear 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR5</name>
+              <description>Port n Output Bit Clear 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR4</name>
+              <description>Port n Output Bit Clear 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR3</name>
+              <description>Port n Output Bit Clear 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR2</name>
+              <description>Port n Output Bit Clear 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR1</name>
+              <description>Port n Output Bit Clear 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR0</name>
+              <description>Port n Output Bit Clear 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_OUTDMSK</name>
+          <description>Port n Output Data Mask Register</description>
+          <alternateRegister>OUTDMSK</alternateRegister>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDMSK15</name>
+              <description>Port n Output Data Mask 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK14</name>
+              <description>Port n Output Data Mask 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK13</name>
+              <description>Port n Output Data Mask 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK12</name>
+              <description>Port n Output Data Mask 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK11</name>
+              <description>Port n Output Data Mask 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK10</name>
+              <description>Port n Output Data Mask 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK9</name>
+              <description>Port n Output Data Mask 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK8</name>
+              <description>Port n Output Data Mask 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK7</name>
+              <description>Port n Output Data Mask 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK6</name>
+              <description>Port n Output Data Mask 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK5</name>
+              <description>Port n Output Data Mask 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK4</name>
+              <description>Port n Output Data Mask 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK3</name>
+              <description>Port n Output Data Mask 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK2</name>
+              <description>Port n Output Data Mask 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK1</name>
+              <description>Port n Output Data Mask 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK0</name>
+              <description>Port n Output Data Mask 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PE_DBCR</name>
+          <description>Port n Debounce Control Register</description>
+          <alternateRegister>DBCR</alternateRegister>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DBCLK</name>
+              <description>Port n Debounce Filter Sampling Clock Selection</description>
+              <bitRange>[18:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN3</name>
+              <description>Port n Debounce Enable 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN2</name>
+              <description>Port n Debounce Enable 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN1</name>
+              <description>Port n Debounce Enable 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBEN0</name>
+              <description>Port n Debounce Enable 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="Pn">
+      <name>PF</name>
+      <version>1.0</version>
+      <description>Port Control Unit &amp; GPIO Port F</description>
+      <groupName>PCU &amp; GPIO</groupName>
+      <baseAddress>0x30000500</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PF_MOD</name>
+          <description>Port n Mode Register</description>
+          <alternateRegister>MOD</alternateRegister>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MODE11</name>
+              <description>Port n Mode Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE10</name>
+              <description>Port n Mode Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE9</name>
+              <description>Port n Mode Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE8</name>
+              <description>Port n Mode Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE7</name>
+              <description>Port n Mode Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE6</name>
+              <description>Port n Mode Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE5</name>
+              <description>Port n Mode Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE4</name>
+              <description>Port n Mode Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE3</name>
+              <description>Port n Mode Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE2</name>
+              <description>Port n Mode Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE1</name>
+              <description>Port n Mode Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE0</name>
+              <description>Port n Mode Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_TYP</name>
+          <description>Port n Output Type Selection Register</description>
+          <alternateRegister>TYP</alternateRegister>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TYP11</name>
+              <description>Port n Output Type Selection 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP10</name>
+              <description>Port n Output Type Selection 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP9</name>
+              <description>Port n Output Type Selection 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP8</name>
+              <description>Port n Output Type Selection 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP7</name>
+              <description>Port n Output Type Selection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP6</name>
+              <description>Port n Output Type Selection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP5</name>
+              <description>Port n Output Type Selection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP4</name>
+              <description>Port n Output Type Selection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP3</name>
+              <description>Port n Output Type Selection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP2</name>
+              <description>Port n Output Type Selection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP1</name>
+              <description>Port n Output Type Selection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TYP0</name>
+              <description>Port n Output Type Selection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_AFSR1</name>
+          <description>Port n Alternative Function Selection Register 1</description>
+          <alternateRegister>AFSR1</alternateRegister>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR7</name>
+              <description>Port n Alternative Function Selection 7</description>
+              <bitRange>[31:28]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR6</name>
+              <description>Port n Alternative Function Selection 6</description>
+              <bitRange>[27:24]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR5</name>
+              <description>Port n Alternative Function Selection 5</description>
+              <bitRange>[23:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR4</name>
+              <description>Port n Alternative Function Selection 4</description>
+              <bitRange>[19:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR3</name>
+              <description>Port n Alternative Function Selection 3</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR2</name>
+              <description>Port n Alternative Function Selection 2</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR1</name>
+              <description>Port n Alternative Function Selection 1</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR0</name>
+              <description>Port n Alternative Function Selection 0</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_AFSR2</name>
+          <description>Port n Alternative Function Selection Register 2</description>
+          <alternateRegister>AFSR2</alternateRegister>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>AFSR11</name>
+              <description>Port n Alternative Function Selection 11</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR10</name>
+              <description>Port n Alternative Function Selection 10</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR9</name>
+              <description>Port n Alternative Function Selection 9</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFSR8</name>
+              <description>Port n Alternative Function Selection 8</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_PUPD</name>
+          <description>Port n Pull-Up/Down Resistor Selection Register</description>
+          <alternateRegister>PUPD</alternateRegister>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PUPD11</name>
+              <description>Port n Pull-Up/Down Resistor Selection 11</description>
+              <bitRange>[23:22]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD10</name>
+              <description>Port n Pull-Up/Down Resistor Selection 10</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD9</name>
+              <description>Port n Pull-Up/Down Resistor Selection 9</description>
+              <bitRange>[19:18]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD8</name>
+              <description>Port n Pull-Up/Down Resistor Selection 8</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD7</name>
+              <description>Port n Pull-Up/Down Resistor Selection 7</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD6</name>
+              <description>Port n Pull-Up/Down Resistor Selection 6</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD5</name>
+              <description>Port n Pull-Up/Down Resistor Selection 5</description>
+              <bitRange>[11:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD4</name>
+              <description>Port n Pull-Up/Down Resistor Selection 4</description>
+              <bitRange>[09:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD3</name>
+              <description>Port n Pull-Up/Down Resistor Selection 3</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD2</name>
+              <description>Port n Pull-Up/Down Resistor Selection 2</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD1</name>
+              <description>Port n Pull-Up/Down Resistor Selection 1</description>
+              <bitRange>[03:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PUPD0</name>
+              <description>Port n Pull-Up/Down Resistor Selection 0</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_INDR</name>
+          <description>Port n Input Data Register</description>
+          <alternateRegister>INDR</alternateRegister>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xfffff000</resetMask>
+          <fields>
+            <field>
+              <name>INDR11</name>
+              <description>Port n Input Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR10</name>
+              <description>Port n Input Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR9</name>
+              <description>Port n Input Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR8</name>
+              <description>Port n Input Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR7</name>
+              <description>Port n Input Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR6</name>
+              <description>Port n Input Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR5</name>
+              <description>Port n Input Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR4</name>
+              <description>Port n Input Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR3</name>
+              <description>Port n Input Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR2</name>
+              <description>Port n Input Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR1</name>
+              <description>Port n Input Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INDR0</name>
+              <description>Port n Input Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_OUTDR</name>
+          <description>Port n Output Data Register</description>
+          <alternateRegister>OUTDR</alternateRegister>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDR11</name>
+              <description>Port n Output Data 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR10</name>
+              <description>Port n Output Data 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR9</name>
+              <description>Port n Output Data 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR8</name>
+              <description>Port n Output Data 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR7</name>
+              <description>Port n Output Data 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR6</name>
+              <description>Port n Output Data 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR5</name>
+              <description>Port n Output Data 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR4</name>
+              <description>Port n Output Data 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR3</name>
+              <description>Port n Output Data 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR2</name>
+              <description>Port n Output Data 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR1</name>
+              <description>Port n Output Data 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDR0</name>
+              <description>Port n Output Data 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_BSR</name>
+          <description>Port n Output Bit Set Register</description>
+          <alternateRegister>BSR</alternateRegister>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BSR11</name>
+              <description>Port n Output Bit Set 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR10</name>
+              <description>Port n Output Bit Set 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR9</name>
+              <description>Port n Output Bit Set 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR8</name>
+              <description>Port n Output Bit Set 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR7</name>
+              <description>Port n Output Bit Set 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR6</name>
+              <description>Port n Output Bit Set 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR5</name>
+              <description>Port n Output Bit Set 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR4</name>
+              <description>Port n Output Bit Set 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR3</name>
+              <description>Port n Output Bit Set 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR2</name>
+              <description>Port n Output Bit Set 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR1</name>
+              <description>Port n Output Bit Set 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BSR0</name>
+              <description>Port n Output Bit Set 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_BCR</name>
+          <description>Port n Output Bit Clear Register</description>
+          <alternateRegister>BCR</alternateRegister>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BCR11</name>
+              <description>Port n Output Bit Clear 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR10</name>
+              <description>Port n Output Bit Clear 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR9</name>
+              <description>Port n Output Bit Clear 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR8</name>
+              <description>Port n Output Bit Clear 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR7</name>
+              <description>Port n Output Bit Clear 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR6</name>
+              <description>Port n Output Bit Clear 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR5</name>
+              <description>Port n Output Bit Clear 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR4</name>
+              <description>Port n Output Bit Clear 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR3</name>
+              <description>Port n Output Bit Clear 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR2</name>
+              <description>Port n Output Bit Clear 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR1</name>
+              <description>Port n Output Bit Clear 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BCR0</name>
+              <description>Port n Output Bit Clear 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PF_OUTDMSK</name>
+          <description>Port n Output Data Mask Register</description>
+          <alternateRegister>OUTDMSK</alternateRegister>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>OUTDMSK11</name>
+              <description>Port n Output Data Mask 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK10</name>
+              <description>Port n Output Data Mask 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK9</name>
+              <description>Port n Output Data Mask 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK8</name>
+              <description>Port n Output Data Mask 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK7</name>
+              <description>Port n Output Data Mask 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK6</name>
+              <description>Port n Output Data Mask 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK5</name>
+              <description>Port n Output Data Mask 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK4</name>
+              <description>Port n Output Data Mask 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK3</name>
+              <description>Port n Output Data Mask 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK2</name>
+              <description>Port n Output Data Mask 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK1</name>
+              <description>Port n Output Data Mask 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDMSK0</name>
+              <description>Port n Output Data Mask 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>FMC</name>
+      <version>1.0</version>
+      <description>Flash Memory Controller</description>
+      <groupName>Flash Memory Controller</groupName>
+      <baseAddress>0x40001b00</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>ADR</name>
+          <description>Flash Memory Address Register</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x5fffff80</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Flash Memory Address Pointer</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDR1</name>
+          <description>Flash Memory Identification Register 1</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ID1</name>
+              <description>Flash Memory Identification 1</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDR2</name>
+          <description>Flash Memory Identification Register 2</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ID2</name>
+              <description>Flash Memory Identification 2</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CR</name>
+          <description>Flash Memory Control Register</description>
+          <addressOffset>0x00c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0x6c93)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0x6c93)</description>
+                  <value>0x6c93</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FMKEY</name>
+              <description>Flash Memory Operation Area Selection</description>
+              <bitRange>[15:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FMBUSY</name>
+              <description>Flash Memory Operation Mode Busy</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FMOD</name>
+              <description>Flash Memory Operation Mode Selection</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BCR</name>
+          <description>Flash Memory Configure Area Bulk Erase Control Register</description>
+          <addressOffset>0x010</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0xc1be)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0xc1be)</description>
+                  <value>0xc1be</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNF3BEN</name>
+              <description>Configure Option Page 3 Bulk Erase Enable</description>
+              <bitRange>[11:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNF2BEN</name>
+              <description>Configure Option Page 2 Bulk Erase Enable</description>
+              <bitRange>[07:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNF1BEN</name>
+              <description>Configure Option Page 1 Bulk Erase Enable</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERFLAG</name>
+          <description>Flash Memory Error Flag</description>
+          <addressOffset>0x014</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>INSTFLAG</name>
+              <description>Don't care</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FMOPFLAG</name>
+              <description>Error bit of Flash Memory Operation Procedure</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAGEBUF</name>
+          <description>Flash Memory Page Buffer Area (128bytes/Accessed by 32bit Word Only)</description>
+          <addressOffset>0x100</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>1.0</version>
+      <description>Watch-Dog Timer</description>
+      <groupName>Watch-Dog Timer</groupName>
+      <baseAddress>0x40001a00</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT</name>
+        <description>WDT Interrupt</description>
+        <value>02</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>Watch-Dog Timer Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0x5a69)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0x5a69)</description>
+                  <value>0x5a69</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RSTEN</name>
+              <description>Watch-Dog Timer Reset Enable</description>
+              <bitRange>[15:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable Watch-Dog Timer reset. (0x25)</description>
+                  <value>0x25</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable Watch-Dog Timer reset.</description>
+                  <value>0x00</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTEN</name>
+              <description>Watch-Dog Timer Counter Enable</description>
+              <bitRange>[09:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable Watch-Dog Timer counter. (0x1a)</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable Watch-Dog Timer counter.</description>
+                  <value>0x00</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINMIEN</name>
+              <description>Watch-Dog Timer Window Match Interrupt Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable window data match interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable window data match interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UNFIEN</name>
+              <description>Watch-Dog Timer Underflow Interrupt Enable</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable Watch-Dog Timer underflow interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable Watch-Dog Timer underflow interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKDIV</name>
+              <description>Watch-Dog Timer Clock Divider</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>fWDT4</name>
+                  <description>fWDT/4</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fWDT16</name>
+                  <description>fWDT/16</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fWDT64</name>
+                  <description>fWDT/64</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fWDT256</name>
+                  <description>fWDT/256</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>Watch-Dog Timer Status Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x80</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DBGCNTEN</name>
+              <description>Watch-Dog Timer Counter Enable when the core is halted in debug mode</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Run</name>
+                  <description>The Watch-Dog Timer counter continues even if the core is halted</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Stop</name>
+                  <description>The Watch-Dog Timer counter is stopped when the core is halted</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINMIFLAG</name>
+              <description>Watch-Dog Timer Window Match Interrupt Flag</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UNFIFLAG</name>
+              <description>Watch-Dog Timer Underflow Interrupt Flag</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DR</name>
+          <description>Watch-Dog Timer Data Register</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xfff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Watch-Dog Timer Data</description>
+              <bitRange>[23:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNT</name>
+          <description>Watch-Dog Timer Counter Register</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0xfff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>Watch-Dog Timer Counter</description>
+              <bitRange>[23:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINDR</name>
+          <description>Watch-Dog Timer Window Data Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1fff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WDATA</name>
+              <description>Watch-Dog Timer Window Data</description>
+              <bitRange>[23:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNTR</name>
+          <description>Watch-Dog Timer Counter Reload Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CNTR</name>
+              <description>Watch-Dog Timer Counter Reload</description>
+              <bitRange>[07:00]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Reload</name>
+                  <description>Reload the WDTDR value to Watch-Dog Timer counter and re-start. (0x6a) (Automatically cleared to '0x00' after operation.)</description>
+                  <value>0x6a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0x00</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WT</name>
+      <version>1.0</version>
+      <description>Watch Timer</description>
+      <groupName>Watch Timer</groupName>
+      <baseAddress>0x40002000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WT</name>
+        <description>WT Interrupt</description>
+        <value>12</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>Watch Timer Control Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTEN</name>
+              <description>Watch Timer Operation Enable</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable watch timer operation.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable watch timer operation.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WTINTV</name>
+              <description>Watch Timer Interval Selection</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>fWT2Pow7</name>
+                  <description>fWT/2^7</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fWT2Pow13</name>
+                  <description>fWT/2^13</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fWT2Pow14</name>
+                  <description>fWT/2^14</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fWT2Pow14DR</name>
+                  <description>fWT/(2^14x(WTDR value + 1))</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WTIEN</name>
+              <description>Watch Timer Interrupt Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable watch timer interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable watch timer interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WTIFLAG</name>
+              <description>Watch Timer Interrupt Flag</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WTCLR</name>
+              <description>Watch Timer Counter and Divider Clear</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear the counter and divider. (Automatically cleared to '0b' after operation)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DR</name>
+          <description>Watch Timer Data Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xfff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTDATA</name>
+              <description>Watch Timer Data</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNT</name>
+          <description>Watch Timer Counter Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>Watch Timer Counter</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMER1n</name>
+      <version>1.0</version>
+      <description>Timer/Counter 1n</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x51000000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>TIMER1n Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T1nEN</name>
+              <description>TIMER1n Operation Enable</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nCLK</name>
+              <description>TIMER1n Clock Selection</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nMS</name>
+              <description>TIMER1n Operation Mode Selection</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nECE</name>
+              <description>TIMER1n External Clock Edge Selection</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nOPOL</name>
+              <description>TIMER1n Output Polarity Selection</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nCPOL</name>
+              <description>TIMER1n Capture Polarity Selection</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nMIEN</name>
+              <description>TIMER1n Match Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nCIEN</name>
+              <description>TIMER1n Capture Interrupt Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nMIFLAG</name>
+              <description>TIMER1n Match Interrupt Flag</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nCIFLAG</name>
+              <description>TIMER1n Capture Interrupt Flag</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nPAU</name>
+              <description>TIMER1n Counter Temporary Pause Control</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1nCLR</name>
+              <description>TIMER1n Counter and Prescaler Clear</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADR</name>
+          <description>TIMER1n A Data Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ADATA</name>
+              <description>TIMER1n A Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDR</name>
+          <description>TIMER1n B Data Register</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BDATA</name>
+              <description>TIMER1n B Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAPDR</name>
+          <description>TIMER1n Capture Data Register</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CAPD</name>
+              <description>TIMER1n Capture Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PREDR</name>
+          <description>TIMER1n Prescaler Data Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xfff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PRED</name>
+              <description>TIMER1n Prescaler Data</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNT</name>
+          <description>TIMER1n Counter Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>TIMER1n Counter</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMER1n">
+      <name>TIMER10</name>
+      <version>1.0</version>
+      <description>Timer/Counter 10</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002100</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER10</name>
+        <description>TIMER10 Interrupt</description>
+        <value>07</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TIMER1n">
+      <name>TIMER11</name>
+      <version>1.0</version>
+      <description>Timer/Counter 11</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002200</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER11</name>
+        <description>TIMER11 Interrupt</description>
+        <value>08</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TIMER1n">
+      <name>TIMER12</name>
+      <version>1.0</version>
+      <description>Timer/Counter 12</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002300</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER12</name>
+        <description>TIMER12 Interrupt</description>
+        <value>09</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TIMER1n">
+      <name>TIMER13</name>
+      <version>1.0</version>
+      <description>Timer/Counter 13</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002700</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER13</name>
+        <description>TIMER13 Interrupt</description>
+        <value>21</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TIMER1n">
+      <name>TIMER14</name>
+      <version>1.0</version>
+      <description>Timer/Counter 14</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002800</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER14</name>
+        <description>TIMER14 Interrupt</description>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TIMER1n">
+      <name>TIMER15</name>
+      <version>1.0</version>
+      <description>Timer/Counter 15</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002900</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER15</name>
+        <description>TIMER15 Interrupt</description>
+        <value>23</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TIMER1n">
+      <name>TIMER16</name>
+      <version>1.0</version>
+      <description>Timer/Counter 16</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002a00</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER16</name>
+        <description>TIMER16 Interrupt</description>
+        <value>24</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TIMER2n</name>
+      <version>1.0</version>
+      <description>Timer/Counter 2n</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x52000000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>TIMER2n Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T2nEN</name>
+              <description>TIMER2n Operation Enable</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCLK</name>
+              <description>TIMER2n Clock Selection</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMS</name>
+              <description>TIMER2n Operation Mode Selection</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nECE</name>
+              <description>TIMER2n External Clock Edge Selection</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAPSEL</name>
+              <description>TIMER2n Capture Signal Selection</description>
+              <bitRange>[10:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nOPOL</name>
+              <description>TIMER2n Output Polarity Selection</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCPOL</name>
+              <description>TIMER2n Capture Polarity Selection</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMIEN</name>
+              <description>TIMER2n Match Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCIEN</name>
+              <description>TIMER2n Capture Interrupt Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMIFLAG</name>
+              <description>TIMER2n Match Interrupt Flag</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCIFLAG</name>
+              <description>TIMER2n Capture Interrupt Flag</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nPAU</name>
+              <description>TIMER2n Counter Temporary Pause Control</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCLR</name>
+              <description>TIMER2n Counter and Prescaler Clear</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADR</name>
+          <description>TIMER2n A Data Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xffffffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ADATA</name>
+              <description>TIMER2n A Data</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDR</name>
+          <description>TIMER2n B Data Register</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xffffffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BDATA</name>
+              <description>TIMER2n B Data</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAPDR</name>
+          <description>TIMER2n Capture Data Register</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CAPD</name>
+              <description>TIMER2n Capture Data</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PREDR</name>
+          <description>TIMER2n Prescaler Data Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xfff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PRED</name>
+              <description>TIMER2n Prescaler Data</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNT</name>
+          <description>TIMER2n Counter Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>TIMER2n Counter</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMER2n">
+      <name>TIMER20</name>
+      <version>1.0</version>
+      <description>Timer/Counter 20</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002500</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER20</name>
+        <description>TIMER20 Interrupt</description>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>TIMER20_CR</name>
+          <description>TIMER2n Control Register</description>
+          <alternateRegister>CR</alternateRegister>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T2nEN</name>
+              <description>TIMER2n Operation Enable</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCLK</name>
+              <description>TIMER2n Clock Selection</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMS</name>
+              <description>TIMER2n Operation Mode Selection</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nECE</name>
+              <description>TIMER2n External Clock Edge Selection</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAPSEL</name>
+              <description>TIMER2n Capture Signal Selection</description>
+              <bitRange>[10:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nOPOL</name>
+              <description>TIMER2n Output Polarity Selection</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCPOL</name>
+              <description>TIMER2n Capture Polarity Selection</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMIEN</name>
+              <description>TIMER2n Match Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCIEN</name>
+              <description>TIMER2n Capture Interrupt Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMIFLAG</name>
+              <description>TIMER2n Match Interrupt Flag</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCIFLAG</name>
+              <description>TIMER2n Capture Interrupt Flag</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nPAU</name>
+              <description>TIMER2n Counter Temporary Pause Control</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCLR</name>
+              <description>TIMER2n Counter and Prescaler Clear</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMER2n">
+      <name>TIMER21</name>
+      <version>1.0</version>
+      <description>Timer/Counter 21</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002600</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER21</name>
+        <description>TIMER21 Interrupt</description>
+        <value>16</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>TIMER21_CR</name>
+          <description>TIMER2n Control Register</description>
+          <alternateRegister>CR</alternateRegister>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T2nEN</name>
+              <description>TIMER2n Operation Enable</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCLK</name>
+              <description>TIMER2n Clock Selection</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMS</name>
+              <description>TIMER2n Operation Mode Selection</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nECE</name>
+              <description>TIMER2n External Clock Edge Selection</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nOPOL</name>
+              <description>TIMER2n Output Polarity Selection</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCPOL</name>
+              <description>TIMER2n Capture Polarity Selection</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMIEN</name>
+              <description>TIMER2n Match Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCIEN</name>
+              <description>TIMER2n Capture Interrupt Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nMIFLAG</name>
+              <description>TIMER2n Match Interrupt Flag</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCIFLAG</name>
+              <description>TIMER2n Capture Interrupt Flag</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nPAU</name>
+              <description>TIMER2n Counter Temporary Pause Control</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T2nCLR</name>
+              <description>TIMER2n Counter and Prescaler Clear</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMER3n</name>
+      <version>1.0</version>
+      <description>Timer/Counter 3n</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x53000000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>TIMER3n Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T3nEN</name>
+              <description>TIMER3n Operation Enable</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable TIMER3n Operation.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable TIMER3n Operation. (Counter Clear and Start)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nCLK</name>
+              <description>TIMER3n Clock Selection</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>IntPrescaledClock</name>
+                  <description>Select an Internal Prescaler Clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ExtClock</name>
+                  <description>Select an External Clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nMS</name>
+              <description>TIMER3n Operation Mode Selection</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>IntervalMode</name>
+                  <description>Interval mode. (All match interrupts can occur)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CaptureMode</name>
+                  <description>Capture mode. (The Period-match interrupt can occur)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BackToBackMode</name>
+                  <description>Back-to-back mode. (All interrupts can occur)</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nECE</name>
+              <description>TIMER3n External Clock Edge Selection</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FallingEdge</name>
+                  <description>Select falling edge of external clock.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdge</name>
+                  <description>Select rising edge of external clock.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FORCA</name>
+              <description>TIMER3n Output Mode Selection</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AllChannelMode</name>
+                  <description>6-Channel mode. (The PWM3nxA/PWM3nxB pins are outputs according to the TIMER30_xDR registers, respectively.)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AChannelMode</name>
+                  <description>Force A-Channel mode. (All PWM3nxA/PWM3nxB pins are outputs according only to the TIMER30_ADR register.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DLYEN</name>
+              <description>Delay Time Insertion Enable</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable delay time insertion to the PWM3nxA/PWM3nxB.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable delay time insertion to the PWM3nxA/PWM3nxB.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DLYPOS</name>
+              <description>Delay Time Insertion Position</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FrontABehindB</name>
+                  <description>Insert in front of PWM3nxA and behind PWM3nxB pins.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BehindAFrontB</name>
+                  <description>Insert behind PWM3nxA and in front of PWM3nxB pins.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nCPOL</name>
+              <description>TIMER3n Capture Polarity Selection</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FallingEdge</name>
+                  <description>Capture on falling edge.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdge</name>
+                  <description>Capture on rising edge.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BothEdge</name>
+                  <description>Capture on both falling and rising edge.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>UPDT</name>
+              <description>Data Reload Time Selection</description>
+              <bitRange>[05:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AtWriting</name>
+                  <description>Update data to buffer at the time of writing.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AtPeriodMatch</name>
+                  <description>Update data to buffer at period match.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AtBottom</name>
+                  <description>Update data to buffer at bottom.</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMOC</name>
+              <description>Period Match Interrupt Occurrence Selection</description>
+              <bitRange>[03:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Every1PeriodMatch</name>
+                  <description>Once every 1 period match.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Every2PeriodMatch</name>
+                  <description>Once every 2 period match.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Every3PeriodMatch</name>
+                  <description>Once every 3 period match.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Every4PeriodMatch</name>
+                  <description>Once every 4 period match.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Every5PeriodMatch</name>
+                  <description>Once every 5 period match.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Every6PeriodMatch</name>
+                  <description>Once every 6 period match.</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Every7PeriodMatch</name>
+                  <description>Once every 7 period match.</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Every8PeriodMatch</name>
+                  <description>Once every 8 period match.</description>
+                  <value>7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nCLR</name>
+              <description>TIMER3n Counter and Prescaler Clear</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear TIMER3n counter and prescaler. (Automatically cleared to '0b' after operation)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDR</name>
+          <description>TIMER3n Period Data Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PDATA</name>
+              <description>TIMER3n Period Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADR</name>
+          <description>TIMER3n A Data Register</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ADATA</name>
+              <description>TIMER3n A Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDR</name>
+          <description>TIMER3n B Data Register</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BDATA</name>
+              <description>TIMER3n B Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CDR</name>
+          <description>TIMER3n C Data Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CDATA</name>
+              <description>TIMER3n C Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAPDR</name>
+          <description>TIMER3n Capture Data Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CAPD</name>
+              <description>TIMER3n Capture Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PREDR</name>
+          <description>TIMER3n Prescaler Data Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xfff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PRED</name>
+              <description>TIMER3n Prescaler Data</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNT</name>
+          <description>TIMER3n Counter Register</description>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>TIMER3n Counter</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTCR</name>
+          <description>TIMER3n Output Control Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>POLB</name>
+              <description>PWM3nxB Output Polarity Selection</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>StartLow</name>
+                  <description>Low level start. (The PWM3nxB pins are started with low level after counting.)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>StartHigh</name>
+                  <description>High level start. (The PWM3nxB pins are started with high level after counting)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POLA</name>
+              <description>PWM3nxA Output Polarity Selection</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>StartLow</name>
+                  <description>Low level start. (The PWM3nxA pins are started with low level after counting.)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>StartHigh</name>
+                  <description>High level start. (The PWM3nxA pins are started with high level after counting)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PABOE</name>
+              <description>PWM3nAB Output Enable</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable output.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable output.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PBBOE</name>
+              <description>PWM3nBB Output Enable</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable output.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable output.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PCBOE</name>
+              <description>PWM3nCB Output Enable</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable output.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable output.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PAAOE</name>
+              <description>PWM3nAA Output Enable</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable output.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable output.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PBAOE</name>
+              <description>PWM3nBA Output Enable</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable output.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable output.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PCAOE</name>
+              <description>PWM3nCA Output Enable</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable output.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable output.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVLAB</name>
+              <description>Configure PWM3nAB Output when Disable</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Low</name>
+                  <description>Low level.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>High</name>
+                  <description>High level.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVLBB</name>
+              <description>Configure PWM3nBB Output when Disable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Low</name>
+                  <description>Low level.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>High</name>
+                  <description>High level.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVLCB</name>
+              <description>Configure PWM3nCB Output when Disable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Low</name>
+                  <description>Low level.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>High</name>
+                  <description>High level.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVLAA</name>
+              <description>Configure PWM3nAA Output when Disable</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Low</name>
+                  <description>Low level.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>High</name>
+                  <description>High level.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVLBA</name>
+              <description>Configure PWM3nBA Output when Disable</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Low</name>
+                  <description>Low level.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>High</name>
+                  <description>High level.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVLCA</name>
+              <description>Configure PWM3nCA Output when Disable</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Low</name>
+                  <description>Low level.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>High</name>
+                  <description>High level.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DLY</name>
+          <description>TIMER3n PWM Output Delay Data Register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DLY</name>
+              <description>TIMER3n PWM Delay Data</description>
+              <bitRange>[09:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTCR</name>
+          <description>TIMER3n Interrupt Control Register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>HIZIEN</name>
+              <description>TIMER3n Output High-Impedance Interrupt Enable</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable TIMER3n output high-impedance interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable TIMER3n output high-impedance interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nCIEN</name>
+              <description>TIMER3n Capture Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable TIMER3n capture interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable TIMER3n capture interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nBTIEN</name>
+              <description>TIMER3n Bottom Interrupt Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable TIMER3n bottom interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable TIMER3n bottom interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nPMIEN</name>
+              <description>TIMER3n Period Match Interrupt Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable TIMER3n period interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable TIMER3n period interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nAMIEN</name>
+              <description>TIMER3n A-ch Match Interrupt Enable</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable TIMER3n A-ch match interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable TIMER3n A-ch match interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nBMIEN</name>
+              <description>TIMER3n B-ch Match Interrupt Enable</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable TIMER3n B-ch match interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable TIMER3n B-ch match interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nCMIEN</name>
+              <description>TIMER3n C-ch Match Interrupt Enable</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable TIMER3n C-ch match interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable TIMER3n C-ch match interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>TIMER3n Interrupt Flag Register</description>
+          <addressOffset>0x2c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>HIZIFLAG</name>
+              <description>TIMER3n Output High-Impedance Interrupt Flag</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred. The bit will be cleared to '0' when '1' is written to this bit.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nCIFLAG</name>
+              <description>TIMER3n Capture Interrupt Flag</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred. The bit will be cleared to '0' when '1' is written to this bit.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nBTIFLAG</name>
+              <description>TIMER3n Bottom Interrupt Flag</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred. The bit will be cleared to '0' when '1' is written to this bit.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nPMIFLAG</name>
+              <description>TIMER3n Period Match Interrupt Flag</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred. The bit will be cleared to '0' when '1' is written to this bit.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nAMIFLAG</name>
+              <description>TIMER3n A-ch Match Interrupt Flag</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred. The bit will be cleared to '0' when '1' is written to this bit.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nBMIFLAG</name>
+              <description>TIMER3n B-ch Match Interrupt Flag</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred. The bit will be cleared to '0' when '1' is written to this bit.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nCMIFLAG</name>
+              <description>TIMER3n C-ch Match Interrupt Flag</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred. The bit will be cleared to '0' when '1' is written to this bit.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIZCR</name>
+          <description>TIMER3n High-Impedance Control Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>HIZEN</name>
+              <description>PWM3nxA/PWM3nxB Output High-Impedance Enable</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable to control the output high-impedance.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable to control the output high-impedance.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HIZSW</name>
+              <description>High-Impedance Output Software Setting</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HiZ</name>
+                  <description>PWM3nxA/PWM3nxB pins go into high impedance. (Automatically cleared to '0' after operation)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HEDGE</name>
+              <description>High-Impedance Edge Selection</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>FallingEdge</name>
+                  <description>Falling edge of the BLNK pin.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RisingEdge</name>
+                  <description>Rising edge of the BLNK pin.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HIZSTA</name>
+              <description>High-Impedance Status</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoHiZ</name>
+                  <description>Indicates that the pins are not under a Hi-Z state.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HiZ</name>
+                  <description>Indicates that the pins are under a Hi-Z state.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HIZCLR</name>
+              <description>High-Impedance Output Clear</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Clear</name>
+                  <description>Clear high-impedance output. (The PWM3nxA/PWM3nxB pins returns as output and this bit is automatically cleared to '0' after operation.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADTCR</name>
+          <description>TIMER3n ADC Trigger Control Register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>T3nBTTG</name>
+              <description>Select TIMER3n Bottom for ADC Trigger Signal Generator.</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable ADC trigger signal generator by bottom.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable ADC trigger signal generator by bottom.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nPMTG</name>
+              <description>Select TIMER3n Period Match for ADC Trigger Signal Generator.</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable ADC trigger signal generator by period match.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable ADC trigger signal generator by period match.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nAMTG</name>
+              <description>Select TIMER3n A-ch Match for ADC Trigger Signal Generator.</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable ADC trigger signal generator by A-ch match.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable ADC trigger signal generator by A-ch match.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nBMTG</name>
+              <description>Select TIMER3n B-ch Match for ADC Trigger Signal Generator.</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable ADC trigger signal generator by B-ch match.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable ADC trigger signal generator by B-ch match.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>T3nCMTG</name>
+              <description>Select TIMER3n C-ch Match for ADC Trigger Signal Generator.</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable ADC trigger signal generator by C-ch match.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable ADC trigger signal generator by C-ch match.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADTDR</name>
+          <description>TIMER3n ADC Trigger Generator Data Register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ADTDATA</name>
+              <description>TIMER3n ADC Trigger Generation Data</description>
+              <bitRange>[13:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMER3n">
+      <name>TIMER30</name>
+      <version>1.0</version>
+      <description>Timer/Counter 30</description>
+      <groupName>Timer/Counter</groupName>
+      <baseAddress>0x40002400</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIMER30</name>
+        <description>TIMER30 Interrupt</description>
+        <value>13</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>T30_OUTCR</name>
+          <description>TIMER3n Output Control Register</description>
+          <alternateRegister>OUTCR</alternateRegister>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0xe06c)</description>
+              <bitRange>[31:16]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0xe06c)</description>
+                  <value>0xe06c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POLB</name>
+              <description>PWM3nxB Output Polarity Selection</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POLA</name>
+              <description>PWM3nxA Output Polarity Selection</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PABOE</name>
+              <description>PWM3nAB Output Enable</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBBOE</name>
+              <description>PWM3nBB Output Enable</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCBOE</name>
+              <description>PWM3nCB Output Enable</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAAOE</name>
+              <description>PWM3nAA Output Enable</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBAOE</name>
+              <description>PWM3nBA Output Enable</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCAOE</name>
+              <description>PWM3nCA Output Enable</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LVLAB</name>
+              <description>Configure PWM3nAB Output when Disable</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LVLBB</name>
+              <description>Configure PWM3nBB Output when Disable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LVLCB</name>
+              <description>Configure PWM3nCB Output when Disable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LVLAA</name>
+              <description>Configure PWM3nAA Output when Disable</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LVLBA</name>
+              <description>Configure PWM3nBA Output when Disable</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LVLCA</name>
+              <description>Configure PWM3nCA Output when Disable</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.0</version>
+      <description>12 Bit A/D Converter</description>
+      <groupName>A/D Converter</groupName>
+      <baseAddress>0x40003000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC</name>
+        <description>ADC Interrupt</description>
+        <value>18</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>A/D Converter Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>ADCEN</name>
+              <description>ADC Module Enable</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable ADC module operation.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable ADC module operation.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIG</name>
+              <description>ADC Trigger Signal Selection</description>
+              <bitRange>[13:11]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ADST</name>
+                  <description>Select ADST.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TIMER10</name>
+                  <description>Select TIMER10 A-Match Signal.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TIMER11</name>
+                  <description>Select TIMER11 A-Match Signal.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TIMER12</name>
+                  <description>Select TIMER12 A-Match Signal.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TIMER30</name>
+                  <description>Select ADC Trigger Signal from TIMER30.</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>ADC Reference Selection</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Vdd</name>
+                  <description>Select analog power (VDD).</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVref</name>
+                  <description>Select external reference (AVREF).</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADST</name>
+              <description>ADC Conversion Start</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Start</name>
+                  <description>Trigger signal generation for conversion start.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADCIEN</name>
+              <description>ADC Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable ADC interrupt.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable ADC interrupt.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADCIFLAG</name>
+              <description>ADC Interrupt Flag</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoRequest</name>
+                  <description>No request occurred.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Request</name>
+                  <description>Request occurred.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADSEL</name>
+              <description>A/D Converter Channel Selection</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AN0</name>
+                  <description>Select AN0.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN1</name>
+                  <description>Select AN1.</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN2</name>
+                  <description>Select AN2.</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN3</name>
+                  <description>Select AN3.</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN4</name>
+                  <description>Select AN4.</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN5</name>
+                  <description>Select AN5.</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN6</name>
+                  <description>Select AN6.</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN7</name>
+                  <description>Select AN7.</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN8</name>
+                  <description>Select AN8.</description>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN9</name>
+                  <description>Select AN9.</description>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN10</name>
+                  <description>Select AN10.</description>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN11</name>
+                  <description>Select AN11</description>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN12</name>
+                  <description>Select AN12</description>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AN13</name>
+                  <description>Select AN13</description>
+                  <value>13</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DR</name>
+          <description>A/D Converter Data Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xfffff000</resetMask>
+          <fields>
+            <field>
+              <name>ADDATA</name>
+              <description>A/D Converter Result Data</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PREDR</name>
+          <description>A/D Converter Prescaler Data Register</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xf</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>PRED</name>
+              <description>A/D Converter Prescaler Data</description>
+              <bitRange>[04:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>USART1n</name>
+      <version>1.0</version>
+      <description>USART 1n (USART + SPI)</description>
+      <groupName>USART &amp; SPI</groupName>
+      <baseAddress>0x54000000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CR1</name>
+          <description>USART1n Control Register 1</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>USTnMS</name>
+              <description>USART1n Operation Mode Selection</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Async</name>
+                  <description>Asynchronous Mode (UART)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Sync</name>
+                  <description>Synchronous Mode (USRT)</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI</name>
+                  <description>SPI Mode</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USTnP</name>
+              <description>Selects Parity Generation and Check method (only UART mode)</description>
+              <bitRange>[13:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No</name>
+                  <description>No Parity</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Even</name>
+                  <description>Even Parity</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Odd</name>
+                  <description>Odd Parity</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>USTnS</name>
+              <description>Selects the length of data bit in a frame when Asynchronous or Synchronous mode</description>
+              <bitRange>[11:09]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>5bit</name>
+                  <description>5 bit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>6bit</name>
+                  <description>6 bit</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>7bit</name>
+                  <description>7 bit</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8bit</name>
+                  <description>8 bit</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9bit</name>
+                  <description>9 bit</description>
+                  <value>7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ORDn</name>
+              <description>Selects the first data bit to be transmitted (only SPI mode)</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>lsbFirst</name>
+                  <description>LSB First</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>msbFirst</name>
+                  <description>MSB First</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPOLn</name>
+              <description>Selects the Clock Polarity of ACK in Synchronous or SPI mode</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>IdleLow</name>
+                  <description>TXD Change @Rising Edge, RXD Change @Falling Edge</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IdleHigh</name>
+                  <description>TXD Change @Falling Edge, RXD Change @Rising Edge</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CPHAn</name>
+              <description>The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>StartIdle</name>
+                  <description>Start with idle state.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>StartInverted</name>
+                  <description>Start with inverted idle state.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DRIEn</name>
+              <description>Transmit Data Register Empty Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXCIEn</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXCIEn</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEIEn</name>
+              <description>Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXEn</name>
+              <description>Enable the transmitter unit.</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXEn</name>
+              <description>Enable the receiver unit.</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CR2</name>
+          <description>USART1n Control Register 2</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>USTnEN</name>
+              <description>Activate USART1n Block</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBLSn</name>
+              <description>Selects receiver sampling rate (only UART mode)</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTERn</name>
+              <description>Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPSn</name>
+              <description>Control the Loop Back mode of USART1n for test mode</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISSCKn</name>
+              <description>In synchronous mode operation, selects the waveform of SCK1n output</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USTnSSEN</name>
+              <description>This bit controls the SS1n pin operation (only SPI mode)</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FXCHn</name>
+              <description>SPI1n port function exchange control (only SPI mode)</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USTnSB</name>
+              <description>Selects the length of stop bit in Asynchronous or Synchronous mode</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USTnTX8</name>
+              <description>The ninth bit of data frame in Asynchronous or Synchronous mode of operation</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USTnRX8</name>
+              <description>The ninth bit of data frame in Asynchronous or Synchronous mode of operation</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ST</name>
+          <description>USART1n Status Register</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x80</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DREn</name>
+              <description>Transmit Data Register Empty Interrupt Flag</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXCn</name>
+              <description>Transmit Complete Interrupt Flag</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXCn</name>
+              <description>Receive Complete Interrupt Flag</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEn</name>
+              <description>Asynchronous Wake-Up Interrupt Flag</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DORn</name>
+              <description>This bit is set if data OverRun takes place</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FEn</name>
+              <description>This bit is set if the first stop bit of next character in the receive buffer is detected as '0'</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PEn</name>
+              <description>This bit is set if the next character in the receive buffer has a Parity Error while parity is checked</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDR</name>
+          <description>USART1n Baud Rate Generation Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xfff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BDATA</name>
+              <description>The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DR</name>
+          <description>USART1n Data Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="USART1n">
+      <name>USART10</name>
+      <version>1.0</version>
+      <description>USART 10 (USART + SPI)</description>
+      <groupName>USART &amp; SPI</groupName>
+      <baseAddress>0x40003800</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USART10</name>
+        <description>USART10 Interrupt</description>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="USART1n">
+      <name>USART11</name>
+      <version>1.0</version>
+      <description>USART 11 (USART + SPI)</description>
+      <groupName>USART &amp; SPI</groupName>
+      <baseAddress>0x40003900</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USART11</name>
+        <description>USART11 Interrupt</description>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="USART1n">
+      <name>USART12</name>
+      <version>1.0</version>
+      <description>USART 12 (USART + SPI)</description>
+      <groupName>USART &amp; SPI</groupName>
+      <baseAddress>0x40003a00</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USART12</name>
+        <description>USART12 Interrupt</description>
+        <value>26</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="USART1n">
+      <name>USART13</name>
+      <version>1.0</version>
+      <description>USART 13 (USART + SPI)</description>
+      <groupName>USART &amp; SPI</groupName>
+      <baseAddress>0x40003b00</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USART13</name>
+        <description>USART13 Interrupt</description>
+        <value>27</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>UARTn</name>
+      <version>1.0</version>
+      <description>UART n</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x55000000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>RBR</name>
+          <description>UARTn Receive Data Buffer Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>RBR</name>
+              <description>UARTn Receive Data Buffer</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THR</name>
+          <description>UARTn Transmit Data Hold Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>THR</name>
+              <description>UARTn Transmit Data Hold</description>
+              <bitRange>[07:00]</bitRange>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IER</name>
+          <description>UARTn Interrupt Enable Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TXEIE</name>
+              <description>Transmit Empty Interrupt Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RLSIE</name>
+              <description>Receiver Line Status Interrupt Enable</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THREIE</name>
+              <description>Transmit Holding Register Empty Interrupt Enable</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRIE</name>
+              <description>Data Receive Interrupt Enable</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IIR</name>
+          <description>UARTn Interrupt ID Register</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TXE</name>
+              <description>Transmit Complete Interrupt Source ID</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IID</name>
+              <description>UARTn Interrupt ID</description>
+              <bitRange>[02:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IPEN</name>
+              <description>Interrupt Pending</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCR</name>
+          <description>UARTn Line Control Register</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BREAK</name>
+              <description>Transfer Break Control</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STICKP</name>
+              <description>Force Parity</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY</name>
+              <description>Parity Mode and Parity Stuck Selection</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PEN</name>
+              <description>Parity Bit Transfer Enable</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOPBIT</name>
+              <description>Stop Bit Length Selection</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DLEN</name>
+              <description>Data Length Selection</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCR</name>
+          <description>UARTn Data Control Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>LBON</name>
+              <description>Local Loopback Test Mode Enable</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXINV</name>
+              <description>Receive Data Inversion Selection</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXINV</name>
+              <description>Transmit Data Inversion Selection</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LSR</name>
+          <description>UARTn Line Status Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x60</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>TEMT</name>
+              <description>Transmit Register Empty</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRE</name>
+              <description>Transmit Hold Register Empty</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BI</name>
+              <description>Break Condition Indication</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FE</name>
+              <description>Frame Error Indicator</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PE</name>
+              <description>Parity Error Indicator</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Overrun Error Indicator</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DR</name>
+              <description>Data Receive Indicator</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BDR</name>
+          <description>UARTn Baud Rate Divisor Latch Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BDR</name>
+              <description>Baud Rate Divider Latch Value</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BFR</name>
+          <description>UARTn Baud Rate Fractional Counter Value</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>BFR</name>
+              <description>Fraction Counter value</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable fraction counter.</description>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDTR</name>
+          <description>UARTn Inter-frame Delay Time Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0xc0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>SMS</name>
+              <description>Start Bit Multi Sampling Enable</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMS</name>
+              <description>Data Bit Multi Sampling Enable</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAITVAL</name>
+              <description>Wait Time Value</description>
+              <bitRange>[02:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UARTn">
+      <name>UART0</name>
+      <version>1.0</version>
+      <description>UART 0</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x40004000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART0</name>
+        <description>UART0 Interrupt</description>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="UARTn">
+      <name>UART1</name>
+      <version>1.0</version>
+      <description>UART 1</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x40004100</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART1</name>
+        <description>UART1 Interrupt</description>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>I2Cn</name>
+      <version>1.0</version>
+      <description>I2C n</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x56000000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>I2Cn Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>I2CnEN</name>
+              <description>Activate I2Cn Block by supplying</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXDLYENBn</name>
+              <description>SDHR Register Control</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2CnIEN</name>
+              <description>I2Cn Interrupt Enable</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2CnIFLAG</name>
+              <description>I2Cn Interrupt Flag</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ACKnEN</name>
+              <description>Controls ACK signal generation at ninth SCL period</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IMASTERn</name>
+              <description>Represent Operation Mode of I2Cn</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STOPCn</name>
+              <description>STOP Condition Generation when I2Cn is master</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STARTCn</name>
+              <description>START Condition Generation when I2Cn is master</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ST</name>
+          <description>I2Cn Status Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>GCALLn</name>
+              <description>
+                This bit has different meaning depending on whether I2C is master or slave.
+                When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.
+                When I2C is a slave, this bit is used to indicate general call.
+              </description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TENDn</name>
+              <description>This bit is set when 1-byte of data is transferred completely</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOPDn</name>
+              <description>This bit is set when a STOP condition is detected</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SSELn</name>
+              <description>This bit is set when I2C is addressed by other master</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MLOSTn</name>
+              <description>This bit represents the result of bus arbitration in master mode</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUSYn</name>
+              <description>This bit reflects bus status</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TMODEn</name>
+              <description>This bit is used to indicate whether I2C is transmitter or receiver</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXACKn</name>
+              <description>This bit shows the state of ACK signal</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1</name>
+          <description>I2Cn Slave Address Register 1</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>SLAn</name>
+              <description>These bits configure the slave address 1 in slave mode</description>
+              <bitRange>[07:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GCALLnEN</name>
+              <description>This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2</name>
+          <description>I2Cn Slave Address Register 2</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>SLAn</name>
+              <description>These bits configure the slave address 2 in slave mode</description>
+              <bitRange>[07:01]</bitRange>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GCALLnEN</name>
+              <description>This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DR</name>
+          <description>I2Cn Data Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDHR</name>
+          <description>I2Cn SDA Hold Time Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>HLDT</name>
+              <description>This register is used to control SDA output timing from the falling edge of SCL</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCLR</name>
+          <description>I2Cn SCL Low Period Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x3f</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>SCLL</name>
+              <description>This register defines the low period of SCL in master mode</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCHR</name>
+          <description>I2Cn SCL High Period Register</description>
+          <addressOffset>0x1c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x3f</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>SCLH</name>
+              <description>This register defines the high period of SCL in master mode</description>
+              <bitRange>[11:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="I2Cn">
+      <name>I2C0</name>
+      <version>1.0</version>
+      <description>I2C 0</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x40004800</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C0</name>
+        <description>I2C0 Interrupt</description>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="I2Cn">
+      <name>I2C1</name>
+      <version>1.0</version>
+      <description>I2C 1</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x40004900</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C1</name>
+        <description>I2C1 Interrupt</description>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="I2Cn">
+      <name>I2C2</name>
+      <version>1.0</version>
+      <description>I2C 2</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x40004a00</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C2</name>
+        <description>I2C2 Interrupt</description>
+        <value>25</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>LCD</name>
+      <version>1.0</version>
+      <description>LCD Driver</description>
+      <groupName>LCD Driver</groupName>
+      <baseAddress>0x40005000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>LCD Driver Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>IRSEL</name>
+              <description>Internal LCD Bias Dividing Resistor Selection</description>
+              <bitRange>[07:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RLCD3</name>
+                  <description>RLCD3: 105/105/80[kohm] @(1/2)/(1/3)/(1/4) bias</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RLCD1</name>
+                  <description>RLCD1: 10/10/10[kohm] @(1/2)/(1/3)/(1/4) bias</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RLCD2</name>
+                  <description>RLCD2: 66/66/50[kohm] @(1/2)/(1/3)/(1/4) bias</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RLCD4</name>
+                  <description>RLCD4: 320/320/240[kohm] @(1/2)/(1/3)/(1/4) bias</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DBS</name>
+              <description>LCD Duty and Bias Selection</description>
+              <bitRange>[05:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Duty8Bias4</name>
+                  <description>1/8 duty, 1/4 bias</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Duty6Bias4</name>
+                  <description>1/6 duty, 1/4 bias</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Duty5Bias3</name>
+                  <description>1/5 duty, 1/3 bias</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Duty4Bias3</name>
+                  <description>1/4 duty, 1/3 bias</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Duty3Bias3</name>
+                  <description>1/3 duty, 1/3 bias</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Duty3Bias2</name>
+                  <description>1/3 duty, 1/2 bias</description>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LCLK</name>
+              <description>LCD Clock Selection (When fLCD = 32.768kHz)</description>
+              <bitRange>[02:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>fLCD256</name>
+                  <description>128Hz</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fLCD128</name>
+                  <description>256Hz</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fLCD64</name>
+                  <description>512Hz</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fLCD32</name>
+                  <description>1024Hz</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DISP</name>
+              <description>LCD Display Control</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Off</name>
+                  <description>Display off</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>On</name>
+                  <description>Normal display on</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BCCR</name>
+          <description>LCD Automatic Bias and Contrast Control Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>LCDABC</name>
+              <description>LCD Automatic Bias Control</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Off</name>
+                  <description>LCD automatic bias is off</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>On</name>
+                  <description>LCD automatic bias is on</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BMSEL</name>
+              <description>'Bias Mode A' Time Selection</description>
+              <bitRange>[10:08]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>BMA1Clk</name>
+                  <description>'Bias Mode A' for 1-clock of fLCD</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BMA2Clk</name>
+                  <description>'Bias Mode A' for 2-clock of fLCD</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BMA3Clk</name>
+                  <description>'Bias Mode A' for 3-clock of fLCD</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BMA4Clk</name>
+                  <description>'Bias Mode A' for 4-clock of fLCD</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BMA5Clk</name>
+                  <description>'Bias Mode A' for 5-clock of fLCD</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BMA6Clk</name>
+                  <description>'Bias Mode A' for 6-clock of fLCD</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BMA7Clk</name>
+                  <description>'Bias Mode A' for 7-clock of fLCD</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BMA8Clk</name>
+                  <description>'Bias Mode A' for 8-clock of fLCD</description>
+                  <value>7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LCTEN</name>
+              <description>LCD Driver Contrast Control</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable LCD driver contrast.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable LCD driver contrast.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>VLCD</name>
+              <description>VLC0 Voltage Control when the contrast is enabled</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Step0</name>
+                  <description>VDD x 16/31 Step</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step1</name>
+                  <description>VDD x 16/30 Step</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step2</name>
+                  <description>VDD x 16/29 Step</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step3</name>
+                  <description>VDD x 16/28 Step</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step4</name>
+                  <description>VDD x 16/27 Step</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step5</name>
+                  <description>VDD x 16/26 Step</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step6</name>
+                  <description>VDD x 16/25 Step</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step7</name>
+                  <description>VDD x 16/24 Step</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step8</name>
+                  <description>VDD x 16/23 Step</description>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step9</name>
+                  <description>VDD x 16/22 Step</description>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step10</name>
+                  <description>VDD x 16/21 Step</description>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step11</name>
+                  <description>VDD x 16/20 Step</description>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step12</name>
+                  <description>VDD x 16/19 Step</description>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step13</name>
+                  <description>VDD x 16/18 Step</description>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step14</name>
+                  <description>VDD x 16/17 Step</description>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Step15</name>
+                  <description>VDD x 16/16 Step</description>
+                  <value>15</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DR0</name>
+          <description>LCD Display Data Register 0</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR1</name>
+          <description>LCD Display Data Register 1</description>
+          <addressOffset>0x11</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR2</name>
+          <description>LCD Display Data Register 2</description>
+          <addressOffset>0x12</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR3</name>
+          <description>LCD Display Data Register 3</description>
+          <addressOffset>0x13</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR4</name>
+          <description>LCD Display Data Register 4</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR5</name>
+          <description>LCD Display Data Register 5</description>
+          <addressOffset>0x15</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR6</name>
+          <description>LCD Display Data Register 6</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR7</name>
+          <description>LCD Display Data Register 7</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR8</name>
+          <description>LCD Display Data Register 8</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR9</name>
+          <description>LCD Display Data Register 9</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR10</name>
+          <description>LCD Display Data Register 10</description>
+          <addressOffset>0x1a</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR11</name>
+          <description>LCD Display Data Register 11</description>
+          <addressOffset>0x1b</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR12</name>
+          <description>LCD Display Data Register 12</description>
+          <addressOffset>0x1c</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR13</name>
+          <description>LCD Display Data Register 13</description>
+          <addressOffset>0x1d</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR14</name>
+          <description>LCD Display Data Register 14</description>
+          <addressOffset>0x1e</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR15</name>
+          <description>LCD Display Data Register 15</description>
+          <addressOffset>0x1f</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR16</name>
+          <description>LCD Display Data Register 16</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR17</name>
+          <description>LCD Display Data Register 17</description>
+          <addressOffset>0x21</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR18</name>
+          <description>LCD Display Data Register 18</description>
+          <addressOffset>0x22</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR19</name>
+          <description>LCD Display Data Register 19</description>
+          <addressOffset>0x23</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR20</name>
+          <description>LCD Display Data Register 20</description>
+          <addressOffset>0x24</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR21</name>
+          <description>LCD Display Data Register 21</description>
+          <addressOffset>0x25</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR22</name>
+          <description>LCD Display Data Register 22</description>
+          <addressOffset>0x26</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR23</name>
+          <description>LCD Display Data Register 23</description>
+          <addressOffset>0x27</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR24</name>
+          <description>LCD Display Data Register 24</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR25</name>
+          <description>LCD Display Data Register 25</description>
+          <addressOffset>0x29</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR26</name>
+          <description>LCD Display Data Register 26</description>
+          <addressOffset>0x2a</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR27</name>
+          <description>LCD Display Data Register 27</description>
+          <addressOffset>0x2b</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR28</name>
+          <description>LCD Display Data Register 28</description>
+          <addressOffset>0x2c</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR29</name>
+          <description>LCD Display Data Register 29</description>
+          <addressOffset>0x2d</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR30</name>
+          <description>LCD Display Data Register 30</description>
+          <addressOffset>0x2e</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR31</name>
+          <description>LCD Display Data Register 31</description>
+          <addressOffset>0x2f</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR32</name>
+          <description>LCD Display Data Register 32</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR33</name>
+          <description>LCD Display Data Register 33</description>
+          <addressOffset>0x31</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR34</name>
+          <description>LCD Display Data Register 34</description>
+          <addressOffset>0x32</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR35</name>
+          <description>LCD Display Data Register 35</description>
+          <addressOffset>0x33</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR36</name>
+          <description>LCD Display Data Register 36</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR37</name>
+          <description>LCD Display Data Register 37</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR38</name>
+          <description>LCD Display Data Register 38</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR39</name>
+          <description>LCD Display Data Register 39</description>
+          <addressOffset>0x37</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR40</name>
+          <description>LCD Display Data Register 40</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR41</name>
+          <description>LCD Display Data Register 41</description>
+          <addressOffset>0x39</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR42</name>
+          <description>LCD Display Data Register 42</description>
+          <addressOffset>0x3a</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>DR43</name>
+          <description>LCD Display Data Register 43</description>
+          <addressOffset>0x3b</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetMask>0x0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>CRC</name>
+      <version>1.0</version>
+      <description>Cyclic Redundancy Check and Checksum</description>
+      <groupName>CRC &amp; Checksum</groupName>
+      <baseAddress>0x30001000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CR</name>
+          <description>CRC/Checksum Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>MODS</name>
+              <description>User/Auto Mode Selection</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>UserMode</name>
+                  <description>User Mode (Calculate every data written to the CRC_IN register)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AutoMode</name>
+                  <description>Auto Mode (Calculate till CRC_SADR == CRC_EADR)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RLTCLR</name>
+              <description>CRC/Checksum Result Data Register (CRCRLT) Initialization</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NoEffect</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Init</name>
+                  <description>Initialize the CRC_RLT register with the value of CRC_INIT. (This bit is automatically cleared to '0' after operation.)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MDSEL</name>
+              <description>CRC/Checksum Selection</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CRC</name>
+                  <description>Select CRC.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Checksum</name>
+                  <description>Select Checksum.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>POLYS</name>
+              <description>Polynomial Selection (CRC only)</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CRC16_CCITT</name>
+                  <description>CRC16-CCITT (G1(x) = x16 + x12 + x5 + 1)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC16 (G2(x) = x16 + x15 + x2 + 1)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SARINC</name>
+              <description>CRC/Checksum Start Address Auto Increment Control (User mode only)</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>No effect.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>The CRC/Checksum start address register is incremented as the selected input size every writing to the CRC_IN register.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FIRSTBS</name>
+              <description>First Shifted-in Selection (CRC only)</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>msbFirst</name>
+                  <description>msb first</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>lsbFirst</name>
+                  <description>lsb first</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCRUN</name>
+              <description>CRC/Checksum Start Control and Busy</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Stop</name>
+                  <description>Not busy. The CRC operation can be finished by writing '0' to this bit while running.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Start</name>
+                  <description>Start CRC operation. This bit is automatically cleared to '0' when the value of CRC_SADR register reaches the value of CRC_EADR register.</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <description>CRC/Checksum Input Data Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>INDATA</name>
+              <description>CRC Input Data</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RLT</name>
+          <description>CRC/Checksum Result Data Register</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0xffff</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>RLTDATA</name>
+              <description>CRC Result Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INIT</name>
+          <description>CRC/Checksum Initial Data Register</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x0</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>INIDATA</name>
+              <description>CRC Initial Data</description>
+              <bitRange>[15:00]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SADR</name>
+          <description>CRC/Checksum Start Address Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x10000000</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>SADR</name>
+              <description>CRC Start Address</description>
+              <bitRange>[31:02]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EADR</name>
+          <description>CRC/Checksum End Address Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x1000fffc</resetValue>
+          <resetMask>0xffffffff</resetMask>
+          <fields>
+            <field>
+              <name>EADR</name>
+              <description>CRC End Address</description>
+              <bitRange>[31:02]</bitRange>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>COA0</name>
+      <version>1.0</version>
+      <description>Configuration Option Area Page 0: System Related Trimming Value</description>
+      <groupName>Configuration Option Area</groupName>
+      <baseAddress>0x1ffff000</baseAddress>
+      <size>32</size>
+      <access>read-only</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>TRIM00</name>
+          <description>System Related Trim Value 00</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0xffffffff</resetValue>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM01</name>
+          <description>System Related Trim Value 01</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM02</name>
+          <description>System Related Trim Value 02</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM03</name>
+          <description>System Related Trim Value 03</description>
+          <addressOffset>0x00c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM04</name>
+          <description>System Related Trim Value 04</description>
+          <addressOffset>0x010</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM05</name>
+          <description>System Related Trim Value 05</description>
+          <addressOffset>0x014</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM06</name>
+          <description>System Related Trim Value 06</description>
+          <addressOffset>0x018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM07</name>
+          <description>System Related Trim Value 07</description>
+          <addressOffset>0x01c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM08</name>
+          <description>System Related Trim Value 08</description>
+          <addressOffset>0x020</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM09</name>
+          <description>System Related Trim Value 09</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM10</name>
+          <description>System Related Trim Value 10</description>
+          <addressOffset>0x028</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM11</name>
+          <description>System Related Trim Value 11</description>
+          <addressOffset>0x02c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM12</name>
+          <description>System Related Trim Value 12</description>
+          <addressOffset>0x030</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM13</name>
+          <description>System Related Trim Value 13</description>
+          <addressOffset>0x034</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM14</name>
+          <description>System Related Trim Value 14</description>
+          <addressOffset>0x038</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM15</name>
+          <description>System Related Trim Value 15</description>
+          <addressOffset>0x03c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM16</name>
+          <description>System Related Trim Value 16</description>
+          <addressOffset>0x040</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM17</name>
+          <description>System Related Trim Value 17</description>
+          <addressOffset>0x044</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM18</name>
+          <description>System Related Trim Value 18</description>
+          <addressOffset>0x048</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM19</name>
+          <description>System Related Trim Value 19</description>
+          <addressOffset>0x04c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>CONF_MF1CNFIG</name>
+          <description>Manufacture Information 1</description>
+          <addressOffset>0x050</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+          <fields>
+            <field>
+              <name>XYCDN</name>
+              <description>X and Y Coordinates</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_MF2CNFIG</name>
+          <description>Manufacture Information 2</description>
+          <addressOffset>0x054</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+          <fields>
+            <field>
+              <name>LOTNO</name>
+              <description>Lot Number [23:0]</description>
+              <bitRange>[31:08]</bitRange>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAFNO</name>
+              <description>Wafer Number</description>
+              <bitRange>[07:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_MF3CNFIG</name>
+          <description>Manufacture Information 3</description>
+          <addressOffset>0x058</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+          <fields>
+            <field>
+              <name>LOTNO</name>
+              <description>Lot Number [55:24]</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_MF4CNFIG</name>
+          <description>Manufacture Information 4</description>
+          <addressOffset>0x05c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+          <fields>
+            <field>
+              <name>LOTNO</name>
+              <description>Lot Number [87:56]</description>
+              <bitRange>[31:00]</bitRange>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIM24</name>
+          <description>System Related Trim Value 24</description>
+          <addressOffset>0x060</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM25</name>
+          <description>System Related Trim Value 25</description>
+          <addressOffset>0x064</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM26</name>
+          <description>System Related Trim Value 26</description>
+          <addressOffset>0x068</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM27</name>
+          <description>System Related Trim Value 27</description>
+          <addressOffset>0x06c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM28</name>
+          <description>System Related Trim Value 28</description>
+          <addressOffset>0x070</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM29</name>
+          <description>System Related Trim Value 29</description>
+          <addressOffset>0x074</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM30</name>
+          <description>System Related Trim Value 30</description>
+          <addressOffset>0x078</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>TRIM31</name>
+          <description>System Related Trim Value 31</description>
+          <addressOffset>0x07c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>COA1</name>
+      <version>1.0</version>
+      <description>Configuration Option Area Page 1: User Option</description>
+      <groupName>Configuration Option Area</groupName>
+      <baseAddress>0x1ffff200</baseAddress>
+      <size>32</size>
+      <access>read-only</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>RPCNFIG</name>
+          <description>Configuration for Read Protection</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0xffffffff</resetValue>
+          <resetMask>0xfffffffc</resetMask>
+          <fields>
+            <field>
+              <name>WTIDKY</name>
+              <description>Write Identification Key (0x69c8a27)</description>
+              <bitRange>[31:04]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Value</name>
+                  <description>Key Value (0x69c8a27)</description>
+                  <value>0x69c8a27</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READP</name>
+              <description>Read Protection for Flash Memory Area</description>
+              <bitRange>[01:00]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Level0</name>
+                  <description>No restriction for read/erase/write.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level1</name>
+                  <description>
+                    1. Not readable/erasable/writable by 'Debug'
+                    2. Bulk erasable only by 'Debug'
+                    3. Readable/erasable/writable by 'Instruction from Flash Memory and RAM'
+                  </description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Level2</name>
+                  <description>
+                    1. Not readable/erasable/writable by 'Debug' / 'Instruction from RAM'
+                    2. Bulk erasable only by 'Instruction from RAM' / 'Debug'
+                    3. Readable/erasable/writable by 'Instruction from Flash Memory'
+                  </description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCNFIG</name>
+          <description>Configuration for Watch-Dog Timer</description>
+          <addressOffset>0x0c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0xffffffff</resetValue>
+          <resetMask>0xffff0008</resetMask>
+          <fields>
+            <field>
+              <name>WRCMF</name>
+              <description>Watch-Dog Timer RC Oscillator Master Configuration</description>
+              <bitRange>[15:04]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>BySW</name>
+                  <description>By S/W (CLKSRCR Register) (0x96d)</description>
+                  <value>0x96d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AlwaysEnableExceptDeepSleep</name>
+                  <description>Always Enable Except for Deep Sleep (0x2a7)</description>
+                  <value>0x2a7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AlwaysEnable</name>
+                  <description>Always Enable</description>
+                  <value>0xfff</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WCLKMF</name>
+              <description>Watch-Dog Timer Clock Selection Master Configuration</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>BySW</name>
+                  <description>By S/W (PPCLKSR Register)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AlwaysWDTRC</name>
+                  <description>Always WDTRC</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WRSTMF</name>
+              <description>Watch-Dog Timer Reset Enable Master Configuration</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AlwaysEnable</name>
+                  <description>Always Enable</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BySW</name>
+                  <description>By S/W (WDTCR Register)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WCNTMF</name>
+              <description>Watch-Dog Timer Counter Enable Master Configuration</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>AlwaysEnable</name>
+                  <description>Always Enable</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BySW</name>
+                  <description>By S/W (WDTCR Register)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LVRCNFIG</name>
+          <description>Configuration for Low Voltage Reset</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0xffffffff</resetValue>
+          <resetMask>0xffff00f0</resetMask>
+          <fields>
+            <field>
+              <name>LVRENM</name>
+              <description>LVR Reset Operation Control Master Configuration</description>
+              <bitRange>[15:08]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>BySW</name>
+                  <description>By S/W (LVRCR Register) (0xaa)</description>
+                  <value>0xaa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AlwaysEnable</name>
+                  <description>Always Enable (0xff)</description>
+                  <value>0xff</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LVRVS</name>
+              <description>LVR Voltage Selection</description>
+              <bitRange>[03:00]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>1p62V</name>
+                  <description>1.62V</description>
+                  <value>15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNW14</name>
+                  <description>Do not write.</description>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNW13</name>
+                  <description>Do not write.</description>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNW12</name>
+                  <description>Do not write.</description>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p00V</name>
+                  <description>2.00V</description>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p13V</name>
+                  <description>2.13V</description>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p28V</name>
+                  <description>2.28V</description>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p46V</name>
+                  <description>2.46V</description>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2p67V</name>
+                  <description>2.67V</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p04V</name>
+                  <description>3.04V</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p20V</name>
+                  <description>3.20V</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p55V</name>
+                  <description>3.55V</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p75V</name>
+                  <description>3.75V</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3p99V</name>
+                  <description>3.99V</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4p25V</name>
+                  <description>4.25V</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4p55</name>
+                  <description>4.55V</description>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNFIGWTP1</name>
+          <description>Erase/Write Protection for Configure Option Page 1/2/3</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0xffffffff</resetValue>
+          <resetMask>0xfffffff8</resetMask>
+          <fields>
+            <field>
+              <name>CP3WP</name>
+              <description>Configure Option Page 3 Erase/Write Protection</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable protection. (Not erasable/writable by instruction)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable protection. (Erasable/writable by instruction)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CP2WP</name>
+              <description>Configure Option Page 2 Erase/Write Protection</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable protection. (Not erasable/writable by instruction)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable protection. (Erasable/writable by instruction)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CP1WP</name>
+              <description>Configure Option Page 1 Erase/Write Protection</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Enable protection. (Not erasable/writable by instruction)</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Disable protection. (Erasable/writable by instruction)</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FMWTP1</name>
+          <description>Erase/Write Protection for Flash Memory</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+          <fields>
+            <field>
+              <name>SWTP31</name>
+              <description>Flash Memory Erase/Write Protection 31</description>
+              <bitRange>[31:31]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP30</name>
+              <description>Flash Memory Erase/Write Protection 30</description>
+              <bitRange>[30:30]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP29</name>
+              <description>Flash Memory Erase/Write Protection 29</description>
+              <bitRange>[29:29]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP28</name>
+              <description>Flash Memory Erase/Write Protection 28</description>
+              <bitRange>[28:28]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP27</name>
+              <description>Flash Memory Erase/Write Protection 27</description>
+              <bitRange>[27:27]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP26</name>
+              <description>Flash Memory Erase/Write Protection 26</description>
+              <bitRange>[26:26]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP25</name>
+              <description>Flash Memory Erase/Write Protection 25</description>
+              <bitRange>[25:25]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP24</name>
+              <description>Flash Memory Erase/Write Protection 24</description>
+              <bitRange>[24:24]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP23</name>
+              <description>Flash Memory Erase/Write Protection 23</description>
+              <bitRange>[23:23]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP22</name>
+              <description>Flash Memory Erase/Write Protection 22</description>
+              <bitRange>[22:22]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP21</name>
+              <description>Flash Memory Erase/Write Protection 21</description>
+              <bitRange>[21:21]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP20</name>
+              <description>Flash Memory Erase/Write Protection 20</description>
+              <bitRange>[20:20]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP19</name>
+              <description>Flash Memory Erase/Write Protection 19</description>
+              <bitRange>[19:19]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP18</name>
+              <description>Flash Memory Erase/Write Protection 18</description>
+              <bitRange>[18:18]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP17</name>
+              <description>Flash Memory Erase/Write Protection 17</description>
+              <bitRange>[17:17]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP16</name>
+              <description>Flash Memory Erase/Write Protection 16</description>
+              <bitRange>[16:16]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP15</name>
+              <description>Flash Memory Erase/Write Protection 15</description>
+              <bitRange>[15:15]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP14</name>
+              <description>Flash Memory Erase/Write Protection 14</description>
+              <bitRange>[14:14]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP13</name>
+              <description>Flash Memory Erase/Write Protection 13</description>
+              <bitRange>[13:13]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP12</name>
+              <description>Flash Memory Erase/Write Protection 12</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP11</name>
+              <description>Flash Memory Erase/Write Protection 11</description>
+              <bitRange>[11:11]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP10</name>
+              <description>Flash Memory Erase/Write Protection 10</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP9</name>
+              <description>Flash Memory Erase/Write Protection 9</description>
+              <bitRange>[09:09]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP8</name>
+              <description>Flash Memory Erase/Write Protection 8</description>
+              <bitRange>[08:08]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP7</name>
+              <description>Flash Memory Erase/Write Protection 7</description>
+              <bitRange>[07:07]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP6</name>
+              <description>Flash Memory Erase/Write Protection 6</description>
+              <bitRange>[06:06]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP5</name>
+              <description>Flash Memory Erase/Write Protection 5</description>
+              <bitRange>[05:05]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP4</name>
+              <description>Flash Memory Erase/Write Protection 4</description>
+              <bitRange>[04:04]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP3</name>
+              <description>Flash Memory Erase/Write Protection 3</description>
+              <bitRange>[03:03]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP2</name>
+              <description>Flash Memory Erase/Write Protection 2</description>
+              <bitRange>[02:02]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP1</name>
+              <description>Flash Memory Erase/Write Protection 1</description>
+              <bitRange>[01:01]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWTP0</name>
+              <description>Flash Memory Erase/Write Protection 0</description>
+              <bitRange>[00:00]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Protect 'flash memory sector n erase/write'</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Permit 'flash memory sector n erase/write'</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
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+      <name>COA2</name>
+      <version>1.0</version>
+      <description>Configuration Option Area Page 2: User Data Area 0</description>
+      <groupName>Configuration Option Area</groupName>
+      <baseAddress>0x1ffff400</baseAddress>
+      <size>32</size>
+      <access>read-only</access>
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+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
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+      <registers>
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+          <name>UDATA00</name>
+          <description>User Data 00</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
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+          <description>User Data 01</description>
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+          <size>32</size>
+          <access>read-only</access>
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+          <description>User Data 02</description>
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+          <access>read-only</access>
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+        </register>
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+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA25</name>
+          <description>User Data 25</description>
+          <addressOffset>0x064</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA26</name>
+          <description>User Data 26</description>
+          <addressOffset>0x068</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA27</name>
+          <description>User Data 27</description>
+          <addressOffset>0x06c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA28</name>
+          <description>User Data 28</description>
+          <addressOffset>0x070</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA29</name>
+          <description>User Data 29</description>
+          <addressOffset>0x074</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA30</name>
+          <description>User Data 30</description>
+          <addressOffset>0x078</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA31</name>
+          <description>User Data 31</description>
+          <addressOffset>0x07c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>COA3</name>
+      <version>1.0</version>
+      <description>Configuration Option Area Page 3: User Data Area 1</description>
+      <groupName>Configuration Option Area</groupName>
+      <baseAddress>0x1ffff600</baseAddress>
+      <size>32</size>
+      <access>read-only</access>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>UDATA00</name>
+          <description>User Data 00</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA01</name>
+          <description>User Data 01</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA02</name>
+          <description>User Data 02</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA03</name>
+          <description>User Data 03</description>
+          <addressOffset>0x00c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA04</name>
+          <description>User Data 04</description>
+          <addressOffset>0x010</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA05</name>
+          <description>User Data 05</description>
+          <addressOffset>0x014</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA06</name>
+          <description>User Data 06</description>
+          <addressOffset>0x018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA07</name>
+          <description>User Data 07</description>
+          <addressOffset>0x01c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA08</name>
+          <description>User Data 08</description>
+          <addressOffset>0x020</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA09</name>
+          <description>User Data 09</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA10</name>
+          <description>User Data 10</description>
+          <addressOffset>0x028</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA11</name>
+          <description>User Data 11</description>
+          <addressOffset>0x02c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA12</name>
+          <description>User Data 12</description>
+          <addressOffset>0x030</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA13</name>
+          <description>User Data 13</description>
+          <addressOffset>0x034</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA14</name>
+          <description>User Data 14</description>
+          <addressOffset>0x038</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA15</name>
+          <description>User Data 15</description>
+          <addressOffset>0x03c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA16</name>
+          <description>User Data 16</description>
+          <addressOffset>0x040</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA17</name>
+          <description>User Data 17</description>
+          <addressOffset>0x044</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA18</name>
+          <description>User Data 18</description>
+          <addressOffset>0x048</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA19</name>
+          <description>User Data 19</description>
+          <addressOffset>0x04c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA20</name>
+          <description>User Data 20</description>
+          <addressOffset>0x050</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA21</name>
+          <description>User Data 21</description>
+          <addressOffset>0x054</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA22</name>
+          <description>User Data 22</description>
+          <addressOffset>0x058</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA23</name>
+          <description>User Data 23</description>
+          <addressOffset>0x05c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA24</name>
+          <description>User Data 24</description>
+          <addressOffset>0x060</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA25</name>
+          <description>User Data 25</description>
+          <addressOffset>0x064</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA26</name>
+          <description>User Data 26</description>
+          <addressOffset>0x068</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA27</name>
+          <description>User Data 27</description>
+          <addressOffset>0x06c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA28</name>
+          <description>User Data 28</description>
+          <addressOffset>0x070</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA29</name>
+          <description>User Data 29</description>
+          <addressOffset>0x074</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA30</name>
+          <description>User Data 30</description>
+          <addressOffset>0x078</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+        <register>
+          <name>UDATA31</name>
+          <description>User Data 31</description>
+          <addressOffset>0x07c</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetMask>0x0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
\ No newline at end of file
diff --git a/Project/SDK_V2_5_0/Device/Startup/A31G12x.h b/Project/SDK_V2_5_0/Device/Startup/A31G12x.h
new file mode 100644
index 0000000..36ecdad
--- /dev/null
+++ b/Project/SDK_V2_5_0/Device/Startup/A31G12x.h
@@ -0,0 +1,23794 @@
+/*
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontroller, but can be equally used for other
+ * suitable processor architectures. This file can be freely distributed.
+ * Modifications to this file shall be clearly marked.
+ * 
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * @file     A31G12x.h
+ * @brief    CMSIS HeaderFile
+ * @version  1.0
+ * @date     23. July 2020
+ * @note     Generated by SVDConv V3.3.18 on Thursday, 23.07.2020 15:12:46
+ *           from File 'A31G12x.svd',
+ *           last modified on Thursday, 23.07.2020 05:38:08
+ */
+
+
+
+/** @addtogroup VENDOR ABOV Semiconductor Co., Ltd.
+  * @{
+  */
+
+
+/** @addtogroup A31G12x
+  * @{
+  */
+
+
+#ifndef A31G12X_H
+#define A31G12X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+typedef enum {
+/* =======================================  ARM Cortex-M0+ Specific Interrupt Numbers  ======================================= */
+  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
+  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
+  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
+  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
+  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
+  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
+/* ==========================================  A31G12x Specific Interrupt Numbers  =========================================== */
+  LVI_IRQn                  =   0,              /*!< 0  LVI Interrupt                                                          */
+  WUT_IRQn                  =   1,              /*!< 1  WUT Interrupt                                                          */
+  WDT_IRQn                  =   2,              /*!< 2  WDT Interrupt                                                          */
+  EINT0_IRQn                =   3,              /*!< 3  EINT0 Interrupt                                                        */
+  EINT1_IRQn                =   4,              /*!< 4  EINT1 Interrupt                                                        */
+  EINT2_IRQn                =   5,              /*!< 5  EINT2 Interrupt                                                        */
+  EINT3_IRQn                =   6,              /*!< 6  EINT3 Interrupt                                                        */
+  TIMER10_IRQn              =   7,              /*!< 7  TIMER10 Interrupt                                                      */
+  TIMER11_IRQn              =   8,              /*!< 8  TIMER11 Interrupt                                                      */
+  TIMER12_IRQn              =   9,              /*!< 9  TIMER12 Interrupt                                                      */
+  I2C0_IRQn                 =  10,              /*!< 10 I2C0 Interrupt                                                         */
+  USART10_IRQn              =  11,              /*!< 11 USART10 Interrupt                                                      */
+  WT_IRQn                   =  12,              /*!< 12 WT Interrupt                                                           */
+  TIMER30_IRQn              =  13,              /*!< 13 TIMER30 Interrupt                                                      */
+  I2C1_IRQn                 =  14,              /*!< 14 I2C1 Interrupt                                                         */
+  TIMER20_IRQn              =  15,              /*!< 15 TIMER20 Interrupt                                                      */
+  TIMER21_IRQn              =  16,              /*!< 16 TIMER21 Interrupt                                                      */
+  USART11_IRQn              =  17,              /*!< 17 USART11 Interrupt                                                      */
+  ADC_IRQn                  =  18,              /*!< 18 ADC Interrupt                                                          */
+  UART0_IRQn                =  19,              /*!< 19 UART0 Interrupt                                                        */
+  UART1_IRQn                =  20,              /*!< 20 UART1 Interrupt                                                        */
+  TIMER13_IRQn              =  21,              /*!< 21 TIMER13 Interrupt                                                      */
+  TIMER14_IRQn              =  22,              /*!< 22 TIMER14 Interrupt                                                      */
+  TIMER15_IRQn              =  23,              /*!< 23 TIMER15 Interrupt                                                      */
+  TIMER16_IRQn              =  24,              /*!< 24 TIMER16 Interrupt                                                      */
+  I2C2_IRQn                 =  25,              /*!< 25 I2C2 Interrupt                                                         */
+  USART12_IRQn              =  26,              /*!< 26 USART12 Interrupt                                                      */
+  USART13_IRQn              =  27               /*!< 27 USART13 Interrupt                                                      */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================  Configuration of the ARM Cortex-M0+ Processor and Core Peripherals  =========================== */
+#define __CM0PLUS_REV                 0x0001U   /*!< CM0PLUS Core Revision                                                     */
+#define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
+#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
+#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0plus.h"                       /*!< ARM Cortex-M0+ processor and core peripherals                             */
+#include "system_A31G12x.h"                     /*!< A31G12x System                                                            */
+
+#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
+  #define __IM   __I
+#endif
+#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
+  #define __OM   __O
+#endif
+#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
+  #define __IOM  __IO
+#endif
+
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+#if defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+  #pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           INTC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Interrupt Controller (INTC)
+  */
+
+typedef struct {                                /*!< (@ 0x40001000) INTC Structure                                             */
+  __IM  uint32_t  RESERVED;
+  
+  union {
+    __IOM uint32_t PBTRIG;                      /*!< (@ 0x00000004) Port B Interrupt Trigger Selection Register                */
+    
+    struct {
+      __IOM uint32_t ITRIG0     : 1;            /*!< [0..0] Port B Interrupt Trigger Selection 0                               */
+      __IOM uint32_t ITRIG1     : 1;            /*!< [1..1] Port B Interrupt Trigger Selection 1                               */
+      __IOM uint32_t ITRIG2     : 1;            /*!< [2..2] Port B Interrupt Trigger Selection 2                               */
+      __IOM uint32_t ITRIG3     : 1;            /*!< [3..3] Port B Interrupt Trigger Selection 3                               */
+      __IOM uint32_t ITRIG4     : 1;            /*!< [4..4] Port B Interrupt Trigger Selection 4                               */
+      __IOM uint32_t ITRIG5     : 1;            /*!< [5..5] Port B Interrupt Trigger Selection 5                               */
+      __IOM uint32_t ITRIG6     : 1;            /*!< [6..6] Port B Interrupt Trigger Selection 6                               */
+      __IOM uint32_t ITRIG7     : 1;            /*!< [7..7] Port B Interrupt Trigger Selection 7                               */
+      __IOM uint32_t ITRIG8     : 1;            /*!< [8..8] Port B Interrupt Trigger Selection 8                               */
+      __IOM uint32_t ITRIG9     : 1;            /*!< [9..9] Port B Interrupt Trigger Selection 9                               */
+      __IOM uint32_t ITRIG10    : 1;            /*!< [10..10] Port B Interrupt Trigger Selection 10                            */
+      __IOM uint32_t ITRIG11    : 1;            /*!< [11..11] Port B Interrupt Trigger Selection 11                            */
+    } PBTRIG_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PCTRIG;                      /*!< (@ 0x00000008) Port C Interrupt Trigger Selection Register                */
+    
+    struct {
+      __IOM uint32_t ITRIG0     : 1;            /*!< [0..0] Port C Interrupt Trigger Selection 0                               */
+      __IOM uint32_t ITRIG1     : 1;            /*!< [1..1] Port C Interrupt Trigger Selection 1                               */
+      __IOM uint32_t ITRIG2     : 1;            /*!< [2..2] Port C Interrupt Trigger Selection 2                               */
+      __IOM uint32_t ITRIG3     : 1;            /*!< [3..3] Port C Interrupt Trigger Selection 3                               */
+    } PCTRIG_b;
+  } ;
+  __IM  uint32_t  RESERVED1;
+  
+  union {
+    __IOM uint32_t PETRIG;                      /*!< (@ 0x00000010) Port E Interrupt Trigger Selection Register                */
+    
+    struct {
+      __IOM uint32_t ITRIG0     : 1;            /*!< [0..0] Port E Interrupt Trigger Selection 0                               */
+      __IOM uint32_t ITRIG1     : 1;            /*!< [1..1] Port E Interrupt Trigger Selection 1                               */
+      __IOM uint32_t ITRIG2     : 1;            /*!< [2..2] Port E Interrupt Trigger Selection 2                               */
+      __IOM uint32_t ITRIG3     : 1;            /*!< [3..3] Port E Interrupt Trigger Selection 3                               */
+    } PETRIG_b;
+  } ;
+  __IM  uint32_t  RESERVED2[60];
+  
+  union {
+    __IOM uint32_t PBCR;                        /*!< (@ 0x00000104) Port B Interrupt Control Register                          */
+    
+    struct {
+      __IOM uint32_t INTCTL0    : 2;            /*!< [1..0] Port B Interrupt Control 0                                         */
+      __IOM uint32_t INTCTL1    : 2;            /*!< [3..2] Port B Interrupt Control 1                                         */
+      __IOM uint32_t INTCTL2    : 2;            /*!< [5..4] Port B Interrupt Control 2                                         */
+      __IOM uint32_t INTCTL3    : 2;            /*!< [7..6] Port B Interrupt Control 3                                         */
+      __IOM uint32_t INTCTL4    : 2;            /*!< [9..8] Port B Interrupt Control 4                                         */
+      __IOM uint32_t INTCTL5    : 2;            /*!< [11..10] Port B Interrupt Control 5                                       */
+      __IOM uint32_t INTCTL6    : 2;            /*!< [13..12] Port B Interrupt Control 6                                       */
+      __IOM uint32_t INTCTL7    : 2;            /*!< [15..14] Port B Interrupt Control 7                                       */
+      __IOM uint32_t INTCTL8    : 2;            /*!< [17..16] Port B Interrupt Control 8                                       */
+      __IOM uint32_t INTCTL9    : 2;            /*!< [19..18] Port B Interrupt Control 9                                       */
+      __IOM uint32_t INTCTL10   : 2;            /*!< [21..20] Port B Interrupt Control 10                                      */
+      __IOM uint32_t INTCTL11   : 2;            /*!< [23..22] Port B Interrupt Control 11                                      */
+    } PBCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PCCR;                        /*!< (@ 0x00000108) Port C Interrupt Control Register                          */
+    
+    struct {
+      __IOM uint32_t INTCTL0    : 2;            /*!< [1..0] Port C Interrupt Control 0                                         */
+      __IOM uint32_t INTCTL1    : 2;            /*!< [3..2] Port C Interrupt Control 1                                         */
+      __IOM uint32_t INTCTL2    : 2;            /*!< [5..4] Port C Interrupt Control 2                                         */
+      __IOM uint32_t INTCTL3    : 2;            /*!< [7..6] Port C Interrupt Control 3                                         */
+    } PCCR_b;
+  } ;
+  __IM  uint32_t  RESERVED3;
+  
+  union {
+    __IOM uint32_t PECR;                        /*!< (@ 0x00000110) Port E Interrupt Control Register                          */
+    
+    struct {
+      __IOM uint32_t INTCTL0    : 2;            /*!< [1..0] Port E Interrupt Control 0                                         */
+      __IOM uint32_t INTCTL1    : 2;            /*!< [3..2] Port E Interrupt Control 1                                         */
+      __IOM uint32_t INTCTL2    : 2;            /*!< [5..4] Port E Interrupt Control 2                                         */
+      __IOM uint32_t INTCTL3    : 2;            /*!< [7..6] Port E Interrupt Control 3                                         */
+    } PECR_b;
+  } ;
+  __IM  uint32_t  RESERVED4[60];
+  
+  union {
+    __IOM uint32_t PBFLAG;                      /*!< (@ 0x00000204) Port B Interrupt Flag Register                             */
+    
+    struct {
+      __IOM uint32_t FLAG0      : 1;            /*!< [0..0] Port B Interrupt Flag 0                                            */
+      __IOM uint32_t FLAG1      : 1;            /*!< [1..1] Port B Interrupt Flag 1                                            */
+      __IOM uint32_t FLAG2      : 1;            /*!< [2..2] Port B Interrupt Flag 2                                            */
+      __IOM uint32_t FLAG3      : 1;            /*!< [3..3] Port B Interrupt Flag 3                                            */
+      __IOM uint32_t FLAG4      : 1;            /*!< [4..4] Port B Interrupt Flag 4                                            */
+      __IOM uint32_t FLAG5      : 1;            /*!< [5..5] Port B Interrupt Flag 5                                            */
+      __IOM uint32_t FLAG6      : 1;            /*!< [6..6] Port B Interrupt Flag 6                                            */
+      __IOM uint32_t FLAG7      : 1;            /*!< [7..7] Port B Interrupt Flag 7                                            */
+      __IOM uint32_t FLAG8      : 1;            /*!< [8..8] Port B Interrupt Flag 8                                            */
+      __IOM uint32_t FLAG9      : 1;            /*!< [9..9] Port B Interrupt Flag 9                                            */
+      __IOM uint32_t FLAG10     : 1;            /*!< [10..10] Port B Interrupt Flag 10                                         */
+      __IOM uint32_t FLAG11     : 1;            /*!< [11..11] Port B Interrupt Flag 11                                         */
+    } PBFLAG_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PCFLAG;                      /*!< (@ 0x00000208) Port C Interrupt Flag Register                             */
+    
+    struct {
+      __IOM uint32_t FLAG0      : 1;            /*!< [0..0] Port C Interrupt Flag 0                                            */
+      __IOM uint32_t FLAG1      : 1;            /*!< [1..1] Port C Interrupt Flag 1                                            */
+      __IOM uint32_t FLAG2      : 1;            /*!< [2..2] Port C Interrupt Flag 2                                            */
+      __IOM uint32_t FLAG3      : 1;            /*!< [3..3] Port C Interrupt Flag 3                                            */
+    } PCFLAG_b;
+  } ;
+  __IM  uint32_t  RESERVED5;
+  
+  union {
+    __IOM uint32_t PEFLAG;                      /*!< (@ 0x00000210) Port E Interrupt Flag Register                             */
+    
+    struct {
+      __IOM uint32_t FLAG0      : 1;            /*!< [0..0] Port E Interrupt Flag 0                                            */
+      __IOM uint32_t FLAG1      : 1;            /*!< [1..1] Port E Interrupt Flag 1                                            */
+      __IOM uint32_t FLAG2      : 1;            /*!< [2..2] Port E Interrupt Flag 2                                            */
+      __IOM uint32_t FLAG3      : 1;            /*!< [3..3] Port E Interrupt Flag 3                                            */
+    } PEFLAG_b;
+  } ;
+  __IM  uint32_t  RESERVED6[59];
+  
+  union {
+    __IOM uint32_t EINT0CONF1;                  /*!< (@ 0x00000300) External Interrupt 0 Configuration Register 1              */
+    
+    struct {
+      __IOM uint32_t CONF0      : 4;            /*!< [3..0] External Interrupt 0 Configuration 0                               */
+      __IOM uint32_t CONF1      : 4;            /*!< [7..4] External Interrupt 0 Configuration 1                               */
+      __IOM uint32_t CONF2      : 4;            /*!< [11..8] External Interrupt 0 Configuration 2                              */
+      __IOM uint32_t CONF3      : 4;            /*!< [15..12] External Interrupt 0 Configuration 3                             */
+      __IOM uint32_t CONF4      : 4;            /*!< [19..16] External Interrupt 0 Configuration 4                             */
+      __IOM uint32_t CONF5      : 4;            /*!< [23..20] External Interrupt 0 Configuration 5                             */
+      __IOM uint32_t CONF6      : 4;            /*!< [27..24] External Interrupt 0 Configuration 6                             */
+      __IOM uint32_t CONF7      : 4;            /*!< [31..28] External Interrupt 0 Configuration 7                             */
+    } EINT0CONF1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t EINT1CONF1;                  /*!< (@ 0x00000304) External Interrupt 1 Configuration Register 1              */
+    
+    struct {
+      __IOM uint32_t CONF0      : 4;            /*!< [3..0] External Interrupt 1 Configuration 0                               */
+      __IOM uint32_t CONF1      : 4;            /*!< [7..4] External Interrupt 1 Configuration 1                               */
+      __IOM uint32_t CONF2      : 4;            /*!< [11..8] External Interrupt 1 Configuration 2                              */
+      __IOM uint32_t CONF3      : 4;            /*!< [15..12] External Interrupt 1 Configuration 3                             */
+      __IOM uint32_t CONF4      : 4;            /*!< [19..16] External Interrupt 1 Configuration 4                             */
+      __IOM uint32_t CONF5      : 4;            /*!< [23..20] External Interrupt 1 Configuration 5                             */
+      __IOM uint32_t CONF6      : 4;            /*!< [27..24] External Interrupt 1 Configuration 6                             */
+      __IOM uint32_t CONF7      : 4;            /*!< [31..28] External Interrupt 1 Configuration 7                             */
+    } EINT1CONF1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t EINT2CONF1;                  /*!< (@ 0x00000308) External Interrupt 2 Configuration Register 1              */
+    
+    struct {
+      __IOM uint32_t CONF0      : 4;            /*!< [3..0] External Interrupt 2 Configuration 0                               */
+      __IOM uint32_t CONF1      : 4;            /*!< [7..4] External Interrupt 2 Configuration 1                               */
+      __IOM uint32_t CONF2      : 4;            /*!< [11..8] External Interrupt 2 Configuration 2                              */
+      __IOM uint32_t CONF3      : 4;            /*!< [15..12] External Interrupt 2 Configuration 3                             */
+      __IOM uint32_t CONF4      : 4;            /*!< [19..16] External Interrupt 2 Configuration 4                             */
+      __IOM uint32_t CONF5      : 4;            /*!< [23..20] External Interrupt 2 Configuration 5                             */
+      __IOM uint32_t CONF6      : 4;            /*!< [27..24] External Interrupt 2 Configuration 6                             */
+      __IOM uint32_t CONF7      : 4;            /*!< [31..28] External Interrupt 2 Configuration 7                             */
+    } EINT2CONF1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t EINT3CONF1;                  /*!< (@ 0x0000030C) External Interrupt 3 Configuration Register 1              */
+    
+    struct {
+      __IOM uint32_t CONF0      : 4;            /*!< [3..0] External Interrupt 3 Configuration 0                               */
+      __IOM uint32_t CONF1      : 4;            /*!< [7..4] External Interrupt 3 Configuration 1                               */
+      __IOM uint32_t CONF2      : 4;            /*!< [11..8] External Interrupt 3 Configuration 2                              */
+      __IOM uint32_t CONF3      : 4;            /*!< [15..12] External Interrupt 3 Configuration 3                             */
+      __IOM uint32_t CONF4      : 4;            /*!< [19..16] External Interrupt 3 Configuration 4                             */
+      __IOM uint32_t CONF5      : 4;            /*!< [23..20] External Interrupt 3 Configuration 5                             */
+      __IOM uint32_t CONF6      : 4;            /*!< [27..24] External Interrupt 3 Configuration 6                             */
+      __IOM uint32_t CONF7      : 4;            /*!< [31..28] External Interrupt 3 Configuration 7                             */
+    } EINT3CONF1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t EINT0CONF2;                  /*!< (@ 0x00000310) External Interrupt 0 Configuration Register 2              */
+    
+    struct {
+      __IOM uint32_t CONF8      : 4;            /*!< [3..0] External Interrupt 0 Configuration 8                               */
+      __IOM uint32_t CONF9      : 4;            /*!< [7..4] External Interrupt 0 Configuration 9                               */
+      __IOM uint32_t CONF10     : 4;            /*!< [11..8] External Interrupt 0 Configuration 10                             */
+      __IOM uint32_t CONF11     : 4;            /*!< [15..12] External Interrupt 0 Configuration 11                            */
+    } EINT0CONF2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t EINT1CONF2;                  /*!< (@ 0x00000314) External Interrupt 1 Configuration Register 2              */
+    
+    struct {
+      __IOM uint32_t CONF8      : 4;            /*!< [3..0] External Interrupt 1 Configuration 8                               */
+      __IOM uint32_t CONF9      : 4;            /*!< [7..4] External Interrupt 1 Configuration 9                               */
+      __IOM uint32_t CONF10     : 4;            /*!< [11..8] External Interrupt 1 Configuration 10                             */
+      __IOM uint32_t CONF11     : 4;            /*!< [15..12] External Interrupt 1 Configuration 11                            */
+    } EINT1CONF2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t EINT2CONF2;                  /*!< (@ 0x00000318) External Interrupt 2 Configuration Register 2              */
+    
+    struct {
+      __IOM uint32_t CONF8      : 4;            /*!< [3..0] External Interrupt 2 Configuration 8                               */
+      __IOM uint32_t CONF9      : 4;            /*!< [7..4] External Interrupt 2 Configuration 9                               */
+      __IOM uint32_t CONF10     : 4;            /*!< [11..8] External Interrupt 2 Configuration 10                             */
+      __IOM uint32_t CONF11     : 4;            /*!< [15..12] External Interrupt 2 Configuration 11                            */
+    } EINT2CONF2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t EINT3CONF2;                  /*!< (@ 0x0000031C) External Interrupt 3 Configuration Register 2              */
+    
+    struct {
+      __IOM uint32_t CONF8      : 4;            /*!< [3..0] External Interrupt 3 Configuration 8                               */
+      __IOM uint32_t CONF9      : 4;            /*!< [7..4] External Interrupt 3 Configuration 9                               */
+      __IOM uint32_t CONF10     : 4;            /*!< [11..8] External Interrupt 3 Configuration 10                             */
+      __IOM uint32_t CONF11     : 4;            /*!< [15..12] External Interrupt 3 Configuration 11                            */
+    } EINT3CONF2_b;
+  } ;
+  __IM  uint32_t  RESERVED7[56];
+  
+  union {
+    __IOM uint32_t MSK;                         /*!< (@ 0x00000400) Interrupt Source Mask Register                             */
+    
+    struct {
+      __IOM uint32_t IMSK0_LVI  : 1;            /*!< [0..0] Interrupt Source Mask 0 (LVI)                                      */
+      __IOM uint32_t IMSK1_WUT  : 1;            /*!< [1..1] Interrupt Source Mask 1 (WUT)                                      */
+      __IOM uint32_t IMSK2_WDT  : 1;            /*!< [2..2] Interrupt Source Mask 2 (WDT)                                      */
+      __IOM uint32_t IMSK3_EINT0 : 1;           /*!< [3..3] Interrupt Source Mask 3 (EINT0)                                    */
+      __IOM uint32_t IMSK4_EINT1 : 1;           /*!< [4..4] Interrupt Source Mask 4 (EINT1)                                    */
+      __IOM uint32_t IMSK5_EINT2 : 1;           /*!< [5..5] Interrupt Source Mask 5 (EINT2)                                    */
+      __IOM uint32_t IMSK6_EINT3 : 1;           /*!< [6..6] Interrupt Source Mask 6 (EINT3)                                    */
+      __IOM uint32_t IMSK7_TIMER10 : 1;         /*!< [7..7] Interrupt Source Mask 7 (TIMER10)                                  */
+      __IOM uint32_t IMSK8_TIMER11 : 1;         /*!< [8..8] Interrupt Source Mask 8 (TIMER11)                                  */
+      __IOM uint32_t IMSK9_TIMER12 : 1;         /*!< [9..9] Interrupt Source Mask 9 (TIMER12)                                  */
+      __IOM uint32_t IMSK10_I2C0 : 1;           /*!< [10..10] Interrupt Source Mask 10 (I2C0)                                  */
+      __IOM uint32_t IMSK11_USART10 : 1;        /*!< [11..11] Interrupt Source Mask 11 (USART10)                               */
+      __IOM uint32_t IMSK12_WT  : 1;            /*!< [12..12] Interrupt Source Mask 12 (WT)                                    */
+      __IOM uint32_t IMSK13_TIMER30 : 1;        /*!< [13..13] Interrupt Source Mask 13 (TIMER30)                               */
+      __IOM uint32_t IMSK14_I2C1 : 1;           /*!< [14..14] Interrupt Source Mask 14 (I2C1)                                  */
+      __IOM uint32_t IMSK15_TIMER20 : 1;        /*!< [15..15] Interrupt Source Mask 15 (TIMER20)                               */
+      __IOM uint32_t IMSK16_TIMER21 : 1;        /*!< [16..16] Interrupt Source Mask 16 (TIMER21)                               */
+      __IOM uint32_t IMSK17_USART11 : 1;        /*!< [17..17] Interrupt Source Mask 17 (USART11)                               */
+      __IOM uint32_t IMSK18_ADC : 1;            /*!< [18..18] Interrupt Source Mask 18 (ADC)                                   */
+      __IOM uint32_t IMSK19_UART0 : 1;          /*!< [19..19] Interrupt Source Mask 19 (UART0)                                 */
+      __IOM uint32_t IMSK20_UART1 : 1;          /*!< [20..20] Interrupt Source Mask 20 (UART1)                                 */
+      __IOM uint32_t IMSK21_TIMER13 : 1;        /*!< [21..21] Interrupt Source Mask 21 (TIMER13)                               */
+      __IOM uint32_t IMSK22_TIMER14 : 1;        /*!< [22..22] Interrupt Source Mask 22 (TIMER14)                               */
+      __IOM uint32_t IMSK23_TIMER15 : 1;        /*!< [23..23] Interrupt Source Mask 23 (TIMER15)                               */
+      __IOM uint32_t IMSK24_TIMER16 : 1;        /*!< [24..24] Interrupt Source Mask 24 (TIMER16)                               */
+      __IOM uint32_t IMSK25_I2C2 : 1;           /*!< [25..25] Interrupt Source Mask 25 (I2C2)                                  */
+      __IOM uint32_t IMSK26_USART12 : 1;        /*!< [26..26] Interrupt Source Mask 26 (USART12)                               */
+      __IOM uint32_t IMSK27_USART13 : 1;        /*!< [27..27] Interrupt Source Mask 27 (USART13)                               */
+      __IOM uint32_t IMSK28_NULL : 1;           /*!< [28..28] Interrupt Source Mask 28 (RSVD)                                  */
+      __IOM uint32_t IMSK29_NULL : 1;           /*!< [29..29] Interrupt Source Mask 29 (RSVD)                                  */
+      __IOM uint32_t IMSK30_NULL : 1;           /*!< [30..30] Interrupt Source Mask 30 (RSVD)                                  */
+      __IOM uint32_t IMSK31_NULL : 1;           /*!< [31..31] Interrupt Source Mask 31 (RSVD)                                  */
+    } MSK_b;
+  } ;
+} INTC_Type;                                    /*!< Size = 1028 (0x404)                                                       */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCUCC                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief System Control Unit: Chip Configuration (SCUCC)
+  */
+
+typedef struct {                                /*!< (@ 0x4000F000) SCUCC Structure                                            */
+  
+  union {
+    __IM  uint32_t VENDORID;                    /*!< (@ 0x00000000) Vendor Identification Register                             */
+    
+    struct {
+      __IM  uint32_t VENDID     : 32;           /*!< [31..0] Vendor Identification                                             */
+    } VENDORID_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CHIPID;                      /*!< (@ 0x00000004) Chip Identification Register                               */
+    
+    struct {
+      __IM  uint32_t CHIPID     : 32;           /*!< [31..0] Chip Identification                                               */
+    } CHIPID_b;
+  } ;
+  
+  union {
+    __IM  uint32_t REVNR;                       /*!< (@ 0x00000008) Revision Number Register                                   */
+    
+    struct {
+      __IM  uint32_t REVNO      : 8;            /*!< [7..0] Chip Revision Number                                               */
+    } REVNR_b;
+  } ;
+  __IM  uint32_t  RESERVED[2];
+  
+  union {
+    __IOM uint32_t PMREMAP;                     /*!< (@ 0x00000014) Program Memory Remap Register                              */
+    
+    struct {
+      __IOM uint32_t PMREM      : 8;            /*!< [7..0] Program Memory Remap                                               */
+      __OM  uint32_t nPMREM     : 8;            /*!< [15..8] Write Complement Key                                              */
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0xe2f1)                                */
+    } PMREMAP_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BTPSCR;                      /*!< (@ 0x00000018) Boot Pin Status and Control Register                       */
+    
+    struct {
+      __IM  uint32_t BTPSTA     : 1;            /*!< [0..0] BOOT Pin Status                                                    */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t BFIND      : 2;            /*!< [6..5] BOOT Pin Function Indicator                                        */
+    } BTPSCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t RSTSSR;                      /*!< (@ 0x0000001C) Reset Source Status Register                               */
+    
+    struct {
+      __IOM uint32_t PORSTA     : 1;            /*!< [0..0] POR Reset Status                                                   */
+      __IOM uint32_t LVRSTA     : 1;            /*!< [1..1] LVR Reset Status                                                   */
+      __IOM uint32_t WDTSTA     : 1;            /*!< [2..2] Watch-Dog Timer Reset Status                                       */
+      __IOM uint32_t EXTSTA     : 1;            /*!< [3..3] External Pin Reset Status                                          */
+      __IOM uint32_t SWSTA      : 1;            /*!< [4..4] Software Reset Status                                              */
+      __IOM uint32_t MONSTA     : 1;            /*!< [5..5] Clock Monitoring Reset Status                                      */
+    } RSTSSR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t NMISRCR;                     /*!< (@ 0x00000020) NMI Source Selection Register                              */
+    
+    struct {
+      __IOM uint32_t NMISRC     : 5;            /*!< [4..0] Non-Maskable Interrupt Source Selection                            */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t MONINT     : 1;            /*!< [6..6] Clock Monitoring Interrupt Selection                               */
+      __IOM uint32_t NMICON     : 1;            /*!< [7..7] Non-Maskable Interrupt (NMI) Control                               */
+    } NMISRCR_b;
+  } ;
+  
+  union {
+    __OM  uint32_t SWRSTR;                      /*!< (@ 0x00000024) Software Reset Register                                    */
+    
+    struct {
+      __OM  uint32_t SWRST      : 8;            /*!< [7..0] Software Reset (System Reset)                                      */
+      __IM  uint32_t            : 8;
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0x9eb3)                                */
+    } SWRSTR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t SRSTVR;                      /*!< (@ 0x00000028) System Reset Validation Register                           */
+    
+    struct {
+      __IM  uint32_t VALID      : 8;            /*!< [7..0] System Reset Validation                                            */
+    } SRSTVR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t WUTCR;                       /*!< (@ 0x0000002C) Wake-Up Timer Control Register                             */
+    
+    struct {
+      __IOM uint32_t WUTIFLAG   : 1;            /*!< [0..0] Wake-Up Timer Interrupt Flag                                       */
+      __IOM uint32_t CNTRLD     : 1;            /*!< [1..1] Counter Reload                                                     */
+      __IM  uint32_t            : 5;
+      __IOM uint32_t WUTIEN     : 1;            /*!< [7..7] Wake-Up Timer Interrupt Enable                                     */
+    } WUTCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t WUTDR;                       /*!< (@ 0x00000030) Wake-Up Timer Data Register                                */
+    
+    struct {
+      __IOM uint32_t WUTDATA    : 16;           /*!< [15..0] Wake-Up Timer Data                                                */
+    } WUTDR_b;
+  } ;
+  __IM  uint32_t  RESERVED1[29];
+  
+  union {
+    __IOM uint32_t HIRCTRM;                     /*!< (@ 0x000000A8) High Frequency Internal RC Trim Register (HIRCNFIG)        */
+    
+    struct {
+      __IOM uint32_t FTRMH      : 5;            /*!< [4..0] Factory HIRC Fine Trim                                             */
+      __IM  uint32_t CTRMH      : 3;            /*!< [7..5] Factory HIRC Coarse Trim                                           */
+      __OM  uint32_t nTRMH      : 8;            /*!< [15..8] Write Complement Key                                              */
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0xa6b5)                                */
+    } HIRCTRM_b;
+  } ;
+  
+  union {
+    __IOM uint32_t WDTRCTRM;                    /*!< (@ 0x000000AC) Watch-Dog Timer RC Trim Register (WDTRCNFIG)               */
+    
+    struct {
+      __IOM uint32_t FTRMW      : 3;            /*!< [2..0] Factory WDTRC Fine Trim                                            */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t CTRMW      : 4;            /*!< [7..4] Factory WDTRC Coarse Trim                                          */
+      __OM  uint32_t nTRMW      : 8;            /*!< [15..8] Write Complement Key                                              */
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0x4c3d)                                */
+    } WDTRCTRM_b;
+  } ;
+} SCUCC_Type;                                   /*!< Size = 176 (0xb0)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCUCG                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief System Control Unit: Clock Generation (SCUCG)
+  */
+
+typedef struct {                                /*!< (@ 0x40001800) SCUCG Structure                                            */
+  
+  union {
+    __IOM uint32_t SCCR;                        /*!< (@ 0x00000000) System Clock Control Register                              */
+    
+    struct {
+      __IOM uint32_t MCLKSEL    : 2;            /*!< [1..0] Main Clock Selection, MCLK                                         */
+      __IM  uint32_t            : 14;
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0x570a)                                */
+    } SCCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CLKSRCR;                     /*!< (@ 0x00000004) Clock Source Control Register                              */
+    
+    struct {
+      __IOM uint32_t XSOSCEN    : 1;            /*!< [0..0] XSOSC Enable                                                       */
+      __IOM uint32_t XMOSCEN    : 1;            /*!< [1..1] XMOSC Enable                                                       */
+      __IOM uint32_t HIRCEN     : 1;            /*!< [2..2] HIRC Enable                                                        */
+      __IOM uint32_t WDTRCEN    : 1;            /*!< [3..3] WDTRC Enable                                                       */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t XMFRNG     : 1;            /*!< [8..8] Main Oscillator Type and Frequency Range Selection                 */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t HIRCSEL    : 2;            /*!< [13..12] HIRC Frequency Selection                                         */
+      __IM  uint32_t            : 2;
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0xa507)                                */
+    } CLKSRCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCDIVR1;                     /*!< (@ 0x00000008) System Clock Divide Register 1                             */
+    
+    struct {
+      __IOM uint32_t HDIV       : 3;            /*!< [2..0] Clock Divide for HCLK, Divider 0                                   */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t WLDIV      : 3;            /*!< [6..4] Clock Divide for Watch Timer and LCD Driver, Divider
+                                                     2                                                                         */
+    } SCDIVR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCDIVR2;                     /*!< (@ 0x0000000C) System Clock Divide Register 2                             */
+    
+    struct {
+      __IOM uint32_t PDIV       : 2;            /*!< [1..0] Clock Divide for PCLK, Divider 1                                   */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t SYSTDIV    : 2;            /*!< [5..4] Clock Divide for SysTick Timer, Divider 3                          */
+    } SCDIVR2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CLKOCR;                      /*!< (@ 0x00000010) Clock Output Control Register                              */
+    
+    struct {
+      __IOM uint32_t CLKOS      : 3;            /*!< [2..0] Clock Output Selection                                             */
+      __IOM uint32_t CLKODIV    : 3;            /*!< [5..3] Output Clock Divide, Divider 4                                     */
+      __IOM uint32_t POLSEL     : 1;            /*!< [6..6] Clock Output Polarity Selection when Disable                       */
+      __IOM uint32_t CLKOEN     : 1;            /*!< [7..7] Clock Output Enable                                                */
+    } CLKOCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CMONCR;                      /*!< (@ 0x00000014) Clock Monitoring Control Register                          */
+    
+    struct {
+      __IOM uint32_t MONCS      : 2;            /*!< [1..0] Monitored Clock Selection                                          */
+      __IOM uint32_t NMINTFG    : 1;            /*!< [2..2] Clock Monitoring Interrupt Flag                                    */
+      __IOM uint32_t MONFLAG    : 1;            /*!< [3..3] Clock Monitoring Result Flag                                       */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t MACTS      : 2;            /*!< [6..5] Clock Monitoring Action Selection                                  */
+      __IOM uint32_t MONEN      : 1;            /*!< [7..7] Clock Monitoring Enable                                            */
+    } CMONCR_b;
+  } ;
+  __IM  uint32_t  RESERVED[2];
+  
+  union {
+    __IOM uint32_t PPCLKEN1;                    /*!< (@ 0x00000020) Peripheral Clock Enable Register 1                         */
+    
+    struct {
+      __IOM uint32_t PACLKE     : 1;            /*!< [0..0] Port A Clock Enable                                                */
+      __IOM uint32_t PBCLKE     : 1;            /*!< [1..1] Port B Clock Enable                                                */
+      __IOM uint32_t PCCLKE     : 1;            /*!< [2..2] Port C Clock Enable                                                */
+      __IOM uint32_t PDCLKE     : 1;            /*!< [3..3] Port D Clock Enable                                                */
+      __IOM uint32_t PECLKE     : 1;            /*!< [4..4] Port E Clock Enable                                                */
+      __IOM uint32_t PFCLKE     : 1;            /*!< [5..5] Port F Clock Enable                                                */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T13CLKE    : 1;            /*!< [8..8] TIMER13 Clock Enable                                               */
+      __IOM uint32_t T14CLKE    : 1;            /*!< [9..9] TIMER14 Clock Enable                                               */
+      __IOM uint32_t T15CLKE    : 1;            /*!< [10..10] TIMER15 Clock Enable                                             */
+      __IOM uint32_t T16CLKE    : 1;            /*!< [11..11] TIMER16 Clock Enable                                             */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t T10CLKE    : 1;            /*!< [16..16] TIMER10 Clock Enable                                             */
+      __IOM uint32_t T11CLKE    : 1;            /*!< [17..17] TIMER11 Clock Enable                                             */
+      __IOM uint32_t T12CLKE    : 1;            /*!< [18..18] TIMER12 Clock Enable                                             */
+      __IOM uint32_t T30CLKE    : 1;            /*!< [19..19] TIMER30 Clock Enable                                             */
+      __IOM uint32_t T20CLKE    : 1;            /*!< [20..20] TIMER20 Clock Enable                                             */
+      __IOM uint32_t T21CLKE    : 1;            /*!< [21..21] TIMER21 Clock Enable                                             */
+    } PPCLKEN1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PPCLKEN2;                    /*!< (@ 0x00000024) Peripheral Clock Enable Register 2                         */
+    
+    struct {
+      __IOM uint32_t UST10CLKE  : 1;            /*!< [0..0] USART10 Clock Enable                                               */
+      __IOM uint32_t UST11CLKE  : 1;            /*!< [1..1] USART11 Clock Enable                                               */
+      __IOM uint32_t UT0CLKE    : 1;            /*!< [2..2] UART0 Clock Enable                                                 */
+      __IOM uint32_t UT1CLKE    : 1;            /*!< [3..3] UART1 Clock Enable                                                 */
+      __IOM uint32_t UST12CLKE  : 1;            /*!< [4..4] USART12 Clock Enable                                               */
+      __IOM uint32_t UST13CLKE  : 1;            /*!< [5..5] USART13 Clock Enable                                               */
+      __IOM uint32_t I2C0CLKE   : 1;            /*!< [6..6] I2C0 (Inter-IC) Clock Enable                                       */
+      __IOM uint32_t I2C1CLKE   : 1;            /*!< [7..7] I2C1 (Inter-IC) Clock Enable                                       */
+      __IOM uint32_t I2C2CLKE   : 1;            /*!< [8..8] I2C2 (Inter-IC) Clock Enable                                       */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t ADCLKE     : 1;            /*!< [10..10] ADC (Analog to Digital Converter) Clock Enable                   */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t CRCLKE     : 1;            /*!< [12..12] CRC (Cyclic Redundancy Check) Clock Enable                       */
+      __IOM uint32_t LCDCLKE    : 1;            /*!< [13..13] LCD (LCD Driver) Clock Enable                                    */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t WTCLKE     : 1;            /*!< [16..16] WT (Watch Timer) Clock Enable                                    */
+      __IOM uint32_t WDTCLKE    : 1;            /*!< [17..17] WDT (Watch-Dog Timer) Clock Enable                               */
+      __IOM uint32_t LVICLKE    : 1;            /*!< [18..18] LVI (Low Voltage Indicator) Clock Enable                         */
+      __IOM uint32_t FMCLKE     : 1;            /*!< [19..19] FMC (Flash Memory Controller) Clock Enable                       */
+    } PPCLKEN2_b;
+  } ;
+  __IM  uint32_t  RESERVED1[6];
+  
+  union {
+    __IOM uint32_t PPCLKSR;                     /*!< (@ 0x00000040) Peripheral Clock Selection Register                        */
+    
+    struct {
+      __IOM uint32_t WDTCLK     : 1;            /*!< [0..0] WDT (Watch-Dog Timer) Clock Selection                              */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t WTCLK      : 2;            /*!< [4..3] WT (Watch Timer) Clock Selection                                   */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LCDCLK     : 2;            /*!< [7..6] LCD (LCD Driver) Clock Selection                                   */
+      __IM  uint32_t            : 9;
+      __IOM uint32_t T30CLK     : 1;            /*!< [17..17] TIMER30 Clock Selection                                          */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T20CLK     : 1;            /*!< [20..20] TIMER20 Clock Selection                                          */
+    } PPCLKSR_b;
+  } ;
+  __IM  uint32_t  RESERVED2[7];
+  
+  union {
+    __IOM uint32_t PPRST1;                      /*!< (@ 0x00000060) Peripheral Reset Register 1                                */
+    
+    struct {
+      __IOM uint32_t PARST      : 1;            /*!< [0..0] Port A Reset                                                       */
+      __IOM uint32_t PBRST      : 1;            /*!< [1..1] Port B Reset                                                       */
+      __IOM uint32_t PCRST      : 1;            /*!< [2..2] Port C Reset                                                       */
+      __IOM uint32_t PDRST      : 1;            /*!< [3..3] Port D Reset                                                       */
+      __IOM uint32_t PERST      : 1;            /*!< [4..4] Port E Reset                                                       */
+      __IOM uint32_t PFRST      : 1;            /*!< [5..5] Port F Reset                                                       */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T13RST     : 1;            /*!< [8..8] TIMER13 Reset                                                      */
+      __IOM uint32_t T14RST     : 1;            /*!< [9..9] TIMER14 Reset                                                      */
+      __IOM uint32_t T15RST     : 1;            /*!< [10..10] TIMER15 Reset                                                    */
+      __IOM uint32_t T16RST     : 1;            /*!< [11..11] TIMER16 Reset                                                    */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t T10RST     : 1;            /*!< [16..16] TIMER10 Reset                                                    */
+      __IOM uint32_t T11RST     : 1;            /*!< [17..17] TIMER11 Reset                                                    */
+      __IOM uint32_t T12RST     : 1;            /*!< [18..18] TIMER12 Reset                                                    */
+      __IOM uint32_t T30RST     : 1;            /*!< [19..19] TIMER30 Reset                                                    */
+      __IOM uint32_t T20RST     : 1;            /*!< [20..20] TIMER20 Reset                                                    */
+      __IOM uint32_t T21RST     : 1;            /*!< [21..21] TIMER21 Reset                                                    */
+    } PPRST1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PPRST2;                      /*!< (@ 0x00000064) Peripheral Reset Register 2                                */
+    
+    struct {
+      __IOM uint32_t UST10RST   : 1;            /*!< [0..0] USART10 Reset                                                      */
+      __IOM uint32_t UST11RST   : 1;            /*!< [1..1] USART11 Reset                                                      */
+      __IOM uint32_t UT0RST     : 1;            /*!< [2..2] UART0 Reset                                                        */
+      __IOM uint32_t UT1RST     : 1;            /*!< [3..3] UART1 Reset                                                        */
+      __IOM uint32_t UST12RST   : 1;            /*!< [4..4] USART12 Reset                                                      */
+      __IOM uint32_t UST13RST   : 1;            /*!< [5..5] USART13 Reset                                                      */
+      __IOM uint32_t I2C0RST    : 1;            /*!< [6..6] I2C0 (Inter-IC) Reset                                              */
+      __IOM uint32_t I2C1RST    : 1;            /*!< [7..7] I2C1 (Inter-IC) Reset                                              */
+      __IOM uint32_t I2C2RST    : 1;            /*!< [8..8] I2C2 (Inter-IC) Reset                                              */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t ADRST      : 1;            /*!< [10..10] ADC (Analog to Digital Converter) Reset                          */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t CRRST      : 1;            /*!< [12..12] CRC (Cyclic Redundancy Check) Reset                              */
+      __IOM uint32_t LCDRST     : 1;            /*!< [13..13] LCD (LCD Driver) Reset                                           */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t WTRST      : 1;            /*!< [16..16] WT (Watch Timer) Reset                                           */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LVIRST     : 1;            /*!< [18..18] LVI (Low Voltage Indicator) Reset                                */
+      __IOM uint32_t FMCRST     : 1;            /*!< [19..19] FMC (Flash Memory Controller) Reset                              */
+    } PPRST2_b;
+  } ;
+  __IM  uint32_t  RESERVED3[6];
+  
+  union {
+    __IOM uint32_t XTFLSR;                      /*!< (@ 0x00000080) X-tal Filter Selection Register                            */
+    
+    struct {
+      __IOM uint32_t XRNS       : 3;            /*!< [2..0] External Main Oscillator Filter Selection                          */
+      __IM  uint32_t            : 13;
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0x9b37)                                */
+    } XTFLSR_b;
+  } ;
+} SCUCG_Type;                                   /*!< Size = 132 (0x84)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCULV                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief System Control Unit: LVI and LVR (SCULV)
+  */
+
+typedef struct {                                /*!< (@ 0x40005100) SCULV Structure                                            */
+  
+  union {
+    __IOM uint32_t LVICR;                       /*!< (@ 0x00000000) Low Voltage Indicator Control Register                     */
+    
+    struct {
+      __IOM uint32_t LVIVS      : 4;            /*!< [3..0] LVI Voltage Selection                                              */
+      __IOM uint32_t LVIFLAG    : 1;            /*!< [4..4] LVI Interrupt Flag                                                 */
+      __IOM uint32_t LVINTEN    : 1;            /*!< [5..5] LVI Interrupt Enable                                               */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LVIEN      : 1;            /*!< [7..7] LVI Enable                                                         */
+    } LVICR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t LVRCR;                       /*!< (@ 0x00000004) Low Voltage Reset Control Register                         */
+    
+    struct {
+      __IOM uint32_t LVREN      : 8;            /*!< [7..0] LVR Enable                                                         */
+    } LVRCR_b;
+  } ;
+} SCULV_Type;                                   /*!< Size = 8 (0x8)                                                            */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            Pn                                             ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Port Control Unit & GPIO Port n (Pn)
+  */
+
+typedef struct {                                /*!< (@ 0x50000000) Pn Structure                                               */
+  
+  union {
+    __IOM uint32_t MOD;                         /*!< (@ 0x00000000) Port n Mode Register                                       */
+    
+    struct {
+      __IOM uint32_t MODE0      : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+      __IOM uint32_t MODE1      : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+      __IOM uint32_t MODE2      : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+      __IOM uint32_t MODE3      : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+      __IOM uint32_t MODE4      : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+      __IOM uint32_t MODE5      : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+      __IOM uint32_t MODE6      : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+      __IOM uint32_t MODE7      : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+      __IOM uint32_t MODE8      : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+      __IOM uint32_t MODE9      : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+      __IOM uint32_t MODE10     : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+      __IOM uint32_t MODE11     : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+      __IOM uint32_t MODE12     : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+      __IOM uint32_t MODE13     : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+      __IOM uint32_t MODE14     : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+      __IOM uint32_t MODE15     : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+    } MOD_b;
+  } ;
+  
+  union {
+    __IOM uint32_t TYP;                         /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+    
+    struct {
+      __IOM uint32_t TYP0       : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+      __IOM uint32_t TYP1       : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+      __IOM uint32_t TYP2       : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+      __IOM uint32_t TYP3       : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+      __IOM uint32_t TYP4       : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+      __IOM uint32_t TYP5       : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+      __IOM uint32_t TYP6       : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+      __IOM uint32_t TYP7       : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+      __IOM uint32_t TYP8       : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+      __IOM uint32_t TYP9       : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+      __IOM uint32_t TYP10      : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+      __IOM uint32_t TYP11      : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+      __IOM uint32_t TYP12      : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+      __IOM uint32_t TYP13      : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+      __IOM uint32_t TYP14      : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+      __IOM uint32_t TYP15      : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+    } TYP_b;
+  } ;
+  
+  union {
+    __IOM uint32_t AFSR1;                       /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+    
+    struct {
+      __IOM uint32_t AFSR0      : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+      __IOM uint32_t AFSR1      : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+      __IOM uint32_t AFSR2      : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+      __IOM uint32_t AFSR3      : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+      __IOM uint32_t AFSR4      : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+      __IOM uint32_t AFSR5      : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+      __IOM uint32_t AFSR6      : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+      __IOM uint32_t AFSR7      : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+    } AFSR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t AFSR2;                       /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+    
+    struct {
+      __IOM uint32_t AFSR8      : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+      __IOM uint32_t AFSR9      : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+      __IOM uint32_t AFSR10     : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+      __IOM uint32_t AFSR11     : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+      __IOM uint32_t AFSR12     : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+      __IOM uint32_t AFSR13     : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+      __IOM uint32_t AFSR14     : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+      __IOM uint32_t AFSR15     : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+    } AFSR2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PUPD;                        /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+    
+    struct {
+      __IOM uint32_t PUPD0      : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+      __IOM uint32_t PUPD1      : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+      __IOM uint32_t PUPD2      : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+      __IOM uint32_t PUPD3      : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+      __IOM uint32_t PUPD4      : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+      __IOM uint32_t PUPD5      : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+      __IOM uint32_t PUPD6      : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+      __IOM uint32_t PUPD7      : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+      __IOM uint32_t PUPD8      : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+      __IOM uint32_t PUPD9      : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+      __IOM uint32_t PUPD10     : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+      __IOM uint32_t PUPD11     : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+      __IOM uint32_t PUPD12     : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+      __IOM uint32_t PUPD13     : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+      __IOM uint32_t PUPD14     : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+      __IOM uint32_t PUPD15     : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+    } PUPD_b;
+  } ;
+  
+  union {
+    __IM  uint32_t INDR;                        /*!< (@ 0x00000014) Port n Input Data Register                                 */
+    
+    struct {
+      __IM  uint32_t INDR0      : 1;            /*!< [0..0] Port n Input Data 0                                                */
+      __IM  uint32_t INDR1      : 1;            /*!< [1..1] Port n Input Data 1                                                */
+      __IM  uint32_t INDR2      : 1;            /*!< [2..2] Port n Input Data 2                                                */
+      __IM  uint32_t INDR3      : 1;            /*!< [3..3] Port n Input Data 3                                                */
+      __IM  uint32_t INDR4      : 1;            /*!< [4..4] Port n Input Data 4                                                */
+      __IM  uint32_t INDR5      : 1;            /*!< [5..5] Port n Input Data 5                                                */
+      __IM  uint32_t INDR6      : 1;            /*!< [6..6] Port n Input Data 6                                                */
+      __IM  uint32_t INDR7      : 1;            /*!< [7..7] Port n Input Data 7                                                */
+      __IM  uint32_t INDR8      : 1;            /*!< [8..8] Port n Input Data 8                                                */
+      __IM  uint32_t INDR9      : 1;            /*!< [9..9] Port n Input Data 9                                                */
+      __IM  uint32_t INDR10     : 1;            /*!< [10..10] Port n Input Data 10                                             */
+      __IM  uint32_t INDR11     : 1;            /*!< [11..11] Port n Input Data 11                                             */
+      __IM  uint32_t INDR12     : 1;            /*!< [12..12] Port n Input Data 12                                             */
+      __IM  uint32_t INDR13     : 1;            /*!< [13..13] Port n Input Data 13                                             */
+      __IM  uint32_t INDR14     : 1;            /*!< [14..14] Port n Input Data 14                                             */
+      __IM  uint32_t INDR15     : 1;            /*!< [15..15] Port n Input Data 15                                             */
+    } INDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t OUTDR;                       /*!< (@ 0x00000018) Port n Output Data Register                                */
+    
+    struct {
+      __IOM uint32_t OUTDR0     : 1;            /*!< [0..0] Port n Output Data 0                                               */
+      __IOM uint32_t OUTDR1     : 1;            /*!< [1..1] Port n Output Data 1                                               */
+      __IOM uint32_t OUTDR2     : 1;            /*!< [2..2] Port n Output Data 2                                               */
+      __IOM uint32_t OUTDR3     : 1;            /*!< [3..3] Port n Output Data 3                                               */
+      __IOM uint32_t OUTDR4     : 1;            /*!< [4..4] Port n Output Data 4                                               */
+      __IOM uint32_t OUTDR5     : 1;            /*!< [5..5] Port n Output Data 5                                               */
+      __IOM uint32_t OUTDR6     : 1;            /*!< [6..6] Port n Output Data 6                                               */
+      __IOM uint32_t OUTDR7     : 1;            /*!< [7..7] Port n Output Data 7                                               */
+      __IOM uint32_t OUTDR8     : 1;            /*!< [8..8] Port n Output Data 8                                               */
+      __IOM uint32_t OUTDR9     : 1;            /*!< [9..9] Port n Output Data 9                                               */
+      __IOM uint32_t OUTDR10    : 1;            /*!< [10..10] Port n Output Data 10                                            */
+      __IOM uint32_t OUTDR11    : 1;            /*!< [11..11] Port n Output Data 11                                            */
+      __IOM uint32_t OUTDR12    : 1;            /*!< [12..12] Port n Output Data 12                                            */
+      __IOM uint32_t OUTDR13    : 1;            /*!< [13..13] Port n Output Data 13                                            */
+      __IOM uint32_t OUTDR14    : 1;            /*!< [14..14] Port n Output Data 14                                            */
+      __IOM uint32_t OUTDR15    : 1;            /*!< [15..15] Port n Output Data 15                                            */
+    } OUTDR_b;
+  } ;
+  
+  union {
+    __OM  uint32_t BSR;                         /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+    
+    struct {
+      __OM  uint32_t BSR0       : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+      __OM  uint32_t BSR1       : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+      __OM  uint32_t BSR2       : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+      __OM  uint32_t BSR3       : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+      __OM  uint32_t BSR4       : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+      __OM  uint32_t BSR5       : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+      __OM  uint32_t BSR6       : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+      __OM  uint32_t BSR7       : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+      __OM  uint32_t BSR8       : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+      __OM  uint32_t BSR9       : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+      __OM  uint32_t BSR10      : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+      __OM  uint32_t BSR11      : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+      __OM  uint32_t BSR12      : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+      __OM  uint32_t BSR13      : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+      __OM  uint32_t BSR14      : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+      __OM  uint32_t BSR15      : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+    } BSR_b;
+  } ;
+  
+  union {
+    __OM  uint32_t BCR;                         /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+    
+    struct {
+      __OM  uint32_t BCR0       : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+      __OM  uint32_t BCR1       : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+      __OM  uint32_t BCR2       : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+      __OM  uint32_t BCR3       : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+      __OM  uint32_t BCR4       : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+      __OM  uint32_t BCR5       : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+      __OM  uint32_t BCR6       : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+      __OM  uint32_t BCR7       : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+      __OM  uint32_t BCR8       : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+      __OM  uint32_t BCR9       : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+      __OM  uint32_t BCR10      : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+      __OM  uint32_t BCR11      : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+      __OM  uint32_t BCR12      : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+      __OM  uint32_t BCR13      : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+      __OM  uint32_t BCR14      : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+      __OM  uint32_t BCR15      : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+    } BCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t OUTDMSK;                     /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+    
+    struct {
+      __IOM uint32_t OUTDMSK0   : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+      __IOM uint32_t OUTDMSK1   : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+      __IOM uint32_t OUTDMSK2   : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+      __IOM uint32_t OUTDMSK3   : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+      __IOM uint32_t OUTDMSK4   : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+      __IOM uint32_t OUTDMSK5   : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+      __IOM uint32_t OUTDMSK6   : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+      __IOM uint32_t OUTDMSK7   : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+      __IOM uint32_t OUTDMSK8   : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+      __IOM uint32_t OUTDMSK9   : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+      __IOM uint32_t OUTDMSK10  : 1;            /*!< [10..10] Port n Output Data Mask 10                                       */
+      __IOM uint32_t OUTDMSK11  : 1;            /*!< [11..11] Port n Output Data Mask 11                                       */
+      __IOM uint32_t OUTDMSK12  : 1;            /*!< [12..12] Port n Output Data Mask 12                                       */
+      __IOM uint32_t OUTDMSK13  : 1;            /*!< [13..13] Port n Output Data Mask 13                                       */
+      __IOM uint32_t OUTDMSK14  : 1;            /*!< [14..14] Port n Output Data Mask 14                                       */
+      __IOM uint32_t OUTDMSK15  : 1;            /*!< [15..15] Port n Output Data Mask 15                                       */
+    } OUTDMSK_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DBCR;                        /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+    
+    struct {
+      __IOM uint32_t DBEN0      : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+      __IOM uint32_t DBEN1      : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+      __IOM uint32_t DBEN2      : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+      __IOM uint32_t DBEN3      : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+      __IOM uint32_t DBEN4      : 1;            /*!< [4..4] Port n Debounce Enable 4                                           */
+      __IOM uint32_t DBEN5      : 1;            /*!< [5..5] Port n Debounce Enable 5                                           */
+      __IOM uint32_t DBEN6      : 1;            /*!< [6..6] Port n Debounce Enable 6                                           */
+      __IOM uint32_t DBEN7      : 1;            /*!< [7..7] Port n Debounce Enable 7                                           */
+      __IOM uint32_t DBEN8      : 1;            /*!< [8..8] Port n Debounce Enable 8                                           */
+      __IOM uint32_t DBEN9      : 1;            /*!< [9..9] Port n Debounce Enable 9                                           */
+      __IOM uint32_t DBEN10     : 1;            /*!< [10..10] Port n Debounce Enable 10                                        */
+      __IOM uint32_t DBEN11     : 1;            /*!< [11..11] Port n Debounce Enable 11                                        */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t DBCLK      : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+    } DBCR_b;
+  } ;
+} Pn_Type;                                      /*!< Size = 44 (0x2c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            PA                                             ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Port Control Unit & GPIO Port A (PA)
+  */
+
+typedef struct {                                /*!< (@ 0x30000000) PA Structure                                               */
+  
+  union {
+    union {
+      __IOM uint32_t MOD;                       /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+        __IOM uint32_t MODE13   : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+        __IOM uint32_t MODE14   : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+        __IOM uint32_t MODE15   : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+      } MOD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PA_MOD;                    /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+      } PA_MOD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t TYP;                       /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+        __IOM uint32_t TYP13    : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+        __IOM uint32_t TYP14    : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+        __IOM uint32_t TYP15    : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+      } TYP_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PA_TYP;                    /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+      } PA_TYP_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR1;                     /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } AFSR1_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PA_AFSR1;                  /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } PA_AFSR1_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR2;                     /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+        __IOM uint32_t AFSR13   : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+        __IOM uint32_t AFSR14   : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+        __IOM uint32_t AFSR15   : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+      } AFSR2_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PA_AFSR2;                  /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+      } PA_AFSR2_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t PUPD;                      /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+        __IOM uint32_t PUPD13   : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+        __IOM uint32_t PUPD14   : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+        __IOM uint32_t PUPD15   : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+      } PUPD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PA_PUPD;                   /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+      } PA_PUPD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IM  uint32_t INDR;                      /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+        __IM  uint32_t INDR13   : 1;            /*!< [13..13] Port n Input Data 13                                             */
+        __IM  uint32_t INDR14   : 1;            /*!< [14..14] Port n Input Data 14                                             */
+        __IM  uint32_t INDR15   : 1;            /*!< [15..15] Port n Input Data 15                                             */
+      } INDR_b;
+    } ;
+    
+    union {
+      __IM  uint32_t PA_INDR;                   /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+      } PA_INDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDR;                     /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+        __IOM uint32_t OUTDR13  : 1;            /*!< [13..13] Port n Output Data 13                                            */
+        __IOM uint32_t OUTDR14  : 1;            /*!< [14..14] Port n Output Data 14                                            */
+        __IOM uint32_t OUTDR15  : 1;            /*!< [15..15] Port n Output Data 15                                            */
+      } OUTDR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PA_OUTDR;                  /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+      } PA_OUTDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BSR;                       /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+        __OM  uint32_t BSR13    : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+        __OM  uint32_t BSR14    : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+        __OM  uint32_t BSR15    : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+      } BSR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PA_BSR;                    /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+      } PA_BSR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BCR;                       /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+        __OM  uint32_t BCR13    : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+        __OM  uint32_t BCR14    : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+        __OM  uint32_t BCR15    : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+      } BCR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PA_BCR;                    /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+      } PA_BCR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDMSK;                   /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+        __IOM uint32_t OUTDMSK13 : 1;           /*!< [13..13] Port n Output Data Mask 13                                       */
+        __IOM uint32_t OUTDMSK14 : 1;           /*!< [14..14] Port n Output Data Mask 14                                       */
+        __IOM uint32_t OUTDMSK15 : 1;           /*!< [15..15] Port n Output Data Mask 15                                       */
+      } OUTDMSK_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PA_OUTDMSK;                /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+      } PA_OUTDMSK_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t DBCR;                        /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+    
+    struct {
+      __IOM uint32_t DBEN0      : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+      __IOM uint32_t DBEN1      : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+      __IOM uint32_t DBEN2      : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+      __IOM uint32_t DBEN3      : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+      __IOM uint32_t DBEN4      : 1;            /*!< [4..4] Port n Debounce Enable 4                                           */
+      __IOM uint32_t DBEN5      : 1;            /*!< [5..5] Port n Debounce Enable 5                                           */
+      __IOM uint32_t DBEN6      : 1;            /*!< [6..6] Port n Debounce Enable 6                                           */
+      __IOM uint32_t DBEN7      : 1;            /*!< [7..7] Port n Debounce Enable 7                                           */
+      __IOM uint32_t DBEN8      : 1;            /*!< [8..8] Port n Debounce Enable 8                                           */
+      __IOM uint32_t DBEN9      : 1;            /*!< [9..9] Port n Debounce Enable 9                                           */
+      __IOM uint32_t DBEN10     : 1;            /*!< [10..10] Port n Debounce Enable 10                                        */
+      __IOM uint32_t DBEN11     : 1;            /*!< [11..11] Port n Debounce Enable 11                                        */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t DBCLK      : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+    } DBCR_b;
+  } ;
+} PA_Type;                                      /*!< Size = 44 (0x2c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            PB                                             ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Port Control Unit & GPIO Port B (PB)
+  */
+
+typedef struct {                                /*!< (@ 0x30000100) PB Structure                                               */
+  
+  union {
+    union {
+      __IOM uint32_t MOD;                       /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+        __IOM uint32_t MODE13   : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+        __IOM uint32_t MODE14   : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+        __IOM uint32_t MODE15   : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+      } MOD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PB_MOD;                    /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+        __IOM uint32_t MODE13   : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+        __IOM uint32_t MODE14   : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+        __IOM uint32_t MODE15   : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+      } PB_MOD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t TYP;                       /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+        __IOM uint32_t TYP13    : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+        __IOM uint32_t TYP14    : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+        __IOM uint32_t TYP15    : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+      } TYP_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PB_TYP;                    /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+        __IOM uint32_t TYP13    : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+        __IOM uint32_t TYP14    : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+        __IOM uint32_t TYP15    : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+      } PB_TYP_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR1;                     /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } AFSR1_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PB_AFSR1;                  /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } PB_AFSR1_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR2;                     /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+        __IOM uint32_t AFSR13   : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+        __IOM uint32_t AFSR14   : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+        __IOM uint32_t AFSR15   : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+      } AFSR2_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PB_AFSR2;                  /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+        __IOM uint32_t AFSR13   : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+        __IOM uint32_t AFSR14   : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+        __IOM uint32_t AFSR15   : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+      } PB_AFSR2_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t PUPD;                      /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+        __IOM uint32_t PUPD13   : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+        __IOM uint32_t PUPD14   : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+        __IOM uint32_t PUPD15   : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+      } PUPD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PB_PUPD;                   /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+        __IOM uint32_t PUPD13   : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+        __IOM uint32_t PUPD14   : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+        __IOM uint32_t PUPD15   : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+      } PB_PUPD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IM  uint32_t INDR;                      /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+        __IM  uint32_t INDR13   : 1;            /*!< [13..13] Port n Input Data 13                                             */
+        __IM  uint32_t INDR14   : 1;            /*!< [14..14] Port n Input Data 14                                             */
+        __IM  uint32_t INDR15   : 1;            /*!< [15..15] Port n Input Data 15                                             */
+      } INDR_b;
+    } ;
+    
+    union {
+      __IM  uint32_t PB_INDR;                   /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+        __IM  uint32_t INDR13   : 1;            /*!< [13..13] Port n Input Data 13                                             */
+        __IM  uint32_t INDR14   : 1;            /*!< [14..14] Port n Input Data 14                                             */
+        __IM  uint32_t INDR15   : 1;            /*!< [15..15] Port n Input Data 15                                             */
+      } PB_INDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDR;                     /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+        __IOM uint32_t OUTDR13  : 1;            /*!< [13..13] Port n Output Data 13                                            */
+        __IOM uint32_t OUTDR14  : 1;            /*!< [14..14] Port n Output Data 14                                            */
+        __IOM uint32_t OUTDR15  : 1;            /*!< [15..15] Port n Output Data 15                                            */
+      } OUTDR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PB_OUTDR;                  /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+        __IOM uint32_t OUTDR13  : 1;            /*!< [13..13] Port n Output Data 13                                            */
+        __IOM uint32_t OUTDR14  : 1;            /*!< [14..14] Port n Output Data 14                                            */
+        __IOM uint32_t OUTDR15  : 1;            /*!< [15..15] Port n Output Data 15                                            */
+      } PB_OUTDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BSR;                       /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+        __OM  uint32_t BSR13    : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+        __OM  uint32_t BSR14    : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+        __OM  uint32_t BSR15    : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+      } BSR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PB_BSR;                    /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+        __OM  uint32_t BSR13    : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+        __OM  uint32_t BSR14    : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+        __OM  uint32_t BSR15    : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+      } PB_BSR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BCR;                       /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+        __OM  uint32_t BCR13    : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+        __OM  uint32_t BCR14    : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+        __OM  uint32_t BCR15    : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+      } BCR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PB_BCR;                    /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+        __OM  uint32_t BCR13    : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+        __OM  uint32_t BCR14    : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+        __OM  uint32_t BCR15    : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+      } PB_BCR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDMSK;                   /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+        __IOM uint32_t OUTDMSK13 : 1;           /*!< [13..13] Port n Output Data Mask 13                                       */
+        __IOM uint32_t OUTDMSK14 : 1;           /*!< [14..14] Port n Output Data Mask 14                                       */
+        __IOM uint32_t OUTDMSK15 : 1;           /*!< [15..15] Port n Output Data Mask 15                                       */
+      } OUTDMSK_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PB_OUTDMSK;                /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+        __IOM uint32_t OUTDMSK13 : 1;           /*!< [13..13] Port n Output Data Mask 13                                       */
+        __IOM uint32_t OUTDMSK14 : 1;           /*!< [14..14] Port n Output Data Mask 14                                       */
+        __IOM uint32_t OUTDMSK15 : 1;           /*!< [15..15] Port n Output Data Mask 15                                       */
+      } PB_OUTDMSK_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t DBCR;                      /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+      
+      struct {
+        __IOM uint32_t DBEN0    : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+        __IOM uint32_t DBEN1    : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+        __IOM uint32_t DBEN2    : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+        __IOM uint32_t DBEN3    : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+        __IOM uint32_t DBEN4    : 1;            /*!< [4..4] Port n Debounce Enable 4                                           */
+        __IOM uint32_t DBEN5    : 1;            /*!< [5..5] Port n Debounce Enable 5                                           */
+        __IOM uint32_t DBEN6    : 1;            /*!< [6..6] Port n Debounce Enable 6                                           */
+        __IOM uint32_t DBEN7    : 1;            /*!< [7..7] Port n Debounce Enable 7                                           */
+        __IOM uint32_t DBEN8    : 1;            /*!< [8..8] Port n Debounce Enable 8                                           */
+        __IOM uint32_t DBEN9    : 1;            /*!< [9..9] Port n Debounce Enable 9                                           */
+        __IOM uint32_t DBEN10   : 1;            /*!< [10..10] Port n Debounce Enable 10                                        */
+        __IOM uint32_t DBEN11   : 1;            /*!< [11..11] Port n Debounce Enable 11                                        */
+        __IM  uint32_t          : 4;
+        __IOM uint32_t DBCLK    : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+      } DBCR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PB_DBCR;                   /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+      
+      struct {
+        __IOM uint32_t DBEN0    : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+        __IOM uint32_t DBEN1    : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+        __IOM uint32_t DBEN2    : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+        __IOM uint32_t DBEN3    : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+        __IOM uint32_t DBEN4    : 1;            /*!< [4..4] Port n Debounce Enable 4                                           */
+        __IOM uint32_t DBEN5    : 1;            /*!< [5..5] Port n Debounce Enable 5                                           */
+        __IOM uint32_t DBEN6    : 1;            /*!< [6..6] Port n Debounce Enable 6                                           */
+        __IOM uint32_t DBEN7    : 1;            /*!< [7..7] Port n Debounce Enable 7                                           */
+        __IOM uint32_t DBEN8    : 1;            /*!< [8..8] Port n Debounce Enable 8                                           */
+        __IOM uint32_t DBEN9    : 1;            /*!< [9..9] Port n Debounce Enable 9                                           */
+        __IOM uint32_t DBEN10   : 1;            /*!< [10..10] Port n Debounce Enable 10                                        */
+        __IOM uint32_t DBEN11   : 1;            /*!< [11..11] Port n Debounce Enable 11                                        */
+        __IM  uint32_t          : 4;
+        __IOM uint32_t DBCLK    : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+      } PB_DBCR_b;
+    } ;
+  };
+} PB_Type;                                      /*!< Size = 44 (0x2c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            PC                                             ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Port Control Unit & GPIO Port C (PC)
+  */
+
+typedef struct {                                /*!< (@ 0x30000200) PC Structure                                               */
+  
+  union {
+    union {
+      __IOM uint32_t MOD;                       /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+        __IOM uint32_t MODE13   : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+        __IOM uint32_t MODE14   : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+        __IOM uint32_t MODE15   : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+      } MOD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PC_MOD;                    /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+      } PC_MOD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t TYP;                       /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+        __IOM uint32_t TYP13    : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+        __IOM uint32_t TYP14    : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+        __IOM uint32_t TYP15    : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+      } TYP_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PC_TYP;                    /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+      } PC_TYP_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR1;                     /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } AFSR1_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PC_AFSR1;                  /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } PC_AFSR1_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR2;                     /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+        __IOM uint32_t AFSR13   : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+        __IOM uint32_t AFSR14   : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+        __IOM uint32_t AFSR15   : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+      } AFSR2_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PC_AFSR2;                  /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+      } PC_AFSR2_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t PUPD;                      /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+        __IOM uint32_t PUPD13   : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+        __IOM uint32_t PUPD14   : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+        __IOM uint32_t PUPD15   : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+      } PUPD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PC_PUPD;                   /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+      } PC_PUPD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IM  uint32_t INDR;                      /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+        __IM  uint32_t INDR13   : 1;            /*!< [13..13] Port n Input Data 13                                             */
+        __IM  uint32_t INDR14   : 1;            /*!< [14..14] Port n Input Data 14                                             */
+        __IM  uint32_t INDR15   : 1;            /*!< [15..15] Port n Input Data 15                                             */
+      } INDR_b;
+    } ;
+    
+    union {
+      __IM  uint32_t PC_INDR;                   /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+      } PC_INDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDR;                     /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+        __IOM uint32_t OUTDR13  : 1;            /*!< [13..13] Port n Output Data 13                                            */
+        __IOM uint32_t OUTDR14  : 1;            /*!< [14..14] Port n Output Data 14                                            */
+        __IOM uint32_t OUTDR15  : 1;            /*!< [15..15] Port n Output Data 15                                            */
+      } OUTDR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PC_OUTDR;                  /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+      } PC_OUTDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BSR;                       /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+        __OM  uint32_t BSR13    : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+        __OM  uint32_t BSR14    : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+        __OM  uint32_t BSR15    : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+      } BSR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PC_BSR;                    /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+      } PC_BSR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BCR;                       /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+        __OM  uint32_t BCR13    : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+        __OM  uint32_t BCR14    : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+        __OM  uint32_t BCR15    : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+      } BCR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PC_BCR;                    /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+      } PC_BCR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDMSK;                   /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+        __IOM uint32_t OUTDMSK13 : 1;           /*!< [13..13] Port n Output Data Mask 13                                       */
+        __IOM uint32_t OUTDMSK14 : 1;           /*!< [14..14] Port n Output Data Mask 14                                       */
+        __IOM uint32_t OUTDMSK15 : 1;           /*!< [15..15] Port n Output Data Mask 15                                       */
+      } OUTDMSK_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PC_OUTDMSK;                /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+      } PC_OUTDMSK_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t DBCR;                      /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+      
+      struct {
+        __IOM uint32_t DBEN0    : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+        __IOM uint32_t DBEN1    : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+        __IOM uint32_t DBEN2    : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+        __IOM uint32_t DBEN3    : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+        __IOM uint32_t DBEN4    : 1;            /*!< [4..4] Port n Debounce Enable 4                                           */
+        __IOM uint32_t DBEN5    : 1;            /*!< [5..5] Port n Debounce Enable 5                                           */
+        __IOM uint32_t DBEN6    : 1;            /*!< [6..6] Port n Debounce Enable 6                                           */
+        __IOM uint32_t DBEN7    : 1;            /*!< [7..7] Port n Debounce Enable 7                                           */
+        __IOM uint32_t DBEN8    : 1;            /*!< [8..8] Port n Debounce Enable 8                                           */
+        __IOM uint32_t DBEN9    : 1;            /*!< [9..9] Port n Debounce Enable 9                                           */
+        __IOM uint32_t DBEN10   : 1;            /*!< [10..10] Port n Debounce Enable 10                                        */
+        __IOM uint32_t DBEN11   : 1;            /*!< [11..11] Port n Debounce Enable 11                                        */
+        __IM  uint32_t          : 4;
+        __IOM uint32_t DBCLK    : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+      } DBCR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PC_DBCR;                   /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+      
+      struct {
+        __IOM uint32_t DBEN0    : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+        __IOM uint32_t DBEN1    : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+        __IOM uint32_t DBEN2    : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+        __IOM uint32_t DBEN3    : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+        __IM  uint32_t          : 12;
+        __IOM uint32_t DBCLK    : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+      } PC_DBCR_b;
+    } ;
+  };
+} PC_Type;                                      /*!< Size = 44 (0x2c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            PD                                             ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Port Control Unit & GPIO Port D (PD)
+  */
+
+typedef struct {                                /*!< (@ 0x30000300) PD Structure                                               */
+  
+  union {
+    union {
+      __IOM uint32_t MOD;                       /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+        __IOM uint32_t MODE13   : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+        __IOM uint32_t MODE14   : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+        __IOM uint32_t MODE15   : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+      } MOD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PD_MOD;                    /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+      } PD_MOD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t TYP;                       /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+        __IOM uint32_t TYP13    : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+        __IOM uint32_t TYP14    : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+        __IOM uint32_t TYP15    : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+      } TYP_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PD_TYP;                    /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+      } PD_TYP_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR1;                     /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } AFSR1_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PD_AFSR1;                  /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } PD_AFSR1_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR2;                     /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+        __IOM uint32_t AFSR13   : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+        __IOM uint32_t AFSR14   : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+        __IOM uint32_t AFSR15   : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+      } AFSR2_b;
+    } ;
+    __IOM uint32_t PD_AFSR2;                    /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+  };
+  
+  union {
+    union {
+      __IOM uint32_t PUPD;                      /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+        __IOM uint32_t PUPD13   : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+        __IOM uint32_t PUPD14   : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+        __IOM uint32_t PUPD15   : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+      } PUPD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PD_PUPD;                   /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+      } PD_PUPD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IM  uint32_t INDR;                      /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+        __IM  uint32_t INDR13   : 1;            /*!< [13..13] Port n Input Data 13                                             */
+        __IM  uint32_t INDR14   : 1;            /*!< [14..14] Port n Input Data 14                                             */
+        __IM  uint32_t INDR15   : 1;            /*!< [15..15] Port n Input Data 15                                             */
+      } INDR_b;
+    } ;
+    
+    union {
+      __IM  uint32_t PD_INDR;                   /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+      } PD_INDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDR;                     /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+        __IOM uint32_t OUTDR13  : 1;            /*!< [13..13] Port n Output Data 13                                            */
+        __IOM uint32_t OUTDR14  : 1;            /*!< [14..14] Port n Output Data 14                                            */
+        __IOM uint32_t OUTDR15  : 1;            /*!< [15..15] Port n Output Data 15                                            */
+      } OUTDR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PD_OUTDR;                  /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+      } PD_OUTDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BSR;                       /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+        __OM  uint32_t BSR13    : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+        __OM  uint32_t BSR14    : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+        __OM  uint32_t BSR15    : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+      } BSR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PD_BSR;                    /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+      } PD_BSR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BCR;                       /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+        __OM  uint32_t BCR13    : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+        __OM  uint32_t BCR14    : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+        __OM  uint32_t BCR15    : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+      } BCR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PD_BCR;                    /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+      } PD_BCR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDMSK;                   /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+        __IOM uint32_t OUTDMSK13 : 1;           /*!< [13..13] Port n Output Data Mask 13                                       */
+        __IOM uint32_t OUTDMSK14 : 1;           /*!< [14..14] Port n Output Data Mask 14                                       */
+        __IOM uint32_t OUTDMSK15 : 1;           /*!< [15..15] Port n Output Data Mask 15                                       */
+      } OUTDMSK_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PD_OUTDMSK;                /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+      } PD_OUTDMSK_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t DBCR;                        /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+    
+    struct {
+      __IOM uint32_t DBEN0      : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+      __IOM uint32_t DBEN1      : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+      __IOM uint32_t DBEN2      : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+      __IOM uint32_t DBEN3      : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+      __IOM uint32_t DBEN4      : 1;            /*!< [4..4] Port n Debounce Enable 4                                           */
+      __IOM uint32_t DBEN5      : 1;            /*!< [5..5] Port n Debounce Enable 5                                           */
+      __IOM uint32_t DBEN6      : 1;            /*!< [6..6] Port n Debounce Enable 6                                           */
+      __IOM uint32_t DBEN7      : 1;            /*!< [7..7] Port n Debounce Enable 7                                           */
+      __IOM uint32_t DBEN8      : 1;            /*!< [8..8] Port n Debounce Enable 8                                           */
+      __IOM uint32_t DBEN9      : 1;            /*!< [9..9] Port n Debounce Enable 9                                           */
+      __IOM uint32_t DBEN10     : 1;            /*!< [10..10] Port n Debounce Enable 10                                        */
+      __IOM uint32_t DBEN11     : 1;            /*!< [11..11] Port n Debounce Enable 11                                        */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t DBCLK      : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+    } DBCR_b;
+  } ;
+} PD_Type;                                      /*!< Size = 44 (0x2c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            PE                                             ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Port Control Unit & GPIO Port E (PE)
+  */
+
+typedef struct {                                /*!< (@ 0x30000400) PE Structure                                               */
+  
+  union {
+    union {
+      __IOM uint32_t MOD;                       /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+        __IOM uint32_t MODE13   : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+        __IOM uint32_t MODE14   : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+        __IOM uint32_t MODE15   : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+      } MOD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PE_MOD;                    /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+        __IOM uint32_t MODE13   : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+        __IOM uint32_t MODE14   : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+        __IOM uint32_t MODE15   : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+      } PE_MOD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t TYP;                       /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+        __IOM uint32_t TYP13    : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+        __IOM uint32_t TYP14    : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+        __IOM uint32_t TYP15    : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+      } TYP_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PE_TYP;                    /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+        __IOM uint32_t TYP13    : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+        __IOM uint32_t TYP14    : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+        __IOM uint32_t TYP15    : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+      } PE_TYP_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR1;                     /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } AFSR1_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PE_AFSR1;                  /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } PE_AFSR1_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR2;                     /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+        __IOM uint32_t AFSR13   : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+        __IOM uint32_t AFSR14   : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+        __IOM uint32_t AFSR15   : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+      } AFSR2_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PE_AFSR2;                  /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+        __IOM uint32_t AFSR13   : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+        __IOM uint32_t AFSR14   : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+        __IOM uint32_t AFSR15   : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+      } PE_AFSR2_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t PUPD;                      /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+        __IOM uint32_t PUPD13   : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+        __IOM uint32_t PUPD14   : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+        __IOM uint32_t PUPD15   : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+      } PUPD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PE_PUPD;                   /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+        __IOM uint32_t PUPD13   : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+        __IOM uint32_t PUPD14   : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+        __IOM uint32_t PUPD15   : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+      } PE_PUPD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IM  uint32_t INDR;                      /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+        __IM  uint32_t INDR13   : 1;            /*!< [13..13] Port n Input Data 13                                             */
+        __IM  uint32_t INDR14   : 1;            /*!< [14..14] Port n Input Data 14                                             */
+        __IM  uint32_t INDR15   : 1;            /*!< [15..15] Port n Input Data 15                                             */
+      } INDR_b;
+    } ;
+    
+    union {
+      __IM  uint32_t PE_INDR;                   /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+        __IM  uint32_t INDR13   : 1;            /*!< [13..13] Port n Input Data 13                                             */
+        __IM  uint32_t INDR14   : 1;            /*!< [14..14] Port n Input Data 14                                             */
+        __IM  uint32_t INDR15   : 1;            /*!< [15..15] Port n Input Data 15                                             */
+      } PE_INDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDR;                     /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+        __IOM uint32_t OUTDR13  : 1;            /*!< [13..13] Port n Output Data 13                                            */
+        __IOM uint32_t OUTDR14  : 1;            /*!< [14..14] Port n Output Data 14                                            */
+        __IOM uint32_t OUTDR15  : 1;            /*!< [15..15] Port n Output Data 15                                            */
+      } OUTDR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PE_OUTDR;                  /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+        __IOM uint32_t OUTDR13  : 1;            /*!< [13..13] Port n Output Data 13                                            */
+        __IOM uint32_t OUTDR14  : 1;            /*!< [14..14] Port n Output Data 14                                            */
+        __IOM uint32_t OUTDR15  : 1;            /*!< [15..15] Port n Output Data 15                                            */
+      } PE_OUTDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BSR;                       /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+        __OM  uint32_t BSR13    : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+        __OM  uint32_t BSR14    : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+        __OM  uint32_t BSR15    : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+      } BSR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PE_BSR;                    /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+        __OM  uint32_t BSR13    : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+        __OM  uint32_t BSR14    : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+        __OM  uint32_t BSR15    : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+      } PE_BSR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BCR;                       /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+        __OM  uint32_t BCR13    : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+        __OM  uint32_t BCR14    : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+        __OM  uint32_t BCR15    : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+      } BCR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PE_BCR;                    /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+        __OM  uint32_t BCR13    : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+        __OM  uint32_t BCR14    : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+        __OM  uint32_t BCR15    : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+      } PE_BCR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDMSK;                   /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+        __IOM uint32_t OUTDMSK13 : 1;           /*!< [13..13] Port n Output Data Mask 13                                       */
+        __IOM uint32_t OUTDMSK14 : 1;           /*!< [14..14] Port n Output Data Mask 14                                       */
+        __IOM uint32_t OUTDMSK15 : 1;           /*!< [15..15] Port n Output Data Mask 15                                       */
+      } OUTDMSK_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PE_OUTDMSK;                /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+        __IOM uint32_t OUTDMSK13 : 1;           /*!< [13..13] Port n Output Data Mask 13                                       */
+        __IOM uint32_t OUTDMSK14 : 1;           /*!< [14..14] Port n Output Data Mask 14                                       */
+        __IOM uint32_t OUTDMSK15 : 1;           /*!< [15..15] Port n Output Data Mask 15                                       */
+      } PE_OUTDMSK_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t DBCR;                      /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+      
+      struct {
+        __IOM uint32_t DBEN0    : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+        __IOM uint32_t DBEN1    : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+        __IOM uint32_t DBEN2    : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+        __IOM uint32_t DBEN3    : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+        __IOM uint32_t DBEN4    : 1;            /*!< [4..4] Port n Debounce Enable 4                                           */
+        __IOM uint32_t DBEN5    : 1;            /*!< [5..5] Port n Debounce Enable 5                                           */
+        __IOM uint32_t DBEN6    : 1;            /*!< [6..6] Port n Debounce Enable 6                                           */
+        __IOM uint32_t DBEN7    : 1;            /*!< [7..7] Port n Debounce Enable 7                                           */
+        __IOM uint32_t DBEN8    : 1;            /*!< [8..8] Port n Debounce Enable 8                                           */
+        __IOM uint32_t DBEN9    : 1;            /*!< [9..9] Port n Debounce Enable 9                                           */
+        __IOM uint32_t DBEN10   : 1;            /*!< [10..10] Port n Debounce Enable 10                                        */
+        __IOM uint32_t DBEN11   : 1;            /*!< [11..11] Port n Debounce Enable 11                                        */
+        __IM  uint32_t          : 4;
+        __IOM uint32_t DBCLK    : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+      } DBCR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PE_DBCR;                   /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+      
+      struct {
+        __IOM uint32_t DBEN0    : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+        __IOM uint32_t DBEN1    : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+        __IOM uint32_t DBEN2    : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+        __IOM uint32_t DBEN3    : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+        __IM  uint32_t          : 12;
+        __IOM uint32_t DBCLK    : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+      } PE_DBCR_b;
+    } ;
+  };
+} PE_Type;                                      /*!< Size = 44 (0x2c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            PF                                             ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Port Control Unit & GPIO Port F (PF)
+  */
+
+typedef struct {                                /*!< (@ 0x30000500) PF Structure                                               */
+  
+  union {
+    union {
+      __IOM uint32_t MOD;                       /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+        __IOM uint32_t MODE12   : 2;            /*!< [25..24] Port n Mode Selection 12                                         */
+        __IOM uint32_t MODE13   : 2;            /*!< [27..26] Port n Mode Selection 13                                         */
+        __IOM uint32_t MODE14   : 2;            /*!< [29..28] Port n Mode Selection 14                                         */
+        __IOM uint32_t MODE15   : 2;            /*!< [31..30] Port n Mode Selection 15                                         */
+      } MOD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PF_MOD;                    /*!< (@ 0x00000000) Port n Mode Register                                       */
+      
+      struct {
+        __IOM uint32_t MODE0    : 2;            /*!< [1..0] Port n Mode Selection 0                                            */
+        __IOM uint32_t MODE1    : 2;            /*!< [3..2] Port n Mode Selection 1                                            */
+        __IOM uint32_t MODE2    : 2;            /*!< [5..4] Port n Mode Selection 2                                            */
+        __IOM uint32_t MODE3    : 2;            /*!< [7..6] Port n Mode Selection 3                                            */
+        __IOM uint32_t MODE4    : 2;            /*!< [9..8] Port n Mode Selection 4                                            */
+        __IOM uint32_t MODE5    : 2;            /*!< [11..10] Port n Mode Selection 5                                          */
+        __IOM uint32_t MODE6    : 2;            /*!< [13..12] Port n Mode Selection 6                                          */
+        __IOM uint32_t MODE7    : 2;            /*!< [15..14] Port n Mode Selection 7                                          */
+        __IOM uint32_t MODE8    : 2;            /*!< [17..16] Port n Mode Selection 8                                          */
+        __IOM uint32_t MODE9    : 2;            /*!< [19..18] Port n Mode Selection 9                                          */
+        __IOM uint32_t MODE10   : 2;            /*!< [21..20] Port n Mode Selection 10                                         */
+        __IOM uint32_t MODE11   : 2;            /*!< [23..22] Port n Mode Selection 11                                         */
+      } PF_MOD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t TYP;                       /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+        __IOM uint32_t TYP12    : 1;            /*!< [12..12] Port n Output Type Selection 12                                  */
+        __IOM uint32_t TYP13    : 1;            /*!< [13..13] Port n Output Type Selection 13                                  */
+        __IOM uint32_t TYP14    : 1;            /*!< [14..14] Port n Output Type Selection 14                                  */
+        __IOM uint32_t TYP15    : 1;            /*!< [15..15] Port n Output Type Selection 15                                  */
+      } TYP_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PF_TYP;                    /*!< (@ 0x00000004) Port n Output Type Selection Register                      */
+      
+      struct {
+        __IOM uint32_t TYP0     : 1;            /*!< [0..0] Port n Output Type Selection 0                                     */
+        __IOM uint32_t TYP1     : 1;            /*!< [1..1] Port n Output Type Selection 1                                     */
+        __IOM uint32_t TYP2     : 1;            /*!< [2..2] Port n Output Type Selection 2                                     */
+        __IOM uint32_t TYP3     : 1;            /*!< [3..3] Port n Output Type Selection 3                                     */
+        __IOM uint32_t TYP4     : 1;            /*!< [4..4] Port n Output Type Selection 4                                     */
+        __IOM uint32_t TYP5     : 1;            /*!< [5..5] Port n Output Type Selection 5                                     */
+        __IOM uint32_t TYP6     : 1;            /*!< [6..6] Port n Output Type Selection 6                                     */
+        __IOM uint32_t TYP7     : 1;            /*!< [7..7] Port n Output Type Selection 7                                     */
+        __IOM uint32_t TYP8     : 1;            /*!< [8..8] Port n Output Type Selection 8                                     */
+        __IOM uint32_t TYP9     : 1;            /*!< [9..9] Port n Output Type Selection 9                                     */
+        __IOM uint32_t TYP10    : 1;            /*!< [10..10] Port n Output Type Selection 10                                  */
+        __IOM uint32_t TYP11    : 1;            /*!< [11..11] Port n Output Type Selection 11                                  */
+      } PF_TYP_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR1;                     /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } AFSR1_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PF_AFSR1;                  /*!< (@ 0x00000008) Port n Alternative Function Selection Register
+                                                                    1                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR0    : 4;            /*!< [3..0] Port n Alternative Function Selection 0                            */
+        __IOM uint32_t AFSR1    : 4;            /*!< [7..4] Port n Alternative Function Selection 1                            */
+        __IOM uint32_t AFSR2    : 4;            /*!< [11..8] Port n Alternative Function Selection 2                           */
+        __IOM uint32_t AFSR3    : 4;            /*!< [15..12] Port n Alternative Function Selection 3                          */
+        __IOM uint32_t AFSR4    : 4;            /*!< [19..16] Port n Alternative Function Selection 4                          */
+        __IOM uint32_t AFSR5    : 4;            /*!< [23..20] Port n Alternative Function Selection 5                          */
+        __IOM uint32_t AFSR6    : 4;            /*!< [27..24] Port n Alternative Function Selection 6                          */
+        __IOM uint32_t AFSR7    : 4;            /*!< [31..28] Port n Alternative Function Selection 7                          */
+      } PF_AFSR1_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t AFSR2;                     /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+        __IOM uint32_t AFSR12   : 4;            /*!< [19..16] Port n Alternative Function Selection 12                         */
+        __IOM uint32_t AFSR13   : 4;            /*!< [23..20] Port n Alternative Function Selection 13                         */
+        __IOM uint32_t AFSR14   : 4;            /*!< [27..24] Port n Alternative Function Selection 14                         */
+        __IOM uint32_t AFSR15   : 4;            /*!< [31..28] Port n Alternative Function Selection 15                         */
+      } AFSR2_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PF_AFSR2;                  /*!< (@ 0x0000000C) Port n Alternative Function Selection Register
+                                                                    2                                                          */
+      
+      struct {
+        __IOM uint32_t AFSR8    : 4;            /*!< [3..0] Port n Alternative Function Selection 8                            */
+        __IOM uint32_t AFSR9    : 4;            /*!< [7..4] Port n Alternative Function Selection 9                            */
+        __IOM uint32_t AFSR10   : 4;            /*!< [11..8] Port n Alternative Function Selection 10                          */
+        __IOM uint32_t AFSR11   : 4;            /*!< [15..12] Port n Alternative Function Selection 11                         */
+      } PF_AFSR2_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t PUPD;                      /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+        __IOM uint32_t PUPD12   : 2;            /*!< [25..24] Port n Pull-Up/Down Resistor Selection 12                        */
+        __IOM uint32_t PUPD13   : 2;            /*!< [27..26] Port n Pull-Up/Down Resistor Selection 13                        */
+        __IOM uint32_t PUPD14   : 2;            /*!< [29..28] Port n Pull-Up/Down Resistor Selection 14                        */
+        __IOM uint32_t PUPD15   : 2;            /*!< [31..30] Port n Pull-Up/Down Resistor Selection 15                        */
+      } PUPD_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PF_PUPD;                   /*!< (@ 0x00000010) Port n Pull-Up/Down Resistor Selection Register            */
+      
+      struct {
+        __IOM uint32_t PUPD0    : 2;            /*!< [1..0] Port n Pull-Up/Down Resistor Selection 0                           */
+        __IOM uint32_t PUPD1    : 2;            /*!< [3..2] Port n Pull-Up/Down Resistor Selection 1                           */
+        __IOM uint32_t PUPD2    : 2;            /*!< [5..4] Port n Pull-Up/Down Resistor Selection 2                           */
+        __IOM uint32_t PUPD3    : 2;            /*!< [7..6] Port n Pull-Up/Down Resistor Selection 3                           */
+        __IOM uint32_t PUPD4    : 2;            /*!< [9..8] Port n Pull-Up/Down Resistor Selection 4                           */
+        __IOM uint32_t PUPD5    : 2;            /*!< [11..10] Port n Pull-Up/Down Resistor Selection 5                         */
+        __IOM uint32_t PUPD6    : 2;            /*!< [13..12] Port n Pull-Up/Down Resistor Selection 6                         */
+        __IOM uint32_t PUPD7    : 2;            /*!< [15..14] Port n Pull-Up/Down Resistor Selection 7                         */
+        __IOM uint32_t PUPD8    : 2;            /*!< [17..16] Port n Pull-Up/Down Resistor Selection 8                         */
+        __IOM uint32_t PUPD9    : 2;            /*!< [19..18] Port n Pull-Up/Down Resistor Selection 9                         */
+        __IOM uint32_t PUPD10   : 2;            /*!< [21..20] Port n Pull-Up/Down Resistor Selection 10                        */
+        __IOM uint32_t PUPD11   : 2;            /*!< [23..22] Port n Pull-Up/Down Resistor Selection 11                        */
+      } PF_PUPD_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IM  uint32_t INDR;                      /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+        __IM  uint32_t INDR12   : 1;            /*!< [12..12] Port n Input Data 12                                             */
+        __IM  uint32_t INDR13   : 1;            /*!< [13..13] Port n Input Data 13                                             */
+        __IM  uint32_t INDR14   : 1;            /*!< [14..14] Port n Input Data 14                                             */
+        __IM  uint32_t INDR15   : 1;            /*!< [15..15] Port n Input Data 15                                             */
+      } INDR_b;
+    } ;
+    
+    union {
+      __IM  uint32_t PF_INDR;                   /*!< (@ 0x00000014) Port n Input Data Register                                 */
+      
+      struct {
+        __IM  uint32_t INDR0    : 1;            /*!< [0..0] Port n Input Data 0                                                */
+        __IM  uint32_t INDR1    : 1;            /*!< [1..1] Port n Input Data 1                                                */
+        __IM  uint32_t INDR2    : 1;            /*!< [2..2] Port n Input Data 2                                                */
+        __IM  uint32_t INDR3    : 1;            /*!< [3..3] Port n Input Data 3                                                */
+        __IM  uint32_t INDR4    : 1;            /*!< [4..4] Port n Input Data 4                                                */
+        __IM  uint32_t INDR5    : 1;            /*!< [5..5] Port n Input Data 5                                                */
+        __IM  uint32_t INDR6    : 1;            /*!< [6..6] Port n Input Data 6                                                */
+        __IM  uint32_t INDR7    : 1;            /*!< [7..7] Port n Input Data 7                                                */
+        __IM  uint32_t INDR8    : 1;            /*!< [8..8] Port n Input Data 8                                                */
+        __IM  uint32_t INDR9    : 1;            /*!< [9..9] Port n Input Data 9                                                */
+        __IM  uint32_t INDR10   : 1;            /*!< [10..10] Port n Input Data 10                                             */
+        __IM  uint32_t INDR11   : 1;            /*!< [11..11] Port n Input Data 11                                             */
+      } PF_INDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDR;                     /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+        __IOM uint32_t OUTDR12  : 1;            /*!< [12..12] Port n Output Data 12                                            */
+        __IOM uint32_t OUTDR13  : 1;            /*!< [13..13] Port n Output Data 13                                            */
+        __IOM uint32_t OUTDR14  : 1;            /*!< [14..14] Port n Output Data 14                                            */
+        __IOM uint32_t OUTDR15  : 1;            /*!< [15..15] Port n Output Data 15                                            */
+      } OUTDR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PF_OUTDR;                  /*!< (@ 0x00000018) Port n Output Data Register                                */
+      
+      struct {
+        __IOM uint32_t OUTDR0   : 1;            /*!< [0..0] Port n Output Data 0                                               */
+        __IOM uint32_t OUTDR1   : 1;            /*!< [1..1] Port n Output Data 1                                               */
+        __IOM uint32_t OUTDR2   : 1;            /*!< [2..2] Port n Output Data 2                                               */
+        __IOM uint32_t OUTDR3   : 1;            /*!< [3..3] Port n Output Data 3                                               */
+        __IOM uint32_t OUTDR4   : 1;            /*!< [4..4] Port n Output Data 4                                               */
+        __IOM uint32_t OUTDR5   : 1;            /*!< [5..5] Port n Output Data 5                                               */
+        __IOM uint32_t OUTDR6   : 1;            /*!< [6..6] Port n Output Data 6                                               */
+        __IOM uint32_t OUTDR7   : 1;            /*!< [7..7] Port n Output Data 7                                               */
+        __IOM uint32_t OUTDR8   : 1;            /*!< [8..8] Port n Output Data 8                                               */
+        __IOM uint32_t OUTDR9   : 1;            /*!< [9..9] Port n Output Data 9                                               */
+        __IOM uint32_t OUTDR10  : 1;            /*!< [10..10] Port n Output Data 10                                            */
+        __IOM uint32_t OUTDR11  : 1;            /*!< [11..11] Port n Output Data 11                                            */
+      } PF_OUTDR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BSR;                       /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+        __OM  uint32_t BSR12    : 1;            /*!< [12..12] Port n Output Bit Set 12                                         */
+        __OM  uint32_t BSR13    : 1;            /*!< [13..13] Port n Output Bit Set 13                                         */
+        __OM  uint32_t BSR14    : 1;            /*!< [14..14] Port n Output Bit Set 14                                         */
+        __OM  uint32_t BSR15    : 1;            /*!< [15..15] Port n Output Bit Set 15                                         */
+      } BSR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PF_BSR;                    /*!< (@ 0x0000001C) Port n Output Bit Set Register                             */
+      
+      struct {
+        __OM  uint32_t BSR0     : 1;            /*!< [0..0] Port n Output Bit Set 0                                            */
+        __OM  uint32_t BSR1     : 1;            /*!< [1..1] Port n Output Bit Set 1                                            */
+        __OM  uint32_t BSR2     : 1;            /*!< [2..2] Port n Output Bit Set 2                                            */
+        __OM  uint32_t BSR3     : 1;            /*!< [3..3] Port n Output Bit Set 3                                            */
+        __OM  uint32_t BSR4     : 1;            /*!< [4..4] Port n Output Bit Set 4                                            */
+        __OM  uint32_t BSR5     : 1;            /*!< [5..5] Port n Output Bit Set 5                                            */
+        __OM  uint32_t BSR6     : 1;            /*!< [6..6] Port n Output Bit Set 6                                            */
+        __OM  uint32_t BSR7     : 1;            /*!< [7..7] Port n Output Bit Set 7                                            */
+        __OM  uint32_t BSR8     : 1;            /*!< [8..8] Port n Output Bit Set 8                                            */
+        __OM  uint32_t BSR9     : 1;            /*!< [9..9] Port n Output Bit Set 9                                            */
+        __OM  uint32_t BSR10    : 1;            /*!< [10..10] Port n Output Bit Set 10                                         */
+        __OM  uint32_t BSR11    : 1;            /*!< [11..11] Port n Output Bit Set 11                                         */
+      } PF_BSR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __OM  uint32_t BCR;                       /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+        __OM  uint32_t BCR12    : 1;            /*!< [12..12] Port n Output Bit Clear 12                                       */
+        __OM  uint32_t BCR13    : 1;            /*!< [13..13] Port n Output Bit Clear 13                                       */
+        __OM  uint32_t BCR14    : 1;            /*!< [14..14] Port n Output Bit Clear 14                                       */
+        __OM  uint32_t BCR15    : 1;            /*!< [15..15] Port n Output Bit Clear 15                                       */
+      } BCR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t PF_BCR;                    /*!< (@ 0x00000020) Port n Output Bit Clear Register                           */
+      
+      struct {
+        __OM  uint32_t BCR0     : 1;            /*!< [0..0] Port n Output Bit Clear 0                                          */
+        __OM  uint32_t BCR1     : 1;            /*!< [1..1] Port n Output Bit Clear 1                                          */
+        __OM  uint32_t BCR2     : 1;            /*!< [2..2] Port n Output Bit Clear 2                                          */
+        __OM  uint32_t BCR3     : 1;            /*!< [3..3] Port n Output Bit Clear 3                                          */
+        __OM  uint32_t BCR4     : 1;            /*!< [4..4] Port n Output Bit Clear 4                                          */
+        __OM  uint32_t BCR5     : 1;            /*!< [5..5] Port n Output Bit Clear 5                                          */
+        __OM  uint32_t BCR6     : 1;            /*!< [6..6] Port n Output Bit Clear 6                                          */
+        __OM  uint32_t BCR7     : 1;            /*!< [7..7] Port n Output Bit Clear 7                                          */
+        __OM  uint32_t BCR8     : 1;            /*!< [8..8] Port n Output Bit Clear 8                                          */
+        __OM  uint32_t BCR9     : 1;            /*!< [9..9] Port n Output Bit Clear 9                                          */
+        __OM  uint32_t BCR10    : 1;            /*!< [10..10] Port n Output Bit Clear 10                                       */
+        __OM  uint32_t BCR11    : 1;            /*!< [11..11] Port n Output Bit Clear 11                                       */
+      } PF_BCR_b;
+    } ;
+  };
+  
+  union {
+    union {
+      __IOM uint32_t OUTDMSK;                   /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+        __IOM uint32_t OUTDMSK12 : 1;           /*!< [12..12] Port n Output Data Mask 12                                       */
+        __IOM uint32_t OUTDMSK13 : 1;           /*!< [13..13] Port n Output Data Mask 13                                       */
+        __IOM uint32_t OUTDMSK14 : 1;           /*!< [14..14] Port n Output Data Mask 14                                       */
+        __IOM uint32_t OUTDMSK15 : 1;           /*!< [15..15] Port n Output Data Mask 15                                       */
+      } OUTDMSK_b;
+    } ;
+    
+    union {
+      __IOM uint32_t PF_OUTDMSK;                /*!< (@ 0x00000024) Port n Output Data Mask Register                           */
+      
+      struct {
+        __IOM uint32_t OUTDMSK0 : 1;            /*!< [0..0] Port n Output Data Mask 0                                          */
+        __IOM uint32_t OUTDMSK1 : 1;            /*!< [1..1] Port n Output Data Mask 1                                          */
+        __IOM uint32_t OUTDMSK2 : 1;            /*!< [2..2] Port n Output Data Mask 2                                          */
+        __IOM uint32_t OUTDMSK3 : 1;            /*!< [3..3] Port n Output Data Mask 3                                          */
+        __IOM uint32_t OUTDMSK4 : 1;            /*!< [4..4] Port n Output Data Mask 4                                          */
+        __IOM uint32_t OUTDMSK5 : 1;            /*!< [5..5] Port n Output Data Mask 5                                          */
+        __IOM uint32_t OUTDMSK6 : 1;            /*!< [6..6] Port n Output Data Mask 6                                          */
+        __IOM uint32_t OUTDMSK7 : 1;            /*!< [7..7] Port n Output Data Mask 7                                          */
+        __IOM uint32_t OUTDMSK8 : 1;            /*!< [8..8] Port n Output Data Mask 8                                          */
+        __IOM uint32_t OUTDMSK9 : 1;            /*!< [9..9] Port n Output Data Mask 9                                          */
+        __IOM uint32_t OUTDMSK10 : 1;           /*!< [10..10] Port n Output Data Mask 10                                       */
+        __IOM uint32_t OUTDMSK11 : 1;           /*!< [11..11] Port n Output Data Mask 11                                       */
+      } PF_OUTDMSK_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t DBCR;                        /*!< (@ 0x00000028) Port n Debounce Control Register                           */
+    
+    struct {
+      __IOM uint32_t DBEN0      : 1;            /*!< [0..0] Port n Debounce Enable 0                                           */
+      __IOM uint32_t DBEN1      : 1;            /*!< [1..1] Port n Debounce Enable 1                                           */
+      __IOM uint32_t DBEN2      : 1;            /*!< [2..2] Port n Debounce Enable 2                                           */
+      __IOM uint32_t DBEN3      : 1;            /*!< [3..3] Port n Debounce Enable 3                                           */
+      __IOM uint32_t DBEN4      : 1;            /*!< [4..4] Port n Debounce Enable 4                                           */
+      __IOM uint32_t DBEN5      : 1;            /*!< [5..5] Port n Debounce Enable 5                                           */
+      __IOM uint32_t DBEN6      : 1;            /*!< [6..6] Port n Debounce Enable 6                                           */
+      __IOM uint32_t DBEN7      : 1;            /*!< [7..7] Port n Debounce Enable 7                                           */
+      __IOM uint32_t DBEN8      : 1;            /*!< [8..8] Port n Debounce Enable 8                                           */
+      __IOM uint32_t DBEN9      : 1;            /*!< [9..9] Port n Debounce Enable 9                                           */
+      __IOM uint32_t DBEN10     : 1;            /*!< [10..10] Port n Debounce Enable 10                                        */
+      __IOM uint32_t DBEN11     : 1;            /*!< [11..11] Port n Debounce Enable 11                                        */
+      __IM  uint32_t            : 4;
+      __IOM uint32_t DBCLK      : 3;            /*!< [18..16] Port n Debounce Filter Sampling Clock Selection                  */
+    } DBCR_b;
+  } ;
+} PF_Type;                                      /*!< Size = 44 (0x2c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            FMC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Flash Memory Controller (FMC)
+  */
+
+typedef struct {                                /*!< (@ 0x40001B00) FMC Structure                                              */
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000000) Flash Memory Address Register                              */
+    
+    struct {
+      __IOM uint32_t ADDR       : 32;           /*!< [31..0] Flash Memory Address Pointer                                      */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t IDR1;                        /*!< (@ 0x00000004) Flash Memory Identification Register 1                     */
+    
+    struct {
+      __IOM uint32_t ID1        : 32;           /*!< [31..0] Flash Memory Identification 1                                     */
+    } IDR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t IDR2;                        /*!< (@ 0x00000008) Flash Memory Identification Register 2                     */
+    
+    struct {
+      __IOM uint32_t ID2        : 32;           /*!< [31..0] Flash Memory Identification 2                                     */
+    } IDR2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x0000000C) Flash Memory Control Register                              */
+    
+    struct {
+      __IOM uint32_t FMOD       : 4;            /*!< [3..0] Flash Memory Operation Mode Selection                              */
+      __IM  uint32_t            : 3;
+      __IM  uint32_t FMBUSY     : 1;            /*!< [7..7] Flash Memory Operation Mode Busy                                   */
+      __IOM uint32_t FMKEY      : 8;            /*!< [15..8] Flash Memory Operation Area Selection                             */
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0x6c93)                                */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BCR;                         /*!< (@ 0x00000010) Flash Memory Configure Area Bulk Erase Control
+                                                                    Register                                                   */
+    
+    struct {
+      __IOM uint32_t CNF1BEN    : 4;            /*!< [3..0] Configure Option Page 1 Bulk Erase Enable                          */
+      __IOM uint32_t CNF2BEN    : 4;            /*!< [7..4] Configure Option Page 2 Bulk Erase Enable                          */
+      __IOM uint32_t CNF3BEN    : 4;            /*!< [11..8] Configure Option Page 3 Bulk Erase Enable                         */
+      __IM  uint32_t            : 4;
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0xc1be)                                */
+    } BCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ERFLAG;                      /*!< (@ 0x00000014) Flash Memory Error Flag                                    */
+    
+    struct {
+      __IOM uint32_t FMOPFLAG   : 1;            /*!< [0..0] Error bit of Flash Memory Operation Procedure                      */
+      __IOM uint32_t INSTFLAG   : 1;            /*!< [1..1] Don't care                                                         */
+    } ERFLAG_b;
+  } ;
+  __IM  uint32_t  RESERVED[58];
+  __OM  uint32_t  PAGEBUF;                      /*!< (@ 0x00000100) Flash Memory Page Buffer Area (128bytes/Accessed
+                                                                    by 32bit Word Only)                                        */
+} FMC_Type;                                     /*!< Size = 260 (0x104)                                                        */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            WDT                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Watch-Dog Timer (WDT)
+  */
+
+typedef struct {                                /*!< (@ 0x40001A00) WDT Structure                                              */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Watch-Dog Timer Control Register                           */
+    
+    struct {
+      __IOM uint32_t CLKDIV     : 2;            /*!< [1..0] Watch-Dog Timer Clock Divider                                      */
+      __IOM uint32_t UNFIEN     : 1;            /*!< [2..2] Watch-Dog Timer Underflow Interrupt Enable                         */
+      __IOM uint32_t WINMIEN    : 1;            /*!< [3..3] Watch-Dog Timer Window Match Interrupt Enable                      */
+      __IOM uint32_t CNTEN      : 6;            /*!< [9..4] Watch-Dog Timer Counter Enable                                     */
+      __IOM uint32_t RSTEN      : 6;            /*!< [15..10] Watch-Dog Timer Reset Enable                                     */
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key (0x5a69)                                */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SR;                          /*!< (@ 0x00000004) Watch-Dog Timer Status Register                            */
+    
+    struct {
+      __IOM uint32_t UNFIFLAG   : 1;            /*!< [0..0] Watch-Dog Timer Underflow Interrupt Flag                           */
+      __IOM uint32_t WINMIFLAG  : 1;            /*!< [1..1] Watch-Dog Timer Window Match Interrupt Flag                        */
+      __IM  uint32_t            : 5;
+      __IOM uint32_t DBGCNTEN   : 1;            /*!< [7..7] Watch-Dog Timer Counter Enable when the core is halted
+                                                     in debug mode                                                             */
+    } SR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000008) Watch-Dog Timer Data Register                              */
+    
+    struct {
+      __IOM uint32_t DATA       : 24;           /*!< [23..0] Watch-Dog Timer Data                                              */
+    } DR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x0000000C) Watch-Dog Timer Counter Register                           */
+    
+    struct {
+      __IM  uint32_t CNT        : 24;           /*!< [23..0] Watch-Dog Timer Counter                                           */
+    } CNT_b;
+  } ;
+  
+  union {
+    __IOM uint32_t WINDR;                       /*!< (@ 0x00000010) Watch-Dog Timer Window Data Register                       */
+    
+    struct {
+      __IOM uint32_t WDATA      : 24;           /*!< [23..0] Watch-Dog Timer Window Data                                       */
+    } WINDR_b;
+  } ;
+  
+  union {
+    __OM  uint32_t CNTR;                        /*!< (@ 0x00000014) Watch-Dog Timer Counter Reload Register                    */
+    
+    struct {
+      __OM  uint32_t CNTR       : 8;            /*!< [7..0] Watch-Dog Timer Counter Reload                                     */
+    } CNTR_b;
+  } ;
+} WDT_Type;                                     /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            WT                                             ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Watch Timer (WT)
+  */
+
+typedef struct {                                /*!< (@ 0x40002000) WT Structure                                               */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Watch Timer Control Register                               */
+    
+    struct {
+      __IOM uint32_t WTCLR      : 1;            /*!< [0..0] Watch Timer Counter and Divider Clear                              */
+      __IOM uint32_t WTIFLAG    : 1;            /*!< [1..1] Watch Timer Interrupt Flag                                         */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t WTIEN      : 1;            /*!< [3..3] Watch Timer Interrupt Enable                                       */
+      __IOM uint32_t WTINTV     : 2;            /*!< [5..4] Watch Timer Interval Selection                                     */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t WTEN       : 1;            /*!< [7..7] Watch Timer Operation Enable                                       */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000004) Watch Timer Data Register                                  */
+    
+    struct {
+      __IOM uint32_t WTDATA     : 12;           /*!< [11..0] Watch Timer Data                                                  */
+    } DR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000008) Watch Timer Counter Register                               */
+    
+    struct {
+      __IM  uint32_t CNT        : 12;           /*!< [11..0] Watch Timer Counter                                               */
+    } CNT_b;
+  } ;
+} WT_Type;                                      /*!< Size = 12 (0xc)                                                           */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER1n                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 1n (TIMER1n)
+  */
+
+typedef struct {                                /*!< (@ 0x51000000) TIMER1n Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER1n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T1nCLR     : 1;            /*!< [0..0] TIMER1n Counter and Prescaler Clear                                */
+      __IOM uint32_t T1nPAU     : 1;            /*!< [1..1] TIMER1n Counter Temporary Pause Control                            */
+      __IOM uint32_t T1nCIFLAG  : 1;            /*!< [2..2] TIMER1n Capture Interrupt Flag                                     */
+      __IOM uint32_t T1nMIFLAG  : 1;            /*!< [3..3] TIMER1n Match Interrupt Flag                                       */
+      __IOM uint32_t T1nCIEN    : 1;            /*!< [4..4] TIMER1n Capture Interrupt Enable                                   */
+      __IOM uint32_t T1nMIEN    : 1;            /*!< [5..5] TIMER1n Match Interrupt Enable                                     */
+      __IOM uint32_t T1nCPOL    : 2;            /*!< [7..6] TIMER1n Capture Polarity Selection                                 */
+      __IOM uint32_t T1nOPOL    : 1;            /*!< [8..8] TIMER1n Output Polarity Selection                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T1nECE     : 1;            /*!< [11..11] TIMER1n External Clock Edge Selection                            */
+      __IOM uint32_t T1nMS      : 2;            /*!< [13..12] TIMER1n Operation Mode Selection                                 */
+      __IOM uint32_t T1nCLK     : 1;            /*!< [14..14] TIMER1n Clock Selection                                          */
+      __IOM uint32_t T1nEN      : 1;            /*!< [15..15] TIMER1n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER1n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER1n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER1n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER1n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER1n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER1n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER1n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER1n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER1n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER1n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER1n_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER10                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 10 (TIMER10)
+  */
+
+typedef struct {                                /*!< (@ 0x40002100) TIMER10 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER1n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T1nCLR     : 1;            /*!< [0..0] TIMER1n Counter and Prescaler Clear                                */
+      __IOM uint32_t T1nPAU     : 1;            /*!< [1..1] TIMER1n Counter Temporary Pause Control                            */
+      __IOM uint32_t T1nCIFLAG  : 1;            /*!< [2..2] TIMER1n Capture Interrupt Flag                                     */
+      __IOM uint32_t T1nMIFLAG  : 1;            /*!< [3..3] TIMER1n Match Interrupt Flag                                       */
+      __IOM uint32_t T1nCIEN    : 1;            /*!< [4..4] TIMER1n Capture Interrupt Enable                                   */
+      __IOM uint32_t T1nMIEN    : 1;            /*!< [5..5] TIMER1n Match Interrupt Enable                                     */
+      __IOM uint32_t T1nCPOL    : 2;            /*!< [7..6] TIMER1n Capture Polarity Selection                                 */
+      __IOM uint32_t T1nOPOL    : 1;            /*!< [8..8] TIMER1n Output Polarity Selection                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T1nECE     : 1;            /*!< [11..11] TIMER1n External Clock Edge Selection                            */
+      __IOM uint32_t T1nMS      : 2;            /*!< [13..12] TIMER1n Operation Mode Selection                                 */
+      __IOM uint32_t T1nCLK     : 1;            /*!< [14..14] TIMER1n Clock Selection                                          */
+      __IOM uint32_t T1nEN      : 1;            /*!< [15..15] TIMER1n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER1n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER1n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER1n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER1n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER1n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER1n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER1n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER1n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER1n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER1n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER10_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER11                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 11 (TIMER11)
+  */
+
+typedef struct {                                /*!< (@ 0x40002200) TIMER11 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER1n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T1nCLR     : 1;            /*!< [0..0] TIMER1n Counter and Prescaler Clear                                */
+      __IOM uint32_t T1nPAU     : 1;            /*!< [1..1] TIMER1n Counter Temporary Pause Control                            */
+      __IOM uint32_t T1nCIFLAG  : 1;            /*!< [2..2] TIMER1n Capture Interrupt Flag                                     */
+      __IOM uint32_t T1nMIFLAG  : 1;            /*!< [3..3] TIMER1n Match Interrupt Flag                                       */
+      __IOM uint32_t T1nCIEN    : 1;            /*!< [4..4] TIMER1n Capture Interrupt Enable                                   */
+      __IOM uint32_t T1nMIEN    : 1;            /*!< [5..5] TIMER1n Match Interrupt Enable                                     */
+      __IOM uint32_t T1nCPOL    : 2;            /*!< [7..6] TIMER1n Capture Polarity Selection                                 */
+      __IOM uint32_t T1nOPOL    : 1;            /*!< [8..8] TIMER1n Output Polarity Selection                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T1nECE     : 1;            /*!< [11..11] TIMER1n External Clock Edge Selection                            */
+      __IOM uint32_t T1nMS      : 2;            /*!< [13..12] TIMER1n Operation Mode Selection                                 */
+      __IOM uint32_t T1nCLK     : 1;            /*!< [14..14] TIMER1n Clock Selection                                          */
+      __IOM uint32_t T1nEN      : 1;            /*!< [15..15] TIMER1n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER1n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER1n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER1n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER1n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER1n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER1n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER1n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER1n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER1n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER1n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER11_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER12                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 12 (TIMER12)
+  */
+
+typedef struct {                                /*!< (@ 0x40002300) TIMER12 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER1n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T1nCLR     : 1;            /*!< [0..0] TIMER1n Counter and Prescaler Clear                                */
+      __IOM uint32_t T1nPAU     : 1;            /*!< [1..1] TIMER1n Counter Temporary Pause Control                            */
+      __IOM uint32_t T1nCIFLAG  : 1;            /*!< [2..2] TIMER1n Capture Interrupt Flag                                     */
+      __IOM uint32_t T1nMIFLAG  : 1;            /*!< [3..3] TIMER1n Match Interrupt Flag                                       */
+      __IOM uint32_t T1nCIEN    : 1;            /*!< [4..4] TIMER1n Capture Interrupt Enable                                   */
+      __IOM uint32_t T1nMIEN    : 1;            /*!< [5..5] TIMER1n Match Interrupt Enable                                     */
+      __IOM uint32_t T1nCPOL    : 2;            /*!< [7..6] TIMER1n Capture Polarity Selection                                 */
+      __IOM uint32_t T1nOPOL    : 1;            /*!< [8..8] TIMER1n Output Polarity Selection                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T1nECE     : 1;            /*!< [11..11] TIMER1n External Clock Edge Selection                            */
+      __IOM uint32_t T1nMS      : 2;            /*!< [13..12] TIMER1n Operation Mode Selection                                 */
+      __IOM uint32_t T1nCLK     : 1;            /*!< [14..14] TIMER1n Clock Selection                                          */
+      __IOM uint32_t T1nEN      : 1;            /*!< [15..15] TIMER1n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER1n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER1n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER1n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER1n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER1n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER1n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER1n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER1n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER1n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER1n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER12_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER13                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 13 (TIMER13)
+  */
+
+typedef struct {                                /*!< (@ 0x40002700) TIMER13 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER1n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T1nCLR     : 1;            /*!< [0..0] TIMER1n Counter and Prescaler Clear                                */
+      __IOM uint32_t T1nPAU     : 1;            /*!< [1..1] TIMER1n Counter Temporary Pause Control                            */
+      __IOM uint32_t T1nCIFLAG  : 1;            /*!< [2..2] TIMER1n Capture Interrupt Flag                                     */
+      __IOM uint32_t T1nMIFLAG  : 1;            /*!< [3..3] TIMER1n Match Interrupt Flag                                       */
+      __IOM uint32_t T1nCIEN    : 1;            /*!< [4..4] TIMER1n Capture Interrupt Enable                                   */
+      __IOM uint32_t T1nMIEN    : 1;            /*!< [5..5] TIMER1n Match Interrupt Enable                                     */
+      __IOM uint32_t T1nCPOL    : 2;            /*!< [7..6] TIMER1n Capture Polarity Selection                                 */
+      __IOM uint32_t T1nOPOL    : 1;            /*!< [8..8] TIMER1n Output Polarity Selection                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T1nECE     : 1;            /*!< [11..11] TIMER1n External Clock Edge Selection                            */
+      __IOM uint32_t T1nMS      : 2;            /*!< [13..12] TIMER1n Operation Mode Selection                                 */
+      __IOM uint32_t T1nCLK     : 1;            /*!< [14..14] TIMER1n Clock Selection                                          */
+      __IOM uint32_t T1nEN      : 1;            /*!< [15..15] TIMER1n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER1n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER1n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER1n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER1n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER1n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER1n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER1n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER1n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER1n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER1n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER13_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER14                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 14 (TIMER14)
+  */
+
+typedef struct {                                /*!< (@ 0x40002800) TIMER14 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER1n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T1nCLR     : 1;            /*!< [0..0] TIMER1n Counter and Prescaler Clear                                */
+      __IOM uint32_t T1nPAU     : 1;            /*!< [1..1] TIMER1n Counter Temporary Pause Control                            */
+      __IOM uint32_t T1nCIFLAG  : 1;            /*!< [2..2] TIMER1n Capture Interrupt Flag                                     */
+      __IOM uint32_t T1nMIFLAG  : 1;            /*!< [3..3] TIMER1n Match Interrupt Flag                                       */
+      __IOM uint32_t T1nCIEN    : 1;            /*!< [4..4] TIMER1n Capture Interrupt Enable                                   */
+      __IOM uint32_t T1nMIEN    : 1;            /*!< [5..5] TIMER1n Match Interrupt Enable                                     */
+      __IOM uint32_t T1nCPOL    : 2;            /*!< [7..6] TIMER1n Capture Polarity Selection                                 */
+      __IOM uint32_t T1nOPOL    : 1;            /*!< [8..8] TIMER1n Output Polarity Selection                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T1nECE     : 1;            /*!< [11..11] TIMER1n External Clock Edge Selection                            */
+      __IOM uint32_t T1nMS      : 2;            /*!< [13..12] TIMER1n Operation Mode Selection                                 */
+      __IOM uint32_t T1nCLK     : 1;            /*!< [14..14] TIMER1n Clock Selection                                          */
+      __IOM uint32_t T1nEN      : 1;            /*!< [15..15] TIMER1n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER1n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER1n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER1n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER1n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER1n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER1n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER1n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER1n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER1n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER1n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER14_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER15                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 15 (TIMER15)
+  */
+
+typedef struct {                                /*!< (@ 0x40002900) TIMER15 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER1n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T1nCLR     : 1;            /*!< [0..0] TIMER1n Counter and Prescaler Clear                                */
+      __IOM uint32_t T1nPAU     : 1;            /*!< [1..1] TIMER1n Counter Temporary Pause Control                            */
+      __IOM uint32_t T1nCIFLAG  : 1;            /*!< [2..2] TIMER1n Capture Interrupt Flag                                     */
+      __IOM uint32_t T1nMIFLAG  : 1;            /*!< [3..3] TIMER1n Match Interrupt Flag                                       */
+      __IOM uint32_t T1nCIEN    : 1;            /*!< [4..4] TIMER1n Capture Interrupt Enable                                   */
+      __IOM uint32_t T1nMIEN    : 1;            /*!< [5..5] TIMER1n Match Interrupt Enable                                     */
+      __IOM uint32_t T1nCPOL    : 2;            /*!< [7..6] TIMER1n Capture Polarity Selection                                 */
+      __IOM uint32_t T1nOPOL    : 1;            /*!< [8..8] TIMER1n Output Polarity Selection                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T1nECE     : 1;            /*!< [11..11] TIMER1n External Clock Edge Selection                            */
+      __IOM uint32_t T1nMS      : 2;            /*!< [13..12] TIMER1n Operation Mode Selection                                 */
+      __IOM uint32_t T1nCLK     : 1;            /*!< [14..14] TIMER1n Clock Selection                                          */
+      __IOM uint32_t T1nEN      : 1;            /*!< [15..15] TIMER1n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER1n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER1n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER1n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER1n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER1n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER1n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER1n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER1n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER1n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER1n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER15_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER16                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 16 (TIMER16)
+  */
+
+typedef struct {                                /*!< (@ 0x40002A00) TIMER16 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER1n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T1nCLR     : 1;            /*!< [0..0] TIMER1n Counter and Prescaler Clear                                */
+      __IOM uint32_t T1nPAU     : 1;            /*!< [1..1] TIMER1n Counter Temporary Pause Control                            */
+      __IOM uint32_t T1nCIFLAG  : 1;            /*!< [2..2] TIMER1n Capture Interrupt Flag                                     */
+      __IOM uint32_t T1nMIFLAG  : 1;            /*!< [3..3] TIMER1n Match Interrupt Flag                                       */
+      __IOM uint32_t T1nCIEN    : 1;            /*!< [4..4] TIMER1n Capture Interrupt Enable                                   */
+      __IOM uint32_t T1nMIEN    : 1;            /*!< [5..5] TIMER1n Match Interrupt Enable                                     */
+      __IOM uint32_t T1nCPOL    : 2;            /*!< [7..6] TIMER1n Capture Polarity Selection                                 */
+      __IOM uint32_t T1nOPOL    : 1;            /*!< [8..8] TIMER1n Output Polarity Selection                                  */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t T1nECE     : 1;            /*!< [11..11] TIMER1n External Clock Edge Selection                            */
+      __IOM uint32_t T1nMS      : 2;            /*!< [13..12] TIMER1n Operation Mode Selection                                 */
+      __IOM uint32_t T1nCLK     : 1;            /*!< [14..14] TIMER1n Clock Selection                                          */
+      __IOM uint32_t T1nEN      : 1;            /*!< [15..15] TIMER1n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER1n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER1n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER1n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER1n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER1n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER1n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER1n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER1n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER1n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER1n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER16_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER2n                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 2n (TIMER2n)
+  */
+
+typedef struct {                                /*!< (@ 0x52000000) TIMER2n Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER2n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T2nCLR     : 1;            /*!< [0..0] TIMER2n Counter and Prescaler Clear                                */
+      __IOM uint32_t T2nPAU     : 1;            /*!< [1..1] TIMER2n Counter Temporary Pause Control                            */
+      __IOM uint32_t T2nCIFLAG  : 1;            /*!< [2..2] TIMER2n Capture Interrupt Flag                                     */
+      __IOM uint32_t T2nMIFLAG  : 1;            /*!< [3..3] TIMER2n Match Interrupt Flag                                       */
+      __IOM uint32_t T2nCIEN    : 1;            /*!< [4..4] TIMER2n Capture Interrupt Enable                                   */
+      __IOM uint32_t T2nMIEN    : 1;            /*!< [5..5] TIMER2n Match Interrupt Enable                                     */
+      __IOM uint32_t T2nCPOL    : 2;            /*!< [7..6] TIMER2n Capture Polarity Selection                                 */
+      __IOM uint32_t T2nOPOL    : 1;            /*!< [8..8] TIMER2n Output Polarity Selection                                  */
+      __IOM uint32_t CAPSEL     : 2;            /*!< [10..9] TIMER2n Capture Signal Selection                                  */
+      __IOM uint32_t T2nECE     : 1;            /*!< [11..11] TIMER2n External Clock Edge Selection                            */
+      __IOM uint32_t T2nMS      : 2;            /*!< [13..12] TIMER2n Operation Mode Selection                                 */
+      __IOM uint32_t T2nCLK     : 1;            /*!< [14..14] TIMER2n Clock Selection                                          */
+      __IOM uint32_t T2nEN      : 1;            /*!< [15..15] TIMER2n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER2n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 32;           /*!< [31..0] TIMER2n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER2n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 32;           /*!< [31..0] TIMER2n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER2n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 32;           /*!< [31..0] TIMER2n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER2n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER2n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER2n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 32;           /*!< [31..0] TIMER2n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER2n_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER20                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 20 (TIMER20)
+  */
+
+typedef struct {                                /*!< (@ 0x40002500) TIMER20 Structure                                          */
+  
+  union {
+    union {
+      __IOM uint32_t CR;                        /*!< (@ 0x00000000) TIMER2n Control Register                                   */
+      
+      struct {
+        __IOM uint32_t T2nCLR   : 1;            /*!< [0..0] TIMER2n Counter and Prescaler Clear                                */
+        __IOM uint32_t T2nPAU   : 1;            /*!< [1..1] TIMER2n Counter Temporary Pause Control                            */
+        __IOM uint32_t T2nCIFLAG : 1;           /*!< [2..2] TIMER2n Capture Interrupt Flag                                     */
+        __IOM uint32_t T2nMIFLAG : 1;           /*!< [3..3] TIMER2n Match Interrupt Flag                                       */
+        __IOM uint32_t T2nCIEN  : 1;            /*!< [4..4] TIMER2n Capture Interrupt Enable                                   */
+        __IOM uint32_t T2nMIEN  : 1;            /*!< [5..5] TIMER2n Match Interrupt Enable                                     */
+        __IOM uint32_t T2nCPOL  : 2;            /*!< [7..6] TIMER2n Capture Polarity Selection                                 */
+        __IOM uint32_t T2nOPOL  : 1;            /*!< [8..8] TIMER2n Output Polarity Selection                                  */
+        __IOM uint32_t CAPSEL   : 2;            /*!< [10..9] TIMER2n Capture Signal Selection                                  */
+        __IOM uint32_t T2nECE   : 1;            /*!< [11..11] TIMER2n External Clock Edge Selection                            */
+        __IOM uint32_t T2nMS    : 2;            /*!< [13..12] TIMER2n Operation Mode Selection                                 */
+        __IOM uint32_t T2nCLK   : 1;            /*!< [14..14] TIMER2n Clock Selection                                          */
+        __IOM uint32_t T2nEN    : 1;            /*!< [15..15] TIMER2n Operation Enable                                         */
+      } CR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t TIMER20_CR;                /*!< (@ 0x00000000) TIMER2n Control Register                                   */
+      
+      struct {
+        __IOM uint32_t T2nCLR   : 1;            /*!< [0..0] TIMER2n Counter and Prescaler Clear                                */
+        __IOM uint32_t T2nPAU   : 1;            /*!< [1..1] TIMER2n Counter Temporary Pause Control                            */
+        __IOM uint32_t T2nCIFLAG : 1;           /*!< [2..2] TIMER2n Capture Interrupt Flag                                     */
+        __IOM uint32_t T2nMIFLAG : 1;           /*!< [3..3] TIMER2n Match Interrupt Flag                                       */
+        __IOM uint32_t T2nCIEN  : 1;            /*!< [4..4] TIMER2n Capture Interrupt Enable                                   */
+        __IOM uint32_t T2nMIEN  : 1;            /*!< [5..5] TIMER2n Match Interrupt Enable                                     */
+        __IOM uint32_t T2nCPOL  : 2;            /*!< [7..6] TIMER2n Capture Polarity Selection                                 */
+        __IOM uint32_t T2nOPOL  : 1;            /*!< [8..8] TIMER2n Output Polarity Selection                                  */
+        __IOM uint32_t CAPSEL   : 2;            /*!< [10..9] TIMER2n Capture Signal Selection                                  */
+        __IOM uint32_t T2nECE   : 1;            /*!< [11..11] TIMER2n External Clock Edge Selection                            */
+        __IOM uint32_t T2nMS    : 2;            /*!< [13..12] TIMER2n Operation Mode Selection                                 */
+        __IOM uint32_t T2nCLK   : 1;            /*!< [14..14] TIMER2n Clock Selection                                          */
+        __IOM uint32_t T2nEN    : 1;            /*!< [15..15] TIMER2n Operation Enable                                         */
+      } TIMER20_CR_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER2n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 32;           /*!< [31..0] TIMER2n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER2n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 32;           /*!< [31..0] TIMER2n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER2n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 32;           /*!< [31..0] TIMER2n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER2n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER2n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER2n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 32;           /*!< [31..0] TIMER2n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER20_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER21                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 21 (TIMER21)
+  */
+
+typedef struct {                                /*!< (@ 0x40002600) TIMER21 Structure                                          */
+  
+  union {
+    union {
+      __IOM uint32_t CR;                        /*!< (@ 0x00000000) TIMER2n Control Register                                   */
+      
+      struct {
+        __IOM uint32_t T2nCLR   : 1;            /*!< [0..0] TIMER2n Counter and Prescaler Clear                                */
+        __IOM uint32_t T2nPAU   : 1;            /*!< [1..1] TIMER2n Counter Temporary Pause Control                            */
+        __IOM uint32_t T2nCIFLAG : 1;           /*!< [2..2] TIMER2n Capture Interrupt Flag                                     */
+        __IOM uint32_t T2nMIFLAG : 1;           /*!< [3..3] TIMER2n Match Interrupt Flag                                       */
+        __IOM uint32_t T2nCIEN  : 1;            /*!< [4..4] TIMER2n Capture Interrupt Enable                                   */
+        __IOM uint32_t T2nMIEN  : 1;            /*!< [5..5] TIMER2n Match Interrupt Enable                                     */
+        __IOM uint32_t T2nCPOL  : 2;            /*!< [7..6] TIMER2n Capture Polarity Selection                                 */
+        __IOM uint32_t T2nOPOL  : 1;            /*!< [8..8] TIMER2n Output Polarity Selection                                  */
+        __IOM uint32_t CAPSEL   : 2;            /*!< [10..9] TIMER2n Capture Signal Selection                                  */
+        __IOM uint32_t T2nECE   : 1;            /*!< [11..11] TIMER2n External Clock Edge Selection                            */
+        __IOM uint32_t T2nMS    : 2;            /*!< [13..12] TIMER2n Operation Mode Selection                                 */
+        __IOM uint32_t T2nCLK   : 1;            /*!< [14..14] TIMER2n Clock Selection                                          */
+        __IOM uint32_t T2nEN    : 1;            /*!< [15..15] TIMER2n Operation Enable                                         */
+      } CR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t TIMER21_CR;                /*!< (@ 0x00000000) TIMER2n Control Register                                   */
+      
+      struct {
+        __IOM uint32_t T2nCLR   : 1;            /*!< [0..0] TIMER2n Counter and Prescaler Clear                                */
+        __IOM uint32_t T2nPAU   : 1;            /*!< [1..1] TIMER2n Counter Temporary Pause Control                            */
+        __IOM uint32_t T2nCIFLAG : 1;           /*!< [2..2] TIMER2n Capture Interrupt Flag                                     */
+        __IOM uint32_t T2nMIFLAG : 1;           /*!< [3..3] TIMER2n Match Interrupt Flag                                       */
+        __IOM uint32_t T2nCIEN  : 1;            /*!< [4..4] TIMER2n Capture Interrupt Enable                                   */
+        __IOM uint32_t T2nMIEN  : 1;            /*!< [5..5] TIMER2n Match Interrupt Enable                                     */
+        __IOM uint32_t T2nCPOL  : 2;            /*!< [7..6] TIMER2n Capture Polarity Selection                                 */
+        __IOM uint32_t T2nOPOL  : 1;            /*!< [8..8] TIMER2n Output Polarity Selection                                  */
+        __IM  uint32_t          : 2;
+        __IOM uint32_t T2nECE   : 1;            /*!< [11..11] TIMER2n External Clock Edge Selection                            */
+        __IOM uint32_t T2nMS    : 2;            /*!< [13..12] TIMER2n Operation Mode Selection                                 */
+        __IOM uint32_t T2nCLK   : 1;            /*!< [14..14] TIMER2n Clock Selection                                          */
+        __IOM uint32_t T2nEN    : 1;            /*!< [15..15] TIMER2n Operation Enable                                         */
+      } TIMER21_CR_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000004) TIMER2n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 32;           /*!< [31..0] TIMER2n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000008) TIMER2n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 32;           /*!< [31..0] TIMER2n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x0000000C) TIMER2n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 32;           /*!< [31..0] TIMER2n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000010) TIMER2n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER2n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x00000014) TIMER2n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 32;           /*!< [31..0] TIMER2n Counter                                                   */
+    } CNT_b;
+  } ;
+} TIMER21_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER3n                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 3n (TIMER3n)
+  */
+
+typedef struct {                                /*!< (@ 0x53000000) TIMER3n Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER3n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T3nCLR     : 1;            /*!< [0..0] TIMER3n Counter and Prescaler Clear                                */
+      __IOM uint32_t PMOC       : 3;            /*!< [3..1] Period Match Interrupt Occurrence Selection                        */
+      __IOM uint32_t UPDT       : 2;            /*!< [5..4] Data Reload Time Selection                                         */
+      __IOM uint32_t T3nCPOL    : 2;            /*!< [7..6] TIMER3n Capture Polarity Selection                                 */
+      __IOM uint32_t DLYPOS     : 1;            /*!< [8..8] Delay Time Insertion Position                                      */
+      __IOM uint32_t DLYEN      : 1;            /*!< [9..9] Delay Time Insertion Enable                                        */
+      __IOM uint32_t FORCA      : 1;            /*!< [10..10] TIMER3n Output Mode Selection                                    */
+      __IOM uint32_t T3nECE     : 1;            /*!< [11..11] TIMER3n External Clock Edge Selection                            */
+      __IOM uint32_t T3nMS      : 2;            /*!< [13..12] TIMER3n Operation Mode Selection                                 */
+      __IOM uint32_t T3nCLK     : 1;            /*!< [14..14] TIMER3n Clock Selection                                          */
+      __IOM uint32_t T3nEN      : 1;            /*!< [15..15] TIMER3n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PDR;                         /*!< (@ 0x00000004) TIMER3n Period Data Register                               */
+    
+    struct {
+      __IOM uint32_t PDATA      : 16;           /*!< [15..0] TIMER3n Period Data                                               */
+    } PDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000008) TIMER3n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER3n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x0000000C) TIMER3n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER3n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CDR;                         /*!< (@ 0x00000010) TIMER3n C Data Register                                    */
+    
+    struct {
+      __IOM uint32_t CDATA      : 16;           /*!< [15..0] TIMER3n C Data                                                    */
+    } CDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x00000014) TIMER3n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER3n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000018) TIMER3n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER3n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x0000001C) TIMER3n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER3n Counter                                                   */
+    } CNT_b;
+  } ;
+  
+  union {
+    __IOM uint32_t OUTCR;                       /*!< (@ 0x00000020) TIMER3n Output Control Register                            */
+    
+    struct {
+      __IOM uint32_t LVLCA      : 1;            /*!< [0..0] Configure PWM3nCA Output when Disable                              */
+      __IOM uint32_t LVLBA      : 1;            /*!< [1..1] Configure PWM3nBA Output when Disable                              */
+      __IOM uint32_t LVLAA      : 1;            /*!< [2..2] Configure PWM3nAA Output when Disable                              */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LVLCB      : 1;            /*!< [4..4] Configure PWM3nCB Output when Disable                              */
+      __IOM uint32_t LVLBB      : 1;            /*!< [5..5] Configure PWM3nBB Output when Disable                              */
+      __IOM uint32_t LVLAB      : 1;            /*!< [6..6] Configure PWM3nAB Output when Disable                              */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t PCAOE      : 1;            /*!< [8..8] PWM3nCA Output Enable                                              */
+      __IOM uint32_t PBAOE      : 1;            /*!< [9..9] PWM3nBA Output Enable                                              */
+      __IOM uint32_t PAAOE      : 1;            /*!< [10..10] PWM3nAA Output Enable                                            */
+      __IOM uint32_t PCBOE      : 1;            /*!< [11..11] PWM3nCB Output Enable                                            */
+      __IOM uint32_t PBBOE      : 1;            /*!< [12..12] PWM3nBB Output Enable                                            */
+      __IOM uint32_t PABOE      : 1;            /*!< [13..13] PWM3nAB Output Enable                                            */
+      __IOM uint32_t POLA       : 1;            /*!< [14..14] PWM3nxA Output Polarity Selection                                */
+      __IOM uint32_t POLB       : 1;            /*!< [15..15] PWM3nxB Output Polarity Selection                                */
+      __OM  uint32_t WTIDKY     : 16;           /*!< [31..16] Write Identification Key                                         */
+    } OUTCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DLY;                         /*!< (@ 0x00000024) TIMER3n PWM Output Delay Data Register                     */
+    
+    struct {
+      __IOM uint32_t DLY        : 10;           /*!< [9..0] TIMER3n PWM Delay Data                                             */
+    } DLY_b;
+  } ;
+  
+  union {
+    __IOM uint32_t INTCR;                       /*!< (@ 0x00000028) TIMER3n Interrupt Control Register                         */
+    
+    struct {
+      __IOM uint32_t T3nCMIEN   : 1;            /*!< [0..0] TIMER3n C-ch Match Interrupt Enable                                */
+      __IOM uint32_t T3nBMIEN   : 1;            /*!< [1..1] TIMER3n B-ch Match Interrupt Enable                                */
+      __IOM uint32_t T3nAMIEN   : 1;            /*!< [2..2] TIMER3n A-ch Match Interrupt Enable                                */
+      __IOM uint32_t T3nPMIEN   : 1;            /*!< [3..3] TIMER3n Period Match Interrupt Enable                              */
+      __IOM uint32_t T3nBTIEN   : 1;            /*!< [4..4] TIMER3n Bottom Interrupt Enable                                    */
+      __IOM uint32_t T3nCIEN    : 1;            /*!< [5..5] TIMER3n Capture Interrupt Enable                                   */
+      __IOM uint32_t HIZIEN     : 1;            /*!< [6..6] TIMER3n Output High-Impedance Interrupt Enable                     */
+    } INTCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t INTFLAG;                     /*!< (@ 0x0000002C) TIMER3n Interrupt Flag Register                            */
+    
+    struct {
+      __IOM uint32_t T3nCMIFLAG : 1;            /*!< [0..0] TIMER3n C-ch Match Interrupt Flag                                  */
+      __IOM uint32_t T3nBMIFLAG : 1;            /*!< [1..1] TIMER3n B-ch Match Interrupt Flag                                  */
+      __IOM uint32_t T3nAMIFLAG : 1;            /*!< [2..2] TIMER3n A-ch Match Interrupt Flag                                  */
+      __IOM uint32_t T3nPMIFLAG : 1;            /*!< [3..3] TIMER3n Period Match Interrupt Flag                                */
+      __IOM uint32_t T3nBTIFLAG : 1;            /*!< [4..4] TIMER3n Bottom Interrupt Flag                                      */
+      __IOM uint32_t T3nCIFLAG  : 1;            /*!< [5..5] TIMER3n Capture Interrupt Flag                                     */
+      __IOM uint32_t HIZIFLAG   : 1;            /*!< [6..6] TIMER3n Output High-Impedance Interrupt Flag                       */
+    } INTFLAG_b;
+  } ;
+  
+  union {
+    __IOM uint32_t HIZCR;                       /*!< (@ 0x00000030) TIMER3n High-Impedance Control Register                    */
+    
+    struct {
+      __IOM uint32_t HIZCLR     : 1;            /*!< [0..0] High-Impedance Output Clear                                        */
+      __IM  uint32_t HIZSTA     : 1;            /*!< [1..1] High-Impedance Status                                              */
+      __IOM uint32_t HEDGE      : 1;            /*!< [2..2] High-Impedance Edge Selection                                      */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t HIZSW      : 1;            /*!< [4..4] High-Impedance Output Software Setting                             */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t HIZEN      : 1;            /*!< [7..7] PWM3nxA/PWM3nxB Output High-Impedance Enable                       */
+    } HIZCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADTCR;                       /*!< (@ 0x00000034) TIMER3n ADC Trigger Control Register                       */
+    
+    struct {
+      __IOM uint32_t T3nCMTG    : 1;            /*!< [0..0] Select TIMER3n C-ch Match for ADC Trigger Signal Generator.        */
+      __IOM uint32_t T3nBMTG    : 1;            /*!< [1..1] Select TIMER3n B-ch Match for ADC Trigger Signal Generator.        */
+      __IOM uint32_t T3nAMTG    : 1;            /*!< [2..2] Select TIMER3n A-ch Match for ADC Trigger Signal Generator.        */
+      __IOM uint32_t T3nPMTG    : 1;            /*!< [3..3] Select TIMER3n Period Match for ADC Trigger Signal Generator.      */
+      __IOM uint32_t T3nBTTG    : 1;            /*!< [4..4] Select TIMER3n Bottom for ADC Trigger Signal Generator.            */
+    } ADTCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADTDR;                       /*!< (@ 0x00000038) TIMER3n ADC Trigger Generator Data Register                */
+    
+    struct {
+      __IOM uint32_t ADTDATA    : 14;           /*!< [13..0] TIMER3n ADC Trigger Generation Data                               */
+    } ADTDR_b;
+  } ;
+} TIMER3n_Type;                                 /*!< Size = 60 (0x3c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER30                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer/Counter 30 (TIMER30)
+  */
+
+typedef struct {                                /*!< (@ 0x40002400) TIMER30 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) TIMER3n Control Register                                   */
+    
+    struct {
+      __IOM uint32_t T3nCLR     : 1;            /*!< [0..0] TIMER3n Counter and Prescaler Clear                                */
+      __IOM uint32_t PMOC       : 3;            /*!< [3..1] Period Match Interrupt Occurrence Selection                        */
+      __IOM uint32_t UPDT       : 2;            /*!< [5..4] Data Reload Time Selection                                         */
+      __IOM uint32_t T3nCPOL    : 2;            /*!< [7..6] TIMER3n Capture Polarity Selection                                 */
+      __IOM uint32_t DLYPOS     : 1;            /*!< [8..8] Delay Time Insertion Position                                      */
+      __IOM uint32_t DLYEN      : 1;            /*!< [9..9] Delay Time Insertion Enable                                        */
+      __IOM uint32_t FORCA      : 1;            /*!< [10..10] TIMER3n Output Mode Selection                                    */
+      __IOM uint32_t T3nECE     : 1;            /*!< [11..11] TIMER3n External Clock Edge Selection                            */
+      __IOM uint32_t T3nMS      : 2;            /*!< [13..12] TIMER3n Operation Mode Selection                                 */
+      __IOM uint32_t T3nCLK     : 1;            /*!< [14..14] TIMER3n Clock Selection                                          */
+      __IOM uint32_t T3nEN      : 1;            /*!< [15..15] TIMER3n Operation Enable                                         */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PDR;                         /*!< (@ 0x00000004) TIMER3n Period Data Register                               */
+    
+    struct {
+      __IOM uint32_t PDATA      : 16;           /*!< [15..0] TIMER3n Period Data                                               */
+    } PDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADR;                         /*!< (@ 0x00000008) TIMER3n A Data Register                                    */
+    
+    struct {
+      __IOM uint32_t ADATA      : 16;           /*!< [15..0] TIMER3n A Data                                                    */
+    } ADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x0000000C) TIMER3n B Data Register                                    */
+    
+    struct {
+      __IOM uint32_t BDATA      : 16;           /*!< [15..0] TIMER3n B Data                                                    */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CDR;                         /*!< (@ 0x00000010) TIMER3n C Data Register                                    */
+    
+    struct {
+      __IOM uint32_t CDATA      : 16;           /*!< [15..0] TIMER3n C Data                                                    */
+    } CDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CAPDR;                       /*!< (@ 0x00000014) TIMER3n Capture Data Register                              */
+    
+    struct {
+      __IM  uint32_t CAPD       : 16;           /*!< [15..0] TIMER3n Capture Data                                              */
+    } CAPDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000018) TIMER3n Prescaler Data Register                            */
+    
+    struct {
+      __IOM uint32_t PRED       : 12;           /*!< [11..0] TIMER3n Prescaler Data                                            */
+    } PREDR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNT;                         /*!< (@ 0x0000001C) TIMER3n Counter Register                                   */
+    
+    struct {
+      __IM  uint32_t CNT        : 16;           /*!< [15..0] TIMER3n Counter                                                   */
+    } CNT_b;
+  } ;
+  
+  union {
+    union {
+      __IOM uint32_t OUTCR;                     /*!< (@ 0x00000020) TIMER3n Output Control Register                            */
+      
+      struct {
+        __IOM uint32_t LVLCA    : 1;            /*!< [0..0] Configure PWM3nCA Output when Disable                              */
+        __IOM uint32_t LVLBA    : 1;            /*!< [1..1] Configure PWM3nBA Output when Disable                              */
+        __IOM uint32_t LVLAA    : 1;            /*!< [2..2] Configure PWM3nAA Output when Disable                              */
+        __IM  uint32_t          : 1;
+        __IOM uint32_t LVLCB    : 1;            /*!< [4..4] Configure PWM3nCB Output when Disable                              */
+        __IOM uint32_t LVLBB    : 1;            /*!< [5..5] Configure PWM3nBB Output when Disable                              */
+        __IOM uint32_t LVLAB    : 1;            /*!< [6..6] Configure PWM3nAB Output when Disable                              */
+        __IM  uint32_t          : 1;
+        __IOM uint32_t PCAOE    : 1;            /*!< [8..8] PWM3nCA Output Enable                                              */
+        __IOM uint32_t PBAOE    : 1;            /*!< [9..9] PWM3nBA Output Enable                                              */
+        __IOM uint32_t PAAOE    : 1;            /*!< [10..10] PWM3nAA Output Enable                                            */
+        __IOM uint32_t PCBOE    : 1;            /*!< [11..11] PWM3nCB Output Enable                                            */
+        __IOM uint32_t PBBOE    : 1;            /*!< [12..12] PWM3nBB Output Enable                                            */
+        __IOM uint32_t PABOE    : 1;            /*!< [13..13] PWM3nAB Output Enable                                            */
+        __IOM uint32_t POLA     : 1;            /*!< [14..14] PWM3nxA Output Polarity Selection                                */
+        __IOM uint32_t POLB     : 1;            /*!< [15..15] PWM3nxB Output Polarity Selection                                */
+        __OM  uint32_t WTIDKY   : 16;           /*!< [31..16] Write Identification Key                                         */
+      } OUTCR_b;
+    } ;
+    
+    union {
+      __IOM uint32_t T30_OUTCR;                 /*!< (@ 0x00000020) TIMER3n Output Control Register                            */
+      
+      struct {
+        __IOM uint32_t LVLCA    : 1;            /*!< [0..0] Configure PWM3nCA Output when Disable                              */
+        __IOM uint32_t LVLBA    : 1;            /*!< [1..1] Configure PWM3nBA Output when Disable                              */
+        __IOM uint32_t LVLAA    : 1;            /*!< [2..2] Configure PWM3nAA Output when Disable                              */
+        __IM  uint32_t          : 1;
+        __IOM uint32_t LVLCB    : 1;            /*!< [4..4] Configure PWM3nCB Output when Disable                              */
+        __IOM uint32_t LVLBB    : 1;            /*!< [5..5] Configure PWM3nBB Output when Disable                              */
+        __IOM uint32_t LVLAB    : 1;            /*!< [6..6] Configure PWM3nAB Output when Disable                              */
+        __IM  uint32_t          : 1;
+        __IOM uint32_t PCAOE    : 1;            /*!< [8..8] PWM3nCA Output Enable                                              */
+        __IOM uint32_t PBAOE    : 1;            /*!< [9..9] PWM3nBA Output Enable                                              */
+        __IOM uint32_t PAAOE    : 1;            /*!< [10..10] PWM3nAA Output Enable                                            */
+        __IOM uint32_t PCBOE    : 1;            /*!< [11..11] PWM3nCB Output Enable                                            */
+        __IOM uint32_t PBBOE    : 1;            /*!< [12..12] PWM3nBB Output Enable                                            */
+        __IOM uint32_t PABOE    : 1;            /*!< [13..13] PWM3nAB Output Enable                                            */
+        __IOM uint32_t POLA     : 1;            /*!< [14..14] PWM3nxA Output Polarity Selection                                */
+        __IOM uint32_t POLB     : 1;            /*!< [15..15] PWM3nxB Output Polarity Selection                                */
+        __OM  uint32_t WTIDKY   : 16;           /*!< [31..16] Write Identification Key (0xe06c)                                */
+      } T30_OUTCR_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t DLY;                         /*!< (@ 0x00000024) TIMER3n PWM Output Delay Data Register                     */
+    
+    struct {
+      __IOM uint32_t DLY        : 10;           /*!< [9..0] TIMER3n PWM Delay Data                                             */
+    } DLY_b;
+  } ;
+  
+  union {
+    __IOM uint32_t INTCR;                       /*!< (@ 0x00000028) TIMER3n Interrupt Control Register                         */
+    
+    struct {
+      __IOM uint32_t T3nCMIEN   : 1;            /*!< [0..0] TIMER3n C-ch Match Interrupt Enable                                */
+      __IOM uint32_t T3nBMIEN   : 1;            /*!< [1..1] TIMER3n B-ch Match Interrupt Enable                                */
+      __IOM uint32_t T3nAMIEN   : 1;            /*!< [2..2] TIMER3n A-ch Match Interrupt Enable                                */
+      __IOM uint32_t T3nPMIEN   : 1;            /*!< [3..3] TIMER3n Period Match Interrupt Enable                              */
+      __IOM uint32_t T3nBTIEN   : 1;            /*!< [4..4] TIMER3n Bottom Interrupt Enable                                    */
+      __IOM uint32_t T3nCIEN    : 1;            /*!< [5..5] TIMER3n Capture Interrupt Enable                                   */
+      __IOM uint32_t HIZIEN     : 1;            /*!< [6..6] TIMER3n Output High-Impedance Interrupt Enable                     */
+    } INTCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t INTFLAG;                     /*!< (@ 0x0000002C) TIMER3n Interrupt Flag Register                            */
+    
+    struct {
+      __IOM uint32_t T3nCMIFLAG : 1;            /*!< [0..0] TIMER3n C-ch Match Interrupt Flag                                  */
+      __IOM uint32_t T3nBMIFLAG : 1;            /*!< [1..1] TIMER3n B-ch Match Interrupt Flag                                  */
+      __IOM uint32_t T3nAMIFLAG : 1;            /*!< [2..2] TIMER3n A-ch Match Interrupt Flag                                  */
+      __IOM uint32_t T3nPMIFLAG : 1;            /*!< [3..3] TIMER3n Period Match Interrupt Flag                                */
+      __IOM uint32_t T3nBTIFLAG : 1;            /*!< [4..4] TIMER3n Bottom Interrupt Flag                                      */
+      __IOM uint32_t T3nCIFLAG  : 1;            /*!< [5..5] TIMER3n Capture Interrupt Flag                                     */
+      __IOM uint32_t HIZIFLAG   : 1;            /*!< [6..6] TIMER3n Output High-Impedance Interrupt Flag                       */
+    } INTFLAG_b;
+  } ;
+  
+  union {
+    __IOM uint32_t HIZCR;                       /*!< (@ 0x00000030) TIMER3n High-Impedance Control Register                    */
+    
+    struct {
+      __IOM uint32_t HIZCLR     : 1;            /*!< [0..0] High-Impedance Output Clear                                        */
+      __IM  uint32_t HIZSTA     : 1;            /*!< [1..1] High-Impedance Status                                              */
+      __IOM uint32_t HEDGE      : 1;            /*!< [2..2] High-Impedance Edge Selection                                      */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t HIZSW      : 1;            /*!< [4..4] High-Impedance Output Software Setting                             */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t HIZEN      : 1;            /*!< [7..7] PWM3nxA/PWM3nxB Output High-Impedance Enable                       */
+    } HIZCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADTCR;                       /*!< (@ 0x00000034) TIMER3n ADC Trigger Control Register                       */
+    
+    struct {
+      __IOM uint32_t T3nCMTG    : 1;            /*!< [0..0] Select TIMER3n C-ch Match for ADC Trigger Signal Generator.        */
+      __IOM uint32_t T3nBMTG    : 1;            /*!< [1..1] Select TIMER3n B-ch Match for ADC Trigger Signal Generator.        */
+      __IOM uint32_t T3nAMTG    : 1;            /*!< [2..2] Select TIMER3n A-ch Match for ADC Trigger Signal Generator.        */
+      __IOM uint32_t T3nPMTG    : 1;            /*!< [3..3] Select TIMER3n Period Match for ADC Trigger Signal Generator.      */
+      __IOM uint32_t T3nBTTG    : 1;            /*!< [4..4] Select TIMER3n Bottom for ADC Trigger Signal Generator.            */
+    } ADTCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ADTDR;                       /*!< (@ 0x00000038) TIMER3n ADC Trigger Generator Data Register                */
+    
+    struct {
+      __IOM uint32_t ADTDATA    : 14;           /*!< [13..0] TIMER3n ADC Trigger Generation Data                               */
+    } ADTDR_b;
+  } ;
+} TIMER30_Type;                                 /*!< Size = 60 (0x3c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            ADC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief 12 Bit A/D Converter (ADC)
+  */
+
+typedef struct {                                /*!< (@ 0x40003000) ADC Structure                                              */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) A/D Converter Control Register                             */
+    
+    struct {
+      __IOM uint32_t ADSEL      : 4;            /*!< [3..0] A/D Converter Channel Selection                                    */
+      __IOM uint32_t ADCIFLAG   : 1;            /*!< [4..4] ADC Interrupt Flag                                                 */
+      __IOM uint32_t ADCIEN     : 1;            /*!< [5..5] ADC Interrupt Enable                                               */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t ADST       : 1;            /*!< [8..8] ADC Conversion Start                                               */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t REFSEL     : 1;            /*!< [10..10] ADC Reference Selection                                          */
+      __IOM uint32_t TRIG       : 3;            /*!< [13..11] ADC Trigger Signal Selection                                     */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t ADCEN      : 1;            /*!< [15..15] ADC Module Enable                                                */
+    } CR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t DR;                          /*!< (@ 0x00000004) A/D Converter Data Register                                */
+    
+    struct {
+      __IM  uint32_t ADDATA     : 12;           /*!< [11..0] A/D Converter Result Data                                         */
+    } DR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t PREDR;                       /*!< (@ 0x00000008) A/D Converter Prescaler Data Register                      */
+    
+    struct {
+      __IOM uint32_t PRED       : 5;            /*!< [4..0] A/D Converter Prescaler Data                                       */
+    } PREDR_b;
+  } ;
+} ADC_Type;                                     /*!< Size = 12 (0xc)                                                           */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART1n                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief USART 1n (USART + SPI) (USART1n)
+  */
+
+typedef struct {                                /*!< (@ 0x54000000) USART1n Structure                                          */
+  
+  union {
+    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) USART1n Control Register 1                                 */
+    
+    struct {
+      __IOM uint32_t RXEn       : 1;            /*!< [0..0] Enable the receiver unit.                                          */
+      __IOM uint32_t TXEn       : 1;            /*!< [1..1] Enable the transmitter unit.                                       */
+      __IOM uint32_t WAKEIEn    : 1;            /*!< [2..2] Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode           */
+      __IOM uint32_t RXCIEn     : 1;            /*!< [3..3] Receive Complete Interrupt Enable                                  */
+      __IOM uint32_t TXCIEn     : 1;            /*!< [4..4] Transmit Complete Interrupt Enable                                 */
+      __IOM uint32_t DRIEn      : 1;            /*!< [5..5] Transmit Data Register Empty Interrupt Enable                      */
+      __IOM uint32_t CPHAn      : 1;            /*!< [6..6] The CPOLn and this bit determine if data are sampled
+                                                     on the leading or trailing edge of SCK (only SPI mode)                    */
+      __IOM uint32_t CPOLn      : 1;            /*!< [7..7] Selects the Clock Polarity of ACK in Synchronous or SPI
+                                                     mode                                                                      */
+      __IOM uint32_t ORDn       : 1;            /*!< [8..8] Selects the first data bit to be transmitted (only SPI
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnS      : 3;            /*!< [11..9] Selects the length of data bit in a frame when Asynchronous
+                                                     or Synchronous mode                                                       */
+      __IOM uint32_t USTnP      : 2;            /*!< [13..12] Selects Parity Generation and Check method (only UART
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnMS     : 2;            /*!< [15..14] USART1n Operation Mode Selection                                 */
+    } CR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) USART1n Control Register 2                                 */
+    
+    struct {
+      __IOM uint32_t USTnRX8    : 1;            /*!< [0..0] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnTX8    : 1;            /*!< [1..1] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnSB     : 1;            /*!< [2..2] Selects the length of stop bit in Asynchronous or Synchronous
+                                                     mode                                                                      */
+      __IOM uint32_t FXCHn      : 1;            /*!< [3..3] SPI1n port function exchange control (only SPI mode)               */
+      __IOM uint32_t USTnSSEN   : 1;            /*!< [4..4] This bit controls the SS1n pin operation (only SPI mode)           */
+      __IOM uint32_t DISSCKn    : 1;            /*!< [5..5] In synchronous mode operation, selects the waveform of
+                                                     SCK1n output                                                              */
+      __IOM uint32_t LOOPSn     : 1;            /*!< [6..6] Control the Loop Back mode of USART1n for test mode                */
+      __IOM uint32_t MASTERn    : 1;            /*!< [7..7] Selects master or slave in SPI1n or Synchronous mode
+                                                     and controls the direction of SCK1n pin                                   */
+      __IOM uint32_t DBLSn      : 1;            /*!< [8..8] Selects receiver sampling rate (only UART mode)                    */
+      __IOM uint32_t USTnEN     : 1;            /*!< [9..9] Activate USART1n Block                                             */
+    } CR2_b;
+  } ;
+  __IM  uint32_t  RESERVED;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x0000000C) USART1n Status Register                                    */
+    
+    struct {
+      __IOM uint32_t PEn        : 1;            /*!< [0..0] This bit is set if the next character in the receive
+                                                     buffer has a Parity Error while parity is checked                         */
+      __IOM uint32_t FEn        : 1;            /*!< [1..1] This bit is set if the first stop bit of next character
+                                                     in the receive buffer is detected as '0'                                  */
+      __IM  uint32_t DORn       : 1;            /*!< [2..2] This bit is set if data OverRun takes place                        */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t WAKEn      : 1;            /*!< [4..4] Asynchronous Wake-Up Interrupt Flag                                */
+      __IM  uint32_t RXCn       : 1;            /*!< [5..5] Receive Complete Interrupt Flag                                    */
+      __IOM uint32_t TXCn       : 1;            /*!< [6..6] Transmit Complete Interrupt Flag                                   */
+      __IOM uint32_t DREn       : 1;            /*!< [7..7] Transmit Data Register Empty Interrupt Flag                        */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000010) USART1n Baud Rate Generation Register                      */
+    
+    struct {
+      __IOM uint32_t BDATA      : 12;           /*!< [11..0] The value in this register is used to generate internal
+                                                     baud rate in UART mode or to generate SCK clock in SPI
+                                                     mode                                                                      */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000014) USART1n Data Register                                      */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The USART Transmit buffer and Receive buffer share the
+                                                     same I/O address with this DATA register                                  */
+    } DR_b;
+  } ;
+} USART1n_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART10                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief USART 10 (USART + SPI) (USART10)
+  */
+
+typedef struct {                                /*!< (@ 0x40003800) USART10 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) USART1n Control Register 1                                 */
+    
+    struct {
+      __IOM uint32_t RXEn       : 1;            /*!< [0..0] Enable the receiver unit.                                          */
+      __IOM uint32_t TXEn       : 1;            /*!< [1..1] Enable the transmitter unit.                                       */
+      __IOM uint32_t WAKEIEn    : 1;            /*!< [2..2] Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode           */
+      __IOM uint32_t RXCIEn     : 1;            /*!< [3..3] Receive Complete Interrupt Enable                                  */
+      __IOM uint32_t TXCIEn     : 1;            /*!< [4..4] Transmit Complete Interrupt Enable                                 */
+      __IOM uint32_t DRIEn      : 1;            /*!< [5..5] Transmit Data Register Empty Interrupt Enable                      */
+      __IOM uint32_t CPHAn      : 1;            /*!< [6..6] The CPOLn and this bit determine if data are sampled
+                                                     on the leading or trailing edge of SCK (only SPI mode)                    */
+      __IOM uint32_t CPOLn      : 1;            /*!< [7..7] Selects the Clock Polarity of ACK in Synchronous or SPI
+                                                     mode                                                                      */
+      __IOM uint32_t ORDn       : 1;            /*!< [8..8] Selects the first data bit to be transmitted (only SPI
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnS      : 3;            /*!< [11..9] Selects the length of data bit in a frame when Asynchronous
+                                                     or Synchronous mode                                                       */
+      __IOM uint32_t USTnP      : 2;            /*!< [13..12] Selects Parity Generation and Check method (only UART
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnMS     : 2;            /*!< [15..14] USART1n Operation Mode Selection                                 */
+    } CR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) USART1n Control Register 2                                 */
+    
+    struct {
+      __IOM uint32_t USTnRX8    : 1;            /*!< [0..0] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnTX8    : 1;            /*!< [1..1] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnSB     : 1;            /*!< [2..2] Selects the length of stop bit in Asynchronous or Synchronous
+                                                     mode                                                                      */
+      __IOM uint32_t FXCHn      : 1;            /*!< [3..3] SPI1n port function exchange control (only SPI mode)               */
+      __IOM uint32_t USTnSSEN   : 1;            /*!< [4..4] This bit controls the SS1n pin operation (only SPI mode)           */
+      __IOM uint32_t DISSCKn    : 1;            /*!< [5..5] In synchronous mode operation, selects the waveform of
+                                                     SCK1n output                                                              */
+      __IOM uint32_t LOOPSn     : 1;            /*!< [6..6] Control the Loop Back mode of USART1n for test mode                */
+      __IOM uint32_t MASTERn    : 1;            /*!< [7..7] Selects master or slave in SPI1n or Synchronous mode
+                                                     and controls the direction of SCK1n pin                                   */
+      __IOM uint32_t DBLSn      : 1;            /*!< [8..8] Selects receiver sampling rate (only UART mode)                    */
+      __IOM uint32_t USTnEN     : 1;            /*!< [9..9] Activate USART1n Block                                             */
+    } CR2_b;
+  } ;
+  __IM  uint32_t  RESERVED;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x0000000C) USART1n Status Register                                    */
+    
+    struct {
+      __IOM uint32_t PEn        : 1;            /*!< [0..0] This bit is set if the next character in the receive
+                                                     buffer has a Parity Error while parity is checked                         */
+      __IOM uint32_t FEn        : 1;            /*!< [1..1] This bit is set if the first stop bit of next character
+                                                     in the receive buffer is detected as '0'                                  */
+      __IM  uint32_t DORn       : 1;            /*!< [2..2] This bit is set if data OverRun takes place                        */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t WAKEn      : 1;            /*!< [4..4] Asynchronous Wake-Up Interrupt Flag                                */
+      __IM  uint32_t RXCn       : 1;            /*!< [5..5] Receive Complete Interrupt Flag                                    */
+      __IOM uint32_t TXCn       : 1;            /*!< [6..6] Transmit Complete Interrupt Flag                                   */
+      __IOM uint32_t DREn       : 1;            /*!< [7..7] Transmit Data Register Empty Interrupt Flag                        */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000010) USART1n Baud Rate Generation Register                      */
+    
+    struct {
+      __IOM uint32_t BDATA      : 12;           /*!< [11..0] The value in this register is used to generate internal
+                                                     baud rate in UART mode or to generate SCK clock in SPI
+                                                     mode                                                                      */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000014) USART1n Data Register                                      */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The USART Transmit buffer and Receive buffer share the
+                                                     same I/O address with this DATA register                                  */
+    } DR_b;
+  } ;
+} USART10_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART11                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief USART 11 (USART + SPI) (USART11)
+  */
+
+typedef struct {                                /*!< (@ 0x40003900) USART11 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) USART1n Control Register 1                                 */
+    
+    struct {
+      __IOM uint32_t RXEn       : 1;            /*!< [0..0] Enable the receiver unit.                                          */
+      __IOM uint32_t TXEn       : 1;            /*!< [1..1] Enable the transmitter unit.                                       */
+      __IOM uint32_t WAKEIEn    : 1;            /*!< [2..2] Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode           */
+      __IOM uint32_t RXCIEn     : 1;            /*!< [3..3] Receive Complete Interrupt Enable                                  */
+      __IOM uint32_t TXCIEn     : 1;            /*!< [4..4] Transmit Complete Interrupt Enable                                 */
+      __IOM uint32_t DRIEn      : 1;            /*!< [5..5] Transmit Data Register Empty Interrupt Enable                      */
+      __IOM uint32_t CPHAn      : 1;            /*!< [6..6] The CPOLn and this bit determine if data are sampled
+                                                     on the leading or trailing edge of SCK (only SPI mode)                    */
+      __IOM uint32_t CPOLn      : 1;            /*!< [7..7] Selects the Clock Polarity of ACK in Synchronous or SPI
+                                                     mode                                                                      */
+      __IOM uint32_t ORDn       : 1;            /*!< [8..8] Selects the first data bit to be transmitted (only SPI
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnS      : 3;            /*!< [11..9] Selects the length of data bit in a frame when Asynchronous
+                                                     or Synchronous mode                                                       */
+      __IOM uint32_t USTnP      : 2;            /*!< [13..12] Selects Parity Generation and Check method (only UART
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnMS     : 2;            /*!< [15..14] USART1n Operation Mode Selection                                 */
+    } CR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) USART1n Control Register 2                                 */
+    
+    struct {
+      __IOM uint32_t USTnRX8    : 1;            /*!< [0..0] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnTX8    : 1;            /*!< [1..1] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnSB     : 1;            /*!< [2..2] Selects the length of stop bit in Asynchronous or Synchronous
+                                                     mode                                                                      */
+      __IOM uint32_t FXCHn      : 1;            /*!< [3..3] SPI1n port function exchange control (only SPI mode)               */
+      __IOM uint32_t USTnSSEN   : 1;            /*!< [4..4] This bit controls the SS1n pin operation (only SPI mode)           */
+      __IOM uint32_t DISSCKn    : 1;            /*!< [5..5] In synchronous mode operation, selects the waveform of
+                                                     SCK1n output                                                              */
+      __IOM uint32_t LOOPSn     : 1;            /*!< [6..6] Control the Loop Back mode of USART1n for test mode                */
+      __IOM uint32_t MASTERn    : 1;            /*!< [7..7] Selects master or slave in SPI1n or Synchronous mode
+                                                     and controls the direction of SCK1n pin                                   */
+      __IOM uint32_t DBLSn      : 1;            /*!< [8..8] Selects receiver sampling rate (only UART mode)                    */
+      __IOM uint32_t USTnEN     : 1;            /*!< [9..9] Activate USART1n Block                                             */
+    } CR2_b;
+  } ;
+  __IM  uint32_t  RESERVED;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x0000000C) USART1n Status Register                                    */
+    
+    struct {
+      __IOM uint32_t PEn        : 1;            /*!< [0..0] This bit is set if the next character in the receive
+                                                     buffer has a Parity Error while parity is checked                         */
+      __IOM uint32_t FEn        : 1;            /*!< [1..1] This bit is set if the first stop bit of next character
+                                                     in the receive buffer is detected as '0'                                  */
+      __IM  uint32_t DORn       : 1;            /*!< [2..2] This bit is set if data OverRun takes place                        */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t WAKEn      : 1;            /*!< [4..4] Asynchronous Wake-Up Interrupt Flag                                */
+      __IM  uint32_t RXCn       : 1;            /*!< [5..5] Receive Complete Interrupt Flag                                    */
+      __IOM uint32_t TXCn       : 1;            /*!< [6..6] Transmit Complete Interrupt Flag                                   */
+      __IOM uint32_t DREn       : 1;            /*!< [7..7] Transmit Data Register Empty Interrupt Flag                        */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000010) USART1n Baud Rate Generation Register                      */
+    
+    struct {
+      __IOM uint32_t BDATA      : 12;           /*!< [11..0] The value in this register is used to generate internal
+                                                     baud rate in UART mode or to generate SCK clock in SPI
+                                                     mode                                                                      */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000014) USART1n Data Register                                      */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The USART Transmit buffer and Receive buffer share the
+                                                     same I/O address with this DATA register                                  */
+    } DR_b;
+  } ;
+} USART11_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART12                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief USART 12 (USART + SPI) (USART12)
+  */
+
+typedef struct {                                /*!< (@ 0x40003A00) USART12 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) USART1n Control Register 1                                 */
+    
+    struct {
+      __IOM uint32_t RXEn       : 1;            /*!< [0..0] Enable the receiver unit.                                          */
+      __IOM uint32_t TXEn       : 1;            /*!< [1..1] Enable the transmitter unit.                                       */
+      __IOM uint32_t WAKEIEn    : 1;            /*!< [2..2] Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode           */
+      __IOM uint32_t RXCIEn     : 1;            /*!< [3..3] Receive Complete Interrupt Enable                                  */
+      __IOM uint32_t TXCIEn     : 1;            /*!< [4..4] Transmit Complete Interrupt Enable                                 */
+      __IOM uint32_t DRIEn      : 1;            /*!< [5..5] Transmit Data Register Empty Interrupt Enable                      */
+      __IOM uint32_t CPHAn      : 1;            /*!< [6..6] The CPOLn and this bit determine if data are sampled
+                                                     on the leading or trailing edge of SCK (only SPI mode)                    */
+      __IOM uint32_t CPOLn      : 1;            /*!< [7..7] Selects the Clock Polarity of ACK in Synchronous or SPI
+                                                     mode                                                                      */
+      __IOM uint32_t ORDn       : 1;            /*!< [8..8] Selects the first data bit to be transmitted (only SPI
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnS      : 3;            /*!< [11..9] Selects the length of data bit in a frame when Asynchronous
+                                                     or Synchronous mode                                                       */
+      __IOM uint32_t USTnP      : 2;            /*!< [13..12] Selects Parity Generation and Check method (only UART
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnMS     : 2;            /*!< [15..14] USART1n Operation Mode Selection                                 */
+    } CR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) USART1n Control Register 2                                 */
+    
+    struct {
+      __IOM uint32_t USTnRX8    : 1;            /*!< [0..0] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnTX8    : 1;            /*!< [1..1] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnSB     : 1;            /*!< [2..2] Selects the length of stop bit in Asynchronous or Synchronous
+                                                     mode                                                                      */
+      __IOM uint32_t FXCHn      : 1;            /*!< [3..3] SPI1n port function exchange control (only SPI mode)               */
+      __IOM uint32_t USTnSSEN   : 1;            /*!< [4..4] This bit controls the SS1n pin operation (only SPI mode)           */
+      __IOM uint32_t DISSCKn    : 1;            /*!< [5..5] In synchronous mode operation, selects the waveform of
+                                                     SCK1n output                                                              */
+      __IOM uint32_t LOOPSn     : 1;            /*!< [6..6] Control the Loop Back mode of USART1n for test mode                */
+      __IOM uint32_t MASTERn    : 1;            /*!< [7..7] Selects master or slave in SPI1n or Synchronous mode
+                                                     and controls the direction of SCK1n pin                                   */
+      __IOM uint32_t DBLSn      : 1;            /*!< [8..8] Selects receiver sampling rate (only UART mode)                    */
+      __IOM uint32_t USTnEN     : 1;            /*!< [9..9] Activate USART1n Block                                             */
+    } CR2_b;
+  } ;
+  __IM  uint32_t  RESERVED;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x0000000C) USART1n Status Register                                    */
+    
+    struct {
+      __IOM uint32_t PEn        : 1;            /*!< [0..0] This bit is set if the next character in the receive
+                                                     buffer has a Parity Error while parity is checked                         */
+      __IOM uint32_t FEn        : 1;            /*!< [1..1] This bit is set if the first stop bit of next character
+                                                     in the receive buffer is detected as '0'                                  */
+      __IM  uint32_t DORn       : 1;            /*!< [2..2] This bit is set if data OverRun takes place                        */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t WAKEn      : 1;            /*!< [4..4] Asynchronous Wake-Up Interrupt Flag                                */
+      __IM  uint32_t RXCn       : 1;            /*!< [5..5] Receive Complete Interrupt Flag                                    */
+      __IOM uint32_t TXCn       : 1;            /*!< [6..6] Transmit Complete Interrupt Flag                                   */
+      __IOM uint32_t DREn       : 1;            /*!< [7..7] Transmit Data Register Empty Interrupt Flag                        */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000010) USART1n Baud Rate Generation Register                      */
+    
+    struct {
+      __IOM uint32_t BDATA      : 12;           /*!< [11..0] The value in this register is used to generate internal
+                                                     baud rate in UART mode or to generate SCK clock in SPI
+                                                     mode                                                                      */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000014) USART1n Data Register                                      */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The USART Transmit buffer and Receive buffer share the
+                                                     same I/O address with this DATA register                                  */
+    } DR_b;
+  } ;
+} USART12_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART13                                          ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief USART 13 (USART + SPI) (USART13)
+  */
+
+typedef struct {                                /*!< (@ 0x40003B00) USART13 Structure                                          */
+  
+  union {
+    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) USART1n Control Register 1                                 */
+    
+    struct {
+      __IOM uint32_t RXEn       : 1;            /*!< [0..0] Enable the receiver unit.                                          */
+      __IOM uint32_t TXEn       : 1;            /*!< [1..1] Enable the transmitter unit.                                       */
+      __IOM uint32_t WAKEIEn    : 1;            /*!< [2..2] Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode           */
+      __IOM uint32_t RXCIEn     : 1;            /*!< [3..3] Receive Complete Interrupt Enable                                  */
+      __IOM uint32_t TXCIEn     : 1;            /*!< [4..4] Transmit Complete Interrupt Enable                                 */
+      __IOM uint32_t DRIEn      : 1;            /*!< [5..5] Transmit Data Register Empty Interrupt Enable                      */
+      __IOM uint32_t CPHAn      : 1;            /*!< [6..6] The CPOLn and this bit determine if data are sampled
+                                                     on the leading or trailing edge of SCK (only SPI mode)                    */
+      __IOM uint32_t CPOLn      : 1;            /*!< [7..7] Selects the Clock Polarity of ACK in Synchronous or SPI
+                                                     mode                                                                      */
+      __IOM uint32_t ORDn       : 1;            /*!< [8..8] Selects the first data bit to be transmitted (only SPI
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnS      : 3;            /*!< [11..9] Selects the length of data bit in a frame when Asynchronous
+                                                     or Synchronous mode                                                       */
+      __IOM uint32_t USTnP      : 2;            /*!< [13..12] Selects Parity Generation and Check method (only UART
+                                                     mode)                                                                     */
+      __IOM uint32_t USTnMS     : 2;            /*!< [15..14] USART1n Operation Mode Selection                                 */
+    } CR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) USART1n Control Register 2                                 */
+    
+    struct {
+      __IOM uint32_t USTnRX8    : 1;            /*!< [0..0] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnTX8    : 1;            /*!< [1..1] The ninth bit of data frame in Asynchronous or Synchronous
+                                                     mode of operation                                                         */
+      __IOM uint32_t USTnSB     : 1;            /*!< [2..2] Selects the length of stop bit in Asynchronous or Synchronous
+                                                     mode                                                                      */
+      __IOM uint32_t FXCHn      : 1;            /*!< [3..3] SPI1n port function exchange control (only SPI mode)               */
+      __IOM uint32_t USTnSSEN   : 1;            /*!< [4..4] This bit controls the SS1n pin operation (only SPI mode)           */
+      __IOM uint32_t DISSCKn    : 1;            /*!< [5..5] In synchronous mode operation, selects the waveform of
+                                                     SCK1n output                                                              */
+      __IOM uint32_t LOOPSn     : 1;            /*!< [6..6] Control the Loop Back mode of USART1n for test mode                */
+      __IOM uint32_t MASTERn    : 1;            /*!< [7..7] Selects master or slave in SPI1n or Synchronous mode
+                                                     and controls the direction of SCK1n pin                                   */
+      __IOM uint32_t DBLSn      : 1;            /*!< [8..8] Selects receiver sampling rate (only UART mode)                    */
+      __IOM uint32_t USTnEN     : 1;            /*!< [9..9] Activate USART1n Block                                             */
+    } CR2_b;
+  } ;
+  __IM  uint32_t  RESERVED;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x0000000C) USART1n Status Register                                    */
+    
+    struct {
+      __IOM uint32_t PEn        : 1;            /*!< [0..0] This bit is set if the next character in the receive
+                                                     buffer has a Parity Error while parity is checked                         */
+      __IOM uint32_t FEn        : 1;            /*!< [1..1] This bit is set if the first stop bit of next character
+                                                     in the receive buffer is detected as '0'                                  */
+      __IM  uint32_t DORn       : 1;            /*!< [2..2] This bit is set if data OverRun takes place                        */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t WAKEn      : 1;            /*!< [4..4] Asynchronous Wake-Up Interrupt Flag                                */
+      __IM  uint32_t RXCn       : 1;            /*!< [5..5] Receive Complete Interrupt Flag                                    */
+      __IOM uint32_t TXCn       : 1;            /*!< [6..6] Transmit Complete Interrupt Flag                                   */
+      __IOM uint32_t DREn       : 1;            /*!< [7..7] Transmit Data Register Empty Interrupt Flag                        */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000010) USART1n Baud Rate Generation Register                      */
+    
+    struct {
+      __IOM uint32_t BDATA      : 12;           /*!< [11..0] The value in this register is used to generate internal
+                                                     baud rate in UART mode or to generate SCK clock in SPI
+                                                     mode                                                                      */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000014) USART1n Data Register                                      */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The USART Transmit buffer and Receive buffer share the
+                                                     same I/O address with this DATA register                                  */
+    } DR_b;
+  } ;
+} USART13_Type;                                 /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           UARTn                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief UART n (UARTn)
+  */
+
+typedef struct {                                /*!< (@ 0x55000000) UARTn Structure                                            */
+  
+  union {
+    union {
+      __IM  uint32_t RBR;                       /*!< (@ 0x00000000) UARTn Receive Data Buffer Register                         */
+      
+      struct {
+        __IM  uint32_t RBR      : 8;            /*!< [7..0] UARTn Receive Data Buffer                                          */
+      } RBR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t THR;                       /*!< (@ 0x00000000) UARTn Transmit Data Hold Register                          */
+      
+      struct {
+        __OM  uint32_t THR      : 8;            /*!< [7..0] UARTn Transmit Data Hold                                           */
+      } THR_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t IER;                         /*!< (@ 0x00000004) UARTn Interrupt Enable Register                            */
+    
+    struct {
+      __IOM uint32_t DRIE       : 1;            /*!< [0..0] Data Receive Interrupt Enable                                      */
+      __IOM uint32_t THREIE     : 1;            /*!< [1..1] Transmit Holding Register Empty Interrupt Enable                   */
+      __IOM uint32_t RLSIE      : 1;            /*!< [2..2] Receiver Line Status Interrupt Enable                              */
+      __IOM uint32_t TXEIE      : 1;            /*!< [3..3] Transmit Empty Interrupt Enable                                    */
+    } IER_b;
+  } ;
+  
+  union {
+    __IM  uint32_t IIR;                         /*!< (@ 0x00000008) UARTn Interrupt ID Register                                */
+    
+    struct {
+      __IM  uint32_t IPEN       : 1;            /*!< [0..0] Interrupt Pending                                                  */
+      __IM  uint32_t IID        : 2;            /*!< [2..1] UARTn Interrupt ID                                                 */
+      __IM  uint32_t            : 1;
+      __IM  uint32_t TXE        : 1;            /*!< [4..4] Transmit Complete Interrupt Source ID                              */
+    } IIR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t LCR;                         /*!< (@ 0x0000000C) UARTn Line Control Register                                */
+    
+    struct {
+      __IOM uint32_t DLEN       : 2;            /*!< [1..0] Data Length Selection                                              */
+      __IOM uint32_t STOPBIT    : 1;            /*!< [2..2] Stop Bit Length Selection                                          */
+      __IOM uint32_t PEN        : 1;            /*!< [3..3] Parity Bit Transfer Enable                                         */
+      __IOM uint32_t PARITY     : 1;            /*!< [4..4] Parity Mode and Parity Stuck Selection                             */
+      __IOM uint32_t STICKP     : 1;            /*!< [5..5] Force Parity                                                       */
+      __IOM uint32_t BREAK      : 1;            /*!< [6..6] Transfer Break Control                                             */
+    } LCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DCR;                         /*!< (@ 0x00000010) UARTn Data Control Register                                */
+    
+    struct {
+      __IM  uint32_t            : 2;
+      __IOM uint32_t TXINV      : 1;            /*!< [2..2] Transmit Data Inversion Selection                                  */
+      __IOM uint32_t RXINV      : 1;            /*!< [3..3] Receive Data Inversion Selection                                   */
+      __IOM uint32_t LBON       : 1;            /*!< [4..4] Local Loopback Test Mode Enable                                    */
+    } DCR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t LSR;                         /*!< (@ 0x00000014) UARTn Line Status Register                                 */
+    
+    struct {
+      __IM  uint32_t DR         : 1;            /*!< [0..0] Data Receive Indicator                                             */
+      __IM  uint32_t OE         : 1;            /*!< [1..1] Overrun Error Indicator                                            */
+      __IM  uint32_t PE         : 1;            /*!< [2..2] Parity Error Indicator                                             */
+      __IM  uint32_t FE         : 1;            /*!< [3..3] Frame Error Indicator                                              */
+      __IM  uint32_t BI         : 1;            /*!< [4..4] Break Condition Indication                                         */
+      __IM  uint32_t THRE       : 1;            /*!< [5..5] Transmit Hold Register Empty                                       */
+      __IM  uint32_t TEMT       : 1;            /*!< [6..6] Transmit Register Empty                                            */
+    } LSR_b;
+  } ;
+  __IM  uint32_t  RESERVED[2];
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000020) UARTn Baud Rate Divisor Latch Register                     */
+    
+    struct {
+      __IOM uint32_t BDR        : 16;           /*!< [15..0] Baud Rate Divider Latch Value                                     */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BFR;                         /*!< (@ 0x00000024) UARTn Baud Rate Fractional Counter Value                   */
+    
+    struct {
+      __IOM uint32_t BFR        : 8;            /*!< [7..0] Fraction Counter value                                             */
+    } BFR_b;
+  } ;
+  __IM  uint32_t  RESERVED1[2];
+  
+  union {
+    __IOM uint32_t IDTR;                        /*!< (@ 0x00000030) UARTn Inter-frame Delay Time Register                      */
+    
+    struct {
+      __IOM uint32_t WAITVAL    : 3;            /*!< [2..0] Wait Time Value                                                    */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t DMS        : 1;            /*!< [6..6] Data Bit Multi Sampling Enable                                     */
+      __IOM uint32_t SMS        : 1;            /*!< [7..7] Start Bit Multi Sampling Enable                                    */
+    } IDTR_b;
+  } ;
+} UARTn_Type;                                   /*!< Size = 52 (0x34)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           UART0                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief UART 0 (UART0)
+  */
+
+typedef struct {                                /*!< (@ 0x40004000) UART0 Structure                                            */
+  
+  union {
+    union {
+      __IM  uint32_t RBR;                       /*!< (@ 0x00000000) UARTn Receive Data Buffer Register                         */
+      
+      struct {
+        __IM  uint32_t RBR      : 8;            /*!< [7..0] UARTn Receive Data Buffer                                          */
+      } RBR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t THR;                       /*!< (@ 0x00000000) UARTn Transmit Data Hold Register                          */
+      
+      struct {
+        __OM  uint32_t THR      : 8;            /*!< [7..0] UARTn Transmit Data Hold                                           */
+      } THR_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t IER;                         /*!< (@ 0x00000004) UARTn Interrupt Enable Register                            */
+    
+    struct {
+      __IOM uint32_t DRIE       : 1;            /*!< [0..0] Data Receive Interrupt Enable                                      */
+      __IOM uint32_t THREIE     : 1;            /*!< [1..1] Transmit Holding Register Empty Interrupt Enable                   */
+      __IOM uint32_t RLSIE      : 1;            /*!< [2..2] Receiver Line Status Interrupt Enable                              */
+      __IOM uint32_t TXEIE      : 1;            /*!< [3..3] Transmit Empty Interrupt Enable                                    */
+    } IER_b;
+  } ;
+  
+  union {
+    __IM  uint32_t IIR;                         /*!< (@ 0x00000008) UARTn Interrupt ID Register                                */
+    
+    struct {
+      __IM  uint32_t IPEN       : 1;            /*!< [0..0] Interrupt Pending                                                  */
+      __IM  uint32_t IID        : 2;            /*!< [2..1] UARTn Interrupt ID                                                 */
+      __IM  uint32_t            : 1;
+      __IM  uint32_t TXE        : 1;            /*!< [4..4] Transmit Complete Interrupt Source ID                              */
+    } IIR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t LCR;                         /*!< (@ 0x0000000C) UARTn Line Control Register                                */
+    
+    struct {
+      __IOM uint32_t DLEN       : 2;            /*!< [1..0] Data Length Selection                                              */
+      __IOM uint32_t STOPBIT    : 1;            /*!< [2..2] Stop Bit Length Selection                                          */
+      __IOM uint32_t PEN        : 1;            /*!< [3..3] Parity Bit Transfer Enable                                         */
+      __IOM uint32_t PARITY     : 1;            /*!< [4..4] Parity Mode and Parity Stuck Selection                             */
+      __IOM uint32_t STICKP     : 1;            /*!< [5..5] Force Parity                                                       */
+      __IOM uint32_t BREAK      : 1;            /*!< [6..6] Transfer Break Control                                             */
+    } LCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DCR;                         /*!< (@ 0x00000010) UARTn Data Control Register                                */
+    
+    struct {
+      __IM  uint32_t            : 2;
+      __IOM uint32_t TXINV      : 1;            /*!< [2..2] Transmit Data Inversion Selection                                  */
+      __IOM uint32_t RXINV      : 1;            /*!< [3..3] Receive Data Inversion Selection                                   */
+      __IOM uint32_t LBON       : 1;            /*!< [4..4] Local Loopback Test Mode Enable                                    */
+    } DCR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t LSR;                         /*!< (@ 0x00000014) UARTn Line Status Register                                 */
+    
+    struct {
+      __IM  uint32_t DR         : 1;            /*!< [0..0] Data Receive Indicator                                             */
+      __IM  uint32_t OE         : 1;            /*!< [1..1] Overrun Error Indicator                                            */
+      __IM  uint32_t PE         : 1;            /*!< [2..2] Parity Error Indicator                                             */
+      __IM  uint32_t FE         : 1;            /*!< [3..3] Frame Error Indicator                                              */
+      __IM  uint32_t BI         : 1;            /*!< [4..4] Break Condition Indication                                         */
+      __IM  uint32_t THRE       : 1;            /*!< [5..5] Transmit Hold Register Empty                                       */
+      __IM  uint32_t TEMT       : 1;            /*!< [6..6] Transmit Register Empty                                            */
+    } LSR_b;
+  } ;
+  __IM  uint32_t  RESERVED[2];
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000020) UARTn Baud Rate Divisor Latch Register                     */
+    
+    struct {
+      __IOM uint32_t BDR        : 16;           /*!< [15..0] Baud Rate Divider Latch Value                                     */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BFR;                         /*!< (@ 0x00000024) UARTn Baud Rate Fractional Counter Value                   */
+    
+    struct {
+      __IOM uint32_t BFR        : 8;            /*!< [7..0] Fraction Counter value                                             */
+    } BFR_b;
+  } ;
+  __IM  uint32_t  RESERVED1[2];
+  
+  union {
+    __IOM uint32_t IDTR;                        /*!< (@ 0x00000030) UARTn Inter-frame Delay Time Register                      */
+    
+    struct {
+      __IOM uint32_t WAITVAL    : 3;            /*!< [2..0] Wait Time Value                                                    */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t DMS        : 1;            /*!< [6..6] Data Bit Multi Sampling Enable                                     */
+      __IOM uint32_t SMS        : 1;            /*!< [7..7] Start Bit Multi Sampling Enable                                    */
+    } IDTR_b;
+  } ;
+} UART0_Type;                                   /*!< Size = 52 (0x34)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           UART1                                           ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief UART 1 (UART1)
+  */
+
+typedef struct {                                /*!< (@ 0x40004100) UART1 Structure                                            */
+  
+  union {
+    union {
+      __IM  uint32_t RBR;                       /*!< (@ 0x00000000) UARTn Receive Data Buffer Register                         */
+      
+      struct {
+        __IM  uint32_t RBR      : 8;            /*!< [7..0] UARTn Receive Data Buffer                                          */
+      } RBR_b;
+    } ;
+    
+    union {
+      __OM  uint32_t THR;                       /*!< (@ 0x00000000) UARTn Transmit Data Hold Register                          */
+      
+      struct {
+        __OM  uint32_t THR      : 8;            /*!< [7..0] UARTn Transmit Data Hold                                           */
+      } THR_b;
+    } ;
+  };
+  
+  union {
+    __IOM uint32_t IER;                         /*!< (@ 0x00000004) UARTn Interrupt Enable Register                            */
+    
+    struct {
+      __IOM uint32_t DRIE       : 1;            /*!< [0..0] Data Receive Interrupt Enable                                      */
+      __IOM uint32_t THREIE     : 1;            /*!< [1..1] Transmit Holding Register Empty Interrupt Enable                   */
+      __IOM uint32_t RLSIE      : 1;            /*!< [2..2] Receiver Line Status Interrupt Enable                              */
+      __IOM uint32_t TXEIE      : 1;            /*!< [3..3] Transmit Empty Interrupt Enable                                    */
+    } IER_b;
+  } ;
+  
+  union {
+    __IM  uint32_t IIR;                         /*!< (@ 0x00000008) UARTn Interrupt ID Register                                */
+    
+    struct {
+      __IM  uint32_t IPEN       : 1;            /*!< [0..0] Interrupt Pending                                                  */
+      __IM  uint32_t IID        : 2;            /*!< [2..1] UARTn Interrupt ID                                                 */
+      __IM  uint32_t            : 1;
+      __IM  uint32_t TXE        : 1;            /*!< [4..4] Transmit Complete Interrupt Source ID                              */
+    } IIR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t LCR;                         /*!< (@ 0x0000000C) UARTn Line Control Register                                */
+    
+    struct {
+      __IOM uint32_t DLEN       : 2;            /*!< [1..0] Data Length Selection                                              */
+      __IOM uint32_t STOPBIT    : 1;            /*!< [2..2] Stop Bit Length Selection                                          */
+      __IOM uint32_t PEN        : 1;            /*!< [3..3] Parity Bit Transfer Enable                                         */
+      __IOM uint32_t PARITY     : 1;            /*!< [4..4] Parity Mode and Parity Stuck Selection                             */
+      __IOM uint32_t STICKP     : 1;            /*!< [5..5] Force Parity                                                       */
+      __IOM uint32_t BREAK      : 1;            /*!< [6..6] Transfer Break Control                                             */
+    } LCR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DCR;                         /*!< (@ 0x00000010) UARTn Data Control Register                                */
+    
+    struct {
+      __IM  uint32_t            : 2;
+      __IOM uint32_t TXINV      : 1;            /*!< [2..2] Transmit Data Inversion Selection                                  */
+      __IOM uint32_t RXINV      : 1;            /*!< [3..3] Receive Data Inversion Selection                                   */
+      __IOM uint32_t LBON       : 1;            /*!< [4..4] Local Loopback Test Mode Enable                                    */
+    } DCR_b;
+  } ;
+  
+  union {
+    __IM  uint32_t LSR;                         /*!< (@ 0x00000014) UARTn Line Status Register                                 */
+    
+    struct {
+      __IM  uint32_t DR         : 1;            /*!< [0..0] Data Receive Indicator                                             */
+      __IM  uint32_t OE         : 1;            /*!< [1..1] Overrun Error Indicator                                            */
+      __IM  uint32_t PE         : 1;            /*!< [2..2] Parity Error Indicator                                             */
+      __IM  uint32_t FE         : 1;            /*!< [3..3] Frame Error Indicator                                              */
+      __IM  uint32_t BI         : 1;            /*!< [4..4] Break Condition Indication                                         */
+      __IM  uint32_t THRE       : 1;            /*!< [5..5] Transmit Hold Register Empty                                       */
+      __IM  uint32_t TEMT       : 1;            /*!< [6..6] Transmit Register Empty                                            */
+    } LSR_b;
+  } ;
+  __IM  uint32_t  RESERVED[2];
+  
+  union {
+    __IOM uint32_t BDR;                         /*!< (@ 0x00000020) UARTn Baud Rate Divisor Latch Register                     */
+    
+    struct {
+      __IOM uint32_t BDR        : 16;           /*!< [15..0] Baud Rate Divider Latch Value                                     */
+    } BDR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BFR;                         /*!< (@ 0x00000024) UARTn Baud Rate Fractional Counter Value                   */
+    
+    struct {
+      __IOM uint32_t BFR        : 8;            /*!< [7..0] Fraction Counter value                                             */
+    } BFR_b;
+  } ;
+  __IM  uint32_t  RESERVED1[2];
+  
+  union {
+    __IOM uint32_t IDTR;                        /*!< (@ 0x00000030) UARTn Inter-frame Delay Time Register                      */
+    
+    struct {
+      __IOM uint32_t WAITVAL    : 3;            /*!< [2..0] Wait Time Value                                                    */
+      __IM  uint32_t            : 3;
+      __IOM uint32_t DMS        : 1;            /*!< [6..6] Data Bit Multi Sampling Enable                                     */
+      __IOM uint32_t SMS        : 1;            /*!< [7..7] Start Bit Multi Sampling Enable                                    */
+    } IDTR_b;
+  } ;
+} UART1_Type;                                   /*!< Size = 52 (0x34)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2Cn                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief I2C n (I2Cn)
+  */
+
+typedef struct {                                /*!< (@ 0x56000000) I2Cn Structure                                             */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) I2Cn Control Register                                      */
+    
+    struct {
+      __IOM uint32_t STARTCn    : 1;            /*!< [0..0] START Condition Generation when I2Cn is master                     */
+      __IOM uint32_t STOPCn     : 1;            /*!< [1..1] STOP Condition Generation when I2Cn is master                      */
+      __IM  uint32_t IMASTERn   : 1;            /*!< [2..2] Represent Operation Mode of I2Cn                                   */
+      __IOM uint32_t ACKnEN     : 1;            /*!< [3..3] Controls ACK signal generation at ninth SCL period                 */
+      __IOM uint32_t I2CnIFLAG  : 1;            /*!< [4..4] I2Cn Interrupt Flag                                                */
+      __IOM uint32_t I2CnIEN    : 1;            /*!< [5..5] I2Cn Interrupt Enable                                              */
+      __IOM uint32_t TXDLYENBn  : 1;            /*!< [6..6] SDHR Register Control                                              */
+      __IOM uint32_t I2CnEN     : 1;            /*!< [7..7] Activate I2Cn Block by supplying                                   */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x00000004) I2Cn Status Register                                       */
+    
+    struct {
+      __IOM uint32_t RXACKn     : 1;            /*!< [0..0] This bit shows the state of ACK signal                             */
+      __IM  uint32_t TMODEn     : 1;            /*!< [1..1] This bit is used to indicate whether I2C is transmitter
+                                                     or receiver                                                               */
+      __IOM uint32_t BUSYn      : 1;            /*!< [2..2] This bit reflects bus status                                       */
+      __IOM uint32_t MLOSTn     : 1;            /*!< [3..3] This bit represents the result of bus arbitration in
+                                                     master mode                                                               */
+      __IOM uint32_t SSELn      : 1;            /*!< [4..4] This bit is set when I2C is addressed by other master              */
+      __IOM uint32_t STOPDn     : 1;            /*!< [5..5] This bit is set when a STOP condition is detected                  */
+      __IOM uint32_t TENDn      : 1;            /*!< [6..6] This bit is set when 1-byte of data is transferred completely      */
+      __IOM uint32_t GCALLn     : 1;            /*!< [7..7] This bit has different meaning depending on whether I2C
+                                                     is master or slave. When I2C is a master, this bit represents
+                                                     whether it received AACK (address ACK) from slave. When
+                                                     I2C is a slave, this bit is used to indicate general call.                */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SAR1;                        /*!< (@ 0x00000008) I2Cn Slave Address Register 1                              */
+    
+    struct {
+      __IOM uint32_t GCALLnEN   : 1;            /*!< [0..0] This bit decides whether I2Cn allows general call address
+                                                     1 or not in I2Cn slave mode                                               */
+      __IOM uint32_t SLAn       : 7;            /*!< [7..1] These bits configure the slave address 1 in slave mode             */
+    } SAR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SAR2;                        /*!< (@ 0x0000000C) I2Cn Slave Address Register 2                              */
+    
+    struct {
+      __IOM uint32_t GCALLnEN   : 1;            /*!< [0..0] This bit decides whether I2Cn allows general call address
+                                                     2 or not in I2Cn slave mode                                               */
+      __IOM uint32_t SLAn       : 7;            /*!< [7..1] These bits configure the slave address 2 in slave mode             */
+    } SAR2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000010) I2Cn Data Register                                         */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The DR Transmit buffer and Receive buffer share the same
+                                                     I/O address with this DATA register                                       */
+    } DR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SDHR;                        /*!< (@ 0x00000014) I2Cn SDA Hold Time Register                                */
+    
+    struct {
+      __IOM uint32_t HLDT       : 12;           /*!< [11..0] This register is used to control SDA output timing from
+                                                     the falling edge of SCL                                                   */
+    } SDHR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCLR;                        /*!< (@ 0x00000018) I2Cn SCL Low Period Register                               */
+    
+    struct {
+      __IOM uint32_t SCLL       : 12;           /*!< [11..0] This register defines the low period of SCL in master
+                                                     mode                                                                      */
+    } SCLR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCHR;                        /*!< (@ 0x0000001C) I2Cn SCL High Period Register                              */
+    
+    struct {
+      __IOM uint32_t SCLH       : 12;           /*!< [11..0] This register defines the high period of SCL in master
+                                                     mode                                                                      */
+    } SCHR_b;
+  } ;
+} I2Cn_Type;                                    /*!< Size = 32 (0x20)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C0                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief I2C 0 (I2C0)
+  */
+
+typedef struct {                                /*!< (@ 0x40004800) I2C0 Structure                                             */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) I2Cn Control Register                                      */
+    
+    struct {
+      __IOM uint32_t STARTCn    : 1;            /*!< [0..0] START Condition Generation when I2Cn is master                     */
+      __IOM uint32_t STOPCn     : 1;            /*!< [1..1] STOP Condition Generation when I2Cn is master                      */
+      __IM  uint32_t IMASTERn   : 1;            /*!< [2..2] Represent Operation Mode of I2Cn                                   */
+      __IOM uint32_t ACKnEN     : 1;            /*!< [3..3] Controls ACK signal generation at ninth SCL period                 */
+      __IOM uint32_t I2CnIFLAG  : 1;            /*!< [4..4] I2Cn Interrupt Flag                                                */
+      __IOM uint32_t I2CnIEN    : 1;            /*!< [5..5] I2Cn Interrupt Enable                                              */
+      __IOM uint32_t TXDLYENBn  : 1;            /*!< [6..6] SDHR Register Control                                              */
+      __IOM uint32_t I2CnEN     : 1;            /*!< [7..7] Activate I2Cn Block by supplying                                   */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x00000004) I2Cn Status Register                                       */
+    
+    struct {
+      __IOM uint32_t RXACKn     : 1;            /*!< [0..0] This bit shows the state of ACK signal                             */
+      __IM  uint32_t TMODEn     : 1;            /*!< [1..1] This bit is used to indicate whether I2C is transmitter
+                                                     or receiver                                                               */
+      __IOM uint32_t BUSYn      : 1;            /*!< [2..2] This bit reflects bus status                                       */
+      __IOM uint32_t MLOSTn     : 1;            /*!< [3..3] This bit represents the result of bus arbitration in
+                                                     master mode                                                               */
+      __IOM uint32_t SSELn      : 1;            /*!< [4..4] This bit is set when I2C is addressed by other master              */
+      __IOM uint32_t STOPDn     : 1;            /*!< [5..5] This bit is set when a STOP condition is detected                  */
+      __IOM uint32_t TENDn      : 1;            /*!< [6..6] This bit is set when 1-byte of data is transferred completely      */
+      __IOM uint32_t GCALLn     : 1;            /*!< [7..7] This bit has different meaning depending on whether I2C
+                                                     is master or slave. When I2C is a master, this bit represents
+                                                     whether it received AACK (address ACK) from slave. When
+                                                     I2C is a slave, this bit is used to indicate general call.                */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SAR1;                        /*!< (@ 0x00000008) I2Cn Slave Address Register 1                              */
+    
+    struct {
+      __IOM uint32_t GCALLnEN   : 1;            /*!< [0..0] This bit decides whether I2Cn allows general call address
+                                                     1 or not in I2Cn slave mode                                               */
+      __IOM uint32_t SLAn       : 7;            /*!< [7..1] These bits configure the slave address 1 in slave mode             */
+    } SAR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SAR2;                        /*!< (@ 0x0000000C) I2Cn Slave Address Register 2                              */
+    
+    struct {
+      __IOM uint32_t GCALLnEN   : 1;            /*!< [0..0] This bit decides whether I2Cn allows general call address
+                                                     2 or not in I2Cn slave mode                                               */
+      __IOM uint32_t SLAn       : 7;            /*!< [7..1] These bits configure the slave address 2 in slave mode             */
+    } SAR2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000010) I2Cn Data Register                                         */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The DR Transmit buffer and Receive buffer share the same
+                                                     I/O address with this DATA register                                       */
+    } DR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SDHR;                        /*!< (@ 0x00000014) I2Cn SDA Hold Time Register                                */
+    
+    struct {
+      __IOM uint32_t HLDT       : 12;           /*!< [11..0] This register is used to control SDA output timing from
+                                                     the falling edge of SCL                                                   */
+    } SDHR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCLR;                        /*!< (@ 0x00000018) I2Cn SCL Low Period Register                               */
+    
+    struct {
+      __IOM uint32_t SCLL       : 12;           /*!< [11..0] This register defines the low period of SCL in master
+                                                     mode                                                                      */
+    } SCLR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCHR;                        /*!< (@ 0x0000001C) I2Cn SCL High Period Register                              */
+    
+    struct {
+      __IOM uint32_t SCLH       : 12;           /*!< [11..0] This register defines the high period of SCL in master
+                                                     mode                                                                      */
+    } SCHR_b;
+  } ;
+} I2C0_Type;                                    /*!< Size = 32 (0x20)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C1                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief I2C 1 (I2C1)
+  */
+
+typedef struct {                                /*!< (@ 0x40004900) I2C1 Structure                                             */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) I2Cn Control Register                                      */
+    
+    struct {
+      __IOM uint32_t STARTCn    : 1;            /*!< [0..0] START Condition Generation when I2Cn is master                     */
+      __IOM uint32_t STOPCn     : 1;            /*!< [1..1] STOP Condition Generation when I2Cn is master                      */
+      __IM  uint32_t IMASTERn   : 1;            /*!< [2..2] Represent Operation Mode of I2Cn                                   */
+      __IOM uint32_t ACKnEN     : 1;            /*!< [3..3] Controls ACK signal generation at ninth SCL period                 */
+      __IOM uint32_t I2CnIFLAG  : 1;            /*!< [4..4] I2Cn Interrupt Flag                                                */
+      __IOM uint32_t I2CnIEN    : 1;            /*!< [5..5] I2Cn Interrupt Enable                                              */
+      __IOM uint32_t TXDLYENBn  : 1;            /*!< [6..6] SDHR Register Control                                              */
+      __IOM uint32_t I2CnEN     : 1;            /*!< [7..7] Activate I2Cn Block by supplying                                   */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x00000004) I2Cn Status Register                                       */
+    
+    struct {
+      __IOM uint32_t RXACKn     : 1;            /*!< [0..0] This bit shows the state of ACK signal                             */
+      __IM  uint32_t TMODEn     : 1;            /*!< [1..1] This bit is used to indicate whether I2C is transmitter
+                                                     or receiver                                                               */
+      __IOM uint32_t BUSYn      : 1;            /*!< [2..2] This bit reflects bus status                                       */
+      __IOM uint32_t MLOSTn     : 1;            /*!< [3..3] This bit represents the result of bus arbitration in
+                                                     master mode                                                               */
+      __IOM uint32_t SSELn      : 1;            /*!< [4..4] This bit is set when I2C is addressed by other master              */
+      __IOM uint32_t STOPDn     : 1;            /*!< [5..5] This bit is set when a STOP condition is detected                  */
+      __IOM uint32_t TENDn      : 1;            /*!< [6..6] This bit is set when 1-byte of data is transferred completely      */
+      __IOM uint32_t GCALLn     : 1;            /*!< [7..7] This bit has different meaning depending on whether I2C
+                                                     is master or slave. When I2C is a master, this bit represents
+                                                     whether it received AACK (address ACK) from slave. When
+                                                     I2C is a slave, this bit is used to indicate general call.                */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SAR1;                        /*!< (@ 0x00000008) I2Cn Slave Address Register 1                              */
+    
+    struct {
+      __IOM uint32_t GCALLnEN   : 1;            /*!< [0..0] This bit decides whether I2Cn allows general call address
+                                                     1 or not in I2Cn slave mode                                               */
+      __IOM uint32_t SLAn       : 7;            /*!< [7..1] These bits configure the slave address 1 in slave mode             */
+    } SAR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SAR2;                        /*!< (@ 0x0000000C) I2Cn Slave Address Register 2                              */
+    
+    struct {
+      __IOM uint32_t GCALLnEN   : 1;            /*!< [0..0] This bit decides whether I2Cn allows general call address
+                                                     2 or not in I2Cn slave mode                                               */
+      __IOM uint32_t SLAn       : 7;            /*!< [7..1] These bits configure the slave address 2 in slave mode             */
+    } SAR2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000010) I2Cn Data Register                                         */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The DR Transmit buffer and Receive buffer share the same
+                                                     I/O address with this DATA register                                       */
+    } DR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SDHR;                        /*!< (@ 0x00000014) I2Cn SDA Hold Time Register                                */
+    
+    struct {
+      __IOM uint32_t HLDT       : 12;           /*!< [11..0] This register is used to control SDA output timing from
+                                                     the falling edge of SCL                                                   */
+    } SDHR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCLR;                        /*!< (@ 0x00000018) I2Cn SCL Low Period Register                               */
+    
+    struct {
+      __IOM uint32_t SCLL       : 12;           /*!< [11..0] This register defines the low period of SCL in master
+                                                     mode                                                                      */
+    } SCLR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCHR;                        /*!< (@ 0x0000001C) I2Cn SCL High Period Register                              */
+    
+    struct {
+      __IOM uint32_t SCLH       : 12;           /*!< [11..0] This register defines the high period of SCL in master
+                                                     mode                                                                      */
+    } SCHR_b;
+  } ;
+} I2C1_Type;                                    /*!< Size = 32 (0x20)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C2                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief I2C 2 (I2C2)
+  */
+
+typedef struct {                                /*!< (@ 0x40004A00) I2C2 Structure                                             */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) I2Cn Control Register                                      */
+    
+    struct {
+      __IOM uint32_t STARTCn    : 1;            /*!< [0..0] START Condition Generation when I2Cn is master                     */
+      __IOM uint32_t STOPCn     : 1;            /*!< [1..1] STOP Condition Generation when I2Cn is master                      */
+      __IM  uint32_t IMASTERn   : 1;            /*!< [2..2] Represent Operation Mode of I2Cn                                   */
+      __IOM uint32_t ACKnEN     : 1;            /*!< [3..3] Controls ACK signal generation at ninth SCL period                 */
+      __IOM uint32_t I2CnIFLAG  : 1;            /*!< [4..4] I2Cn Interrupt Flag                                                */
+      __IOM uint32_t I2CnIEN    : 1;            /*!< [5..5] I2Cn Interrupt Enable                                              */
+      __IOM uint32_t TXDLYENBn  : 1;            /*!< [6..6] SDHR Register Control                                              */
+      __IOM uint32_t I2CnEN     : 1;            /*!< [7..7] Activate I2Cn Block by supplying                                   */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t ST;                          /*!< (@ 0x00000004) I2Cn Status Register                                       */
+    
+    struct {
+      __IOM uint32_t RXACKn     : 1;            /*!< [0..0] This bit shows the state of ACK signal                             */
+      __IM  uint32_t TMODEn     : 1;            /*!< [1..1] This bit is used to indicate whether I2C is transmitter
+                                                     or receiver                                                               */
+      __IOM uint32_t BUSYn      : 1;            /*!< [2..2] This bit reflects bus status                                       */
+      __IOM uint32_t MLOSTn     : 1;            /*!< [3..3] This bit represents the result of bus arbitration in
+                                                     master mode                                                               */
+      __IOM uint32_t SSELn      : 1;            /*!< [4..4] This bit is set when I2C is addressed by other master              */
+      __IOM uint32_t STOPDn     : 1;            /*!< [5..5] This bit is set when a STOP condition is detected                  */
+      __IOM uint32_t TENDn      : 1;            /*!< [6..6] This bit is set when 1-byte of data is transferred completely      */
+      __IOM uint32_t GCALLn     : 1;            /*!< [7..7] This bit has different meaning depending on whether I2C
+                                                     is master or slave. When I2C is a master, this bit represents
+                                                     whether it received AACK (address ACK) from slave. When
+                                                     I2C is a slave, this bit is used to indicate general call.                */
+    } ST_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SAR1;                        /*!< (@ 0x00000008) I2Cn Slave Address Register 1                              */
+    
+    struct {
+      __IOM uint32_t GCALLnEN   : 1;            /*!< [0..0] This bit decides whether I2Cn allows general call address
+                                                     1 or not in I2Cn slave mode                                               */
+      __IOM uint32_t SLAn       : 7;            /*!< [7..1] These bits configure the slave address 1 in slave mode             */
+    } SAR1_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SAR2;                        /*!< (@ 0x0000000C) I2Cn Slave Address Register 2                              */
+    
+    struct {
+      __IOM uint32_t GCALLnEN   : 1;            /*!< [0..0] This bit decides whether I2Cn allows general call address
+                                                     2 or not in I2Cn slave mode                                               */
+      __IOM uint32_t SLAn       : 7;            /*!< [7..1] These bits configure the slave address 2 in slave mode             */
+    } SAR2_b;
+  } ;
+  
+  union {
+    __IOM uint32_t DR;                          /*!< (@ 0x00000010) I2Cn Data Register                                         */
+    
+    struct {
+      __IOM uint32_t DATA       : 8;            /*!< [7..0] The DR Transmit buffer and Receive buffer share the same
+                                                     I/O address with this DATA register                                       */
+    } DR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SDHR;                        /*!< (@ 0x00000014) I2Cn SDA Hold Time Register                                */
+    
+    struct {
+      __IOM uint32_t HLDT       : 12;           /*!< [11..0] This register is used to control SDA output timing from
+                                                     the falling edge of SCL                                                   */
+    } SDHR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCLR;                        /*!< (@ 0x00000018) I2Cn SCL Low Period Register                               */
+    
+    struct {
+      __IOM uint32_t SCLL       : 12;           /*!< [11..0] This register defines the low period of SCL in master
+                                                     mode                                                                      */
+    } SCLR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SCHR;                        /*!< (@ 0x0000001C) I2Cn SCL High Period Register                              */
+    
+    struct {
+      __IOM uint32_t SCLH       : 12;           /*!< [11..0] This register defines the high period of SCL in master
+                                                     mode                                                                      */
+    } SCHR_b;
+  } ;
+} I2C2_Type;                                    /*!< Size = 32 (0x20)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            LCD                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief LCD Driver (LCD)
+  */
+
+typedef struct {                                /*!< (@ 0x40005000) LCD Structure                                              */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) LCD Driver Control Register                                */
+    
+    struct {
+      __IOM uint32_t DISP       : 1;            /*!< [0..0] LCD Display Control                                                */
+      __IOM uint32_t LCLK       : 2;            /*!< [2..1] LCD Clock Selection (When fLCD = 32.768kHz)                        */
+      __IOM uint32_t DBS        : 3;            /*!< [5..3] LCD Duty and Bias Selection                                        */
+      __IOM uint32_t IRSEL      : 2;            /*!< [7..6] Internal LCD Bias Dividing Resistor Selection                      */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t BCCR;                        /*!< (@ 0x00000004) LCD Automatic Bias and Contrast Control Register           */
+    
+    struct {
+      __IOM uint32_t VLCD       : 4;            /*!< [3..0] VLC0 Voltage Control when the contrast is enabled                  */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LCTEN      : 1;            /*!< [5..5] LCD Driver Contrast Control                                        */
+      __IM  uint32_t            : 2;
+      __IOM uint32_t BMSEL      : 3;            /*!< [10..8] 'Bias Mode A' Time Selection                                      */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t LCDABC     : 1;            /*!< [12..12] LCD Automatic Bias Control                                       */
+    } BCCR_b;
+  } ;
+  __IM  uint32_t  RESERVED[2];
+  __IOM uint8_t   DR0;                          /*!< (@ 0x00000010) LCD Display Data Register 0                                */
+  __IOM uint8_t   DR1;                          /*!< (@ 0x00000011) LCD Display Data Register 1                                */
+  __IOM uint8_t   DR2;                          /*!< (@ 0x00000012) LCD Display Data Register 2                                */
+  __IOM uint8_t   DR3;                          /*!< (@ 0x00000013) LCD Display Data Register 3                                */
+  __IOM uint8_t   DR4;                          /*!< (@ 0x00000014) LCD Display Data Register 4                                */
+  __IOM uint8_t   DR5;                          /*!< (@ 0x00000015) LCD Display Data Register 5                                */
+  __IOM uint8_t   DR6;                          /*!< (@ 0x00000016) LCD Display Data Register 6                                */
+  __IOM uint8_t   DR7;                          /*!< (@ 0x00000017) LCD Display Data Register 7                                */
+  __IOM uint8_t   DR8;                          /*!< (@ 0x00000018) LCD Display Data Register 8                                */
+  __IOM uint8_t   DR9;                          /*!< (@ 0x00000019) LCD Display Data Register 9                                */
+  __IOM uint8_t   DR10;                         /*!< (@ 0x0000001A) LCD Display Data Register 10                               */
+  __IOM uint8_t   DR11;                         /*!< (@ 0x0000001B) LCD Display Data Register 11                               */
+  __IOM uint8_t   DR12;                         /*!< (@ 0x0000001C) LCD Display Data Register 12                               */
+  __IOM uint8_t   DR13;                         /*!< (@ 0x0000001D) LCD Display Data Register 13                               */
+  __IOM uint8_t   DR14;                         /*!< (@ 0x0000001E) LCD Display Data Register 14                               */
+  __IOM uint8_t   DR15;                         /*!< (@ 0x0000001F) LCD Display Data Register 15                               */
+  __IOM uint8_t   DR16;                         /*!< (@ 0x00000020) LCD Display Data Register 16                               */
+  __IOM uint8_t   DR17;                         /*!< (@ 0x00000021) LCD Display Data Register 17                               */
+  __IOM uint8_t   DR18;                         /*!< (@ 0x00000022) LCD Display Data Register 18                               */
+  __IOM uint8_t   DR19;                         /*!< (@ 0x00000023) LCD Display Data Register 19                               */
+  __IOM uint8_t   DR20;                         /*!< (@ 0x00000024) LCD Display Data Register 20                               */
+  __IOM uint8_t   DR21;                         /*!< (@ 0x00000025) LCD Display Data Register 21                               */
+  __IOM uint8_t   DR22;                         /*!< (@ 0x00000026) LCD Display Data Register 22                               */
+  __IOM uint8_t   DR23;                         /*!< (@ 0x00000027) LCD Display Data Register 23                               */
+  __IOM uint8_t   DR24;                         /*!< (@ 0x00000028) LCD Display Data Register 24                               */
+  __IOM uint8_t   DR25;                         /*!< (@ 0x00000029) LCD Display Data Register 25                               */
+  __IOM uint8_t   DR26;                         /*!< (@ 0x0000002A) LCD Display Data Register 26                               */
+  __IOM uint8_t   DR27;                         /*!< (@ 0x0000002B) LCD Display Data Register 27                               */
+  __IOM uint8_t   DR28;                         /*!< (@ 0x0000002C) LCD Display Data Register 28                               */
+  __IOM uint8_t   DR29;                         /*!< (@ 0x0000002D) LCD Display Data Register 29                               */
+  __IOM uint8_t   DR30;                         /*!< (@ 0x0000002E) LCD Display Data Register 30                               */
+  __IOM uint8_t   DR31;                         /*!< (@ 0x0000002F) LCD Display Data Register 31                               */
+  __IOM uint8_t   DR32;                         /*!< (@ 0x00000030) LCD Display Data Register 32                               */
+  __IOM uint8_t   DR33;                         /*!< (@ 0x00000031) LCD Display Data Register 33                               */
+  __IOM uint8_t   DR34;                         /*!< (@ 0x00000032) LCD Display Data Register 34                               */
+  __IOM uint8_t   DR35;                         /*!< (@ 0x00000033) LCD Display Data Register 35                               */
+  __IOM uint8_t   DR36;                         /*!< (@ 0x00000034) LCD Display Data Register 36                               */
+  __IOM uint8_t   DR37;                         /*!< (@ 0x00000035) LCD Display Data Register 37                               */
+  __IOM uint8_t   DR38;                         /*!< (@ 0x00000036) LCD Display Data Register 38                               */
+  __IOM uint8_t   DR39;                         /*!< (@ 0x00000037) LCD Display Data Register 39                               */
+  __IOM uint8_t   DR40;                         /*!< (@ 0x00000038) LCD Display Data Register 40                               */
+  __IOM uint8_t   DR41;                         /*!< (@ 0x00000039) LCD Display Data Register 41                               */
+  __IOM uint8_t   DR42;                         /*!< (@ 0x0000003A) LCD Display Data Register 42                               */
+  __IOM uint8_t   DR43;                         /*!< (@ 0x0000003B) LCD Display Data Register 43                               */
+} LCD_Type;                                     /*!< Size = 60 (0x3c)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            CRC                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Cyclic Redundancy Check and Checksum (CRC)
+  */
+
+typedef struct {                                /*!< (@ 0x30001000) CRC Structure                                              */
+  
+  union {
+    __IOM uint32_t CR;                          /*!< (@ 0x00000000) CRC/Checksum Control Register                              */
+    
+    struct {
+      __IOM uint32_t CRCRUN     : 1;            /*!< [0..0] CRC/Checksum Start Control and Busy                                */
+      __IOM uint32_t FIRSTBS    : 1;            /*!< [1..1] First Shifted-in Selection (CRC only)                              */
+      __IM  uint32_t            : 1;
+      __IOM uint32_t SARINC     : 1;            /*!< [3..3] CRC/Checksum Start Address Auto Increment Control (User
+                                                     mode only)                                                                */
+      __IOM uint32_t POLYS      : 1;            /*!< [4..4] Polynomial Selection (CRC only)                                    */
+      __IOM uint32_t MDSEL      : 1;            /*!< [5..5] CRC/Checksum Selection                                             */
+      __IOM uint32_t RLTCLR     : 1;            /*!< [6..6] CRC/Checksum Result Data Register (CRCRLT) Initialization          */
+      __IOM uint32_t MODS       : 1;            /*!< [7..7] User/Auto Mode Selection                                           */
+    } CR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t IN;                          /*!< (@ 0x00000004) CRC/Checksum Input Data Register                           */
+    
+    struct {
+      __IOM uint32_t INDATA     : 32;           /*!< [31..0] CRC Input Data                                                    */
+    } IN_b;
+  } ;
+  
+  union {
+    __IM  uint32_t RLT;                         /*!< (@ 0x00000008) CRC/Checksum Result Data Register                          */
+    
+    struct {
+      __IM  uint32_t RLTDATA    : 16;           /*!< [15..0] CRC Result Data                                                   */
+    } RLT_b;
+  } ;
+  
+  union {
+    __IOM uint32_t INIT;                        /*!< (@ 0x0000000C) CRC/Checksum Initial Data Register                         */
+    
+    struct {
+      __IOM uint32_t INIDATA    : 16;           /*!< [15..0] CRC Initial Data                                                  */
+    } INIT_b;
+  } ;
+  
+  union {
+    __IOM uint32_t SADR;                        /*!< (@ 0x00000010) CRC/Checksum Start Address Register                        */
+    
+    struct {
+      __IM  uint32_t            : 2;
+      __IOM uint32_t SADR       : 30;           /*!< [31..2] CRC Start Address                                                 */
+    } SADR_b;
+  } ;
+  
+  union {
+    __IOM uint32_t EADR;                        /*!< (@ 0x00000014) CRC/Checksum End Address Register                          */
+    
+    struct {
+      __IM  uint32_t            : 2;
+      __IOM uint32_t EADR       : 30;           /*!< [31..2] CRC End Address                                                   */
+    } EADR_b;
+  } ;
+} CRC_Type;                                     /*!< Size = 24 (0x18)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA0                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Configuration Option Area Page 0: System Related Trimming Value (COA0)
+  */
+
+typedef struct {                                /*!< (@ 0x1FFFF000) COA0 Structure                                             */
+  __IM  uint32_t  TRIM00;                       /*!< (@ 0x00000000) System Related Trim Value 00                               */
+  __IM  uint32_t  TRIM01;                       /*!< (@ 0x00000004) System Related Trim Value 01                               */
+  __IM  uint32_t  TRIM02;                       /*!< (@ 0x00000008) System Related Trim Value 02                               */
+  __IM  uint32_t  TRIM03;                       /*!< (@ 0x0000000C) System Related Trim Value 03                               */
+  __IM  uint32_t  TRIM04;                       /*!< (@ 0x00000010) System Related Trim Value 04                               */
+  __IM  uint32_t  TRIM05;                       /*!< (@ 0x00000014) System Related Trim Value 05                               */
+  __IM  uint32_t  TRIM06;                       /*!< (@ 0x00000018) System Related Trim Value 06                               */
+  __IM  uint32_t  TRIM07;                       /*!< (@ 0x0000001C) System Related Trim Value 07                               */
+  __IM  uint32_t  TRIM08;                       /*!< (@ 0x00000020) System Related Trim Value 08                               */
+  __IM  uint32_t  TRIM09;                       /*!< (@ 0x00000024) System Related Trim Value 09                               */
+  __IM  uint32_t  TRIM10;                       /*!< (@ 0x00000028) System Related Trim Value 10                               */
+  __IM  uint32_t  TRIM11;                       /*!< (@ 0x0000002C) System Related Trim Value 11                               */
+  __IM  uint32_t  TRIM12;                       /*!< (@ 0x00000030) System Related Trim Value 12                               */
+  __IM  uint32_t  TRIM13;                       /*!< (@ 0x00000034) System Related Trim Value 13                               */
+  __IM  uint32_t  TRIM14;                       /*!< (@ 0x00000038) System Related Trim Value 14                               */
+  __IM  uint32_t  TRIM15;                       /*!< (@ 0x0000003C) System Related Trim Value 15                               */
+  __IM  uint32_t  TRIM16;                       /*!< (@ 0x00000040) System Related Trim Value 16                               */
+  __IM  uint32_t  TRIM17;                       /*!< (@ 0x00000044) System Related Trim Value 17                               */
+  __IM  uint32_t  TRIM18;                       /*!< (@ 0x00000048) System Related Trim Value 18                               */
+  __IM  uint32_t  TRIM19;                       /*!< (@ 0x0000004C) System Related Trim Value 19                               */
+  
+  union {
+    __IM  uint32_t CONF_MF1CNFIG;               /*!< (@ 0x00000050) Manufacture Information 1                                  */
+    
+    struct {
+      __IM  uint32_t XYCDN      : 32;           /*!< [31..0] X and Y Coordinates                                               */
+    } CONF_MF1CNFIG_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CONF_MF2CNFIG;               /*!< (@ 0x00000054) Manufacture Information 2                                  */
+    
+    struct {
+      __IM  uint32_t WAFNO      : 8;            /*!< [7..0] Wafer Number                                                       */
+      __IM  uint32_t LOTNO      : 24;           /*!< [31..8] Lot Number [23:0]                                                 */
+    } CONF_MF2CNFIG_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CONF_MF3CNFIG;               /*!< (@ 0x00000058) Manufacture Information 3                                  */
+    
+    struct {
+      __IM  uint32_t LOTNO      : 32;           /*!< [31..0] Lot Number [55:24]                                                */
+    } CONF_MF3CNFIG_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CONF_MF4CNFIG;               /*!< (@ 0x0000005C) Manufacture Information 4                                  */
+    
+    struct {
+      __IM  uint32_t LOTNO      : 32;           /*!< [31..0] Lot Number [87:56]                                                */
+    } CONF_MF4CNFIG_b;
+  } ;
+  __IM  uint32_t  TRIM24;                       /*!< (@ 0x00000060) System Related Trim Value 24                               */
+  __IM  uint32_t  TRIM25;                       /*!< (@ 0x00000064) System Related Trim Value 25                               */
+  __IM  uint32_t  TRIM26;                       /*!< (@ 0x00000068) System Related Trim Value 26                               */
+  __IM  uint32_t  TRIM27;                       /*!< (@ 0x0000006C) System Related Trim Value 27                               */
+  __IM  uint32_t  TRIM28;                       /*!< (@ 0x00000070) System Related Trim Value 28                               */
+  __IM  uint32_t  TRIM29;                       /*!< (@ 0x00000074) System Related Trim Value 29                               */
+  __IM  uint32_t  TRIM30;                       /*!< (@ 0x00000078) System Related Trim Value 30                               */
+  __IM  uint32_t  TRIM31;                       /*!< (@ 0x0000007C) System Related Trim Value 31                               */
+} COA0_Type;                                    /*!< Size = 128 (0x80)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA1                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Configuration Option Area Page 1: User Option (COA1)
+  */
+
+typedef struct {                                /*!< (@ 0x1FFFF200) COA1 Structure                                             */
+  
+  union {
+    __IM  uint32_t RPCNFIG;                     /*!< (@ 0x00000000) Configuration for Read Protection                          */
+    
+    struct {
+      __IM  uint32_t READP      : 2;            /*!< [1..0] Read Protection for Flash Memory Area                              */
+      __IM  uint32_t            : 2;
+      __IM  uint32_t WTIDKY     : 28;           /*!< [31..4] Write Identification Key (0x69c8a27)                              */
+    } RPCNFIG_b;
+  } ;
+  __IM  uint32_t  RESERVED[2];
+  
+  union {
+    __IM  uint32_t WDTCNFIG;                    /*!< (@ 0x0000000C) Configuration for Watch-Dog Timer                          */
+    
+    struct {
+      __IM  uint32_t WCNTMF     : 1;            /*!< [0..0] Watch-Dog Timer Counter Enable Master Configuration                */
+      __IM  uint32_t WRSTMF     : 1;            /*!< [1..1] Watch-Dog Timer Reset Enable Master Configuration                  */
+      __IM  uint32_t WCLKMF     : 1;            /*!< [2..2] Watch-Dog Timer Clock Selection Master Configuration               */
+      __IM  uint32_t            : 1;
+      __IM  uint32_t WRCMF      : 12;           /*!< [15..4] Watch-Dog Timer RC Oscillator Master Configuration                */
+    } WDTCNFIG_b;
+  } ;
+  
+  union {
+    __IM  uint32_t LVRCNFIG;                    /*!< (@ 0x00000010) Configuration for Low Voltage Reset                        */
+    
+    struct {
+      __IM  uint32_t LVRVS      : 4;            /*!< [3..0] LVR Voltage Selection                                              */
+      __IM  uint32_t            : 4;
+      __IM  uint32_t LVRENM     : 8;            /*!< [15..8] LVR Reset Operation Control Master Configuration                  */
+    } LVRCNFIG_b;
+  } ;
+  
+  union {
+    __IM  uint32_t CNFIGWTP1;                   /*!< (@ 0x00000014) Erase/Write Protection for Configure Option Page
+                                                                    1/2/3                                                      */
+    
+    struct {
+      __IM  uint32_t CP1WP      : 1;            /*!< [0..0] Configure Option Page 1 Erase/Write Protection                     */
+      __IM  uint32_t CP2WP      : 1;            /*!< [1..1] Configure Option Page 2 Erase/Write Protection                     */
+      __IM  uint32_t CP3WP      : 1;            /*!< [2..2] Configure Option Page 3 Erase/Write Protection                     */
+    } CNFIGWTP1_b;
+  } ;
+  __IM  uint32_t  RESERVED1[10];
+  
+  union {
+    __IM  uint32_t FMWTP1;                      /*!< (@ 0x00000040) Erase/Write Protection for Flash Memory                    */
+    
+    struct {
+      __IM  uint32_t SWTP0      : 1;            /*!< [0..0] Flash Memory Erase/Write Protection 0                              */
+      __IM  uint32_t SWTP1      : 1;            /*!< [1..1] Flash Memory Erase/Write Protection 1                              */
+      __IM  uint32_t SWTP2      : 1;            /*!< [2..2] Flash Memory Erase/Write Protection 2                              */
+      __IM  uint32_t SWTP3      : 1;            /*!< [3..3] Flash Memory Erase/Write Protection 3                              */
+      __IM  uint32_t SWTP4      : 1;            /*!< [4..4] Flash Memory Erase/Write Protection 4                              */
+      __IM  uint32_t SWTP5      : 1;            /*!< [5..5] Flash Memory Erase/Write Protection 5                              */
+      __IM  uint32_t SWTP6      : 1;            /*!< [6..6] Flash Memory Erase/Write Protection 6                              */
+      __IM  uint32_t SWTP7      : 1;            /*!< [7..7] Flash Memory Erase/Write Protection 7                              */
+      __IM  uint32_t SWTP8      : 1;            /*!< [8..8] Flash Memory Erase/Write Protection 8                              */
+      __IM  uint32_t SWTP9      : 1;            /*!< [9..9] Flash Memory Erase/Write Protection 9                              */
+      __IM  uint32_t SWTP10     : 1;            /*!< [10..10] Flash Memory Erase/Write Protection 10                           */
+      __IM  uint32_t SWTP11     : 1;            /*!< [11..11] Flash Memory Erase/Write Protection 11                           */
+      __IM  uint32_t SWTP12     : 1;            /*!< [12..12] Flash Memory Erase/Write Protection 12                           */
+      __IM  uint32_t SWTP13     : 1;            /*!< [13..13] Flash Memory Erase/Write Protection 13                           */
+      __IM  uint32_t SWTP14     : 1;            /*!< [14..14] Flash Memory Erase/Write Protection 14                           */
+      __IM  uint32_t SWTP15     : 1;            /*!< [15..15] Flash Memory Erase/Write Protection 15                           */
+      __IM  uint32_t SWTP16     : 1;            /*!< [16..16] Flash Memory Erase/Write Protection 16                           */
+      __IM  uint32_t SWTP17     : 1;            /*!< [17..17] Flash Memory Erase/Write Protection 17                           */
+      __IM  uint32_t SWTP18     : 1;            /*!< [18..18] Flash Memory Erase/Write Protection 18                           */
+      __IM  uint32_t SWTP19     : 1;            /*!< [19..19] Flash Memory Erase/Write Protection 19                           */
+      __IM  uint32_t SWTP20     : 1;            /*!< [20..20] Flash Memory Erase/Write Protection 20                           */
+      __IM  uint32_t SWTP21     : 1;            /*!< [21..21] Flash Memory Erase/Write Protection 21                           */
+      __IM  uint32_t SWTP22     : 1;            /*!< [22..22] Flash Memory Erase/Write Protection 22                           */
+      __IM  uint32_t SWTP23     : 1;            /*!< [23..23] Flash Memory Erase/Write Protection 23                           */
+      __IM  uint32_t SWTP24     : 1;            /*!< [24..24] Flash Memory Erase/Write Protection 24                           */
+      __IM  uint32_t SWTP25     : 1;            /*!< [25..25] Flash Memory Erase/Write Protection 25                           */
+      __IM  uint32_t SWTP26     : 1;            /*!< [26..26] Flash Memory Erase/Write Protection 26                           */
+      __IM  uint32_t SWTP27     : 1;            /*!< [27..27] Flash Memory Erase/Write Protection 27                           */
+      __IM  uint32_t SWTP28     : 1;            /*!< [28..28] Flash Memory Erase/Write Protection 28                           */
+      __IM  uint32_t SWTP29     : 1;            /*!< [29..29] Flash Memory Erase/Write Protection 29                           */
+      __IM  uint32_t SWTP30     : 1;            /*!< [30..30] Flash Memory Erase/Write Protection 30                           */
+      __IM  uint32_t SWTP31     : 1;            /*!< [31..31] Flash Memory Erase/Write Protection 31                           */
+    } FMWTP1_b;
+  } ;
+} COA1_Type;                                    /*!< Size = 68 (0x44)                                                          */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA2                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Configuration Option Area Page 2: User Data Area 0 (COA2)
+  */
+
+typedef struct {                                /*!< (@ 0x1FFFF400) COA2 Structure                                             */
+  __IM  uint32_t  UDATA00;                      /*!< (@ 0x00000000) User Data 00                                               */
+  __IM  uint32_t  UDATA01;                      /*!< (@ 0x00000004) User Data 01                                               */
+  __IM  uint32_t  UDATA02;                      /*!< (@ 0x00000008) User Data 02                                               */
+  __IM  uint32_t  UDATA03;                      /*!< (@ 0x0000000C) User Data 03                                               */
+  __IM  uint32_t  UDATA04;                      /*!< (@ 0x00000010) User Data 04                                               */
+  __IM  uint32_t  UDATA05;                      /*!< (@ 0x00000014) User Data 05                                               */
+  __IM  uint32_t  UDATA06;                      /*!< (@ 0x00000018) User Data 06                                               */
+  __IM  uint32_t  UDATA07;                      /*!< (@ 0x0000001C) User Data 07                                               */
+  __IM  uint32_t  UDATA08;                      /*!< (@ 0x00000020) User Data 08                                               */
+  __IM  uint32_t  UDATA09;                      /*!< (@ 0x00000024) User Data 09                                               */
+  __IM  uint32_t  UDATA10;                      /*!< (@ 0x00000028) User Data 10                                               */
+  __IM  uint32_t  UDATA11;                      /*!< (@ 0x0000002C) User Data 11                                               */
+  __IM  uint32_t  UDATA12;                      /*!< (@ 0x00000030) User Data 12                                               */
+  __IM  uint32_t  UDATA13;                      /*!< (@ 0x00000034) User Data 13                                               */
+  __IM  uint32_t  UDATA14;                      /*!< (@ 0x00000038) User Data 14                                               */
+  __IM  uint32_t  UDATA15;                      /*!< (@ 0x0000003C) User Data 15                                               */
+  __IM  uint32_t  UDATA16;                      /*!< (@ 0x00000040) User Data 16                                               */
+  __IM  uint32_t  UDATA17;                      /*!< (@ 0x00000044) User Data 17                                               */
+  __IM  uint32_t  UDATA18;                      /*!< (@ 0x00000048) User Data 18                                               */
+  __IM  uint32_t  UDATA19;                      /*!< (@ 0x0000004C) User Data 19                                               */
+  __IM  uint32_t  UDATA20;                      /*!< (@ 0x00000050) User Data 20                                               */
+  __IM  uint32_t  UDATA21;                      /*!< (@ 0x00000054) User Data 21                                               */
+  __IM  uint32_t  UDATA22;                      /*!< (@ 0x00000058) User Data 22                                               */
+  __IM  uint32_t  UDATA23;                      /*!< (@ 0x0000005C) User Data 23                                               */
+  __IM  uint32_t  UDATA24;                      /*!< (@ 0x00000060) User Data 24                                               */
+  __IM  uint32_t  UDATA25;                      /*!< (@ 0x00000064) User Data 25                                               */
+  __IM  uint32_t  UDATA26;                      /*!< (@ 0x00000068) User Data 26                                               */
+  __IM  uint32_t  UDATA27;                      /*!< (@ 0x0000006C) User Data 27                                               */
+  __IM  uint32_t  UDATA28;                      /*!< (@ 0x00000070) User Data 28                                               */
+  __IM  uint32_t  UDATA29;                      /*!< (@ 0x00000074) User Data 29                                               */
+  __IM  uint32_t  UDATA30;                      /*!< (@ 0x00000078) User Data 30                                               */
+  __IM  uint32_t  UDATA31;                      /*!< (@ 0x0000007C) User Data 31                                               */
+} COA2_Type;                                    /*!< Size = 128 (0x80)                                                         */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA3                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Configuration Option Area Page 3: User Data Area 1 (COA3)
+  */
+
+typedef struct {                                /*!< (@ 0x1FFFF600) COA3 Structure                                             */
+  __IM  uint32_t  UDATA00;                      /*!< (@ 0x00000000) User Data 00                                               */
+  __IM  uint32_t  UDATA01;                      /*!< (@ 0x00000004) User Data 01                                               */
+  __IM  uint32_t  UDATA02;                      /*!< (@ 0x00000008) User Data 02                                               */
+  __IM  uint32_t  UDATA03;                      /*!< (@ 0x0000000C) User Data 03                                               */
+  __IM  uint32_t  UDATA04;                      /*!< (@ 0x00000010) User Data 04                                               */
+  __IM  uint32_t  UDATA05;                      /*!< (@ 0x00000014) User Data 05                                               */
+  __IM  uint32_t  UDATA06;                      /*!< (@ 0x00000018) User Data 06                                               */
+  __IM  uint32_t  UDATA07;                      /*!< (@ 0x0000001C) User Data 07                                               */
+  __IM  uint32_t  UDATA08;                      /*!< (@ 0x00000020) User Data 08                                               */
+  __IM  uint32_t  UDATA09;                      /*!< (@ 0x00000024) User Data 09                                               */
+  __IM  uint32_t  UDATA10;                      /*!< (@ 0x00000028) User Data 10                                               */
+  __IM  uint32_t  UDATA11;                      /*!< (@ 0x0000002C) User Data 11                                               */
+  __IM  uint32_t  UDATA12;                      /*!< (@ 0x00000030) User Data 12                                               */
+  __IM  uint32_t  UDATA13;                      /*!< (@ 0x00000034) User Data 13                                               */
+  __IM  uint32_t  UDATA14;                      /*!< (@ 0x00000038) User Data 14                                               */
+  __IM  uint32_t  UDATA15;                      /*!< (@ 0x0000003C) User Data 15                                               */
+  __IM  uint32_t  UDATA16;                      /*!< (@ 0x00000040) User Data 16                                               */
+  __IM  uint32_t  UDATA17;                      /*!< (@ 0x00000044) User Data 17                                               */
+  __IM  uint32_t  UDATA18;                      /*!< (@ 0x00000048) User Data 18                                               */
+  __IM  uint32_t  UDATA19;                      /*!< (@ 0x0000004C) User Data 19                                               */
+  __IM  uint32_t  UDATA20;                      /*!< (@ 0x00000050) User Data 20                                               */
+  __IM  uint32_t  UDATA21;                      /*!< (@ 0x00000054) User Data 21                                               */
+  __IM  uint32_t  UDATA22;                      /*!< (@ 0x00000058) User Data 22                                               */
+  __IM  uint32_t  UDATA23;                      /*!< (@ 0x0000005C) User Data 23                                               */
+  __IM  uint32_t  UDATA24;                      /*!< (@ 0x00000060) User Data 24                                               */
+  __IM  uint32_t  UDATA25;                      /*!< (@ 0x00000064) User Data 25                                               */
+  __IM  uint32_t  UDATA26;                      /*!< (@ 0x00000068) User Data 26                                               */
+  __IM  uint32_t  UDATA27;                      /*!< (@ 0x0000006C) User Data 27                                               */
+  __IM  uint32_t  UDATA28;                      /*!< (@ 0x00000070) User Data 28                                               */
+  __IM  uint32_t  UDATA29;                      /*!< (@ 0x00000074) User Data 29                                               */
+  __IM  uint32_t  UDATA30;                      /*!< (@ 0x00000078) User Data 30                                               */
+  __IM  uint32_t  UDATA31;                      /*!< (@ 0x0000007C) User Data 31                                               */
+} COA3_Type;                                    /*!< Size = 128 (0x80)                                                         */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+  * @{
+  */
+
+#define INTC_BASE                   0x40001000UL
+#define SCUCC_BASE                  0x4000F000UL
+#define SCUCG_BASE                  0x40001800UL
+#define SCULV_BASE                  0x40005100UL
+#define Pn_BASE                     0x50000000UL
+#define PA_BASE                     0x30000000UL
+#define PB_BASE                     0x30000100UL
+#define PC_BASE                     0x30000200UL
+#define PD_BASE                     0x30000300UL
+#define PE_BASE                     0x30000400UL
+#define PF_BASE                     0x30000500UL
+#define FMC_BASE                    0x40001B00UL
+#define WDT_BASE                    0x40001A00UL
+#define WT_BASE                     0x40002000UL
+#define TIMER1n_BASE                0x51000000UL
+#define TIMER10_BASE                0x40002100UL
+#define TIMER11_BASE                0x40002200UL
+#define TIMER12_BASE                0x40002300UL
+#define TIMER13_BASE                0x40002700UL
+#define TIMER14_BASE                0x40002800UL
+#define TIMER15_BASE                0x40002900UL
+#define TIMER16_BASE                0x40002A00UL
+#define TIMER2n_BASE                0x52000000UL
+#define TIMER20_BASE                0x40002500UL
+#define TIMER21_BASE                0x40002600UL
+#define TIMER3n_BASE                0x53000000UL
+#define TIMER30_BASE                0x40002400UL
+#define ADC_BASE                    0x40003000UL
+#define USART1n_BASE                0x54000000UL
+#define USART10_BASE                0x40003800UL
+#define USART11_BASE                0x40003900UL
+#define USART12_BASE                0x40003A00UL
+#define USART13_BASE                0x40003B00UL
+#define UARTn_BASE                  0x55000000UL
+#define UART0_BASE                  0x40004000UL
+#define UART1_BASE                  0x40004100UL
+#define I2Cn_BASE                   0x56000000UL
+#define I2C0_BASE                   0x40004800UL
+#define I2C1_BASE                   0x40004900UL
+#define I2C2_BASE                   0x40004A00UL
+#define LCD_BASE                    0x40005000UL
+#define CRC_BASE                    0x30001000UL
+#define COA0_BASE                   0x1FFFF000UL
+#define COA1_BASE                   0x1FFFF200UL
+#define COA2_BASE                   0x1FFFF400UL
+#define COA3_BASE                   0x1FFFF600UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+  * @{
+  */
+
+#define INTC                        ((INTC_Type*)              INTC_BASE)
+#define SCUCC                       ((SCUCC_Type*)             SCUCC_BASE)
+#define SCUCG                       ((SCUCG_Type*)             SCUCG_BASE)
+#define SCULV                       ((SCULV_Type*)             SCULV_BASE)
+#define Pn                          ((Pn_Type*)                Pn_BASE)
+#define PA                          ((PA_Type*)                PA_BASE)
+#define PB                          ((PB_Type*)                PB_BASE)
+#define PC                          ((PC_Type*)                PC_BASE)
+#define PD                          ((PD_Type*)                PD_BASE)
+#define PE                          ((PE_Type*)                PE_BASE)
+#define PF                          ((PF_Type*)                PF_BASE)
+#define FMC                         ((FMC_Type*)               FMC_BASE)
+#define WDT                         ((WDT_Type*)               WDT_BASE)
+#define WT                          ((WT_Type*)                WT_BASE)
+#define TIMER1n                     ((TIMER1n_Type*)           TIMER1n_BASE)
+#define TIMER10                     ((TIMER10_Type*)           TIMER10_BASE)
+#define TIMER11                     ((TIMER11_Type*)           TIMER11_BASE)
+#define TIMER12                     ((TIMER12_Type*)           TIMER12_BASE)
+#define TIMER13                     ((TIMER13_Type*)           TIMER13_BASE)
+#define TIMER14                     ((TIMER14_Type*)           TIMER14_BASE)
+#define TIMER15                     ((TIMER15_Type*)           TIMER15_BASE)
+#define TIMER16                     ((TIMER16_Type*)           TIMER16_BASE)
+#define TIMER2n                     ((TIMER2n_Type*)           TIMER2n_BASE)
+#define TIMER20                     ((TIMER20_Type*)           TIMER20_BASE)
+#define TIMER21                     ((TIMER21_Type*)           TIMER21_BASE)
+#define TIMER3n                     ((TIMER3n_Type*)           TIMER3n_BASE)
+#define TIMER30                     ((TIMER30_Type*)           TIMER30_BASE)
+#define ADC                         ((ADC_Type*)               ADC_BASE)
+#define USART1n                     ((USART1n_Type*)           USART1n_BASE)
+#define USART10                     ((USART10_Type*)           USART10_BASE)
+#define USART11                     ((USART11_Type*)           USART11_BASE)
+#define USART12                     ((USART12_Type*)           USART12_BASE)
+#define USART13                     ((USART13_Type*)           USART13_BASE)
+#define UARTn                       ((UARTn_Type*)             UARTn_BASE)
+#define UART0                       ((UART0_Type*)             UART0_BASE)
+#define UART1                       ((UART1_Type*)             UART1_BASE)
+#define I2Cn                        ((I2Cn_Type*)              I2Cn_BASE)
+#define I2C0                        ((I2C0_Type*)              I2C0_BASE)
+#define I2C1                        ((I2C1_Type*)              I2C1_BASE)
+#define I2C2                        ((I2C2_Type*)              I2C2_BASE)
+#define LCD                         ((LCD_Type*)               LCD_BASE)
+#define CRC                         ((CRC_Type*)               CRC_BASE)
+#define COA0                        ((COA0_Type*)              COA0_BASE)
+#define COA1                        ((COA1_Type*)              COA1_BASE)
+#define COA2                        ((COA2_Type*)              COA2_BASE)
+#define COA3                        ((COA3_Type*)              COA3_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+#if defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                                Pos/Mask Peripheral Section                                ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup PosMask_peripherals
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           INTC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PBTRIG  ========================================================= */
+#define INTC_PBTRIG_ITRIG11_Pos           (11UL)                    /*!< INTC PBTRIG: ITRIG11 (Bit 11)                         */
+#define INTC_PBTRIG_ITRIG11_Msk           (0x800UL)                 /*!< INTC PBTRIG: ITRIG11 (Bitfield-Mask: 0x01)            */
+#define INTC_PBTRIG_ITRIG10_Pos           (10UL)                    /*!< INTC PBTRIG: ITRIG10 (Bit 10)                         */
+#define INTC_PBTRIG_ITRIG10_Msk           (0x400UL)                 /*!< INTC PBTRIG: ITRIG10 (Bitfield-Mask: 0x01)            */
+#define INTC_PBTRIG_ITRIG9_Pos            (9UL)                     /*!< INTC PBTRIG: ITRIG9 (Bit 9)                           */
+#define INTC_PBTRIG_ITRIG9_Msk            (0x200UL)                 /*!< INTC PBTRIG: ITRIG9 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG8_Pos            (8UL)                     /*!< INTC PBTRIG: ITRIG8 (Bit 8)                           */
+#define INTC_PBTRIG_ITRIG8_Msk            (0x100UL)                 /*!< INTC PBTRIG: ITRIG8 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG7_Pos            (7UL)                     /*!< INTC PBTRIG: ITRIG7 (Bit 7)                           */
+#define INTC_PBTRIG_ITRIG7_Msk            (0x80UL)                  /*!< INTC PBTRIG: ITRIG7 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG6_Pos            (6UL)                     /*!< INTC PBTRIG: ITRIG6 (Bit 6)                           */
+#define INTC_PBTRIG_ITRIG6_Msk            (0x40UL)                  /*!< INTC PBTRIG: ITRIG6 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG5_Pos            (5UL)                     /*!< INTC PBTRIG: ITRIG5 (Bit 5)                           */
+#define INTC_PBTRIG_ITRIG5_Msk            (0x20UL)                  /*!< INTC PBTRIG: ITRIG5 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG4_Pos            (4UL)                     /*!< INTC PBTRIG: ITRIG4 (Bit 4)                           */
+#define INTC_PBTRIG_ITRIG4_Msk            (0x10UL)                  /*!< INTC PBTRIG: ITRIG4 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG3_Pos            (3UL)                     /*!< INTC PBTRIG: ITRIG3 (Bit 3)                           */
+#define INTC_PBTRIG_ITRIG3_Msk            (0x8UL)                   /*!< INTC PBTRIG: ITRIG3 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG2_Pos            (2UL)                     /*!< INTC PBTRIG: ITRIG2 (Bit 2)                           */
+#define INTC_PBTRIG_ITRIG2_Msk            (0x4UL)                   /*!< INTC PBTRIG: ITRIG2 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG1_Pos            (1UL)                     /*!< INTC PBTRIG: ITRIG1 (Bit 1)                           */
+#define INTC_PBTRIG_ITRIG1_Msk            (0x2UL)                   /*!< INTC PBTRIG: ITRIG1 (Bitfield-Mask: 0x01)             */
+#define INTC_PBTRIG_ITRIG0_Pos            (0UL)                     /*!< INTC PBTRIG: ITRIG0 (Bit 0)                           */
+#define INTC_PBTRIG_ITRIG0_Msk            (0x1UL)                   /*!< INTC PBTRIG: ITRIG0 (Bitfield-Mask: 0x01)             */
+/* ========================================================  PCTRIG  ========================================================= */
+#define INTC_PCTRIG_ITRIG3_Pos            (3UL)                     /*!< INTC PCTRIG: ITRIG3 (Bit 3)                           */
+#define INTC_PCTRIG_ITRIG3_Msk            (0x8UL)                   /*!< INTC PCTRIG: ITRIG3 (Bitfield-Mask: 0x01)             */
+#define INTC_PCTRIG_ITRIG2_Pos            (2UL)                     /*!< INTC PCTRIG: ITRIG2 (Bit 2)                           */
+#define INTC_PCTRIG_ITRIG2_Msk            (0x4UL)                   /*!< INTC PCTRIG: ITRIG2 (Bitfield-Mask: 0x01)             */
+#define INTC_PCTRIG_ITRIG1_Pos            (1UL)                     /*!< INTC PCTRIG: ITRIG1 (Bit 1)                           */
+#define INTC_PCTRIG_ITRIG1_Msk            (0x2UL)                   /*!< INTC PCTRIG: ITRIG1 (Bitfield-Mask: 0x01)             */
+#define INTC_PCTRIG_ITRIG0_Pos            (0UL)                     /*!< INTC PCTRIG: ITRIG0 (Bit 0)                           */
+#define INTC_PCTRIG_ITRIG0_Msk            (0x1UL)                   /*!< INTC PCTRIG: ITRIG0 (Bitfield-Mask: 0x01)             */
+/* ========================================================  PETRIG  ========================================================= */
+#define INTC_PETRIG_ITRIG3_Pos            (3UL)                     /*!< INTC PETRIG: ITRIG3 (Bit 3)                           */
+#define INTC_PETRIG_ITRIG3_Msk            (0x8UL)                   /*!< INTC PETRIG: ITRIG3 (Bitfield-Mask: 0x01)             */
+#define INTC_PETRIG_ITRIG2_Pos            (2UL)                     /*!< INTC PETRIG: ITRIG2 (Bit 2)                           */
+#define INTC_PETRIG_ITRIG2_Msk            (0x4UL)                   /*!< INTC PETRIG: ITRIG2 (Bitfield-Mask: 0x01)             */
+#define INTC_PETRIG_ITRIG1_Pos            (1UL)                     /*!< INTC PETRIG: ITRIG1 (Bit 1)                           */
+#define INTC_PETRIG_ITRIG1_Msk            (0x2UL)                   /*!< INTC PETRIG: ITRIG1 (Bitfield-Mask: 0x01)             */
+#define INTC_PETRIG_ITRIG0_Pos            (0UL)                     /*!< INTC PETRIG: ITRIG0 (Bit 0)                           */
+#define INTC_PETRIG_ITRIG0_Msk            (0x1UL)                   /*!< INTC PETRIG: ITRIG0 (Bitfield-Mask: 0x01)             */
+/* =========================================================  PBCR  ========================================================== */
+#define INTC_PBCR_INTCTL11_Pos            (22UL)                    /*!< INTC PBCR: INTCTL11 (Bit 22)                          */
+#define INTC_PBCR_INTCTL11_Msk            (0xc00000UL)              /*!< INTC PBCR: INTCTL11 (Bitfield-Mask: 0x03)             */
+#define INTC_PBCR_INTCTL10_Pos            (20UL)                    /*!< INTC PBCR: INTCTL10 (Bit 20)                          */
+#define INTC_PBCR_INTCTL10_Msk            (0x300000UL)              /*!< INTC PBCR: INTCTL10 (Bitfield-Mask: 0x03)             */
+#define INTC_PBCR_INTCTL9_Pos             (18UL)                    /*!< INTC PBCR: INTCTL9 (Bit 18)                           */
+#define INTC_PBCR_INTCTL9_Msk             (0xc0000UL)               /*!< INTC PBCR: INTCTL9 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL8_Pos             (16UL)                    /*!< INTC PBCR: INTCTL8 (Bit 16)                           */
+#define INTC_PBCR_INTCTL8_Msk             (0x30000UL)               /*!< INTC PBCR: INTCTL8 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL7_Pos             (14UL)                    /*!< INTC PBCR: INTCTL7 (Bit 14)                           */
+#define INTC_PBCR_INTCTL7_Msk             (0xc000UL)                /*!< INTC PBCR: INTCTL7 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL6_Pos             (12UL)                    /*!< INTC PBCR: INTCTL6 (Bit 12)                           */
+#define INTC_PBCR_INTCTL6_Msk             (0x3000UL)                /*!< INTC PBCR: INTCTL6 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL5_Pos             (10UL)                    /*!< INTC PBCR: INTCTL5 (Bit 10)                           */
+#define INTC_PBCR_INTCTL5_Msk             (0xc00UL)                 /*!< INTC PBCR: INTCTL5 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL4_Pos             (8UL)                     /*!< INTC PBCR: INTCTL4 (Bit 8)                            */
+#define INTC_PBCR_INTCTL4_Msk             (0x300UL)                 /*!< INTC PBCR: INTCTL4 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL3_Pos             (6UL)                     /*!< INTC PBCR: INTCTL3 (Bit 6)                            */
+#define INTC_PBCR_INTCTL3_Msk             (0xc0UL)                  /*!< INTC PBCR: INTCTL3 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL2_Pos             (4UL)                     /*!< INTC PBCR: INTCTL2 (Bit 4)                            */
+#define INTC_PBCR_INTCTL2_Msk             (0x30UL)                  /*!< INTC PBCR: INTCTL2 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL1_Pos             (2UL)                     /*!< INTC PBCR: INTCTL1 (Bit 2)                            */
+#define INTC_PBCR_INTCTL1_Msk             (0xcUL)                   /*!< INTC PBCR: INTCTL1 (Bitfield-Mask: 0x03)              */
+#define INTC_PBCR_INTCTL0_Pos             (0UL)                     /*!< INTC PBCR: INTCTL0 (Bit 0)                            */
+#define INTC_PBCR_INTCTL0_Msk             (0x3UL)                   /*!< INTC PBCR: INTCTL0 (Bitfield-Mask: 0x03)              */
+/* =========================================================  PCCR  ========================================================== */
+#define INTC_PCCR_INTCTL3_Pos             (6UL)                     /*!< INTC PCCR: INTCTL3 (Bit 6)                            */
+#define INTC_PCCR_INTCTL3_Msk             (0xc0UL)                  /*!< INTC PCCR: INTCTL3 (Bitfield-Mask: 0x03)              */
+#define INTC_PCCR_INTCTL2_Pos             (4UL)                     /*!< INTC PCCR: INTCTL2 (Bit 4)                            */
+#define INTC_PCCR_INTCTL2_Msk             (0x30UL)                  /*!< INTC PCCR: INTCTL2 (Bitfield-Mask: 0x03)              */
+#define INTC_PCCR_INTCTL1_Pos             (2UL)                     /*!< INTC PCCR: INTCTL1 (Bit 2)                            */
+#define INTC_PCCR_INTCTL1_Msk             (0xcUL)                   /*!< INTC PCCR: INTCTL1 (Bitfield-Mask: 0x03)              */
+#define INTC_PCCR_INTCTL0_Pos             (0UL)                     /*!< INTC PCCR: INTCTL0 (Bit 0)                            */
+#define INTC_PCCR_INTCTL0_Msk             (0x3UL)                   /*!< INTC PCCR: INTCTL0 (Bitfield-Mask: 0x03)              */
+/* =========================================================  PECR  ========================================================== */
+#define INTC_PECR_INTCTL3_Pos             (6UL)                     /*!< INTC PECR: INTCTL3 (Bit 6)                            */
+#define INTC_PECR_INTCTL3_Msk             (0xc0UL)                  /*!< INTC PECR: INTCTL3 (Bitfield-Mask: 0x03)              */
+#define INTC_PECR_INTCTL2_Pos             (4UL)                     /*!< INTC PECR: INTCTL2 (Bit 4)                            */
+#define INTC_PECR_INTCTL2_Msk             (0x30UL)                  /*!< INTC PECR: INTCTL2 (Bitfield-Mask: 0x03)              */
+#define INTC_PECR_INTCTL1_Pos             (2UL)                     /*!< INTC PECR: INTCTL1 (Bit 2)                            */
+#define INTC_PECR_INTCTL1_Msk             (0xcUL)                   /*!< INTC PECR: INTCTL1 (Bitfield-Mask: 0x03)              */
+#define INTC_PECR_INTCTL0_Pos             (0UL)                     /*!< INTC PECR: INTCTL0 (Bit 0)                            */
+#define INTC_PECR_INTCTL0_Msk             (0x3UL)                   /*!< INTC PECR: INTCTL0 (Bitfield-Mask: 0x03)              */
+/* ========================================================  PBFLAG  ========================================================= */
+#define INTC_PBFLAG_FLAG11_Pos            (11UL)                    /*!< INTC PBFLAG: FLAG11 (Bit 11)                          */
+#define INTC_PBFLAG_FLAG11_Msk            (0x800UL)                 /*!< INTC PBFLAG: FLAG11 (Bitfield-Mask: 0x01)             */
+#define INTC_PBFLAG_FLAG10_Pos            (10UL)                    /*!< INTC PBFLAG: FLAG10 (Bit 10)                          */
+#define INTC_PBFLAG_FLAG10_Msk            (0x400UL)                 /*!< INTC PBFLAG: FLAG10 (Bitfield-Mask: 0x01)             */
+#define INTC_PBFLAG_FLAG9_Pos             (9UL)                     /*!< INTC PBFLAG: FLAG9 (Bit 9)                            */
+#define INTC_PBFLAG_FLAG9_Msk             (0x200UL)                 /*!< INTC PBFLAG: FLAG9 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG8_Pos             (8UL)                     /*!< INTC PBFLAG: FLAG8 (Bit 8)                            */
+#define INTC_PBFLAG_FLAG8_Msk             (0x100UL)                 /*!< INTC PBFLAG: FLAG8 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG7_Pos             (7UL)                     /*!< INTC PBFLAG: FLAG7 (Bit 7)                            */
+#define INTC_PBFLAG_FLAG7_Msk             (0x80UL)                  /*!< INTC PBFLAG: FLAG7 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG6_Pos             (6UL)                     /*!< INTC PBFLAG: FLAG6 (Bit 6)                            */
+#define INTC_PBFLAG_FLAG6_Msk             (0x40UL)                  /*!< INTC PBFLAG: FLAG6 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG5_Pos             (5UL)                     /*!< INTC PBFLAG: FLAG5 (Bit 5)                            */
+#define INTC_PBFLAG_FLAG5_Msk             (0x20UL)                  /*!< INTC PBFLAG: FLAG5 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG4_Pos             (4UL)                     /*!< INTC PBFLAG: FLAG4 (Bit 4)                            */
+#define INTC_PBFLAG_FLAG4_Msk             (0x10UL)                  /*!< INTC PBFLAG: FLAG4 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG3_Pos             (3UL)                     /*!< INTC PBFLAG: FLAG3 (Bit 3)                            */
+#define INTC_PBFLAG_FLAG3_Msk             (0x8UL)                   /*!< INTC PBFLAG: FLAG3 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG2_Pos             (2UL)                     /*!< INTC PBFLAG: FLAG2 (Bit 2)                            */
+#define INTC_PBFLAG_FLAG2_Msk             (0x4UL)                   /*!< INTC PBFLAG: FLAG2 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG1_Pos             (1UL)                     /*!< INTC PBFLAG: FLAG1 (Bit 1)                            */
+#define INTC_PBFLAG_FLAG1_Msk             (0x2UL)                   /*!< INTC PBFLAG: FLAG1 (Bitfield-Mask: 0x01)              */
+#define INTC_PBFLAG_FLAG0_Pos             (0UL)                     /*!< INTC PBFLAG: FLAG0 (Bit 0)                            */
+#define INTC_PBFLAG_FLAG0_Msk             (0x1UL)                   /*!< INTC PBFLAG: FLAG0 (Bitfield-Mask: 0x01)              */
+/* ========================================================  PCFLAG  ========================================================= */
+#define INTC_PCFLAG_FLAG3_Pos             (3UL)                     /*!< INTC PCFLAG: FLAG3 (Bit 3)                            */
+#define INTC_PCFLAG_FLAG3_Msk             (0x8UL)                   /*!< INTC PCFLAG: FLAG3 (Bitfield-Mask: 0x01)              */
+#define INTC_PCFLAG_FLAG2_Pos             (2UL)                     /*!< INTC PCFLAG: FLAG2 (Bit 2)                            */
+#define INTC_PCFLAG_FLAG2_Msk             (0x4UL)                   /*!< INTC PCFLAG: FLAG2 (Bitfield-Mask: 0x01)              */
+#define INTC_PCFLAG_FLAG1_Pos             (1UL)                     /*!< INTC PCFLAG: FLAG1 (Bit 1)                            */
+#define INTC_PCFLAG_FLAG1_Msk             (0x2UL)                   /*!< INTC PCFLAG: FLAG1 (Bitfield-Mask: 0x01)              */
+#define INTC_PCFLAG_FLAG0_Pos             (0UL)                     /*!< INTC PCFLAG: FLAG0 (Bit 0)                            */
+#define INTC_PCFLAG_FLAG0_Msk             (0x1UL)                   /*!< INTC PCFLAG: FLAG0 (Bitfield-Mask: 0x01)              */
+/* ========================================================  PEFLAG  ========================================================= */
+#define INTC_PEFLAG_FLAG3_Pos             (3UL)                     /*!< INTC PEFLAG: FLAG3 (Bit 3)                            */
+#define INTC_PEFLAG_FLAG3_Msk             (0x8UL)                   /*!< INTC PEFLAG: FLAG3 (Bitfield-Mask: 0x01)              */
+#define INTC_PEFLAG_FLAG2_Pos             (2UL)                     /*!< INTC PEFLAG: FLAG2 (Bit 2)                            */
+#define INTC_PEFLAG_FLAG2_Msk             (0x4UL)                   /*!< INTC PEFLAG: FLAG2 (Bitfield-Mask: 0x01)              */
+#define INTC_PEFLAG_FLAG1_Pos             (1UL)                     /*!< INTC PEFLAG: FLAG1 (Bit 1)                            */
+#define INTC_PEFLAG_FLAG1_Msk             (0x2UL)                   /*!< INTC PEFLAG: FLAG1 (Bitfield-Mask: 0x01)              */
+#define INTC_PEFLAG_FLAG0_Pos             (0UL)                     /*!< INTC PEFLAG: FLAG0 (Bit 0)                            */
+#define INTC_PEFLAG_FLAG0_Msk             (0x1UL)                   /*!< INTC PEFLAG: FLAG0 (Bitfield-Mask: 0x01)              */
+/* ======================================================  EINT0CONF1  ======================================================= */
+#define INTC_EINT0CONF1_CONF7_Pos         (28UL)                    /*!< INTC EINT0CONF1: CONF7 (Bit 28)                       */
+#define INTC_EINT0CONF1_CONF7_Msk         (0xf0000000UL)            /*!< INTC EINT0CONF1: CONF7 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT0CONF1_CONF6_Pos         (24UL)                    /*!< INTC EINT0CONF1: CONF6 (Bit 24)                       */
+#define INTC_EINT0CONF1_CONF6_Msk         (0xf000000UL)             /*!< INTC EINT0CONF1: CONF6 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT0CONF1_CONF5_Pos         (20UL)                    /*!< INTC EINT0CONF1: CONF5 (Bit 20)                       */
+#define INTC_EINT0CONF1_CONF5_Msk         (0xf00000UL)              /*!< INTC EINT0CONF1: CONF5 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT0CONF1_CONF4_Pos         (16UL)                    /*!< INTC EINT0CONF1: CONF4 (Bit 16)                       */
+#define INTC_EINT0CONF1_CONF4_Msk         (0xf0000UL)               /*!< INTC EINT0CONF1: CONF4 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT0CONF1_CONF3_Pos         (12UL)                    /*!< INTC EINT0CONF1: CONF3 (Bit 12)                       */
+#define INTC_EINT0CONF1_CONF3_Msk         (0xf000UL)                /*!< INTC EINT0CONF1: CONF3 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT0CONF1_CONF2_Pos         (8UL)                     /*!< INTC EINT0CONF1: CONF2 (Bit 8)                        */
+#define INTC_EINT0CONF1_CONF2_Msk         (0xf00UL)                 /*!< INTC EINT0CONF1: CONF2 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT0CONF1_CONF1_Pos         (4UL)                     /*!< INTC EINT0CONF1: CONF1 (Bit 4)                        */
+#define INTC_EINT0CONF1_CONF1_Msk         (0xf0UL)                  /*!< INTC EINT0CONF1: CONF1 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT0CONF1_CONF0_Pos         (0UL)                     /*!< INTC EINT0CONF1: CONF0 (Bit 0)                        */
+#define INTC_EINT0CONF1_CONF0_Msk         (0xfUL)                   /*!< INTC EINT0CONF1: CONF0 (Bitfield-Mask: 0x0f)          */
+/* ======================================================  EINT1CONF1  ======================================================= */
+#define INTC_EINT1CONF1_CONF7_Pos         (28UL)                    /*!< INTC EINT1CONF1: CONF7 (Bit 28)                       */
+#define INTC_EINT1CONF1_CONF7_Msk         (0xf0000000UL)            /*!< INTC EINT1CONF1: CONF7 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT1CONF1_CONF6_Pos         (24UL)                    /*!< INTC EINT1CONF1: CONF6 (Bit 24)                       */
+#define INTC_EINT1CONF1_CONF6_Msk         (0xf000000UL)             /*!< INTC EINT1CONF1: CONF6 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT1CONF1_CONF5_Pos         (20UL)                    /*!< INTC EINT1CONF1: CONF5 (Bit 20)                       */
+#define INTC_EINT1CONF1_CONF5_Msk         (0xf00000UL)              /*!< INTC EINT1CONF1: CONF5 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT1CONF1_CONF4_Pos         (16UL)                    /*!< INTC EINT1CONF1: CONF4 (Bit 16)                       */
+#define INTC_EINT1CONF1_CONF4_Msk         (0xf0000UL)               /*!< INTC EINT1CONF1: CONF4 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT1CONF1_CONF3_Pos         (12UL)                    /*!< INTC EINT1CONF1: CONF3 (Bit 12)                       */
+#define INTC_EINT1CONF1_CONF3_Msk         (0xf000UL)                /*!< INTC EINT1CONF1: CONF3 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT1CONF1_CONF2_Pos         (8UL)                     /*!< INTC EINT1CONF1: CONF2 (Bit 8)                        */
+#define INTC_EINT1CONF1_CONF2_Msk         (0xf00UL)                 /*!< INTC EINT1CONF1: CONF2 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT1CONF1_CONF1_Pos         (4UL)                     /*!< INTC EINT1CONF1: CONF1 (Bit 4)                        */
+#define INTC_EINT1CONF1_CONF1_Msk         (0xf0UL)                  /*!< INTC EINT1CONF1: CONF1 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT1CONF1_CONF0_Pos         (0UL)                     /*!< INTC EINT1CONF1: CONF0 (Bit 0)                        */
+#define INTC_EINT1CONF1_CONF0_Msk         (0xfUL)                   /*!< INTC EINT1CONF1: CONF0 (Bitfield-Mask: 0x0f)          */
+/* ======================================================  EINT2CONF1  ======================================================= */
+#define INTC_EINT2CONF1_CONF7_Pos         (28UL)                    /*!< INTC EINT2CONF1: CONF7 (Bit 28)                       */
+#define INTC_EINT2CONF1_CONF7_Msk         (0xf0000000UL)            /*!< INTC EINT2CONF1: CONF7 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT2CONF1_CONF6_Pos         (24UL)                    /*!< INTC EINT2CONF1: CONF6 (Bit 24)                       */
+#define INTC_EINT2CONF1_CONF6_Msk         (0xf000000UL)             /*!< INTC EINT2CONF1: CONF6 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT2CONF1_CONF5_Pos         (20UL)                    /*!< INTC EINT2CONF1: CONF5 (Bit 20)                       */
+#define INTC_EINT2CONF1_CONF5_Msk         (0xf00000UL)              /*!< INTC EINT2CONF1: CONF5 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT2CONF1_CONF4_Pos         (16UL)                    /*!< INTC EINT2CONF1: CONF4 (Bit 16)                       */
+#define INTC_EINT2CONF1_CONF4_Msk         (0xf0000UL)               /*!< INTC EINT2CONF1: CONF4 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT2CONF1_CONF3_Pos         (12UL)                    /*!< INTC EINT2CONF1: CONF3 (Bit 12)                       */
+#define INTC_EINT2CONF1_CONF3_Msk         (0xf000UL)                /*!< INTC EINT2CONF1: CONF3 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT2CONF1_CONF2_Pos         (8UL)                     /*!< INTC EINT2CONF1: CONF2 (Bit 8)                        */
+#define INTC_EINT2CONF1_CONF2_Msk         (0xf00UL)                 /*!< INTC EINT2CONF1: CONF2 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT2CONF1_CONF1_Pos         (4UL)                     /*!< INTC EINT2CONF1: CONF1 (Bit 4)                        */
+#define INTC_EINT2CONF1_CONF1_Msk         (0xf0UL)                  /*!< INTC EINT2CONF1: CONF1 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT2CONF1_CONF0_Pos         (0UL)                     /*!< INTC EINT2CONF1: CONF0 (Bit 0)                        */
+#define INTC_EINT2CONF1_CONF0_Msk         (0xfUL)                   /*!< INTC EINT2CONF1: CONF0 (Bitfield-Mask: 0x0f)          */
+/* ======================================================  EINT3CONF1  ======================================================= */
+#define INTC_EINT3CONF1_CONF7_Pos         (28UL)                    /*!< INTC EINT3CONF1: CONF7 (Bit 28)                       */
+#define INTC_EINT3CONF1_CONF7_Msk         (0xf0000000UL)            /*!< INTC EINT3CONF1: CONF7 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT3CONF1_CONF6_Pos         (24UL)                    /*!< INTC EINT3CONF1: CONF6 (Bit 24)                       */
+#define INTC_EINT3CONF1_CONF6_Msk         (0xf000000UL)             /*!< INTC EINT3CONF1: CONF6 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT3CONF1_CONF5_Pos         (20UL)                    /*!< INTC EINT3CONF1: CONF5 (Bit 20)                       */
+#define INTC_EINT3CONF1_CONF5_Msk         (0xf00000UL)              /*!< INTC EINT3CONF1: CONF5 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT3CONF1_CONF4_Pos         (16UL)                    /*!< INTC EINT3CONF1: CONF4 (Bit 16)                       */
+#define INTC_EINT3CONF1_CONF4_Msk         (0xf0000UL)               /*!< INTC EINT3CONF1: CONF4 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT3CONF1_CONF3_Pos         (12UL)                    /*!< INTC EINT3CONF1: CONF3 (Bit 12)                       */
+#define INTC_EINT3CONF1_CONF3_Msk         (0xf000UL)                /*!< INTC EINT3CONF1: CONF3 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT3CONF1_CONF2_Pos         (8UL)                     /*!< INTC EINT3CONF1: CONF2 (Bit 8)                        */
+#define INTC_EINT3CONF1_CONF2_Msk         (0xf00UL)                 /*!< INTC EINT3CONF1: CONF2 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT3CONF1_CONF1_Pos         (4UL)                     /*!< INTC EINT3CONF1: CONF1 (Bit 4)                        */
+#define INTC_EINT3CONF1_CONF1_Msk         (0xf0UL)                  /*!< INTC EINT3CONF1: CONF1 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT3CONF1_CONF0_Pos         (0UL)                     /*!< INTC EINT3CONF1: CONF0 (Bit 0)                        */
+#define INTC_EINT3CONF1_CONF0_Msk         (0xfUL)                   /*!< INTC EINT3CONF1: CONF0 (Bitfield-Mask: 0x0f)          */
+/* ======================================================  EINT0CONF2  ======================================================= */
+#define INTC_EINT0CONF2_CONF11_Pos        (12UL)                    /*!< INTC EINT0CONF2: CONF11 (Bit 12)                      */
+#define INTC_EINT0CONF2_CONF11_Msk        (0xf000UL)                /*!< INTC EINT0CONF2: CONF11 (Bitfield-Mask: 0x0f)         */
+#define INTC_EINT0CONF2_CONF10_Pos        (8UL)                     /*!< INTC EINT0CONF2: CONF10 (Bit 8)                       */
+#define INTC_EINT0CONF2_CONF10_Msk        (0xf00UL)                 /*!< INTC EINT0CONF2: CONF10 (Bitfield-Mask: 0x0f)         */
+#define INTC_EINT0CONF2_CONF9_Pos         (4UL)                     /*!< INTC EINT0CONF2: CONF9 (Bit 4)                        */
+#define INTC_EINT0CONF2_CONF9_Msk         (0xf0UL)                  /*!< INTC EINT0CONF2: CONF9 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT0CONF2_CONF8_Pos         (0UL)                     /*!< INTC EINT0CONF2: CONF8 (Bit 0)                        */
+#define INTC_EINT0CONF2_CONF8_Msk         (0xfUL)                   /*!< INTC EINT0CONF2: CONF8 (Bitfield-Mask: 0x0f)          */
+/* ======================================================  EINT1CONF2  ======================================================= */
+#define INTC_EINT1CONF2_CONF11_Pos        (12UL)                    /*!< INTC EINT1CONF2: CONF11 (Bit 12)                      */
+#define INTC_EINT1CONF2_CONF11_Msk        (0xf000UL)                /*!< INTC EINT1CONF2: CONF11 (Bitfield-Mask: 0x0f)         */
+#define INTC_EINT1CONF2_CONF10_Pos        (8UL)                     /*!< INTC EINT1CONF2: CONF10 (Bit 8)                       */
+#define INTC_EINT1CONF2_CONF10_Msk        (0xf00UL)                 /*!< INTC EINT1CONF2: CONF10 (Bitfield-Mask: 0x0f)         */
+#define INTC_EINT1CONF2_CONF9_Pos         (4UL)                     /*!< INTC EINT1CONF2: CONF9 (Bit 4)                        */
+#define INTC_EINT1CONF2_CONF9_Msk         (0xf0UL)                  /*!< INTC EINT1CONF2: CONF9 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT1CONF2_CONF8_Pos         (0UL)                     /*!< INTC EINT1CONF2: CONF8 (Bit 0)                        */
+#define INTC_EINT1CONF2_CONF8_Msk         (0xfUL)                   /*!< INTC EINT1CONF2: CONF8 (Bitfield-Mask: 0x0f)          */
+/* ======================================================  EINT2CONF2  ======================================================= */
+#define INTC_EINT2CONF2_CONF11_Pos        (12UL)                    /*!< INTC EINT2CONF2: CONF11 (Bit 12)                      */
+#define INTC_EINT2CONF2_CONF11_Msk        (0xf000UL)                /*!< INTC EINT2CONF2: CONF11 (Bitfield-Mask: 0x0f)         */
+#define INTC_EINT2CONF2_CONF10_Pos        (8UL)                     /*!< INTC EINT2CONF2: CONF10 (Bit 8)                       */
+#define INTC_EINT2CONF2_CONF10_Msk        (0xf00UL)                 /*!< INTC EINT2CONF2: CONF10 (Bitfield-Mask: 0x0f)         */
+#define INTC_EINT2CONF2_CONF9_Pos         (4UL)                     /*!< INTC EINT2CONF2: CONF9 (Bit 4)                        */
+#define INTC_EINT2CONF2_CONF9_Msk         (0xf0UL)                  /*!< INTC EINT2CONF2: CONF9 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT2CONF2_CONF8_Pos         (0UL)                     /*!< INTC EINT2CONF2: CONF8 (Bit 0)                        */
+#define INTC_EINT2CONF2_CONF8_Msk         (0xfUL)                   /*!< INTC EINT2CONF2: CONF8 (Bitfield-Mask: 0x0f)          */
+/* ======================================================  EINT3CONF2  ======================================================= */
+#define INTC_EINT3CONF2_CONF11_Pos        (12UL)                    /*!< INTC EINT3CONF2: CONF11 (Bit 12)                      */
+#define INTC_EINT3CONF2_CONF11_Msk        (0xf000UL)                /*!< INTC EINT3CONF2: CONF11 (Bitfield-Mask: 0x0f)         */
+#define INTC_EINT3CONF2_CONF10_Pos        (8UL)                     /*!< INTC EINT3CONF2: CONF10 (Bit 8)                       */
+#define INTC_EINT3CONF2_CONF10_Msk        (0xf00UL)                 /*!< INTC EINT3CONF2: CONF10 (Bitfield-Mask: 0x0f)         */
+#define INTC_EINT3CONF2_CONF9_Pos         (4UL)                     /*!< INTC EINT3CONF2: CONF9 (Bit 4)                        */
+#define INTC_EINT3CONF2_CONF9_Msk         (0xf0UL)                  /*!< INTC EINT3CONF2: CONF9 (Bitfield-Mask: 0x0f)          */
+#define INTC_EINT3CONF2_CONF8_Pos         (0UL)                     /*!< INTC EINT3CONF2: CONF8 (Bit 0)                        */
+#define INTC_EINT3CONF2_CONF8_Msk         (0xfUL)                   /*!< INTC EINT3CONF2: CONF8 (Bitfield-Mask: 0x0f)          */
+/* ==========================================================  MSK  ========================================================== */
+#define INTC_MSK_IMSK31_NULL_Pos          (31UL)                    /*!< INTC MSK: IMSK31_NULL (Bit 31)                        */
+#define INTC_MSK_IMSK31_NULL_Msk          (0x80000000UL)            /*!< INTC MSK: IMSK31_NULL (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK30_NULL_Pos          (30UL)                    /*!< INTC MSK: IMSK30_NULL (Bit 30)                        */
+#define INTC_MSK_IMSK30_NULL_Msk          (0x40000000UL)            /*!< INTC MSK: IMSK30_NULL (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK29_NULL_Pos          (29UL)                    /*!< INTC MSK: IMSK29_NULL (Bit 29)                        */
+#define INTC_MSK_IMSK29_NULL_Msk          (0x20000000UL)            /*!< INTC MSK: IMSK29_NULL (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK28_NULL_Pos          (28UL)                    /*!< INTC MSK: IMSK28_NULL (Bit 28)                        */
+#define INTC_MSK_IMSK28_NULL_Msk          (0x10000000UL)            /*!< INTC MSK: IMSK28_NULL (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK27_USART13_Pos       (27UL)                    /*!< INTC MSK: IMSK27_USART13 (Bit 27)                     */
+#define INTC_MSK_IMSK27_USART13_Msk       (0x8000000UL)             /*!< INTC MSK: IMSK27_USART13 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK26_USART12_Pos       (26UL)                    /*!< INTC MSK: IMSK26_USART12 (Bit 26)                     */
+#define INTC_MSK_IMSK26_USART12_Msk       (0x4000000UL)             /*!< INTC MSK: IMSK26_USART12 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK25_I2C2_Pos          (25UL)                    /*!< INTC MSK: IMSK25_I2C2 (Bit 25)                        */
+#define INTC_MSK_IMSK25_I2C2_Msk          (0x2000000UL)             /*!< INTC MSK: IMSK25_I2C2 (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK24_TIMER16_Pos       (24UL)                    /*!< INTC MSK: IMSK24_TIMER16 (Bit 24)                     */
+#define INTC_MSK_IMSK24_TIMER16_Msk       (0x1000000UL)             /*!< INTC MSK: IMSK24_TIMER16 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK23_TIMER15_Pos       (23UL)                    /*!< INTC MSK: IMSK23_TIMER15 (Bit 23)                     */
+#define INTC_MSK_IMSK23_TIMER15_Msk       (0x800000UL)              /*!< INTC MSK: IMSK23_TIMER15 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK22_TIMER14_Pos       (22UL)                    /*!< INTC MSK: IMSK22_TIMER14 (Bit 22)                     */
+#define INTC_MSK_IMSK22_TIMER14_Msk       (0x400000UL)              /*!< INTC MSK: IMSK22_TIMER14 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK21_TIMER13_Pos       (21UL)                    /*!< INTC MSK: IMSK21_TIMER13 (Bit 21)                     */
+#define INTC_MSK_IMSK21_TIMER13_Msk       (0x200000UL)              /*!< INTC MSK: IMSK21_TIMER13 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK20_UART1_Pos         (20UL)                    /*!< INTC MSK: IMSK20_UART1 (Bit 20)                       */
+#define INTC_MSK_IMSK20_UART1_Msk         (0x100000UL)              /*!< INTC MSK: IMSK20_UART1 (Bitfield-Mask: 0x01)          */
+#define INTC_MSK_IMSK19_UART0_Pos         (19UL)                    /*!< INTC MSK: IMSK19_UART0 (Bit 19)                       */
+#define INTC_MSK_IMSK19_UART0_Msk         (0x80000UL)               /*!< INTC MSK: IMSK19_UART0 (Bitfield-Mask: 0x01)          */
+#define INTC_MSK_IMSK18_ADC_Pos           (18UL)                    /*!< INTC MSK: IMSK18_ADC (Bit 18)                         */
+#define INTC_MSK_IMSK18_ADC_Msk           (0x40000UL)               /*!< INTC MSK: IMSK18_ADC (Bitfield-Mask: 0x01)            */
+#define INTC_MSK_IMSK17_USART11_Pos       (17UL)                    /*!< INTC MSK: IMSK17_USART11 (Bit 17)                     */
+#define INTC_MSK_IMSK17_USART11_Msk       (0x20000UL)               /*!< INTC MSK: IMSK17_USART11 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK16_TIMER21_Pos       (16UL)                    /*!< INTC MSK: IMSK16_TIMER21 (Bit 16)                     */
+#define INTC_MSK_IMSK16_TIMER21_Msk       (0x10000UL)               /*!< INTC MSK: IMSK16_TIMER21 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK15_TIMER20_Pos       (15UL)                    /*!< INTC MSK: IMSK15_TIMER20 (Bit 15)                     */
+#define INTC_MSK_IMSK15_TIMER20_Msk       (0x8000UL)                /*!< INTC MSK: IMSK15_TIMER20 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK14_I2C1_Pos          (14UL)                    /*!< INTC MSK: IMSK14_I2C1 (Bit 14)                        */
+#define INTC_MSK_IMSK14_I2C1_Msk          (0x4000UL)                /*!< INTC MSK: IMSK14_I2C1 (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK13_TIMER30_Pos       (13UL)                    /*!< INTC MSK: IMSK13_TIMER30 (Bit 13)                     */
+#define INTC_MSK_IMSK13_TIMER30_Msk       (0x2000UL)                /*!< INTC MSK: IMSK13_TIMER30 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK12_WT_Pos            (12UL)                    /*!< INTC MSK: IMSK12_WT (Bit 12)                          */
+#define INTC_MSK_IMSK12_WT_Msk            (0x1000UL)                /*!< INTC MSK: IMSK12_WT (Bitfield-Mask: 0x01)             */
+#define INTC_MSK_IMSK11_USART10_Pos       (11UL)                    /*!< INTC MSK: IMSK11_USART10 (Bit 11)                     */
+#define INTC_MSK_IMSK11_USART10_Msk       (0x800UL)                 /*!< INTC MSK: IMSK11_USART10 (Bitfield-Mask: 0x01)        */
+#define INTC_MSK_IMSK10_I2C0_Pos          (10UL)                    /*!< INTC MSK: IMSK10_I2C0 (Bit 10)                        */
+#define INTC_MSK_IMSK10_I2C0_Msk          (0x400UL)                 /*!< INTC MSK: IMSK10_I2C0 (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK9_TIMER12_Pos        (9UL)                     /*!< INTC MSK: IMSK9_TIMER12 (Bit 9)                       */
+#define INTC_MSK_IMSK9_TIMER12_Msk        (0x200UL)                 /*!< INTC MSK: IMSK9_TIMER12 (Bitfield-Mask: 0x01)         */
+#define INTC_MSK_IMSK8_TIMER11_Pos        (8UL)                     /*!< INTC MSK: IMSK8_TIMER11 (Bit 8)                       */
+#define INTC_MSK_IMSK8_TIMER11_Msk        (0x100UL)                 /*!< INTC MSK: IMSK8_TIMER11 (Bitfield-Mask: 0x01)         */
+#define INTC_MSK_IMSK7_TIMER10_Pos        (7UL)                     /*!< INTC MSK: IMSK7_TIMER10 (Bit 7)                       */
+#define INTC_MSK_IMSK7_TIMER10_Msk        (0x80UL)                  /*!< INTC MSK: IMSK7_TIMER10 (Bitfield-Mask: 0x01)         */
+#define INTC_MSK_IMSK6_EINT3_Pos          (6UL)                     /*!< INTC MSK: IMSK6_EINT3 (Bit 6)                         */
+#define INTC_MSK_IMSK6_EINT3_Msk          (0x40UL)                  /*!< INTC MSK: IMSK6_EINT3 (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK5_EINT2_Pos          (5UL)                     /*!< INTC MSK: IMSK5_EINT2 (Bit 5)                         */
+#define INTC_MSK_IMSK5_EINT2_Msk          (0x20UL)                  /*!< INTC MSK: IMSK5_EINT2 (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK4_EINT1_Pos          (4UL)                     /*!< INTC MSK: IMSK4_EINT1 (Bit 4)                         */
+#define INTC_MSK_IMSK4_EINT1_Msk          (0x10UL)                  /*!< INTC MSK: IMSK4_EINT1 (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK3_EINT0_Pos          (3UL)                     /*!< INTC MSK: IMSK3_EINT0 (Bit 3)                         */
+#define INTC_MSK_IMSK3_EINT0_Msk          (0x8UL)                   /*!< INTC MSK: IMSK3_EINT0 (Bitfield-Mask: 0x01)           */
+#define INTC_MSK_IMSK2_WDT_Pos            (2UL)                     /*!< INTC MSK: IMSK2_WDT (Bit 2)                           */
+#define INTC_MSK_IMSK2_WDT_Msk            (0x4UL)                   /*!< INTC MSK: IMSK2_WDT (Bitfield-Mask: 0x01)             */
+#define INTC_MSK_IMSK1_WUT_Pos            (1UL)                     /*!< INTC MSK: IMSK1_WUT (Bit 1)                           */
+#define INTC_MSK_IMSK1_WUT_Msk            (0x2UL)                   /*!< INTC MSK: IMSK1_WUT (Bitfield-Mask: 0x01)             */
+#define INTC_MSK_IMSK0_LVI_Pos            (0UL)                     /*!< INTC MSK: IMSK0_LVI (Bit 0)                           */
+#define INTC_MSK_IMSK0_LVI_Msk            (0x1UL)                   /*!< INTC MSK: IMSK0_LVI (Bitfield-Mask: 0x01)             */
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCUCC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  VENDORID  ======================================================== */
+#define SCUCC_VENDORID_VENDID_Pos         (0UL)                     /*!< SCUCC VENDORID: VENDID (Bit 0)                        */
+#define SCUCC_VENDORID_VENDID_Msk         (0xffffffffUL)            /*!< SCUCC VENDORID: VENDID (Bitfield-Mask: 0xffffffff)    */
+/* ========================================================  CHIPID  ========================================================= */
+#define SCUCC_CHIPID_CHIPID_Pos           (0UL)                     /*!< SCUCC CHIPID: CHIPID (Bit 0)                          */
+#define SCUCC_CHIPID_CHIPID_Msk           (0xffffffffUL)            /*!< SCUCC CHIPID: CHIPID (Bitfield-Mask: 0xffffffff)      */
+/* =========================================================  REVNR  ========================================================= */
+#define SCUCC_REVNR_REVNO_Pos             (0UL)                     /*!< SCUCC REVNR: REVNO (Bit 0)                            */
+#define SCUCC_REVNR_REVNO_Msk             (0xffUL)                  /*!< SCUCC REVNR: REVNO (Bitfield-Mask: 0xff)              */
+/* ========================================================  PMREMAP  ======================================================== */
+#define SCUCC_PMREMAP_WTIDKY_Pos          (16UL)                    /*!< SCUCC PMREMAP: WTIDKY (Bit 16)                        */
+#define SCUCC_PMREMAP_WTIDKY_Msk          (0xffff0000UL)            /*!< SCUCC PMREMAP: WTIDKY (Bitfield-Mask: 0xffff)         */
+#define SCUCC_PMREMAP_nPMREM_Pos          (8UL)                     /*!< SCUCC PMREMAP: nPMREM (Bit 8)                         */
+#define SCUCC_PMREMAP_nPMREM_Msk          (0xff00UL)                /*!< SCUCC PMREMAP: nPMREM (Bitfield-Mask: 0xff)           */
+#define SCUCC_PMREMAP_PMREM_Pos           (0UL)                     /*!< SCUCC PMREMAP: PMREM (Bit 0)                          */
+#define SCUCC_PMREMAP_PMREM_Msk           (0xffUL)                  /*!< SCUCC PMREMAP: PMREM (Bitfield-Mask: 0xff)            */
+/* ========================================================  BTPSCR  ========================================================= */
+#define SCUCC_BTPSCR_BFIND_Pos            (5UL)                     /*!< SCUCC BTPSCR: BFIND (Bit 5)                           */
+#define SCUCC_BTPSCR_BFIND_Msk            (0x60UL)                  /*!< SCUCC BTPSCR: BFIND (Bitfield-Mask: 0x03)             */
+#define SCUCC_BTPSCR_BTPSTA_Pos           (0UL)                     /*!< SCUCC BTPSCR: BTPSTA (Bit 0)                          */
+#define SCUCC_BTPSCR_BTPSTA_Msk           (0x1UL)                   /*!< SCUCC BTPSCR: BTPSTA (Bitfield-Mask: 0x01)            */
+/* ========================================================  RSTSSR  ========================================================= */
+#define SCUCC_RSTSSR_MONSTA_Pos           (5UL)                     /*!< SCUCC RSTSSR: MONSTA (Bit 5)                          */
+#define SCUCC_RSTSSR_MONSTA_Msk           (0x20UL)                  /*!< SCUCC RSTSSR: MONSTA (Bitfield-Mask: 0x01)            */
+#define SCUCC_RSTSSR_SWSTA_Pos            (4UL)                     /*!< SCUCC RSTSSR: SWSTA (Bit 4)                           */
+#define SCUCC_RSTSSR_SWSTA_Msk            (0x10UL)                  /*!< SCUCC RSTSSR: SWSTA (Bitfield-Mask: 0x01)             */
+#define SCUCC_RSTSSR_EXTSTA_Pos           (3UL)                     /*!< SCUCC RSTSSR: EXTSTA (Bit 3)                          */
+#define SCUCC_RSTSSR_EXTSTA_Msk           (0x8UL)                   /*!< SCUCC RSTSSR: EXTSTA (Bitfield-Mask: 0x01)            */
+#define SCUCC_RSTSSR_WDTSTA_Pos           (2UL)                     /*!< SCUCC RSTSSR: WDTSTA (Bit 2)                          */
+#define SCUCC_RSTSSR_WDTSTA_Msk           (0x4UL)                   /*!< SCUCC RSTSSR: WDTSTA (Bitfield-Mask: 0x01)            */
+#define SCUCC_RSTSSR_LVRSTA_Pos           (1UL)                     /*!< SCUCC RSTSSR: LVRSTA (Bit 1)                          */
+#define SCUCC_RSTSSR_LVRSTA_Msk           (0x2UL)                   /*!< SCUCC RSTSSR: LVRSTA (Bitfield-Mask: 0x01)            */
+#define SCUCC_RSTSSR_PORSTA_Pos           (0UL)                     /*!< SCUCC RSTSSR: PORSTA (Bit 0)                          */
+#define SCUCC_RSTSSR_PORSTA_Msk           (0x1UL)                   /*!< SCUCC RSTSSR: PORSTA (Bitfield-Mask: 0x01)            */
+/* ========================================================  NMISRCR  ======================================================== */
+#define SCUCC_NMISRCR_NMICON_Pos          (7UL)                     /*!< SCUCC NMISRCR: NMICON (Bit 7)                         */
+#define SCUCC_NMISRCR_NMICON_Msk          (0x80UL)                  /*!< SCUCC NMISRCR: NMICON (Bitfield-Mask: 0x01)           */
+#define SCUCC_NMISRCR_MONINT_Pos          (6UL)                     /*!< SCUCC NMISRCR: MONINT (Bit 6)                         */
+#define SCUCC_NMISRCR_MONINT_Msk          (0x40UL)                  /*!< SCUCC NMISRCR: MONINT (Bitfield-Mask: 0x01)           */
+#define SCUCC_NMISRCR_NMISRC_Pos          (0UL)                     /*!< SCUCC NMISRCR: NMISRC (Bit 0)                         */
+#define SCUCC_NMISRCR_NMISRC_Msk          (0x1fUL)                  /*!< SCUCC NMISRCR: NMISRC (Bitfield-Mask: 0x1f)           */
+/* ========================================================  SWRSTR  ========================================================= */
+#define SCUCC_SWRSTR_WTIDKY_Pos           (16UL)                    /*!< SCUCC SWRSTR: WTIDKY (Bit 16)                         */
+#define SCUCC_SWRSTR_WTIDKY_Msk           (0xffff0000UL)            /*!< SCUCC SWRSTR: WTIDKY (Bitfield-Mask: 0xffff)          */
+#define SCUCC_SWRSTR_SWRST_Pos            (0UL)                     /*!< SCUCC SWRSTR: SWRST (Bit 0)                           */
+#define SCUCC_SWRSTR_SWRST_Msk            (0xffUL)                  /*!< SCUCC SWRSTR: SWRST (Bitfield-Mask: 0xff)             */
+/* ========================================================  SRSTVR  ========================================================= */
+#define SCUCC_SRSTVR_VALID_Pos            (0UL)                     /*!< SCUCC SRSTVR: VALID (Bit 0)                           */
+#define SCUCC_SRSTVR_VALID_Msk            (0xffUL)                  /*!< SCUCC SRSTVR: VALID (Bitfield-Mask: 0xff)             */
+/* =========================================================  WUTCR  ========================================================= */
+#define SCUCC_WUTCR_WUTIEN_Pos            (7UL)                     /*!< SCUCC WUTCR: WUTIEN (Bit 7)                           */
+#define SCUCC_WUTCR_WUTIEN_Msk            (0x80UL)                  /*!< SCUCC WUTCR: WUTIEN (Bitfield-Mask: 0x01)             */
+#define SCUCC_WUTCR_CNTRLD_Pos            (1UL)                     /*!< SCUCC WUTCR: CNTRLD (Bit 1)                           */
+#define SCUCC_WUTCR_CNTRLD_Msk            (0x2UL)                   /*!< SCUCC WUTCR: CNTRLD (Bitfield-Mask: 0x01)             */
+#define SCUCC_WUTCR_WUTIFLAG_Pos          (0UL)                     /*!< SCUCC WUTCR: WUTIFLAG (Bit 0)                         */
+#define SCUCC_WUTCR_WUTIFLAG_Msk          (0x1UL)                   /*!< SCUCC WUTCR: WUTIFLAG (Bitfield-Mask: 0x01)           */
+/* =========================================================  WUTDR  ========================================================= */
+#define SCUCC_WUTDR_WUTDATA_Pos           (0UL)                     /*!< SCUCC WUTDR: WUTDATA (Bit 0)                          */
+#define SCUCC_WUTDR_WUTDATA_Msk           (0xffffUL)                /*!< SCUCC WUTDR: WUTDATA (Bitfield-Mask: 0xffff)          */
+/* ========================================================  HIRCTRM  ======================================================== */
+#define SCUCC_HIRCTRM_WTIDKY_Pos          (16UL)                    /*!< SCUCC HIRCTRM: WTIDKY (Bit 16)                        */
+#define SCUCC_HIRCTRM_WTIDKY_Msk          (0xffff0000UL)            /*!< SCUCC HIRCTRM: WTIDKY (Bitfield-Mask: 0xffff)         */
+#define SCUCC_HIRCTRM_nTRMH_Pos           (8UL)                     /*!< SCUCC HIRCTRM: nTRMH (Bit 8)                          */
+#define SCUCC_HIRCTRM_nTRMH_Msk           (0xff00UL)                /*!< SCUCC HIRCTRM: nTRMH (Bitfield-Mask: 0xff)            */
+#define SCUCC_HIRCTRM_CTRMH_Pos           (5UL)                     /*!< SCUCC HIRCTRM: CTRMH (Bit 5)                          */
+#define SCUCC_HIRCTRM_CTRMH_Msk           (0xe0UL)                  /*!< SCUCC HIRCTRM: CTRMH (Bitfield-Mask: 0x07)            */
+#define SCUCC_HIRCTRM_FTRMH_Pos           (0UL)                     /*!< SCUCC HIRCTRM: FTRMH (Bit 0)                          */
+#define SCUCC_HIRCTRM_FTRMH_Msk           (0x1fUL)                  /*!< SCUCC HIRCTRM: FTRMH (Bitfield-Mask: 0x1f)            */
+/* =======================================================  WDTRCTRM  ======================================================== */
+#define SCUCC_WDTRCTRM_WTIDKY_Pos         (16UL)                    /*!< SCUCC WDTRCTRM: WTIDKY (Bit 16)                       */
+#define SCUCC_WDTRCTRM_WTIDKY_Msk         (0xffff0000UL)            /*!< SCUCC WDTRCTRM: WTIDKY (Bitfield-Mask: 0xffff)        */
+#define SCUCC_WDTRCTRM_nTRMW_Pos          (8UL)                     /*!< SCUCC WDTRCTRM: nTRMW (Bit 8)                         */
+#define SCUCC_WDTRCTRM_nTRMW_Msk          (0xff00UL)                /*!< SCUCC WDTRCTRM: nTRMW (Bitfield-Mask: 0xff)           */
+#define SCUCC_WDTRCTRM_CTRMW_Pos          (4UL)                     /*!< SCUCC WDTRCTRM: CTRMW (Bit 4)                         */
+#define SCUCC_WDTRCTRM_CTRMW_Msk          (0xf0UL)                  /*!< SCUCC WDTRCTRM: CTRMW (Bitfield-Mask: 0x0f)           */
+#define SCUCC_WDTRCTRM_FTRMW_Pos          (0UL)                     /*!< SCUCC WDTRCTRM: FTRMW (Bit 0)                         */
+#define SCUCC_WDTRCTRM_FTRMW_Msk          (0x7UL)                   /*!< SCUCC WDTRCTRM: FTRMW (Bitfield-Mask: 0x07)           */
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCUCG                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SCCR  ========================================================== */
+#define SCUCG_SCCR_WTIDKY_Pos             (16UL)                    /*!< SCUCG SCCR: WTIDKY (Bit 16)                           */
+#define SCUCG_SCCR_WTIDKY_Msk             (0xffff0000UL)            /*!< SCUCG SCCR: WTIDKY (Bitfield-Mask: 0xffff)            */
+#define SCUCG_SCCR_MCLKSEL_Pos            (0UL)                     /*!< SCUCG SCCR: MCLKSEL (Bit 0)                           */
+#define SCUCG_SCCR_MCLKSEL_Msk            (0x3UL)                   /*!< SCUCG SCCR: MCLKSEL (Bitfield-Mask: 0x03)             */
+/* ========================================================  CLKSRCR  ======================================================== */
+#define SCUCG_CLKSRCR_WTIDKY_Pos          (16UL)                    /*!< SCUCG CLKSRCR: WTIDKY (Bit 16)                        */
+#define SCUCG_CLKSRCR_WTIDKY_Msk          (0xffff0000UL)            /*!< SCUCG CLKSRCR: WTIDKY (Bitfield-Mask: 0xffff)         */
+#define SCUCG_CLKSRCR_HIRCSEL_Pos         (12UL)                    /*!< SCUCG CLKSRCR: HIRCSEL (Bit 12)                       */
+#define SCUCG_CLKSRCR_HIRCSEL_Msk         (0x3000UL)                /*!< SCUCG CLKSRCR: HIRCSEL (Bitfield-Mask: 0x03)          */
+#define SCUCG_CLKSRCR_XMFRNG_Pos          (8UL)                     /*!< SCUCG CLKSRCR: XMFRNG (Bit 8)                         */
+#define SCUCG_CLKSRCR_XMFRNG_Msk          (0x100UL)                 /*!< SCUCG CLKSRCR: XMFRNG (Bitfield-Mask: 0x01)           */
+#define SCUCG_CLKSRCR_WDTRCEN_Pos         (3UL)                     /*!< SCUCG CLKSRCR: WDTRCEN (Bit 3)                        */
+#define SCUCG_CLKSRCR_WDTRCEN_Msk         (0x8UL)                   /*!< SCUCG CLKSRCR: WDTRCEN (Bitfield-Mask: 0x01)          */
+#define SCUCG_CLKSRCR_HIRCEN_Pos          (2UL)                     /*!< SCUCG CLKSRCR: HIRCEN (Bit 2)                         */
+#define SCUCG_CLKSRCR_HIRCEN_Msk          (0x4UL)                   /*!< SCUCG CLKSRCR: HIRCEN (Bitfield-Mask: 0x01)           */
+#define SCUCG_CLKSRCR_XMOSCEN_Pos         (1UL)                     /*!< SCUCG CLKSRCR: XMOSCEN (Bit 1)                        */
+#define SCUCG_CLKSRCR_XMOSCEN_Msk         (0x2UL)                   /*!< SCUCG CLKSRCR: XMOSCEN (Bitfield-Mask: 0x01)          */
+#define SCUCG_CLKSRCR_XSOSCEN_Pos         (0UL)                     /*!< SCUCG CLKSRCR: XSOSCEN (Bit 0)                        */
+#define SCUCG_CLKSRCR_XSOSCEN_Msk         (0x1UL)                   /*!< SCUCG CLKSRCR: XSOSCEN (Bitfield-Mask: 0x01)          */
+/* ========================================================  SCDIVR1  ======================================================== */
+#define SCUCG_SCDIVR1_WLDIV_Pos           (4UL)                     /*!< SCUCG SCDIVR1: WLDIV (Bit 4)                          */
+#define SCUCG_SCDIVR1_WLDIV_Msk           (0x70UL)                  /*!< SCUCG SCDIVR1: WLDIV (Bitfield-Mask: 0x07)            */
+#define SCUCG_SCDIVR1_HDIV_Pos            (0UL)                     /*!< SCUCG SCDIVR1: HDIV (Bit 0)                           */
+#define SCUCG_SCDIVR1_HDIV_Msk            (0x7UL)                   /*!< SCUCG SCDIVR1: HDIV (Bitfield-Mask: 0x07)             */
+/* ========================================================  SCDIVR2  ======================================================== */
+#define SCUCG_SCDIVR2_SYSTDIV_Pos         (4UL)                     /*!< SCUCG SCDIVR2: SYSTDIV (Bit 4)                        */
+#define SCUCG_SCDIVR2_SYSTDIV_Msk         (0x30UL)                  /*!< SCUCG SCDIVR2: SYSTDIV (Bitfield-Mask: 0x03)          */
+#define SCUCG_SCDIVR2_PDIV_Pos            (0UL)                     /*!< SCUCG SCDIVR2: PDIV (Bit 0)                           */
+#define SCUCG_SCDIVR2_PDIV_Msk            (0x3UL)                   /*!< SCUCG SCDIVR2: PDIV (Bitfield-Mask: 0x03)             */
+/* ========================================================  CLKOCR  ========================================================= */
+#define SCUCG_CLKOCR_CLKOEN_Pos           (7UL)                     /*!< SCUCG CLKOCR: CLKOEN (Bit 7)                          */
+#define SCUCG_CLKOCR_CLKOEN_Msk           (0x80UL)                  /*!< SCUCG CLKOCR: CLKOEN (Bitfield-Mask: 0x01)            */
+#define SCUCG_CLKOCR_POLSEL_Pos           (6UL)                     /*!< SCUCG CLKOCR: POLSEL (Bit 6)                          */
+#define SCUCG_CLKOCR_POLSEL_Msk           (0x40UL)                  /*!< SCUCG CLKOCR: POLSEL (Bitfield-Mask: 0x01)            */
+#define SCUCG_CLKOCR_CLKODIV_Pos          (3UL)                     /*!< SCUCG CLKOCR: CLKODIV (Bit 3)                         */
+#define SCUCG_CLKOCR_CLKODIV_Msk          (0x38UL)                  /*!< SCUCG CLKOCR: CLKODIV (Bitfield-Mask: 0x07)           */
+#define SCUCG_CLKOCR_CLKOS_Pos            (0UL)                     /*!< SCUCG CLKOCR: CLKOS (Bit 0)                           */
+#define SCUCG_CLKOCR_CLKOS_Msk            (0x7UL)                   /*!< SCUCG CLKOCR: CLKOS (Bitfield-Mask: 0x07)             */
+/* ========================================================  CMONCR  ========================================================= */
+#define SCUCG_CMONCR_MONEN_Pos            (7UL)                     /*!< SCUCG CMONCR: MONEN (Bit 7)                           */
+#define SCUCG_CMONCR_MONEN_Msk            (0x80UL)                  /*!< SCUCG CMONCR: MONEN (Bitfield-Mask: 0x01)             */
+#define SCUCG_CMONCR_MACTS_Pos            (5UL)                     /*!< SCUCG CMONCR: MACTS (Bit 5)                           */
+#define SCUCG_CMONCR_MACTS_Msk            (0x60UL)                  /*!< SCUCG CMONCR: MACTS (Bitfield-Mask: 0x03)             */
+#define SCUCG_CMONCR_MONFLAG_Pos          (3UL)                     /*!< SCUCG CMONCR: MONFLAG (Bit 3)                         */
+#define SCUCG_CMONCR_MONFLAG_Msk          (0x8UL)                   /*!< SCUCG CMONCR: MONFLAG (Bitfield-Mask: 0x01)           */
+#define SCUCG_CMONCR_NMINTFG_Pos          (2UL)                     /*!< SCUCG CMONCR: NMINTFG (Bit 2)                         */
+#define SCUCG_CMONCR_NMINTFG_Msk          (0x4UL)                   /*!< SCUCG CMONCR: NMINTFG (Bitfield-Mask: 0x01)           */
+#define SCUCG_CMONCR_MONCS_Pos            (0UL)                     /*!< SCUCG CMONCR: MONCS (Bit 0)                           */
+#define SCUCG_CMONCR_MONCS_Msk            (0x3UL)                   /*!< SCUCG CMONCR: MONCS (Bitfield-Mask: 0x03)             */
+/* =======================================================  PPCLKEN1  ======================================================== */
+#define SCUCG_PPCLKEN1_T21CLKE_Pos        (21UL)                    /*!< SCUCG PPCLKEN1: T21CLKE (Bit 21)                      */
+#define SCUCG_PPCLKEN1_T21CLKE_Msk        (0x200000UL)              /*!< SCUCG PPCLKEN1: T21CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T20CLKE_Pos        (20UL)                    /*!< SCUCG PPCLKEN1: T20CLKE (Bit 20)                      */
+#define SCUCG_PPCLKEN1_T20CLKE_Msk        (0x100000UL)              /*!< SCUCG PPCLKEN1: T20CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T30CLKE_Pos        (19UL)                    /*!< SCUCG PPCLKEN1: T30CLKE (Bit 19)                      */
+#define SCUCG_PPCLKEN1_T30CLKE_Msk        (0x80000UL)               /*!< SCUCG PPCLKEN1: T30CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T12CLKE_Pos        (18UL)                    /*!< SCUCG PPCLKEN1: T12CLKE (Bit 18)                      */
+#define SCUCG_PPCLKEN1_T12CLKE_Msk        (0x40000UL)               /*!< SCUCG PPCLKEN1: T12CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T11CLKE_Pos        (17UL)                    /*!< SCUCG PPCLKEN1: T11CLKE (Bit 17)                      */
+#define SCUCG_PPCLKEN1_T11CLKE_Msk        (0x20000UL)               /*!< SCUCG PPCLKEN1: T11CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T10CLKE_Pos        (16UL)                    /*!< SCUCG PPCLKEN1: T10CLKE (Bit 16)                      */
+#define SCUCG_PPCLKEN1_T10CLKE_Msk        (0x10000UL)               /*!< SCUCG PPCLKEN1: T10CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T16CLKE_Pos        (11UL)                    /*!< SCUCG PPCLKEN1: T16CLKE (Bit 11)                      */
+#define SCUCG_PPCLKEN1_T16CLKE_Msk        (0x800UL)                 /*!< SCUCG PPCLKEN1: T16CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T15CLKE_Pos        (10UL)                    /*!< SCUCG PPCLKEN1: T15CLKE (Bit 10)                      */
+#define SCUCG_PPCLKEN1_T15CLKE_Msk        (0x400UL)                 /*!< SCUCG PPCLKEN1: T15CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T14CLKE_Pos        (9UL)                     /*!< SCUCG PPCLKEN1: T14CLKE (Bit 9)                       */
+#define SCUCG_PPCLKEN1_T14CLKE_Msk        (0x200UL)                 /*!< SCUCG PPCLKEN1: T14CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_T13CLKE_Pos        (8UL)                     /*!< SCUCG PPCLKEN1: T13CLKE (Bit 8)                       */
+#define SCUCG_PPCLKEN1_T13CLKE_Msk        (0x100UL)                 /*!< SCUCG PPCLKEN1: T13CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN1_PFCLKE_Pos         (5UL)                     /*!< SCUCG PPCLKEN1: PFCLKE (Bit 5)                        */
+#define SCUCG_PPCLKEN1_PFCLKE_Msk         (0x20UL)                  /*!< SCUCG PPCLKEN1: PFCLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN1_PECLKE_Pos         (4UL)                     /*!< SCUCG PPCLKEN1: PECLKE (Bit 4)                        */
+#define SCUCG_PPCLKEN1_PECLKE_Msk         (0x10UL)                  /*!< SCUCG PPCLKEN1: PECLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN1_PDCLKE_Pos         (3UL)                     /*!< SCUCG PPCLKEN1: PDCLKE (Bit 3)                        */
+#define SCUCG_PPCLKEN1_PDCLKE_Msk         (0x8UL)                   /*!< SCUCG PPCLKEN1: PDCLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN1_PCCLKE_Pos         (2UL)                     /*!< SCUCG PPCLKEN1: PCCLKE (Bit 2)                        */
+#define SCUCG_PPCLKEN1_PCCLKE_Msk         (0x4UL)                   /*!< SCUCG PPCLKEN1: PCCLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN1_PBCLKE_Pos         (1UL)                     /*!< SCUCG PPCLKEN1: PBCLKE (Bit 1)                        */
+#define SCUCG_PPCLKEN1_PBCLKE_Msk         (0x2UL)                   /*!< SCUCG PPCLKEN1: PBCLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN1_PACLKE_Pos         (0UL)                     /*!< SCUCG PPCLKEN1: PACLKE (Bit 0)                        */
+#define SCUCG_PPCLKEN1_PACLKE_Msk         (0x1UL)                   /*!< SCUCG PPCLKEN1: PACLKE (Bitfield-Mask: 0x01)          */
+/* =======================================================  PPCLKEN2  ======================================================== */
+#define SCUCG_PPCLKEN2_FMCLKE_Pos         (19UL)                    /*!< SCUCG PPCLKEN2: FMCLKE (Bit 19)                       */
+#define SCUCG_PPCLKEN2_FMCLKE_Msk         (0x80000UL)               /*!< SCUCG PPCLKEN2: FMCLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN2_LVICLKE_Pos        (18UL)                    /*!< SCUCG PPCLKEN2: LVICLKE (Bit 18)                      */
+#define SCUCG_PPCLKEN2_LVICLKE_Msk        (0x40000UL)               /*!< SCUCG PPCLKEN2: LVICLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN2_WDTCLKE_Pos        (17UL)                    /*!< SCUCG PPCLKEN2: WDTCLKE (Bit 17)                      */
+#define SCUCG_PPCLKEN2_WDTCLKE_Msk        (0x20000UL)               /*!< SCUCG PPCLKEN2: WDTCLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN2_WTCLKE_Pos         (16UL)                    /*!< SCUCG PPCLKEN2: WTCLKE (Bit 16)                       */
+#define SCUCG_PPCLKEN2_WTCLKE_Msk         (0x10000UL)               /*!< SCUCG PPCLKEN2: WTCLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN2_LCDCLKE_Pos        (13UL)                    /*!< SCUCG PPCLKEN2: LCDCLKE (Bit 13)                      */
+#define SCUCG_PPCLKEN2_LCDCLKE_Msk        (0x2000UL)                /*!< SCUCG PPCLKEN2: LCDCLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN2_CRCLKE_Pos         (12UL)                    /*!< SCUCG PPCLKEN2: CRCLKE (Bit 12)                       */
+#define SCUCG_PPCLKEN2_CRCLKE_Msk         (0x1000UL)                /*!< SCUCG PPCLKEN2: CRCLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN2_ADCLKE_Pos         (10UL)                    /*!< SCUCG PPCLKEN2: ADCLKE (Bit 10)                       */
+#define SCUCG_PPCLKEN2_ADCLKE_Msk         (0x400UL)                 /*!< SCUCG PPCLKEN2: ADCLKE (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPCLKEN2_I2C2CLKE_Pos       (8UL)                     /*!< SCUCG PPCLKEN2: I2C2CLKE (Bit 8)                      */
+#define SCUCG_PPCLKEN2_I2C2CLKE_Msk       (0x100UL)                 /*!< SCUCG PPCLKEN2: I2C2CLKE (Bitfield-Mask: 0x01)        */
+#define SCUCG_PPCLKEN2_I2C1CLKE_Pos       (7UL)                     /*!< SCUCG PPCLKEN2: I2C1CLKE (Bit 7)                      */
+#define SCUCG_PPCLKEN2_I2C1CLKE_Msk       (0x80UL)                  /*!< SCUCG PPCLKEN2: I2C1CLKE (Bitfield-Mask: 0x01)        */
+#define SCUCG_PPCLKEN2_I2C0CLKE_Pos       (6UL)                     /*!< SCUCG PPCLKEN2: I2C0CLKE (Bit 6)                      */
+#define SCUCG_PPCLKEN2_I2C0CLKE_Msk       (0x40UL)                  /*!< SCUCG PPCLKEN2: I2C0CLKE (Bitfield-Mask: 0x01)        */
+#define SCUCG_PPCLKEN2_UST13CLKE_Pos      (5UL)                     /*!< SCUCG PPCLKEN2: UST13CLKE (Bit 5)                     */
+#define SCUCG_PPCLKEN2_UST13CLKE_Msk      (0x20UL)                  /*!< SCUCG PPCLKEN2: UST13CLKE (Bitfield-Mask: 0x01)       */
+#define SCUCG_PPCLKEN2_UST12CLKE_Pos      (4UL)                     /*!< SCUCG PPCLKEN2: UST12CLKE (Bit 4)                     */
+#define SCUCG_PPCLKEN2_UST12CLKE_Msk      (0x10UL)                  /*!< SCUCG PPCLKEN2: UST12CLKE (Bitfield-Mask: 0x01)       */
+#define SCUCG_PPCLKEN2_UT1CLKE_Pos        (3UL)                     /*!< SCUCG PPCLKEN2: UT1CLKE (Bit 3)                       */
+#define SCUCG_PPCLKEN2_UT1CLKE_Msk        (0x8UL)                   /*!< SCUCG PPCLKEN2: UT1CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN2_UT0CLKE_Pos        (2UL)                     /*!< SCUCG PPCLKEN2: UT0CLKE (Bit 2)                       */
+#define SCUCG_PPCLKEN2_UT0CLKE_Msk        (0x4UL)                   /*!< SCUCG PPCLKEN2: UT0CLKE (Bitfield-Mask: 0x01)         */
+#define SCUCG_PPCLKEN2_UST11CLKE_Pos      (1UL)                     /*!< SCUCG PPCLKEN2: UST11CLKE (Bit 1)                     */
+#define SCUCG_PPCLKEN2_UST11CLKE_Msk      (0x2UL)                   /*!< SCUCG PPCLKEN2: UST11CLKE (Bitfield-Mask: 0x01)       */
+#define SCUCG_PPCLKEN2_UST10CLKE_Pos      (0UL)                     /*!< SCUCG PPCLKEN2: UST10CLKE (Bit 0)                     */
+#define SCUCG_PPCLKEN2_UST10CLKE_Msk      (0x1UL)                   /*!< SCUCG PPCLKEN2: UST10CLKE (Bitfield-Mask: 0x01)       */
+/* ========================================================  PPCLKSR  ======================================================== */
+#define SCUCG_PPCLKSR_T20CLK_Pos          (20UL)                    /*!< SCUCG PPCLKSR: T20CLK (Bit 20)                        */
+#define SCUCG_PPCLKSR_T20CLK_Msk          (0x100000UL)              /*!< SCUCG PPCLKSR: T20CLK (Bitfield-Mask: 0x01)           */
+#define SCUCG_PPCLKSR_T30CLK_Pos          (17UL)                    /*!< SCUCG PPCLKSR: T30CLK (Bit 17)                        */
+#define SCUCG_PPCLKSR_T30CLK_Msk          (0x20000UL)               /*!< SCUCG PPCLKSR: T30CLK (Bitfield-Mask: 0x01)           */
+#define SCUCG_PPCLKSR_LCDCLK_Pos          (6UL)                     /*!< SCUCG PPCLKSR: LCDCLK (Bit 6)                         */
+#define SCUCG_PPCLKSR_LCDCLK_Msk          (0xc0UL)                  /*!< SCUCG PPCLKSR: LCDCLK (Bitfield-Mask: 0x03)           */
+#define SCUCG_PPCLKSR_WTCLK_Pos           (3UL)                     /*!< SCUCG PPCLKSR: WTCLK (Bit 3)                          */
+#define SCUCG_PPCLKSR_WTCLK_Msk           (0x18UL)                  /*!< SCUCG PPCLKSR: WTCLK (Bitfield-Mask: 0x03)            */
+#define SCUCG_PPCLKSR_WDTCLK_Pos          (0UL)                     /*!< SCUCG PPCLKSR: WDTCLK (Bit 0)                         */
+#define SCUCG_PPCLKSR_WDTCLK_Msk          (0x1UL)                   /*!< SCUCG PPCLKSR: WDTCLK (Bitfield-Mask: 0x01)           */
+/* ========================================================  PPRST1  ========================================================= */
+#define SCUCG_PPRST1_T21RST_Pos           (21UL)                    /*!< SCUCG PPRST1: T21RST (Bit 21)                         */
+#define SCUCG_PPRST1_T21RST_Msk           (0x200000UL)              /*!< SCUCG PPRST1: T21RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T20RST_Pos           (20UL)                    /*!< SCUCG PPRST1: T20RST (Bit 20)                         */
+#define SCUCG_PPRST1_T20RST_Msk           (0x100000UL)              /*!< SCUCG PPRST1: T20RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T30RST_Pos           (19UL)                    /*!< SCUCG PPRST1: T30RST (Bit 19)                         */
+#define SCUCG_PPRST1_T30RST_Msk           (0x80000UL)               /*!< SCUCG PPRST1: T30RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T12RST_Pos           (18UL)                    /*!< SCUCG PPRST1: T12RST (Bit 18)                         */
+#define SCUCG_PPRST1_T12RST_Msk           (0x40000UL)               /*!< SCUCG PPRST1: T12RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T11RST_Pos           (17UL)                    /*!< SCUCG PPRST1: T11RST (Bit 17)                         */
+#define SCUCG_PPRST1_T11RST_Msk           (0x20000UL)               /*!< SCUCG PPRST1: T11RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T10RST_Pos           (16UL)                    /*!< SCUCG PPRST1: T10RST (Bit 16)                         */
+#define SCUCG_PPRST1_T10RST_Msk           (0x10000UL)               /*!< SCUCG PPRST1: T10RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T16RST_Pos           (11UL)                    /*!< SCUCG PPRST1: T16RST (Bit 11)                         */
+#define SCUCG_PPRST1_T16RST_Msk           (0x800UL)                 /*!< SCUCG PPRST1: T16RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T15RST_Pos           (10UL)                    /*!< SCUCG PPRST1: T15RST (Bit 10)                         */
+#define SCUCG_PPRST1_T15RST_Msk           (0x400UL)                 /*!< SCUCG PPRST1: T15RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T14RST_Pos           (9UL)                     /*!< SCUCG PPRST1: T14RST (Bit 9)                          */
+#define SCUCG_PPRST1_T14RST_Msk           (0x200UL)                 /*!< SCUCG PPRST1: T14RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_T13RST_Pos           (8UL)                     /*!< SCUCG PPRST1: T13RST (Bit 8)                          */
+#define SCUCG_PPRST1_T13RST_Msk           (0x100UL)                 /*!< SCUCG PPRST1: T13RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST1_PFRST_Pos            (5UL)                     /*!< SCUCG PPRST1: PFRST (Bit 5)                           */
+#define SCUCG_PPRST1_PFRST_Msk            (0x20UL)                  /*!< SCUCG PPRST1: PFRST (Bitfield-Mask: 0x01)             */
+#define SCUCG_PPRST1_PERST_Pos            (4UL)                     /*!< SCUCG PPRST1: PERST (Bit 4)                           */
+#define SCUCG_PPRST1_PERST_Msk            (0x10UL)                  /*!< SCUCG PPRST1: PERST (Bitfield-Mask: 0x01)             */
+#define SCUCG_PPRST1_PDRST_Pos            (3UL)                     /*!< SCUCG PPRST1: PDRST (Bit 3)                           */
+#define SCUCG_PPRST1_PDRST_Msk            (0x8UL)                   /*!< SCUCG PPRST1: PDRST (Bitfield-Mask: 0x01)             */
+#define SCUCG_PPRST1_PCRST_Pos            (2UL)                     /*!< SCUCG PPRST1: PCRST (Bit 2)                           */
+#define SCUCG_PPRST1_PCRST_Msk            (0x4UL)                   /*!< SCUCG PPRST1: PCRST (Bitfield-Mask: 0x01)             */
+#define SCUCG_PPRST1_PBRST_Pos            (1UL)                     /*!< SCUCG PPRST1: PBRST (Bit 1)                           */
+#define SCUCG_PPRST1_PBRST_Msk            (0x2UL)                   /*!< SCUCG PPRST1: PBRST (Bitfield-Mask: 0x01)             */
+#define SCUCG_PPRST1_PARST_Pos            (0UL)                     /*!< SCUCG PPRST1: PARST (Bit 0)                           */
+#define SCUCG_PPRST1_PARST_Msk            (0x1UL)                   /*!< SCUCG PPRST1: PARST (Bitfield-Mask: 0x01)             */
+/* ========================================================  PPRST2  ========================================================= */
+#define SCUCG_PPRST2_FMCRST_Pos           (19UL)                    /*!< SCUCG PPRST2: FMCRST (Bit 19)                         */
+#define SCUCG_PPRST2_FMCRST_Msk           (0x80000UL)               /*!< SCUCG PPRST2: FMCRST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST2_LVIRST_Pos           (18UL)                    /*!< SCUCG PPRST2: LVIRST (Bit 18)                         */
+#define SCUCG_PPRST2_LVIRST_Msk           (0x40000UL)               /*!< SCUCG PPRST2: LVIRST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST2_WTRST_Pos            (16UL)                    /*!< SCUCG PPRST2: WTRST (Bit 16)                          */
+#define SCUCG_PPRST2_WTRST_Msk            (0x10000UL)               /*!< SCUCG PPRST2: WTRST (Bitfield-Mask: 0x01)             */
+#define SCUCG_PPRST2_LCDRST_Pos           (13UL)                    /*!< SCUCG PPRST2: LCDRST (Bit 13)                         */
+#define SCUCG_PPRST2_LCDRST_Msk           (0x2000UL)                /*!< SCUCG PPRST2: LCDRST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST2_CRRST_Pos            (12UL)                    /*!< SCUCG PPRST2: CRRST (Bit 12)                          */
+#define SCUCG_PPRST2_CRRST_Msk            (0x1000UL)                /*!< SCUCG PPRST2: CRRST (Bitfield-Mask: 0x01)             */
+#define SCUCG_PPRST2_ADRST_Pos            (10UL)                    /*!< SCUCG PPRST2: ADRST (Bit 10)                          */
+#define SCUCG_PPRST2_ADRST_Msk            (0x400UL)                 /*!< SCUCG PPRST2: ADRST (Bitfield-Mask: 0x01)             */
+#define SCUCG_PPRST2_I2C2RST_Pos          (8UL)                     /*!< SCUCG PPRST2: I2C2RST (Bit 8)                         */
+#define SCUCG_PPRST2_I2C2RST_Msk          (0x100UL)                 /*!< SCUCG PPRST2: I2C2RST (Bitfield-Mask: 0x01)           */
+#define SCUCG_PPRST2_I2C1RST_Pos          (7UL)                     /*!< SCUCG PPRST2: I2C1RST (Bit 7)                         */
+#define SCUCG_PPRST2_I2C1RST_Msk          (0x80UL)                  /*!< SCUCG PPRST2: I2C1RST (Bitfield-Mask: 0x01)           */
+#define SCUCG_PPRST2_I2C0RST_Pos          (6UL)                     /*!< SCUCG PPRST2: I2C0RST (Bit 6)                         */
+#define SCUCG_PPRST2_I2C0RST_Msk          (0x40UL)                  /*!< SCUCG PPRST2: I2C0RST (Bitfield-Mask: 0x01)           */
+#define SCUCG_PPRST2_UST13RST_Pos         (5UL)                     /*!< SCUCG PPRST2: UST13RST (Bit 5)                        */
+#define SCUCG_PPRST2_UST13RST_Msk         (0x20UL)                  /*!< SCUCG PPRST2: UST13RST (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPRST2_UST12RST_Pos         (4UL)                     /*!< SCUCG PPRST2: UST12RST (Bit 4)                        */
+#define SCUCG_PPRST2_UST12RST_Msk         (0x10UL)                  /*!< SCUCG PPRST2: UST12RST (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPRST2_UT1RST_Pos           (3UL)                     /*!< SCUCG PPRST2: UT1RST (Bit 3)                          */
+#define SCUCG_PPRST2_UT1RST_Msk           (0x8UL)                   /*!< SCUCG PPRST2: UT1RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST2_UT0RST_Pos           (2UL)                     /*!< SCUCG PPRST2: UT0RST (Bit 2)                          */
+#define SCUCG_PPRST2_UT0RST_Msk           (0x4UL)                   /*!< SCUCG PPRST2: UT0RST (Bitfield-Mask: 0x01)            */
+#define SCUCG_PPRST2_UST11RST_Pos         (1UL)                     /*!< SCUCG PPRST2: UST11RST (Bit 1)                        */
+#define SCUCG_PPRST2_UST11RST_Msk         (0x2UL)                   /*!< SCUCG PPRST2: UST11RST (Bitfield-Mask: 0x01)          */
+#define SCUCG_PPRST2_UST10RST_Pos         (0UL)                     /*!< SCUCG PPRST2: UST10RST (Bit 0)                        */
+#define SCUCG_PPRST2_UST10RST_Msk         (0x1UL)                   /*!< SCUCG PPRST2: UST10RST (Bitfield-Mask: 0x01)          */
+/* ========================================================  XTFLSR  ========================================================= */
+#define SCUCG_XTFLSR_WTIDKY_Pos           (16UL)                    /*!< SCUCG XTFLSR: WTIDKY (Bit 16)                         */
+#define SCUCG_XTFLSR_WTIDKY_Msk           (0xffff0000UL)            /*!< SCUCG XTFLSR: WTIDKY (Bitfield-Mask: 0xffff)          */
+#define SCUCG_XTFLSR_XRNS_Pos             (0UL)                     /*!< SCUCG XTFLSR: XRNS (Bit 0)                            */
+#define SCUCG_XTFLSR_XRNS_Msk             (0x7UL)                   /*!< SCUCG XTFLSR: XRNS (Bitfield-Mask: 0x07)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCULV                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  LVICR  ========================================================= */
+#define SCULV_LVICR_LVIEN_Pos             (7UL)                     /*!< SCULV LVICR: LVIEN (Bit 7)                            */
+#define SCULV_LVICR_LVIEN_Msk             (0x80UL)                  /*!< SCULV LVICR: LVIEN (Bitfield-Mask: 0x01)              */
+#define SCULV_LVICR_LVINTEN_Pos           (5UL)                     /*!< SCULV LVICR: LVINTEN (Bit 5)                          */
+#define SCULV_LVICR_LVINTEN_Msk           (0x20UL)                  /*!< SCULV LVICR: LVINTEN (Bitfield-Mask: 0x01)            */
+#define SCULV_LVICR_LVIFLAG_Pos           (4UL)                     /*!< SCULV LVICR: LVIFLAG (Bit 4)                          */
+#define SCULV_LVICR_LVIFLAG_Msk           (0x10UL)                  /*!< SCULV LVICR: LVIFLAG (Bitfield-Mask: 0x01)            */
+#define SCULV_LVICR_LVIVS_Pos             (0UL)                     /*!< SCULV LVICR: LVIVS (Bit 0)                            */
+#define SCULV_LVICR_LVIVS_Msk             (0xfUL)                   /*!< SCULV LVICR: LVIVS (Bitfield-Mask: 0x0f)              */
+/* =========================================================  LVRCR  ========================================================= */
+#define SCULV_LVRCR_LVREN_Pos             (0UL)                     /*!< SCULV LVRCR: LVREN (Bit 0)                            */
+#define SCULV_LVRCR_LVREN_Msk             (0xffUL)                  /*!< SCULV LVRCR: LVREN (Bitfield-Mask: 0xff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                            Pn                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+#define Pn_MOD_MODE15_Pos                 (30UL)                    /*!< Pn MOD: MODE15 (Bit 30)                               */
+#define Pn_MOD_MODE15_Msk                 (0xc0000000UL)            /*!< Pn MOD: MODE15 (Bitfield-Mask: 0x03)                  */
+#define Pn_MOD_MODE14_Pos                 (28UL)                    /*!< Pn MOD: MODE14 (Bit 28)                               */
+#define Pn_MOD_MODE14_Msk                 (0x30000000UL)            /*!< Pn MOD: MODE14 (Bitfield-Mask: 0x03)                  */
+#define Pn_MOD_MODE13_Pos                 (26UL)                    /*!< Pn MOD: MODE13 (Bit 26)                               */
+#define Pn_MOD_MODE13_Msk                 (0xc000000UL)             /*!< Pn MOD: MODE13 (Bitfield-Mask: 0x03)                  */
+#define Pn_MOD_MODE12_Pos                 (24UL)                    /*!< Pn MOD: MODE12 (Bit 24)                               */
+#define Pn_MOD_MODE12_Msk                 (0x3000000UL)             /*!< Pn MOD: MODE12 (Bitfield-Mask: 0x03)                  */
+#define Pn_MOD_MODE11_Pos                 (22UL)                    /*!< Pn MOD: MODE11 (Bit 22)                               */
+#define Pn_MOD_MODE11_Msk                 (0xc00000UL)              /*!< Pn MOD: MODE11 (Bitfield-Mask: 0x03)                  */
+#define Pn_MOD_MODE10_Pos                 (20UL)                    /*!< Pn MOD: MODE10 (Bit 20)                               */
+#define Pn_MOD_MODE10_Msk                 (0x300000UL)              /*!< Pn MOD: MODE10 (Bitfield-Mask: 0x03)                  */
+#define Pn_MOD_MODE9_Pos                  (18UL)                    /*!< Pn MOD: MODE9 (Bit 18)                                */
+#define Pn_MOD_MODE9_Msk                  (0xc0000UL)               /*!< Pn MOD: MODE9 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE8_Pos                  (16UL)                    /*!< Pn MOD: MODE8 (Bit 16)                                */
+#define Pn_MOD_MODE8_Msk                  (0x30000UL)               /*!< Pn MOD: MODE8 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE7_Pos                  (14UL)                    /*!< Pn MOD: MODE7 (Bit 14)                                */
+#define Pn_MOD_MODE7_Msk                  (0xc000UL)                /*!< Pn MOD: MODE7 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE6_Pos                  (12UL)                    /*!< Pn MOD: MODE6 (Bit 12)                                */
+#define Pn_MOD_MODE6_Msk                  (0x3000UL)                /*!< Pn MOD: MODE6 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE5_Pos                  (10UL)                    /*!< Pn MOD: MODE5 (Bit 10)                                */
+#define Pn_MOD_MODE5_Msk                  (0xc00UL)                 /*!< Pn MOD: MODE5 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE4_Pos                  (8UL)                     /*!< Pn MOD: MODE4 (Bit 8)                                 */
+#define Pn_MOD_MODE4_Msk                  (0x300UL)                 /*!< Pn MOD: MODE4 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE3_Pos                  (6UL)                     /*!< Pn MOD: MODE3 (Bit 6)                                 */
+#define Pn_MOD_MODE3_Msk                  (0xc0UL)                  /*!< Pn MOD: MODE3 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE2_Pos                  (4UL)                     /*!< Pn MOD: MODE2 (Bit 4)                                 */
+#define Pn_MOD_MODE2_Msk                  (0x30UL)                  /*!< Pn MOD: MODE2 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE1_Pos                  (2UL)                     /*!< Pn MOD: MODE1 (Bit 2)                                 */
+#define Pn_MOD_MODE1_Msk                  (0xcUL)                   /*!< Pn MOD: MODE1 (Bitfield-Mask: 0x03)                   */
+#define Pn_MOD_MODE0_Pos                  (0UL)                     /*!< Pn MOD: MODE0 (Bit 0)                                 */
+#define Pn_MOD_MODE0_Msk                  (0x3UL)                   /*!< Pn MOD: MODE0 (Bitfield-Mask: 0x03)                   */
+/* ==========================================================  TYP  ========================================================== */
+#define Pn_TYP_TYP15_Pos                  (15UL)                    /*!< Pn TYP: TYP15 (Bit 15)                                */
+#define Pn_TYP_TYP15_Msk                  (0x8000UL)                /*!< Pn TYP: TYP15 (Bitfield-Mask: 0x01)                   */
+#define Pn_TYP_TYP14_Pos                  (14UL)                    /*!< Pn TYP: TYP14 (Bit 14)                                */
+#define Pn_TYP_TYP14_Msk                  (0x4000UL)                /*!< Pn TYP: TYP14 (Bitfield-Mask: 0x01)                   */
+#define Pn_TYP_TYP13_Pos                  (13UL)                    /*!< Pn TYP: TYP13 (Bit 13)                                */
+#define Pn_TYP_TYP13_Msk                  (0x2000UL)                /*!< Pn TYP: TYP13 (Bitfield-Mask: 0x01)                   */
+#define Pn_TYP_TYP12_Pos                  (12UL)                    /*!< Pn TYP: TYP12 (Bit 12)                                */
+#define Pn_TYP_TYP12_Msk                  (0x1000UL)                /*!< Pn TYP: TYP12 (Bitfield-Mask: 0x01)                   */
+#define Pn_TYP_TYP11_Pos                  (11UL)                    /*!< Pn TYP: TYP11 (Bit 11)                                */
+#define Pn_TYP_TYP11_Msk                  (0x800UL)                 /*!< Pn TYP: TYP11 (Bitfield-Mask: 0x01)                   */
+#define Pn_TYP_TYP10_Pos                  (10UL)                    /*!< Pn TYP: TYP10 (Bit 10)                                */
+#define Pn_TYP_TYP10_Msk                  (0x400UL)                 /*!< Pn TYP: TYP10 (Bitfield-Mask: 0x01)                   */
+#define Pn_TYP_TYP9_Pos                   (9UL)                     /*!< Pn TYP: TYP9 (Bit 9)                                  */
+#define Pn_TYP_TYP9_Msk                   (0x200UL)                 /*!< Pn TYP: TYP9 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP8_Pos                   (8UL)                     /*!< Pn TYP: TYP8 (Bit 8)                                  */
+#define Pn_TYP_TYP8_Msk                   (0x100UL)                 /*!< Pn TYP: TYP8 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP7_Pos                   (7UL)                     /*!< Pn TYP: TYP7 (Bit 7)                                  */
+#define Pn_TYP_TYP7_Msk                   (0x80UL)                  /*!< Pn TYP: TYP7 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP6_Pos                   (6UL)                     /*!< Pn TYP: TYP6 (Bit 6)                                  */
+#define Pn_TYP_TYP6_Msk                   (0x40UL)                  /*!< Pn TYP: TYP6 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP5_Pos                   (5UL)                     /*!< Pn TYP: TYP5 (Bit 5)                                  */
+#define Pn_TYP_TYP5_Msk                   (0x20UL)                  /*!< Pn TYP: TYP5 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP4_Pos                   (4UL)                     /*!< Pn TYP: TYP4 (Bit 4)                                  */
+#define Pn_TYP_TYP4_Msk                   (0x10UL)                  /*!< Pn TYP: TYP4 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP3_Pos                   (3UL)                     /*!< Pn TYP: TYP3 (Bit 3)                                  */
+#define Pn_TYP_TYP3_Msk                   (0x8UL)                   /*!< Pn TYP: TYP3 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP2_Pos                   (2UL)                     /*!< Pn TYP: TYP2 (Bit 2)                                  */
+#define Pn_TYP_TYP2_Msk                   (0x4UL)                   /*!< Pn TYP: TYP2 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP1_Pos                   (1UL)                     /*!< Pn TYP: TYP1 (Bit 1)                                  */
+#define Pn_TYP_TYP1_Msk                   (0x2UL)                   /*!< Pn TYP: TYP1 (Bitfield-Mask: 0x01)                    */
+#define Pn_TYP_TYP0_Pos                   (0UL)                     /*!< Pn TYP: TYP0 (Bit 0)                                  */
+#define Pn_TYP_TYP0_Msk                   (0x1UL)                   /*!< Pn TYP: TYP0 (Bitfield-Mask: 0x01)                    */
+/* =========================================================  AFSR1  ========================================================= */
+#define Pn_AFSR1_AFSR7_Pos                (28UL)                    /*!< Pn AFSR1: AFSR7 (Bit 28)                              */
+#define Pn_AFSR1_AFSR7_Msk                (0xf0000000UL)            /*!< Pn AFSR1: AFSR7 (Bitfield-Mask: 0x0f)                 */
+#define Pn_AFSR1_AFSR6_Pos                (24UL)                    /*!< Pn AFSR1: AFSR6 (Bit 24)                              */
+#define Pn_AFSR1_AFSR6_Msk                (0xf000000UL)             /*!< Pn AFSR1: AFSR6 (Bitfield-Mask: 0x0f)                 */
+#define Pn_AFSR1_AFSR5_Pos                (20UL)                    /*!< Pn AFSR1: AFSR5 (Bit 20)                              */
+#define Pn_AFSR1_AFSR5_Msk                (0xf00000UL)              /*!< Pn AFSR1: AFSR5 (Bitfield-Mask: 0x0f)                 */
+#define Pn_AFSR1_AFSR4_Pos                (16UL)                    /*!< Pn AFSR1: AFSR4 (Bit 16)                              */
+#define Pn_AFSR1_AFSR4_Msk                (0xf0000UL)               /*!< Pn AFSR1: AFSR4 (Bitfield-Mask: 0x0f)                 */
+#define Pn_AFSR1_AFSR3_Pos                (12UL)                    /*!< Pn AFSR1: AFSR3 (Bit 12)                              */
+#define Pn_AFSR1_AFSR3_Msk                (0xf000UL)                /*!< Pn AFSR1: AFSR3 (Bitfield-Mask: 0x0f)                 */
+#define Pn_AFSR1_AFSR2_Pos                (8UL)                     /*!< Pn AFSR1: AFSR2 (Bit 8)                               */
+#define Pn_AFSR1_AFSR2_Msk                (0xf00UL)                 /*!< Pn AFSR1: AFSR2 (Bitfield-Mask: 0x0f)                 */
+#define Pn_AFSR1_AFSR1_Pos                (4UL)                     /*!< Pn AFSR1: AFSR1 (Bit 4)                               */
+#define Pn_AFSR1_AFSR1_Msk                (0xf0UL)                  /*!< Pn AFSR1: AFSR1 (Bitfield-Mask: 0x0f)                 */
+#define Pn_AFSR1_AFSR0_Pos                (0UL)                     /*!< Pn AFSR1: AFSR0 (Bit 0)                               */
+#define Pn_AFSR1_AFSR0_Msk                (0xfUL)                   /*!< Pn AFSR1: AFSR0 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  AFSR2  ========================================================= */
+#define Pn_AFSR2_AFSR15_Pos               (28UL)                    /*!< Pn AFSR2: AFSR15 (Bit 28)                             */
+#define Pn_AFSR2_AFSR15_Msk               (0xf0000000UL)            /*!< Pn AFSR2: AFSR15 (Bitfield-Mask: 0x0f)                */
+#define Pn_AFSR2_AFSR14_Pos               (24UL)                    /*!< Pn AFSR2: AFSR14 (Bit 24)                             */
+#define Pn_AFSR2_AFSR14_Msk               (0xf000000UL)             /*!< Pn AFSR2: AFSR14 (Bitfield-Mask: 0x0f)                */
+#define Pn_AFSR2_AFSR13_Pos               (20UL)                    /*!< Pn AFSR2: AFSR13 (Bit 20)                             */
+#define Pn_AFSR2_AFSR13_Msk               (0xf00000UL)              /*!< Pn AFSR2: AFSR13 (Bitfield-Mask: 0x0f)                */
+#define Pn_AFSR2_AFSR12_Pos               (16UL)                    /*!< Pn AFSR2: AFSR12 (Bit 16)                             */
+#define Pn_AFSR2_AFSR12_Msk               (0xf0000UL)               /*!< Pn AFSR2: AFSR12 (Bitfield-Mask: 0x0f)                */
+#define Pn_AFSR2_AFSR11_Pos               (12UL)                    /*!< Pn AFSR2: AFSR11 (Bit 12)                             */
+#define Pn_AFSR2_AFSR11_Msk               (0xf000UL)                /*!< Pn AFSR2: AFSR11 (Bitfield-Mask: 0x0f)                */
+#define Pn_AFSR2_AFSR10_Pos               (8UL)                     /*!< Pn AFSR2: AFSR10 (Bit 8)                              */
+#define Pn_AFSR2_AFSR10_Msk               (0xf00UL)                 /*!< Pn AFSR2: AFSR10 (Bitfield-Mask: 0x0f)                */
+#define Pn_AFSR2_AFSR9_Pos                (4UL)                     /*!< Pn AFSR2: AFSR9 (Bit 4)                               */
+#define Pn_AFSR2_AFSR9_Msk                (0xf0UL)                  /*!< Pn AFSR2: AFSR9 (Bitfield-Mask: 0x0f)                 */
+#define Pn_AFSR2_AFSR8_Pos                (0UL)                     /*!< Pn AFSR2: AFSR8 (Bit 0)                               */
+#define Pn_AFSR2_AFSR8_Msk                (0xfUL)                   /*!< Pn AFSR2: AFSR8 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  PUPD  ========================================================== */
+#define Pn_PUPD_PUPD15_Pos                (30UL)                    /*!< Pn PUPD: PUPD15 (Bit 30)                              */
+#define Pn_PUPD_PUPD15_Msk                (0xc0000000UL)            /*!< Pn PUPD: PUPD15 (Bitfield-Mask: 0x03)                 */
+#define Pn_PUPD_PUPD14_Pos                (28UL)                    /*!< Pn PUPD: PUPD14 (Bit 28)                              */
+#define Pn_PUPD_PUPD14_Msk                (0x30000000UL)            /*!< Pn PUPD: PUPD14 (Bitfield-Mask: 0x03)                 */
+#define Pn_PUPD_PUPD13_Pos                (26UL)                    /*!< Pn PUPD: PUPD13 (Bit 26)                              */
+#define Pn_PUPD_PUPD13_Msk                (0xc000000UL)             /*!< Pn PUPD: PUPD13 (Bitfield-Mask: 0x03)                 */
+#define Pn_PUPD_PUPD12_Pos                (24UL)                    /*!< Pn PUPD: PUPD12 (Bit 24)                              */
+#define Pn_PUPD_PUPD12_Msk                (0x3000000UL)             /*!< Pn PUPD: PUPD12 (Bitfield-Mask: 0x03)                 */
+#define Pn_PUPD_PUPD11_Pos                (22UL)                    /*!< Pn PUPD: PUPD11 (Bit 22)                              */
+#define Pn_PUPD_PUPD11_Msk                (0xc00000UL)              /*!< Pn PUPD: PUPD11 (Bitfield-Mask: 0x03)                 */
+#define Pn_PUPD_PUPD10_Pos                (20UL)                    /*!< Pn PUPD: PUPD10 (Bit 20)                              */
+#define Pn_PUPD_PUPD10_Msk                (0x300000UL)              /*!< Pn PUPD: PUPD10 (Bitfield-Mask: 0x03)                 */
+#define Pn_PUPD_PUPD9_Pos                 (18UL)                    /*!< Pn PUPD: PUPD9 (Bit 18)                               */
+#define Pn_PUPD_PUPD9_Msk                 (0xc0000UL)               /*!< Pn PUPD: PUPD9 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD8_Pos                 (16UL)                    /*!< Pn PUPD: PUPD8 (Bit 16)                               */
+#define Pn_PUPD_PUPD8_Msk                 (0x30000UL)               /*!< Pn PUPD: PUPD8 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD7_Pos                 (14UL)                    /*!< Pn PUPD: PUPD7 (Bit 14)                               */
+#define Pn_PUPD_PUPD7_Msk                 (0xc000UL)                /*!< Pn PUPD: PUPD7 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD6_Pos                 (12UL)                    /*!< Pn PUPD: PUPD6 (Bit 12)                               */
+#define Pn_PUPD_PUPD6_Msk                 (0x3000UL)                /*!< Pn PUPD: PUPD6 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD5_Pos                 (10UL)                    /*!< Pn PUPD: PUPD5 (Bit 10)                               */
+#define Pn_PUPD_PUPD5_Msk                 (0xc00UL)                 /*!< Pn PUPD: PUPD5 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD4_Pos                 (8UL)                     /*!< Pn PUPD: PUPD4 (Bit 8)                                */
+#define Pn_PUPD_PUPD4_Msk                 (0x300UL)                 /*!< Pn PUPD: PUPD4 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD3_Pos                 (6UL)                     /*!< Pn PUPD: PUPD3 (Bit 6)                                */
+#define Pn_PUPD_PUPD3_Msk                 (0xc0UL)                  /*!< Pn PUPD: PUPD3 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD2_Pos                 (4UL)                     /*!< Pn PUPD: PUPD2 (Bit 4)                                */
+#define Pn_PUPD_PUPD2_Msk                 (0x30UL)                  /*!< Pn PUPD: PUPD2 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD1_Pos                 (2UL)                     /*!< Pn PUPD: PUPD1 (Bit 2)                                */
+#define Pn_PUPD_PUPD1_Msk                 (0xcUL)                   /*!< Pn PUPD: PUPD1 (Bitfield-Mask: 0x03)                  */
+#define Pn_PUPD_PUPD0_Pos                 (0UL)                     /*!< Pn PUPD: PUPD0 (Bit 0)                                */
+#define Pn_PUPD_PUPD0_Msk                 (0x3UL)                   /*!< Pn PUPD: PUPD0 (Bitfield-Mask: 0x03)                  */
+/* =========================================================  INDR  ========================================================== */
+#define Pn_INDR_INDR15_Pos                (15UL)                    /*!< Pn INDR: INDR15 (Bit 15)                              */
+#define Pn_INDR_INDR15_Msk                (0x8000UL)                /*!< Pn INDR: INDR15 (Bitfield-Mask: 0x01)                 */
+#define Pn_INDR_INDR14_Pos                (14UL)                    /*!< Pn INDR: INDR14 (Bit 14)                              */
+#define Pn_INDR_INDR14_Msk                (0x4000UL)                /*!< Pn INDR: INDR14 (Bitfield-Mask: 0x01)                 */
+#define Pn_INDR_INDR13_Pos                (13UL)                    /*!< Pn INDR: INDR13 (Bit 13)                              */
+#define Pn_INDR_INDR13_Msk                (0x2000UL)                /*!< Pn INDR: INDR13 (Bitfield-Mask: 0x01)                 */
+#define Pn_INDR_INDR12_Pos                (12UL)                    /*!< Pn INDR: INDR12 (Bit 12)                              */
+#define Pn_INDR_INDR12_Msk                (0x1000UL)                /*!< Pn INDR: INDR12 (Bitfield-Mask: 0x01)                 */
+#define Pn_INDR_INDR11_Pos                (11UL)                    /*!< Pn INDR: INDR11 (Bit 11)                              */
+#define Pn_INDR_INDR11_Msk                (0x800UL)                 /*!< Pn INDR: INDR11 (Bitfield-Mask: 0x01)                 */
+#define Pn_INDR_INDR10_Pos                (10UL)                    /*!< Pn INDR: INDR10 (Bit 10)                              */
+#define Pn_INDR_INDR10_Msk                (0x400UL)                 /*!< Pn INDR: INDR10 (Bitfield-Mask: 0x01)                 */
+#define Pn_INDR_INDR9_Pos                 (9UL)                     /*!< Pn INDR: INDR9 (Bit 9)                                */
+#define Pn_INDR_INDR9_Msk                 (0x200UL)                 /*!< Pn INDR: INDR9 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR8_Pos                 (8UL)                     /*!< Pn INDR: INDR8 (Bit 8)                                */
+#define Pn_INDR_INDR8_Msk                 (0x100UL)                 /*!< Pn INDR: INDR8 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR7_Pos                 (7UL)                     /*!< Pn INDR: INDR7 (Bit 7)                                */
+#define Pn_INDR_INDR7_Msk                 (0x80UL)                  /*!< Pn INDR: INDR7 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR6_Pos                 (6UL)                     /*!< Pn INDR: INDR6 (Bit 6)                                */
+#define Pn_INDR_INDR6_Msk                 (0x40UL)                  /*!< Pn INDR: INDR6 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR5_Pos                 (5UL)                     /*!< Pn INDR: INDR5 (Bit 5)                                */
+#define Pn_INDR_INDR5_Msk                 (0x20UL)                  /*!< Pn INDR: INDR5 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR4_Pos                 (4UL)                     /*!< Pn INDR: INDR4 (Bit 4)                                */
+#define Pn_INDR_INDR4_Msk                 (0x10UL)                  /*!< Pn INDR: INDR4 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR3_Pos                 (3UL)                     /*!< Pn INDR: INDR3 (Bit 3)                                */
+#define Pn_INDR_INDR3_Msk                 (0x8UL)                   /*!< Pn INDR: INDR3 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR2_Pos                 (2UL)                     /*!< Pn INDR: INDR2 (Bit 2)                                */
+#define Pn_INDR_INDR2_Msk                 (0x4UL)                   /*!< Pn INDR: INDR2 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR1_Pos                 (1UL)                     /*!< Pn INDR: INDR1 (Bit 1)                                */
+#define Pn_INDR_INDR1_Msk                 (0x2UL)                   /*!< Pn INDR: INDR1 (Bitfield-Mask: 0x01)                  */
+#define Pn_INDR_INDR0_Pos                 (0UL)                     /*!< Pn INDR: INDR0 (Bit 0)                                */
+#define Pn_INDR_INDR0_Msk                 (0x1UL)                   /*!< Pn INDR: INDR0 (Bitfield-Mask: 0x01)                  */
+/* =========================================================  OUTDR  ========================================================= */
+#define Pn_OUTDR_OUTDR15_Pos              (15UL)                    /*!< Pn OUTDR: OUTDR15 (Bit 15)                            */
+#define Pn_OUTDR_OUTDR15_Msk              (0x8000UL)                /*!< Pn OUTDR: OUTDR15 (Bitfield-Mask: 0x01)               */
+#define Pn_OUTDR_OUTDR14_Pos              (14UL)                    /*!< Pn OUTDR: OUTDR14 (Bit 14)                            */
+#define Pn_OUTDR_OUTDR14_Msk              (0x4000UL)                /*!< Pn OUTDR: OUTDR14 (Bitfield-Mask: 0x01)               */
+#define Pn_OUTDR_OUTDR13_Pos              (13UL)                    /*!< Pn OUTDR: OUTDR13 (Bit 13)                            */
+#define Pn_OUTDR_OUTDR13_Msk              (0x2000UL)                /*!< Pn OUTDR: OUTDR13 (Bitfield-Mask: 0x01)               */
+#define Pn_OUTDR_OUTDR12_Pos              (12UL)                    /*!< Pn OUTDR: OUTDR12 (Bit 12)                            */
+#define Pn_OUTDR_OUTDR12_Msk              (0x1000UL)                /*!< Pn OUTDR: OUTDR12 (Bitfield-Mask: 0x01)               */
+#define Pn_OUTDR_OUTDR11_Pos              (11UL)                    /*!< Pn OUTDR: OUTDR11 (Bit 11)                            */
+#define Pn_OUTDR_OUTDR11_Msk              (0x800UL)                 /*!< Pn OUTDR: OUTDR11 (Bitfield-Mask: 0x01)               */
+#define Pn_OUTDR_OUTDR10_Pos              (10UL)                    /*!< Pn OUTDR: OUTDR10 (Bit 10)                            */
+#define Pn_OUTDR_OUTDR10_Msk              (0x400UL)                 /*!< Pn OUTDR: OUTDR10 (Bitfield-Mask: 0x01)               */
+#define Pn_OUTDR_OUTDR9_Pos               (9UL)                     /*!< Pn OUTDR: OUTDR9 (Bit 9)                              */
+#define Pn_OUTDR_OUTDR9_Msk               (0x200UL)                 /*!< Pn OUTDR: OUTDR9 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR8_Pos               (8UL)                     /*!< Pn OUTDR: OUTDR8 (Bit 8)                              */
+#define Pn_OUTDR_OUTDR8_Msk               (0x100UL)                 /*!< Pn OUTDR: OUTDR8 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR7_Pos               (7UL)                     /*!< Pn OUTDR: OUTDR7 (Bit 7)                              */
+#define Pn_OUTDR_OUTDR7_Msk               (0x80UL)                  /*!< Pn OUTDR: OUTDR7 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR6_Pos               (6UL)                     /*!< Pn OUTDR: OUTDR6 (Bit 6)                              */
+#define Pn_OUTDR_OUTDR6_Msk               (0x40UL)                  /*!< Pn OUTDR: OUTDR6 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR5_Pos               (5UL)                     /*!< Pn OUTDR: OUTDR5 (Bit 5)                              */
+#define Pn_OUTDR_OUTDR5_Msk               (0x20UL)                  /*!< Pn OUTDR: OUTDR5 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR4_Pos               (4UL)                     /*!< Pn OUTDR: OUTDR4 (Bit 4)                              */
+#define Pn_OUTDR_OUTDR4_Msk               (0x10UL)                  /*!< Pn OUTDR: OUTDR4 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR3_Pos               (3UL)                     /*!< Pn OUTDR: OUTDR3 (Bit 3)                              */
+#define Pn_OUTDR_OUTDR3_Msk               (0x8UL)                   /*!< Pn OUTDR: OUTDR3 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR2_Pos               (2UL)                     /*!< Pn OUTDR: OUTDR2 (Bit 2)                              */
+#define Pn_OUTDR_OUTDR2_Msk               (0x4UL)                   /*!< Pn OUTDR: OUTDR2 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR1_Pos               (1UL)                     /*!< Pn OUTDR: OUTDR1 (Bit 1)                              */
+#define Pn_OUTDR_OUTDR1_Msk               (0x2UL)                   /*!< Pn OUTDR: OUTDR1 (Bitfield-Mask: 0x01)                */
+#define Pn_OUTDR_OUTDR0_Pos               (0UL)                     /*!< Pn OUTDR: OUTDR0 (Bit 0)                              */
+#define Pn_OUTDR_OUTDR0_Msk               (0x1UL)                   /*!< Pn OUTDR: OUTDR0 (Bitfield-Mask: 0x01)                */
+/* ==========================================================  BSR  ========================================================== */
+#define Pn_BSR_BSR15_Pos                  (15UL)                    /*!< Pn BSR: BSR15 (Bit 15)                                */
+#define Pn_BSR_BSR15_Msk                  (0x8000UL)                /*!< Pn BSR: BSR15 (Bitfield-Mask: 0x01)                   */
+#define Pn_BSR_BSR14_Pos                  (14UL)                    /*!< Pn BSR: BSR14 (Bit 14)                                */
+#define Pn_BSR_BSR14_Msk                  (0x4000UL)                /*!< Pn BSR: BSR14 (Bitfield-Mask: 0x01)                   */
+#define Pn_BSR_BSR13_Pos                  (13UL)                    /*!< Pn BSR: BSR13 (Bit 13)                                */
+#define Pn_BSR_BSR13_Msk                  (0x2000UL)                /*!< Pn BSR: BSR13 (Bitfield-Mask: 0x01)                   */
+#define Pn_BSR_BSR12_Pos                  (12UL)                    /*!< Pn BSR: BSR12 (Bit 12)                                */
+#define Pn_BSR_BSR12_Msk                  (0x1000UL)                /*!< Pn BSR: BSR12 (Bitfield-Mask: 0x01)                   */
+#define Pn_BSR_BSR11_Pos                  (11UL)                    /*!< Pn BSR: BSR11 (Bit 11)                                */
+#define Pn_BSR_BSR11_Msk                  (0x800UL)                 /*!< Pn BSR: BSR11 (Bitfield-Mask: 0x01)                   */
+#define Pn_BSR_BSR10_Pos                  (10UL)                    /*!< Pn BSR: BSR10 (Bit 10)                                */
+#define Pn_BSR_BSR10_Msk                  (0x400UL)                 /*!< Pn BSR: BSR10 (Bitfield-Mask: 0x01)                   */
+#define Pn_BSR_BSR9_Pos                   (9UL)                     /*!< Pn BSR: BSR9 (Bit 9)                                  */
+#define Pn_BSR_BSR9_Msk                   (0x200UL)                 /*!< Pn BSR: BSR9 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR8_Pos                   (8UL)                     /*!< Pn BSR: BSR8 (Bit 8)                                  */
+#define Pn_BSR_BSR8_Msk                   (0x100UL)                 /*!< Pn BSR: BSR8 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR7_Pos                   (7UL)                     /*!< Pn BSR: BSR7 (Bit 7)                                  */
+#define Pn_BSR_BSR7_Msk                   (0x80UL)                  /*!< Pn BSR: BSR7 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR6_Pos                   (6UL)                     /*!< Pn BSR: BSR6 (Bit 6)                                  */
+#define Pn_BSR_BSR6_Msk                   (0x40UL)                  /*!< Pn BSR: BSR6 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR5_Pos                   (5UL)                     /*!< Pn BSR: BSR5 (Bit 5)                                  */
+#define Pn_BSR_BSR5_Msk                   (0x20UL)                  /*!< Pn BSR: BSR5 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR4_Pos                   (4UL)                     /*!< Pn BSR: BSR4 (Bit 4)                                  */
+#define Pn_BSR_BSR4_Msk                   (0x10UL)                  /*!< Pn BSR: BSR4 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR3_Pos                   (3UL)                     /*!< Pn BSR: BSR3 (Bit 3)                                  */
+#define Pn_BSR_BSR3_Msk                   (0x8UL)                   /*!< Pn BSR: BSR3 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR2_Pos                   (2UL)                     /*!< Pn BSR: BSR2 (Bit 2)                                  */
+#define Pn_BSR_BSR2_Msk                   (0x4UL)                   /*!< Pn BSR: BSR2 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR1_Pos                   (1UL)                     /*!< Pn BSR: BSR1 (Bit 1)                                  */
+#define Pn_BSR_BSR1_Msk                   (0x2UL)                   /*!< Pn BSR: BSR1 (Bitfield-Mask: 0x01)                    */
+#define Pn_BSR_BSR0_Pos                   (0UL)                     /*!< Pn BSR: BSR0 (Bit 0)                                  */
+#define Pn_BSR_BSR0_Msk                   (0x1UL)                   /*!< Pn BSR: BSR0 (Bitfield-Mask: 0x01)                    */
+/* ==========================================================  BCR  ========================================================== */
+#define Pn_BCR_BCR15_Pos                  (15UL)                    /*!< Pn BCR: BCR15 (Bit 15)                                */
+#define Pn_BCR_BCR15_Msk                  (0x8000UL)                /*!< Pn BCR: BCR15 (Bitfield-Mask: 0x01)                   */
+#define Pn_BCR_BCR14_Pos                  (14UL)                    /*!< Pn BCR: BCR14 (Bit 14)                                */
+#define Pn_BCR_BCR14_Msk                  (0x4000UL)                /*!< Pn BCR: BCR14 (Bitfield-Mask: 0x01)                   */
+#define Pn_BCR_BCR13_Pos                  (13UL)                    /*!< Pn BCR: BCR13 (Bit 13)                                */
+#define Pn_BCR_BCR13_Msk                  (0x2000UL)                /*!< Pn BCR: BCR13 (Bitfield-Mask: 0x01)                   */
+#define Pn_BCR_BCR12_Pos                  (12UL)                    /*!< Pn BCR: BCR12 (Bit 12)                                */
+#define Pn_BCR_BCR12_Msk                  (0x1000UL)                /*!< Pn BCR: BCR12 (Bitfield-Mask: 0x01)                   */
+#define Pn_BCR_BCR11_Pos                  (11UL)                    /*!< Pn BCR: BCR11 (Bit 11)                                */
+#define Pn_BCR_BCR11_Msk                  (0x800UL)                 /*!< Pn BCR: BCR11 (Bitfield-Mask: 0x01)                   */
+#define Pn_BCR_BCR10_Pos                  (10UL)                    /*!< Pn BCR: BCR10 (Bit 10)                                */
+#define Pn_BCR_BCR10_Msk                  (0x400UL)                 /*!< Pn BCR: BCR10 (Bitfield-Mask: 0x01)                   */
+#define Pn_BCR_BCR9_Pos                   (9UL)                     /*!< Pn BCR: BCR9 (Bit 9)                                  */
+#define Pn_BCR_BCR9_Msk                   (0x200UL)                 /*!< Pn BCR: BCR9 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR8_Pos                   (8UL)                     /*!< Pn BCR: BCR8 (Bit 8)                                  */
+#define Pn_BCR_BCR8_Msk                   (0x100UL)                 /*!< Pn BCR: BCR8 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR7_Pos                   (7UL)                     /*!< Pn BCR: BCR7 (Bit 7)                                  */
+#define Pn_BCR_BCR7_Msk                   (0x80UL)                  /*!< Pn BCR: BCR7 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR6_Pos                   (6UL)                     /*!< Pn BCR: BCR6 (Bit 6)                                  */
+#define Pn_BCR_BCR6_Msk                   (0x40UL)                  /*!< Pn BCR: BCR6 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR5_Pos                   (5UL)                     /*!< Pn BCR: BCR5 (Bit 5)                                  */
+#define Pn_BCR_BCR5_Msk                   (0x20UL)                  /*!< Pn BCR: BCR5 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR4_Pos                   (4UL)                     /*!< Pn BCR: BCR4 (Bit 4)                                  */
+#define Pn_BCR_BCR4_Msk                   (0x10UL)                  /*!< Pn BCR: BCR4 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR3_Pos                   (3UL)                     /*!< Pn BCR: BCR3 (Bit 3)                                  */
+#define Pn_BCR_BCR3_Msk                   (0x8UL)                   /*!< Pn BCR: BCR3 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR2_Pos                   (2UL)                     /*!< Pn BCR: BCR2 (Bit 2)                                  */
+#define Pn_BCR_BCR2_Msk                   (0x4UL)                   /*!< Pn BCR: BCR2 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR1_Pos                   (1UL)                     /*!< Pn BCR: BCR1 (Bit 1)                                  */
+#define Pn_BCR_BCR1_Msk                   (0x2UL)                   /*!< Pn BCR: BCR1 (Bitfield-Mask: 0x01)                    */
+#define Pn_BCR_BCR0_Pos                   (0UL)                     /*!< Pn BCR: BCR0 (Bit 0)                                  */
+#define Pn_BCR_BCR0_Msk                   (0x1UL)                   /*!< Pn BCR: BCR0 (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OUTDMSK  ======================================================== */
+#define Pn_OUTDMSK_OUTDMSK15_Pos          (15UL)                    /*!< Pn OUTDMSK: OUTDMSK15 (Bit 15)                        */
+#define Pn_OUTDMSK_OUTDMSK15_Msk          (0x8000UL)                /*!< Pn OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)           */
+#define Pn_OUTDMSK_OUTDMSK14_Pos          (14UL)                    /*!< Pn OUTDMSK: OUTDMSK14 (Bit 14)                        */
+#define Pn_OUTDMSK_OUTDMSK14_Msk          (0x4000UL)                /*!< Pn OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)           */
+#define Pn_OUTDMSK_OUTDMSK13_Pos          (13UL)                    /*!< Pn OUTDMSK: OUTDMSK13 (Bit 13)                        */
+#define Pn_OUTDMSK_OUTDMSK13_Msk          (0x2000UL)                /*!< Pn OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)           */
+#define Pn_OUTDMSK_OUTDMSK12_Pos          (12UL)                    /*!< Pn OUTDMSK: OUTDMSK12 (Bit 12)                        */
+#define Pn_OUTDMSK_OUTDMSK12_Msk          (0x1000UL)                /*!< Pn OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)           */
+#define Pn_OUTDMSK_OUTDMSK11_Pos          (11UL)                    /*!< Pn OUTDMSK: OUTDMSK11 (Bit 11)                        */
+#define Pn_OUTDMSK_OUTDMSK11_Msk          (0x800UL)                 /*!< Pn OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)           */
+#define Pn_OUTDMSK_OUTDMSK10_Pos          (10UL)                    /*!< Pn OUTDMSK: OUTDMSK10 (Bit 10)                        */
+#define Pn_OUTDMSK_OUTDMSK10_Msk          (0x400UL)                 /*!< Pn OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)           */
+#define Pn_OUTDMSK_OUTDMSK9_Pos           (9UL)                     /*!< Pn OUTDMSK: OUTDMSK9 (Bit 9)                          */
+#define Pn_OUTDMSK_OUTDMSK9_Msk           (0x200UL)                 /*!< Pn OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK8_Pos           (8UL)                     /*!< Pn OUTDMSK: OUTDMSK8 (Bit 8)                          */
+#define Pn_OUTDMSK_OUTDMSK8_Msk           (0x100UL)                 /*!< Pn OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK7_Pos           (7UL)                     /*!< Pn OUTDMSK: OUTDMSK7 (Bit 7)                          */
+#define Pn_OUTDMSK_OUTDMSK7_Msk           (0x80UL)                  /*!< Pn OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK6_Pos           (6UL)                     /*!< Pn OUTDMSK: OUTDMSK6 (Bit 6)                          */
+#define Pn_OUTDMSK_OUTDMSK6_Msk           (0x40UL)                  /*!< Pn OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK5_Pos           (5UL)                     /*!< Pn OUTDMSK: OUTDMSK5 (Bit 5)                          */
+#define Pn_OUTDMSK_OUTDMSK5_Msk           (0x20UL)                  /*!< Pn OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK4_Pos           (4UL)                     /*!< Pn OUTDMSK: OUTDMSK4 (Bit 4)                          */
+#define Pn_OUTDMSK_OUTDMSK4_Msk           (0x10UL)                  /*!< Pn OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK3_Pos           (3UL)                     /*!< Pn OUTDMSK: OUTDMSK3 (Bit 3)                          */
+#define Pn_OUTDMSK_OUTDMSK3_Msk           (0x8UL)                   /*!< Pn OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK2_Pos           (2UL)                     /*!< Pn OUTDMSK: OUTDMSK2 (Bit 2)                          */
+#define Pn_OUTDMSK_OUTDMSK2_Msk           (0x4UL)                   /*!< Pn OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK1_Pos           (1UL)                     /*!< Pn OUTDMSK: OUTDMSK1 (Bit 1)                          */
+#define Pn_OUTDMSK_OUTDMSK1_Msk           (0x2UL)                   /*!< Pn OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)            */
+#define Pn_OUTDMSK_OUTDMSK0_Pos           (0UL)                     /*!< Pn OUTDMSK: OUTDMSK0 (Bit 0)                          */
+#define Pn_OUTDMSK_OUTDMSK0_Msk           (0x1UL)                   /*!< Pn OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)            */
+/* =========================================================  DBCR  ========================================================== */
+#define Pn_DBCR_DBCLK_Pos                 (16UL)                    /*!< Pn DBCR: DBCLK (Bit 16)                               */
+#define Pn_DBCR_DBCLK_Msk                 (0x70000UL)               /*!< Pn DBCR: DBCLK (Bitfield-Mask: 0x07)                  */
+#define Pn_DBCR_DBEN11_Pos                (11UL)                    /*!< Pn DBCR: DBEN11 (Bit 11)                              */
+#define Pn_DBCR_DBEN11_Msk                (0x800UL)                 /*!< Pn DBCR: DBEN11 (Bitfield-Mask: 0x01)                 */
+#define Pn_DBCR_DBEN10_Pos                (10UL)                    /*!< Pn DBCR: DBEN10 (Bit 10)                              */
+#define Pn_DBCR_DBEN10_Msk                (0x400UL)                 /*!< Pn DBCR: DBEN10 (Bitfield-Mask: 0x01)                 */
+#define Pn_DBCR_DBEN9_Pos                 (9UL)                     /*!< Pn DBCR: DBEN9 (Bit 9)                                */
+#define Pn_DBCR_DBEN9_Msk                 (0x200UL)                 /*!< Pn DBCR: DBEN9 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN8_Pos                 (8UL)                     /*!< Pn DBCR: DBEN8 (Bit 8)                                */
+#define Pn_DBCR_DBEN8_Msk                 (0x100UL)                 /*!< Pn DBCR: DBEN8 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN7_Pos                 (7UL)                     /*!< Pn DBCR: DBEN7 (Bit 7)                                */
+#define Pn_DBCR_DBEN7_Msk                 (0x80UL)                  /*!< Pn DBCR: DBEN7 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN6_Pos                 (6UL)                     /*!< Pn DBCR: DBEN6 (Bit 6)                                */
+#define Pn_DBCR_DBEN6_Msk                 (0x40UL)                  /*!< Pn DBCR: DBEN6 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN5_Pos                 (5UL)                     /*!< Pn DBCR: DBEN5 (Bit 5)                                */
+#define Pn_DBCR_DBEN5_Msk                 (0x20UL)                  /*!< Pn DBCR: DBEN5 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN4_Pos                 (4UL)                     /*!< Pn DBCR: DBEN4 (Bit 4)                                */
+#define Pn_DBCR_DBEN4_Msk                 (0x10UL)                  /*!< Pn DBCR: DBEN4 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN3_Pos                 (3UL)                     /*!< Pn DBCR: DBEN3 (Bit 3)                                */
+#define Pn_DBCR_DBEN3_Msk                 (0x8UL)                   /*!< Pn DBCR: DBEN3 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN2_Pos                 (2UL)                     /*!< Pn DBCR: DBEN2 (Bit 2)                                */
+#define Pn_DBCR_DBEN2_Msk                 (0x4UL)                   /*!< Pn DBCR: DBEN2 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN1_Pos                 (1UL)                     /*!< Pn DBCR: DBEN1 (Bit 1)                                */
+#define Pn_DBCR_DBEN1_Msk                 (0x2UL)                   /*!< Pn DBCR: DBEN1 (Bitfield-Mask: 0x01)                  */
+#define Pn_DBCR_DBEN0_Pos                 (0UL)                     /*!< Pn DBCR: DBEN0 (Bit 0)                                */
+#define Pn_DBCR_DBEN0_Msk                 (0x1UL)                   /*!< Pn DBCR: DBEN0 (Bitfield-Mask: 0x01)                  */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PA                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+#define PA_MOD_MODE15_Pos                 (30UL)                    /*!< PA MOD: MODE15 (Bit 30)                               */
+#define PA_MOD_MODE15_Msk                 (0xc0000000UL)            /*!< PA MOD: MODE15 (Bitfield-Mask: 0x03)                  */
+#define PA_MOD_MODE14_Pos                 (28UL)                    /*!< PA MOD: MODE14 (Bit 28)                               */
+#define PA_MOD_MODE14_Msk                 (0x30000000UL)            /*!< PA MOD: MODE14 (Bitfield-Mask: 0x03)                  */
+#define PA_MOD_MODE13_Pos                 (26UL)                    /*!< PA MOD: MODE13 (Bit 26)                               */
+#define PA_MOD_MODE13_Msk                 (0xc000000UL)             /*!< PA MOD: MODE13 (Bitfield-Mask: 0x03)                  */
+#define PA_MOD_MODE12_Pos                 (24UL)                    /*!< PA MOD: MODE12 (Bit 24)                               */
+#define PA_MOD_MODE12_Msk                 (0x3000000UL)             /*!< PA MOD: MODE12 (Bitfield-Mask: 0x03)                  */
+#define PA_MOD_MODE11_Pos                 (22UL)                    /*!< PA MOD: MODE11 (Bit 22)                               */
+#define PA_MOD_MODE11_Msk                 (0xc00000UL)              /*!< PA MOD: MODE11 (Bitfield-Mask: 0x03)                  */
+#define PA_MOD_MODE10_Pos                 (20UL)                    /*!< PA MOD: MODE10 (Bit 20)                               */
+#define PA_MOD_MODE10_Msk                 (0x300000UL)              /*!< PA MOD: MODE10 (Bitfield-Mask: 0x03)                  */
+#define PA_MOD_MODE9_Pos                  (18UL)                    /*!< PA MOD: MODE9 (Bit 18)                                */
+#define PA_MOD_MODE9_Msk                  (0xc0000UL)               /*!< PA MOD: MODE9 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE8_Pos                  (16UL)                    /*!< PA MOD: MODE8 (Bit 16)                                */
+#define PA_MOD_MODE8_Msk                  (0x30000UL)               /*!< PA MOD: MODE8 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE7_Pos                  (14UL)                    /*!< PA MOD: MODE7 (Bit 14)                                */
+#define PA_MOD_MODE7_Msk                  (0xc000UL)                /*!< PA MOD: MODE7 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE6_Pos                  (12UL)                    /*!< PA MOD: MODE6 (Bit 12)                                */
+#define PA_MOD_MODE6_Msk                  (0x3000UL)                /*!< PA MOD: MODE6 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE5_Pos                  (10UL)                    /*!< PA MOD: MODE5 (Bit 10)                                */
+#define PA_MOD_MODE5_Msk                  (0xc00UL)                 /*!< PA MOD: MODE5 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE4_Pos                  (8UL)                     /*!< PA MOD: MODE4 (Bit 8)                                 */
+#define PA_MOD_MODE4_Msk                  (0x300UL)                 /*!< PA MOD: MODE4 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE3_Pos                  (6UL)                     /*!< PA MOD: MODE3 (Bit 6)                                 */
+#define PA_MOD_MODE3_Msk                  (0xc0UL)                  /*!< PA MOD: MODE3 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE2_Pos                  (4UL)                     /*!< PA MOD: MODE2 (Bit 4)                                 */
+#define PA_MOD_MODE2_Msk                  (0x30UL)                  /*!< PA MOD: MODE2 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE1_Pos                  (2UL)                     /*!< PA MOD: MODE1 (Bit 2)                                 */
+#define PA_MOD_MODE1_Msk                  (0xcUL)                   /*!< PA MOD: MODE1 (Bitfield-Mask: 0x03)                   */
+#define PA_MOD_MODE0_Pos                  (0UL)                     /*!< PA MOD: MODE0 (Bit 0)                                 */
+#define PA_MOD_MODE0_Msk                  (0x3UL)                   /*!< PA MOD: MODE0 (Bitfield-Mask: 0x03)                   */
+/* ==========================================================  TYP  ========================================================== */
+#define PA_TYP_TYP15_Pos                  (15UL)                    /*!< PA TYP: TYP15 (Bit 15)                                */
+#define PA_TYP_TYP15_Msk                  (0x8000UL)                /*!< PA TYP: TYP15 (Bitfield-Mask: 0x01)                   */
+#define PA_TYP_TYP14_Pos                  (14UL)                    /*!< PA TYP: TYP14 (Bit 14)                                */
+#define PA_TYP_TYP14_Msk                  (0x4000UL)                /*!< PA TYP: TYP14 (Bitfield-Mask: 0x01)                   */
+#define PA_TYP_TYP13_Pos                  (13UL)                    /*!< PA TYP: TYP13 (Bit 13)                                */
+#define PA_TYP_TYP13_Msk                  (0x2000UL)                /*!< PA TYP: TYP13 (Bitfield-Mask: 0x01)                   */
+#define PA_TYP_TYP12_Pos                  (12UL)                    /*!< PA TYP: TYP12 (Bit 12)                                */
+#define PA_TYP_TYP12_Msk                  (0x1000UL)                /*!< PA TYP: TYP12 (Bitfield-Mask: 0x01)                   */
+#define PA_TYP_TYP11_Pos                  (11UL)                    /*!< PA TYP: TYP11 (Bit 11)                                */
+#define PA_TYP_TYP11_Msk                  (0x800UL)                 /*!< PA TYP: TYP11 (Bitfield-Mask: 0x01)                   */
+#define PA_TYP_TYP10_Pos                  (10UL)                    /*!< PA TYP: TYP10 (Bit 10)                                */
+#define PA_TYP_TYP10_Msk                  (0x400UL)                 /*!< PA TYP: TYP10 (Bitfield-Mask: 0x01)                   */
+#define PA_TYP_TYP9_Pos                   (9UL)                     /*!< PA TYP: TYP9 (Bit 9)                                  */
+#define PA_TYP_TYP9_Msk                   (0x200UL)                 /*!< PA TYP: TYP9 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP8_Pos                   (8UL)                     /*!< PA TYP: TYP8 (Bit 8)                                  */
+#define PA_TYP_TYP8_Msk                   (0x100UL)                 /*!< PA TYP: TYP8 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP7_Pos                   (7UL)                     /*!< PA TYP: TYP7 (Bit 7)                                  */
+#define PA_TYP_TYP7_Msk                   (0x80UL)                  /*!< PA TYP: TYP7 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP6_Pos                   (6UL)                     /*!< PA TYP: TYP6 (Bit 6)                                  */
+#define PA_TYP_TYP6_Msk                   (0x40UL)                  /*!< PA TYP: TYP6 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP5_Pos                   (5UL)                     /*!< PA TYP: TYP5 (Bit 5)                                  */
+#define PA_TYP_TYP5_Msk                   (0x20UL)                  /*!< PA TYP: TYP5 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP4_Pos                   (4UL)                     /*!< PA TYP: TYP4 (Bit 4)                                  */
+#define PA_TYP_TYP4_Msk                   (0x10UL)                  /*!< PA TYP: TYP4 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP3_Pos                   (3UL)                     /*!< PA TYP: TYP3 (Bit 3)                                  */
+#define PA_TYP_TYP3_Msk                   (0x8UL)                   /*!< PA TYP: TYP3 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP2_Pos                   (2UL)                     /*!< PA TYP: TYP2 (Bit 2)                                  */
+#define PA_TYP_TYP2_Msk                   (0x4UL)                   /*!< PA TYP: TYP2 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP1_Pos                   (1UL)                     /*!< PA TYP: TYP1 (Bit 1)                                  */
+#define PA_TYP_TYP1_Msk                   (0x2UL)                   /*!< PA TYP: TYP1 (Bitfield-Mask: 0x01)                    */
+#define PA_TYP_TYP0_Pos                   (0UL)                     /*!< PA TYP: TYP0 (Bit 0)                                  */
+#define PA_TYP_TYP0_Msk                   (0x1UL)                   /*!< PA TYP: TYP0 (Bitfield-Mask: 0x01)                    */
+/* =========================================================  AFSR1  ========================================================= */
+#define PA_AFSR1_AFSR7_Pos                (28UL)                    /*!< PA AFSR1: AFSR7 (Bit 28)                              */
+#define PA_AFSR1_AFSR7_Msk                (0xf0000000UL)            /*!< PA AFSR1: AFSR7 (Bitfield-Mask: 0x0f)                 */
+#define PA_AFSR1_AFSR6_Pos                (24UL)                    /*!< PA AFSR1: AFSR6 (Bit 24)                              */
+#define PA_AFSR1_AFSR6_Msk                (0xf000000UL)             /*!< PA AFSR1: AFSR6 (Bitfield-Mask: 0x0f)                 */
+#define PA_AFSR1_AFSR5_Pos                (20UL)                    /*!< PA AFSR1: AFSR5 (Bit 20)                              */
+#define PA_AFSR1_AFSR5_Msk                (0xf00000UL)              /*!< PA AFSR1: AFSR5 (Bitfield-Mask: 0x0f)                 */
+#define PA_AFSR1_AFSR4_Pos                (16UL)                    /*!< PA AFSR1: AFSR4 (Bit 16)                              */
+#define PA_AFSR1_AFSR4_Msk                (0xf0000UL)               /*!< PA AFSR1: AFSR4 (Bitfield-Mask: 0x0f)                 */
+#define PA_AFSR1_AFSR3_Pos                (12UL)                    /*!< PA AFSR1: AFSR3 (Bit 12)                              */
+#define PA_AFSR1_AFSR3_Msk                (0xf000UL)                /*!< PA AFSR1: AFSR3 (Bitfield-Mask: 0x0f)                 */
+#define PA_AFSR1_AFSR2_Pos                (8UL)                     /*!< PA AFSR1: AFSR2 (Bit 8)                               */
+#define PA_AFSR1_AFSR2_Msk                (0xf00UL)                 /*!< PA AFSR1: AFSR2 (Bitfield-Mask: 0x0f)                 */
+#define PA_AFSR1_AFSR1_Pos                (4UL)                     /*!< PA AFSR1: AFSR1 (Bit 4)                               */
+#define PA_AFSR1_AFSR1_Msk                (0xf0UL)                  /*!< PA AFSR1: AFSR1 (Bitfield-Mask: 0x0f)                 */
+#define PA_AFSR1_AFSR0_Pos                (0UL)                     /*!< PA AFSR1: AFSR0 (Bit 0)                               */
+#define PA_AFSR1_AFSR0_Msk                (0xfUL)                   /*!< PA AFSR1: AFSR0 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  AFSR2  ========================================================= */
+#define PA_AFSR2_AFSR15_Pos               (28UL)                    /*!< PA AFSR2: AFSR15 (Bit 28)                             */
+#define PA_AFSR2_AFSR15_Msk               (0xf0000000UL)            /*!< PA AFSR2: AFSR15 (Bitfield-Mask: 0x0f)                */
+#define PA_AFSR2_AFSR14_Pos               (24UL)                    /*!< PA AFSR2: AFSR14 (Bit 24)                             */
+#define PA_AFSR2_AFSR14_Msk               (0xf000000UL)             /*!< PA AFSR2: AFSR14 (Bitfield-Mask: 0x0f)                */
+#define PA_AFSR2_AFSR13_Pos               (20UL)                    /*!< PA AFSR2: AFSR13 (Bit 20)                             */
+#define PA_AFSR2_AFSR13_Msk               (0xf00000UL)              /*!< PA AFSR2: AFSR13 (Bitfield-Mask: 0x0f)                */
+#define PA_AFSR2_AFSR12_Pos               (16UL)                    /*!< PA AFSR2: AFSR12 (Bit 16)                             */
+#define PA_AFSR2_AFSR12_Msk               (0xf0000UL)               /*!< PA AFSR2: AFSR12 (Bitfield-Mask: 0x0f)                */
+#define PA_AFSR2_AFSR11_Pos               (12UL)                    /*!< PA AFSR2: AFSR11 (Bit 12)                             */
+#define PA_AFSR2_AFSR11_Msk               (0xf000UL)                /*!< PA AFSR2: AFSR11 (Bitfield-Mask: 0x0f)                */
+#define PA_AFSR2_AFSR10_Pos               (8UL)                     /*!< PA AFSR2: AFSR10 (Bit 8)                              */
+#define PA_AFSR2_AFSR10_Msk               (0xf00UL)                 /*!< PA AFSR2: AFSR10 (Bitfield-Mask: 0x0f)                */
+#define PA_AFSR2_AFSR9_Pos                (4UL)                     /*!< PA AFSR2: AFSR9 (Bit 4)                               */
+#define PA_AFSR2_AFSR9_Msk                (0xf0UL)                  /*!< PA AFSR2: AFSR9 (Bitfield-Mask: 0x0f)                 */
+#define PA_AFSR2_AFSR8_Pos                (0UL)                     /*!< PA AFSR2: AFSR8 (Bit 0)                               */
+#define PA_AFSR2_AFSR8_Msk                (0xfUL)                   /*!< PA AFSR2: AFSR8 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  PUPD  ========================================================== */
+#define PA_PUPD_PUPD15_Pos                (30UL)                    /*!< PA PUPD: PUPD15 (Bit 30)                              */
+#define PA_PUPD_PUPD15_Msk                (0xc0000000UL)            /*!< PA PUPD: PUPD15 (Bitfield-Mask: 0x03)                 */
+#define PA_PUPD_PUPD14_Pos                (28UL)                    /*!< PA PUPD: PUPD14 (Bit 28)                              */
+#define PA_PUPD_PUPD14_Msk                (0x30000000UL)            /*!< PA PUPD: PUPD14 (Bitfield-Mask: 0x03)                 */
+#define PA_PUPD_PUPD13_Pos                (26UL)                    /*!< PA PUPD: PUPD13 (Bit 26)                              */
+#define PA_PUPD_PUPD13_Msk                (0xc000000UL)             /*!< PA PUPD: PUPD13 (Bitfield-Mask: 0x03)                 */
+#define PA_PUPD_PUPD12_Pos                (24UL)                    /*!< PA PUPD: PUPD12 (Bit 24)                              */
+#define PA_PUPD_PUPD12_Msk                (0x3000000UL)             /*!< PA PUPD: PUPD12 (Bitfield-Mask: 0x03)                 */
+#define PA_PUPD_PUPD11_Pos                (22UL)                    /*!< PA PUPD: PUPD11 (Bit 22)                              */
+#define PA_PUPD_PUPD11_Msk                (0xc00000UL)              /*!< PA PUPD: PUPD11 (Bitfield-Mask: 0x03)                 */
+#define PA_PUPD_PUPD10_Pos                (20UL)                    /*!< PA PUPD: PUPD10 (Bit 20)                              */
+#define PA_PUPD_PUPD10_Msk                (0x300000UL)              /*!< PA PUPD: PUPD10 (Bitfield-Mask: 0x03)                 */
+#define PA_PUPD_PUPD9_Pos                 (18UL)                    /*!< PA PUPD: PUPD9 (Bit 18)                               */
+#define PA_PUPD_PUPD9_Msk                 (0xc0000UL)               /*!< PA PUPD: PUPD9 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD8_Pos                 (16UL)                    /*!< PA PUPD: PUPD8 (Bit 16)                               */
+#define PA_PUPD_PUPD8_Msk                 (0x30000UL)               /*!< PA PUPD: PUPD8 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD7_Pos                 (14UL)                    /*!< PA PUPD: PUPD7 (Bit 14)                               */
+#define PA_PUPD_PUPD7_Msk                 (0xc000UL)                /*!< PA PUPD: PUPD7 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD6_Pos                 (12UL)                    /*!< PA PUPD: PUPD6 (Bit 12)                               */
+#define PA_PUPD_PUPD6_Msk                 (0x3000UL)                /*!< PA PUPD: PUPD6 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD5_Pos                 (10UL)                    /*!< PA PUPD: PUPD5 (Bit 10)                               */
+#define PA_PUPD_PUPD5_Msk                 (0xc00UL)                 /*!< PA PUPD: PUPD5 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD4_Pos                 (8UL)                     /*!< PA PUPD: PUPD4 (Bit 8)                                */
+#define PA_PUPD_PUPD4_Msk                 (0x300UL)                 /*!< PA PUPD: PUPD4 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD3_Pos                 (6UL)                     /*!< PA PUPD: PUPD3 (Bit 6)                                */
+#define PA_PUPD_PUPD3_Msk                 (0xc0UL)                  /*!< PA PUPD: PUPD3 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD2_Pos                 (4UL)                     /*!< PA PUPD: PUPD2 (Bit 4)                                */
+#define PA_PUPD_PUPD2_Msk                 (0x30UL)                  /*!< PA PUPD: PUPD2 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD1_Pos                 (2UL)                     /*!< PA PUPD: PUPD1 (Bit 2)                                */
+#define PA_PUPD_PUPD1_Msk                 (0xcUL)                   /*!< PA PUPD: PUPD1 (Bitfield-Mask: 0x03)                  */
+#define PA_PUPD_PUPD0_Pos                 (0UL)                     /*!< PA PUPD: PUPD0 (Bit 0)                                */
+#define PA_PUPD_PUPD0_Msk                 (0x3UL)                   /*!< PA PUPD: PUPD0 (Bitfield-Mask: 0x03)                  */
+/* =========================================================  INDR  ========================================================== */
+#define PA_INDR_INDR15_Pos                (15UL)                    /*!< PA INDR: INDR15 (Bit 15)                              */
+#define PA_INDR_INDR15_Msk                (0x8000UL)                /*!< PA INDR: INDR15 (Bitfield-Mask: 0x01)                 */
+#define PA_INDR_INDR14_Pos                (14UL)                    /*!< PA INDR: INDR14 (Bit 14)                              */
+#define PA_INDR_INDR14_Msk                (0x4000UL)                /*!< PA INDR: INDR14 (Bitfield-Mask: 0x01)                 */
+#define PA_INDR_INDR13_Pos                (13UL)                    /*!< PA INDR: INDR13 (Bit 13)                              */
+#define PA_INDR_INDR13_Msk                (0x2000UL)                /*!< PA INDR: INDR13 (Bitfield-Mask: 0x01)                 */
+#define PA_INDR_INDR12_Pos                (12UL)                    /*!< PA INDR: INDR12 (Bit 12)                              */
+#define PA_INDR_INDR12_Msk                (0x1000UL)                /*!< PA INDR: INDR12 (Bitfield-Mask: 0x01)                 */
+#define PA_INDR_INDR11_Pos                (11UL)                    /*!< PA INDR: INDR11 (Bit 11)                              */
+#define PA_INDR_INDR11_Msk                (0x800UL)                 /*!< PA INDR: INDR11 (Bitfield-Mask: 0x01)                 */
+#define PA_INDR_INDR10_Pos                (10UL)                    /*!< PA INDR: INDR10 (Bit 10)                              */
+#define PA_INDR_INDR10_Msk                (0x400UL)                 /*!< PA INDR: INDR10 (Bitfield-Mask: 0x01)                 */
+#define PA_INDR_INDR9_Pos                 (9UL)                     /*!< PA INDR: INDR9 (Bit 9)                                */
+#define PA_INDR_INDR9_Msk                 (0x200UL)                 /*!< PA INDR: INDR9 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR8_Pos                 (8UL)                     /*!< PA INDR: INDR8 (Bit 8)                                */
+#define PA_INDR_INDR8_Msk                 (0x100UL)                 /*!< PA INDR: INDR8 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR7_Pos                 (7UL)                     /*!< PA INDR: INDR7 (Bit 7)                                */
+#define PA_INDR_INDR7_Msk                 (0x80UL)                  /*!< PA INDR: INDR7 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR6_Pos                 (6UL)                     /*!< PA INDR: INDR6 (Bit 6)                                */
+#define PA_INDR_INDR6_Msk                 (0x40UL)                  /*!< PA INDR: INDR6 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR5_Pos                 (5UL)                     /*!< PA INDR: INDR5 (Bit 5)                                */
+#define PA_INDR_INDR5_Msk                 (0x20UL)                  /*!< PA INDR: INDR5 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR4_Pos                 (4UL)                     /*!< PA INDR: INDR4 (Bit 4)                                */
+#define PA_INDR_INDR4_Msk                 (0x10UL)                  /*!< PA INDR: INDR4 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR3_Pos                 (3UL)                     /*!< PA INDR: INDR3 (Bit 3)                                */
+#define PA_INDR_INDR3_Msk                 (0x8UL)                   /*!< PA INDR: INDR3 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR2_Pos                 (2UL)                     /*!< PA INDR: INDR2 (Bit 2)                                */
+#define PA_INDR_INDR2_Msk                 (0x4UL)                   /*!< PA INDR: INDR2 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR1_Pos                 (1UL)                     /*!< PA INDR: INDR1 (Bit 1)                                */
+#define PA_INDR_INDR1_Msk                 (0x2UL)                   /*!< PA INDR: INDR1 (Bitfield-Mask: 0x01)                  */
+#define PA_INDR_INDR0_Pos                 (0UL)                     /*!< PA INDR: INDR0 (Bit 0)                                */
+#define PA_INDR_INDR0_Msk                 (0x1UL)                   /*!< PA INDR: INDR0 (Bitfield-Mask: 0x01)                  */
+/* =========================================================  OUTDR  ========================================================= */
+#define PA_OUTDR_OUTDR15_Pos              (15UL)                    /*!< PA OUTDR: OUTDR15 (Bit 15)                            */
+#define PA_OUTDR_OUTDR15_Msk              (0x8000UL)                /*!< PA OUTDR: OUTDR15 (Bitfield-Mask: 0x01)               */
+#define PA_OUTDR_OUTDR14_Pos              (14UL)                    /*!< PA OUTDR: OUTDR14 (Bit 14)                            */
+#define PA_OUTDR_OUTDR14_Msk              (0x4000UL)                /*!< PA OUTDR: OUTDR14 (Bitfield-Mask: 0x01)               */
+#define PA_OUTDR_OUTDR13_Pos              (13UL)                    /*!< PA OUTDR: OUTDR13 (Bit 13)                            */
+#define PA_OUTDR_OUTDR13_Msk              (0x2000UL)                /*!< PA OUTDR: OUTDR13 (Bitfield-Mask: 0x01)               */
+#define PA_OUTDR_OUTDR12_Pos              (12UL)                    /*!< PA OUTDR: OUTDR12 (Bit 12)                            */
+#define PA_OUTDR_OUTDR12_Msk              (0x1000UL)                /*!< PA OUTDR: OUTDR12 (Bitfield-Mask: 0x01)               */
+#define PA_OUTDR_OUTDR11_Pos              (11UL)                    /*!< PA OUTDR: OUTDR11 (Bit 11)                            */
+#define PA_OUTDR_OUTDR11_Msk              (0x800UL)                 /*!< PA OUTDR: OUTDR11 (Bitfield-Mask: 0x01)               */
+#define PA_OUTDR_OUTDR10_Pos              (10UL)                    /*!< PA OUTDR: OUTDR10 (Bit 10)                            */
+#define PA_OUTDR_OUTDR10_Msk              (0x400UL)                 /*!< PA OUTDR: OUTDR10 (Bitfield-Mask: 0x01)               */
+#define PA_OUTDR_OUTDR9_Pos               (9UL)                     /*!< PA OUTDR: OUTDR9 (Bit 9)                              */
+#define PA_OUTDR_OUTDR9_Msk               (0x200UL)                 /*!< PA OUTDR: OUTDR9 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR8_Pos               (8UL)                     /*!< PA OUTDR: OUTDR8 (Bit 8)                              */
+#define PA_OUTDR_OUTDR8_Msk               (0x100UL)                 /*!< PA OUTDR: OUTDR8 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR7_Pos               (7UL)                     /*!< PA OUTDR: OUTDR7 (Bit 7)                              */
+#define PA_OUTDR_OUTDR7_Msk               (0x80UL)                  /*!< PA OUTDR: OUTDR7 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR6_Pos               (6UL)                     /*!< PA OUTDR: OUTDR6 (Bit 6)                              */
+#define PA_OUTDR_OUTDR6_Msk               (0x40UL)                  /*!< PA OUTDR: OUTDR6 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR5_Pos               (5UL)                     /*!< PA OUTDR: OUTDR5 (Bit 5)                              */
+#define PA_OUTDR_OUTDR5_Msk               (0x20UL)                  /*!< PA OUTDR: OUTDR5 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR4_Pos               (4UL)                     /*!< PA OUTDR: OUTDR4 (Bit 4)                              */
+#define PA_OUTDR_OUTDR4_Msk               (0x10UL)                  /*!< PA OUTDR: OUTDR4 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR3_Pos               (3UL)                     /*!< PA OUTDR: OUTDR3 (Bit 3)                              */
+#define PA_OUTDR_OUTDR3_Msk               (0x8UL)                   /*!< PA OUTDR: OUTDR3 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR2_Pos               (2UL)                     /*!< PA OUTDR: OUTDR2 (Bit 2)                              */
+#define PA_OUTDR_OUTDR2_Msk               (0x4UL)                   /*!< PA OUTDR: OUTDR2 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR1_Pos               (1UL)                     /*!< PA OUTDR: OUTDR1 (Bit 1)                              */
+#define PA_OUTDR_OUTDR1_Msk               (0x2UL)                   /*!< PA OUTDR: OUTDR1 (Bitfield-Mask: 0x01)                */
+#define PA_OUTDR_OUTDR0_Pos               (0UL)                     /*!< PA OUTDR: OUTDR0 (Bit 0)                              */
+#define PA_OUTDR_OUTDR0_Msk               (0x1UL)                   /*!< PA OUTDR: OUTDR0 (Bitfield-Mask: 0x01)                */
+/* ==========================================================  BSR  ========================================================== */
+#define PA_BSR_BSR15_Pos                  (15UL)                    /*!< PA BSR: BSR15 (Bit 15)                                */
+#define PA_BSR_BSR15_Msk                  (0x8000UL)                /*!< PA BSR: BSR15 (Bitfield-Mask: 0x01)                   */
+#define PA_BSR_BSR14_Pos                  (14UL)                    /*!< PA BSR: BSR14 (Bit 14)                                */
+#define PA_BSR_BSR14_Msk                  (0x4000UL)                /*!< PA BSR: BSR14 (Bitfield-Mask: 0x01)                   */
+#define PA_BSR_BSR13_Pos                  (13UL)                    /*!< PA BSR: BSR13 (Bit 13)                                */
+#define PA_BSR_BSR13_Msk                  (0x2000UL)                /*!< PA BSR: BSR13 (Bitfield-Mask: 0x01)                   */
+#define PA_BSR_BSR12_Pos                  (12UL)                    /*!< PA BSR: BSR12 (Bit 12)                                */
+#define PA_BSR_BSR12_Msk                  (0x1000UL)                /*!< PA BSR: BSR12 (Bitfield-Mask: 0x01)                   */
+#define PA_BSR_BSR11_Pos                  (11UL)                    /*!< PA BSR: BSR11 (Bit 11)                                */
+#define PA_BSR_BSR11_Msk                  (0x800UL)                 /*!< PA BSR: BSR11 (Bitfield-Mask: 0x01)                   */
+#define PA_BSR_BSR10_Pos                  (10UL)                    /*!< PA BSR: BSR10 (Bit 10)                                */
+#define PA_BSR_BSR10_Msk                  (0x400UL)                 /*!< PA BSR: BSR10 (Bitfield-Mask: 0x01)                   */
+#define PA_BSR_BSR9_Pos                   (9UL)                     /*!< PA BSR: BSR9 (Bit 9)                                  */
+#define PA_BSR_BSR9_Msk                   (0x200UL)                 /*!< PA BSR: BSR9 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR8_Pos                   (8UL)                     /*!< PA BSR: BSR8 (Bit 8)                                  */
+#define PA_BSR_BSR8_Msk                   (0x100UL)                 /*!< PA BSR: BSR8 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR7_Pos                   (7UL)                     /*!< PA BSR: BSR7 (Bit 7)                                  */
+#define PA_BSR_BSR7_Msk                   (0x80UL)                  /*!< PA BSR: BSR7 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR6_Pos                   (6UL)                     /*!< PA BSR: BSR6 (Bit 6)                                  */
+#define PA_BSR_BSR6_Msk                   (0x40UL)                  /*!< PA BSR: BSR6 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR5_Pos                   (5UL)                     /*!< PA BSR: BSR5 (Bit 5)                                  */
+#define PA_BSR_BSR5_Msk                   (0x20UL)                  /*!< PA BSR: BSR5 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR4_Pos                   (4UL)                     /*!< PA BSR: BSR4 (Bit 4)                                  */
+#define PA_BSR_BSR4_Msk                   (0x10UL)                  /*!< PA BSR: BSR4 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR3_Pos                   (3UL)                     /*!< PA BSR: BSR3 (Bit 3)                                  */
+#define PA_BSR_BSR3_Msk                   (0x8UL)                   /*!< PA BSR: BSR3 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR2_Pos                   (2UL)                     /*!< PA BSR: BSR2 (Bit 2)                                  */
+#define PA_BSR_BSR2_Msk                   (0x4UL)                   /*!< PA BSR: BSR2 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR1_Pos                   (1UL)                     /*!< PA BSR: BSR1 (Bit 1)                                  */
+#define PA_BSR_BSR1_Msk                   (0x2UL)                   /*!< PA BSR: BSR1 (Bitfield-Mask: 0x01)                    */
+#define PA_BSR_BSR0_Pos                   (0UL)                     /*!< PA BSR: BSR0 (Bit 0)                                  */
+#define PA_BSR_BSR0_Msk                   (0x1UL)                   /*!< PA BSR: BSR0 (Bitfield-Mask: 0x01)                    */
+/* ==========================================================  BCR  ========================================================== */
+#define PA_BCR_BCR15_Pos                  (15UL)                    /*!< PA BCR: BCR15 (Bit 15)                                */
+#define PA_BCR_BCR15_Msk                  (0x8000UL)                /*!< PA BCR: BCR15 (Bitfield-Mask: 0x01)                   */
+#define PA_BCR_BCR14_Pos                  (14UL)                    /*!< PA BCR: BCR14 (Bit 14)                                */
+#define PA_BCR_BCR14_Msk                  (0x4000UL)                /*!< PA BCR: BCR14 (Bitfield-Mask: 0x01)                   */
+#define PA_BCR_BCR13_Pos                  (13UL)                    /*!< PA BCR: BCR13 (Bit 13)                                */
+#define PA_BCR_BCR13_Msk                  (0x2000UL)                /*!< PA BCR: BCR13 (Bitfield-Mask: 0x01)                   */
+#define PA_BCR_BCR12_Pos                  (12UL)                    /*!< PA BCR: BCR12 (Bit 12)                                */
+#define PA_BCR_BCR12_Msk                  (0x1000UL)                /*!< PA BCR: BCR12 (Bitfield-Mask: 0x01)                   */
+#define PA_BCR_BCR11_Pos                  (11UL)                    /*!< PA BCR: BCR11 (Bit 11)                                */
+#define PA_BCR_BCR11_Msk                  (0x800UL)                 /*!< PA BCR: BCR11 (Bitfield-Mask: 0x01)                   */
+#define PA_BCR_BCR10_Pos                  (10UL)                    /*!< PA BCR: BCR10 (Bit 10)                                */
+#define PA_BCR_BCR10_Msk                  (0x400UL)                 /*!< PA BCR: BCR10 (Bitfield-Mask: 0x01)                   */
+#define PA_BCR_BCR9_Pos                   (9UL)                     /*!< PA BCR: BCR9 (Bit 9)                                  */
+#define PA_BCR_BCR9_Msk                   (0x200UL)                 /*!< PA BCR: BCR9 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR8_Pos                   (8UL)                     /*!< PA BCR: BCR8 (Bit 8)                                  */
+#define PA_BCR_BCR8_Msk                   (0x100UL)                 /*!< PA BCR: BCR8 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR7_Pos                   (7UL)                     /*!< PA BCR: BCR7 (Bit 7)                                  */
+#define PA_BCR_BCR7_Msk                   (0x80UL)                  /*!< PA BCR: BCR7 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR6_Pos                   (6UL)                     /*!< PA BCR: BCR6 (Bit 6)                                  */
+#define PA_BCR_BCR6_Msk                   (0x40UL)                  /*!< PA BCR: BCR6 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR5_Pos                   (5UL)                     /*!< PA BCR: BCR5 (Bit 5)                                  */
+#define PA_BCR_BCR5_Msk                   (0x20UL)                  /*!< PA BCR: BCR5 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR4_Pos                   (4UL)                     /*!< PA BCR: BCR4 (Bit 4)                                  */
+#define PA_BCR_BCR4_Msk                   (0x10UL)                  /*!< PA BCR: BCR4 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR3_Pos                   (3UL)                     /*!< PA BCR: BCR3 (Bit 3)                                  */
+#define PA_BCR_BCR3_Msk                   (0x8UL)                   /*!< PA BCR: BCR3 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR2_Pos                   (2UL)                     /*!< PA BCR: BCR2 (Bit 2)                                  */
+#define PA_BCR_BCR2_Msk                   (0x4UL)                   /*!< PA BCR: BCR2 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR1_Pos                   (1UL)                     /*!< PA BCR: BCR1 (Bit 1)                                  */
+#define PA_BCR_BCR1_Msk                   (0x2UL)                   /*!< PA BCR: BCR1 (Bitfield-Mask: 0x01)                    */
+#define PA_BCR_BCR0_Pos                   (0UL)                     /*!< PA BCR: BCR0 (Bit 0)                                  */
+#define PA_BCR_BCR0_Msk                   (0x1UL)                   /*!< PA BCR: BCR0 (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OUTDMSK  ======================================================== */
+#define PA_OUTDMSK_OUTDMSK15_Pos          (15UL)                    /*!< PA OUTDMSK: OUTDMSK15 (Bit 15)                        */
+#define PA_OUTDMSK_OUTDMSK15_Msk          (0x8000UL)                /*!< PA OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)           */
+#define PA_OUTDMSK_OUTDMSK14_Pos          (14UL)                    /*!< PA OUTDMSK: OUTDMSK14 (Bit 14)                        */
+#define PA_OUTDMSK_OUTDMSK14_Msk          (0x4000UL)                /*!< PA OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)           */
+#define PA_OUTDMSK_OUTDMSK13_Pos          (13UL)                    /*!< PA OUTDMSK: OUTDMSK13 (Bit 13)                        */
+#define PA_OUTDMSK_OUTDMSK13_Msk          (0x2000UL)                /*!< PA OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)           */
+#define PA_OUTDMSK_OUTDMSK12_Pos          (12UL)                    /*!< PA OUTDMSK: OUTDMSK12 (Bit 12)                        */
+#define PA_OUTDMSK_OUTDMSK12_Msk          (0x1000UL)                /*!< PA OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)           */
+#define PA_OUTDMSK_OUTDMSK11_Pos          (11UL)                    /*!< PA OUTDMSK: OUTDMSK11 (Bit 11)                        */
+#define PA_OUTDMSK_OUTDMSK11_Msk          (0x800UL)                 /*!< PA OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)           */
+#define PA_OUTDMSK_OUTDMSK10_Pos          (10UL)                    /*!< PA OUTDMSK: OUTDMSK10 (Bit 10)                        */
+#define PA_OUTDMSK_OUTDMSK10_Msk          (0x400UL)                 /*!< PA OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)           */
+#define PA_OUTDMSK_OUTDMSK9_Pos           (9UL)                     /*!< PA OUTDMSK: OUTDMSK9 (Bit 9)                          */
+#define PA_OUTDMSK_OUTDMSK9_Msk           (0x200UL)                 /*!< PA OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK8_Pos           (8UL)                     /*!< PA OUTDMSK: OUTDMSK8 (Bit 8)                          */
+#define PA_OUTDMSK_OUTDMSK8_Msk           (0x100UL)                 /*!< PA OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK7_Pos           (7UL)                     /*!< PA OUTDMSK: OUTDMSK7 (Bit 7)                          */
+#define PA_OUTDMSK_OUTDMSK7_Msk           (0x80UL)                  /*!< PA OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK6_Pos           (6UL)                     /*!< PA OUTDMSK: OUTDMSK6 (Bit 6)                          */
+#define PA_OUTDMSK_OUTDMSK6_Msk           (0x40UL)                  /*!< PA OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK5_Pos           (5UL)                     /*!< PA OUTDMSK: OUTDMSK5 (Bit 5)                          */
+#define PA_OUTDMSK_OUTDMSK5_Msk           (0x20UL)                  /*!< PA OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK4_Pos           (4UL)                     /*!< PA OUTDMSK: OUTDMSK4 (Bit 4)                          */
+#define PA_OUTDMSK_OUTDMSK4_Msk           (0x10UL)                  /*!< PA OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK3_Pos           (3UL)                     /*!< PA OUTDMSK: OUTDMSK3 (Bit 3)                          */
+#define PA_OUTDMSK_OUTDMSK3_Msk           (0x8UL)                   /*!< PA OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK2_Pos           (2UL)                     /*!< PA OUTDMSK: OUTDMSK2 (Bit 2)                          */
+#define PA_OUTDMSK_OUTDMSK2_Msk           (0x4UL)                   /*!< PA OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK1_Pos           (1UL)                     /*!< PA OUTDMSK: OUTDMSK1 (Bit 1)                          */
+#define PA_OUTDMSK_OUTDMSK1_Msk           (0x2UL)                   /*!< PA OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)            */
+#define PA_OUTDMSK_OUTDMSK0_Pos           (0UL)                     /*!< PA OUTDMSK: OUTDMSK0 (Bit 0)                          */
+#define PA_OUTDMSK_OUTDMSK0_Msk           (0x1UL)                   /*!< PA OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)            */
+/* =========================================================  DBCR  ========================================================== */
+#define PA_DBCR_DBCLK_Pos                 (16UL)                    /*!< PA DBCR: DBCLK (Bit 16)                               */
+#define PA_DBCR_DBCLK_Msk                 (0x70000UL)               /*!< PA DBCR: DBCLK (Bitfield-Mask: 0x07)                  */
+#define PA_DBCR_DBEN11_Pos                (11UL)                    /*!< PA DBCR: DBEN11 (Bit 11)                              */
+#define PA_DBCR_DBEN11_Msk                (0x800UL)                 /*!< PA DBCR: DBEN11 (Bitfield-Mask: 0x01)                 */
+#define PA_DBCR_DBEN10_Pos                (10UL)                    /*!< PA DBCR: DBEN10 (Bit 10)                              */
+#define PA_DBCR_DBEN10_Msk                (0x400UL)                 /*!< PA DBCR: DBEN10 (Bitfield-Mask: 0x01)                 */
+#define PA_DBCR_DBEN9_Pos                 (9UL)                     /*!< PA DBCR: DBEN9 (Bit 9)                                */
+#define PA_DBCR_DBEN9_Msk                 (0x200UL)                 /*!< PA DBCR: DBEN9 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN8_Pos                 (8UL)                     /*!< PA DBCR: DBEN8 (Bit 8)                                */
+#define PA_DBCR_DBEN8_Msk                 (0x100UL)                 /*!< PA DBCR: DBEN8 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN7_Pos                 (7UL)                     /*!< PA DBCR: DBEN7 (Bit 7)                                */
+#define PA_DBCR_DBEN7_Msk                 (0x80UL)                  /*!< PA DBCR: DBEN7 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN6_Pos                 (6UL)                     /*!< PA DBCR: DBEN6 (Bit 6)                                */
+#define PA_DBCR_DBEN6_Msk                 (0x40UL)                  /*!< PA DBCR: DBEN6 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN5_Pos                 (5UL)                     /*!< PA DBCR: DBEN5 (Bit 5)                                */
+#define PA_DBCR_DBEN5_Msk                 (0x20UL)                  /*!< PA DBCR: DBEN5 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN4_Pos                 (4UL)                     /*!< PA DBCR: DBEN4 (Bit 4)                                */
+#define PA_DBCR_DBEN4_Msk                 (0x10UL)                  /*!< PA DBCR: DBEN4 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN3_Pos                 (3UL)                     /*!< PA DBCR: DBEN3 (Bit 3)                                */
+#define PA_DBCR_DBEN3_Msk                 (0x8UL)                   /*!< PA DBCR: DBEN3 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN2_Pos                 (2UL)                     /*!< PA DBCR: DBEN2 (Bit 2)                                */
+#define PA_DBCR_DBEN2_Msk                 (0x4UL)                   /*!< PA DBCR: DBEN2 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN1_Pos                 (1UL)                     /*!< PA DBCR: DBEN1 (Bit 1)                                */
+#define PA_DBCR_DBEN1_Msk                 (0x2UL)                   /*!< PA DBCR: DBEN1 (Bitfield-Mask: 0x01)                  */
+#define PA_DBCR_DBEN0_Pos                 (0UL)                     /*!< PA DBCR: DBEN0 (Bit 0)                                */
+#define PA_DBCR_DBEN0_Msk                 (0x1UL)                   /*!< PA DBCR: DBEN0 (Bitfield-Mask: 0x01)                  */
+/* ========================================================  PA_MOD  ========================================================= */
+#define PA_PA_MOD_MODE11_Pos              (22UL)                    /*!< PA PA_MOD: MODE11 (Bit 22)                            */
+#define PA_PA_MOD_MODE11_Msk              (0xc00000UL)              /*!< PA PA_MOD: MODE11 (Bitfield-Mask: 0x03)               */
+#define PA_PA_MOD_MODE10_Pos              (20UL)                    /*!< PA PA_MOD: MODE10 (Bit 20)                            */
+#define PA_PA_MOD_MODE10_Msk              (0x300000UL)              /*!< PA PA_MOD: MODE10 (Bitfield-Mask: 0x03)               */
+#define PA_PA_MOD_MODE9_Pos               (18UL)                    /*!< PA PA_MOD: MODE9 (Bit 18)                             */
+#define PA_PA_MOD_MODE9_Msk               (0xc0000UL)               /*!< PA PA_MOD: MODE9 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE8_Pos               (16UL)                    /*!< PA PA_MOD: MODE8 (Bit 16)                             */
+#define PA_PA_MOD_MODE8_Msk               (0x30000UL)               /*!< PA PA_MOD: MODE8 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE7_Pos               (14UL)                    /*!< PA PA_MOD: MODE7 (Bit 14)                             */
+#define PA_PA_MOD_MODE7_Msk               (0xc000UL)                /*!< PA PA_MOD: MODE7 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE6_Pos               (12UL)                    /*!< PA PA_MOD: MODE6 (Bit 12)                             */
+#define PA_PA_MOD_MODE6_Msk               (0x3000UL)                /*!< PA PA_MOD: MODE6 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE5_Pos               (10UL)                    /*!< PA PA_MOD: MODE5 (Bit 10)                             */
+#define PA_PA_MOD_MODE5_Msk               (0xc00UL)                 /*!< PA PA_MOD: MODE5 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE4_Pos               (8UL)                     /*!< PA PA_MOD: MODE4 (Bit 8)                              */
+#define PA_PA_MOD_MODE4_Msk               (0x300UL)                 /*!< PA PA_MOD: MODE4 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE3_Pos               (6UL)                     /*!< PA PA_MOD: MODE3 (Bit 6)                              */
+#define PA_PA_MOD_MODE3_Msk               (0xc0UL)                  /*!< PA PA_MOD: MODE3 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE2_Pos               (4UL)                     /*!< PA PA_MOD: MODE2 (Bit 4)                              */
+#define PA_PA_MOD_MODE2_Msk               (0x30UL)                  /*!< PA PA_MOD: MODE2 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE1_Pos               (2UL)                     /*!< PA PA_MOD: MODE1 (Bit 2)                              */
+#define PA_PA_MOD_MODE1_Msk               (0xcUL)                   /*!< PA PA_MOD: MODE1 (Bitfield-Mask: 0x03)                */
+#define PA_PA_MOD_MODE0_Pos               (0UL)                     /*!< PA PA_MOD: MODE0 (Bit 0)                              */
+#define PA_PA_MOD_MODE0_Msk               (0x3UL)                   /*!< PA PA_MOD: MODE0 (Bitfield-Mask: 0x03)                */
+/* ========================================================  PA_TYP  ========================================================= */
+#define PA_PA_TYP_TYP11_Pos               (11UL)                    /*!< PA PA_TYP: TYP11 (Bit 11)                             */
+#define PA_PA_TYP_TYP11_Msk               (0x800UL)                 /*!< PA PA_TYP: TYP11 (Bitfield-Mask: 0x01)                */
+#define PA_PA_TYP_TYP10_Pos               (10UL)                    /*!< PA PA_TYP: TYP10 (Bit 10)                             */
+#define PA_PA_TYP_TYP10_Msk               (0x400UL)                 /*!< PA PA_TYP: TYP10 (Bitfield-Mask: 0x01)                */
+#define PA_PA_TYP_TYP9_Pos                (9UL)                     /*!< PA PA_TYP: TYP9 (Bit 9)                               */
+#define PA_PA_TYP_TYP9_Msk                (0x200UL)                 /*!< PA PA_TYP: TYP9 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP8_Pos                (8UL)                     /*!< PA PA_TYP: TYP8 (Bit 8)                               */
+#define PA_PA_TYP_TYP8_Msk                (0x100UL)                 /*!< PA PA_TYP: TYP8 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP7_Pos                (7UL)                     /*!< PA PA_TYP: TYP7 (Bit 7)                               */
+#define PA_PA_TYP_TYP7_Msk                (0x80UL)                  /*!< PA PA_TYP: TYP7 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP6_Pos                (6UL)                     /*!< PA PA_TYP: TYP6 (Bit 6)                               */
+#define PA_PA_TYP_TYP6_Msk                (0x40UL)                  /*!< PA PA_TYP: TYP6 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP5_Pos                (5UL)                     /*!< PA PA_TYP: TYP5 (Bit 5)                               */
+#define PA_PA_TYP_TYP5_Msk                (0x20UL)                  /*!< PA PA_TYP: TYP5 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP4_Pos                (4UL)                     /*!< PA PA_TYP: TYP4 (Bit 4)                               */
+#define PA_PA_TYP_TYP4_Msk                (0x10UL)                  /*!< PA PA_TYP: TYP4 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP3_Pos                (3UL)                     /*!< PA PA_TYP: TYP3 (Bit 3)                               */
+#define PA_PA_TYP_TYP3_Msk                (0x8UL)                   /*!< PA PA_TYP: TYP3 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP2_Pos                (2UL)                     /*!< PA PA_TYP: TYP2 (Bit 2)                               */
+#define PA_PA_TYP_TYP2_Msk                (0x4UL)                   /*!< PA PA_TYP: TYP2 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP1_Pos                (1UL)                     /*!< PA PA_TYP: TYP1 (Bit 1)                               */
+#define PA_PA_TYP_TYP1_Msk                (0x2UL)                   /*!< PA PA_TYP: TYP1 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_TYP_TYP0_Pos                (0UL)                     /*!< PA PA_TYP: TYP0 (Bit 0)                               */
+#define PA_PA_TYP_TYP0_Msk                (0x1UL)                   /*!< PA PA_TYP: TYP0 (Bitfield-Mask: 0x01)                 */
+/* =======================================================  PA_AFSR1  ======================================================== */
+#define PA_PA_AFSR1_AFSR7_Pos             (28UL)                    /*!< PA PA_AFSR1: AFSR7 (Bit 28)                           */
+#define PA_PA_AFSR1_AFSR7_Msk             (0xf0000000UL)            /*!< PA PA_AFSR1: AFSR7 (Bitfield-Mask: 0x0f)              */
+#define PA_PA_AFSR1_AFSR6_Pos             (24UL)                    /*!< PA PA_AFSR1: AFSR6 (Bit 24)                           */
+#define PA_PA_AFSR1_AFSR6_Msk             (0xf000000UL)             /*!< PA PA_AFSR1: AFSR6 (Bitfield-Mask: 0x0f)              */
+#define PA_PA_AFSR1_AFSR5_Pos             (20UL)                    /*!< PA PA_AFSR1: AFSR5 (Bit 20)                           */
+#define PA_PA_AFSR1_AFSR5_Msk             (0xf00000UL)              /*!< PA PA_AFSR1: AFSR5 (Bitfield-Mask: 0x0f)              */
+#define PA_PA_AFSR1_AFSR4_Pos             (16UL)                    /*!< PA PA_AFSR1: AFSR4 (Bit 16)                           */
+#define PA_PA_AFSR1_AFSR4_Msk             (0xf0000UL)               /*!< PA PA_AFSR1: AFSR4 (Bitfield-Mask: 0x0f)              */
+#define PA_PA_AFSR1_AFSR3_Pos             (12UL)                    /*!< PA PA_AFSR1: AFSR3 (Bit 12)                           */
+#define PA_PA_AFSR1_AFSR3_Msk             (0xf000UL)                /*!< PA PA_AFSR1: AFSR3 (Bitfield-Mask: 0x0f)              */
+#define PA_PA_AFSR1_AFSR2_Pos             (8UL)                     /*!< PA PA_AFSR1: AFSR2 (Bit 8)                            */
+#define PA_PA_AFSR1_AFSR2_Msk             (0xf00UL)                 /*!< PA PA_AFSR1: AFSR2 (Bitfield-Mask: 0x0f)              */
+#define PA_PA_AFSR1_AFSR1_Pos             (4UL)                     /*!< PA PA_AFSR1: AFSR1 (Bit 4)                            */
+#define PA_PA_AFSR1_AFSR1_Msk             (0xf0UL)                  /*!< PA PA_AFSR1: AFSR1 (Bitfield-Mask: 0x0f)              */
+#define PA_PA_AFSR1_AFSR0_Pos             (0UL)                     /*!< PA PA_AFSR1: AFSR0 (Bit 0)                            */
+#define PA_PA_AFSR1_AFSR0_Msk             (0xfUL)                   /*!< PA PA_AFSR1: AFSR0 (Bitfield-Mask: 0x0f)              */
+/* =======================================================  PA_AFSR2  ======================================================== */
+#define PA_PA_AFSR2_AFSR11_Pos            (12UL)                    /*!< PA PA_AFSR2: AFSR11 (Bit 12)                          */
+#define PA_PA_AFSR2_AFSR11_Msk            (0xf000UL)                /*!< PA PA_AFSR2: AFSR11 (Bitfield-Mask: 0x0f)             */
+#define PA_PA_AFSR2_AFSR10_Pos            (8UL)                     /*!< PA PA_AFSR2: AFSR10 (Bit 8)                           */
+#define PA_PA_AFSR2_AFSR10_Msk            (0xf00UL)                 /*!< PA PA_AFSR2: AFSR10 (Bitfield-Mask: 0x0f)             */
+#define PA_PA_AFSR2_AFSR9_Pos             (4UL)                     /*!< PA PA_AFSR2: AFSR9 (Bit 4)                            */
+#define PA_PA_AFSR2_AFSR9_Msk             (0xf0UL)                  /*!< PA PA_AFSR2: AFSR9 (Bitfield-Mask: 0x0f)              */
+#define PA_PA_AFSR2_AFSR8_Pos             (0UL)                     /*!< PA PA_AFSR2: AFSR8 (Bit 0)                            */
+#define PA_PA_AFSR2_AFSR8_Msk             (0xfUL)                   /*!< PA PA_AFSR2: AFSR8 (Bitfield-Mask: 0x0f)              */
+/* ========================================================  PA_PUPD  ======================================================== */
+#define PA_PA_PUPD_PUPD11_Pos             (22UL)                    /*!< PA PA_PUPD: PUPD11 (Bit 22)                           */
+#define PA_PA_PUPD_PUPD11_Msk             (0xc00000UL)              /*!< PA PA_PUPD: PUPD11 (Bitfield-Mask: 0x03)              */
+#define PA_PA_PUPD_PUPD10_Pos             (20UL)                    /*!< PA PA_PUPD: PUPD10 (Bit 20)                           */
+#define PA_PA_PUPD_PUPD10_Msk             (0x300000UL)              /*!< PA PA_PUPD: PUPD10 (Bitfield-Mask: 0x03)              */
+#define PA_PA_PUPD_PUPD9_Pos              (18UL)                    /*!< PA PA_PUPD: PUPD9 (Bit 18)                            */
+#define PA_PA_PUPD_PUPD9_Msk              (0xc0000UL)               /*!< PA PA_PUPD: PUPD9 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD8_Pos              (16UL)                    /*!< PA PA_PUPD: PUPD8 (Bit 16)                            */
+#define PA_PA_PUPD_PUPD8_Msk              (0x30000UL)               /*!< PA PA_PUPD: PUPD8 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD7_Pos              (14UL)                    /*!< PA PA_PUPD: PUPD7 (Bit 14)                            */
+#define PA_PA_PUPD_PUPD7_Msk              (0xc000UL)                /*!< PA PA_PUPD: PUPD7 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD6_Pos              (12UL)                    /*!< PA PA_PUPD: PUPD6 (Bit 12)                            */
+#define PA_PA_PUPD_PUPD6_Msk              (0x3000UL)                /*!< PA PA_PUPD: PUPD6 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD5_Pos              (10UL)                    /*!< PA PA_PUPD: PUPD5 (Bit 10)                            */
+#define PA_PA_PUPD_PUPD5_Msk              (0xc00UL)                 /*!< PA PA_PUPD: PUPD5 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD4_Pos              (8UL)                     /*!< PA PA_PUPD: PUPD4 (Bit 8)                             */
+#define PA_PA_PUPD_PUPD4_Msk              (0x300UL)                 /*!< PA PA_PUPD: PUPD4 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD3_Pos              (6UL)                     /*!< PA PA_PUPD: PUPD3 (Bit 6)                             */
+#define PA_PA_PUPD_PUPD3_Msk              (0xc0UL)                  /*!< PA PA_PUPD: PUPD3 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD2_Pos              (4UL)                     /*!< PA PA_PUPD: PUPD2 (Bit 4)                             */
+#define PA_PA_PUPD_PUPD2_Msk              (0x30UL)                  /*!< PA PA_PUPD: PUPD2 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD1_Pos              (2UL)                     /*!< PA PA_PUPD: PUPD1 (Bit 2)                             */
+#define PA_PA_PUPD_PUPD1_Msk              (0xcUL)                   /*!< PA PA_PUPD: PUPD1 (Bitfield-Mask: 0x03)               */
+#define PA_PA_PUPD_PUPD0_Pos              (0UL)                     /*!< PA PA_PUPD: PUPD0 (Bit 0)                             */
+#define PA_PA_PUPD_PUPD0_Msk              (0x3UL)                   /*!< PA PA_PUPD: PUPD0 (Bitfield-Mask: 0x03)               */
+/* ========================================================  PA_INDR  ======================================================== */
+#define PA_PA_INDR_INDR11_Pos             (11UL)                    /*!< PA PA_INDR: INDR11 (Bit 11)                           */
+#define PA_PA_INDR_INDR11_Msk             (0x800UL)                 /*!< PA PA_INDR: INDR11 (Bitfield-Mask: 0x01)              */
+#define PA_PA_INDR_INDR10_Pos             (10UL)                    /*!< PA PA_INDR: INDR10 (Bit 10)                           */
+#define PA_PA_INDR_INDR10_Msk             (0x400UL)                 /*!< PA PA_INDR: INDR10 (Bitfield-Mask: 0x01)              */
+#define PA_PA_INDR_INDR9_Pos              (9UL)                     /*!< PA PA_INDR: INDR9 (Bit 9)                             */
+#define PA_PA_INDR_INDR9_Msk              (0x200UL)                 /*!< PA PA_INDR: INDR9 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR8_Pos              (8UL)                     /*!< PA PA_INDR: INDR8 (Bit 8)                             */
+#define PA_PA_INDR_INDR8_Msk              (0x100UL)                 /*!< PA PA_INDR: INDR8 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR7_Pos              (7UL)                     /*!< PA PA_INDR: INDR7 (Bit 7)                             */
+#define PA_PA_INDR_INDR7_Msk              (0x80UL)                  /*!< PA PA_INDR: INDR7 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR6_Pos              (6UL)                     /*!< PA PA_INDR: INDR6 (Bit 6)                             */
+#define PA_PA_INDR_INDR6_Msk              (0x40UL)                  /*!< PA PA_INDR: INDR6 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR5_Pos              (5UL)                     /*!< PA PA_INDR: INDR5 (Bit 5)                             */
+#define PA_PA_INDR_INDR5_Msk              (0x20UL)                  /*!< PA PA_INDR: INDR5 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR4_Pos              (4UL)                     /*!< PA PA_INDR: INDR4 (Bit 4)                             */
+#define PA_PA_INDR_INDR4_Msk              (0x10UL)                  /*!< PA PA_INDR: INDR4 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR3_Pos              (3UL)                     /*!< PA PA_INDR: INDR3 (Bit 3)                             */
+#define PA_PA_INDR_INDR3_Msk              (0x8UL)                   /*!< PA PA_INDR: INDR3 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR2_Pos              (2UL)                     /*!< PA PA_INDR: INDR2 (Bit 2)                             */
+#define PA_PA_INDR_INDR2_Msk              (0x4UL)                   /*!< PA PA_INDR: INDR2 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR1_Pos              (1UL)                     /*!< PA PA_INDR: INDR1 (Bit 1)                             */
+#define PA_PA_INDR_INDR1_Msk              (0x2UL)                   /*!< PA PA_INDR: INDR1 (Bitfield-Mask: 0x01)               */
+#define PA_PA_INDR_INDR0_Pos              (0UL)                     /*!< PA PA_INDR: INDR0 (Bit 0)                             */
+#define PA_PA_INDR_INDR0_Msk              (0x1UL)                   /*!< PA PA_INDR: INDR0 (Bitfield-Mask: 0x01)               */
+/* =======================================================  PA_OUTDR  ======================================================== */
+#define PA_PA_OUTDR_OUTDR11_Pos           (11UL)                    /*!< PA PA_OUTDR: OUTDR11 (Bit 11)                         */
+#define PA_PA_OUTDR_OUTDR11_Msk           (0x800UL)                 /*!< PA PA_OUTDR: OUTDR11 (Bitfield-Mask: 0x01)            */
+#define PA_PA_OUTDR_OUTDR10_Pos           (10UL)                    /*!< PA PA_OUTDR: OUTDR10 (Bit 10)                         */
+#define PA_PA_OUTDR_OUTDR10_Msk           (0x400UL)                 /*!< PA PA_OUTDR: OUTDR10 (Bitfield-Mask: 0x01)            */
+#define PA_PA_OUTDR_OUTDR9_Pos            (9UL)                     /*!< PA PA_OUTDR: OUTDR9 (Bit 9)                           */
+#define PA_PA_OUTDR_OUTDR9_Msk            (0x200UL)                 /*!< PA PA_OUTDR: OUTDR9 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR8_Pos            (8UL)                     /*!< PA PA_OUTDR: OUTDR8 (Bit 8)                           */
+#define PA_PA_OUTDR_OUTDR8_Msk            (0x100UL)                 /*!< PA PA_OUTDR: OUTDR8 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR7_Pos            (7UL)                     /*!< PA PA_OUTDR: OUTDR7 (Bit 7)                           */
+#define PA_PA_OUTDR_OUTDR7_Msk            (0x80UL)                  /*!< PA PA_OUTDR: OUTDR7 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR6_Pos            (6UL)                     /*!< PA PA_OUTDR: OUTDR6 (Bit 6)                           */
+#define PA_PA_OUTDR_OUTDR6_Msk            (0x40UL)                  /*!< PA PA_OUTDR: OUTDR6 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR5_Pos            (5UL)                     /*!< PA PA_OUTDR: OUTDR5 (Bit 5)                           */
+#define PA_PA_OUTDR_OUTDR5_Msk            (0x20UL)                  /*!< PA PA_OUTDR: OUTDR5 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR4_Pos            (4UL)                     /*!< PA PA_OUTDR: OUTDR4 (Bit 4)                           */
+#define PA_PA_OUTDR_OUTDR4_Msk            (0x10UL)                  /*!< PA PA_OUTDR: OUTDR4 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR3_Pos            (3UL)                     /*!< PA PA_OUTDR: OUTDR3 (Bit 3)                           */
+#define PA_PA_OUTDR_OUTDR3_Msk            (0x8UL)                   /*!< PA PA_OUTDR: OUTDR3 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR2_Pos            (2UL)                     /*!< PA PA_OUTDR: OUTDR2 (Bit 2)                           */
+#define PA_PA_OUTDR_OUTDR2_Msk            (0x4UL)                   /*!< PA PA_OUTDR: OUTDR2 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR1_Pos            (1UL)                     /*!< PA PA_OUTDR: OUTDR1 (Bit 1)                           */
+#define PA_PA_OUTDR_OUTDR1_Msk            (0x2UL)                   /*!< PA PA_OUTDR: OUTDR1 (Bitfield-Mask: 0x01)             */
+#define PA_PA_OUTDR_OUTDR0_Pos            (0UL)                     /*!< PA PA_OUTDR: OUTDR0 (Bit 0)                           */
+#define PA_PA_OUTDR_OUTDR0_Msk            (0x1UL)                   /*!< PA PA_OUTDR: OUTDR0 (Bitfield-Mask: 0x01)             */
+/* ========================================================  PA_BSR  ========================================================= */
+#define PA_PA_BSR_BSR11_Pos               (11UL)                    /*!< PA PA_BSR: BSR11 (Bit 11)                             */
+#define PA_PA_BSR_BSR11_Msk               (0x800UL)                 /*!< PA PA_BSR: BSR11 (Bitfield-Mask: 0x01)                */
+#define PA_PA_BSR_BSR10_Pos               (10UL)                    /*!< PA PA_BSR: BSR10 (Bit 10)                             */
+#define PA_PA_BSR_BSR10_Msk               (0x400UL)                 /*!< PA PA_BSR: BSR10 (Bitfield-Mask: 0x01)                */
+#define PA_PA_BSR_BSR9_Pos                (9UL)                     /*!< PA PA_BSR: BSR9 (Bit 9)                               */
+#define PA_PA_BSR_BSR9_Msk                (0x200UL)                 /*!< PA PA_BSR: BSR9 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR8_Pos                (8UL)                     /*!< PA PA_BSR: BSR8 (Bit 8)                               */
+#define PA_PA_BSR_BSR8_Msk                (0x100UL)                 /*!< PA PA_BSR: BSR8 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR7_Pos                (7UL)                     /*!< PA PA_BSR: BSR7 (Bit 7)                               */
+#define PA_PA_BSR_BSR7_Msk                (0x80UL)                  /*!< PA PA_BSR: BSR7 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR6_Pos                (6UL)                     /*!< PA PA_BSR: BSR6 (Bit 6)                               */
+#define PA_PA_BSR_BSR6_Msk                (0x40UL)                  /*!< PA PA_BSR: BSR6 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR5_Pos                (5UL)                     /*!< PA PA_BSR: BSR5 (Bit 5)                               */
+#define PA_PA_BSR_BSR5_Msk                (0x20UL)                  /*!< PA PA_BSR: BSR5 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR4_Pos                (4UL)                     /*!< PA PA_BSR: BSR4 (Bit 4)                               */
+#define PA_PA_BSR_BSR4_Msk                (0x10UL)                  /*!< PA PA_BSR: BSR4 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR3_Pos                (3UL)                     /*!< PA PA_BSR: BSR3 (Bit 3)                               */
+#define PA_PA_BSR_BSR3_Msk                (0x8UL)                   /*!< PA PA_BSR: BSR3 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR2_Pos                (2UL)                     /*!< PA PA_BSR: BSR2 (Bit 2)                               */
+#define PA_PA_BSR_BSR2_Msk                (0x4UL)                   /*!< PA PA_BSR: BSR2 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR1_Pos                (1UL)                     /*!< PA PA_BSR: BSR1 (Bit 1)                               */
+#define PA_PA_BSR_BSR1_Msk                (0x2UL)                   /*!< PA PA_BSR: BSR1 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BSR_BSR0_Pos                (0UL)                     /*!< PA PA_BSR: BSR0 (Bit 0)                               */
+#define PA_PA_BSR_BSR0_Msk                (0x1UL)                   /*!< PA PA_BSR: BSR0 (Bitfield-Mask: 0x01)                 */
+/* ========================================================  PA_BCR  ========================================================= */
+#define PA_PA_BCR_BCR11_Pos               (11UL)                    /*!< PA PA_BCR: BCR11 (Bit 11)                             */
+#define PA_PA_BCR_BCR11_Msk               (0x800UL)                 /*!< PA PA_BCR: BCR11 (Bitfield-Mask: 0x01)                */
+#define PA_PA_BCR_BCR10_Pos               (10UL)                    /*!< PA PA_BCR: BCR10 (Bit 10)                             */
+#define PA_PA_BCR_BCR10_Msk               (0x400UL)                 /*!< PA PA_BCR: BCR10 (Bitfield-Mask: 0x01)                */
+#define PA_PA_BCR_BCR9_Pos                (9UL)                     /*!< PA PA_BCR: BCR9 (Bit 9)                               */
+#define PA_PA_BCR_BCR9_Msk                (0x200UL)                 /*!< PA PA_BCR: BCR9 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR8_Pos                (8UL)                     /*!< PA PA_BCR: BCR8 (Bit 8)                               */
+#define PA_PA_BCR_BCR8_Msk                (0x100UL)                 /*!< PA PA_BCR: BCR8 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR7_Pos                (7UL)                     /*!< PA PA_BCR: BCR7 (Bit 7)                               */
+#define PA_PA_BCR_BCR7_Msk                (0x80UL)                  /*!< PA PA_BCR: BCR7 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR6_Pos                (6UL)                     /*!< PA PA_BCR: BCR6 (Bit 6)                               */
+#define PA_PA_BCR_BCR6_Msk                (0x40UL)                  /*!< PA PA_BCR: BCR6 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR5_Pos                (5UL)                     /*!< PA PA_BCR: BCR5 (Bit 5)                               */
+#define PA_PA_BCR_BCR5_Msk                (0x20UL)                  /*!< PA PA_BCR: BCR5 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR4_Pos                (4UL)                     /*!< PA PA_BCR: BCR4 (Bit 4)                               */
+#define PA_PA_BCR_BCR4_Msk                (0x10UL)                  /*!< PA PA_BCR: BCR4 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR3_Pos                (3UL)                     /*!< PA PA_BCR: BCR3 (Bit 3)                               */
+#define PA_PA_BCR_BCR3_Msk                (0x8UL)                   /*!< PA PA_BCR: BCR3 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR2_Pos                (2UL)                     /*!< PA PA_BCR: BCR2 (Bit 2)                               */
+#define PA_PA_BCR_BCR2_Msk                (0x4UL)                   /*!< PA PA_BCR: BCR2 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR1_Pos                (1UL)                     /*!< PA PA_BCR: BCR1 (Bit 1)                               */
+#define PA_PA_BCR_BCR1_Msk                (0x2UL)                   /*!< PA PA_BCR: BCR1 (Bitfield-Mask: 0x01)                 */
+#define PA_PA_BCR_BCR0_Pos                (0UL)                     /*!< PA PA_BCR: BCR0 (Bit 0)                               */
+#define PA_PA_BCR_BCR0_Msk                (0x1UL)                   /*!< PA PA_BCR: BCR0 (Bitfield-Mask: 0x01)                 */
+/* ======================================================  PA_OUTDMSK  ======================================================= */
+#define PA_PA_OUTDMSK_OUTDMSK11_Pos       (11UL)                    /*!< PA PA_OUTDMSK: OUTDMSK11 (Bit 11)                     */
+#define PA_PA_OUTDMSK_OUTDMSK11_Msk       (0x800UL)                 /*!< PA PA_OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)        */
+#define PA_PA_OUTDMSK_OUTDMSK10_Pos       (10UL)                    /*!< PA PA_OUTDMSK: OUTDMSK10 (Bit 10)                     */
+#define PA_PA_OUTDMSK_OUTDMSK10_Msk       (0x400UL)                 /*!< PA PA_OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)        */
+#define PA_PA_OUTDMSK_OUTDMSK9_Pos        (9UL)                     /*!< PA PA_OUTDMSK: OUTDMSK9 (Bit 9)                       */
+#define PA_PA_OUTDMSK_OUTDMSK9_Msk        (0x200UL)                 /*!< PA PA_OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK8_Pos        (8UL)                     /*!< PA PA_OUTDMSK: OUTDMSK8 (Bit 8)                       */
+#define PA_PA_OUTDMSK_OUTDMSK8_Msk        (0x100UL)                 /*!< PA PA_OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK7_Pos        (7UL)                     /*!< PA PA_OUTDMSK: OUTDMSK7 (Bit 7)                       */
+#define PA_PA_OUTDMSK_OUTDMSK7_Msk        (0x80UL)                  /*!< PA PA_OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK6_Pos        (6UL)                     /*!< PA PA_OUTDMSK: OUTDMSK6 (Bit 6)                       */
+#define PA_PA_OUTDMSK_OUTDMSK6_Msk        (0x40UL)                  /*!< PA PA_OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK5_Pos        (5UL)                     /*!< PA PA_OUTDMSK: OUTDMSK5 (Bit 5)                       */
+#define PA_PA_OUTDMSK_OUTDMSK5_Msk        (0x20UL)                  /*!< PA PA_OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK4_Pos        (4UL)                     /*!< PA PA_OUTDMSK: OUTDMSK4 (Bit 4)                       */
+#define PA_PA_OUTDMSK_OUTDMSK4_Msk        (0x10UL)                  /*!< PA PA_OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK3_Pos        (3UL)                     /*!< PA PA_OUTDMSK: OUTDMSK3 (Bit 3)                       */
+#define PA_PA_OUTDMSK_OUTDMSK3_Msk        (0x8UL)                   /*!< PA PA_OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK2_Pos        (2UL)                     /*!< PA PA_OUTDMSK: OUTDMSK2 (Bit 2)                       */
+#define PA_PA_OUTDMSK_OUTDMSK2_Msk        (0x4UL)                   /*!< PA PA_OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK1_Pos        (1UL)                     /*!< PA PA_OUTDMSK: OUTDMSK1 (Bit 1)                       */
+#define PA_PA_OUTDMSK_OUTDMSK1_Msk        (0x2UL)                   /*!< PA PA_OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)         */
+#define PA_PA_OUTDMSK_OUTDMSK0_Pos        (0UL)                     /*!< PA PA_OUTDMSK: OUTDMSK0 (Bit 0)                       */
+#define PA_PA_OUTDMSK_OUTDMSK0_Msk        (0x1UL)                   /*!< PA PA_OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)         */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PB                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+#define PB_MOD_MODE15_Pos                 (30UL)                    /*!< PB MOD: MODE15 (Bit 30)                               */
+#define PB_MOD_MODE15_Msk                 (0xc0000000UL)            /*!< PB MOD: MODE15 (Bitfield-Mask: 0x03)                  */
+#define PB_MOD_MODE14_Pos                 (28UL)                    /*!< PB MOD: MODE14 (Bit 28)                               */
+#define PB_MOD_MODE14_Msk                 (0x30000000UL)            /*!< PB MOD: MODE14 (Bitfield-Mask: 0x03)                  */
+#define PB_MOD_MODE13_Pos                 (26UL)                    /*!< PB MOD: MODE13 (Bit 26)                               */
+#define PB_MOD_MODE13_Msk                 (0xc000000UL)             /*!< PB MOD: MODE13 (Bitfield-Mask: 0x03)                  */
+#define PB_MOD_MODE12_Pos                 (24UL)                    /*!< PB MOD: MODE12 (Bit 24)                               */
+#define PB_MOD_MODE12_Msk                 (0x3000000UL)             /*!< PB MOD: MODE12 (Bitfield-Mask: 0x03)                  */
+#define PB_MOD_MODE11_Pos                 (22UL)                    /*!< PB MOD: MODE11 (Bit 22)                               */
+#define PB_MOD_MODE11_Msk                 (0xc00000UL)              /*!< PB MOD: MODE11 (Bitfield-Mask: 0x03)                  */
+#define PB_MOD_MODE10_Pos                 (20UL)                    /*!< PB MOD: MODE10 (Bit 20)                               */
+#define PB_MOD_MODE10_Msk                 (0x300000UL)              /*!< PB MOD: MODE10 (Bitfield-Mask: 0x03)                  */
+#define PB_MOD_MODE9_Pos                  (18UL)                    /*!< PB MOD: MODE9 (Bit 18)                                */
+#define PB_MOD_MODE9_Msk                  (0xc0000UL)               /*!< PB MOD: MODE9 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE8_Pos                  (16UL)                    /*!< PB MOD: MODE8 (Bit 16)                                */
+#define PB_MOD_MODE8_Msk                  (0x30000UL)               /*!< PB MOD: MODE8 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE7_Pos                  (14UL)                    /*!< PB MOD: MODE7 (Bit 14)                                */
+#define PB_MOD_MODE7_Msk                  (0xc000UL)                /*!< PB MOD: MODE7 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE6_Pos                  (12UL)                    /*!< PB MOD: MODE6 (Bit 12)                                */
+#define PB_MOD_MODE6_Msk                  (0x3000UL)                /*!< PB MOD: MODE6 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE5_Pos                  (10UL)                    /*!< PB MOD: MODE5 (Bit 10)                                */
+#define PB_MOD_MODE5_Msk                  (0xc00UL)                 /*!< PB MOD: MODE5 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE4_Pos                  (8UL)                     /*!< PB MOD: MODE4 (Bit 8)                                 */
+#define PB_MOD_MODE4_Msk                  (0x300UL)                 /*!< PB MOD: MODE4 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE3_Pos                  (6UL)                     /*!< PB MOD: MODE3 (Bit 6)                                 */
+#define PB_MOD_MODE3_Msk                  (0xc0UL)                  /*!< PB MOD: MODE3 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE2_Pos                  (4UL)                     /*!< PB MOD: MODE2 (Bit 4)                                 */
+#define PB_MOD_MODE2_Msk                  (0x30UL)                  /*!< PB MOD: MODE2 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE1_Pos                  (2UL)                     /*!< PB MOD: MODE1 (Bit 2)                                 */
+#define PB_MOD_MODE1_Msk                  (0xcUL)                   /*!< PB MOD: MODE1 (Bitfield-Mask: 0x03)                   */
+#define PB_MOD_MODE0_Pos                  (0UL)                     /*!< PB MOD: MODE0 (Bit 0)                                 */
+#define PB_MOD_MODE0_Msk                  (0x3UL)                   /*!< PB MOD: MODE0 (Bitfield-Mask: 0x03)                   */
+/* ==========================================================  TYP  ========================================================== */
+#define PB_TYP_TYP15_Pos                  (15UL)                    /*!< PB TYP: TYP15 (Bit 15)                                */
+#define PB_TYP_TYP15_Msk                  (0x8000UL)                /*!< PB TYP: TYP15 (Bitfield-Mask: 0x01)                   */
+#define PB_TYP_TYP14_Pos                  (14UL)                    /*!< PB TYP: TYP14 (Bit 14)                                */
+#define PB_TYP_TYP14_Msk                  (0x4000UL)                /*!< PB TYP: TYP14 (Bitfield-Mask: 0x01)                   */
+#define PB_TYP_TYP13_Pos                  (13UL)                    /*!< PB TYP: TYP13 (Bit 13)                                */
+#define PB_TYP_TYP13_Msk                  (0x2000UL)                /*!< PB TYP: TYP13 (Bitfield-Mask: 0x01)                   */
+#define PB_TYP_TYP12_Pos                  (12UL)                    /*!< PB TYP: TYP12 (Bit 12)                                */
+#define PB_TYP_TYP12_Msk                  (0x1000UL)                /*!< PB TYP: TYP12 (Bitfield-Mask: 0x01)                   */
+#define PB_TYP_TYP11_Pos                  (11UL)                    /*!< PB TYP: TYP11 (Bit 11)                                */
+#define PB_TYP_TYP11_Msk                  (0x800UL)                 /*!< PB TYP: TYP11 (Bitfield-Mask: 0x01)                   */
+#define PB_TYP_TYP10_Pos                  (10UL)                    /*!< PB TYP: TYP10 (Bit 10)                                */
+#define PB_TYP_TYP10_Msk                  (0x400UL)                 /*!< PB TYP: TYP10 (Bitfield-Mask: 0x01)                   */
+#define PB_TYP_TYP9_Pos                   (9UL)                     /*!< PB TYP: TYP9 (Bit 9)                                  */
+#define PB_TYP_TYP9_Msk                   (0x200UL)                 /*!< PB TYP: TYP9 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP8_Pos                   (8UL)                     /*!< PB TYP: TYP8 (Bit 8)                                  */
+#define PB_TYP_TYP8_Msk                   (0x100UL)                 /*!< PB TYP: TYP8 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP7_Pos                   (7UL)                     /*!< PB TYP: TYP7 (Bit 7)                                  */
+#define PB_TYP_TYP7_Msk                   (0x80UL)                  /*!< PB TYP: TYP7 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP6_Pos                   (6UL)                     /*!< PB TYP: TYP6 (Bit 6)                                  */
+#define PB_TYP_TYP6_Msk                   (0x40UL)                  /*!< PB TYP: TYP6 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP5_Pos                   (5UL)                     /*!< PB TYP: TYP5 (Bit 5)                                  */
+#define PB_TYP_TYP5_Msk                   (0x20UL)                  /*!< PB TYP: TYP5 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP4_Pos                   (4UL)                     /*!< PB TYP: TYP4 (Bit 4)                                  */
+#define PB_TYP_TYP4_Msk                   (0x10UL)                  /*!< PB TYP: TYP4 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP3_Pos                   (3UL)                     /*!< PB TYP: TYP3 (Bit 3)                                  */
+#define PB_TYP_TYP3_Msk                   (0x8UL)                   /*!< PB TYP: TYP3 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP2_Pos                   (2UL)                     /*!< PB TYP: TYP2 (Bit 2)                                  */
+#define PB_TYP_TYP2_Msk                   (0x4UL)                   /*!< PB TYP: TYP2 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP1_Pos                   (1UL)                     /*!< PB TYP: TYP1 (Bit 1)                                  */
+#define PB_TYP_TYP1_Msk                   (0x2UL)                   /*!< PB TYP: TYP1 (Bitfield-Mask: 0x01)                    */
+#define PB_TYP_TYP0_Pos                   (0UL)                     /*!< PB TYP: TYP0 (Bit 0)                                  */
+#define PB_TYP_TYP0_Msk                   (0x1UL)                   /*!< PB TYP: TYP0 (Bitfield-Mask: 0x01)                    */
+/* =========================================================  AFSR1  ========================================================= */
+#define PB_AFSR1_AFSR7_Pos                (28UL)                    /*!< PB AFSR1: AFSR7 (Bit 28)                              */
+#define PB_AFSR1_AFSR7_Msk                (0xf0000000UL)            /*!< PB AFSR1: AFSR7 (Bitfield-Mask: 0x0f)                 */
+#define PB_AFSR1_AFSR6_Pos                (24UL)                    /*!< PB AFSR1: AFSR6 (Bit 24)                              */
+#define PB_AFSR1_AFSR6_Msk                (0xf000000UL)             /*!< PB AFSR1: AFSR6 (Bitfield-Mask: 0x0f)                 */
+#define PB_AFSR1_AFSR5_Pos                (20UL)                    /*!< PB AFSR1: AFSR5 (Bit 20)                              */
+#define PB_AFSR1_AFSR5_Msk                (0xf00000UL)              /*!< PB AFSR1: AFSR5 (Bitfield-Mask: 0x0f)                 */
+#define PB_AFSR1_AFSR4_Pos                (16UL)                    /*!< PB AFSR1: AFSR4 (Bit 16)                              */
+#define PB_AFSR1_AFSR4_Msk                (0xf0000UL)               /*!< PB AFSR1: AFSR4 (Bitfield-Mask: 0x0f)                 */
+#define PB_AFSR1_AFSR3_Pos                (12UL)                    /*!< PB AFSR1: AFSR3 (Bit 12)                              */
+#define PB_AFSR1_AFSR3_Msk                (0xf000UL)                /*!< PB AFSR1: AFSR3 (Bitfield-Mask: 0x0f)                 */
+#define PB_AFSR1_AFSR2_Pos                (8UL)                     /*!< PB AFSR1: AFSR2 (Bit 8)                               */
+#define PB_AFSR1_AFSR2_Msk                (0xf00UL)                 /*!< PB AFSR1: AFSR2 (Bitfield-Mask: 0x0f)                 */
+#define PB_AFSR1_AFSR1_Pos                (4UL)                     /*!< PB AFSR1: AFSR1 (Bit 4)                               */
+#define PB_AFSR1_AFSR1_Msk                (0xf0UL)                  /*!< PB AFSR1: AFSR1 (Bitfield-Mask: 0x0f)                 */
+#define PB_AFSR1_AFSR0_Pos                (0UL)                     /*!< PB AFSR1: AFSR0 (Bit 0)                               */
+#define PB_AFSR1_AFSR0_Msk                (0xfUL)                   /*!< PB AFSR1: AFSR0 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  AFSR2  ========================================================= */
+#define PB_AFSR2_AFSR15_Pos               (28UL)                    /*!< PB AFSR2: AFSR15 (Bit 28)                             */
+#define PB_AFSR2_AFSR15_Msk               (0xf0000000UL)            /*!< PB AFSR2: AFSR15 (Bitfield-Mask: 0x0f)                */
+#define PB_AFSR2_AFSR14_Pos               (24UL)                    /*!< PB AFSR2: AFSR14 (Bit 24)                             */
+#define PB_AFSR2_AFSR14_Msk               (0xf000000UL)             /*!< PB AFSR2: AFSR14 (Bitfield-Mask: 0x0f)                */
+#define PB_AFSR2_AFSR13_Pos               (20UL)                    /*!< PB AFSR2: AFSR13 (Bit 20)                             */
+#define PB_AFSR2_AFSR13_Msk               (0xf00000UL)              /*!< PB AFSR2: AFSR13 (Bitfield-Mask: 0x0f)                */
+#define PB_AFSR2_AFSR12_Pos               (16UL)                    /*!< PB AFSR2: AFSR12 (Bit 16)                             */
+#define PB_AFSR2_AFSR12_Msk               (0xf0000UL)               /*!< PB AFSR2: AFSR12 (Bitfield-Mask: 0x0f)                */
+#define PB_AFSR2_AFSR11_Pos               (12UL)                    /*!< PB AFSR2: AFSR11 (Bit 12)                             */
+#define PB_AFSR2_AFSR11_Msk               (0xf000UL)                /*!< PB AFSR2: AFSR11 (Bitfield-Mask: 0x0f)                */
+#define PB_AFSR2_AFSR10_Pos               (8UL)                     /*!< PB AFSR2: AFSR10 (Bit 8)                              */
+#define PB_AFSR2_AFSR10_Msk               (0xf00UL)                 /*!< PB AFSR2: AFSR10 (Bitfield-Mask: 0x0f)                */
+#define PB_AFSR2_AFSR9_Pos                (4UL)                     /*!< PB AFSR2: AFSR9 (Bit 4)                               */
+#define PB_AFSR2_AFSR9_Msk                (0xf0UL)                  /*!< PB AFSR2: AFSR9 (Bitfield-Mask: 0x0f)                 */
+#define PB_AFSR2_AFSR8_Pos                (0UL)                     /*!< PB AFSR2: AFSR8 (Bit 0)                               */
+#define PB_AFSR2_AFSR8_Msk                (0xfUL)                   /*!< PB AFSR2: AFSR8 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  PUPD  ========================================================== */
+#define PB_PUPD_PUPD15_Pos                (30UL)                    /*!< PB PUPD: PUPD15 (Bit 30)                              */
+#define PB_PUPD_PUPD15_Msk                (0xc0000000UL)            /*!< PB PUPD: PUPD15 (Bitfield-Mask: 0x03)                 */
+#define PB_PUPD_PUPD14_Pos                (28UL)                    /*!< PB PUPD: PUPD14 (Bit 28)                              */
+#define PB_PUPD_PUPD14_Msk                (0x30000000UL)            /*!< PB PUPD: PUPD14 (Bitfield-Mask: 0x03)                 */
+#define PB_PUPD_PUPD13_Pos                (26UL)                    /*!< PB PUPD: PUPD13 (Bit 26)                              */
+#define PB_PUPD_PUPD13_Msk                (0xc000000UL)             /*!< PB PUPD: PUPD13 (Bitfield-Mask: 0x03)                 */
+#define PB_PUPD_PUPD12_Pos                (24UL)                    /*!< PB PUPD: PUPD12 (Bit 24)                              */
+#define PB_PUPD_PUPD12_Msk                (0x3000000UL)             /*!< PB PUPD: PUPD12 (Bitfield-Mask: 0x03)                 */
+#define PB_PUPD_PUPD11_Pos                (22UL)                    /*!< PB PUPD: PUPD11 (Bit 22)                              */
+#define PB_PUPD_PUPD11_Msk                (0xc00000UL)              /*!< PB PUPD: PUPD11 (Bitfield-Mask: 0x03)                 */
+#define PB_PUPD_PUPD10_Pos                (20UL)                    /*!< PB PUPD: PUPD10 (Bit 20)                              */
+#define PB_PUPD_PUPD10_Msk                (0x300000UL)              /*!< PB PUPD: PUPD10 (Bitfield-Mask: 0x03)                 */
+#define PB_PUPD_PUPD9_Pos                 (18UL)                    /*!< PB PUPD: PUPD9 (Bit 18)                               */
+#define PB_PUPD_PUPD9_Msk                 (0xc0000UL)               /*!< PB PUPD: PUPD9 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD8_Pos                 (16UL)                    /*!< PB PUPD: PUPD8 (Bit 16)                               */
+#define PB_PUPD_PUPD8_Msk                 (0x30000UL)               /*!< PB PUPD: PUPD8 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD7_Pos                 (14UL)                    /*!< PB PUPD: PUPD7 (Bit 14)                               */
+#define PB_PUPD_PUPD7_Msk                 (0xc000UL)                /*!< PB PUPD: PUPD7 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD6_Pos                 (12UL)                    /*!< PB PUPD: PUPD6 (Bit 12)                               */
+#define PB_PUPD_PUPD6_Msk                 (0x3000UL)                /*!< PB PUPD: PUPD6 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD5_Pos                 (10UL)                    /*!< PB PUPD: PUPD5 (Bit 10)                               */
+#define PB_PUPD_PUPD5_Msk                 (0xc00UL)                 /*!< PB PUPD: PUPD5 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD4_Pos                 (8UL)                     /*!< PB PUPD: PUPD4 (Bit 8)                                */
+#define PB_PUPD_PUPD4_Msk                 (0x300UL)                 /*!< PB PUPD: PUPD4 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD3_Pos                 (6UL)                     /*!< PB PUPD: PUPD3 (Bit 6)                                */
+#define PB_PUPD_PUPD3_Msk                 (0xc0UL)                  /*!< PB PUPD: PUPD3 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD2_Pos                 (4UL)                     /*!< PB PUPD: PUPD2 (Bit 4)                                */
+#define PB_PUPD_PUPD2_Msk                 (0x30UL)                  /*!< PB PUPD: PUPD2 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD1_Pos                 (2UL)                     /*!< PB PUPD: PUPD1 (Bit 2)                                */
+#define PB_PUPD_PUPD1_Msk                 (0xcUL)                   /*!< PB PUPD: PUPD1 (Bitfield-Mask: 0x03)                  */
+#define PB_PUPD_PUPD0_Pos                 (0UL)                     /*!< PB PUPD: PUPD0 (Bit 0)                                */
+#define PB_PUPD_PUPD0_Msk                 (0x3UL)                   /*!< PB PUPD: PUPD0 (Bitfield-Mask: 0x03)                  */
+/* =========================================================  INDR  ========================================================== */
+#define PB_INDR_INDR15_Pos                (15UL)                    /*!< PB INDR: INDR15 (Bit 15)                              */
+#define PB_INDR_INDR15_Msk                (0x8000UL)                /*!< PB INDR: INDR15 (Bitfield-Mask: 0x01)                 */
+#define PB_INDR_INDR14_Pos                (14UL)                    /*!< PB INDR: INDR14 (Bit 14)                              */
+#define PB_INDR_INDR14_Msk                (0x4000UL)                /*!< PB INDR: INDR14 (Bitfield-Mask: 0x01)                 */
+#define PB_INDR_INDR13_Pos                (13UL)                    /*!< PB INDR: INDR13 (Bit 13)                              */
+#define PB_INDR_INDR13_Msk                (0x2000UL)                /*!< PB INDR: INDR13 (Bitfield-Mask: 0x01)                 */
+#define PB_INDR_INDR12_Pos                (12UL)                    /*!< PB INDR: INDR12 (Bit 12)                              */
+#define PB_INDR_INDR12_Msk                (0x1000UL)                /*!< PB INDR: INDR12 (Bitfield-Mask: 0x01)                 */
+#define PB_INDR_INDR11_Pos                (11UL)                    /*!< PB INDR: INDR11 (Bit 11)                              */
+#define PB_INDR_INDR11_Msk                (0x800UL)                 /*!< PB INDR: INDR11 (Bitfield-Mask: 0x01)                 */
+#define PB_INDR_INDR10_Pos                (10UL)                    /*!< PB INDR: INDR10 (Bit 10)                              */
+#define PB_INDR_INDR10_Msk                (0x400UL)                 /*!< PB INDR: INDR10 (Bitfield-Mask: 0x01)                 */
+#define PB_INDR_INDR9_Pos                 (9UL)                     /*!< PB INDR: INDR9 (Bit 9)                                */
+#define PB_INDR_INDR9_Msk                 (0x200UL)                 /*!< PB INDR: INDR9 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR8_Pos                 (8UL)                     /*!< PB INDR: INDR8 (Bit 8)                                */
+#define PB_INDR_INDR8_Msk                 (0x100UL)                 /*!< PB INDR: INDR8 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR7_Pos                 (7UL)                     /*!< PB INDR: INDR7 (Bit 7)                                */
+#define PB_INDR_INDR7_Msk                 (0x80UL)                  /*!< PB INDR: INDR7 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR6_Pos                 (6UL)                     /*!< PB INDR: INDR6 (Bit 6)                                */
+#define PB_INDR_INDR6_Msk                 (0x40UL)                  /*!< PB INDR: INDR6 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR5_Pos                 (5UL)                     /*!< PB INDR: INDR5 (Bit 5)                                */
+#define PB_INDR_INDR5_Msk                 (0x20UL)                  /*!< PB INDR: INDR5 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR4_Pos                 (4UL)                     /*!< PB INDR: INDR4 (Bit 4)                                */
+#define PB_INDR_INDR4_Msk                 (0x10UL)                  /*!< PB INDR: INDR4 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR3_Pos                 (3UL)                     /*!< PB INDR: INDR3 (Bit 3)                                */
+#define PB_INDR_INDR3_Msk                 (0x8UL)                   /*!< PB INDR: INDR3 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR2_Pos                 (2UL)                     /*!< PB INDR: INDR2 (Bit 2)                                */
+#define PB_INDR_INDR2_Msk                 (0x4UL)                   /*!< PB INDR: INDR2 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR1_Pos                 (1UL)                     /*!< PB INDR: INDR1 (Bit 1)                                */
+#define PB_INDR_INDR1_Msk                 (0x2UL)                   /*!< PB INDR: INDR1 (Bitfield-Mask: 0x01)                  */
+#define PB_INDR_INDR0_Pos                 (0UL)                     /*!< PB INDR: INDR0 (Bit 0)                                */
+#define PB_INDR_INDR0_Msk                 (0x1UL)                   /*!< PB INDR: INDR0 (Bitfield-Mask: 0x01)                  */
+/* =========================================================  OUTDR  ========================================================= */
+#define PB_OUTDR_OUTDR15_Pos              (15UL)                    /*!< PB OUTDR: OUTDR15 (Bit 15)                            */
+#define PB_OUTDR_OUTDR15_Msk              (0x8000UL)                /*!< PB OUTDR: OUTDR15 (Bitfield-Mask: 0x01)               */
+#define PB_OUTDR_OUTDR14_Pos              (14UL)                    /*!< PB OUTDR: OUTDR14 (Bit 14)                            */
+#define PB_OUTDR_OUTDR14_Msk              (0x4000UL)                /*!< PB OUTDR: OUTDR14 (Bitfield-Mask: 0x01)               */
+#define PB_OUTDR_OUTDR13_Pos              (13UL)                    /*!< PB OUTDR: OUTDR13 (Bit 13)                            */
+#define PB_OUTDR_OUTDR13_Msk              (0x2000UL)                /*!< PB OUTDR: OUTDR13 (Bitfield-Mask: 0x01)               */
+#define PB_OUTDR_OUTDR12_Pos              (12UL)                    /*!< PB OUTDR: OUTDR12 (Bit 12)                            */
+#define PB_OUTDR_OUTDR12_Msk              (0x1000UL)                /*!< PB OUTDR: OUTDR12 (Bitfield-Mask: 0x01)               */
+#define PB_OUTDR_OUTDR11_Pos              (11UL)                    /*!< PB OUTDR: OUTDR11 (Bit 11)                            */
+#define PB_OUTDR_OUTDR11_Msk              (0x800UL)                 /*!< PB OUTDR: OUTDR11 (Bitfield-Mask: 0x01)               */
+#define PB_OUTDR_OUTDR10_Pos              (10UL)                    /*!< PB OUTDR: OUTDR10 (Bit 10)                            */
+#define PB_OUTDR_OUTDR10_Msk              (0x400UL)                 /*!< PB OUTDR: OUTDR10 (Bitfield-Mask: 0x01)               */
+#define PB_OUTDR_OUTDR9_Pos               (9UL)                     /*!< PB OUTDR: OUTDR9 (Bit 9)                              */
+#define PB_OUTDR_OUTDR9_Msk               (0x200UL)                 /*!< PB OUTDR: OUTDR9 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR8_Pos               (8UL)                     /*!< PB OUTDR: OUTDR8 (Bit 8)                              */
+#define PB_OUTDR_OUTDR8_Msk               (0x100UL)                 /*!< PB OUTDR: OUTDR8 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR7_Pos               (7UL)                     /*!< PB OUTDR: OUTDR7 (Bit 7)                              */
+#define PB_OUTDR_OUTDR7_Msk               (0x80UL)                  /*!< PB OUTDR: OUTDR7 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR6_Pos               (6UL)                     /*!< PB OUTDR: OUTDR6 (Bit 6)                              */
+#define PB_OUTDR_OUTDR6_Msk               (0x40UL)                  /*!< PB OUTDR: OUTDR6 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR5_Pos               (5UL)                     /*!< PB OUTDR: OUTDR5 (Bit 5)                              */
+#define PB_OUTDR_OUTDR5_Msk               (0x20UL)                  /*!< PB OUTDR: OUTDR5 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR4_Pos               (4UL)                     /*!< PB OUTDR: OUTDR4 (Bit 4)                              */
+#define PB_OUTDR_OUTDR4_Msk               (0x10UL)                  /*!< PB OUTDR: OUTDR4 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR3_Pos               (3UL)                     /*!< PB OUTDR: OUTDR3 (Bit 3)                              */
+#define PB_OUTDR_OUTDR3_Msk               (0x8UL)                   /*!< PB OUTDR: OUTDR3 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR2_Pos               (2UL)                     /*!< PB OUTDR: OUTDR2 (Bit 2)                              */
+#define PB_OUTDR_OUTDR2_Msk               (0x4UL)                   /*!< PB OUTDR: OUTDR2 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR1_Pos               (1UL)                     /*!< PB OUTDR: OUTDR1 (Bit 1)                              */
+#define PB_OUTDR_OUTDR1_Msk               (0x2UL)                   /*!< PB OUTDR: OUTDR1 (Bitfield-Mask: 0x01)                */
+#define PB_OUTDR_OUTDR0_Pos               (0UL)                     /*!< PB OUTDR: OUTDR0 (Bit 0)                              */
+#define PB_OUTDR_OUTDR0_Msk               (0x1UL)                   /*!< PB OUTDR: OUTDR0 (Bitfield-Mask: 0x01)                */
+/* ==========================================================  BSR  ========================================================== */
+#define PB_BSR_BSR15_Pos                  (15UL)                    /*!< PB BSR: BSR15 (Bit 15)                                */
+#define PB_BSR_BSR15_Msk                  (0x8000UL)                /*!< PB BSR: BSR15 (Bitfield-Mask: 0x01)                   */
+#define PB_BSR_BSR14_Pos                  (14UL)                    /*!< PB BSR: BSR14 (Bit 14)                                */
+#define PB_BSR_BSR14_Msk                  (0x4000UL)                /*!< PB BSR: BSR14 (Bitfield-Mask: 0x01)                   */
+#define PB_BSR_BSR13_Pos                  (13UL)                    /*!< PB BSR: BSR13 (Bit 13)                                */
+#define PB_BSR_BSR13_Msk                  (0x2000UL)                /*!< PB BSR: BSR13 (Bitfield-Mask: 0x01)                   */
+#define PB_BSR_BSR12_Pos                  (12UL)                    /*!< PB BSR: BSR12 (Bit 12)                                */
+#define PB_BSR_BSR12_Msk                  (0x1000UL)                /*!< PB BSR: BSR12 (Bitfield-Mask: 0x01)                   */
+#define PB_BSR_BSR11_Pos                  (11UL)                    /*!< PB BSR: BSR11 (Bit 11)                                */
+#define PB_BSR_BSR11_Msk                  (0x800UL)                 /*!< PB BSR: BSR11 (Bitfield-Mask: 0x01)                   */
+#define PB_BSR_BSR10_Pos                  (10UL)                    /*!< PB BSR: BSR10 (Bit 10)                                */
+#define PB_BSR_BSR10_Msk                  (0x400UL)                 /*!< PB BSR: BSR10 (Bitfield-Mask: 0x01)                   */
+#define PB_BSR_BSR9_Pos                   (9UL)                     /*!< PB BSR: BSR9 (Bit 9)                                  */
+#define PB_BSR_BSR9_Msk                   (0x200UL)                 /*!< PB BSR: BSR9 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR8_Pos                   (8UL)                     /*!< PB BSR: BSR8 (Bit 8)                                  */
+#define PB_BSR_BSR8_Msk                   (0x100UL)                 /*!< PB BSR: BSR8 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR7_Pos                   (7UL)                     /*!< PB BSR: BSR7 (Bit 7)                                  */
+#define PB_BSR_BSR7_Msk                   (0x80UL)                  /*!< PB BSR: BSR7 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR6_Pos                   (6UL)                     /*!< PB BSR: BSR6 (Bit 6)                                  */
+#define PB_BSR_BSR6_Msk                   (0x40UL)                  /*!< PB BSR: BSR6 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR5_Pos                   (5UL)                     /*!< PB BSR: BSR5 (Bit 5)                                  */
+#define PB_BSR_BSR5_Msk                   (0x20UL)                  /*!< PB BSR: BSR5 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR4_Pos                   (4UL)                     /*!< PB BSR: BSR4 (Bit 4)                                  */
+#define PB_BSR_BSR4_Msk                   (0x10UL)                  /*!< PB BSR: BSR4 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR3_Pos                   (3UL)                     /*!< PB BSR: BSR3 (Bit 3)                                  */
+#define PB_BSR_BSR3_Msk                   (0x8UL)                   /*!< PB BSR: BSR3 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR2_Pos                   (2UL)                     /*!< PB BSR: BSR2 (Bit 2)                                  */
+#define PB_BSR_BSR2_Msk                   (0x4UL)                   /*!< PB BSR: BSR2 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR1_Pos                   (1UL)                     /*!< PB BSR: BSR1 (Bit 1)                                  */
+#define PB_BSR_BSR1_Msk                   (0x2UL)                   /*!< PB BSR: BSR1 (Bitfield-Mask: 0x01)                    */
+#define PB_BSR_BSR0_Pos                   (0UL)                     /*!< PB BSR: BSR0 (Bit 0)                                  */
+#define PB_BSR_BSR0_Msk                   (0x1UL)                   /*!< PB BSR: BSR0 (Bitfield-Mask: 0x01)                    */
+/* ==========================================================  BCR  ========================================================== */
+#define PB_BCR_BCR15_Pos                  (15UL)                    /*!< PB BCR: BCR15 (Bit 15)                                */
+#define PB_BCR_BCR15_Msk                  (0x8000UL)                /*!< PB BCR: BCR15 (Bitfield-Mask: 0x01)                   */
+#define PB_BCR_BCR14_Pos                  (14UL)                    /*!< PB BCR: BCR14 (Bit 14)                                */
+#define PB_BCR_BCR14_Msk                  (0x4000UL)                /*!< PB BCR: BCR14 (Bitfield-Mask: 0x01)                   */
+#define PB_BCR_BCR13_Pos                  (13UL)                    /*!< PB BCR: BCR13 (Bit 13)                                */
+#define PB_BCR_BCR13_Msk                  (0x2000UL)                /*!< PB BCR: BCR13 (Bitfield-Mask: 0x01)                   */
+#define PB_BCR_BCR12_Pos                  (12UL)                    /*!< PB BCR: BCR12 (Bit 12)                                */
+#define PB_BCR_BCR12_Msk                  (0x1000UL)                /*!< PB BCR: BCR12 (Bitfield-Mask: 0x01)                   */
+#define PB_BCR_BCR11_Pos                  (11UL)                    /*!< PB BCR: BCR11 (Bit 11)                                */
+#define PB_BCR_BCR11_Msk                  (0x800UL)                 /*!< PB BCR: BCR11 (Bitfield-Mask: 0x01)                   */
+#define PB_BCR_BCR10_Pos                  (10UL)                    /*!< PB BCR: BCR10 (Bit 10)                                */
+#define PB_BCR_BCR10_Msk                  (0x400UL)                 /*!< PB BCR: BCR10 (Bitfield-Mask: 0x01)                   */
+#define PB_BCR_BCR9_Pos                   (9UL)                     /*!< PB BCR: BCR9 (Bit 9)                                  */
+#define PB_BCR_BCR9_Msk                   (0x200UL)                 /*!< PB BCR: BCR9 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR8_Pos                   (8UL)                     /*!< PB BCR: BCR8 (Bit 8)                                  */
+#define PB_BCR_BCR8_Msk                   (0x100UL)                 /*!< PB BCR: BCR8 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR7_Pos                   (7UL)                     /*!< PB BCR: BCR7 (Bit 7)                                  */
+#define PB_BCR_BCR7_Msk                   (0x80UL)                  /*!< PB BCR: BCR7 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR6_Pos                   (6UL)                     /*!< PB BCR: BCR6 (Bit 6)                                  */
+#define PB_BCR_BCR6_Msk                   (0x40UL)                  /*!< PB BCR: BCR6 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR5_Pos                   (5UL)                     /*!< PB BCR: BCR5 (Bit 5)                                  */
+#define PB_BCR_BCR5_Msk                   (0x20UL)                  /*!< PB BCR: BCR5 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR4_Pos                   (4UL)                     /*!< PB BCR: BCR4 (Bit 4)                                  */
+#define PB_BCR_BCR4_Msk                   (0x10UL)                  /*!< PB BCR: BCR4 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR3_Pos                   (3UL)                     /*!< PB BCR: BCR3 (Bit 3)                                  */
+#define PB_BCR_BCR3_Msk                   (0x8UL)                   /*!< PB BCR: BCR3 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR2_Pos                   (2UL)                     /*!< PB BCR: BCR2 (Bit 2)                                  */
+#define PB_BCR_BCR2_Msk                   (0x4UL)                   /*!< PB BCR: BCR2 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR1_Pos                   (1UL)                     /*!< PB BCR: BCR1 (Bit 1)                                  */
+#define PB_BCR_BCR1_Msk                   (0x2UL)                   /*!< PB BCR: BCR1 (Bitfield-Mask: 0x01)                    */
+#define PB_BCR_BCR0_Pos                   (0UL)                     /*!< PB BCR: BCR0 (Bit 0)                                  */
+#define PB_BCR_BCR0_Msk                   (0x1UL)                   /*!< PB BCR: BCR0 (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OUTDMSK  ======================================================== */
+#define PB_OUTDMSK_OUTDMSK15_Pos          (15UL)                    /*!< PB OUTDMSK: OUTDMSK15 (Bit 15)                        */
+#define PB_OUTDMSK_OUTDMSK15_Msk          (0x8000UL)                /*!< PB OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)           */
+#define PB_OUTDMSK_OUTDMSK14_Pos          (14UL)                    /*!< PB OUTDMSK: OUTDMSK14 (Bit 14)                        */
+#define PB_OUTDMSK_OUTDMSK14_Msk          (0x4000UL)                /*!< PB OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)           */
+#define PB_OUTDMSK_OUTDMSK13_Pos          (13UL)                    /*!< PB OUTDMSK: OUTDMSK13 (Bit 13)                        */
+#define PB_OUTDMSK_OUTDMSK13_Msk          (0x2000UL)                /*!< PB OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)           */
+#define PB_OUTDMSK_OUTDMSK12_Pos          (12UL)                    /*!< PB OUTDMSK: OUTDMSK12 (Bit 12)                        */
+#define PB_OUTDMSK_OUTDMSK12_Msk          (0x1000UL)                /*!< PB OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)           */
+#define PB_OUTDMSK_OUTDMSK11_Pos          (11UL)                    /*!< PB OUTDMSK: OUTDMSK11 (Bit 11)                        */
+#define PB_OUTDMSK_OUTDMSK11_Msk          (0x800UL)                 /*!< PB OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)           */
+#define PB_OUTDMSK_OUTDMSK10_Pos          (10UL)                    /*!< PB OUTDMSK: OUTDMSK10 (Bit 10)                        */
+#define PB_OUTDMSK_OUTDMSK10_Msk          (0x400UL)                 /*!< PB OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)           */
+#define PB_OUTDMSK_OUTDMSK9_Pos           (9UL)                     /*!< PB OUTDMSK: OUTDMSK9 (Bit 9)                          */
+#define PB_OUTDMSK_OUTDMSK9_Msk           (0x200UL)                 /*!< PB OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK8_Pos           (8UL)                     /*!< PB OUTDMSK: OUTDMSK8 (Bit 8)                          */
+#define PB_OUTDMSK_OUTDMSK8_Msk           (0x100UL)                 /*!< PB OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK7_Pos           (7UL)                     /*!< PB OUTDMSK: OUTDMSK7 (Bit 7)                          */
+#define PB_OUTDMSK_OUTDMSK7_Msk           (0x80UL)                  /*!< PB OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK6_Pos           (6UL)                     /*!< PB OUTDMSK: OUTDMSK6 (Bit 6)                          */
+#define PB_OUTDMSK_OUTDMSK6_Msk           (0x40UL)                  /*!< PB OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK5_Pos           (5UL)                     /*!< PB OUTDMSK: OUTDMSK5 (Bit 5)                          */
+#define PB_OUTDMSK_OUTDMSK5_Msk           (0x20UL)                  /*!< PB OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK4_Pos           (4UL)                     /*!< PB OUTDMSK: OUTDMSK4 (Bit 4)                          */
+#define PB_OUTDMSK_OUTDMSK4_Msk           (0x10UL)                  /*!< PB OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK3_Pos           (3UL)                     /*!< PB OUTDMSK: OUTDMSK3 (Bit 3)                          */
+#define PB_OUTDMSK_OUTDMSK3_Msk           (0x8UL)                   /*!< PB OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK2_Pos           (2UL)                     /*!< PB OUTDMSK: OUTDMSK2 (Bit 2)                          */
+#define PB_OUTDMSK_OUTDMSK2_Msk           (0x4UL)                   /*!< PB OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK1_Pos           (1UL)                     /*!< PB OUTDMSK: OUTDMSK1 (Bit 1)                          */
+#define PB_OUTDMSK_OUTDMSK1_Msk           (0x2UL)                   /*!< PB OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)            */
+#define PB_OUTDMSK_OUTDMSK0_Pos           (0UL)                     /*!< PB OUTDMSK: OUTDMSK0 (Bit 0)                          */
+#define PB_OUTDMSK_OUTDMSK0_Msk           (0x1UL)                   /*!< PB OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)            */
+/* =========================================================  DBCR  ========================================================== */
+#define PB_DBCR_DBCLK_Pos                 (16UL)                    /*!< PB DBCR: DBCLK (Bit 16)                               */
+#define PB_DBCR_DBCLK_Msk                 (0x70000UL)               /*!< PB DBCR: DBCLK (Bitfield-Mask: 0x07)                  */
+#define PB_DBCR_DBEN11_Pos                (11UL)                    /*!< PB DBCR: DBEN11 (Bit 11)                              */
+#define PB_DBCR_DBEN11_Msk                (0x800UL)                 /*!< PB DBCR: DBEN11 (Bitfield-Mask: 0x01)                 */
+#define PB_DBCR_DBEN10_Pos                (10UL)                    /*!< PB DBCR: DBEN10 (Bit 10)                              */
+#define PB_DBCR_DBEN10_Msk                (0x400UL)                 /*!< PB DBCR: DBEN10 (Bitfield-Mask: 0x01)                 */
+#define PB_DBCR_DBEN9_Pos                 (9UL)                     /*!< PB DBCR: DBEN9 (Bit 9)                                */
+#define PB_DBCR_DBEN9_Msk                 (0x200UL)                 /*!< PB DBCR: DBEN9 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN8_Pos                 (8UL)                     /*!< PB DBCR: DBEN8 (Bit 8)                                */
+#define PB_DBCR_DBEN8_Msk                 (0x100UL)                 /*!< PB DBCR: DBEN8 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN7_Pos                 (7UL)                     /*!< PB DBCR: DBEN7 (Bit 7)                                */
+#define PB_DBCR_DBEN7_Msk                 (0x80UL)                  /*!< PB DBCR: DBEN7 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN6_Pos                 (6UL)                     /*!< PB DBCR: DBEN6 (Bit 6)                                */
+#define PB_DBCR_DBEN6_Msk                 (0x40UL)                  /*!< PB DBCR: DBEN6 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN5_Pos                 (5UL)                     /*!< PB DBCR: DBEN5 (Bit 5)                                */
+#define PB_DBCR_DBEN5_Msk                 (0x20UL)                  /*!< PB DBCR: DBEN5 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN4_Pos                 (4UL)                     /*!< PB DBCR: DBEN4 (Bit 4)                                */
+#define PB_DBCR_DBEN4_Msk                 (0x10UL)                  /*!< PB DBCR: DBEN4 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN3_Pos                 (3UL)                     /*!< PB DBCR: DBEN3 (Bit 3)                                */
+#define PB_DBCR_DBEN3_Msk                 (0x8UL)                   /*!< PB DBCR: DBEN3 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN2_Pos                 (2UL)                     /*!< PB DBCR: DBEN2 (Bit 2)                                */
+#define PB_DBCR_DBEN2_Msk                 (0x4UL)                   /*!< PB DBCR: DBEN2 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN1_Pos                 (1UL)                     /*!< PB DBCR: DBEN1 (Bit 1)                                */
+#define PB_DBCR_DBEN1_Msk                 (0x2UL)                   /*!< PB DBCR: DBEN1 (Bitfield-Mask: 0x01)                  */
+#define PB_DBCR_DBEN0_Pos                 (0UL)                     /*!< PB DBCR: DBEN0 (Bit 0)                                */
+#define PB_DBCR_DBEN0_Msk                 (0x1UL)                   /*!< PB DBCR: DBEN0 (Bitfield-Mask: 0x01)                  */
+/* ========================================================  PB_MOD  ========================================================= */
+#define PB_PB_MOD_MODE15_Pos              (30UL)                    /*!< PB PB_MOD: MODE15 (Bit 30)                            */
+#define PB_PB_MOD_MODE15_Msk              (0xc0000000UL)            /*!< PB PB_MOD: MODE15 (Bitfield-Mask: 0x03)               */
+#define PB_PB_MOD_MODE14_Pos              (28UL)                    /*!< PB PB_MOD: MODE14 (Bit 28)                            */
+#define PB_PB_MOD_MODE14_Msk              (0x30000000UL)            /*!< PB PB_MOD: MODE14 (Bitfield-Mask: 0x03)               */
+#define PB_PB_MOD_MODE13_Pos              (26UL)                    /*!< PB PB_MOD: MODE13 (Bit 26)                            */
+#define PB_PB_MOD_MODE13_Msk              (0xc000000UL)             /*!< PB PB_MOD: MODE13 (Bitfield-Mask: 0x03)               */
+#define PB_PB_MOD_MODE12_Pos              (24UL)                    /*!< PB PB_MOD: MODE12 (Bit 24)                            */
+#define PB_PB_MOD_MODE12_Msk              (0x3000000UL)             /*!< PB PB_MOD: MODE12 (Bitfield-Mask: 0x03)               */
+#define PB_PB_MOD_MODE11_Pos              (22UL)                    /*!< PB PB_MOD: MODE11 (Bit 22)                            */
+#define PB_PB_MOD_MODE11_Msk              (0xc00000UL)              /*!< PB PB_MOD: MODE11 (Bitfield-Mask: 0x03)               */
+#define PB_PB_MOD_MODE10_Pos              (20UL)                    /*!< PB PB_MOD: MODE10 (Bit 20)                            */
+#define PB_PB_MOD_MODE10_Msk              (0x300000UL)              /*!< PB PB_MOD: MODE10 (Bitfield-Mask: 0x03)               */
+#define PB_PB_MOD_MODE9_Pos               (18UL)                    /*!< PB PB_MOD: MODE9 (Bit 18)                             */
+#define PB_PB_MOD_MODE9_Msk               (0xc0000UL)               /*!< PB PB_MOD: MODE9 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE8_Pos               (16UL)                    /*!< PB PB_MOD: MODE8 (Bit 16)                             */
+#define PB_PB_MOD_MODE8_Msk               (0x30000UL)               /*!< PB PB_MOD: MODE8 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE7_Pos               (14UL)                    /*!< PB PB_MOD: MODE7 (Bit 14)                             */
+#define PB_PB_MOD_MODE7_Msk               (0xc000UL)                /*!< PB PB_MOD: MODE7 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE6_Pos               (12UL)                    /*!< PB PB_MOD: MODE6 (Bit 12)                             */
+#define PB_PB_MOD_MODE6_Msk               (0x3000UL)                /*!< PB PB_MOD: MODE6 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE5_Pos               (10UL)                    /*!< PB PB_MOD: MODE5 (Bit 10)                             */
+#define PB_PB_MOD_MODE5_Msk               (0xc00UL)                 /*!< PB PB_MOD: MODE5 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE4_Pos               (8UL)                     /*!< PB PB_MOD: MODE4 (Bit 8)                              */
+#define PB_PB_MOD_MODE4_Msk               (0x300UL)                 /*!< PB PB_MOD: MODE4 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE3_Pos               (6UL)                     /*!< PB PB_MOD: MODE3 (Bit 6)                              */
+#define PB_PB_MOD_MODE3_Msk               (0xc0UL)                  /*!< PB PB_MOD: MODE3 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE2_Pos               (4UL)                     /*!< PB PB_MOD: MODE2 (Bit 4)                              */
+#define PB_PB_MOD_MODE2_Msk               (0x30UL)                  /*!< PB PB_MOD: MODE2 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE1_Pos               (2UL)                     /*!< PB PB_MOD: MODE1 (Bit 2)                              */
+#define PB_PB_MOD_MODE1_Msk               (0xcUL)                   /*!< PB PB_MOD: MODE1 (Bitfield-Mask: 0x03)                */
+#define PB_PB_MOD_MODE0_Pos               (0UL)                     /*!< PB PB_MOD: MODE0 (Bit 0)                              */
+#define PB_PB_MOD_MODE0_Msk               (0x3UL)                   /*!< PB PB_MOD: MODE0 (Bitfield-Mask: 0x03)                */
+/* ========================================================  PB_TYP  ========================================================= */
+#define PB_PB_TYP_TYP15_Pos               (15UL)                    /*!< PB PB_TYP: TYP15 (Bit 15)                             */
+#define PB_PB_TYP_TYP15_Msk               (0x8000UL)                /*!< PB PB_TYP: TYP15 (Bitfield-Mask: 0x01)                */
+#define PB_PB_TYP_TYP14_Pos               (14UL)                    /*!< PB PB_TYP: TYP14 (Bit 14)                             */
+#define PB_PB_TYP_TYP14_Msk               (0x4000UL)                /*!< PB PB_TYP: TYP14 (Bitfield-Mask: 0x01)                */
+#define PB_PB_TYP_TYP13_Pos               (13UL)                    /*!< PB PB_TYP: TYP13 (Bit 13)                             */
+#define PB_PB_TYP_TYP13_Msk               (0x2000UL)                /*!< PB PB_TYP: TYP13 (Bitfield-Mask: 0x01)                */
+#define PB_PB_TYP_TYP12_Pos               (12UL)                    /*!< PB PB_TYP: TYP12 (Bit 12)                             */
+#define PB_PB_TYP_TYP12_Msk               (0x1000UL)                /*!< PB PB_TYP: TYP12 (Bitfield-Mask: 0x01)                */
+#define PB_PB_TYP_TYP11_Pos               (11UL)                    /*!< PB PB_TYP: TYP11 (Bit 11)                             */
+#define PB_PB_TYP_TYP11_Msk               (0x800UL)                 /*!< PB PB_TYP: TYP11 (Bitfield-Mask: 0x01)                */
+#define PB_PB_TYP_TYP10_Pos               (10UL)                    /*!< PB PB_TYP: TYP10 (Bit 10)                             */
+#define PB_PB_TYP_TYP10_Msk               (0x400UL)                 /*!< PB PB_TYP: TYP10 (Bitfield-Mask: 0x01)                */
+#define PB_PB_TYP_TYP9_Pos                (9UL)                     /*!< PB PB_TYP: TYP9 (Bit 9)                               */
+#define PB_PB_TYP_TYP9_Msk                (0x200UL)                 /*!< PB PB_TYP: TYP9 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP8_Pos                (8UL)                     /*!< PB PB_TYP: TYP8 (Bit 8)                               */
+#define PB_PB_TYP_TYP8_Msk                (0x100UL)                 /*!< PB PB_TYP: TYP8 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP7_Pos                (7UL)                     /*!< PB PB_TYP: TYP7 (Bit 7)                               */
+#define PB_PB_TYP_TYP7_Msk                (0x80UL)                  /*!< PB PB_TYP: TYP7 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP6_Pos                (6UL)                     /*!< PB PB_TYP: TYP6 (Bit 6)                               */
+#define PB_PB_TYP_TYP6_Msk                (0x40UL)                  /*!< PB PB_TYP: TYP6 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP5_Pos                (5UL)                     /*!< PB PB_TYP: TYP5 (Bit 5)                               */
+#define PB_PB_TYP_TYP5_Msk                (0x20UL)                  /*!< PB PB_TYP: TYP5 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP4_Pos                (4UL)                     /*!< PB PB_TYP: TYP4 (Bit 4)                               */
+#define PB_PB_TYP_TYP4_Msk                (0x10UL)                  /*!< PB PB_TYP: TYP4 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP3_Pos                (3UL)                     /*!< PB PB_TYP: TYP3 (Bit 3)                               */
+#define PB_PB_TYP_TYP3_Msk                (0x8UL)                   /*!< PB PB_TYP: TYP3 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP2_Pos                (2UL)                     /*!< PB PB_TYP: TYP2 (Bit 2)                               */
+#define PB_PB_TYP_TYP2_Msk                (0x4UL)                   /*!< PB PB_TYP: TYP2 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP1_Pos                (1UL)                     /*!< PB PB_TYP: TYP1 (Bit 1)                               */
+#define PB_PB_TYP_TYP1_Msk                (0x2UL)                   /*!< PB PB_TYP: TYP1 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_TYP_TYP0_Pos                (0UL)                     /*!< PB PB_TYP: TYP0 (Bit 0)                               */
+#define PB_PB_TYP_TYP0_Msk                (0x1UL)                   /*!< PB PB_TYP: TYP0 (Bitfield-Mask: 0x01)                 */
+/* =======================================================  PB_AFSR1  ======================================================== */
+#define PB_PB_AFSR1_AFSR7_Pos             (28UL)                    /*!< PB PB_AFSR1: AFSR7 (Bit 28)                           */
+#define PB_PB_AFSR1_AFSR7_Msk             (0xf0000000UL)            /*!< PB PB_AFSR1: AFSR7 (Bitfield-Mask: 0x0f)              */
+#define PB_PB_AFSR1_AFSR6_Pos             (24UL)                    /*!< PB PB_AFSR1: AFSR6 (Bit 24)                           */
+#define PB_PB_AFSR1_AFSR6_Msk             (0xf000000UL)             /*!< PB PB_AFSR1: AFSR6 (Bitfield-Mask: 0x0f)              */
+#define PB_PB_AFSR1_AFSR5_Pos             (20UL)                    /*!< PB PB_AFSR1: AFSR5 (Bit 20)                           */
+#define PB_PB_AFSR1_AFSR5_Msk             (0xf00000UL)              /*!< PB PB_AFSR1: AFSR5 (Bitfield-Mask: 0x0f)              */
+#define PB_PB_AFSR1_AFSR4_Pos             (16UL)                    /*!< PB PB_AFSR1: AFSR4 (Bit 16)                           */
+#define PB_PB_AFSR1_AFSR4_Msk             (0xf0000UL)               /*!< PB PB_AFSR1: AFSR4 (Bitfield-Mask: 0x0f)              */
+#define PB_PB_AFSR1_AFSR3_Pos             (12UL)                    /*!< PB PB_AFSR1: AFSR3 (Bit 12)                           */
+#define PB_PB_AFSR1_AFSR3_Msk             (0xf000UL)                /*!< PB PB_AFSR1: AFSR3 (Bitfield-Mask: 0x0f)              */
+#define PB_PB_AFSR1_AFSR2_Pos             (8UL)                     /*!< PB PB_AFSR1: AFSR2 (Bit 8)                            */
+#define PB_PB_AFSR1_AFSR2_Msk             (0xf00UL)                 /*!< PB PB_AFSR1: AFSR2 (Bitfield-Mask: 0x0f)              */
+#define PB_PB_AFSR1_AFSR1_Pos             (4UL)                     /*!< PB PB_AFSR1: AFSR1 (Bit 4)                            */
+#define PB_PB_AFSR1_AFSR1_Msk             (0xf0UL)                  /*!< PB PB_AFSR1: AFSR1 (Bitfield-Mask: 0x0f)              */
+#define PB_PB_AFSR1_AFSR0_Pos             (0UL)                     /*!< PB PB_AFSR1: AFSR0 (Bit 0)                            */
+#define PB_PB_AFSR1_AFSR0_Msk             (0xfUL)                   /*!< PB PB_AFSR1: AFSR0 (Bitfield-Mask: 0x0f)              */
+/* =======================================================  PB_AFSR2  ======================================================== */
+#define PB_PB_AFSR2_AFSR15_Pos            (28UL)                    /*!< PB PB_AFSR2: AFSR15 (Bit 28)                          */
+#define PB_PB_AFSR2_AFSR15_Msk            (0xf0000000UL)            /*!< PB PB_AFSR2: AFSR15 (Bitfield-Mask: 0x0f)             */
+#define PB_PB_AFSR2_AFSR14_Pos            (24UL)                    /*!< PB PB_AFSR2: AFSR14 (Bit 24)                          */
+#define PB_PB_AFSR2_AFSR14_Msk            (0xf000000UL)             /*!< PB PB_AFSR2: AFSR14 (Bitfield-Mask: 0x0f)             */
+#define PB_PB_AFSR2_AFSR13_Pos            (20UL)                    /*!< PB PB_AFSR2: AFSR13 (Bit 20)                          */
+#define PB_PB_AFSR2_AFSR13_Msk            (0xf00000UL)              /*!< PB PB_AFSR2: AFSR13 (Bitfield-Mask: 0x0f)             */
+#define PB_PB_AFSR2_AFSR12_Pos            (16UL)                    /*!< PB PB_AFSR2: AFSR12 (Bit 16)                          */
+#define PB_PB_AFSR2_AFSR12_Msk            (0xf0000UL)               /*!< PB PB_AFSR2: AFSR12 (Bitfield-Mask: 0x0f)             */
+#define PB_PB_AFSR2_AFSR11_Pos            (12UL)                    /*!< PB PB_AFSR2: AFSR11 (Bit 12)                          */
+#define PB_PB_AFSR2_AFSR11_Msk            (0xf000UL)                /*!< PB PB_AFSR2: AFSR11 (Bitfield-Mask: 0x0f)             */
+#define PB_PB_AFSR2_AFSR10_Pos            (8UL)                     /*!< PB PB_AFSR2: AFSR10 (Bit 8)                           */
+#define PB_PB_AFSR2_AFSR10_Msk            (0xf00UL)                 /*!< PB PB_AFSR2: AFSR10 (Bitfield-Mask: 0x0f)             */
+#define PB_PB_AFSR2_AFSR9_Pos             (4UL)                     /*!< PB PB_AFSR2: AFSR9 (Bit 4)                            */
+#define PB_PB_AFSR2_AFSR9_Msk             (0xf0UL)                  /*!< PB PB_AFSR2: AFSR9 (Bitfield-Mask: 0x0f)              */
+#define PB_PB_AFSR2_AFSR8_Pos             (0UL)                     /*!< PB PB_AFSR2: AFSR8 (Bit 0)                            */
+#define PB_PB_AFSR2_AFSR8_Msk             (0xfUL)                   /*!< PB PB_AFSR2: AFSR8 (Bitfield-Mask: 0x0f)              */
+/* ========================================================  PB_PUPD  ======================================================== */
+#define PB_PB_PUPD_PUPD15_Pos             (30UL)                    /*!< PB PB_PUPD: PUPD15 (Bit 30)                           */
+#define PB_PB_PUPD_PUPD15_Msk             (0xc0000000UL)            /*!< PB PB_PUPD: PUPD15 (Bitfield-Mask: 0x03)              */
+#define PB_PB_PUPD_PUPD14_Pos             (28UL)                    /*!< PB PB_PUPD: PUPD14 (Bit 28)                           */
+#define PB_PB_PUPD_PUPD14_Msk             (0x30000000UL)            /*!< PB PB_PUPD: PUPD14 (Bitfield-Mask: 0x03)              */
+#define PB_PB_PUPD_PUPD13_Pos             (26UL)                    /*!< PB PB_PUPD: PUPD13 (Bit 26)                           */
+#define PB_PB_PUPD_PUPD13_Msk             (0xc000000UL)             /*!< PB PB_PUPD: PUPD13 (Bitfield-Mask: 0x03)              */
+#define PB_PB_PUPD_PUPD12_Pos             (24UL)                    /*!< PB PB_PUPD: PUPD12 (Bit 24)                           */
+#define PB_PB_PUPD_PUPD12_Msk             (0x3000000UL)             /*!< PB PB_PUPD: PUPD12 (Bitfield-Mask: 0x03)              */
+#define PB_PB_PUPD_PUPD11_Pos             (22UL)                    /*!< PB PB_PUPD: PUPD11 (Bit 22)                           */
+#define PB_PB_PUPD_PUPD11_Msk             (0xc00000UL)              /*!< PB PB_PUPD: PUPD11 (Bitfield-Mask: 0x03)              */
+#define PB_PB_PUPD_PUPD10_Pos             (20UL)                    /*!< PB PB_PUPD: PUPD10 (Bit 20)                           */
+#define PB_PB_PUPD_PUPD10_Msk             (0x300000UL)              /*!< PB PB_PUPD: PUPD10 (Bitfield-Mask: 0x03)              */
+#define PB_PB_PUPD_PUPD9_Pos              (18UL)                    /*!< PB PB_PUPD: PUPD9 (Bit 18)                            */
+#define PB_PB_PUPD_PUPD9_Msk              (0xc0000UL)               /*!< PB PB_PUPD: PUPD9 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD8_Pos              (16UL)                    /*!< PB PB_PUPD: PUPD8 (Bit 16)                            */
+#define PB_PB_PUPD_PUPD8_Msk              (0x30000UL)               /*!< PB PB_PUPD: PUPD8 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD7_Pos              (14UL)                    /*!< PB PB_PUPD: PUPD7 (Bit 14)                            */
+#define PB_PB_PUPD_PUPD7_Msk              (0xc000UL)                /*!< PB PB_PUPD: PUPD7 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD6_Pos              (12UL)                    /*!< PB PB_PUPD: PUPD6 (Bit 12)                            */
+#define PB_PB_PUPD_PUPD6_Msk              (0x3000UL)                /*!< PB PB_PUPD: PUPD6 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD5_Pos              (10UL)                    /*!< PB PB_PUPD: PUPD5 (Bit 10)                            */
+#define PB_PB_PUPD_PUPD5_Msk              (0xc00UL)                 /*!< PB PB_PUPD: PUPD5 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD4_Pos              (8UL)                     /*!< PB PB_PUPD: PUPD4 (Bit 8)                             */
+#define PB_PB_PUPD_PUPD4_Msk              (0x300UL)                 /*!< PB PB_PUPD: PUPD4 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD3_Pos              (6UL)                     /*!< PB PB_PUPD: PUPD3 (Bit 6)                             */
+#define PB_PB_PUPD_PUPD3_Msk              (0xc0UL)                  /*!< PB PB_PUPD: PUPD3 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD2_Pos              (4UL)                     /*!< PB PB_PUPD: PUPD2 (Bit 4)                             */
+#define PB_PB_PUPD_PUPD2_Msk              (0x30UL)                  /*!< PB PB_PUPD: PUPD2 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD1_Pos              (2UL)                     /*!< PB PB_PUPD: PUPD1 (Bit 2)                             */
+#define PB_PB_PUPD_PUPD1_Msk              (0xcUL)                   /*!< PB PB_PUPD: PUPD1 (Bitfield-Mask: 0x03)               */
+#define PB_PB_PUPD_PUPD0_Pos              (0UL)                     /*!< PB PB_PUPD: PUPD0 (Bit 0)                             */
+#define PB_PB_PUPD_PUPD0_Msk              (0x3UL)                   /*!< PB PB_PUPD: PUPD0 (Bitfield-Mask: 0x03)               */
+/* ========================================================  PB_INDR  ======================================================== */
+#define PB_PB_INDR_INDR15_Pos             (15UL)                    /*!< PB PB_INDR: INDR15 (Bit 15)                           */
+#define PB_PB_INDR_INDR15_Msk             (0x8000UL)                /*!< PB PB_INDR: INDR15 (Bitfield-Mask: 0x01)              */
+#define PB_PB_INDR_INDR14_Pos             (14UL)                    /*!< PB PB_INDR: INDR14 (Bit 14)                           */
+#define PB_PB_INDR_INDR14_Msk             (0x4000UL)                /*!< PB PB_INDR: INDR14 (Bitfield-Mask: 0x01)              */
+#define PB_PB_INDR_INDR13_Pos             (13UL)                    /*!< PB PB_INDR: INDR13 (Bit 13)                           */
+#define PB_PB_INDR_INDR13_Msk             (0x2000UL)                /*!< PB PB_INDR: INDR13 (Bitfield-Mask: 0x01)              */
+#define PB_PB_INDR_INDR12_Pos             (12UL)                    /*!< PB PB_INDR: INDR12 (Bit 12)                           */
+#define PB_PB_INDR_INDR12_Msk             (0x1000UL)                /*!< PB PB_INDR: INDR12 (Bitfield-Mask: 0x01)              */
+#define PB_PB_INDR_INDR11_Pos             (11UL)                    /*!< PB PB_INDR: INDR11 (Bit 11)                           */
+#define PB_PB_INDR_INDR11_Msk             (0x800UL)                 /*!< PB PB_INDR: INDR11 (Bitfield-Mask: 0x01)              */
+#define PB_PB_INDR_INDR10_Pos             (10UL)                    /*!< PB PB_INDR: INDR10 (Bit 10)                           */
+#define PB_PB_INDR_INDR10_Msk             (0x400UL)                 /*!< PB PB_INDR: INDR10 (Bitfield-Mask: 0x01)              */
+#define PB_PB_INDR_INDR9_Pos              (9UL)                     /*!< PB PB_INDR: INDR9 (Bit 9)                             */
+#define PB_PB_INDR_INDR9_Msk              (0x200UL)                 /*!< PB PB_INDR: INDR9 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR8_Pos              (8UL)                     /*!< PB PB_INDR: INDR8 (Bit 8)                             */
+#define PB_PB_INDR_INDR8_Msk              (0x100UL)                 /*!< PB PB_INDR: INDR8 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR7_Pos              (7UL)                     /*!< PB PB_INDR: INDR7 (Bit 7)                             */
+#define PB_PB_INDR_INDR7_Msk              (0x80UL)                  /*!< PB PB_INDR: INDR7 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR6_Pos              (6UL)                     /*!< PB PB_INDR: INDR6 (Bit 6)                             */
+#define PB_PB_INDR_INDR6_Msk              (0x40UL)                  /*!< PB PB_INDR: INDR6 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR5_Pos              (5UL)                     /*!< PB PB_INDR: INDR5 (Bit 5)                             */
+#define PB_PB_INDR_INDR5_Msk              (0x20UL)                  /*!< PB PB_INDR: INDR5 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR4_Pos              (4UL)                     /*!< PB PB_INDR: INDR4 (Bit 4)                             */
+#define PB_PB_INDR_INDR4_Msk              (0x10UL)                  /*!< PB PB_INDR: INDR4 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR3_Pos              (3UL)                     /*!< PB PB_INDR: INDR3 (Bit 3)                             */
+#define PB_PB_INDR_INDR3_Msk              (0x8UL)                   /*!< PB PB_INDR: INDR3 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR2_Pos              (2UL)                     /*!< PB PB_INDR: INDR2 (Bit 2)                             */
+#define PB_PB_INDR_INDR2_Msk              (0x4UL)                   /*!< PB PB_INDR: INDR2 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR1_Pos              (1UL)                     /*!< PB PB_INDR: INDR1 (Bit 1)                             */
+#define PB_PB_INDR_INDR1_Msk              (0x2UL)                   /*!< PB PB_INDR: INDR1 (Bitfield-Mask: 0x01)               */
+#define PB_PB_INDR_INDR0_Pos              (0UL)                     /*!< PB PB_INDR: INDR0 (Bit 0)                             */
+#define PB_PB_INDR_INDR0_Msk              (0x1UL)                   /*!< PB PB_INDR: INDR0 (Bitfield-Mask: 0x01)               */
+/* =======================================================  PB_OUTDR  ======================================================== */
+#define PB_PB_OUTDR_OUTDR15_Pos           (15UL)                    /*!< PB PB_OUTDR: OUTDR15 (Bit 15)                         */
+#define PB_PB_OUTDR_OUTDR15_Msk           (0x8000UL)                /*!< PB PB_OUTDR: OUTDR15 (Bitfield-Mask: 0x01)            */
+#define PB_PB_OUTDR_OUTDR14_Pos           (14UL)                    /*!< PB PB_OUTDR: OUTDR14 (Bit 14)                         */
+#define PB_PB_OUTDR_OUTDR14_Msk           (0x4000UL)                /*!< PB PB_OUTDR: OUTDR14 (Bitfield-Mask: 0x01)            */
+#define PB_PB_OUTDR_OUTDR13_Pos           (13UL)                    /*!< PB PB_OUTDR: OUTDR13 (Bit 13)                         */
+#define PB_PB_OUTDR_OUTDR13_Msk           (0x2000UL)                /*!< PB PB_OUTDR: OUTDR13 (Bitfield-Mask: 0x01)            */
+#define PB_PB_OUTDR_OUTDR12_Pos           (12UL)                    /*!< PB PB_OUTDR: OUTDR12 (Bit 12)                         */
+#define PB_PB_OUTDR_OUTDR12_Msk           (0x1000UL)                /*!< PB PB_OUTDR: OUTDR12 (Bitfield-Mask: 0x01)            */
+#define PB_PB_OUTDR_OUTDR11_Pos           (11UL)                    /*!< PB PB_OUTDR: OUTDR11 (Bit 11)                         */
+#define PB_PB_OUTDR_OUTDR11_Msk           (0x800UL)                 /*!< PB PB_OUTDR: OUTDR11 (Bitfield-Mask: 0x01)            */
+#define PB_PB_OUTDR_OUTDR10_Pos           (10UL)                    /*!< PB PB_OUTDR: OUTDR10 (Bit 10)                         */
+#define PB_PB_OUTDR_OUTDR10_Msk           (0x400UL)                 /*!< PB PB_OUTDR: OUTDR10 (Bitfield-Mask: 0x01)            */
+#define PB_PB_OUTDR_OUTDR9_Pos            (9UL)                     /*!< PB PB_OUTDR: OUTDR9 (Bit 9)                           */
+#define PB_PB_OUTDR_OUTDR9_Msk            (0x200UL)                 /*!< PB PB_OUTDR: OUTDR9 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR8_Pos            (8UL)                     /*!< PB PB_OUTDR: OUTDR8 (Bit 8)                           */
+#define PB_PB_OUTDR_OUTDR8_Msk            (0x100UL)                 /*!< PB PB_OUTDR: OUTDR8 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR7_Pos            (7UL)                     /*!< PB PB_OUTDR: OUTDR7 (Bit 7)                           */
+#define PB_PB_OUTDR_OUTDR7_Msk            (0x80UL)                  /*!< PB PB_OUTDR: OUTDR7 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR6_Pos            (6UL)                     /*!< PB PB_OUTDR: OUTDR6 (Bit 6)                           */
+#define PB_PB_OUTDR_OUTDR6_Msk            (0x40UL)                  /*!< PB PB_OUTDR: OUTDR6 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR5_Pos            (5UL)                     /*!< PB PB_OUTDR: OUTDR5 (Bit 5)                           */
+#define PB_PB_OUTDR_OUTDR5_Msk            (0x20UL)                  /*!< PB PB_OUTDR: OUTDR5 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR4_Pos            (4UL)                     /*!< PB PB_OUTDR: OUTDR4 (Bit 4)                           */
+#define PB_PB_OUTDR_OUTDR4_Msk            (0x10UL)                  /*!< PB PB_OUTDR: OUTDR4 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR3_Pos            (3UL)                     /*!< PB PB_OUTDR: OUTDR3 (Bit 3)                           */
+#define PB_PB_OUTDR_OUTDR3_Msk            (0x8UL)                   /*!< PB PB_OUTDR: OUTDR3 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR2_Pos            (2UL)                     /*!< PB PB_OUTDR: OUTDR2 (Bit 2)                           */
+#define PB_PB_OUTDR_OUTDR2_Msk            (0x4UL)                   /*!< PB PB_OUTDR: OUTDR2 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR1_Pos            (1UL)                     /*!< PB PB_OUTDR: OUTDR1 (Bit 1)                           */
+#define PB_PB_OUTDR_OUTDR1_Msk            (0x2UL)                   /*!< PB PB_OUTDR: OUTDR1 (Bitfield-Mask: 0x01)             */
+#define PB_PB_OUTDR_OUTDR0_Pos            (0UL)                     /*!< PB PB_OUTDR: OUTDR0 (Bit 0)                           */
+#define PB_PB_OUTDR_OUTDR0_Msk            (0x1UL)                   /*!< PB PB_OUTDR: OUTDR0 (Bitfield-Mask: 0x01)             */
+/* ========================================================  PB_BSR  ========================================================= */
+#define PB_PB_BSR_BSR15_Pos               (15UL)                    /*!< PB PB_BSR: BSR15 (Bit 15)                             */
+#define PB_PB_BSR_BSR15_Msk               (0x8000UL)                /*!< PB PB_BSR: BSR15 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BSR_BSR14_Pos               (14UL)                    /*!< PB PB_BSR: BSR14 (Bit 14)                             */
+#define PB_PB_BSR_BSR14_Msk               (0x4000UL)                /*!< PB PB_BSR: BSR14 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BSR_BSR13_Pos               (13UL)                    /*!< PB PB_BSR: BSR13 (Bit 13)                             */
+#define PB_PB_BSR_BSR13_Msk               (0x2000UL)                /*!< PB PB_BSR: BSR13 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BSR_BSR12_Pos               (12UL)                    /*!< PB PB_BSR: BSR12 (Bit 12)                             */
+#define PB_PB_BSR_BSR12_Msk               (0x1000UL)                /*!< PB PB_BSR: BSR12 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BSR_BSR11_Pos               (11UL)                    /*!< PB PB_BSR: BSR11 (Bit 11)                             */
+#define PB_PB_BSR_BSR11_Msk               (0x800UL)                 /*!< PB PB_BSR: BSR11 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BSR_BSR10_Pos               (10UL)                    /*!< PB PB_BSR: BSR10 (Bit 10)                             */
+#define PB_PB_BSR_BSR10_Msk               (0x400UL)                 /*!< PB PB_BSR: BSR10 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BSR_BSR9_Pos                (9UL)                     /*!< PB PB_BSR: BSR9 (Bit 9)                               */
+#define PB_PB_BSR_BSR9_Msk                (0x200UL)                 /*!< PB PB_BSR: BSR9 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR8_Pos                (8UL)                     /*!< PB PB_BSR: BSR8 (Bit 8)                               */
+#define PB_PB_BSR_BSR8_Msk                (0x100UL)                 /*!< PB PB_BSR: BSR8 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR7_Pos                (7UL)                     /*!< PB PB_BSR: BSR7 (Bit 7)                               */
+#define PB_PB_BSR_BSR7_Msk                (0x80UL)                  /*!< PB PB_BSR: BSR7 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR6_Pos                (6UL)                     /*!< PB PB_BSR: BSR6 (Bit 6)                               */
+#define PB_PB_BSR_BSR6_Msk                (0x40UL)                  /*!< PB PB_BSR: BSR6 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR5_Pos                (5UL)                     /*!< PB PB_BSR: BSR5 (Bit 5)                               */
+#define PB_PB_BSR_BSR5_Msk                (0x20UL)                  /*!< PB PB_BSR: BSR5 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR4_Pos                (4UL)                     /*!< PB PB_BSR: BSR4 (Bit 4)                               */
+#define PB_PB_BSR_BSR4_Msk                (0x10UL)                  /*!< PB PB_BSR: BSR4 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR3_Pos                (3UL)                     /*!< PB PB_BSR: BSR3 (Bit 3)                               */
+#define PB_PB_BSR_BSR3_Msk                (0x8UL)                   /*!< PB PB_BSR: BSR3 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR2_Pos                (2UL)                     /*!< PB PB_BSR: BSR2 (Bit 2)                               */
+#define PB_PB_BSR_BSR2_Msk                (0x4UL)                   /*!< PB PB_BSR: BSR2 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR1_Pos                (1UL)                     /*!< PB PB_BSR: BSR1 (Bit 1)                               */
+#define PB_PB_BSR_BSR1_Msk                (0x2UL)                   /*!< PB PB_BSR: BSR1 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BSR_BSR0_Pos                (0UL)                     /*!< PB PB_BSR: BSR0 (Bit 0)                               */
+#define PB_PB_BSR_BSR0_Msk                (0x1UL)                   /*!< PB PB_BSR: BSR0 (Bitfield-Mask: 0x01)                 */
+/* ========================================================  PB_BCR  ========================================================= */
+#define PB_PB_BCR_BCR15_Pos               (15UL)                    /*!< PB PB_BCR: BCR15 (Bit 15)                             */
+#define PB_PB_BCR_BCR15_Msk               (0x8000UL)                /*!< PB PB_BCR: BCR15 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BCR_BCR14_Pos               (14UL)                    /*!< PB PB_BCR: BCR14 (Bit 14)                             */
+#define PB_PB_BCR_BCR14_Msk               (0x4000UL)                /*!< PB PB_BCR: BCR14 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BCR_BCR13_Pos               (13UL)                    /*!< PB PB_BCR: BCR13 (Bit 13)                             */
+#define PB_PB_BCR_BCR13_Msk               (0x2000UL)                /*!< PB PB_BCR: BCR13 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BCR_BCR12_Pos               (12UL)                    /*!< PB PB_BCR: BCR12 (Bit 12)                             */
+#define PB_PB_BCR_BCR12_Msk               (0x1000UL)                /*!< PB PB_BCR: BCR12 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BCR_BCR11_Pos               (11UL)                    /*!< PB PB_BCR: BCR11 (Bit 11)                             */
+#define PB_PB_BCR_BCR11_Msk               (0x800UL)                 /*!< PB PB_BCR: BCR11 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BCR_BCR10_Pos               (10UL)                    /*!< PB PB_BCR: BCR10 (Bit 10)                             */
+#define PB_PB_BCR_BCR10_Msk               (0x400UL)                 /*!< PB PB_BCR: BCR10 (Bitfield-Mask: 0x01)                */
+#define PB_PB_BCR_BCR9_Pos                (9UL)                     /*!< PB PB_BCR: BCR9 (Bit 9)                               */
+#define PB_PB_BCR_BCR9_Msk                (0x200UL)                 /*!< PB PB_BCR: BCR9 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR8_Pos                (8UL)                     /*!< PB PB_BCR: BCR8 (Bit 8)                               */
+#define PB_PB_BCR_BCR8_Msk                (0x100UL)                 /*!< PB PB_BCR: BCR8 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR7_Pos                (7UL)                     /*!< PB PB_BCR: BCR7 (Bit 7)                               */
+#define PB_PB_BCR_BCR7_Msk                (0x80UL)                  /*!< PB PB_BCR: BCR7 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR6_Pos                (6UL)                     /*!< PB PB_BCR: BCR6 (Bit 6)                               */
+#define PB_PB_BCR_BCR6_Msk                (0x40UL)                  /*!< PB PB_BCR: BCR6 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR5_Pos                (5UL)                     /*!< PB PB_BCR: BCR5 (Bit 5)                               */
+#define PB_PB_BCR_BCR5_Msk                (0x20UL)                  /*!< PB PB_BCR: BCR5 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR4_Pos                (4UL)                     /*!< PB PB_BCR: BCR4 (Bit 4)                               */
+#define PB_PB_BCR_BCR4_Msk                (0x10UL)                  /*!< PB PB_BCR: BCR4 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR3_Pos                (3UL)                     /*!< PB PB_BCR: BCR3 (Bit 3)                               */
+#define PB_PB_BCR_BCR3_Msk                (0x8UL)                   /*!< PB PB_BCR: BCR3 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR2_Pos                (2UL)                     /*!< PB PB_BCR: BCR2 (Bit 2)                               */
+#define PB_PB_BCR_BCR2_Msk                (0x4UL)                   /*!< PB PB_BCR: BCR2 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR1_Pos                (1UL)                     /*!< PB PB_BCR: BCR1 (Bit 1)                               */
+#define PB_PB_BCR_BCR1_Msk                (0x2UL)                   /*!< PB PB_BCR: BCR1 (Bitfield-Mask: 0x01)                 */
+#define PB_PB_BCR_BCR0_Pos                (0UL)                     /*!< PB PB_BCR: BCR0 (Bit 0)                               */
+#define PB_PB_BCR_BCR0_Msk                (0x1UL)                   /*!< PB PB_BCR: BCR0 (Bitfield-Mask: 0x01)                 */
+/* ======================================================  PB_OUTDMSK  ======================================================= */
+#define PB_PB_OUTDMSK_OUTDMSK15_Pos       (15UL)                    /*!< PB PB_OUTDMSK: OUTDMSK15 (Bit 15)                     */
+#define PB_PB_OUTDMSK_OUTDMSK15_Msk       (0x8000UL)                /*!< PB PB_OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)        */
+#define PB_PB_OUTDMSK_OUTDMSK14_Pos       (14UL)                    /*!< PB PB_OUTDMSK: OUTDMSK14 (Bit 14)                     */
+#define PB_PB_OUTDMSK_OUTDMSK14_Msk       (0x4000UL)                /*!< PB PB_OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)        */
+#define PB_PB_OUTDMSK_OUTDMSK13_Pos       (13UL)                    /*!< PB PB_OUTDMSK: OUTDMSK13 (Bit 13)                     */
+#define PB_PB_OUTDMSK_OUTDMSK13_Msk       (0x2000UL)                /*!< PB PB_OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)        */
+#define PB_PB_OUTDMSK_OUTDMSK12_Pos       (12UL)                    /*!< PB PB_OUTDMSK: OUTDMSK12 (Bit 12)                     */
+#define PB_PB_OUTDMSK_OUTDMSK12_Msk       (0x1000UL)                /*!< PB PB_OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)        */
+#define PB_PB_OUTDMSK_OUTDMSK11_Pos       (11UL)                    /*!< PB PB_OUTDMSK: OUTDMSK11 (Bit 11)                     */
+#define PB_PB_OUTDMSK_OUTDMSK11_Msk       (0x800UL)                 /*!< PB PB_OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)        */
+#define PB_PB_OUTDMSK_OUTDMSK10_Pos       (10UL)                    /*!< PB PB_OUTDMSK: OUTDMSK10 (Bit 10)                     */
+#define PB_PB_OUTDMSK_OUTDMSK10_Msk       (0x400UL)                 /*!< PB PB_OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)        */
+#define PB_PB_OUTDMSK_OUTDMSK9_Pos        (9UL)                     /*!< PB PB_OUTDMSK: OUTDMSK9 (Bit 9)                       */
+#define PB_PB_OUTDMSK_OUTDMSK9_Msk        (0x200UL)                 /*!< PB PB_OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK8_Pos        (8UL)                     /*!< PB PB_OUTDMSK: OUTDMSK8 (Bit 8)                       */
+#define PB_PB_OUTDMSK_OUTDMSK8_Msk        (0x100UL)                 /*!< PB PB_OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK7_Pos        (7UL)                     /*!< PB PB_OUTDMSK: OUTDMSK7 (Bit 7)                       */
+#define PB_PB_OUTDMSK_OUTDMSK7_Msk        (0x80UL)                  /*!< PB PB_OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK6_Pos        (6UL)                     /*!< PB PB_OUTDMSK: OUTDMSK6 (Bit 6)                       */
+#define PB_PB_OUTDMSK_OUTDMSK6_Msk        (0x40UL)                  /*!< PB PB_OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK5_Pos        (5UL)                     /*!< PB PB_OUTDMSK: OUTDMSK5 (Bit 5)                       */
+#define PB_PB_OUTDMSK_OUTDMSK5_Msk        (0x20UL)                  /*!< PB PB_OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK4_Pos        (4UL)                     /*!< PB PB_OUTDMSK: OUTDMSK4 (Bit 4)                       */
+#define PB_PB_OUTDMSK_OUTDMSK4_Msk        (0x10UL)                  /*!< PB PB_OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK3_Pos        (3UL)                     /*!< PB PB_OUTDMSK: OUTDMSK3 (Bit 3)                       */
+#define PB_PB_OUTDMSK_OUTDMSK3_Msk        (0x8UL)                   /*!< PB PB_OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK2_Pos        (2UL)                     /*!< PB PB_OUTDMSK: OUTDMSK2 (Bit 2)                       */
+#define PB_PB_OUTDMSK_OUTDMSK2_Msk        (0x4UL)                   /*!< PB PB_OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK1_Pos        (1UL)                     /*!< PB PB_OUTDMSK: OUTDMSK1 (Bit 1)                       */
+#define PB_PB_OUTDMSK_OUTDMSK1_Msk        (0x2UL)                   /*!< PB PB_OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)         */
+#define PB_PB_OUTDMSK_OUTDMSK0_Pos        (0UL)                     /*!< PB PB_OUTDMSK: OUTDMSK0 (Bit 0)                       */
+#define PB_PB_OUTDMSK_OUTDMSK0_Msk        (0x1UL)                   /*!< PB PB_OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)         */
+/* ========================================================  PB_DBCR  ======================================================== */
+#define PB_PB_DBCR_DBCLK_Pos              (16UL)                    /*!< PB PB_DBCR: DBCLK (Bit 16)                            */
+#define PB_PB_DBCR_DBCLK_Msk              (0x70000UL)               /*!< PB PB_DBCR: DBCLK (Bitfield-Mask: 0x07)               */
+#define PB_PB_DBCR_DBEN11_Pos             (11UL)                    /*!< PB PB_DBCR: DBEN11 (Bit 11)                           */
+#define PB_PB_DBCR_DBEN11_Msk             (0x800UL)                 /*!< PB PB_DBCR: DBEN11 (Bitfield-Mask: 0x01)              */
+#define PB_PB_DBCR_DBEN10_Pos             (10UL)                    /*!< PB PB_DBCR: DBEN10 (Bit 10)                           */
+#define PB_PB_DBCR_DBEN10_Msk             (0x400UL)                 /*!< PB PB_DBCR: DBEN10 (Bitfield-Mask: 0x01)              */
+#define PB_PB_DBCR_DBEN9_Pos              (9UL)                     /*!< PB PB_DBCR: DBEN9 (Bit 9)                             */
+#define PB_PB_DBCR_DBEN9_Msk              (0x200UL)                 /*!< PB PB_DBCR: DBEN9 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN8_Pos              (8UL)                     /*!< PB PB_DBCR: DBEN8 (Bit 8)                             */
+#define PB_PB_DBCR_DBEN8_Msk              (0x100UL)                 /*!< PB PB_DBCR: DBEN8 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN7_Pos              (7UL)                     /*!< PB PB_DBCR: DBEN7 (Bit 7)                             */
+#define PB_PB_DBCR_DBEN7_Msk              (0x80UL)                  /*!< PB PB_DBCR: DBEN7 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN6_Pos              (6UL)                     /*!< PB PB_DBCR: DBEN6 (Bit 6)                             */
+#define PB_PB_DBCR_DBEN6_Msk              (0x40UL)                  /*!< PB PB_DBCR: DBEN6 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN5_Pos              (5UL)                     /*!< PB PB_DBCR: DBEN5 (Bit 5)                             */
+#define PB_PB_DBCR_DBEN5_Msk              (0x20UL)                  /*!< PB PB_DBCR: DBEN5 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN4_Pos              (4UL)                     /*!< PB PB_DBCR: DBEN4 (Bit 4)                             */
+#define PB_PB_DBCR_DBEN4_Msk              (0x10UL)                  /*!< PB PB_DBCR: DBEN4 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN3_Pos              (3UL)                     /*!< PB PB_DBCR: DBEN3 (Bit 3)                             */
+#define PB_PB_DBCR_DBEN3_Msk              (0x8UL)                   /*!< PB PB_DBCR: DBEN3 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN2_Pos              (2UL)                     /*!< PB PB_DBCR: DBEN2 (Bit 2)                             */
+#define PB_PB_DBCR_DBEN2_Msk              (0x4UL)                   /*!< PB PB_DBCR: DBEN2 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN1_Pos              (1UL)                     /*!< PB PB_DBCR: DBEN1 (Bit 1)                             */
+#define PB_PB_DBCR_DBEN1_Msk              (0x2UL)                   /*!< PB PB_DBCR: DBEN1 (Bitfield-Mask: 0x01)               */
+#define PB_PB_DBCR_DBEN0_Pos              (0UL)                     /*!< PB PB_DBCR: DBEN0 (Bit 0)                             */
+#define PB_PB_DBCR_DBEN0_Msk              (0x1UL)                   /*!< PB PB_DBCR: DBEN0 (Bitfield-Mask: 0x01)               */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PC                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+#define PC_MOD_MODE15_Pos                 (30UL)                    /*!< PC MOD: MODE15 (Bit 30)                               */
+#define PC_MOD_MODE15_Msk                 (0xc0000000UL)            /*!< PC MOD: MODE15 (Bitfield-Mask: 0x03)                  */
+#define PC_MOD_MODE14_Pos                 (28UL)                    /*!< PC MOD: MODE14 (Bit 28)                               */
+#define PC_MOD_MODE14_Msk                 (0x30000000UL)            /*!< PC MOD: MODE14 (Bitfield-Mask: 0x03)                  */
+#define PC_MOD_MODE13_Pos                 (26UL)                    /*!< PC MOD: MODE13 (Bit 26)                               */
+#define PC_MOD_MODE13_Msk                 (0xc000000UL)             /*!< PC MOD: MODE13 (Bitfield-Mask: 0x03)                  */
+#define PC_MOD_MODE12_Pos                 (24UL)                    /*!< PC MOD: MODE12 (Bit 24)                               */
+#define PC_MOD_MODE12_Msk                 (0x3000000UL)             /*!< PC MOD: MODE12 (Bitfield-Mask: 0x03)                  */
+#define PC_MOD_MODE11_Pos                 (22UL)                    /*!< PC MOD: MODE11 (Bit 22)                               */
+#define PC_MOD_MODE11_Msk                 (0xc00000UL)              /*!< PC MOD: MODE11 (Bitfield-Mask: 0x03)                  */
+#define PC_MOD_MODE10_Pos                 (20UL)                    /*!< PC MOD: MODE10 (Bit 20)                               */
+#define PC_MOD_MODE10_Msk                 (0x300000UL)              /*!< PC MOD: MODE10 (Bitfield-Mask: 0x03)                  */
+#define PC_MOD_MODE9_Pos                  (18UL)                    /*!< PC MOD: MODE9 (Bit 18)                                */
+#define PC_MOD_MODE9_Msk                  (0xc0000UL)               /*!< PC MOD: MODE9 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE8_Pos                  (16UL)                    /*!< PC MOD: MODE8 (Bit 16)                                */
+#define PC_MOD_MODE8_Msk                  (0x30000UL)               /*!< PC MOD: MODE8 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE7_Pos                  (14UL)                    /*!< PC MOD: MODE7 (Bit 14)                                */
+#define PC_MOD_MODE7_Msk                  (0xc000UL)                /*!< PC MOD: MODE7 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE6_Pos                  (12UL)                    /*!< PC MOD: MODE6 (Bit 12)                                */
+#define PC_MOD_MODE6_Msk                  (0x3000UL)                /*!< PC MOD: MODE6 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE5_Pos                  (10UL)                    /*!< PC MOD: MODE5 (Bit 10)                                */
+#define PC_MOD_MODE5_Msk                  (0xc00UL)                 /*!< PC MOD: MODE5 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE4_Pos                  (8UL)                     /*!< PC MOD: MODE4 (Bit 8)                                 */
+#define PC_MOD_MODE4_Msk                  (0x300UL)                 /*!< PC MOD: MODE4 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE3_Pos                  (6UL)                     /*!< PC MOD: MODE3 (Bit 6)                                 */
+#define PC_MOD_MODE3_Msk                  (0xc0UL)                  /*!< PC MOD: MODE3 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE2_Pos                  (4UL)                     /*!< PC MOD: MODE2 (Bit 4)                                 */
+#define PC_MOD_MODE2_Msk                  (0x30UL)                  /*!< PC MOD: MODE2 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE1_Pos                  (2UL)                     /*!< PC MOD: MODE1 (Bit 2)                                 */
+#define PC_MOD_MODE1_Msk                  (0xcUL)                   /*!< PC MOD: MODE1 (Bitfield-Mask: 0x03)                   */
+#define PC_MOD_MODE0_Pos                  (0UL)                     /*!< PC MOD: MODE0 (Bit 0)                                 */
+#define PC_MOD_MODE0_Msk                  (0x3UL)                   /*!< PC MOD: MODE0 (Bitfield-Mask: 0x03)                   */
+/* ==========================================================  TYP  ========================================================== */
+#define PC_TYP_TYP15_Pos                  (15UL)                    /*!< PC TYP: TYP15 (Bit 15)                                */
+#define PC_TYP_TYP15_Msk                  (0x8000UL)                /*!< PC TYP: TYP15 (Bitfield-Mask: 0x01)                   */
+#define PC_TYP_TYP14_Pos                  (14UL)                    /*!< PC TYP: TYP14 (Bit 14)                                */
+#define PC_TYP_TYP14_Msk                  (0x4000UL)                /*!< PC TYP: TYP14 (Bitfield-Mask: 0x01)                   */
+#define PC_TYP_TYP13_Pos                  (13UL)                    /*!< PC TYP: TYP13 (Bit 13)                                */
+#define PC_TYP_TYP13_Msk                  (0x2000UL)                /*!< PC TYP: TYP13 (Bitfield-Mask: 0x01)                   */
+#define PC_TYP_TYP12_Pos                  (12UL)                    /*!< PC TYP: TYP12 (Bit 12)                                */
+#define PC_TYP_TYP12_Msk                  (0x1000UL)                /*!< PC TYP: TYP12 (Bitfield-Mask: 0x01)                   */
+#define PC_TYP_TYP11_Pos                  (11UL)                    /*!< PC TYP: TYP11 (Bit 11)                                */
+#define PC_TYP_TYP11_Msk                  (0x800UL)                 /*!< PC TYP: TYP11 (Bitfield-Mask: 0x01)                   */
+#define PC_TYP_TYP10_Pos                  (10UL)                    /*!< PC TYP: TYP10 (Bit 10)                                */
+#define PC_TYP_TYP10_Msk                  (0x400UL)                 /*!< PC TYP: TYP10 (Bitfield-Mask: 0x01)                   */
+#define PC_TYP_TYP9_Pos                   (9UL)                     /*!< PC TYP: TYP9 (Bit 9)                                  */
+#define PC_TYP_TYP9_Msk                   (0x200UL)                 /*!< PC TYP: TYP9 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP8_Pos                   (8UL)                     /*!< PC TYP: TYP8 (Bit 8)                                  */
+#define PC_TYP_TYP8_Msk                   (0x100UL)                 /*!< PC TYP: TYP8 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP7_Pos                   (7UL)                     /*!< PC TYP: TYP7 (Bit 7)                                  */
+#define PC_TYP_TYP7_Msk                   (0x80UL)                  /*!< PC TYP: TYP7 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP6_Pos                   (6UL)                     /*!< PC TYP: TYP6 (Bit 6)                                  */
+#define PC_TYP_TYP6_Msk                   (0x40UL)                  /*!< PC TYP: TYP6 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP5_Pos                   (5UL)                     /*!< PC TYP: TYP5 (Bit 5)                                  */
+#define PC_TYP_TYP5_Msk                   (0x20UL)                  /*!< PC TYP: TYP5 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP4_Pos                   (4UL)                     /*!< PC TYP: TYP4 (Bit 4)                                  */
+#define PC_TYP_TYP4_Msk                   (0x10UL)                  /*!< PC TYP: TYP4 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP3_Pos                   (3UL)                     /*!< PC TYP: TYP3 (Bit 3)                                  */
+#define PC_TYP_TYP3_Msk                   (0x8UL)                   /*!< PC TYP: TYP3 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP2_Pos                   (2UL)                     /*!< PC TYP: TYP2 (Bit 2)                                  */
+#define PC_TYP_TYP2_Msk                   (0x4UL)                   /*!< PC TYP: TYP2 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP1_Pos                   (1UL)                     /*!< PC TYP: TYP1 (Bit 1)                                  */
+#define PC_TYP_TYP1_Msk                   (0x2UL)                   /*!< PC TYP: TYP1 (Bitfield-Mask: 0x01)                    */
+#define PC_TYP_TYP0_Pos                   (0UL)                     /*!< PC TYP: TYP0 (Bit 0)                                  */
+#define PC_TYP_TYP0_Msk                   (0x1UL)                   /*!< PC TYP: TYP0 (Bitfield-Mask: 0x01)                    */
+/* =========================================================  AFSR1  ========================================================= */
+#define PC_AFSR1_AFSR7_Pos                (28UL)                    /*!< PC AFSR1: AFSR7 (Bit 28)                              */
+#define PC_AFSR1_AFSR7_Msk                (0xf0000000UL)            /*!< PC AFSR1: AFSR7 (Bitfield-Mask: 0x0f)                 */
+#define PC_AFSR1_AFSR6_Pos                (24UL)                    /*!< PC AFSR1: AFSR6 (Bit 24)                              */
+#define PC_AFSR1_AFSR6_Msk                (0xf000000UL)             /*!< PC AFSR1: AFSR6 (Bitfield-Mask: 0x0f)                 */
+#define PC_AFSR1_AFSR5_Pos                (20UL)                    /*!< PC AFSR1: AFSR5 (Bit 20)                              */
+#define PC_AFSR1_AFSR5_Msk                (0xf00000UL)              /*!< PC AFSR1: AFSR5 (Bitfield-Mask: 0x0f)                 */
+#define PC_AFSR1_AFSR4_Pos                (16UL)                    /*!< PC AFSR1: AFSR4 (Bit 16)                              */
+#define PC_AFSR1_AFSR4_Msk                (0xf0000UL)               /*!< PC AFSR1: AFSR4 (Bitfield-Mask: 0x0f)                 */
+#define PC_AFSR1_AFSR3_Pos                (12UL)                    /*!< PC AFSR1: AFSR3 (Bit 12)                              */
+#define PC_AFSR1_AFSR3_Msk                (0xf000UL)                /*!< PC AFSR1: AFSR3 (Bitfield-Mask: 0x0f)                 */
+#define PC_AFSR1_AFSR2_Pos                (8UL)                     /*!< PC AFSR1: AFSR2 (Bit 8)                               */
+#define PC_AFSR1_AFSR2_Msk                (0xf00UL)                 /*!< PC AFSR1: AFSR2 (Bitfield-Mask: 0x0f)                 */
+#define PC_AFSR1_AFSR1_Pos                (4UL)                     /*!< PC AFSR1: AFSR1 (Bit 4)                               */
+#define PC_AFSR1_AFSR1_Msk                (0xf0UL)                  /*!< PC AFSR1: AFSR1 (Bitfield-Mask: 0x0f)                 */
+#define PC_AFSR1_AFSR0_Pos                (0UL)                     /*!< PC AFSR1: AFSR0 (Bit 0)                               */
+#define PC_AFSR1_AFSR0_Msk                (0xfUL)                   /*!< PC AFSR1: AFSR0 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  AFSR2  ========================================================= */
+#define PC_AFSR2_AFSR15_Pos               (28UL)                    /*!< PC AFSR2: AFSR15 (Bit 28)                             */
+#define PC_AFSR2_AFSR15_Msk               (0xf0000000UL)            /*!< PC AFSR2: AFSR15 (Bitfield-Mask: 0x0f)                */
+#define PC_AFSR2_AFSR14_Pos               (24UL)                    /*!< PC AFSR2: AFSR14 (Bit 24)                             */
+#define PC_AFSR2_AFSR14_Msk               (0xf000000UL)             /*!< PC AFSR2: AFSR14 (Bitfield-Mask: 0x0f)                */
+#define PC_AFSR2_AFSR13_Pos               (20UL)                    /*!< PC AFSR2: AFSR13 (Bit 20)                             */
+#define PC_AFSR2_AFSR13_Msk               (0xf00000UL)              /*!< PC AFSR2: AFSR13 (Bitfield-Mask: 0x0f)                */
+#define PC_AFSR2_AFSR12_Pos               (16UL)                    /*!< PC AFSR2: AFSR12 (Bit 16)                             */
+#define PC_AFSR2_AFSR12_Msk               (0xf0000UL)               /*!< PC AFSR2: AFSR12 (Bitfield-Mask: 0x0f)                */
+#define PC_AFSR2_AFSR11_Pos               (12UL)                    /*!< PC AFSR2: AFSR11 (Bit 12)                             */
+#define PC_AFSR2_AFSR11_Msk               (0xf000UL)                /*!< PC AFSR2: AFSR11 (Bitfield-Mask: 0x0f)                */
+#define PC_AFSR2_AFSR10_Pos               (8UL)                     /*!< PC AFSR2: AFSR10 (Bit 8)                              */
+#define PC_AFSR2_AFSR10_Msk               (0xf00UL)                 /*!< PC AFSR2: AFSR10 (Bitfield-Mask: 0x0f)                */
+#define PC_AFSR2_AFSR9_Pos                (4UL)                     /*!< PC AFSR2: AFSR9 (Bit 4)                               */
+#define PC_AFSR2_AFSR9_Msk                (0xf0UL)                  /*!< PC AFSR2: AFSR9 (Bitfield-Mask: 0x0f)                 */
+#define PC_AFSR2_AFSR8_Pos                (0UL)                     /*!< PC AFSR2: AFSR8 (Bit 0)                               */
+#define PC_AFSR2_AFSR8_Msk                (0xfUL)                   /*!< PC AFSR2: AFSR8 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  PUPD  ========================================================== */
+#define PC_PUPD_PUPD15_Pos                (30UL)                    /*!< PC PUPD: PUPD15 (Bit 30)                              */
+#define PC_PUPD_PUPD15_Msk                (0xc0000000UL)            /*!< PC PUPD: PUPD15 (Bitfield-Mask: 0x03)                 */
+#define PC_PUPD_PUPD14_Pos                (28UL)                    /*!< PC PUPD: PUPD14 (Bit 28)                              */
+#define PC_PUPD_PUPD14_Msk                (0x30000000UL)            /*!< PC PUPD: PUPD14 (Bitfield-Mask: 0x03)                 */
+#define PC_PUPD_PUPD13_Pos                (26UL)                    /*!< PC PUPD: PUPD13 (Bit 26)                              */
+#define PC_PUPD_PUPD13_Msk                (0xc000000UL)             /*!< PC PUPD: PUPD13 (Bitfield-Mask: 0x03)                 */
+#define PC_PUPD_PUPD12_Pos                (24UL)                    /*!< PC PUPD: PUPD12 (Bit 24)                              */
+#define PC_PUPD_PUPD12_Msk                (0x3000000UL)             /*!< PC PUPD: PUPD12 (Bitfield-Mask: 0x03)                 */
+#define PC_PUPD_PUPD11_Pos                (22UL)                    /*!< PC PUPD: PUPD11 (Bit 22)                              */
+#define PC_PUPD_PUPD11_Msk                (0xc00000UL)              /*!< PC PUPD: PUPD11 (Bitfield-Mask: 0x03)                 */
+#define PC_PUPD_PUPD10_Pos                (20UL)                    /*!< PC PUPD: PUPD10 (Bit 20)                              */
+#define PC_PUPD_PUPD10_Msk                (0x300000UL)              /*!< PC PUPD: PUPD10 (Bitfield-Mask: 0x03)                 */
+#define PC_PUPD_PUPD9_Pos                 (18UL)                    /*!< PC PUPD: PUPD9 (Bit 18)                               */
+#define PC_PUPD_PUPD9_Msk                 (0xc0000UL)               /*!< PC PUPD: PUPD9 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD8_Pos                 (16UL)                    /*!< PC PUPD: PUPD8 (Bit 16)                               */
+#define PC_PUPD_PUPD8_Msk                 (0x30000UL)               /*!< PC PUPD: PUPD8 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD7_Pos                 (14UL)                    /*!< PC PUPD: PUPD7 (Bit 14)                               */
+#define PC_PUPD_PUPD7_Msk                 (0xc000UL)                /*!< PC PUPD: PUPD7 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD6_Pos                 (12UL)                    /*!< PC PUPD: PUPD6 (Bit 12)                               */
+#define PC_PUPD_PUPD6_Msk                 (0x3000UL)                /*!< PC PUPD: PUPD6 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD5_Pos                 (10UL)                    /*!< PC PUPD: PUPD5 (Bit 10)                               */
+#define PC_PUPD_PUPD5_Msk                 (0xc00UL)                 /*!< PC PUPD: PUPD5 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD4_Pos                 (8UL)                     /*!< PC PUPD: PUPD4 (Bit 8)                                */
+#define PC_PUPD_PUPD4_Msk                 (0x300UL)                 /*!< PC PUPD: PUPD4 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD3_Pos                 (6UL)                     /*!< PC PUPD: PUPD3 (Bit 6)                                */
+#define PC_PUPD_PUPD3_Msk                 (0xc0UL)                  /*!< PC PUPD: PUPD3 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD2_Pos                 (4UL)                     /*!< PC PUPD: PUPD2 (Bit 4)                                */
+#define PC_PUPD_PUPD2_Msk                 (0x30UL)                  /*!< PC PUPD: PUPD2 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD1_Pos                 (2UL)                     /*!< PC PUPD: PUPD1 (Bit 2)                                */
+#define PC_PUPD_PUPD1_Msk                 (0xcUL)                   /*!< PC PUPD: PUPD1 (Bitfield-Mask: 0x03)                  */
+#define PC_PUPD_PUPD0_Pos                 (0UL)                     /*!< PC PUPD: PUPD0 (Bit 0)                                */
+#define PC_PUPD_PUPD0_Msk                 (0x3UL)                   /*!< PC PUPD: PUPD0 (Bitfield-Mask: 0x03)                  */
+/* =========================================================  INDR  ========================================================== */
+#define PC_INDR_INDR15_Pos                (15UL)                    /*!< PC INDR: INDR15 (Bit 15)                              */
+#define PC_INDR_INDR15_Msk                (0x8000UL)                /*!< PC INDR: INDR15 (Bitfield-Mask: 0x01)                 */
+#define PC_INDR_INDR14_Pos                (14UL)                    /*!< PC INDR: INDR14 (Bit 14)                              */
+#define PC_INDR_INDR14_Msk                (0x4000UL)                /*!< PC INDR: INDR14 (Bitfield-Mask: 0x01)                 */
+#define PC_INDR_INDR13_Pos                (13UL)                    /*!< PC INDR: INDR13 (Bit 13)                              */
+#define PC_INDR_INDR13_Msk                (0x2000UL)                /*!< PC INDR: INDR13 (Bitfield-Mask: 0x01)                 */
+#define PC_INDR_INDR12_Pos                (12UL)                    /*!< PC INDR: INDR12 (Bit 12)                              */
+#define PC_INDR_INDR12_Msk                (0x1000UL)                /*!< PC INDR: INDR12 (Bitfield-Mask: 0x01)                 */
+#define PC_INDR_INDR11_Pos                (11UL)                    /*!< PC INDR: INDR11 (Bit 11)                              */
+#define PC_INDR_INDR11_Msk                (0x800UL)                 /*!< PC INDR: INDR11 (Bitfield-Mask: 0x01)                 */
+#define PC_INDR_INDR10_Pos                (10UL)                    /*!< PC INDR: INDR10 (Bit 10)                              */
+#define PC_INDR_INDR10_Msk                (0x400UL)                 /*!< PC INDR: INDR10 (Bitfield-Mask: 0x01)                 */
+#define PC_INDR_INDR9_Pos                 (9UL)                     /*!< PC INDR: INDR9 (Bit 9)                                */
+#define PC_INDR_INDR9_Msk                 (0x200UL)                 /*!< PC INDR: INDR9 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR8_Pos                 (8UL)                     /*!< PC INDR: INDR8 (Bit 8)                                */
+#define PC_INDR_INDR8_Msk                 (0x100UL)                 /*!< PC INDR: INDR8 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR7_Pos                 (7UL)                     /*!< PC INDR: INDR7 (Bit 7)                                */
+#define PC_INDR_INDR7_Msk                 (0x80UL)                  /*!< PC INDR: INDR7 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR6_Pos                 (6UL)                     /*!< PC INDR: INDR6 (Bit 6)                                */
+#define PC_INDR_INDR6_Msk                 (0x40UL)                  /*!< PC INDR: INDR6 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR5_Pos                 (5UL)                     /*!< PC INDR: INDR5 (Bit 5)                                */
+#define PC_INDR_INDR5_Msk                 (0x20UL)                  /*!< PC INDR: INDR5 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR4_Pos                 (4UL)                     /*!< PC INDR: INDR4 (Bit 4)                                */
+#define PC_INDR_INDR4_Msk                 (0x10UL)                  /*!< PC INDR: INDR4 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR3_Pos                 (3UL)                     /*!< PC INDR: INDR3 (Bit 3)                                */
+#define PC_INDR_INDR3_Msk                 (0x8UL)                   /*!< PC INDR: INDR3 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR2_Pos                 (2UL)                     /*!< PC INDR: INDR2 (Bit 2)                                */
+#define PC_INDR_INDR2_Msk                 (0x4UL)                   /*!< PC INDR: INDR2 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR1_Pos                 (1UL)                     /*!< PC INDR: INDR1 (Bit 1)                                */
+#define PC_INDR_INDR1_Msk                 (0x2UL)                   /*!< PC INDR: INDR1 (Bitfield-Mask: 0x01)                  */
+#define PC_INDR_INDR0_Pos                 (0UL)                     /*!< PC INDR: INDR0 (Bit 0)                                */
+#define PC_INDR_INDR0_Msk                 (0x1UL)                   /*!< PC INDR: INDR0 (Bitfield-Mask: 0x01)                  */
+/* =========================================================  OUTDR  ========================================================= */
+#define PC_OUTDR_OUTDR15_Pos              (15UL)                    /*!< PC OUTDR: OUTDR15 (Bit 15)                            */
+#define PC_OUTDR_OUTDR15_Msk              (0x8000UL)                /*!< PC OUTDR: OUTDR15 (Bitfield-Mask: 0x01)               */
+#define PC_OUTDR_OUTDR14_Pos              (14UL)                    /*!< PC OUTDR: OUTDR14 (Bit 14)                            */
+#define PC_OUTDR_OUTDR14_Msk              (0x4000UL)                /*!< PC OUTDR: OUTDR14 (Bitfield-Mask: 0x01)               */
+#define PC_OUTDR_OUTDR13_Pos              (13UL)                    /*!< PC OUTDR: OUTDR13 (Bit 13)                            */
+#define PC_OUTDR_OUTDR13_Msk              (0x2000UL)                /*!< PC OUTDR: OUTDR13 (Bitfield-Mask: 0x01)               */
+#define PC_OUTDR_OUTDR12_Pos              (12UL)                    /*!< PC OUTDR: OUTDR12 (Bit 12)                            */
+#define PC_OUTDR_OUTDR12_Msk              (0x1000UL)                /*!< PC OUTDR: OUTDR12 (Bitfield-Mask: 0x01)               */
+#define PC_OUTDR_OUTDR11_Pos              (11UL)                    /*!< PC OUTDR: OUTDR11 (Bit 11)                            */
+#define PC_OUTDR_OUTDR11_Msk              (0x800UL)                 /*!< PC OUTDR: OUTDR11 (Bitfield-Mask: 0x01)               */
+#define PC_OUTDR_OUTDR10_Pos              (10UL)                    /*!< PC OUTDR: OUTDR10 (Bit 10)                            */
+#define PC_OUTDR_OUTDR10_Msk              (0x400UL)                 /*!< PC OUTDR: OUTDR10 (Bitfield-Mask: 0x01)               */
+#define PC_OUTDR_OUTDR9_Pos               (9UL)                     /*!< PC OUTDR: OUTDR9 (Bit 9)                              */
+#define PC_OUTDR_OUTDR9_Msk               (0x200UL)                 /*!< PC OUTDR: OUTDR9 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR8_Pos               (8UL)                     /*!< PC OUTDR: OUTDR8 (Bit 8)                              */
+#define PC_OUTDR_OUTDR8_Msk               (0x100UL)                 /*!< PC OUTDR: OUTDR8 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR7_Pos               (7UL)                     /*!< PC OUTDR: OUTDR7 (Bit 7)                              */
+#define PC_OUTDR_OUTDR7_Msk               (0x80UL)                  /*!< PC OUTDR: OUTDR7 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR6_Pos               (6UL)                     /*!< PC OUTDR: OUTDR6 (Bit 6)                              */
+#define PC_OUTDR_OUTDR6_Msk               (0x40UL)                  /*!< PC OUTDR: OUTDR6 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR5_Pos               (5UL)                     /*!< PC OUTDR: OUTDR5 (Bit 5)                              */
+#define PC_OUTDR_OUTDR5_Msk               (0x20UL)                  /*!< PC OUTDR: OUTDR5 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR4_Pos               (4UL)                     /*!< PC OUTDR: OUTDR4 (Bit 4)                              */
+#define PC_OUTDR_OUTDR4_Msk               (0x10UL)                  /*!< PC OUTDR: OUTDR4 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR3_Pos               (3UL)                     /*!< PC OUTDR: OUTDR3 (Bit 3)                              */
+#define PC_OUTDR_OUTDR3_Msk               (0x8UL)                   /*!< PC OUTDR: OUTDR3 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR2_Pos               (2UL)                     /*!< PC OUTDR: OUTDR2 (Bit 2)                              */
+#define PC_OUTDR_OUTDR2_Msk               (0x4UL)                   /*!< PC OUTDR: OUTDR2 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR1_Pos               (1UL)                     /*!< PC OUTDR: OUTDR1 (Bit 1)                              */
+#define PC_OUTDR_OUTDR1_Msk               (0x2UL)                   /*!< PC OUTDR: OUTDR1 (Bitfield-Mask: 0x01)                */
+#define PC_OUTDR_OUTDR0_Pos               (0UL)                     /*!< PC OUTDR: OUTDR0 (Bit 0)                              */
+#define PC_OUTDR_OUTDR0_Msk               (0x1UL)                   /*!< PC OUTDR: OUTDR0 (Bitfield-Mask: 0x01)                */
+/* ==========================================================  BSR  ========================================================== */
+#define PC_BSR_BSR15_Pos                  (15UL)                    /*!< PC BSR: BSR15 (Bit 15)                                */
+#define PC_BSR_BSR15_Msk                  (0x8000UL)                /*!< PC BSR: BSR15 (Bitfield-Mask: 0x01)                   */
+#define PC_BSR_BSR14_Pos                  (14UL)                    /*!< PC BSR: BSR14 (Bit 14)                                */
+#define PC_BSR_BSR14_Msk                  (0x4000UL)                /*!< PC BSR: BSR14 (Bitfield-Mask: 0x01)                   */
+#define PC_BSR_BSR13_Pos                  (13UL)                    /*!< PC BSR: BSR13 (Bit 13)                                */
+#define PC_BSR_BSR13_Msk                  (0x2000UL)                /*!< PC BSR: BSR13 (Bitfield-Mask: 0x01)                   */
+#define PC_BSR_BSR12_Pos                  (12UL)                    /*!< PC BSR: BSR12 (Bit 12)                                */
+#define PC_BSR_BSR12_Msk                  (0x1000UL)                /*!< PC BSR: BSR12 (Bitfield-Mask: 0x01)                   */
+#define PC_BSR_BSR11_Pos                  (11UL)                    /*!< PC BSR: BSR11 (Bit 11)                                */
+#define PC_BSR_BSR11_Msk                  (0x800UL)                 /*!< PC BSR: BSR11 (Bitfield-Mask: 0x01)                   */
+#define PC_BSR_BSR10_Pos                  (10UL)                    /*!< PC BSR: BSR10 (Bit 10)                                */
+#define PC_BSR_BSR10_Msk                  (0x400UL)                 /*!< PC BSR: BSR10 (Bitfield-Mask: 0x01)                   */
+#define PC_BSR_BSR9_Pos                   (9UL)                     /*!< PC BSR: BSR9 (Bit 9)                                  */
+#define PC_BSR_BSR9_Msk                   (0x200UL)                 /*!< PC BSR: BSR9 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR8_Pos                   (8UL)                     /*!< PC BSR: BSR8 (Bit 8)                                  */
+#define PC_BSR_BSR8_Msk                   (0x100UL)                 /*!< PC BSR: BSR8 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR7_Pos                   (7UL)                     /*!< PC BSR: BSR7 (Bit 7)                                  */
+#define PC_BSR_BSR7_Msk                   (0x80UL)                  /*!< PC BSR: BSR7 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR6_Pos                   (6UL)                     /*!< PC BSR: BSR6 (Bit 6)                                  */
+#define PC_BSR_BSR6_Msk                   (0x40UL)                  /*!< PC BSR: BSR6 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR5_Pos                   (5UL)                     /*!< PC BSR: BSR5 (Bit 5)                                  */
+#define PC_BSR_BSR5_Msk                   (0x20UL)                  /*!< PC BSR: BSR5 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR4_Pos                   (4UL)                     /*!< PC BSR: BSR4 (Bit 4)                                  */
+#define PC_BSR_BSR4_Msk                   (0x10UL)                  /*!< PC BSR: BSR4 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR3_Pos                   (3UL)                     /*!< PC BSR: BSR3 (Bit 3)                                  */
+#define PC_BSR_BSR3_Msk                   (0x8UL)                   /*!< PC BSR: BSR3 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR2_Pos                   (2UL)                     /*!< PC BSR: BSR2 (Bit 2)                                  */
+#define PC_BSR_BSR2_Msk                   (0x4UL)                   /*!< PC BSR: BSR2 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR1_Pos                   (1UL)                     /*!< PC BSR: BSR1 (Bit 1)                                  */
+#define PC_BSR_BSR1_Msk                   (0x2UL)                   /*!< PC BSR: BSR1 (Bitfield-Mask: 0x01)                    */
+#define PC_BSR_BSR0_Pos                   (0UL)                     /*!< PC BSR: BSR0 (Bit 0)                                  */
+#define PC_BSR_BSR0_Msk                   (0x1UL)                   /*!< PC BSR: BSR0 (Bitfield-Mask: 0x01)                    */
+/* ==========================================================  BCR  ========================================================== */
+#define PC_BCR_BCR15_Pos                  (15UL)                    /*!< PC BCR: BCR15 (Bit 15)                                */
+#define PC_BCR_BCR15_Msk                  (0x8000UL)                /*!< PC BCR: BCR15 (Bitfield-Mask: 0x01)                   */
+#define PC_BCR_BCR14_Pos                  (14UL)                    /*!< PC BCR: BCR14 (Bit 14)                                */
+#define PC_BCR_BCR14_Msk                  (0x4000UL)                /*!< PC BCR: BCR14 (Bitfield-Mask: 0x01)                   */
+#define PC_BCR_BCR13_Pos                  (13UL)                    /*!< PC BCR: BCR13 (Bit 13)                                */
+#define PC_BCR_BCR13_Msk                  (0x2000UL)                /*!< PC BCR: BCR13 (Bitfield-Mask: 0x01)                   */
+#define PC_BCR_BCR12_Pos                  (12UL)                    /*!< PC BCR: BCR12 (Bit 12)                                */
+#define PC_BCR_BCR12_Msk                  (0x1000UL)                /*!< PC BCR: BCR12 (Bitfield-Mask: 0x01)                   */
+#define PC_BCR_BCR11_Pos                  (11UL)                    /*!< PC BCR: BCR11 (Bit 11)                                */
+#define PC_BCR_BCR11_Msk                  (0x800UL)                 /*!< PC BCR: BCR11 (Bitfield-Mask: 0x01)                   */
+#define PC_BCR_BCR10_Pos                  (10UL)                    /*!< PC BCR: BCR10 (Bit 10)                                */
+#define PC_BCR_BCR10_Msk                  (0x400UL)                 /*!< PC BCR: BCR10 (Bitfield-Mask: 0x01)                   */
+#define PC_BCR_BCR9_Pos                   (9UL)                     /*!< PC BCR: BCR9 (Bit 9)                                  */
+#define PC_BCR_BCR9_Msk                   (0x200UL)                 /*!< PC BCR: BCR9 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR8_Pos                   (8UL)                     /*!< PC BCR: BCR8 (Bit 8)                                  */
+#define PC_BCR_BCR8_Msk                   (0x100UL)                 /*!< PC BCR: BCR8 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR7_Pos                   (7UL)                     /*!< PC BCR: BCR7 (Bit 7)                                  */
+#define PC_BCR_BCR7_Msk                   (0x80UL)                  /*!< PC BCR: BCR7 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR6_Pos                   (6UL)                     /*!< PC BCR: BCR6 (Bit 6)                                  */
+#define PC_BCR_BCR6_Msk                   (0x40UL)                  /*!< PC BCR: BCR6 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR5_Pos                   (5UL)                     /*!< PC BCR: BCR5 (Bit 5)                                  */
+#define PC_BCR_BCR5_Msk                   (0x20UL)                  /*!< PC BCR: BCR5 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR4_Pos                   (4UL)                     /*!< PC BCR: BCR4 (Bit 4)                                  */
+#define PC_BCR_BCR4_Msk                   (0x10UL)                  /*!< PC BCR: BCR4 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR3_Pos                   (3UL)                     /*!< PC BCR: BCR3 (Bit 3)                                  */
+#define PC_BCR_BCR3_Msk                   (0x8UL)                   /*!< PC BCR: BCR3 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR2_Pos                   (2UL)                     /*!< PC BCR: BCR2 (Bit 2)                                  */
+#define PC_BCR_BCR2_Msk                   (0x4UL)                   /*!< PC BCR: BCR2 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR1_Pos                   (1UL)                     /*!< PC BCR: BCR1 (Bit 1)                                  */
+#define PC_BCR_BCR1_Msk                   (0x2UL)                   /*!< PC BCR: BCR1 (Bitfield-Mask: 0x01)                    */
+#define PC_BCR_BCR0_Pos                   (0UL)                     /*!< PC BCR: BCR0 (Bit 0)                                  */
+#define PC_BCR_BCR0_Msk                   (0x1UL)                   /*!< PC BCR: BCR0 (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OUTDMSK  ======================================================== */
+#define PC_OUTDMSK_OUTDMSK15_Pos          (15UL)                    /*!< PC OUTDMSK: OUTDMSK15 (Bit 15)                        */
+#define PC_OUTDMSK_OUTDMSK15_Msk          (0x8000UL)                /*!< PC OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)           */
+#define PC_OUTDMSK_OUTDMSK14_Pos          (14UL)                    /*!< PC OUTDMSK: OUTDMSK14 (Bit 14)                        */
+#define PC_OUTDMSK_OUTDMSK14_Msk          (0x4000UL)                /*!< PC OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)           */
+#define PC_OUTDMSK_OUTDMSK13_Pos          (13UL)                    /*!< PC OUTDMSK: OUTDMSK13 (Bit 13)                        */
+#define PC_OUTDMSK_OUTDMSK13_Msk          (0x2000UL)                /*!< PC OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)           */
+#define PC_OUTDMSK_OUTDMSK12_Pos          (12UL)                    /*!< PC OUTDMSK: OUTDMSK12 (Bit 12)                        */
+#define PC_OUTDMSK_OUTDMSK12_Msk          (0x1000UL)                /*!< PC OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)           */
+#define PC_OUTDMSK_OUTDMSK11_Pos          (11UL)                    /*!< PC OUTDMSK: OUTDMSK11 (Bit 11)                        */
+#define PC_OUTDMSK_OUTDMSK11_Msk          (0x800UL)                 /*!< PC OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)           */
+#define PC_OUTDMSK_OUTDMSK10_Pos          (10UL)                    /*!< PC OUTDMSK: OUTDMSK10 (Bit 10)                        */
+#define PC_OUTDMSK_OUTDMSK10_Msk          (0x400UL)                 /*!< PC OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)           */
+#define PC_OUTDMSK_OUTDMSK9_Pos           (9UL)                     /*!< PC OUTDMSK: OUTDMSK9 (Bit 9)                          */
+#define PC_OUTDMSK_OUTDMSK9_Msk           (0x200UL)                 /*!< PC OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK8_Pos           (8UL)                     /*!< PC OUTDMSK: OUTDMSK8 (Bit 8)                          */
+#define PC_OUTDMSK_OUTDMSK8_Msk           (0x100UL)                 /*!< PC OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK7_Pos           (7UL)                     /*!< PC OUTDMSK: OUTDMSK7 (Bit 7)                          */
+#define PC_OUTDMSK_OUTDMSK7_Msk           (0x80UL)                  /*!< PC OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK6_Pos           (6UL)                     /*!< PC OUTDMSK: OUTDMSK6 (Bit 6)                          */
+#define PC_OUTDMSK_OUTDMSK6_Msk           (0x40UL)                  /*!< PC OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK5_Pos           (5UL)                     /*!< PC OUTDMSK: OUTDMSK5 (Bit 5)                          */
+#define PC_OUTDMSK_OUTDMSK5_Msk           (0x20UL)                  /*!< PC OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK4_Pos           (4UL)                     /*!< PC OUTDMSK: OUTDMSK4 (Bit 4)                          */
+#define PC_OUTDMSK_OUTDMSK4_Msk           (0x10UL)                  /*!< PC OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK3_Pos           (3UL)                     /*!< PC OUTDMSK: OUTDMSK3 (Bit 3)                          */
+#define PC_OUTDMSK_OUTDMSK3_Msk           (0x8UL)                   /*!< PC OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK2_Pos           (2UL)                     /*!< PC OUTDMSK: OUTDMSK2 (Bit 2)                          */
+#define PC_OUTDMSK_OUTDMSK2_Msk           (0x4UL)                   /*!< PC OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK1_Pos           (1UL)                     /*!< PC OUTDMSK: OUTDMSK1 (Bit 1)                          */
+#define PC_OUTDMSK_OUTDMSK1_Msk           (0x2UL)                   /*!< PC OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)            */
+#define PC_OUTDMSK_OUTDMSK0_Pos           (0UL)                     /*!< PC OUTDMSK: OUTDMSK0 (Bit 0)                          */
+#define PC_OUTDMSK_OUTDMSK0_Msk           (0x1UL)                   /*!< PC OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)            */
+/* =========================================================  DBCR  ========================================================== */
+#define PC_DBCR_DBCLK_Pos                 (16UL)                    /*!< PC DBCR: DBCLK (Bit 16)                               */
+#define PC_DBCR_DBCLK_Msk                 (0x70000UL)               /*!< PC DBCR: DBCLK (Bitfield-Mask: 0x07)                  */
+#define PC_DBCR_DBEN11_Pos                (11UL)                    /*!< PC DBCR: DBEN11 (Bit 11)                              */
+#define PC_DBCR_DBEN11_Msk                (0x800UL)                 /*!< PC DBCR: DBEN11 (Bitfield-Mask: 0x01)                 */
+#define PC_DBCR_DBEN10_Pos                (10UL)                    /*!< PC DBCR: DBEN10 (Bit 10)                              */
+#define PC_DBCR_DBEN10_Msk                (0x400UL)                 /*!< PC DBCR: DBEN10 (Bitfield-Mask: 0x01)                 */
+#define PC_DBCR_DBEN9_Pos                 (9UL)                     /*!< PC DBCR: DBEN9 (Bit 9)                                */
+#define PC_DBCR_DBEN9_Msk                 (0x200UL)                 /*!< PC DBCR: DBEN9 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN8_Pos                 (8UL)                     /*!< PC DBCR: DBEN8 (Bit 8)                                */
+#define PC_DBCR_DBEN8_Msk                 (0x100UL)                 /*!< PC DBCR: DBEN8 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN7_Pos                 (7UL)                     /*!< PC DBCR: DBEN7 (Bit 7)                                */
+#define PC_DBCR_DBEN7_Msk                 (0x80UL)                  /*!< PC DBCR: DBEN7 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN6_Pos                 (6UL)                     /*!< PC DBCR: DBEN6 (Bit 6)                                */
+#define PC_DBCR_DBEN6_Msk                 (0x40UL)                  /*!< PC DBCR: DBEN6 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN5_Pos                 (5UL)                     /*!< PC DBCR: DBEN5 (Bit 5)                                */
+#define PC_DBCR_DBEN5_Msk                 (0x20UL)                  /*!< PC DBCR: DBEN5 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN4_Pos                 (4UL)                     /*!< PC DBCR: DBEN4 (Bit 4)                                */
+#define PC_DBCR_DBEN4_Msk                 (0x10UL)                  /*!< PC DBCR: DBEN4 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN3_Pos                 (3UL)                     /*!< PC DBCR: DBEN3 (Bit 3)                                */
+#define PC_DBCR_DBEN3_Msk                 (0x8UL)                   /*!< PC DBCR: DBEN3 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN2_Pos                 (2UL)                     /*!< PC DBCR: DBEN2 (Bit 2)                                */
+#define PC_DBCR_DBEN2_Msk                 (0x4UL)                   /*!< PC DBCR: DBEN2 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN1_Pos                 (1UL)                     /*!< PC DBCR: DBEN1 (Bit 1)                                */
+#define PC_DBCR_DBEN1_Msk                 (0x2UL)                   /*!< PC DBCR: DBEN1 (Bitfield-Mask: 0x01)                  */
+#define PC_DBCR_DBEN0_Pos                 (0UL)                     /*!< PC DBCR: DBEN0 (Bit 0)                                */
+#define PC_DBCR_DBEN0_Msk                 (0x1UL)                   /*!< PC DBCR: DBEN0 (Bitfield-Mask: 0x01)                  */
+/* ========================================================  PC_MOD  ========================================================= */
+#define PC_PC_MOD_MODE12_Pos              (24UL)                    /*!< PC PC_MOD: MODE12 (Bit 24)                            */
+#define PC_PC_MOD_MODE12_Msk              (0x3000000UL)             /*!< PC PC_MOD: MODE12 (Bitfield-Mask: 0x03)               */
+#define PC_PC_MOD_MODE11_Pos              (22UL)                    /*!< PC PC_MOD: MODE11 (Bit 22)                            */
+#define PC_PC_MOD_MODE11_Msk              (0xc00000UL)              /*!< PC PC_MOD: MODE11 (Bitfield-Mask: 0x03)               */
+#define PC_PC_MOD_MODE10_Pos              (20UL)                    /*!< PC PC_MOD: MODE10 (Bit 20)                            */
+#define PC_PC_MOD_MODE10_Msk              (0x300000UL)              /*!< PC PC_MOD: MODE10 (Bitfield-Mask: 0x03)               */
+#define PC_PC_MOD_MODE9_Pos               (18UL)                    /*!< PC PC_MOD: MODE9 (Bit 18)                             */
+#define PC_PC_MOD_MODE9_Msk               (0xc0000UL)               /*!< PC PC_MOD: MODE9 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE8_Pos               (16UL)                    /*!< PC PC_MOD: MODE8 (Bit 16)                             */
+#define PC_PC_MOD_MODE8_Msk               (0x30000UL)               /*!< PC PC_MOD: MODE8 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE7_Pos               (14UL)                    /*!< PC PC_MOD: MODE7 (Bit 14)                             */
+#define PC_PC_MOD_MODE7_Msk               (0xc000UL)                /*!< PC PC_MOD: MODE7 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE6_Pos               (12UL)                    /*!< PC PC_MOD: MODE6 (Bit 12)                             */
+#define PC_PC_MOD_MODE6_Msk               (0x3000UL)                /*!< PC PC_MOD: MODE6 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE5_Pos               (10UL)                    /*!< PC PC_MOD: MODE5 (Bit 10)                             */
+#define PC_PC_MOD_MODE5_Msk               (0xc00UL)                 /*!< PC PC_MOD: MODE5 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE4_Pos               (8UL)                     /*!< PC PC_MOD: MODE4 (Bit 8)                              */
+#define PC_PC_MOD_MODE4_Msk               (0x300UL)                 /*!< PC PC_MOD: MODE4 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE3_Pos               (6UL)                     /*!< PC PC_MOD: MODE3 (Bit 6)                              */
+#define PC_PC_MOD_MODE3_Msk               (0xc0UL)                  /*!< PC PC_MOD: MODE3 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE2_Pos               (4UL)                     /*!< PC PC_MOD: MODE2 (Bit 4)                              */
+#define PC_PC_MOD_MODE2_Msk               (0x30UL)                  /*!< PC PC_MOD: MODE2 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE1_Pos               (2UL)                     /*!< PC PC_MOD: MODE1 (Bit 2)                              */
+#define PC_PC_MOD_MODE1_Msk               (0xcUL)                   /*!< PC PC_MOD: MODE1 (Bitfield-Mask: 0x03)                */
+#define PC_PC_MOD_MODE0_Pos               (0UL)                     /*!< PC PC_MOD: MODE0 (Bit 0)                              */
+#define PC_PC_MOD_MODE0_Msk               (0x3UL)                   /*!< PC PC_MOD: MODE0 (Bitfield-Mask: 0x03)                */
+/* ========================================================  PC_TYP  ========================================================= */
+#define PC_PC_TYP_TYP12_Pos               (12UL)                    /*!< PC PC_TYP: TYP12 (Bit 12)                             */
+#define PC_PC_TYP_TYP12_Msk               (0x1000UL)                /*!< PC PC_TYP: TYP12 (Bitfield-Mask: 0x01)                */
+#define PC_PC_TYP_TYP11_Pos               (11UL)                    /*!< PC PC_TYP: TYP11 (Bit 11)                             */
+#define PC_PC_TYP_TYP11_Msk               (0x800UL)                 /*!< PC PC_TYP: TYP11 (Bitfield-Mask: 0x01)                */
+#define PC_PC_TYP_TYP10_Pos               (10UL)                    /*!< PC PC_TYP: TYP10 (Bit 10)                             */
+#define PC_PC_TYP_TYP10_Msk               (0x400UL)                 /*!< PC PC_TYP: TYP10 (Bitfield-Mask: 0x01)                */
+#define PC_PC_TYP_TYP9_Pos                (9UL)                     /*!< PC PC_TYP: TYP9 (Bit 9)                               */
+#define PC_PC_TYP_TYP9_Msk                (0x200UL)                 /*!< PC PC_TYP: TYP9 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP8_Pos                (8UL)                     /*!< PC PC_TYP: TYP8 (Bit 8)                               */
+#define PC_PC_TYP_TYP8_Msk                (0x100UL)                 /*!< PC PC_TYP: TYP8 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP7_Pos                (7UL)                     /*!< PC PC_TYP: TYP7 (Bit 7)                               */
+#define PC_PC_TYP_TYP7_Msk                (0x80UL)                  /*!< PC PC_TYP: TYP7 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP6_Pos                (6UL)                     /*!< PC PC_TYP: TYP6 (Bit 6)                               */
+#define PC_PC_TYP_TYP6_Msk                (0x40UL)                  /*!< PC PC_TYP: TYP6 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP5_Pos                (5UL)                     /*!< PC PC_TYP: TYP5 (Bit 5)                               */
+#define PC_PC_TYP_TYP5_Msk                (0x20UL)                  /*!< PC PC_TYP: TYP5 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP4_Pos                (4UL)                     /*!< PC PC_TYP: TYP4 (Bit 4)                               */
+#define PC_PC_TYP_TYP4_Msk                (0x10UL)                  /*!< PC PC_TYP: TYP4 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP3_Pos                (3UL)                     /*!< PC PC_TYP: TYP3 (Bit 3)                               */
+#define PC_PC_TYP_TYP3_Msk                (0x8UL)                   /*!< PC PC_TYP: TYP3 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP2_Pos                (2UL)                     /*!< PC PC_TYP: TYP2 (Bit 2)                               */
+#define PC_PC_TYP_TYP2_Msk                (0x4UL)                   /*!< PC PC_TYP: TYP2 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP1_Pos                (1UL)                     /*!< PC PC_TYP: TYP1 (Bit 1)                               */
+#define PC_PC_TYP_TYP1_Msk                (0x2UL)                   /*!< PC PC_TYP: TYP1 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_TYP_TYP0_Pos                (0UL)                     /*!< PC PC_TYP: TYP0 (Bit 0)                               */
+#define PC_PC_TYP_TYP0_Msk                (0x1UL)                   /*!< PC PC_TYP: TYP0 (Bitfield-Mask: 0x01)                 */
+/* =======================================================  PC_AFSR1  ======================================================== */
+#define PC_PC_AFSR1_AFSR7_Pos             (28UL)                    /*!< PC PC_AFSR1: AFSR7 (Bit 28)                           */
+#define PC_PC_AFSR1_AFSR7_Msk             (0xf0000000UL)            /*!< PC PC_AFSR1: AFSR7 (Bitfield-Mask: 0x0f)              */
+#define PC_PC_AFSR1_AFSR6_Pos             (24UL)                    /*!< PC PC_AFSR1: AFSR6 (Bit 24)                           */
+#define PC_PC_AFSR1_AFSR6_Msk             (0xf000000UL)             /*!< PC PC_AFSR1: AFSR6 (Bitfield-Mask: 0x0f)              */
+#define PC_PC_AFSR1_AFSR5_Pos             (20UL)                    /*!< PC PC_AFSR1: AFSR5 (Bit 20)                           */
+#define PC_PC_AFSR1_AFSR5_Msk             (0xf00000UL)              /*!< PC PC_AFSR1: AFSR5 (Bitfield-Mask: 0x0f)              */
+#define PC_PC_AFSR1_AFSR4_Pos             (16UL)                    /*!< PC PC_AFSR1: AFSR4 (Bit 16)                           */
+#define PC_PC_AFSR1_AFSR4_Msk             (0xf0000UL)               /*!< PC PC_AFSR1: AFSR4 (Bitfield-Mask: 0x0f)              */
+#define PC_PC_AFSR1_AFSR3_Pos             (12UL)                    /*!< PC PC_AFSR1: AFSR3 (Bit 12)                           */
+#define PC_PC_AFSR1_AFSR3_Msk             (0xf000UL)                /*!< PC PC_AFSR1: AFSR3 (Bitfield-Mask: 0x0f)              */
+#define PC_PC_AFSR1_AFSR2_Pos             (8UL)                     /*!< PC PC_AFSR1: AFSR2 (Bit 8)                            */
+#define PC_PC_AFSR1_AFSR2_Msk             (0xf00UL)                 /*!< PC PC_AFSR1: AFSR2 (Bitfield-Mask: 0x0f)              */
+#define PC_PC_AFSR1_AFSR1_Pos             (4UL)                     /*!< PC PC_AFSR1: AFSR1 (Bit 4)                            */
+#define PC_PC_AFSR1_AFSR1_Msk             (0xf0UL)                  /*!< PC PC_AFSR1: AFSR1 (Bitfield-Mask: 0x0f)              */
+#define PC_PC_AFSR1_AFSR0_Pos             (0UL)                     /*!< PC PC_AFSR1: AFSR0 (Bit 0)                            */
+#define PC_PC_AFSR1_AFSR0_Msk             (0xfUL)                   /*!< PC PC_AFSR1: AFSR0 (Bitfield-Mask: 0x0f)              */
+/* =======================================================  PC_AFSR2  ======================================================== */
+#define PC_PC_AFSR2_AFSR12_Pos            (16UL)                    /*!< PC PC_AFSR2: AFSR12 (Bit 16)                          */
+#define PC_PC_AFSR2_AFSR12_Msk            (0xf0000UL)               /*!< PC PC_AFSR2: AFSR12 (Bitfield-Mask: 0x0f)             */
+#define PC_PC_AFSR2_AFSR11_Pos            (12UL)                    /*!< PC PC_AFSR2: AFSR11 (Bit 12)                          */
+#define PC_PC_AFSR2_AFSR11_Msk            (0xf000UL)                /*!< PC PC_AFSR2: AFSR11 (Bitfield-Mask: 0x0f)             */
+#define PC_PC_AFSR2_AFSR10_Pos            (8UL)                     /*!< PC PC_AFSR2: AFSR10 (Bit 8)                           */
+#define PC_PC_AFSR2_AFSR10_Msk            (0xf00UL)                 /*!< PC PC_AFSR2: AFSR10 (Bitfield-Mask: 0x0f)             */
+#define PC_PC_AFSR2_AFSR9_Pos             (4UL)                     /*!< PC PC_AFSR2: AFSR9 (Bit 4)                            */
+#define PC_PC_AFSR2_AFSR9_Msk             (0xf0UL)                  /*!< PC PC_AFSR2: AFSR9 (Bitfield-Mask: 0x0f)              */
+#define PC_PC_AFSR2_AFSR8_Pos             (0UL)                     /*!< PC PC_AFSR2: AFSR8 (Bit 0)                            */
+#define PC_PC_AFSR2_AFSR8_Msk             (0xfUL)                   /*!< PC PC_AFSR2: AFSR8 (Bitfield-Mask: 0x0f)              */
+/* ========================================================  PC_PUPD  ======================================================== */
+#define PC_PC_PUPD_PUPD12_Pos             (24UL)                    /*!< PC PC_PUPD: PUPD12 (Bit 24)                           */
+#define PC_PC_PUPD_PUPD12_Msk             (0x3000000UL)             /*!< PC PC_PUPD: PUPD12 (Bitfield-Mask: 0x03)              */
+#define PC_PC_PUPD_PUPD11_Pos             (22UL)                    /*!< PC PC_PUPD: PUPD11 (Bit 22)                           */
+#define PC_PC_PUPD_PUPD11_Msk             (0xc00000UL)              /*!< PC PC_PUPD: PUPD11 (Bitfield-Mask: 0x03)              */
+#define PC_PC_PUPD_PUPD10_Pos             (20UL)                    /*!< PC PC_PUPD: PUPD10 (Bit 20)                           */
+#define PC_PC_PUPD_PUPD10_Msk             (0x300000UL)              /*!< PC PC_PUPD: PUPD10 (Bitfield-Mask: 0x03)              */
+#define PC_PC_PUPD_PUPD9_Pos              (18UL)                    /*!< PC PC_PUPD: PUPD9 (Bit 18)                            */
+#define PC_PC_PUPD_PUPD9_Msk              (0xc0000UL)               /*!< PC PC_PUPD: PUPD9 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD8_Pos              (16UL)                    /*!< PC PC_PUPD: PUPD8 (Bit 16)                            */
+#define PC_PC_PUPD_PUPD8_Msk              (0x30000UL)               /*!< PC PC_PUPD: PUPD8 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD7_Pos              (14UL)                    /*!< PC PC_PUPD: PUPD7 (Bit 14)                            */
+#define PC_PC_PUPD_PUPD7_Msk              (0xc000UL)                /*!< PC PC_PUPD: PUPD7 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD6_Pos              (12UL)                    /*!< PC PC_PUPD: PUPD6 (Bit 12)                            */
+#define PC_PC_PUPD_PUPD6_Msk              (0x3000UL)                /*!< PC PC_PUPD: PUPD6 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD5_Pos              (10UL)                    /*!< PC PC_PUPD: PUPD5 (Bit 10)                            */
+#define PC_PC_PUPD_PUPD5_Msk              (0xc00UL)                 /*!< PC PC_PUPD: PUPD5 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD4_Pos              (8UL)                     /*!< PC PC_PUPD: PUPD4 (Bit 8)                             */
+#define PC_PC_PUPD_PUPD4_Msk              (0x300UL)                 /*!< PC PC_PUPD: PUPD4 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD3_Pos              (6UL)                     /*!< PC PC_PUPD: PUPD3 (Bit 6)                             */
+#define PC_PC_PUPD_PUPD3_Msk              (0xc0UL)                  /*!< PC PC_PUPD: PUPD3 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD2_Pos              (4UL)                     /*!< PC PC_PUPD: PUPD2 (Bit 4)                             */
+#define PC_PC_PUPD_PUPD2_Msk              (0x30UL)                  /*!< PC PC_PUPD: PUPD2 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD1_Pos              (2UL)                     /*!< PC PC_PUPD: PUPD1 (Bit 2)                             */
+#define PC_PC_PUPD_PUPD1_Msk              (0xcUL)                   /*!< PC PC_PUPD: PUPD1 (Bitfield-Mask: 0x03)               */
+#define PC_PC_PUPD_PUPD0_Pos              (0UL)                     /*!< PC PC_PUPD: PUPD0 (Bit 0)                             */
+#define PC_PC_PUPD_PUPD0_Msk              (0x3UL)                   /*!< PC PC_PUPD: PUPD0 (Bitfield-Mask: 0x03)               */
+/* ========================================================  PC_INDR  ======================================================== */
+#define PC_PC_INDR_INDR12_Pos             (12UL)                    /*!< PC PC_INDR: INDR12 (Bit 12)                           */
+#define PC_PC_INDR_INDR12_Msk             (0x1000UL)                /*!< PC PC_INDR: INDR12 (Bitfield-Mask: 0x01)              */
+#define PC_PC_INDR_INDR11_Pos             (11UL)                    /*!< PC PC_INDR: INDR11 (Bit 11)                           */
+#define PC_PC_INDR_INDR11_Msk             (0x800UL)                 /*!< PC PC_INDR: INDR11 (Bitfield-Mask: 0x01)              */
+#define PC_PC_INDR_INDR10_Pos             (10UL)                    /*!< PC PC_INDR: INDR10 (Bit 10)                           */
+#define PC_PC_INDR_INDR10_Msk             (0x400UL)                 /*!< PC PC_INDR: INDR10 (Bitfield-Mask: 0x01)              */
+#define PC_PC_INDR_INDR9_Pos              (9UL)                     /*!< PC PC_INDR: INDR9 (Bit 9)                             */
+#define PC_PC_INDR_INDR9_Msk              (0x200UL)                 /*!< PC PC_INDR: INDR9 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR8_Pos              (8UL)                     /*!< PC PC_INDR: INDR8 (Bit 8)                             */
+#define PC_PC_INDR_INDR8_Msk              (0x100UL)                 /*!< PC PC_INDR: INDR8 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR7_Pos              (7UL)                     /*!< PC PC_INDR: INDR7 (Bit 7)                             */
+#define PC_PC_INDR_INDR7_Msk              (0x80UL)                  /*!< PC PC_INDR: INDR7 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR6_Pos              (6UL)                     /*!< PC PC_INDR: INDR6 (Bit 6)                             */
+#define PC_PC_INDR_INDR6_Msk              (0x40UL)                  /*!< PC PC_INDR: INDR6 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR5_Pos              (5UL)                     /*!< PC PC_INDR: INDR5 (Bit 5)                             */
+#define PC_PC_INDR_INDR5_Msk              (0x20UL)                  /*!< PC PC_INDR: INDR5 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR4_Pos              (4UL)                     /*!< PC PC_INDR: INDR4 (Bit 4)                             */
+#define PC_PC_INDR_INDR4_Msk              (0x10UL)                  /*!< PC PC_INDR: INDR4 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR3_Pos              (3UL)                     /*!< PC PC_INDR: INDR3 (Bit 3)                             */
+#define PC_PC_INDR_INDR3_Msk              (0x8UL)                   /*!< PC PC_INDR: INDR3 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR2_Pos              (2UL)                     /*!< PC PC_INDR: INDR2 (Bit 2)                             */
+#define PC_PC_INDR_INDR2_Msk              (0x4UL)                   /*!< PC PC_INDR: INDR2 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR1_Pos              (1UL)                     /*!< PC PC_INDR: INDR1 (Bit 1)                             */
+#define PC_PC_INDR_INDR1_Msk              (0x2UL)                   /*!< PC PC_INDR: INDR1 (Bitfield-Mask: 0x01)               */
+#define PC_PC_INDR_INDR0_Pos              (0UL)                     /*!< PC PC_INDR: INDR0 (Bit 0)                             */
+#define PC_PC_INDR_INDR0_Msk              (0x1UL)                   /*!< PC PC_INDR: INDR0 (Bitfield-Mask: 0x01)               */
+/* =======================================================  PC_OUTDR  ======================================================== */
+#define PC_PC_OUTDR_OUTDR12_Pos           (12UL)                    /*!< PC PC_OUTDR: OUTDR12 (Bit 12)                         */
+#define PC_PC_OUTDR_OUTDR12_Msk           (0x1000UL)                /*!< PC PC_OUTDR: OUTDR12 (Bitfield-Mask: 0x01)            */
+#define PC_PC_OUTDR_OUTDR11_Pos           (11UL)                    /*!< PC PC_OUTDR: OUTDR11 (Bit 11)                         */
+#define PC_PC_OUTDR_OUTDR11_Msk           (0x800UL)                 /*!< PC PC_OUTDR: OUTDR11 (Bitfield-Mask: 0x01)            */
+#define PC_PC_OUTDR_OUTDR10_Pos           (10UL)                    /*!< PC PC_OUTDR: OUTDR10 (Bit 10)                         */
+#define PC_PC_OUTDR_OUTDR10_Msk           (0x400UL)                 /*!< PC PC_OUTDR: OUTDR10 (Bitfield-Mask: 0x01)            */
+#define PC_PC_OUTDR_OUTDR9_Pos            (9UL)                     /*!< PC PC_OUTDR: OUTDR9 (Bit 9)                           */
+#define PC_PC_OUTDR_OUTDR9_Msk            (0x200UL)                 /*!< PC PC_OUTDR: OUTDR9 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR8_Pos            (8UL)                     /*!< PC PC_OUTDR: OUTDR8 (Bit 8)                           */
+#define PC_PC_OUTDR_OUTDR8_Msk            (0x100UL)                 /*!< PC PC_OUTDR: OUTDR8 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR7_Pos            (7UL)                     /*!< PC PC_OUTDR: OUTDR7 (Bit 7)                           */
+#define PC_PC_OUTDR_OUTDR7_Msk            (0x80UL)                  /*!< PC PC_OUTDR: OUTDR7 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR6_Pos            (6UL)                     /*!< PC PC_OUTDR: OUTDR6 (Bit 6)                           */
+#define PC_PC_OUTDR_OUTDR6_Msk            (0x40UL)                  /*!< PC PC_OUTDR: OUTDR6 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR5_Pos            (5UL)                     /*!< PC PC_OUTDR: OUTDR5 (Bit 5)                           */
+#define PC_PC_OUTDR_OUTDR5_Msk            (0x20UL)                  /*!< PC PC_OUTDR: OUTDR5 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR4_Pos            (4UL)                     /*!< PC PC_OUTDR: OUTDR4 (Bit 4)                           */
+#define PC_PC_OUTDR_OUTDR4_Msk            (0x10UL)                  /*!< PC PC_OUTDR: OUTDR4 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR3_Pos            (3UL)                     /*!< PC PC_OUTDR: OUTDR3 (Bit 3)                           */
+#define PC_PC_OUTDR_OUTDR3_Msk            (0x8UL)                   /*!< PC PC_OUTDR: OUTDR3 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR2_Pos            (2UL)                     /*!< PC PC_OUTDR: OUTDR2 (Bit 2)                           */
+#define PC_PC_OUTDR_OUTDR2_Msk            (0x4UL)                   /*!< PC PC_OUTDR: OUTDR2 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR1_Pos            (1UL)                     /*!< PC PC_OUTDR: OUTDR1 (Bit 1)                           */
+#define PC_PC_OUTDR_OUTDR1_Msk            (0x2UL)                   /*!< PC PC_OUTDR: OUTDR1 (Bitfield-Mask: 0x01)             */
+#define PC_PC_OUTDR_OUTDR0_Pos            (0UL)                     /*!< PC PC_OUTDR: OUTDR0 (Bit 0)                           */
+#define PC_PC_OUTDR_OUTDR0_Msk            (0x1UL)                   /*!< PC PC_OUTDR: OUTDR0 (Bitfield-Mask: 0x01)             */
+/* ========================================================  PC_BSR  ========================================================= */
+#define PC_PC_BSR_BSR12_Pos               (12UL)                    /*!< PC PC_BSR: BSR12 (Bit 12)                             */
+#define PC_PC_BSR_BSR12_Msk               (0x1000UL)                /*!< PC PC_BSR: BSR12 (Bitfield-Mask: 0x01)                */
+#define PC_PC_BSR_BSR11_Pos               (11UL)                    /*!< PC PC_BSR: BSR11 (Bit 11)                             */
+#define PC_PC_BSR_BSR11_Msk               (0x800UL)                 /*!< PC PC_BSR: BSR11 (Bitfield-Mask: 0x01)                */
+#define PC_PC_BSR_BSR10_Pos               (10UL)                    /*!< PC PC_BSR: BSR10 (Bit 10)                             */
+#define PC_PC_BSR_BSR10_Msk               (0x400UL)                 /*!< PC PC_BSR: BSR10 (Bitfield-Mask: 0x01)                */
+#define PC_PC_BSR_BSR9_Pos                (9UL)                     /*!< PC PC_BSR: BSR9 (Bit 9)                               */
+#define PC_PC_BSR_BSR9_Msk                (0x200UL)                 /*!< PC PC_BSR: BSR9 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR8_Pos                (8UL)                     /*!< PC PC_BSR: BSR8 (Bit 8)                               */
+#define PC_PC_BSR_BSR8_Msk                (0x100UL)                 /*!< PC PC_BSR: BSR8 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR7_Pos                (7UL)                     /*!< PC PC_BSR: BSR7 (Bit 7)                               */
+#define PC_PC_BSR_BSR7_Msk                (0x80UL)                  /*!< PC PC_BSR: BSR7 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR6_Pos                (6UL)                     /*!< PC PC_BSR: BSR6 (Bit 6)                               */
+#define PC_PC_BSR_BSR6_Msk                (0x40UL)                  /*!< PC PC_BSR: BSR6 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR5_Pos                (5UL)                     /*!< PC PC_BSR: BSR5 (Bit 5)                               */
+#define PC_PC_BSR_BSR5_Msk                (0x20UL)                  /*!< PC PC_BSR: BSR5 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR4_Pos                (4UL)                     /*!< PC PC_BSR: BSR4 (Bit 4)                               */
+#define PC_PC_BSR_BSR4_Msk                (0x10UL)                  /*!< PC PC_BSR: BSR4 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR3_Pos                (3UL)                     /*!< PC PC_BSR: BSR3 (Bit 3)                               */
+#define PC_PC_BSR_BSR3_Msk                (0x8UL)                   /*!< PC PC_BSR: BSR3 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR2_Pos                (2UL)                     /*!< PC PC_BSR: BSR2 (Bit 2)                               */
+#define PC_PC_BSR_BSR2_Msk                (0x4UL)                   /*!< PC PC_BSR: BSR2 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR1_Pos                (1UL)                     /*!< PC PC_BSR: BSR1 (Bit 1)                               */
+#define PC_PC_BSR_BSR1_Msk                (0x2UL)                   /*!< PC PC_BSR: BSR1 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BSR_BSR0_Pos                (0UL)                     /*!< PC PC_BSR: BSR0 (Bit 0)                               */
+#define PC_PC_BSR_BSR0_Msk                (0x1UL)                   /*!< PC PC_BSR: BSR0 (Bitfield-Mask: 0x01)                 */
+/* ========================================================  PC_BCR  ========================================================= */
+#define PC_PC_BCR_BCR12_Pos               (12UL)                    /*!< PC PC_BCR: BCR12 (Bit 12)                             */
+#define PC_PC_BCR_BCR12_Msk               (0x1000UL)                /*!< PC PC_BCR: BCR12 (Bitfield-Mask: 0x01)                */
+#define PC_PC_BCR_BCR11_Pos               (11UL)                    /*!< PC PC_BCR: BCR11 (Bit 11)                             */
+#define PC_PC_BCR_BCR11_Msk               (0x800UL)                 /*!< PC PC_BCR: BCR11 (Bitfield-Mask: 0x01)                */
+#define PC_PC_BCR_BCR10_Pos               (10UL)                    /*!< PC PC_BCR: BCR10 (Bit 10)                             */
+#define PC_PC_BCR_BCR10_Msk               (0x400UL)                 /*!< PC PC_BCR: BCR10 (Bitfield-Mask: 0x01)                */
+#define PC_PC_BCR_BCR9_Pos                (9UL)                     /*!< PC PC_BCR: BCR9 (Bit 9)                               */
+#define PC_PC_BCR_BCR9_Msk                (0x200UL)                 /*!< PC PC_BCR: BCR9 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR8_Pos                (8UL)                     /*!< PC PC_BCR: BCR8 (Bit 8)                               */
+#define PC_PC_BCR_BCR8_Msk                (0x100UL)                 /*!< PC PC_BCR: BCR8 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR7_Pos                (7UL)                     /*!< PC PC_BCR: BCR7 (Bit 7)                               */
+#define PC_PC_BCR_BCR7_Msk                (0x80UL)                  /*!< PC PC_BCR: BCR7 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR6_Pos                (6UL)                     /*!< PC PC_BCR: BCR6 (Bit 6)                               */
+#define PC_PC_BCR_BCR6_Msk                (0x40UL)                  /*!< PC PC_BCR: BCR6 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR5_Pos                (5UL)                     /*!< PC PC_BCR: BCR5 (Bit 5)                               */
+#define PC_PC_BCR_BCR5_Msk                (0x20UL)                  /*!< PC PC_BCR: BCR5 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR4_Pos                (4UL)                     /*!< PC PC_BCR: BCR4 (Bit 4)                               */
+#define PC_PC_BCR_BCR4_Msk                (0x10UL)                  /*!< PC PC_BCR: BCR4 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR3_Pos                (3UL)                     /*!< PC PC_BCR: BCR3 (Bit 3)                               */
+#define PC_PC_BCR_BCR3_Msk                (0x8UL)                   /*!< PC PC_BCR: BCR3 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR2_Pos                (2UL)                     /*!< PC PC_BCR: BCR2 (Bit 2)                               */
+#define PC_PC_BCR_BCR2_Msk                (0x4UL)                   /*!< PC PC_BCR: BCR2 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR1_Pos                (1UL)                     /*!< PC PC_BCR: BCR1 (Bit 1)                               */
+#define PC_PC_BCR_BCR1_Msk                (0x2UL)                   /*!< PC PC_BCR: BCR1 (Bitfield-Mask: 0x01)                 */
+#define PC_PC_BCR_BCR0_Pos                (0UL)                     /*!< PC PC_BCR: BCR0 (Bit 0)                               */
+#define PC_PC_BCR_BCR0_Msk                (0x1UL)                   /*!< PC PC_BCR: BCR0 (Bitfield-Mask: 0x01)                 */
+/* ======================================================  PC_OUTDMSK  ======================================================= */
+#define PC_PC_OUTDMSK_OUTDMSK12_Pos       (12UL)                    /*!< PC PC_OUTDMSK: OUTDMSK12 (Bit 12)                     */
+#define PC_PC_OUTDMSK_OUTDMSK12_Msk       (0x1000UL)                /*!< PC PC_OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)        */
+#define PC_PC_OUTDMSK_OUTDMSK11_Pos       (11UL)                    /*!< PC PC_OUTDMSK: OUTDMSK11 (Bit 11)                     */
+#define PC_PC_OUTDMSK_OUTDMSK11_Msk       (0x800UL)                 /*!< PC PC_OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)        */
+#define PC_PC_OUTDMSK_OUTDMSK10_Pos       (10UL)                    /*!< PC PC_OUTDMSK: OUTDMSK10 (Bit 10)                     */
+#define PC_PC_OUTDMSK_OUTDMSK10_Msk       (0x400UL)                 /*!< PC PC_OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)        */
+#define PC_PC_OUTDMSK_OUTDMSK9_Pos        (9UL)                     /*!< PC PC_OUTDMSK: OUTDMSK9 (Bit 9)                       */
+#define PC_PC_OUTDMSK_OUTDMSK9_Msk        (0x200UL)                 /*!< PC PC_OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK8_Pos        (8UL)                     /*!< PC PC_OUTDMSK: OUTDMSK8 (Bit 8)                       */
+#define PC_PC_OUTDMSK_OUTDMSK8_Msk        (0x100UL)                 /*!< PC PC_OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK7_Pos        (7UL)                     /*!< PC PC_OUTDMSK: OUTDMSK7 (Bit 7)                       */
+#define PC_PC_OUTDMSK_OUTDMSK7_Msk        (0x80UL)                  /*!< PC PC_OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK6_Pos        (6UL)                     /*!< PC PC_OUTDMSK: OUTDMSK6 (Bit 6)                       */
+#define PC_PC_OUTDMSK_OUTDMSK6_Msk        (0x40UL)                  /*!< PC PC_OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK5_Pos        (5UL)                     /*!< PC PC_OUTDMSK: OUTDMSK5 (Bit 5)                       */
+#define PC_PC_OUTDMSK_OUTDMSK5_Msk        (0x20UL)                  /*!< PC PC_OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK4_Pos        (4UL)                     /*!< PC PC_OUTDMSK: OUTDMSK4 (Bit 4)                       */
+#define PC_PC_OUTDMSK_OUTDMSK4_Msk        (0x10UL)                  /*!< PC PC_OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK3_Pos        (3UL)                     /*!< PC PC_OUTDMSK: OUTDMSK3 (Bit 3)                       */
+#define PC_PC_OUTDMSK_OUTDMSK3_Msk        (0x8UL)                   /*!< PC PC_OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK2_Pos        (2UL)                     /*!< PC PC_OUTDMSK: OUTDMSK2 (Bit 2)                       */
+#define PC_PC_OUTDMSK_OUTDMSK2_Msk        (0x4UL)                   /*!< PC PC_OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK1_Pos        (1UL)                     /*!< PC PC_OUTDMSK: OUTDMSK1 (Bit 1)                       */
+#define PC_PC_OUTDMSK_OUTDMSK1_Msk        (0x2UL)                   /*!< PC PC_OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)         */
+#define PC_PC_OUTDMSK_OUTDMSK0_Pos        (0UL)                     /*!< PC PC_OUTDMSK: OUTDMSK0 (Bit 0)                       */
+#define PC_PC_OUTDMSK_OUTDMSK0_Msk        (0x1UL)                   /*!< PC PC_OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)         */
+/* ========================================================  PC_DBCR  ======================================================== */
+#define PC_PC_DBCR_DBCLK_Pos              (16UL)                    /*!< PC PC_DBCR: DBCLK (Bit 16)                            */
+#define PC_PC_DBCR_DBCLK_Msk              (0x70000UL)               /*!< PC PC_DBCR: DBCLK (Bitfield-Mask: 0x07)               */
+#define PC_PC_DBCR_DBEN3_Pos              (3UL)                     /*!< PC PC_DBCR: DBEN3 (Bit 3)                             */
+#define PC_PC_DBCR_DBEN3_Msk              (0x8UL)                   /*!< PC PC_DBCR: DBEN3 (Bitfield-Mask: 0x01)               */
+#define PC_PC_DBCR_DBEN2_Pos              (2UL)                     /*!< PC PC_DBCR: DBEN2 (Bit 2)                             */
+#define PC_PC_DBCR_DBEN2_Msk              (0x4UL)                   /*!< PC PC_DBCR: DBEN2 (Bitfield-Mask: 0x01)               */
+#define PC_PC_DBCR_DBEN1_Pos              (1UL)                     /*!< PC PC_DBCR: DBEN1 (Bit 1)                             */
+#define PC_PC_DBCR_DBEN1_Msk              (0x2UL)                   /*!< PC PC_DBCR: DBEN1 (Bitfield-Mask: 0x01)               */
+#define PC_PC_DBCR_DBEN0_Pos              (0UL)                     /*!< PC PC_DBCR: DBEN0 (Bit 0)                             */
+#define PC_PC_DBCR_DBEN0_Msk              (0x1UL)                   /*!< PC PC_DBCR: DBEN0 (Bitfield-Mask: 0x01)               */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PD                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+#define PD_MOD_MODE15_Pos                 (30UL)                    /*!< PD MOD: MODE15 (Bit 30)                               */
+#define PD_MOD_MODE15_Msk                 (0xc0000000UL)            /*!< PD MOD: MODE15 (Bitfield-Mask: 0x03)                  */
+#define PD_MOD_MODE14_Pos                 (28UL)                    /*!< PD MOD: MODE14 (Bit 28)                               */
+#define PD_MOD_MODE14_Msk                 (0x30000000UL)            /*!< PD MOD: MODE14 (Bitfield-Mask: 0x03)                  */
+#define PD_MOD_MODE13_Pos                 (26UL)                    /*!< PD MOD: MODE13 (Bit 26)                               */
+#define PD_MOD_MODE13_Msk                 (0xc000000UL)             /*!< PD MOD: MODE13 (Bitfield-Mask: 0x03)                  */
+#define PD_MOD_MODE12_Pos                 (24UL)                    /*!< PD MOD: MODE12 (Bit 24)                               */
+#define PD_MOD_MODE12_Msk                 (0x3000000UL)             /*!< PD MOD: MODE12 (Bitfield-Mask: 0x03)                  */
+#define PD_MOD_MODE11_Pos                 (22UL)                    /*!< PD MOD: MODE11 (Bit 22)                               */
+#define PD_MOD_MODE11_Msk                 (0xc00000UL)              /*!< PD MOD: MODE11 (Bitfield-Mask: 0x03)                  */
+#define PD_MOD_MODE10_Pos                 (20UL)                    /*!< PD MOD: MODE10 (Bit 20)                               */
+#define PD_MOD_MODE10_Msk                 (0x300000UL)              /*!< PD MOD: MODE10 (Bitfield-Mask: 0x03)                  */
+#define PD_MOD_MODE9_Pos                  (18UL)                    /*!< PD MOD: MODE9 (Bit 18)                                */
+#define PD_MOD_MODE9_Msk                  (0xc0000UL)               /*!< PD MOD: MODE9 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE8_Pos                  (16UL)                    /*!< PD MOD: MODE8 (Bit 16)                                */
+#define PD_MOD_MODE8_Msk                  (0x30000UL)               /*!< PD MOD: MODE8 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE7_Pos                  (14UL)                    /*!< PD MOD: MODE7 (Bit 14)                                */
+#define PD_MOD_MODE7_Msk                  (0xc000UL)                /*!< PD MOD: MODE7 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE6_Pos                  (12UL)                    /*!< PD MOD: MODE6 (Bit 12)                                */
+#define PD_MOD_MODE6_Msk                  (0x3000UL)                /*!< PD MOD: MODE6 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE5_Pos                  (10UL)                    /*!< PD MOD: MODE5 (Bit 10)                                */
+#define PD_MOD_MODE5_Msk                  (0xc00UL)                 /*!< PD MOD: MODE5 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE4_Pos                  (8UL)                     /*!< PD MOD: MODE4 (Bit 8)                                 */
+#define PD_MOD_MODE4_Msk                  (0x300UL)                 /*!< PD MOD: MODE4 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE3_Pos                  (6UL)                     /*!< PD MOD: MODE3 (Bit 6)                                 */
+#define PD_MOD_MODE3_Msk                  (0xc0UL)                  /*!< PD MOD: MODE3 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE2_Pos                  (4UL)                     /*!< PD MOD: MODE2 (Bit 4)                                 */
+#define PD_MOD_MODE2_Msk                  (0x30UL)                  /*!< PD MOD: MODE2 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE1_Pos                  (2UL)                     /*!< PD MOD: MODE1 (Bit 2)                                 */
+#define PD_MOD_MODE1_Msk                  (0xcUL)                   /*!< PD MOD: MODE1 (Bitfield-Mask: 0x03)                   */
+#define PD_MOD_MODE0_Pos                  (0UL)                     /*!< PD MOD: MODE0 (Bit 0)                                 */
+#define PD_MOD_MODE0_Msk                  (0x3UL)                   /*!< PD MOD: MODE0 (Bitfield-Mask: 0x03)                   */
+/* ==========================================================  TYP  ========================================================== */
+#define PD_TYP_TYP15_Pos                  (15UL)                    /*!< PD TYP: TYP15 (Bit 15)                                */
+#define PD_TYP_TYP15_Msk                  (0x8000UL)                /*!< PD TYP: TYP15 (Bitfield-Mask: 0x01)                   */
+#define PD_TYP_TYP14_Pos                  (14UL)                    /*!< PD TYP: TYP14 (Bit 14)                                */
+#define PD_TYP_TYP14_Msk                  (0x4000UL)                /*!< PD TYP: TYP14 (Bitfield-Mask: 0x01)                   */
+#define PD_TYP_TYP13_Pos                  (13UL)                    /*!< PD TYP: TYP13 (Bit 13)                                */
+#define PD_TYP_TYP13_Msk                  (0x2000UL)                /*!< PD TYP: TYP13 (Bitfield-Mask: 0x01)                   */
+#define PD_TYP_TYP12_Pos                  (12UL)                    /*!< PD TYP: TYP12 (Bit 12)                                */
+#define PD_TYP_TYP12_Msk                  (0x1000UL)                /*!< PD TYP: TYP12 (Bitfield-Mask: 0x01)                   */
+#define PD_TYP_TYP11_Pos                  (11UL)                    /*!< PD TYP: TYP11 (Bit 11)                                */
+#define PD_TYP_TYP11_Msk                  (0x800UL)                 /*!< PD TYP: TYP11 (Bitfield-Mask: 0x01)                   */
+#define PD_TYP_TYP10_Pos                  (10UL)                    /*!< PD TYP: TYP10 (Bit 10)                                */
+#define PD_TYP_TYP10_Msk                  (0x400UL)                 /*!< PD TYP: TYP10 (Bitfield-Mask: 0x01)                   */
+#define PD_TYP_TYP9_Pos                   (9UL)                     /*!< PD TYP: TYP9 (Bit 9)                                  */
+#define PD_TYP_TYP9_Msk                   (0x200UL)                 /*!< PD TYP: TYP9 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP8_Pos                   (8UL)                     /*!< PD TYP: TYP8 (Bit 8)                                  */
+#define PD_TYP_TYP8_Msk                   (0x100UL)                 /*!< PD TYP: TYP8 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP7_Pos                   (7UL)                     /*!< PD TYP: TYP7 (Bit 7)                                  */
+#define PD_TYP_TYP7_Msk                   (0x80UL)                  /*!< PD TYP: TYP7 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP6_Pos                   (6UL)                     /*!< PD TYP: TYP6 (Bit 6)                                  */
+#define PD_TYP_TYP6_Msk                   (0x40UL)                  /*!< PD TYP: TYP6 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP5_Pos                   (5UL)                     /*!< PD TYP: TYP5 (Bit 5)                                  */
+#define PD_TYP_TYP5_Msk                   (0x20UL)                  /*!< PD TYP: TYP5 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP4_Pos                   (4UL)                     /*!< PD TYP: TYP4 (Bit 4)                                  */
+#define PD_TYP_TYP4_Msk                   (0x10UL)                  /*!< PD TYP: TYP4 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP3_Pos                   (3UL)                     /*!< PD TYP: TYP3 (Bit 3)                                  */
+#define PD_TYP_TYP3_Msk                   (0x8UL)                   /*!< PD TYP: TYP3 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP2_Pos                   (2UL)                     /*!< PD TYP: TYP2 (Bit 2)                                  */
+#define PD_TYP_TYP2_Msk                   (0x4UL)                   /*!< PD TYP: TYP2 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP1_Pos                   (1UL)                     /*!< PD TYP: TYP1 (Bit 1)                                  */
+#define PD_TYP_TYP1_Msk                   (0x2UL)                   /*!< PD TYP: TYP1 (Bitfield-Mask: 0x01)                    */
+#define PD_TYP_TYP0_Pos                   (0UL)                     /*!< PD TYP: TYP0 (Bit 0)                                  */
+#define PD_TYP_TYP0_Msk                   (0x1UL)                   /*!< PD TYP: TYP0 (Bitfield-Mask: 0x01)                    */
+/* =========================================================  AFSR1  ========================================================= */
+#define PD_AFSR1_AFSR7_Pos                (28UL)                    /*!< PD AFSR1: AFSR7 (Bit 28)                              */
+#define PD_AFSR1_AFSR7_Msk                (0xf0000000UL)            /*!< PD AFSR1: AFSR7 (Bitfield-Mask: 0x0f)                 */
+#define PD_AFSR1_AFSR6_Pos                (24UL)                    /*!< PD AFSR1: AFSR6 (Bit 24)                              */
+#define PD_AFSR1_AFSR6_Msk                (0xf000000UL)             /*!< PD AFSR1: AFSR6 (Bitfield-Mask: 0x0f)                 */
+#define PD_AFSR1_AFSR5_Pos                (20UL)                    /*!< PD AFSR1: AFSR5 (Bit 20)                              */
+#define PD_AFSR1_AFSR5_Msk                (0xf00000UL)              /*!< PD AFSR1: AFSR5 (Bitfield-Mask: 0x0f)                 */
+#define PD_AFSR1_AFSR4_Pos                (16UL)                    /*!< PD AFSR1: AFSR4 (Bit 16)                              */
+#define PD_AFSR1_AFSR4_Msk                (0xf0000UL)               /*!< PD AFSR1: AFSR4 (Bitfield-Mask: 0x0f)                 */
+#define PD_AFSR1_AFSR3_Pos                (12UL)                    /*!< PD AFSR1: AFSR3 (Bit 12)                              */
+#define PD_AFSR1_AFSR3_Msk                (0xf000UL)                /*!< PD AFSR1: AFSR3 (Bitfield-Mask: 0x0f)                 */
+#define PD_AFSR1_AFSR2_Pos                (8UL)                     /*!< PD AFSR1: AFSR2 (Bit 8)                               */
+#define PD_AFSR1_AFSR2_Msk                (0xf00UL)                 /*!< PD AFSR1: AFSR2 (Bitfield-Mask: 0x0f)                 */
+#define PD_AFSR1_AFSR1_Pos                (4UL)                     /*!< PD AFSR1: AFSR1 (Bit 4)                               */
+#define PD_AFSR1_AFSR1_Msk                (0xf0UL)                  /*!< PD AFSR1: AFSR1 (Bitfield-Mask: 0x0f)                 */
+#define PD_AFSR1_AFSR0_Pos                (0UL)                     /*!< PD AFSR1: AFSR0 (Bit 0)                               */
+#define PD_AFSR1_AFSR0_Msk                (0xfUL)                   /*!< PD AFSR1: AFSR0 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  AFSR2  ========================================================= */
+#define PD_AFSR2_AFSR15_Pos               (28UL)                    /*!< PD AFSR2: AFSR15 (Bit 28)                             */
+#define PD_AFSR2_AFSR15_Msk               (0xf0000000UL)            /*!< PD AFSR2: AFSR15 (Bitfield-Mask: 0x0f)                */
+#define PD_AFSR2_AFSR14_Pos               (24UL)                    /*!< PD AFSR2: AFSR14 (Bit 24)                             */
+#define PD_AFSR2_AFSR14_Msk               (0xf000000UL)             /*!< PD AFSR2: AFSR14 (Bitfield-Mask: 0x0f)                */
+#define PD_AFSR2_AFSR13_Pos               (20UL)                    /*!< PD AFSR2: AFSR13 (Bit 20)                             */
+#define PD_AFSR2_AFSR13_Msk               (0xf00000UL)              /*!< PD AFSR2: AFSR13 (Bitfield-Mask: 0x0f)                */
+#define PD_AFSR2_AFSR12_Pos               (16UL)                    /*!< PD AFSR2: AFSR12 (Bit 16)                             */
+#define PD_AFSR2_AFSR12_Msk               (0xf0000UL)               /*!< PD AFSR2: AFSR12 (Bitfield-Mask: 0x0f)                */
+#define PD_AFSR2_AFSR11_Pos               (12UL)                    /*!< PD AFSR2: AFSR11 (Bit 12)                             */
+#define PD_AFSR2_AFSR11_Msk               (0xf000UL)                /*!< PD AFSR2: AFSR11 (Bitfield-Mask: 0x0f)                */
+#define PD_AFSR2_AFSR10_Pos               (8UL)                     /*!< PD AFSR2: AFSR10 (Bit 8)                              */
+#define PD_AFSR2_AFSR10_Msk               (0xf00UL)                 /*!< PD AFSR2: AFSR10 (Bitfield-Mask: 0x0f)                */
+#define PD_AFSR2_AFSR9_Pos                (4UL)                     /*!< PD AFSR2: AFSR9 (Bit 4)                               */
+#define PD_AFSR2_AFSR9_Msk                (0xf0UL)                  /*!< PD AFSR2: AFSR9 (Bitfield-Mask: 0x0f)                 */
+#define PD_AFSR2_AFSR8_Pos                (0UL)                     /*!< PD AFSR2: AFSR8 (Bit 0)                               */
+#define PD_AFSR2_AFSR8_Msk                (0xfUL)                   /*!< PD AFSR2: AFSR8 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  PUPD  ========================================================== */
+#define PD_PUPD_PUPD15_Pos                (30UL)                    /*!< PD PUPD: PUPD15 (Bit 30)                              */
+#define PD_PUPD_PUPD15_Msk                (0xc0000000UL)            /*!< PD PUPD: PUPD15 (Bitfield-Mask: 0x03)                 */
+#define PD_PUPD_PUPD14_Pos                (28UL)                    /*!< PD PUPD: PUPD14 (Bit 28)                              */
+#define PD_PUPD_PUPD14_Msk                (0x30000000UL)            /*!< PD PUPD: PUPD14 (Bitfield-Mask: 0x03)                 */
+#define PD_PUPD_PUPD13_Pos                (26UL)                    /*!< PD PUPD: PUPD13 (Bit 26)                              */
+#define PD_PUPD_PUPD13_Msk                (0xc000000UL)             /*!< PD PUPD: PUPD13 (Bitfield-Mask: 0x03)                 */
+#define PD_PUPD_PUPD12_Pos                (24UL)                    /*!< PD PUPD: PUPD12 (Bit 24)                              */
+#define PD_PUPD_PUPD12_Msk                (0x3000000UL)             /*!< PD PUPD: PUPD12 (Bitfield-Mask: 0x03)                 */
+#define PD_PUPD_PUPD11_Pos                (22UL)                    /*!< PD PUPD: PUPD11 (Bit 22)                              */
+#define PD_PUPD_PUPD11_Msk                (0xc00000UL)              /*!< PD PUPD: PUPD11 (Bitfield-Mask: 0x03)                 */
+#define PD_PUPD_PUPD10_Pos                (20UL)                    /*!< PD PUPD: PUPD10 (Bit 20)                              */
+#define PD_PUPD_PUPD10_Msk                (0x300000UL)              /*!< PD PUPD: PUPD10 (Bitfield-Mask: 0x03)                 */
+#define PD_PUPD_PUPD9_Pos                 (18UL)                    /*!< PD PUPD: PUPD9 (Bit 18)                               */
+#define PD_PUPD_PUPD9_Msk                 (0xc0000UL)               /*!< PD PUPD: PUPD9 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD8_Pos                 (16UL)                    /*!< PD PUPD: PUPD8 (Bit 16)                               */
+#define PD_PUPD_PUPD8_Msk                 (0x30000UL)               /*!< PD PUPD: PUPD8 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD7_Pos                 (14UL)                    /*!< PD PUPD: PUPD7 (Bit 14)                               */
+#define PD_PUPD_PUPD7_Msk                 (0xc000UL)                /*!< PD PUPD: PUPD7 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD6_Pos                 (12UL)                    /*!< PD PUPD: PUPD6 (Bit 12)                               */
+#define PD_PUPD_PUPD6_Msk                 (0x3000UL)                /*!< PD PUPD: PUPD6 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD5_Pos                 (10UL)                    /*!< PD PUPD: PUPD5 (Bit 10)                               */
+#define PD_PUPD_PUPD5_Msk                 (0xc00UL)                 /*!< PD PUPD: PUPD5 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD4_Pos                 (8UL)                     /*!< PD PUPD: PUPD4 (Bit 8)                                */
+#define PD_PUPD_PUPD4_Msk                 (0x300UL)                 /*!< PD PUPD: PUPD4 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD3_Pos                 (6UL)                     /*!< PD PUPD: PUPD3 (Bit 6)                                */
+#define PD_PUPD_PUPD3_Msk                 (0xc0UL)                  /*!< PD PUPD: PUPD3 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD2_Pos                 (4UL)                     /*!< PD PUPD: PUPD2 (Bit 4)                                */
+#define PD_PUPD_PUPD2_Msk                 (0x30UL)                  /*!< PD PUPD: PUPD2 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD1_Pos                 (2UL)                     /*!< PD PUPD: PUPD1 (Bit 2)                                */
+#define PD_PUPD_PUPD1_Msk                 (0xcUL)                   /*!< PD PUPD: PUPD1 (Bitfield-Mask: 0x03)                  */
+#define PD_PUPD_PUPD0_Pos                 (0UL)                     /*!< PD PUPD: PUPD0 (Bit 0)                                */
+#define PD_PUPD_PUPD0_Msk                 (0x3UL)                   /*!< PD PUPD: PUPD0 (Bitfield-Mask: 0x03)                  */
+/* =========================================================  INDR  ========================================================== */
+#define PD_INDR_INDR15_Pos                (15UL)                    /*!< PD INDR: INDR15 (Bit 15)                              */
+#define PD_INDR_INDR15_Msk                (0x8000UL)                /*!< PD INDR: INDR15 (Bitfield-Mask: 0x01)                 */
+#define PD_INDR_INDR14_Pos                (14UL)                    /*!< PD INDR: INDR14 (Bit 14)                              */
+#define PD_INDR_INDR14_Msk                (0x4000UL)                /*!< PD INDR: INDR14 (Bitfield-Mask: 0x01)                 */
+#define PD_INDR_INDR13_Pos                (13UL)                    /*!< PD INDR: INDR13 (Bit 13)                              */
+#define PD_INDR_INDR13_Msk                (0x2000UL)                /*!< PD INDR: INDR13 (Bitfield-Mask: 0x01)                 */
+#define PD_INDR_INDR12_Pos                (12UL)                    /*!< PD INDR: INDR12 (Bit 12)                              */
+#define PD_INDR_INDR12_Msk                (0x1000UL)                /*!< PD INDR: INDR12 (Bitfield-Mask: 0x01)                 */
+#define PD_INDR_INDR11_Pos                (11UL)                    /*!< PD INDR: INDR11 (Bit 11)                              */
+#define PD_INDR_INDR11_Msk                (0x800UL)                 /*!< PD INDR: INDR11 (Bitfield-Mask: 0x01)                 */
+#define PD_INDR_INDR10_Pos                (10UL)                    /*!< PD INDR: INDR10 (Bit 10)                              */
+#define PD_INDR_INDR10_Msk                (0x400UL)                 /*!< PD INDR: INDR10 (Bitfield-Mask: 0x01)                 */
+#define PD_INDR_INDR9_Pos                 (9UL)                     /*!< PD INDR: INDR9 (Bit 9)                                */
+#define PD_INDR_INDR9_Msk                 (0x200UL)                 /*!< PD INDR: INDR9 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR8_Pos                 (8UL)                     /*!< PD INDR: INDR8 (Bit 8)                                */
+#define PD_INDR_INDR8_Msk                 (0x100UL)                 /*!< PD INDR: INDR8 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR7_Pos                 (7UL)                     /*!< PD INDR: INDR7 (Bit 7)                                */
+#define PD_INDR_INDR7_Msk                 (0x80UL)                  /*!< PD INDR: INDR7 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR6_Pos                 (6UL)                     /*!< PD INDR: INDR6 (Bit 6)                                */
+#define PD_INDR_INDR6_Msk                 (0x40UL)                  /*!< PD INDR: INDR6 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR5_Pos                 (5UL)                     /*!< PD INDR: INDR5 (Bit 5)                                */
+#define PD_INDR_INDR5_Msk                 (0x20UL)                  /*!< PD INDR: INDR5 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR4_Pos                 (4UL)                     /*!< PD INDR: INDR4 (Bit 4)                                */
+#define PD_INDR_INDR4_Msk                 (0x10UL)                  /*!< PD INDR: INDR4 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR3_Pos                 (3UL)                     /*!< PD INDR: INDR3 (Bit 3)                                */
+#define PD_INDR_INDR3_Msk                 (0x8UL)                   /*!< PD INDR: INDR3 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR2_Pos                 (2UL)                     /*!< PD INDR: INDR2 (Bit 2)                                */
+#define PD_INDR_INDR2_Msk                 (0x4UL)                   /*!< PD INDR: INDR2 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR1_Pos                 (1UL)                     /*!< PD INDR: INDR1 (Bit 1)                                */
+#define PD_INDR_INDR1_Msk                 (0x2UL)                   /*!< PD INDR: INDR1 (Bitfield-Mask: 0x01)                  */
+#define PD_INDR_INDR0_Pos                 (0UL)                     /*!< PD INDR: INDR0 (Bit 0)                                */
+#define PD_INDR_INDR0_Msk                 (0x1UL)                   /*!< PD INDR: INDR0 (Bitfield-Mask: 0x01)                  */
+/* =========================================================  OUTDR  ========================================================= */
+#define PD_OUTDR_OUTDR15_Pos              (15UL)                    /*!< PD OUTDR: OUTDR15 (Bit 15)                            */
+#define PD_OUTDR_OUTDR15_Msk              (0x8000UL)                /*!< PD OUTDR: OUTDR15 (Bitfield-Mask: 0x01)               */
+#define PD_OUTDR_OUTDR14_Pos              (14UL)                    /*!< PD OUTDR: OUTDR14 (Bit 14)                            */
+#define PD_OUTDR_OUTDR14_Msk              (0x4000UL)                /*!< PD OUTDR: OUTDR14 (Bitfield-Mask: 0x01)               */
+#define PD_OUTDR_OUTDR13_Pos              (13UL)                    /*!< PD OUTDR: OUTDR13 (Bit 13)                            */
+#define PD_OUTDR_OUTDR13_Msk              (0x2000UL)                /*!< PD OUTDR: OUTDR13 (Bitfield-Mask: 0x01)               */
+#define PD_OUTDR_OUTDR12_Pos              (12UL)                    /*!< PD OUTDR: OUTDR12 (Bit 12)                            */
+#define PD_OUTDR_OUTDR12_Msk              (0x1000UL)                /*!< PD OUTDR: OUTDR12 (Bitfield-Mask: 0x01)               */
+#define PD_OUTDR_OUTDR11_Pos              (11UL)                    /*!< PD OUTDR: OUTDR11 (Bit 11)                            */
+#define PD_OUTDR_OUTDR11_Msk              (0x800UL)                 /*!< PD OUTDR: OUTDR11 (Bitfield-Mask: 0x01)               */
+#define PD_OUTDR_OUTDR10_Pos              (10UL)                    /*!< PD OUTDR: OUTDR10 (Bit 10)                            */
+#define PD_OUTDR_OUTDR10_Msk              (0x400UL)                 /*!< PD OUTDR: OUTDR10 (Bitfield-Mask: 0x01)               */
+#define PD_OUTDR_OUTDR9_Pos               (9UL)                     /*!< PD OUTDR: OUTDR9 (Bit 9)                              */
+#define PD_OUTDR_OUTDR9_Msk               (0x200UL)                 /*!< PD OUTDR: OUTDR9 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR8_Pos               (8UL)                     /*!< PD OUTDR: OUTDR8 (Bit 8)                              */
+#define PD_OUTDR_OUTDR8_Msk               (0x100UL)                 /*!< PD OUTDR: OUTDR8 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR7_Pos               (7UL)                     /*!< PD OUTDR: OUTDR7 (Bit 7)                              */
+#define PD_OUTDR_OUTDR7_Msk               (0x80UL)                  /*!< PD OUTDR: OUTDR7 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR6_Pos               (6UL)                     /*!< PD OUTDR: OUTDR6 (Bit 6)                              */
+#define PD_OUTDR_OUTDR6_Msk               (0x40UL)                  /*!< PD OUTDR: OUTDR6 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR5_Pos               (5UL)                     /*!< PD OUTDR: OUTDR5 (Bit 5)                              */
+#define PD_OUTDR_OUTDR5_Msk               (0x20UL)                  /*!< PD OUTDR: OUTDR5 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR4_Pos               (4UL)                     /*!< PD OUTDR: OUTDR4 (Bit 4)                              */
+#define PD_OUTDR_OUTDR4_Msk               (0x10UL)                  /*!< PD OUTDR: OUTDR4 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR3_Pos               (3UL)                     /*!< PD OUTDR: OUTDR3 (Bit 3)                              */
+#define PD_OUTDR_OUTDR3_Msk               (0x8UL)                   /*!< PD OUTDR: OUTDR3 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR2_Pos               (2UL)                     /*!< PD OUTDR: OUTDR2 (Bit 2)                              */
+#define PD_OUTDR_OUTDR2_Msk               (0x4UL)                   /*!< PD OUTDR: OUTDR2 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR1_Pos               (1UL)                     /*!< PD OUTDR: OUTDR1 (Bit 1)                              */
+#define PD_OUTDR_OUTDR1_Msk               (0x2UL)                   /*!< PD OUTDR: OUTDR1 (Bitfield-Mask: 0x01)                */
+#define PD_OUTDR_OUTDR0_Pos               (0UL)                     /*!< PD OUTDR: OUTDR0 (Bit 0)                              */
+#define PD_OUTDR_OUTDR0_Msk               (0x1UL)                   /*!< PD OUTDR: OUTDR0 (Bitfield-Mask: 0x01)                */
+/* ==========================================================  BSR  ========================================================== */
+#define PD_BSR_BSR15_Pos                  (15UL)                    /*!< PD BSR: BSR15 (Bit 15)                                */
+#define PD_BSR_BSR15_Msk                  (0x8000UL)                /*!< PD BSR: BSR15 (Bitfield-Mask: 0x01)                   */
+#define PD_BSR_BSR14_Pos                  (14UL)                    /*!< PD BSR: BSR14 (Bit 14)                                */
+#define PD_BSR_BSR14_Msk                  (0x4000UL)                /*!< PD BSR: BSR14 (Bitfield-Mask: 0x01)                   */
+#define PD_BSR_BSR13_Pos                  (13UL)                    /*!< PD BSR: BSR13 (Bit 13)                                */
+#define PD_BSR_BSR13_Msk                  (0x2000UL)                /*!< PD BSR: BSR13 (Bitfield-Mask: 0x01)                   */
+#define PD_BSR_BSR12_Pos                  (12UL)                    /*!< PD BSR: BSR12 (Bit 12)                                */
+#define PD_BSR_BSR12_Msk                  (0x1000UL)                /*!< PD BSR: BSR12 (Bitfield-Mask: 0x01)                   */
+#define PD_BSR_BSR11_Pos                  (11UL)                    /*!< PD BSR: BSR11 (Bit 11)                                */
+#define PD_BSR_BSR11_Msk                  (0x800UL)                 /*!< PD BSR: BSR11 (Bitfield-Mask: 0x01)                   */
+#define PD_BSR_BSR10_Pos                  (10UL)                    /*!< PD BSR: BSR10 (Bit 10)                                */
+#define PD_BSR_BSR10_Msk                  (0x400UL)                 /*!< PD BSR: BSR10 (Bitfield-Mask: 0x01)                   */
+#define PD_BSR_BSR9_Pos                   (9UL)                     /*!< PD BSR: BSR9 (Bit 9)                                  */
+#define PD_BSR_BSR9_Msk                   (0x200UL)                 /*!< PD BSR: BSR9 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR8_Pos                   (8UL)                     /*!< PD BSR: BSR8 (Bit 8)                                  */
+#define PD_BSR_BSR8_Msk                   (0x100UL)                 /*!< PD BSR: BSR8 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR7_Pos                   (7UL)                     /*!< PD BSR: BSR7 (Bit 7)                                  */
+#define PD_BSR_BSR7_Msk                   (0x80UL)                  /*!< PD BSR: BSR7 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR6_Pos                   (6UL)                     /*!< PD BSR: BSR6 (Bit 6)                                  */
+#define PD_BSR_BSR6_Msk                   (0x40UL)                  /*!< PD BSR: BSR6 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR5_Pos                   (5UL)                     /*!< PD BSR: BSR5 (Bit 5)                                  */
+#define PD_BSR_BSR5_Msk                   (0x20UL)                  /*!< PD BSR: BSR5 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR4_Pos                   (4UL)                     /*!< PD BSR: BSR4 (Bit 4)                                  */
+#define PD_BSR_BSR4_Msk                   (0x10UL)                  /*!< PD BSR: BSR4 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR3_Pos                   (3UL)                     /*!< PD BSR: BSR3 (Bit 3)                                  */
+#define PD_BSR_BSR3_Msk                   (0x8UL)                   /*!< PD BSR: BSR3 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR2_Pos                   (2UL)                     /*!< PD BSR: BSR2 (Bit 2)                                  */
+#define PD_BSR_BSR2_Msk                   (0x4UL)                   /*!< PD BSR: BSR2 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR1_Pos                   (1UL)                     /*!< PD BSR: BSR1 (Bit 1)                                  */
+#define PD_BSR_BSR1_Msk                   (0x2UL)                   /*!< PD BSR: BSR1 (Bitfield-Mask: 0x01)                    */
+#define PD_BSR_BSR0_Pos                   (0UL)                     /*!< PD BSR: BSR0 (Bit 0)                                  */
+#define PD_BSR_BSR0_Msk                   (0x1UL)                   /*!< PD BSR: BSR0 (Bitfield-Mask: 0x01)                    */
+/* ==========================================================  BCR  ========================================================== */
+#define PD_BCR_BCR15_Pos                  (15UL)                    /*!< PD BCR: BCR15 (Bit 15)                                */
+#define PD_BCR_BCR15_Msk                  (0x8000UL)                /*!< PD BCR: BCR15 (Bitfield-Mask: 0x01)                   */
+#define PD_BCR_BCR14_Pos                  (14UL)                    /*!< PD BCR: BCR14 (Bit 14)                                */
+#define PD_BCR_BCR14_Msk                  (0x4000UL)                /*!< PD BCR: BCR14 (Bitfield-Mask: 0x01)                   */
+#define PD_BCR_BCR13_Pos                  (13UL)                    /*!< PD BCR: BCR13 (Bit 13)                                */
+#define PD_BCR_BCR13_Msk                  (0x2000UL)                /*!< PD BCR: BCR13 (Bitfield-Mask: 0x01)                   */
+#define PD_BCR_BCR12_Pos                  (12UL)                    /*!< PD BCR: BCR12 (Bit 12)                                */
+#define PD_BCR_BCR12_Msk                  (0x1000UL)                /*!< PD BCR: BCR12 (Bitfield-Mask: 0x01)                   */
+#define PD_BCR_BCR11_Pos                  (11UL)                    /*!< PD BCR: BCR11 (Bit 11)                                */
+#define PD_BCR_BCR11_Msk                  (0x800UL)                 /*!< PD BCR: BCR11 (Bitfield-Mask: 0x01)                   */
+#define PD_BCR_BCR10_Pos                  (10UL)                    /*!< PD BCR: BCR10 (Bit 10)                                */
+#define PD_BCR_BCR10_Msk                  (0x400UL)                 /*!< PD BCR: BCR10 (Bitfield-Mask: 0x01)                   */
+#define PD_BCR_BCR9_Pos                   (9UL)                     /*!< PD BCR: BCR9 (Bit 9)                                  */
+#define PD_BCR_BCR9_Msk                   (0x200UL)                 /*!< PD BCR: BCR9 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR8_Pos                   (8UL)                     /*!< PD BCR: BCR8 (Bit 8)                                  */
+#define PD_BCR_BCR8_Msk                   (0x100UL)                 /*!< PD BCR: BCR8 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR7_Pos                   (7UL)                     /*!< PD BCR: BCR7 (Bit 7)                                  */
+#define PD_BCR_BCR7_Msk                   (0x80UL)                  /*!< PD BCR: BCR7 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR6_Pos                   (6UL)                     /*!< PD BCR: BCR6 (Bit 6)                                  */
+#define PD_BCR_BCR6_Msk                   (0x40UL)                  /*!< PD BCR: BCR6 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR5_Pos                   (5UL)                     /*!< PD BCR: BCR5 (Bit 5)                                  */
+#define PD_BCR_BCR5_Msk                   (0x20UL)                  /*!< PD BCR: BCR5 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR4_Pos                   (4UL)                     /*!< PD BCR: BCR4 (Bit 4)                                  */
+#define PD_BCR_BCR4_Msk                   (0x10UL)                  /*!< PD BCR: BCR4 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR3_Pos                   (3UL)                     /*!< PD BCR: BCR3 (Bit 3)                                  */
+#define PD_BCR_BCR3_Msk                   (0x8UL)                   /*!< PD BCR: BCR3 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR2_Pos                   (2UL)                     /*!< PD BCR: BCR2 (Bit 2)                                  */
+#define PD_BCR_BCR2_Msk                   (0x4UL)                   /*!< PD BCR: BCR2 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR1_Pos                   (1UL)                     /*!< PD BCR: BCR1 (Bit 1)                                  */
+#define PD_BCR_BCR1_Msk                   (0x2UL)                   /*!< PD BCR: BCR1 (Bitfield-Mask: 0x01)                    */
+#define PD_BCR_BCR0_Pos                   (0UL)                     /*!< PD BCR: BCR0 (Bit 0)                                  */
+#define PD_BCR_BCR0_Msk                   (0x1UL)                   /*!< PD BCR: BCR0 (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OUTDMSK  ======================================================== */
+#define PD_OUTDMSK_OUTDMSK15_Pos          (15UL)                    /*!< PD OUTDMSK: OUTDMSK15 (Bit 15)                        */
+#define PD_OUTDMSK_OUTDMSK15_Msk          (0x8000UL)                /*!< PD OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)           */
+#define PD_OUTDMSK_OUTDMSK14_Pos          (14UL)                    /*!< PD OUTDMSK: OUTDMSK14 (Bit 14)                        */
+#define PD_OUTDMSK_OUTDMSK14_Msk          (0x4000UL)                /*!< PD OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)           */
+#define PD_OUTDMSK_OUTDMSK13_Pos          (13UL)                    /*!< PD OUTDMSK: OUTDMSK13 (Bit 13)                        */
+#define PD_OUTDMSK_OUTDMSK13_Msk          (0x2000UL)                /*!< PD OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)           */
+#define PD_OUTDMSK_OUTDMSK12_Pos          (12UL)                    /*!< PD OUTDMSK: OUTDMSK12 (Bit 12)                        */
+#define PD_OUTDMSK_OUTDMSK12_Msk          (0x1000UL)                /*!< PD OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)           */
+#define PD_OUTDMSK_OUTDMSK11_Pos          (11UL)                    /*!< PD OUTDMSK: OUTDMSK11 (Bit 11)                        */
+#define PD_OUTDMSK_OUTDMSK11_Msk          (0x800UL)                 /*!< PD OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)           */
+#define PD_OUTDMSK_OUTDMSK10_Pos          (10UL)                    /*!< PD OUTDMSK: OUTDMSK10 (Bit 10)                        */
+#define PD_OUTDMSK_OUTDMSK10_Msk          (0x400UL)                 /*!< PD OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)           */
+#define PD_OUTDMSK_OUTDMSK9_Pos           (9UL)                     /*!< PD OUTDMSK: OUTDMSK9 (Bit 9)                          */
+#define PD_OUTDMSK_OUTDMSK9_Msk           (0x200UL)                 /*!< PD OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK8_Pos           (8UL)                     /*!< PD OUTDMSK: OUTDMSK8 (Bit 8)                          */
+#define PD_OUTDMSK_OUTDMSK8_Msk           (0x100UL)                 /*!< PD OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK7_Pos           (7UL)                     /*!< PD OUTDMSK: OUTDMSK7 (Bit 7)                          */
+#define PD_OUTDMSK_OUTDMSK7_Msk           (0x80UL)                  /*!< PD OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK6_Pos           (6UL)                     /*!< PD OUTDMSK: OUTDMSK6 (Bit 6)                          */
+#define PD_OUTDMSK_OUTDMSK6_Msk           (0x40UL)                  /*!< PD OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK5_Pos           (5UL)                     /*!< PD OUTDMSK: OUTDMSK5 (Bit 5)                          */
+#define PD_OUTDMSK_OUTDMSK5_Msk           (0x20UL)                  /*!< PD OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK4_Pos           (4UL)                     /*!< PD OUTDMSK: OUTDMSK4 (Bit 4)                          */
+#define PD_OUTDMSK_OUTDMSK4_Msk           (0x10UL)                  /*!< PD OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK3_Pos           (3UL)                     /*!< PD OUTDMSK: OUTDMSK3 (Bit 3)                          */
+#define PD_OUTDMSK_OUTDMSK3_Msk           (0x8UL)                   /*!< PD OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK2_Pos           (2UL)                     /*!< PD OUTDMSK: OUTDMSK2 (Bit 2)                          */
+#define PD_OUTDMSK_OUTDMSK2_Msk           (0x4UL)                   /*!< PD OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK1_Pos           (1UL)                     /*!< PD OUTDMSK: OUTDMSK1 (Bit 1)                          */
+#define PD_OUTDMSK_OUTDMSK1_Msk           (0x2UL)                   /*!< PD OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)            */
+#define PD_OUTDMSK_OUTDMSK0_Pos           (0UL)                     /*!< PD OUTDMSK: OUTDMSK0 (Bit 0)                          */
+#define PD_OUTDMSK_OUTDMSK0_Msk           (0x1UL)                   /*!< PD OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)            */
+/* =========================================================  DBCR  ========================================================== */
+#define PD_DBCR_DBCLK_Pos                 (16UL)                    /*!< PD DBCR: DBCLK (Bit 16)                               */
+#define PD_DBCR_DBCLK_Msk                 (0x70000UL)               /*!< PD DBCR: DBCLK (Bitfield-Mask: 0x07)                  */
+#define PD_DBCR_DBEN11_Pos                (11UL)                    /*!< PD DBCR: DBEN11 (Bit 11)                              */
+#define PD_DBCR_DBEN11_Msk                (0x800UL)                 /*!< PD DBCR: DBEN11 (Bitfield-Mask: 0x01)                 */
+#define PD_DBCR_DBEN10_Pos                (10UL)                    /*!< PD DBCR: DBEN10 (Bit 10)                              */
+#define PD_DBCR_DBEN10_Msk                (0x400UL)                 /*!< PD DBCR: DBEN10 (Bitfield-Mask: 0x01)                 */
+#define PD_DBCR_DBEN9_Pos                 (9UL)                     /*!< PD DBCR: DBEN9 (Bit 9)                                */
+#define PD_DBCR_DBEN9_Msk                 (0x200UL)                 /*!< PD DBCR: DBEN9 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN8_Pos                 (8UL)                     /*!< PD DBCR: DBEN8 (Bit 8)                                */
+#define PD_DBCR_DBEN8_Msk                 (0x100UL)                 /*!< PD DBCR: DBEN8 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN7_Pos                 (7UL)                     /*!< PD DBCR: DBEN7 (Bit 7)                                */
+#define PD_DBCR_DBEN7_Msk                 (0x80UL)                  /*!< PD DBCR: DBEN7 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN6_Pos                 (6UL)                     /*!< PD DBCR: DBEN6 (Bit 6)                                */
+#define PD_DBCR_DBEN6_Msk                 (0x40UL)                  /*!< PD DBCR: DBEN6 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN5_Pos                 (5UL)                     /*!< PD DBCR: DBEN5 (Bit 5)                                */
+#define PD_DBCR_DBEN5_Msk                 (0x20UL)                  /*!< PD DBCR: DBEN5 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN4_Pos                 (4UL)                     /*!< PD DBCR: DBEN4 (Bit 4)                                */
+#define PD_DBCR_DBEN4_Msk                 (0x10UL)                  /*!< PD DBCR: DBEN4 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN3_Pos                 (3UL)                     /*!< PD DBCR: DBEN3 (Bit 3)                                */
+#define PD_DBCR_DBEN3_Msk                 (0x8UL)                   /*!< PD DBCR: DBEN3 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN2_Pos                 (2UL)                     /*!< PD DBCR: DBEN2 (Bit 2)                                */
+#define PD_DBCR_DBEN2_Msk                 (0x4UL)                   /*!< PD DBCR: DBEN2 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN1_Pos                 (1UL)                     /*!< PD DBCR: DBEN1 (Bit 1)                                */
+#define PD_DBCR_DBEN1_Msk                 (0x2UL)                   /*!< PD DBCR: DBEN1 (Bitfield-Mask: 0x01)                  */
+#define PD_DBCR_DBEN0_Pos                 (0UL)                     /*!< PD DBCR: DBEN0 (Bit 0)                                */
+#define PD_DBCR_DBEN0_Msk                 (0x1UL)                   /*!< PD DBCR: DBEN0 (Bitfield-Mask: 0x01)                  */
+/* ========================================================  PD_MOD  ========================================================= */
+#define PD_PD_MOD_MODE7_Pos               (14UL)                    /*!< PD PD_MOD: MODE7 (Bit 14)                             */
+#define PD_PD_MOD_MODE7_Msk               (0xc000UL)                /*!< PD PD_MOD: MODE7 (Bitfield-Mask: 0x03)                */
+#define PD_PD_MOD_MODE6_Pos               (12UL)                    /*!< PD PD_MOD: MODE6 (Bit 12)                             */
+#define PD_PD_MOD_MODE6_Msk               (0x3000UL)                /*!< PD PD_MOD: MODE6 (Bitfield-Mask: 0x03)                */
+#define PD_PD_MOD_MODE5_Pos               (10UL)                    /*!< PD PD_MOD: MODE5 (Bit 10)                             */
+#define PD_PD_MOD_MODE5_Msk               (0xc00UL)                 /*!< PD PD_MOD: MODE5 (Bitfield-Mask: 0x03)                */
+#define PD_PD_MOD_MODE4_Pos               (8UL)                     /*!< PD PD_MOD: MODE4 (Bit 8)                              */
+#define PD_PD_MOD_MODE4_Msk               (0x300UL)                 /*!< PD PD_MOD: MODE4 (Bitfield-Mask: 0x03)                */
+#define PD_PD_MOD_MODE3_Pos               (6UL)                     /*!< PD PD_MOD: MODE3 (Bit 6)                              */
+#define PD_PD_MOD_MODE3_Msk               (0xc0UL)                  /*!< PD PD_MOD: MODE3 (Bitfield-Mask: 0x03)                */
+#define PD_PD_MOD_MODE2_Pos               (4UL)                     /*!< PD PD_MOD: MODE2 (Bit 4)                              */
+#define PD_PD_MOD_MODE2_Msk               (0x30UL)                  /*!< PD PD_MOD: MODE2 (Bitfield-Mask: 0x03)                */
+#define PD_PD_MOD_MODE1_Pos               (2UL)                     /*!< PD PD_MOD: MODE1 (Bit 2)                              */
+#define PD_PD_MOD_MODE1_Msk               (0xcUL)                   /*!< PD PD_MOD: MODE1 (Bitfield-Mask: 0x03)                */
+#define PD_PD_MOD_MODE0_Pos               (0UL)                     /*!< PD PD_MOD: MODE0 (Bit 0)                              */
+#define PD_PD_MOD_MODE0_Msk               (0x3UL)                   /*!< PD PD_MOD: MODE0 (Bitfield-Mask: 0x03)                */
+/* ========================================================  PD_TYP  ========================================================= */
+#define PD_PD_TYP_TYP7_Pos                (7UL)                     /*!< PD PD_TYP: TYP7 (Bit 7)                               */
+#define PD_PD_TYP_TYP7_Msk                (0x80UL)                  /*!< PD PD_TYP: TYP7 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_TYP_TYP6_Pos                (6UL)                     /*!< PD PD_TYP: TYP6 (Bit 6)                               */
+#define PD_PD_TYP_TYP6_Msk                (0x40UL)                  /*!< PD PD_TYP: TYP6 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_TYP_TYP5_Pos                (5UL)                     /*!< PD PD_TYP: TYP5 (Bit 5)                               */
+#define PD_PD_TYP_TYP5_Msk                (0x20UL)                  /*!< PD PD_TYP: TYP5 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_TYP_TYP4_Pos                (4UL)                     /*!< PD PD_TYP: TYP4 (Bit 4)                               */
+#define PD_PD_TYP_TYP4_Msk                (0x10UL)                  /*!< PD PD_TYP: TYP4 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_TYP_TYP3_Pos                (3UL)                     /*!< PD PD_TYP: TYP3 (Bit 3)                               */
+#define PD_PD_TYP_TYP3_Msk                (0x8UL)                   /*!< PD PD_TYP: TYP3 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_TYP_TYP2_Pos                (2UL)                     /*!< PD PD_TYP: TYP2 (Bit 2)                               */
+#define PD_PD_TYP_TYP2_Msk                (0x4UL)                   /*!< PD PD_TYP: TYP2 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_TYP_TYP1_Pos                (1UL)                     /*!< PD PD_TYP: TYP1 (Bit 1)                               */
+#define PD_PD_TYP_TYP1_Msk                (0x2UL)                   /*!< PD PD_TYP: TYP1 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_TYP_TYP0_Pos                (0UL)                     /*!< PD PD_TYP: TYP0 (Bit 0)                               */
+#define PD_PD_TYP_TYP0_Msk                (0x1UL)                   /*!< PD PD_TYP: TYP0 (Bitfield-Mask: 0x01)                 */
+/* =======================================================  PD_AFSR1  ======================================================== */
+#define PD_PD_AFSR1_AFSR7_Pos             (28UL)                    /*!< PD PD_AFSR1: AFSR7 (Bit 28)                           */
+#define PD_PD_AFSR1_AFSR7_Msk             (0xf0000000UL)            /*!< PD PD_AFSR1: AFSR7 (Bitfield-Mask: 0x0f)              */
+#define PD_PD_AFSR1_AFSR6_Pos             (24UL)                    /*!< PD PD_AFSR1: AFSR6 (Bit 24)                           */
+#define PD_PD_AFSR1_AFSR6_Msk             (0xf000000UL)             /*!< PD PD_AFSR1: AFSR6 (Bitfield-Mask: 0x0f)              */
+#define PD_PD_AFSR1_AFSR5_Pos             (20UL)                    /*!< PD PD_AFSR1: AFSR5 (Bit 20)                           */
+#define PD_PD_AFSR1_AFSR5_Msk             (0xf00000UL)              /*!< PD PD_AFSR1: AFSR5 (Bitfield-Mask: 0x0f)              */
+#define PD_PD_AFSR1_AFSR4_Pos             (16UL)                    /*!< PD PD_AFSR1: AFSR4 (Bit 16)                           */
+#define PD_PD_AFSR1_AFSR4_Msk             (0xf0000UL)               /*!< PD PD_AFSR1: AFSR4 (Bitfield-Mask: 0x0f)              */
+#define PD_PD_AFSR1_AFSR3_Pos             (12UL)                    /*!< PD PD_AFSR1: AFSR3 (Bit 12)                           */
+#define PD_PD_AFSR1_AFSR3_Msk             (0xf000UL)                /*!< PD PD_AFSR1: AFSR3 (Bitfield-Mask: 0x0f)              */
+#define PD_PD_AFSR1_AFSR2_Pos             (8UL)                     /*!< PD PD_AFSR1: AFSR2 (Bit 8)                            */
+#define PD_PD_AFSR1_AFSR2_Msk             (0xf00UL)                 /*!< PD PD_AFSR1: AFSR2 (Bitfield-Mask: 0x0f)              */
+#define PD_PD_AFSR1_AFSR1_Pos             (4UL)                     /*!< PD PD_AFSR1: AFSR1 (Bit 4)                            */
+#define PD_PD_AFSR1_AFSR1_Msk             (0xf0UL)                  /*!< PD PD_AFSR1: AFSR1 (Bitfield-Mask: 0x0f)              */
+#define PD_PD_AFSR1_AFSR0_Pos             (0UL)                     /*!< PD PD_AFSR1: AFSR0 (Bit 0)                            */
+#define PD_PD_AFSR1_AFSR0_Msk             (0xfUL)                   /*!< PD PD_AFSR1: AFSR0 (Bitfield-Mask: 0x0f)              */
+/* =======================================================  PD_AFSR2  ======================================================== */
+/* ========================================================  PD_PUPD  ======================================================== */
+#define PD_PD_PUPD_PUPD7_Pos              (14UL)                    /*!< PD PD_PUPD: PUPD7 (Bit 14)                            */
+#define PD_PD_PUPD_PUPD7_Msk              (0xc000UL)                /*!< PD PD_PUPD: PUPD7 (Bitfield-Mask: 0x03)               */
+#define PD_PD_PUPD_PUPD6_Pos              (12UL)                    /*!< PD PD_PUPD: PUPD6 (Bit 12)                            */
+#define PD_PD_PUPD_PUPD6_Msk              (0x3000UL)                /*!< PD PD_PUPD: PUPD6 (Bitfield-Mask: 0x03)               */
+#define PD_PD_PUPD_PUPD5_Pos              (10UL)                    /*!< PD PD_PUPD: PUPD5 (Bit 10)                            */
+#define PD_PD_PUPD_PUPD5_Msk              (0xc00UL)                 /*!< PD PD_PUPD: PUPD5 (Bitfield-Mask: 0x03)               */
+#define PD_PD_PUPD_PUPD4_Pos              (8UL)                     /*!< PD PD_PUPD: PUPD4 (Bit 8)                             */
+#define PD_PD_PUPD_PUPD4_Msk              (0x300UL)                 /*!< PD PD_PUPD: PUPD4 (Bitfield-Mask: 0x03)               */
+#define PD_PD_PUPD_PUPD3_Pos              (6UL)                     /*!< PD PD_PUPD: PUPD3 (Bit 6)                             */
+#define PD_PD_PUPD_PUPD3_Msk              (0xc0UL)                  /*!< PD PD_PUPD: PUPD3 (Bitfield-Mask: 0x03)               */
+#define PD_PD_PUPD_PUPD2_Pos              (4UL)                     /*!< PD PD_PUPD: PUPD2 (Bit 4)                             */
+#define PD_PD_PUPD_PUPD2_Msk              (0x30UL)                  /*!< PD PD_PUPD: PUPD2 (Bitfield-Mask: 0x03)               */
+#define PD_PD_PUPD_PUPD1_Pos              (2UL)                     /*!< PD PD_PUPD: PUPD1 (Bit 2)                             */
+#define PD_PD_PUPD_PUPD1_Msk              (0xcUL)                   /*!< PD PD_PUPD: PUPD1 (Bitfield-Mask: 0x03)               */
+#define PD_PD_PUPD_PUPD0_Pos              (0UL)                     /*!< PD PD_PUPD: PUPD0 (Bit 0)                             */
+#define PD_PD_PUPD_PUPD0_Msk              (0x3UL)                   /*!< PD PD_PUPD: PUPD0 (Bitfield-Mask: 0x03)               */
+/* ========================================================  PD_INDR  ======================================================== */
+#define PD_PD_INDR_INDR7_Pos              (7UL)                     /*!< PD PD_INDR: INDR7 (Bit 7)                             */
+#define PD_PD_INDR_INDR7_Msk              (0x80UL)                  /*!< PD PD_INDR: INDR7 (Bitfield-Mask: 0x01)               */
+#define PD_PD_INDR_INDR6_Pos              (6UL)                     /*!< PD PD_INDR: INDR6 (Bit 6)                             */
+#define PD_PD_INDR_INDR6_Msk              (0x40UL)                  /*!< PD PD_INDR: INDR6 (Bitfield-Mask: 0x01)               */
+#define PD_PD_INDR_INDR5_Pos              (5UL)                     /*!< PD PD_INDR: INDR5 (Bit 5)                             */
+#define PD_PD_INDR_INDR5_Msk              (0x20UL)                  /*!< PD PD_INDR: INDR5 (Bitfield-Mask: 0x01)               */
+#define PD_PD_INDR_INDR4_Pos              (4UL)                     /*!< PD PD_INDR: INDR4 (Bit 4)                             */
+#define PD_PD_INDR_INDR4_Msk              (0x10UL)                  /*!< PD PD_INDR: INDR4 (Bitfield-Mask: 0x01)               */
+#define PD_PD_INDR_INDR3_Pos              (3UL)                     /*!< PD PD_INDR: INDR3 (Bit 3)                             */
+#define PD_PD_INDR_INDR3_Msk              (0x8UL)                   /*!< PD PD_INDR: INDR3 (Bitfield-Mask: 0x01)               */
+#define PD_PD_INDR_INDR2_Pos              (2UL)                     /*!< PD PD_INDR: INDR2 (Bit 2)                             */
+#define PD_PD_INDR_INDR2_Msk              (0x4UL)                   /*!< PD PD_INDR: INDR2 (Bitfield-Mask: 0x01)               */
+#define PD_PD_INDR_INDR1_Pos              (1UL)                     /*!< PD PD_INDR: INDR1 (Bit 1)                             */
+#define PD_PD_INDR_INDR1_Msk              (0x2UL)                   /*!< PD PD_INDR: INDR1 (Bitfield-Mask: 0x01)               */
+#define PD_PD_INDR_INDR0_Pos              (0UL)                     /*!< PD PD_INDR: INDR0 (Bit 0)                             */
+#define PD_PD_INDR_INDR0_Msk              (0x1UL)                   /*!< PD PD_INDR: INDR0 (Bitfield-Mask: 0x01)               */
+/* =======================================================  PD_OUTDR  ======================================================== */
+#define PD_PD_OUTDR_OUTDR7_Pos            (7UL)                     /*!< PD PD_OUTDR: OUTDR7 (Bit 7)                           */
+#define PD_PD_OUTDR_OUTDR7_Msk            (0x80UL)                  /*!< PD PD_OUTDR: OUTDR7 (Bitfield-Mask: 0x01)             */
+#define PD_PD_OUTDR_OUTDR6_Pos            (6UL)                     /*!< PD PD_OUTDR: OUTDR6 (Bit 6)                           */
+#define PD_PD_OUTDR_OUTDR6_Msk            (0x40UL)                  /*!< PD PD_OUTDR: OUTDR6 (Bitfield-Mask: 0x01)             */
+#define PD_PD_OUTDR_OUTDR5_Pos            (5UL)                     /*!< PD PD_OUTDR: OUTDR5 (Bit 5)                           */
+#define PD_PD_OUTDR_OUTDR5_Msk            (0x20UL)                  /*!< PD PD_OUTDR: OUTDR5 (Bitfield-Mask: 0x01)             */
+#define PD_PD_OUTDR_OUTDR4_Pos            (4UL)                     /*!< PD PD_OUTDR: OUTDR4 (Bit 4)                           */
+#define PD_PD_OUTDR_OUTDR4_Msk            (0x10UL)                  /*!< PD PD_OUTDR: OUTDR4 (Bitfield-Mask: 0x01)             */
+#define PD_PD_OUTDR_OUTDR3_Pos            (3UL)                     /*!< PD PD_OUTDR: OUTDR3 (Bit 3)                           */
+#define PD_PD_OUTDR_OUTDR3_Msk            (0x8UL)                   /*!< PD PD_OUTDR: OUTDR3 (Bitfield-Mask: 0x01)             */
+#define PD_PD_OUTDR_OUTDR2_Pos            (2UL)                     /*!< PD PD_OUTDR: OUTDR2 (Bit 2)                           */
+#define PD_PD_OUTDR_OUTDR2_Msk            (0x4UL)                   /*!< PD PD_OUTDR: OUTDR2 (Bitfield-Mask: 0x01)             */
+#define PD_PD_OUTDR_OUTDR1_Pos            (1UL)                     /*!< PD PD_OUTDR: OUTDR1 (Bit 1)                           */
+#define PD_PD_OUTDR_OUTDR1_Msk            (0x2UL)                   /*!< PD PD_OUTDR: OUTDR1 (Bitfield-Mask: 0x01)             */
+#define PD_PD_OUTDR_OUTDR0_Pos            (0UL)                     /*!< PD PD_OUTDR: OUTDR0 (Bit 0)                           */
+#define PD_PD_OUTDR_OUTDR0_Msk            (0x1UL)                   /*!< PD PD_OUTDR: OUTDR0 (Bitfield-Mask: 0x01)             */
+/* ========================================================  PD_BSR  ========================================================= */
+#define PD_PD_BSR_BSR7_Pos                (7UL)                     /*!< PD PD_BSR: BSR7 (Bit 7)                               */
+#define PD_PD_BSR_BSR7_Msk                (0x80UL)                  /*!< PD PD_BSR: BSR7 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BSR_BSR6_Pos                (6UL)                     /*!< PD PD_BSR: BSR6 (Bit 6)                               */
+#define PD_PD_BSR_BSR6_Msk                (0x40UL)                  /*!< PD PD_BSR: BSR6 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BSR_BSR5_Pos                (5UL)                     /*!< PD PD_BSR: BSR5 (Bit 5)                               */
+#define PD_PD_BSR_BSR5_Msk                (0x20UL)                  /*!< PD PD_BSR: BSR5 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BSR_BSR4_Pos                (4UL)                     /*!< PD PD_BSR: BSR4 (Bit 4)                               */
+#define PD_PD_BSR_BSR4_Msk                (0x10UL)                  /*!< PD PD_BSR: BSR4 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BSR_BSR3_Pos                (3UL)                     /*!< PD PD_BSR: BSR3 (Bit 3)                               */
+#define PD_PD_BSR_BSR3_Msk                (0x8UL)                   /*!< PD PD_BSR: BSR3 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BSR_BSR2_Pos                (2UL)                     /*!< PD PD_BSR: BSR2 (Bit 2)                               */
+#define PD_PD_BSR_BSR2_Msk                (0x4UL)                   /*!< PD PD_BSR: BSR2 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BSR_BSR1_Pos                (1UL)                     /*!< PD PD_BSR: BSR1 (Bit 1)                               */
+#define PD_PD_BSR_BSR1_Msk                (0x2UL)                   /*!< PD PD_BSR: BSR1 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BSR_BSR0_Pos                (0UL)                     /*!< PD PD_BSR: BSR0 (Bit 0)                               */
+#define PD_PD_BSR_BSR0_Msk                (0x1UL)                   /*!< PD PD_BSR: BSR0 (Bitfield-Mask: 0x01)                 */
+/* ========================================================  PD_BCR  ========================================================= */
+#define PD_PD_BCR_BCR7_Pos                (7UL)                     /*!< PD PD_BCR: BCR7 (Bit 7)                               */
+#define PD_PD_BCR_BCR7_Msk                (0x80UL)                  /*!< PD PD_BCR: BCR7 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BCR_BCR6_Pos                (6UL)                     /*!< PD PD_BCR: BCR6 (Bit 6)                               */
+#define PD_PD_BCR_BCR6_Msk                (0x40UL)                  /*!< PD PD_BCR: BCR6 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BCR_BCR5_Pos                (5UL)                     /*!< PD PD_BCR: BCR5 (Bit 5)                               */
+#define PD_PD_BCR_BCR5_Msk                (0x20UL)                  /*!< PD PD_BCR: BCR5 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BCR_BCR4_Pos                (4UL)                     /*!< PD PD_BCR: BCR4 (Bit 4)                               */
+#define PD_PD_BCR_BCR4_Msk                (0x10UL)                  /*!< PD PD_BCR: BCR4 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BCR_BCR3_Pos                (3UL)                     /*!< PD PD_BCR: BCR3 (Bit 3)                               */
+#define PD_PD_BCR_BCR3_Msk                (0x8UL)                   /*!< PD PD_BCR: BCR3 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BCR_BCR2_Pos                (2UL)                     /*!< PD PD_BCR: BCR2 (Bit 2)                               */
+#define PD_PD_BCR_BCR2_Msk                (0x4UL)                   /*!< PD PD_BCR: BCR2 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BCR_BCR1_Pos                (1UL)                     /*!< PD PD_BCR: BCR1 (Bit 1)                               */
+#define PD_PD_BCR_BCR1_Msk                (0x2UL)                   /*!< PD PD_BCR: BCR1 (Bitfield-Mask: 0x01)                 */
+#define PD_PD_BCR_BCR0_Pos                (0UL)                     /*!< PD PD_BCR: BCR0 (Bit 0)                               */
+#define PD_PD_BCR_BCR0_Msk                (0x1UL)                   /*!< PD PD_BCR: BCR0 (Bitfield-Mask: 0x01)                 */
+/* ======================================================  PD_OUTDMSK  ======================================================= */
+#define PD_PD_OUTDMSK_OUTDMSK7_Pos        (7UL)                     /*!< PD PD_OUTDMSK: OUTDMSK7 (Bit 7)                       */
+#define PD_PD_OUTDMSK_OUTDMSK7_Msk        (0x80UL)                  /*!< PD PD_OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)         */
+#define PD_PD_OUTDMSK_OUTDMSK6_Pos        (6UL)                     /*!< PD PD_OUTDMSK: OUTDMSK6 (Bit 6)                       */
+#define PD_PD_OUTDMSK_OUTDMSK6_Msk        (0x40UL)                  /*!< PD PD_OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)         */
+#define PD_PD_OUTDMSK_OUTDMSK5_Pos        (5UL)                     /*!< PD PD_OUTDMSK: OUTDMSK5 (Bit 5)                       */
+#define PD_PD_OUTDMSK_OUTDMSK5_Msk        (0x20UL)                  /*!< PD PD_OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)         */
+#define PD_PD_OUTDMSK_OUTDMSK4_Pos        (4UL)                     /*!< PD PD_OUTDMSK: OUTDMSK4 (Bit 4)                       */
+#define PD_PD_OUTDMSK_OUTDMSK4_Msk        (0x10UL)                  /*!< PD PD_OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)         */
+#define PD_PD_OUTDMSK_OUTDMSK3_Pos        (3UL)                     /*!< PD PD_OUTDMSK: OUTDMSK3 (Bit 3)                       */
+#define PD_PD_OUTDMSK_OUTDMSK3_Msk        (0x8UL)                   /*!< PD PD_OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)         */
+#define PD_PD_OUTDMSK_OUTDMSK2_Pos        (2UL)                     /*!< PD PD_OUTDMSK: OUTDMSK2 (Bit 2)                       */
+#define PD_PD_OUTDMSK_OUTDMSK2_Msk        (0x4UL)                   /*!< PD PD_OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)         */
+#define PD_PD_OUTDMSK_OUTDMSK1_Pos        (1UL)                     /*!< PD PD_OUTDMSK: OUTDMSK1 (Bit 1)                       */
+#define PD_PD_OUTDMSK_OUTDMSK1_Msk        (0x2UL)                   /*!< PD PD_OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)         */
+#define PD_PD_OUTDMSK_OUTDMSK0_Pos        (0UL)                     /*!< PD PD_OUTDMSK: OUTDMSK0 (Bit 0)                       */
+#define PD_PD_OUTDMSK_OUTDMSK0_Msk        (0x1UL)                   /*!< PD PD_OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)         */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PE                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+#define PE_MOD_MODE15_Pos                 (30UL)                    /*!< PE MOD: MODE15 (Bit 30)                               */
+#define PE_MOD_MODE15_Msk                 (0xc0000000UL)            /*!< PE MOD: MODE15 (Bitfield-Mask: 0x03)                  */
+#define PE_MOD_MODE14_Pos                 (28UL)                    /*!< PE MOD: MODE14 (Bit 28)                               */
+#define PE_MOD_MODE14_Msk                 (0x30000000UL)            /*!< PE MOD: MODE14 (Bitfield-Mask: 0x03)                  */
+#define PE_MOD_MODE13_Pos                 (26UL)                    /*!< PE MOD: MODE13 (Bit 26)                               */
+#define PE_MOD_MODE13_Msk                 (0xc000000UL)             /*!< PE MOD: MODE13 (Bitfield-Mask: 0x03)                  */
+#define PE_MOD_MODE12_Pos                 (24UL)                    /*!< PE MOD: MODE12 (Bit 24)                               */
+#define PE_MOD_MODE12_Msk                 (0x3000000UL)             /*!< PE MOD: MODE12 (Bitfield-Mask: 0x03)                  */
+#define PE_MOD_MODE11_Pos                 (22UL)                    /*!< PE MOD: MODE11 (Bit 22)                               */
+#define PE_MOD_MODE11_Msk                 (0xc00000UL)              /*!< PE MOD: MODE11 (Bitfield-Mask: 0x03)                  */
+#define PE_MOD_MODE10_Pos                 (20UL)                    /*!< PE MOD: MODE10 (Bit 20)                               */
+#define PE_MOD_MODE10_Msk                 (0x300000UL)              /*!< PE MOD: MODE10 (Bitfield-Mask: 0x03)                  */
+#define PE_MOD_MODE9_Pos                  (18UL)                    /*!< PE MOD: MODE9 (Bit 18)                                */
+#define PE_MOD_MODE9_Msk                  (0xc0000UL)               /*!< PE MOD: MODE9 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE8_Pos                  (16UL)                    /*!< PE MOD: MODE8 (Bit 16)                                */
+#define PE_MOD_MODE8_Msk                  (0x30000UL)               /*!< PE MOD: MODE8 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE7_Pos                  (14UL)                    /*!< PE MOD: MODE7 (Bit 14)                                */
+#define PE_MOD_MODE7_Msk                  (0xc000UL)                /*!< PE MOD: MODE7 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE6_Pos                  (12UL)                    /*!< PE MOD: MODE6 (Bit 12)                                */
+#define PE_MOD_MODE6_Msk                  (0x3000UL)                /*!< PE MOD: MODE6 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE5_Pos                  (10UL)                    /*!< PE MOD: MODE5 (Bit 10)                                */
+#define PE_MOD_MODE5_Msk                  (0xc00UL)                 /*!< PE MOD: MODE5 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE4_Pos                  (8UL)                     /*!< PE MOD: MODE4 (Bit 8)                                 */
+#define PE_MOD_MODE4_Msk                  (0x300UL)                 /*!< PE MOD: MODE4 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE3_Pos                  (6UL)                     /*!< PE MOD: MODE3 (Bit 6)                                 */
+#define PE_MOD_MODE3_Msk                  (0xc0UL)                  /*!< PE MOD: MODE3 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE2_Pos                  (4UL)                     /*!< PE MOD: MODE2 (Bit 4)                                 */
+#define PE_MOD_MODE2_Msk                  (0x30UL)                  /*!< PE MOD: MODE2 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE1_Pos                  (2UL)                     /*!< PE MOD: MODE1 (Bit 2)                                 */
+#define PE_MOD_MODE1_Msk                  (0xcUL)                   /*!< PE MOD: MODE1 (Bitfield-Mask: 0x03)                   */
+#define PE_MOD_MODE0_Pos                  (0UL)                     /*!< PE MOD: MODE0 (Bit 0)                                 */
+#define PE_MOD_MODE0_Msk                  (0x3UL)                   /*!< PE MOD: MODE0 (Bitfield-Mask: 0x03)                   */
+/* ==========================================================  TYP  ========================================================== */
+#define PE_TYP_TYP15_Pos                  (15UL)                    /*!< PE TYP: TYP15 (Bit 15)                                */
+#define PE_TYP_TYP15_Msk                  (0x8000UL)                /*!< PE TYP: TYP15 (Bitfield-Mask: 0x01)                   */
+#define PE_TYP_TYP14_Pos                  (14UL)                    /*!< PE TYP: TYP14 (Bit 14)                                */
+#define PE_TYP_TYP14_Msk                  (0x4000UL)                /*!< PE TYP: TYP14 (Bitfield-Mask: 0x01)                   */
+#define PE_TYP_TYP13_Pos                  (13UL)                    /*!< PE TYP: TYP13 (Bit 13)                                */
+#define PE_TYP_TYP13_Msk                  (0x2000UL)                /*!< PE TYP: TYP13 (Bitfield-Mask: 0x01)                   */
+#define PE_TYP_TYP12_Pos                  (12UL)                    /*!< PE TYP: TYP12 (Bit 12)                                */
+#define PE_TYP_TYP12_Msk                  (0x1000UL)                /*!< PE TYP: TYP12 (Bitfield-Mask: 0x01)                   */
+#define PE_TYP_TYP11_Pos                  (11UL)                    /*!< PE TYP: TYP11 (Bit 11)                                */
+#define PE_TYP_TYP11_Msk                  (0x800UL)                 /*!< PE TYP: TYP11 (Bitfield-Mask: 0x01)                   */
+#define PE_TYP_TYP10_Pos                  (10UL)                    /*!< PE TYP: TYP10 (Bit 10)                                */
+#define PE_TYP_TYP10_Msk                  (0x400UL)                 /*!< PE TYP: TYP10 (Bitfield-Mask: 0x01)                   */
+#define PE_TYP_TYP9_Pos                   (9UL)                     /*!< PE TYP: TYP9 (Bit 9)                                  */
+#define PE_TYP_TYP9_Msk                   (0x200UL)                 /*!< PE TYP: TYP9 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP8_Pos                   (8UL)                     /*!< PE TYP: TYP8 (Bit 8)                                  */
+#define PE_TYP_TYP8_Msk                   (0x100UL)                 /*!< PE TYP: TYP8 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP7_Pos                   (7UL)                     /*!< PE TYP: TYP7 (Bit 7)                                  */
+#define PE_TYP_TYP7_Msk                   (0x80UL)                  /*!< PE TYP: TYP7 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP6_Pos                   (6UL)                     /*!< PE TYP: TYP6 (Bit 6)                                  */
+#define PE_TYP_TYP6_Msk                   (0x40UL)                  /*!< PE TYP: TYP6 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP5_Pos                   (5UL)                     /*!< PE TYP: TYP5 (Bit 5)                                  */
+#define PE_TYP_TYP5_Msk                   (0x20UL)                  /*!< PE TYP: TYP5 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP4_Pos                   (4UL)                     /*!< PE TYP: TYP4 (Bit 4)                                  */
+#define PE_TYP_TYP4_Msk                   (0x10UL)                  /*!< PE TYP: TYP4 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP3_Pos                   (3UL)                     /*!< PE TYP: TYP3 (Bit 3)                                  */
+#define PE_TYP_TYP3_Msk                   (0x8UL)                   /*!< PE TYP: TYP3 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP2_Pos                   (2UL)                     /*!< PE TYP: TYP2 (Bit 2)                                  */
+#define PE_TYP_TYP2_Msk                   (0x4UL)                   /*!< PE TYP: TYP2 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP1_Pos                   (1UL)                     /*!< PE TYP: TYP1 (Bit 1)                                  */
+#define PE_TYP_TYP1_Msk                   (0x2UL)                   /*!< PE TYP: TYP1 (Bitfield-Mask: 0x01)                    */
+#define PE_TYP_TYP0_Pos                   (0UL)                     /*!< PE TYP: TYP0 (Bit 0)                                  */
+#define PE_TYP_TYP0_Msk                   (0x1UL)                   /*!< PE TYP: TYP0 (Bitfield-Mask: 0x01)                    */
+/* =========================================================  AFSR1  ========================================================= */
+#define PE_AFSR1_AFSR7_Pos                (28UL)                    /*!< PE AFSR1: AFSR7 (Bit 28)                              */
+#define PE_AFSR1_AFSR7_Msk                (0xf0000000UL)            /*!< PE AFSR1: AFSR7 (Bitfield-Mask: 0x0f)                 */
+#define PE_AFSR1_AFSR6_Pos                (24UL)                    /*!< PE AFSR1: AFSR6 (Bit 24)                              */
+#define PE_AFSR1_AFSR6_Msk                (0xf000000UL)             /*!< PE AFSR1: AFSR6 (Bitfield-Mask: 0x0f)                 */
+#define PE_AFSR1_AFSR5_Pos                (20UL)                    /*!< PE AFSR1: AFSR5 (Bit 20)                              */
+#define PE_AFSR1_AFSR5_Msk                (0xf00000UL)              /*!< PE AFSR1: AFSR5 (Bitfield-Mask: 0x0f)                 */
+#define PE_AFSR1_AFSR4_Pos                (16UL)                    /*!< PE AFSR1: AFSR4 (Bit 16)                              */
+#define PE_AFSR1_AFSR4_Msk                (0xf0000UL)               /*!< PE AFSR1: AFSR4 (Bitfield-Mask: 0x0f)                 */
+#define PE_AFSR1_AFSR3_Pos                (12UL)                    /*!< PE AFSR1: AFSR3 (Bit 12)                              */
+#define PE_AFSR1_AFSR3_Msk                (0xf000UL)                /*!< PE AFSR1: AFSR3 (Bitfield-Mask: 0x0f)                 */
+#define PE_AFSR1_AFSR2_Pos                (8UL)                     /*!< PE AFSR1: AFSR2 (Bit 8)                               */
+#define PE_AFSR1_AFSR2_Msk                (0xf00UL)                 /*!< PE AFSR1: AFSR2 (Bitfield-Mask: 0x0f)                 */
+#define PE_AFSR1_AFSR1_Pos                (4UL)                     /*!< PE AFSR1: AFSR1 (Bit 4)                               */
+#define PE_AFSR1_AFSR1_Msk                (0xf0UL)                  /*!< PE AFSR1: AFSR1 (Bitfield-Mask: 0x0f)                 */
+#define PE_AFSR1_AFSR0_Pos                (0UL)                     /*!< PE AFSR1: AFSR0 (Bit 0)                               */
+#define PE_AFSR1_AFSR0_Msk                (0xfUL)                   /*!< PE AFSR1: AFSR0 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  AFSR2  ========================================================= */
+#define PE_AFSR2_AFSR15_Pos               (28UL)                    /*!< PE AFSR2: AFSR15 (Bit 28)                             */
+#define PE_AFSR2_AFSR15_Msk               (0xf0000000UL)            /*!< PE AFSR2: AFSR15 (Bitfield-Mask: 0x0f)                */
+#define PE_AFSR2_AFSR14_Pos               (24UL)                    /*!< PE AFSR2: AFSR14 (Bit 24)                             */
+#define PE_AFSR2_AFSR14_Msk               (0xf000000UL)             /*!< PE AFSR2: AFSR14 (Bitfield-Mask: 0x0f)                */
+#define PE_AFSR2_AFSR13_Pos               (20UL)                    /*!< PE AFSR2: AFSR13 (Bit 20)                             */
+#define PE_AFSR2_AFSR13_Msk               (0xf00000UL)              /*!< PE AFSR2: AFSR13 (Bitfield-Mask: 0x0f)                */
+#define PE_AFSR2_AFSR12_Pos               (16UL)                    /*!< PE AFSR2: AFSR12 (Bit 16)                             */
+#define PE_AFSR2_AFSR12_Msk               (0xf0000UL)               /*!< PE AFSR2: AFSR12 (Bitfield-Mask: 0x0f)                */
+#define PE_AFSR2_AFSR11_Pos               (12UL)                    /*!< PE AFSR2: AFSR11 (Bit 12)                             */
+#define PE_AFSR2_AFSR11_Msk               (0xf000UL)                /*!< PE AFSR2: AFSR11 (Bitfield-Mask: 0x0f)                */
+#define PE_AFSR2_AFSR10_Pos               (8UL)                     /*!< PE AFSR2: AFSR10 (Bit 8)                              */
+#define PE_AFSR2_AFSR10_Msk               (0xf00UL)                 /*!< PE AFSR2: AFSR10 (Bitfield-Mask: 0x0f)                */
+#define PE_AFSR2_AFSR9_Pos                (4UL)                     /*!< PE AFSR2: AFSR9 (Bit 4)                               */
+#define PE_AFSR2_AFSR9_Msk                (0xf0UL)                  /*!< PE AFSR2: AFSR9 (Bitfield-Mask: 0x0f)                 */
+#define PE_AFSR2_AFSR8_Pos                (0UL)                     /*!< PE AFSR2: AFSR8 (Bit 0)                               */
+#define PE_AFSR2_AFSR8_Msk                (0xfUL)                   /*!< PE AFSR2: AFSR8 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  PUPD  ========================================================== */
+#define PE_PUPD_PUPD15_Pos                (30UL)                    /*!< PE PUPD: PUPD15 (Bit 30)                              */
+#define PE_PUPD_PUPD15_Msk                (0xc0000000UL)            /*!< PE PUPD: PUPD15 (Bitfield-Mask: 0x03)                 */
+#define PE_PUPD_PUPD14_Pos                (28UL)                    /*!< PE PUPD: PUPD14 (Bit 28)                              */
+#define PE_PUPD_PUPD14_Msk                (0x30000000UL)            /*!< PE PUPD: PUPD14 (Bitfield-Mask: 0x03)                 */
+#define PE_PUPD_PUPD13_Pos                (26UL)                    /*!< PE PUPD: PUPD13 (Bit 26)                              */
+#define PE_PUPD_PUPD13_Msk                (0xc000000UL)             /*!< PE PUPD: PUPD13 (Bitfield-Mask: 0x03)                 */
+#define PE_PUPD_PUPD12_Pos                (24UL)                    /*!< PE PUPD: PUPD12 (Bit 24)                              */
+#define PE_PUPD_PUPD12_Msk                (0x3000000UL)             /*!< PE PUPD: PUPD12 (Bitfield-Mask: 0x03)                 */
+#define PE_PUPD_PUPD11_Pos                (22UL)                    /*!< PE PUPD: PUPD11 (Bit 22)                              */
+#define PE_PUPD_PUPD11_Msk                (0xc00000UL)              /*!< PE PUPD: PUPD11 (Bitfield-Mask: 0x03)                 */
+#define PE_PUPD_PUPD10_Pos                (20UL)                    /*!< PE PUPD: PUPD10 (Bit 20)                              */
+#define PE_PUPD_PUPD10_Msk                (0x300000UL)              /*!< PE PUPD: PUPD10 (Bitfield-Mask: 0x03)                 */
+#define PE_PUPD_PUPD9_Pos                 (18UL)                    /*!< PE PUPD: PUPD9 (Bit 18)                               */
+#define PE_PUPD_PUPD9_Msk                 (0xc0000UL)               /*!< PE PUPD: PUPD9 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD8_Pos                 (16UL)                    /*!< PE PUPD: PUPD8 (Bit 16)                               */
+#define PE_PUPD_PUPD8_Msk                 (0x30000UL)               /*!< PE PUPD: PUPD8 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD7_Pos                 (14UL)                    /*!< PE PUPD: PUPD7 (Bit 14)                               */
+#define PE_PUPD_PUPD7_Msk                 (0xc000UL)                /*!< PE PUPD: PUPD7 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD6_Pos                 (12UL)                    /*!< PE PUPD: PUPD6 (Bit 12)                               */
+#define PE_PUPD_PUPD6_Msk                 (0x3000UL)                /*!< PE PUPD: PUPD6 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD5_Pos                 (10UL)                    /*!< PE PUPD: PUPD5 (Bit 10)                               */
+#define PE_PUPD_PUPD5_Msk                 (0xc00UL)                 /*!< PE PUPD: PUPD5 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD4_Pos                 (8UL)                     /*!< PE PUPD: PUPD4 (Bit 8)                                */
+#define PE_PUPD_PUPD4_Msk                 (0x300UL)                 /*!< PE PUPD: PUPD4 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD3_Pos                 (6UL)                     /*!< PE PUPD: PUPD3 (Bit 6)                                */
+#define PE_PUPD_PUPD3_Msk                 (0xc0UL)                  /*!< PE PUPD: PUPD3 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD2_Pos                 (4UL)                     /*!< PE PUPD: PUPD2 (Bit 4)                                */
+#define PE_PUPD_PUPD2_Msk                 (0x30UL)                  /*!< PE PUPD: PUPD2 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD1_Pos                 (2UL)                     /*!< PE PUPD: PUPD1 (Bit 2)                                */
+#define PE_PUPD_PUPD1_Msk                 (0xcUL)                   /*!< PE PUPD: PUPD1 (Bitfield-Mask: 0x03)                  */
+#define PE_PUPD_PUPD0_Pos                 (0UL)                     /*!< PE PUPD: PUPD0 (Bit 0)                                */
+#define PE_PUPD_PUPD0_Msk                 (0x3UL)                   /*!< PE PUPD: PUPD0 (Bitfield-Mask: 0x03)                  */
+/* =========================================================  INDR  ========================================================== */
+#define PE_INDR_INDR15_Pos                (15UL)                    /*!< PE INDR: INDR15 (Bit 15)                              */
+#define PE_INDR_INDR15_Msk                (0x8000UL)                /*!< PE INDR: INDR15 (Bitfield-Mask: 0x01)                 */
+#define PE_INDR_INDR14_Pos                (14UL)                    /*!< PE INDR: INDR14 (Bit 14)                              */
+#define PE_INDR_INDR14_Msk                (0x4000UL)                /*!< PE INDR: INDR14 (Bitfield-Mask: 0x01)                 */
+#define PE_INDR_INDR13_Pos                (13UL)                    /*!< PE INDR: INDR13 (Bit 13)                              */
+#define PE_INDR_INDR13_Msk                (0x2000UL)                /*!< PE INDR: INDR13 (Bitfield-Mask: 0x01)                 */
+#define PE_INDR_INDR12_Pos                (12UL)                    /*!< PE INDR: INDR12 (Bit 12)                              */
+#define PE_INDR_INDR12_Msk                (0x1000UL)                /*!< PE INDR: INDR12 (Bitfield-Mask: 0x01)                 */
+#define PE_INDR_INDR11_Pos                (11UL)                    /*!< PE INDR: INDR11 (Bit 11)                              */
+#define PE_INDR_INDR11_Msk                (0x800UL)                 /*!< PE INDR: INDR11 (Bitfield-Mask: 0x01)                 */
+#define PE_INDR_INDR10_Pos                (10UL)                    /*!< PE INDR: INDR10 (Bit 10)                              */
+#define PE_INDR_INDR10_Msk                (0x400UL)                 /*!< PE INDR: INDR10 (Bitfield-Mask: 0x01)                 */
+#define PE_INDR_INDR9_Pos                 (9UL)                     /*!< PE INDR: INDR9 (Bit 9)                                */
+#define PE_INDR_INDR9_Msk                 (0x200UL)                 /*!< PE INDR: INDR9 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR8_Pos                 (8UL)                     /*!< PE INDR: INDR8 (Bit 8)                                */
+#define PE_INDR_INDR8_Msk                 (0x100UL)                 /*!< PE INDR: INDR8 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR7_Pos                 (7UL)                     /*!< PE INDR: INDR7 (Bit 7)                                */
+#define PE_INDR_INDR7_Msk                 (0x80UL)                  /*!< PE INDR: INDR7 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR6_Pos                 (6UL)                     /*!< PE INDR: INDR6 (Bit 6)                                */
+#define PE_INDR_INDR6_Msk                 (0x40UL)                  /*!< PE INDR: INDR6 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR5_Pos                 (5UL)                     /*!< PE INDR: INDR5 (Bit 5)                                */
+#define PE_INDR_INDR5_Msk                 (0x20UL)                  /*!< PE INDR: INDR5 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR4_Pos                 (4UL)                     /*!< PE INDR: INDR4 (Bit 4)                                */
+#define PE_INDR_INDR4_Msk                 (0x10UL)                  /*!< PE INDR: INDR4 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR3_Pos                 (3UL)                     /*!< PE INDR: INDR3 (Bit 3)                                */
+#define PE_INDR_INDR3_Msk                 (0x8UL)                   /*!< PE INDR: INDR3 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR2_Pos                 (2UL)                     /*!< PE INDR: INDR2 (Bit 2)                                */
+#define PE_INDR_INDR2_Msk                 (0x4UL)                   /*!< PE INDR: INDR2 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR1_Pos                 (1UL)                     /*!< PE INDR: INDR1 (Bit 1)                                */
+#define PE_INDR_INDR1_Msk                 (0x2UL)                   /*!< PE INDR: INDR1 (Bitfield-Mask: 0x01)                  */
+#define PE_INDR_INDR0_Pos                 (0UL)                     /*!< PE INDR: INDR0 (Bit 0)                                */
+#define PE_INDR_INDR0_Msk                 (0x1UL)                   /*!< PE INDR: INDR0 (Bitfield-Mask: 0x01)                  */
+/* =========================================================  OUTDR  ========================================================= */
+#define PE_OUTDR_OUTDR15_Pos              (15UL)                    /*!< PE OUTDR: OUTDR15 (Bit 15)                            */
+#define PE_OUTDR_OUTDR15_Msk              (0x8000UL)                /*!< PE OUTDR: OUTDR15 (Bitfield-Mask: 0x01)               */
+#define PE_OUTDR_OUTDR14_Pos              (14UL)                    /*!< PE OUTDR: OUTDR14 (Bit 14)                            */
+#define PE_OUTDR_OUTDR14_Msk              (0x4000UL)                /*!< PE OUTDR: OUTDR14 (Bitfield-Mask: 0x01)               */
+#define PE_OUTDR_OUTDR13_Pos              (13UL)                    /*!< PE OUTDR: OUTDR13 (Bit 13)                            */
+#define PE_OUTDR_OUTDR13_Msk              (0x2000UL)                /*!< PE OUTDR: OUTDR13 (Bitfield-Mask: 0x01)               */
+#define PE_OUTDR_OUTDR12_Pos              (12UL)                    /*!< PE OUTDR: OUTDR12 (Bit 12)                            */
+#define PE_OUTDR_OUTDR12_Msk              (0x1000UL)                /*!< PE OUTDR: OUTDR12 (Bitfield-Mask: 0x01)               */
+#define PE_OUTDR_OUTDR11_Pos              (11UL)                    /*!< PE OUTDR: OUTDR11 (Bit 11)                            */
+#define PE_OUTDR_OUTDR11_Msk              (0x800UL)                 /*!< PE OUTDR: OUTDR11 (Bitfield-Mask: 0x01)               */
+#define PE_OUTDR_OUTDR10_Pos              (10UL)                    /*!< PE OUTDR: OUTDR10 (Bit 10)                            */
+#define PE_OUTDR_OUTDR10_Msk              (0x400UL)                 /*!< PE OUTDR: OUTDR10 (Bitfield-Mask: 0x01)               */
+#define PE_OUTDR_OUTDR9_Pos               (9UL)                     /*!< PE OUTDR: OUTDR9 (Bit 9)                              */
+#define PE_OUTDR_OUTDR9_Msk               (0x200UL)                 /*!< PE OUTDR: OUTDR9 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR8_Pos               (8UL)                     /*!< PE OUTDR: OUTDR8 (Bit 8)                              */
+#define PE_OUTDR_OUTDR8_Msk               (0x100UL)                 /*!< PE OUTDR: OUTDR8 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR7_Pos               (7UL)                     /*!< PE OUTDR: OUTDR7 (Bit 7)                              */
+#define PE_OUTDR_OUTDR7_Msk               (0x80UL)                  /*!< PE OUTDR: OUTDR7 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR6_Pos               (6UL)                     /*!< PE OUTDR: OUTDR6 (Bit 6)                              */
+#define PE_OUTDR_OUTDR6_Msk               (0x40UL)                  /*!< PE OUTDR: OUTDR6 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR5_Pos               (5UL)                     /*!< PE OUTDR: OUTDR5 (Bit 5)                              */
+#define PE_OUTDR_OUTDR5_Msk               (0x20UL)                  /*!< PE OUTDR: OUTDR5 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR4_Pos               (4UL)                     /*!< PE OUTDR: OUTDR4 (Bit 4)                              */
+#define PE_OUTDR_OUTDR4_Msk               (0x10UL)                  /*!< PE OUTDR: OUTDR4 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR3_Pos               (3UL)                     /*!< PE OUTDR: OUTDR3 (Bit 3)                              */
+#define PE_OUTDR_OUTDR3_Msk               (0x8UL)                   /*!< PE OUTDR: OUTDR3 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR2_Pos               (2UL)                     /*!< PE OUTDR: OUTDR2 (Bit 2)                              */
+#define PE_OUTDR_OUTDR2_Msk               (0x4UL)                   /*!< PE OUTDR: OUTDR2 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR1_Pos               (1UL)                     /*!< PE OUTDR: OUTDR1 (Bit 1)                              */
+#define PE_OUTDR_OUTDR1_Msk               (0x2UL)                   /*!< PE OUTDR: OUTDR1 (Bitfield-Mask: 0x01)                */
+#define PE_OUTDR_OUTDR0_Pos               (0UL)                     /*!< PE OUTDR: OUTDR0 (Bit 0)                              */
+#define PE_OUTDR_OUTDR0_Msk               (0x1UL)                   /*!< PE OUTDR: OUTDR0 (Bitfield-Mask: 0x01)                */
+/* ==========================================================  BSR  ========================================================== */
+#define PE_BSR_BSR15_Pos                  (15UL)                    /*!< PE BSR: BSR15 (Bit 15)                                */
+#define PE_BSR_BSR15_Msk                  (0x8000UL)                /*!< PE BSR: BSR15 (Bitfield-Mask: 0x01)                   */
+#define PE_BSR_BSR14_Pos                  (14UL)                    /*!< PE BSR: BSR14 (Bit 14)                                */
+#define PE_BSR_BSR14_Msk                  (0x4000UL)                /*!< PE BSR: BSR14 (Bitfield-Mask: 0x01)                   */
+#define PE_BSR_BSR13_Pos                  (13UL)                    /*!< PE BSR: BSR13 (Bit 13)                                */
+#define PE_BSR_BSR13_Msk                  (0x2000UL)                /*!< PE BSR: BSR13 (Bitfield-Mask: 0x01)                   */
+#define PE_BSR_BSR12_Pos                  (12UL)                    /*!< PE BSR: BSR12 (Bit 12)                                */
+#define PE_BSR_BSR12_Msk                  (0x1000UL)                /*!< PE BSR: BSR12 (Bitfield-Mask: 0x01)                   */
+#define PE_BSR_BSR11_Pos                  (11UL)                    /*!< PE BSR: BSR11 (Bit 11)                                */
+#define PE_BSR_BSR11_Msk                  (0x800UL)                 /*!< PE BSR: BSR11 (Bitfield-Mask: 0x01)                   */
+#define PE_BSR_BSR10_Pos                  (10UL)                    /*!< PE BSR: BSR10 (Bit 10)                                */
+#define PE_BSR_BSR10_Msk                  (0x400UL)                 /*!< PE BSR: BSR10 (Bitfield-Mask: 0x01)                   */
+#define PE_BSR_BSR9_Pos                   (9UL)                     /*!< PE BSR: BSR9 (Bit 9)                                  */
+#define PE_BSR_BSR9_Msk                   (0x200UL)                 /*!< PE BSR: BSR9 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR8_Pos                   (8UL)                     /*!< PE BSR: BSR8 (Bit 8)                                  */
+#define PE_BSR_BSR8_Msk                   (0x100UL)                 /*!< PE BSR: BSR8 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR7_Pos                   (7UL)                     /*!< PE BSR: BSR7 (Bit 7)                                  */
+#define PE_BSR_BSR7_Msk                   (0x80UL)                  /*!< PE BSR: BSR7 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR6_Pos                   (6UL)                     /*!< PE BSR: BSR6 (Bit 6)                                  */
+#define PE_BSR_BSR6_Msk                   (0x40UL)                  /*!< PE BSR: BSR6 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR5_Pos                   (5UL)                     /*!< PE BSR: BSR5 (Bit 5)                                  */
+#define PE_BSR_BSR5_Msk                   (0x20UL)                  /*!< PE BSR: BSR5 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR4_Pos                   (4UL)                     /*!< PE BSR: BSR4 (Bit 4)                                  */
+#define PE_BSR_BSR4_Msk                   (0x10UL)                  /*!< PE BSR: BSR4 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR3_Pos                   (3UL)                     /*!< PE BSR: BSR3 (Bit 3)                                  */
+#define PE_BSR_BSR3_Msk                   (0x8UL)                   /*!< PE BSR: BSR3 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR2_Pos                   (2UL)                     /*!< PE BSR: BSR2 (Bit 2)                                  */
+#define PE_BSR_BSR2_Msk                   (0x4UL)                   /*!< PE BSR: BSR2 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR1_Pos                   (1UL)                     /*!< PE BSR: BSR1 (Bit 1)                                  */
+#define PE_BSR_BSR1_Msk                   (0x2UL)                   /*!< PE BSR: BSR1 (Bitfield-Mask: 0x01)                    */
+#define PE_BSR_BSR0_Pos                   (0UL)                     /*!< PE BSR: BSR0 (Bit 0)                                  */
+#define PE_BSR_BSR0_Msk                   (0x1UL)                   /*!< PE BSR: BSR0 (Bitfield-Mask: 0x01)                    */
+/* ==========================================================  BCR  ========================================================== */
+#define PE_BCR_BCR15_Pos                  (15UL)                    /*!< PE BCR: BCR15 (Bit 15)                                */
+#define PE_BCR_BCR15_Msk                  (0x8000UL)                /*!< PE BCR: BCR15 (Bitfield-Mask: 0x01)                   */
+#define PE_BCR_BCR14_Pos                  (14UL)                    /*!< PE BCR: BCR14 (Bit 14)                                */
+#define PE_BCR_BCR14_Msk                  (0x4000UL)                /*!< PE BCR: BCR14 (Bitfield-Mask: 0x01)                   */
+#define PE_BCR_BCR13_Pos                  (13UL)                    /*!< PE BCR: BCR13 (Bit 13)                                */
+#define PE_BCR_BCR13_Msk                  (0x2000UL)                /*!< PE BCR: BCR13 (Bitfield-Mask: 0x01)                   */
+#define PE_BCR_BCR12_Pos                  (12UL)                    /*!< PE BCR: BCR12 (Bit 12)                                */
+#define PE_BCR_BCR12_Msk                  (0x1000UL)                /*!< PE BCR: BCR12 (Bitfield-Mask: 0x01)                   */
+#define PE_BCR_BCR11_Pos                  (11UL)                    /*!< PE BCR: BCR11 (Bit 11)                                */
+#define PE_BCR_BCR11_Msk                  (0x800UL)                 /*!< PE BCR: BCR11 (Bitfield-Mask: 0x01)                   */
+#define PE_BCR_BCR10_Pos                  (10UL)                    /*!< PE BCR: BCR10 (Bit 10)                                */
+#define PE_BCR_BCR10_Msk                  (0x400UL)                 /*!< PE BCR: BCR10 (Bitfield-Mask: 0x01)                   */
+#define PE_BCR_BCR9_Pos                   (9UL)                     /*!< PE BCR: BCR9 (Bit 9)                                  */
+#define PE_BCR_BCR9_Msk                   (0x200UL)                 /*!< PE BCR: BCR9 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR8_Pos                   (8UL)                     /*!< PE BCR: BCR8 (Bit 8)                                  */
+#define PE_BCR_BCR8_Msk                   (0x100UL)                 /*!< PE BCR: BCR8 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR7_Pos                   (7UL)                     /*!< PE BCR: BCR7 (Bit 7)                                  */
+#define PE_BCR_BCR7_Msk                   (0x80UL)                  /*!< PE BCR: BCR7 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR6_Pos                   (6UL)                     /*!< PE BCR: BCR6 (Bit 6)                                  */
+#define PE_BCR_BCR6_Msk                   (0x40UL)                  /*!< PE BCR: BCR6 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR5_Pos                   (5UL)                     /*!< PE BCR: BCR5 (Bit 5)                                  */
+#define PE_BCR_BCR5_Msk                   (0x20UL)                  /*!< PE BCR: BCR5 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR4_Pos                   (4UL)                     /*!< PE BCR: BCR4 (Bit 4)                                  */
+#define PE_BCR_BCR4_Msk                   (0x10UL)                  /*!< PE BCR: BCR4 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR3_Pos                   (3UL)                     /*!< PE BCR: BCR3 (Bit 3)                                  */
+#define PE_BCR_BCR3_Msk                   (0x8UL)                   /*!< PE BCR: BCR3 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR2_Pos                   (2UL)                     /*!< PE BCR: BCR2 (Bit 2)                                  */
+#define PE_BCR_BCR2_Msk                   (0x4UL)                   /*!< PE BCR: BCR2 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR1_Pos                   (1UL)                     /*!< PE BCR: BCR1 (Bit 1)                                  */
+#define PE_BCR_BCR1_Msk                   (0x2UL)                   /*!< PE BCR: BCR1 (Bitfield-Mask: 0x01)                    */
+#define PE_BCR_BCR0_Pos                   (0UL)                     /*!< PE BCR: BCR0 (Bit 0)                                  */
+#define PE_BCR_BCR0_Msk                   (0x1UL)                   /*!< PE BCR: BCR0 (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OUTDMSK  ======================================================== */
+#define PE_OUTDMSK_OUTDMSK15_Pos          (15UL)                    /*!< PE OUTDMSK: OUTDMSK15 (Bit 15)                        */
+#define PE_OUTDMSK_OUTDMSK15_Msk          (0x8000UL)                /*!< PE OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)           */
+#define PE_OUTDMSK_OUTDMSK14_Pos          (14UL)                    /*!< PE OUTDMSK: OUTDMSK14 (Bit 14)                        */
+#define PE_OUTDMSK_OUTDMSK14_Msk          (0x4000UL)                /*!< PE OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)           */
+#define PE_OUTDMSK_OUTDMSK13_Pos          (13UL)                    /*!< PE OUTDMSK: OUTDMSK13 (Bit 13)                        */
+#define PE_OUTDMSK_OUTDMSK13_Msk          (0x2000UL)                /*!< PE OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)           */
+#define PE_OUTDMSK_OUTDMSK12_Pos          (12UL)                    /*!< PE OUTDMSK: OUTDMSK12 (Bit 12)                        */
+#define PE_OUTDMSK_OUTDMSK12_Msk          (0x1000UL)                /*!< PE OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)           */
+#define PE_OUTDMSK_OUTDMSK11_Pos          (11UL)                    /*!< PE OUTDMSK: OUTDMSK11 (Bit 11)                        */
+#define PE_OUTDMSK_OUTDMSK11_Msk          (0x800UL)                 /*!< PE OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)           */
+#define PE_OUTDMSK_OUTDMSK10_Pos          (10UL)                    /*!< PE OUTDMSK: OUTDMSK10 (Bit 10)                        */
+#define PE_OUTDMSK_OUTDMSK10_Msk          (0x400UL)                 /*!< PE OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)           */
+#define PE_OUTDMSK_OUTDMSK9_Pos           (9UL)                     /*!< PE OUTDMSK: OUTDMSK9 (Bit 9)                          */
+#define PE_OUTDMSK_OUTDMSK9_Msk           (0x200UL)                 /*!< PE OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK8_Pos           (8UL)                     /*!< PE OUTDMSK: OUTDMSK8 (Bit 8)                          */
+#define PE_OUTDMSK_OUTDMSK8_Msk           (0x100UL)                 /*!< PE OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK7_Pos           (7UL)                     /*!< PE OUTDMSK: OUTDMSK7 (Bit 7)                          */
+#define PE_OUTDMSK_OUTDMSK7_Msk           (0x80UL)                  /*!< PE OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK6_Pos           (6UL)                     /*!< PE OUTDMSK: OUTDMSK6 (Bit 6)                          */
+#define PE_OUTDMSK_OUTDMSK6_Msk           (0x40UL)                  /*!< PE OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK5_Pos           (5UL)                     /*!< PE OUTDMSK: OUTDMSK5 (Bit 5)                          */
+#define PE_OUTDMSK_OUTDMSK5_Msk           (0x20UL)                  /*!< PE OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK4_Pos           (4UL)                     /*!< PE OUTDMSK: OUTDMSK4 (Bit 4)                          */
+#define PE_OUTDMSK_OUTDMSK4_Msk           (0x10UL)                  /*!< PE OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK3_Pos           (3UL)                     /*!< PE OUTDMSK: OUTDMSK3 (Bit 3)                          */
+#define PE_OUTDMSK_OUTDMSK3_Msk           (0x8UL)                   /*!< PE OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK2_Pos           (2UL)                     /*!< PE OUTDMSK: OUTDMSK2 (Bit 2)                          */
+#define PE_OUTDMSK_OUTDMSK2_Msk           (0x4UL)                   /*!< PE OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK1_Pos           (1UL)                     /*!< PE OUTDMSK: OUTDMSK1 (Bit 1)                          */
+#define PE_OUTDMSK_OUTDMSK1_Msk           (0x2UL)                   /*!< PE OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)            */
+#define PE_OUTDMSK_OUTDMSK0_Pos           (0UL)                     /*!< PE OUTDMSK: OUTDMSK0 (Bit 0)                          */
+#define PE_OUTDMSK_OUTDMSK0_Msk           (0x1UL)                   /*!< PE OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)            */
+/* =========================================================  DBCR  ========================================================== */
+#define PE_DBCR_DBCLK_Pos                 (16UL)                    /*!< PE DBCR: DBCLK (Bit 16)                               */
+#define PE_DBCR_DBCLK_Msk                 (0x70000UL)               /*!< PE DBCR: DBCLK (Bitfield-Mask: 0x07)                  */
+#define PE_DBCR_DBEN11_Pos                (11UL)                    /*!< PE DBCR: DBEN11 (Bit 11)                              */
+#define PE_DBCR_DBEN11_Msk                (0x800UL)                 /*!< PE DBCR: DBEN11 (Bitfield-Mask: 0x01)                 */
+#define PE_DBCR_DBEN10_Pos                (10UL)                    /*!< PE DBCR: DBEN10 (Bit 10)                              */
+#define PE_DBCR_DBEN10_Msk                (0x400UL)                 /*!< PE DBCR: DBEN10 (Bitfield-Mask: 0x01)                 */
+#define PE_DBCR_DBEN9_Pos                 (9UL)                     /*!< PE DBCR: DBEN9 (Bit 9)                                */
+#define PE_DBCR_DBEN9_Msk                 (0x200UL)                 /*!< PE DBCR: DBEN9 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN8_Pos                 (8UL)                     /*!< PE DBCR: DBEN8 (Bit 8)                                */
+#define PE_DBCR_DBEN8_Msk                 (0x100UL)                 /*!< PE DBCR: DBEN8 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN7_Pos                 (7UL)                     /*!< PE DBCR: DBEN7 (Bit 7)                                */
+#define PE_DBCR_DBEN7_Msk                 (0x80UL)                  /*!< PE DBCR: DBEN7 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN6_Pos                 (6UL)                     /*!< PE DBCR: DBEN6 (Bit 6)                                */
+#define PE_DBCR_DBEN6_Msk                 (0x40UL)                  /*!< PE DBCR: DBEN6 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN5_Pos                 (5UL)                     /*!< PE DBCR: DBEN5 (Bit 5)                                */
+#define PE_DBCR_DBEN5_Msk                 (0x20UL)                  /*!< PE DBCR: DBEN5 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN4_Pos                 (4UL)                     /*!< PE DBCR: DBEN4 (Bit 4)                                */
+#define PE_DBCR_DBEN4_Msk                 (0x10UL)                  /*!< PE DBCR: DBEN4 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN3_Pos                 (3UL)                     /*!< PE DBCR: DBEN3 (Bit 3)                                */
+#define PE_DBCR_DBEN3_Msk                 (0x8UL)                   /*!< PE DBCR: DBEN3 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN2_Pos                 (2UL)                     /*!< PE DBCR: DBEN2 (Bit 2)                                */
+#define PE_DBCR_DBEN2_Msk                 (0x4UL)                   /*!< PE DBCR: DBEN2 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN1_Pos                 (1UL)                     /*!< PE DBCR: DBEN1 (Bit 1)                                */
+#define PE_DBCR_DBEN1_Msk                 (0x2UL)                   /*!< PE DBCR: DBEN1 (Bitfield-Mask: 0x01)                  */
+#define PE_DBCR_DBEN0_Pos                 (0UL)                     /*!< PE DBCR: DBEN0 (Bit 0)                                */
+#define PE_DBCR_DBEN0_Msk                 (0x1UL)                   /*!< PE DBCR: DBEN0 (Bitfield-Mask: 0x01)                  */
+/* ========================================================  PE_MOD  ========================================================= */
+#define PE_PE_MOD_MODE15_Pos              (30UL)                    /*!< PE PE_MOD: MODE15 (Bit 30)                            */
+#define PE_PE_MOD_MODE15_Msk              (0xc0000000UL)            /*!< PE PE_MOD: MODE15 (Bitfield-Mask: 0x03)               */
+#define PE_PE_MOD_MODE14_Pos              (28UL)                    /*!< PE PE_MOD: MODE14 (Bit 28)                            */
+#define PE_PE_MOD_MODE14_Msk              (0x30000000UL)            /*!< PE PE_MOD: MODE14 (Bitfield-Mask: 0x03)               */
+#define PE_PE_MOD_MODE13_Pos              (26UL)                    /*!< PE PE_MOD: MODE13 (Bit 26)                            */
+#define PE_PE_MOD_MODE13_Msk              (0xc000000UL)             /*!< PE PE_MOD: MODE13 (Bitfield-Mask: 0x03)               */
+#define PE_PE_MOD_MODE12_Pos              (24UL)                    /*!< PE PE_MOD: MODE12 (Bit 24)                            */
+#define PE_PE_MOD_MODE12_Msk              (0x3000000UL)             /*!< PE PE_MOD: MODE12 (Bitfield-Mask: 0x03)               */
+#define PE_PE_MOD_MODE11_Pos              (22UL)                    /*!< PE PE_MOD: MODE11 (Bit 22)                            */
+#define PE_PE_MOD_MODE11_Msk              (0xc00000UL)              /*!< PE PE_MOD: MODE11 (Bitfield-Mask: 0x03)               */
+#define PE_PE_MOD_MODE10_Pos              (20UL)                    /*!< PE PE_MOD: MODE10 (Bit 20)                            */
+#define PE_PE_MOD_MODE10_Msk              (0x300000UL)              /*!< PE PE_MOD: MODE10 (Bitfield-Mask: 0x03)               */
+#define PE_PE_MOD_MODE9_Pos               (18UL)                    /*!< PE PE_MOD: MODE9 (Bit 18)                             */
+#define PE_PE_MOD_MODE9_Msk               (0xc0000UL)               /*!< PE PE_MOD: MODE9 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE8_Pos               (16UL)                    /*!< PE PE_MOD: MODE8 (Bit 16)                             */
+#define PE_PE_MOD_MODE8_Msk               (0x30000UL)               /*!< PE PE_MOD: MODE8 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE7_Pos               (14UL)                    /*!< PE PE_MOD: MODE7 (Bit 14)                             */
+#define PE_PE_MOD_MODE7_Msk               (0xc000UL)                /*!< PE PE_MOD: MODE7 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE6_Pos               (12UL)                    /*!< PE PE_MOD: MODE6 (Bit 12)                             */
+#define PE_PE_MOD_MODE6_Msk               (0x3000UL)                /*!< PE PE_MOD: MODE6 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE5_Pos               (10UL)                    /*!< PE PE_MOD: MODE5 (Bit 10)                             */
+#define PE_PE_MOD_MODE5_Msk               (0xc00UL)                 /*!< PE PE_MOD: MODE5 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE4_Pos               (8UL)                     /*!< PE PE_MOD: MODE4 (Bit 8)                              */
+#define PE_PE_MOD_MODE4_Msk               (0x300UL)                 /*!< PE PE_MOD: MODE4 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE3_Pos               (6UL)                     /*!< PE PE_MOD: MODE3 (Bit 6)                              */
+#define PE_PE_MOD_MODE3_Msk               (0xc0UL)                  /*!< PE PE_MOD: MODE3 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE2_Pos               (4UL)                     /*!< PE PE_MOD: MODE2 (Bit 4)                              */
+#define PE_PE_MOD_MODE2_Msk               (0x30UL)                  /*!< PE PE_MOD: MODE2 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE1_Pos               (2UL)                     /*!< PE PE_MOD: MODE1 (Bit 2)                              */
+#define PE_PE_MOD_MODE1_Msk               (0xcUL)                   /*!< PE PE_MOD: MODE1 (Bitfield-Mask: 0x03)                */
+#define PE_PE_MOD_MODE0_Pos               (0UL)                     /*!< PE PE_MOD: MODE0 (Bit 0)                              */
+#define PE_PE_MOD_MODE0_Msk               (0x3UL)                   /*!< PE PE_MOD: MODE0 (Bitfield-Mask: 0x03)                */
+/* ========================================================  PE_TYP  ========================================================= */
+#define PE_PE_TYP_TYP15_Pos               (15UL)                    /*!< PE PE_TYP: TYP15 (Bit 15)                             */
+#define PE_PE_TYP_TYP15_Msk               (0x8000UL)                /*!< PE PE_TYP: TYP15 (Bitfield-Mask: 0x01)                */
+#define PE_PE_TYP_TYP14_Pos               (14UL)                    /*!< PE PE_TYP: TYP14 (Bit 14)                             */
+#define PE_PE_TYP_TYP14_Msk               (0x4000UL)                /*!< PE PE_TYP: TYP14 (Bitfield-Mask: 0x01)                */
+#define PE_PE_TYP_TYP13_Pos               (13UL)                    /*!< PE PE_TYP: TYP13 (Bit 13)                             */
+#define PE_PE_TYP_TYP13_Msk               (0x2000UL)                /*!< PE PE_TYP: TYP13 (Bitfield-Mask: 0x01)                */
+#define PE_PE_TYP_TYP12_Pos               (12UL)                    /*!< PE PE_TYP: TYP12 (Bit 12)                             */
+#define PE_PE_TYP_TYP12_Msk               (0x1000UL)                /*!< PE PE_TYP: TYP12 (Bitfield-Mask: 0x01)                */
+#define PE_PE_TYP_TYP11_Pos               (11UL)                    /*!< PE PE_TYP: TYP11 (Bit 11)                             */
+#define PE_PE_TYP_TYP11_Msk               (0x800UL)                 /*!< PE PE_TYP: TYP11 (Bitfield-Mask: 0x01)                */
+#define PE_PE_TYP_TYP10_Pos               (10UL)                    /*!< PE PE_TYP: TYP10 (Bit 10)                             */
+#define PE_PE_TYP_TYP10_Msk               (0x400UL)                 /*!< PE PE_TYP: TYP10 (Bitfield-Mask: 0x01)                */
+#define PE_PE_TYP_TYP9_Pos                (9UL)                     /*!< PE PE_TYP: TYP9 (Bit 9)                               */
+#define PE_PE_TYP_TYP9_Msk                (0x200UL)                 /*!< PE PE_TYP: TYP9 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP8_Pos                (8UL)                     /*!< PE PE_TYP: TYP8 (Bit 8)                               */
+#define PE_PE_TYP_TYP8_Msk                (0x100UL)                 /*!< PE PE_TYP: TYP8 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP7_Pos                (7UL)                     /*!< PE PE_TYP: TYP7 (Bit 7)                               */
+#define PE_PE_TYP_TYP7_Msk                (0x80UL)                  /*!< PE PE_TYP: TYP7 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP6_Pos                (6UL)                     /*!< PE PE_TYP: TYP6 (Bit 6)                               */
+#define PE_PE_TYP_TYP6_Msk                (0x40UL)                  /*!< PE PE_TYP: TYP6 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP5_Pos                (5UL)                     /*!< PE PE_TYP: TYP5 (Bit 5)                               */
+#define PE_PE_TYP_TYP5_Msk                (0x20UL)                  /*!< PE PE_TYP: TYP5 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP4_Pos                (4UL)                     /*!< PE PE_TYP: TYP4 (Bit 4)                               */
+#define PE_PE_TYP_TYP4_Msk                (0x10UL)                  /*!< PE PE_TYP: TYP4 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP3_Pos                (3UL)                     /*!< PE PE_TYP: TYP3 (Bit 3)                               */
+#define PE_PE_TYP_TYP3_Msk                (0x8UL)                   /*!< PE PE_TYP: TYP3 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP2_Pos                (2UL)                     /*!< PE PE_TYP: TYP2 (Bit 2)                               */
+#define PE_PE_TYP_TYP2_Msk                (0x4UL)                   /*!< PE PE_TYP: TYP2 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP1_Pos                (1UL)                     /*!< PE PE_TYP: TYP1 (Bit 1)                               */
+#define PE_PE_TYP_TYP1_Msk                (0x2UL)                   /*!< PE PE_TYP: TYP1 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_TYP_TYP0_Pos                (0UL)                     /*!< PE PE_TYP: TYP0 (Bit 0)                               */
+#define PE_PE_TYP_TYP0_Msk                (0x1UL)                   /*!< PE PE_TYP: TYP0 (Bitfield-Mask: 0x01)                 */
+/* =======================================================  PE_AFSR1  ======================================================== */
+#define PE_PE_AFSR1_AFSR7_Pos             (28UL)                    /*!< PE PE_AFSR1: AFSR7 (Bit 28)                           */
+#define PE_PE_AFSR1_AFSR7_Msk             (0xf0000000UL)            /*!< PE PE_AFSR1: AFSR7 (Bitfield-Mask: 0x0f)              */
+#define PE_PE_AFSR1_AFSR6_Pos             (24UL)                    /*!< PE PE_AFSR1: AFSR6 (Bit 24)                           */
+#define PE_PE_AFSR1_AFSR6_Msk             (0xf000000UL)             /*!< PE PE_AFSR1: AFSR6 (Bitfield-Mask: 0x0f)              */
+#define PE_PE_AFSR1_AFSR5_Pos             (20UL)                    /*!< PE PE_AFSR1: AFSR5 (Bit 20)                           */
+#define PE_PE_AFSR1_AFSR5_Msk             (0xf00000UL)              /*!< PE PE_AFSR1: AFSR5 (Bitfield-Mask: 0x0f)              */
+#define PE_PE_AFSR1_AFSR4_Pos             (16UL)                    /*!< PE PE_AFSR1: AFSR4 (Bit 16)                           */
+#define PE_PE_AFSR1_AFSR4_Msk             (0xf0000UL)               /*!< PE PE_AFSR1: AFSR4 (Bitfield-Mask: 0x0f)              */
+#define PE_PE_AFSR1_AFSR3_Pos             (12UL)                    /*!< PE PE_AFSR1: AFSR3 (Bit 12)                           */
+#define PE_PE_AFSR1_AFSR3_Msk             (0xf000UL)                /*!< PE PE_AFSR1: AFSR3 (Bitfield-Mask: 0x0f)              */
+#define PE_PE_AFSR1_AFSR2_Pos             (8UL)                     /*!< PE PE_AFSR1: AFSR2 (Bit 8)                            */
+#define PE_PE_AFSR1_AFSR2_Msk             (0xf00UL)                 /*!< PE PE_AFSR1: AFSR2 (Bitfield-Mask: 0x0f)              */
+#define PE_PE_AFSR1_AFSR1_Pos             (4UL)                     /*!< PE PE_AFSR1: AFSR1 (Bit 4)                            */
+#define PE_PE_AFSR1_AFSR1_Msk             (0xf0UL)                  /*!< PE PE_AFSR1: AFSR1 (Bitfield-Mask: 0x0f)              */
+#define PE_PE_AFSR1_AFSR0_Pos             (0UL)                     /*!< PE PE_AFSR1: AFSR0 (Bit 0)                            */
+#define PE_PE_AFSR1_AFSR0_Msk             (0xfUL)                   /*!< PE PE_AFSR1: AFSR0 (Bitfield-Mask: 0x0f)              */
+/* =======================================================  PE_AFSR2  ======================================================== */
+#define PE_PE_AFSR2_AFSR15_Pos            (28UL)                    /*!< PE PE_AFSR2: AFSR15 (Bit 28)                          */
+#define PE_PE_AFSR2_AFSR15_Msk            (0xf0000000UL)            /*!< PE PE_AFSR2: AFSR15 (Bitfield-Mask: 0x0f)             */
+#define PE_PE_AFSR2_AFSR14_Pos            (24UL)                    /*!< PE PE_AFSR2: AFSR14 (Bit 24)                          */
+#define PE_PE_AFSR2_AFSR14_Msk            (0xf000000UL)             /*!< PE PE_AFSR2: AFSR14 (Bitfield-Mask: 0x0f)             */
+#define PE_PE_AFSR2_AFSR13_Pos            (20UL)                    /*!< PE PE_AFSR2: AFSR13 (Bit 20)                          */
+#define PE_PE_AFSR2_AFSR13_Msk            (0xf00000UL)              /*!< PE PE_AFSR2: AFSR13 (Bitfield-Mask: 0x0f)             */
+#define PE_PE_AFSR2_AFSR12_Pos            (16UL)                    /*!< PE PE_AFSR2: AFSR12 (Bit 16)                          */
+#define PE_PE_AFSR2_AFSR12_Msk            (0xf0000UL)               /*!< PE PE_AFSR2: AFSR12 (Bitfield-Mask: 0x0f)             */
+#define PE_PE_AFSR2_AFSR11_Pos            (12UL)                    /*!< PE PE_AFSR2: AFSR11 (Bit 12)                          */
+#define PE_PE_AFSR2_AFSR11_Msk            (0xf000UL)                /*!< PE PE_AFSR2: AFSR11 (Bitfield-Mask: 0x0f)             */
+#define PE_PE_AFSR2_AFSR10_Pos            (8UL)                     /*!< PE PE_AFSR2: AFSR10 (Bit 8)                           */
+#define PE_PE_AFSR2_AFSR10_Msk            (0xf00UL)                 /*!< PE PE_AFSR2: AFSR10 (Bitfield-Mask: 0x0f)             */
+#define PE_PE_AFSR2_AFSR9_Pos             (4UL)                     /*!< PE PE_AFSR2: AFSR9 (Bit 4)                            */
+#define PE_PE_AFSR2_AFSR9_Msk             (0xf0UL)                  /*!< PE PE_AFSR2: AFSR9 (Bitfield-Mask: 0x0f)              */
+#define PE_PE_AFSR2_AFSR8_Pos             (0UL)                     /*!< PE PE_AFSR2: AFSR8 (Bit 0)                            */
+#define PE_PE_AFSR2_AFSR8_Msk             (0xfUL)                   /*!< PE PE_AFSR2: AFSR8 (Bitfield-Mask: 0x0f)              */
+/* ========================================================  PE_PUPD  ======================================================== */
+#define PE_PE_PUPD_PUPD15_Pos             (30UL)                    /*!< PE PE_PUPD: PUPD15 (Bit 30)                           */
+#define PE_PE_PUPD_PUPD15_Msk             (0xc0000000UL)            /*!< PE PE_PUPD: PUPD15 (Bitfield-Mask: 0x03)              */
+#define PE_PE_PUPD_PUPD14_Pos             (28UL)                    /*!< PE PE_PUPD: PUPD14 (Bit 28)                           */
+#define PE_PE_PUPD_PUPD14_Msk             (0x30000000UL)            /*!< PE PE_PUPD: PUPD14 (Bitfield-Mask: 0x03)              */
+#define PE_PE_PUPD_PUPD13_Pos             (26UL)                    /*!< PE PE_PUPD: PUPD13 (Bit 26)                           */
+#define PE_PE_PUPD_PUPD13_Msk             (0xc000000UL)             /*!< PE PE_PUPD: PUPD13 (Bitfield-Mask: 0x03)              */
+#define PE_PE_PUPD_PUPD12_Pos             (24UL)                    /*!< PE PE_PUPD: PUPD12 (Bit 24)                           */
+#define PE_PE_PUPD_PUPD12_Msk             (0x3000000UL)             /*!< PE PE_PUPD: PUPD12 (Bitfield-Mask: 0x03)              */
+#define PE_PE_PUPD_PUPD11_Pos             (22UL)                    /*!< PE PE_PUPD: PUPD11 (Bit 22)                           */
+#define PE_PE_PUPD_PUPD11_Msk             (0xc00000UL)              /*!< PE PE_PUPD: PUPD11 (Bitfield-Mask: 0x03)              */
+#define PE_PE_PUPD_PUPD10_Pos             (20UL)                    /*!< PE PE_PUPD: PUPD10 (Bit 20)                           */
+#define PE_PE_PUPD_PUPD10_Msk             (0x300000UL)              /*!< PE PE_PUPD: PUPD10 (Bitfield-Mask: 0x03)              */
+#define PE_PE_PUPD_PUPD9_Pos              (18UL)                    /*!< PE PE_PUPD: PUPD9 (Bit 18)                            */
+#define PE_PE_PUPD_PUPD9_Msk              (0xc0000UL)               /*!< PE PE_PUPD: PUPD9 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD8_Pos              (16UL)                    /*!< PE PE_PUPD: PUPD8 (Bit 16)                            */
+#define PE_PE_PUPD_PUPD8_Msk              (0x30000UL)               /*!< PE PE_PUPD: PUPD8 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD7_Pos              (14UL)                    /*!< PE PE_PUPD: PUPD7 (Bit 14)                            */
+#define PE_PE_PUPD_PUPD7_Msk              (0xc000UL)                /*!< PE PE_PUPD: PUPD7 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD6_Pos              (12UL)                    /*!< PE PE_PUPD: PUPD6 (Bit 12)                            */
+#define PE_PE_PUPD_PUPD6_Msk              (0x3000UL)                /*!< PE PE_PUPD: PUPD6 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD5_Pos              (10UL)                    /*!< PE PE_PUPD: PUPD5 (Bit 10)                            */
+#define PE_PE_PUPD_PUPD5_Msk              (0xc00UL)                 /*!< PE PE_PUPD: PUPD5 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD4_Pos              (8UL)                     /*!< PE PE_PUPD: PUPD4 (Bit 8)                             */
+#define PE_PE_PUPD_PUPD4_Msk              (0x300UL)                 /*!< PE PE_PUPD: PUPD4 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD3_Pos              (6UL)                     /*!< PE PE_PUPD: PUPD3 (Bit 6)                             */
+#define PE_PE_PUPD_PUPD3_Msk              (0xc0UL)                  /*!< PE PE_PUPD: PUPD3 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD2_Pos              (4UL)                     /*!< PE PE_PUPD: PUPD2 (Bit 4)                             */
+#define PE_PE_PUPD_PUPD2_Msk              (0x30UL)                  /*!< PE PE_PUPD: PUPD2 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD1_Pos              (2UL)                     /*!< PE PE_PUPD: PUPD1 (Bit 2)                             */
+#define PE_PE_PUPD_PUPD1_Msk              (0xcUL)                   /*!< PE PE_PUPD: PUPD1 (Bitfield-Mask: 0x03)               */
+#define PE_PE_PUPD_PUPD0_Pos              (0UL)                     /*!< PE PE_PUPD: PUPD0 (Bit 0)                             */
+#define PE_PE_PUPD_PUPD0_Msk              (0x3UL)                   /*!< PE PE_PUPD: PUPD0 (Bitfield-Mask: 0x03)               */
+/* ========================================================  PE_INDR  ======================================================== */
+#define PE_PE_INDR_INDR15_Pos             (15UL)                    /*!< PE PE_INDR: INDR15 (Bit 15)                           */
+#define PE_PE_INDR_INDR15_Msk             (0x8000UL)                /*!< PE PE_INDR: INDR15 (Bitfield-Mask: 0x01)              */
+#define PE_PE_INDR_INDR14_Pos             (14UL)                    /*!< PE PE_INDR: INDR14 (Bit 14)                           */
+#define PE_PE_INDR_INDR14_Msk             (0x4000UL)                /*!< PE PE_INDR: INDR14 (Bitfield-Mask: 0x01)              */
+#define PE_PE_INDR_INDR13_Pos             (13UL)                    /*!< PE PE_INDR: INDR13 (Bit 13)                           */
+#define PE_PE_INDR_INDR13_Msk             (0x2000UL)                /*!< PE PE_INDR: INDR13 (Bitfield-Mask: 0x01)              */
+#define PE_PE_INDR_INDR12_Pos             (12UL)                    /*!< PE PE_INDR: INDR12 (Bit 12)                           */
+#define PE_PE_INDR_INDR12_Msk             (0x1000UL)                /*!< PE PE_INDR: INDR12 (Bitfield-Mask: 0x01)              */
+#define PE_PE_INDR_INDR11_Pos             (11UL)                    /*!< PE PE_INDR: INDR11 (Bit 11)                           */
+#define PE_PE_INDR_INDR11_Msk             (0x800UL)                 /*!< PE PE_INDR: INDR11 (Bitfield-Mask: 0x01)              */
+#define PE_PE_INDR_INDR10_Pos             (10UL)                    /*!< PE PE_INDR: INDR10 (Bit 10)                           */
+#define PE_PE_INDR_INDR10_Msk             (0x400UL)                 /*!< PE PE_INDR: INDR10 (Bitfield-Mask: 0x01)              */
+#define PE_PE_INDR_INDR9_Pos              (9UL)                     /*!< PE PE_INDR: INDR9 (Bit 9)                             */
+#define PE_PE_INDR_INDR9_Msk              (0x200UL)                 /*!< PE PE_INDR: INDR9 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR8_Pos              (8UL)                     /*!< PE PE_INDR: INDR8 (Bit 8)                             */
+#define PE_PE_INDR_INDR8_Msk              (0x100UL)                 /*!< PE PE_INDR: INDR8 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR7_Pos              (7UL)                     /*!< PE PE_INDR: INDR7 (Bit 7)                             */
+#define PE_PE_INDR_INDR7_Msk              (0x80UL)                  /*!< PE PE_INDR: INDR7 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR6_Pos              (6UL)                     /*!< PE PE_INDR: INDR6 (Bit 6)                             */
+#define PE_PE_INDR_INDR6_Msk              (0x40UL)                  /*!< PE PE_INDR: INDR6 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR5_Pos              (5UL)                     /*!< PE PE_INDR: INDR5 (Bit 5)                             */
+#define PE_PE_INDR_INDR5_Msk              (0x20UL)                  /*!< PE PE_INDR: INDR5 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR4_Pos              (4UL)                     /*!< PE PE_INDR: INDR4 (Bit 4)                             */
+#define PE_PE_INDR_INDR4_Msk              (0x10UL)                  /*!< PE PE_INDR: INDR4 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR3_Pos              (3UL)                     /*!< PE PE_INDR: INDR3 (Bit 3)                             */
+#define PE_PE_INDR_INDR3_Msk              (0x8UL)                   /*!< PE PE_INDR: INDR3 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR2_Pos              (2UL)                     /*!< PE PE_INDR: INDR2 (Bit 2)                             */
+#define PE_PE_INDR_INDR2_Msk              (0x4UL)                   /*!< PE PE_INDR: INDR2 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR1_Pos              (1UL)                     /*!< PE PE_INDR: INDR1 (Bit 1)                             */
+#define PE_PE_INDR_INDR1_Msk              (0x2UL)                   /*!< PE PE_INDR: INDR1 (Bitfield-Mask: 0x01)               */
+#define PE_PE_INDR_INDR0_Pos              (0UL)                     /*!< PE PE_INDR: INDR0 (Bit 0)                             */
+#define PE_PE_INDR_INDR0_Msk              (0x1UL)                   /*!< PE PE_INDR: INDR0 (Bitfield-Mask: 0x01)               */
+/* =======================================================  PE_OUTDR  ======================================================== */
+#define PE_PE_OUTDR_OUTDR15_Pos           (15UL)                    /*!< PE PE_OUTDR: OUTDR15 (Bit 15)                         */
+#define PE_PE_OUTDR_OUTDR15_Msk           (0x8000UL)                /*!< PE PE_OUTDR: OUTDR15 (Bitfield-Mask: 0x01)            */
+#define PE_PE_OUTDR_OUTDR14_Pos           (14UL)                    /*!< PE PE_OUTDR: OUTDR14 (Bit 14)                         */
+#define PE_PE_OUTDR_OUTDR14_Msk           (0x4000UL)                /*!< PE PE_OUTDR: OUTDR14 (Bitfield-Mask: 0x01)            */
+#define PE_PE_OUTDR_OUTDR13_Pos           (13UL)                    /*!< PE PE_OUTDR: OUTDR13 (Bit 13)                         */
+#define PE_PE_OUTDR_OUTDR13_Msk           (0x2000UL)                /*!< PE PE_OUTDR: OUTDR13 (Bitfield-Mask: 0x01)            */
+#define PE_PE_OUTDR_OUTDR12_Pos           (12UL)                    /*!< PE PE_OUTDR: OUTDR12 (Bit 12)                         */
+#define PE_PE_OUTDR_OUTDR12_Msk           (0x1000UL)                /*!< PE PE_OUTDR: OUTDR12 (Bitfield-Mask: 0x01)            */
+#define PE_PE_OUTDR_OUTDR11_Pos           (11UL)                    /*!< PE PE_OUTDR: OUTDR11 (Bit 11)                         */
+#define PE_PE_OUTDR_OUTDR11_Msk           (0x800UL)                 /*!< PE PE_OUTDR: OUTDR11 (Bitfield-Mask: 0x01)            */
+#define PE_PE_OUTDR_OUTDR10_Pos           (10UL)                    /*!< PE PE_OUTDR: OUTDR10 (Bit 10)                         */
+#define PE_PE_OUTDR_OUTDR10_Msk           (0x400UL)                 /*!< PE PE_OUTDR: OUTDR10 (Bitfield-Mask: 0x01)            */
+#define PE_PE_OUTDR_OUTDR9_Pos            (9UL)                     /*!< PE PE_OUTDR: OUTDR9 (Bit 9)                           */
+#define PE_PE_OUTDR_OUTDR9_Msk            (0x200UL)                 /*!< PE PE_OUTDR: OUTDR9 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR8_Pos            (8UL)                     /*!< PE PE_OUTDR: OUTDR8 (Bit 8)                           */
+#define PE_PE_OUTDR_OUTDR8_Msk            (0x100UL)                 /*!< PE PE_OUTDR: OUTDR8 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR7_Pos            (7UL)                     /*!< PE PE_OUTDR: OUTDR7 (Bit 7)                           */
+#define PE_PE_OUTDR_OUTDR7_Msk            (0x80UL)                  /*!< PE PE_OUTDR: OUTDR7 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR6_Pos            (6UL)                     /*!< PE PE_OUTDR: OUTDR6 (Bit 6)                           */
+#define PE_PE_OUTDR_OUTDR6_Msk            (0x40UL)                  /*!< PE PE_OUTDR: OUTDR6 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR5_Pos            (5UL)                     /*!< PE PE_OUTDR: OUTDR5 (Bit 5)                           */
+#define PE_PE_OUTDR_OUTDR5_Msk            (0x20UL)                  /*!< PE PE_OUTDR: OUTDR5 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR4_Pos            (4UL)                     /*!< PE PE_OUTDR: OUTDR4 (Bit 4)                           */
+#define PE_PE_OUTDR_OUTDR4_Msk            (0x10UL)                  /*!< PE PE_OUTDR: OUTDR4 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR3_Pos            (3UL)                     /*!< PE PE_OUTDR: OUTDR3 (Bit 3)                           */
+#define PE_PE_OUTDR_OUTDR3_Msk            (0x8UL)                   /*!< PE PE_OUTDR: OUTDR3 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR2_Pos            (2UL)                     /*!< PE PE_OUTDR: OUTDR2 (Bit 2)                           */
+#define PE_PE_OUTDR_OUTDR2_Msk            (0x4UL)                   /*!< PE PE_OUTDR: OUTDR2 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR1_Pos            (1UL)                     /*!< PE PE_OUTDR: OUTDR1 (Bit 1)                           */
+#define PE_PE_OUTDR_OUTDR1_Msk            (0x2UL)                   /*!< PE PE_OUTDR: OUTDR1 (Bitfield-Mask: 0x01)             */
+#define PE_PE_OUTDR_OUTDR0_Pos            (0UL)                     /*!< PE PE_OUTDR: OUTDR0 (Bit 0)                           */
+#define PE_PE_OUTDR_OUTDR0_Msk            (0x1UL)                   /*!< PE PE_OUTDR: OUTDR0 (Bitfield-Mask: 0x01)             */
+/* ========================================================  PE_BSR  ========================================================= */
+#define PE_PE_BSR_BSR15_Pos               (15UL)                    /*!< PE PE_BSR: BSR15 (Bit 15)                             */
+#define PE_PE_BSR_BSR15_Msk               (0x8000UL)                /*!< PE PE_BSR: BSR15 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BSR_BSR14_Pos               (14UL)                    /*!< PE PE_BSR: BSR14 (Bit 14)                             */
+#define PE_PE_BSR_BSR14_Msk               (0x4000UL)                /*!< PE PE_BSR: BSR14 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BSR_BSR13_Pos               (13UL)                    /*!< PE PE_BSR: BSR13 (Bit 13)                             */
+#define PE_PE_BSR_BSR13_Msk               (0x2000UL)                /*!< PE PE_BSR: BSR13 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BSR_BSR12_Pos               (12UL)                    /*!< PE PE_BSR: BSR12 (Bit 12)                             */
+#define PE_PE_BSR_BSR12_Msk               (0x1000UL)                /*!< PE PE_BSR: BSR12 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BSR_BSR11_Pos               (11UL)                    /*!< PE PE_BSR: BSR11 (Bit 11)                             */
+#define PE_PE_BSR_BSR11_Msk               (0x800UL)                 /*!< PE PE_BSR: BSR11 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BSR_BSR10_Pos               (10UL)                    /*!< PE PE_BSR: BSR10 (Bit 10)                             */
+#define PE_PE_BSR_BSR10_Msk               (0x400UL)                 /*!< PE PE_BSR: BSR10 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BSR_BSR9_Pos                (9UL)                     /*!< PE PE_BSR: BSR9 (Bit 9)                               */
+#define PE_PE_BSR_BSR9_Msk                (0x200UL)                 /*!< PE PE_BSR: BSR9 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR8_Pos                (8UL)                     /*!< PE PE_BSR: BSR8 (Bit 8)                               */
+#define PE_PE_BSR_BSR8_Msk                (0x100UL)                 /*!< PE PE_BSR: BSR8 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR7_Pos                (7UL)                     /*!< PE PE_BSR: BSR7 (Bit 7)                               */
+#define PE_PE_BSR_BSR7_Msk                (0x80UL)                  /*!< PE PE_BSR: BSR7 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR6_Pos                (6UL)                     /*!< PE PE_BSR: BSR6 (Bit 6)                               */
+#define PE_PE_BSR_BSR6_Msk                (0x40UL)                  /*!< PE PE_BSR: BSR6 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR5_Pos                (5UL)                     /*!< PE PE_BSR: BSR5 (Bit 5)                               */
+#define PE_PE_BSR_BSR5_Msk                (0x20UL)                  /*!< PE PE_BSR: BSR5 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR4_Pos                (4UL)                     /*!< PE PE_BSR: BSR4 (Bit 4)                               */
+#define PE_PE_BSR_BSR4_Msk                (0x10UL)                  /*!< PE PE_BSR: BSR4 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR3_Pos                (3UL)                     /*!< PE PE_BSR: BSR3 (Bit 3)                               */
+#define PE_PE_BSR_BSR3_Msk                (0x8UL)                   /*!< PE PE_BSR: BSR3 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR2_Pos                (2UL)                     /*!< PE PE_BSR: BSR2 (Bit 2)                               */
+#define PE_PE_BSR_BSR2_Msk                (0x4UL)                   /*!< PE PE_BSR: BSR2 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR1_Pos                (1UL)                     /*!< PE PE_BSR: BSR1 (Bit 1)                               */
+#define PE_PE_BSR_BSR1_Msk                (0x2UL)                   /*!< PE PE_BSR: BSR1 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BSR_BSR0_Pos                (0UL)                     /*!< PE PE_BSR: BSR0 (Bit 0)                               */
+#define PE_PE_BSR_BSR0_Msk                (0x1UL)                   /*!< PE PE_BSR: BSR0 (Bitfield-Mask: 0x01)                 */
+/* ========================================================  PE_BCR  ========================================================= */
+#define PE_PE_BCR_BCR15_Pos               (15UL)                    /*!< PE PE_BCR: BCR15 (Bit 15)                             */
+#define PE_PE_BCR_BCR15_Msk               (0x8000UL)                /*!< PE PE_BCR: BCR15 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BCR_BCR14_Pos               (14UL)                    /*!< PE PE_BCR: BCR14 (Bit 14)                             */
+#define PE_PE_BCR_BCR14_Msk               (0x4000UL)                /*!< PE PE_BCR: BCR14 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BCR_BCR13_Pos               (13UL)                    /*!< PE PE_BCR: BCR13 (Bit 13)                             */
+#define PE_PE_BCR_BCR13_Msk               (0x2000UL)                /*!< PE PE_BCR: BCR13 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BCR_BCR12_Pos               (12UL)                    /*!< PE PE_BCR: BCR12 (Bit 12)                             */
+#define PE_PE_BCR_BCR12_Msk               (0x1000UL)                /*!< PE PE_BCR: BCR12 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BCR_BCR11_Pos               (11UL)                    /*!< PE PE_BCR: BCR11 (Bit 11)                             */
+#define PE_PE_BCR_BCR11_Msk               (0x800UL)                 /*!< PE PE_BCR: BCR11 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BCR_BCR10_Pos               (10UL)                    /*!< PE PE_BCR: BCR10 (Bit 10)                             */
+#define PE_PE_BCR_BCR10_Msk               (0x400UL)                 /*!< PE PE_BCR: BCR10 (Bitfield-Mask: 0x01)                */
+#define PE_PE_BCR_BCR9_Pos                (9UL)                     /*!< PE PE_BCR: BCR9 (Bit 9)                               */
+#define PE_PE_BCR_BCR9_Msk                (0x200UL)                 /*!< PE PE_BCR: BCR9 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR8_Pos                (8UL)                     /*!< PE PE_BCR: BCR8 (Bit 8)                               */
+#define PE_PE_BCR_BCR8_Msk                (0x100UL)                 /*!< PE PE_BCR: BCR8 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR7_Pos                (7UL)                     /*!< PE PE_BCR: BCR7 (Bit 7)                               */
+#define PE_PE_BCR_BCR7_Msk                (0x80UL)                  /*!< PE PE_BCR: BCR7 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR6_Pos                (6UL)                     /*!< PE PE_BCR: BCR6 (Bit 6)                               */
+#define PE_PE_BCR_BCR6_Msk                (0x40UL)                  /*!< PE PE_BCR: BCR6 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR5_Pos                (5UL)                     /*!< PE PE_BCR: BCR5 (Bit 5)                               */
+#define PE_PE_BCR_BCR5_Msk                (0x20UL)                  /*!< PE PE_BCR: BCR5 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR4_Pos                (4UL)                     /*!< PE PE_BCR: BCR4 (Bit 4)                               */
+#define PE_PE_BCR_BCR4_Msk                (0x10UL)                  /*!< PE PE_BCR: BCR4 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR3_Pos                (3UL)                     /*!< PE PE_BCR: BCR3 (Bit 3)                               */
+#define PE_PE_BCR_BCR3_Msk                (0x8UL)                   /*!< PE PE_BCR: BCR3 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR2_Pos                (2UL)                     /*!< PE PE_BCR: BCR2 (Bit 2)                               */
+#define PE_PE_BCR_BCR2_Msk                (0x4UL)                   /*!< PE PE_BCR: BCR2 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR1_Pos                (1UL)                     /*!< PE PE_BCR: BCR1 (Bit 1)                               */
+#define PE_PE_BCR_BCR1_Msk                (0x2UL)                   /*!< PE PE_BCR: BCR1 (Bitfield-Mask: 0x01)                 */
+#define PE_PE_BCR_BCR0_Pos                (0UL)                     /*!< PE PE_BCR: BCR0 (Bit 0)                               */
+#define PE_PE_BCR_BCR0_Msk                (0x1UL)                   /*!< PE PE_BCR: BCR0 (Bitfield-Mask: 0x01)                 */
+/* ======================================================  PE_OUTDMSK  ======================================================= */
+#define PE_PE_OUTDMSK_OUTDMSK15_Pos       (15UL)                    /*!< PE PE_OUTDMSK: OUTDMSK15 (Bit 15)                     */
+#define PE_PE_OUTDMSK_OUTDMSK15_Msk       (0x8000UL)                /*!< PE PE_OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)        */
+#define PE_PE_OUTDMSK_OUTDMSK14_Pos       (14UL)                    /*!< PE PE_OUTDMSK: OUTDMSK14 (Bit 14)                     */
+#define PE_PE_OUTDMSK_OUTDMSK14_Msk       (0x4000UL)                /*!< PE PE_OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)        */
+#define PE_PE_OUTDMSK_OUTDMSK13_Pos       (13UL)                    /*!< PE PE_OUTDMSK: OUTDMSK13 (Bit 13)                     */
+#define PE_PE_OUTDMSK_OUTDMSK13_Msk       (0x2000UL)                /*!< PE PE_OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)        */
+#define PE_PE_OUTDMSK_OUTDMSK12_Pos       (12UL)                    /*!< PE PE_OUTDMSK: OUTDMSK12 (Bit 12)                     */
+#define PE_PE_OUTDMSK_OUTDMSK12_Msk       (0x1000UL)                /*!< PE PE_OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)        */
+#define PE_PE_OUTDMSK_OUTDMSK11_Pos       (11UL)                    /*!< PE PE_OUTDMSK: OUTDMSK11 (Bit 11)                     */
+#define PE_PE_OUTDMSK_OUTDMSK11_Msk       (0x800UL)                 /*!< PE PE_OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)        */
+#define PE_PE_OUTDMSK_OUTDMSK10_Pos       (10UL)                    /*!< PE PE_OUTDMSK: OUTDMSK10 (Bit 10)                     */
+#define PE_PE_OUTDMSK_OUTDMSK10_Msk       (0x400UL)                 /*!< PE PE_OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)        */
+#define PE_PE_OUTDMSK_OUTDMSK9_Pos        (9UL)                     /*!< PE PE_OUTDMSK: OUTDMSK9 (Bit 9)                       */
+#define PE_PE_OUTDMSK_OUTDMSK9_Msk        (0x200UL)                 /*!< PE PE_OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK8_Pos        (8UL)                     /*!< PE PE_OUTDMSK: OUTDMSK8 (Bit 8)                       */
+#define PE_PE_OUTDMSK_OUTDMSK8_Msk        (0x100UL)                 /*!< PE PE_OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK7_Pos        (7UL)                     /*!< PE PE_OUTDMSK: OUTDMSK7 (Bit 7)                       */
+#define PE_PE_OUTDMSK_OUTDMSK7_Msk        (0x80UL)                  /*!< PE PE_OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK6_Pos        (6UL)                     /*!< PE PE_OUTDMSK: OUTDMSK6 (Bit 6)                       */
+#define PE_PE_OUTDMSK_OUTDMSK6_Msk        (0x40UL)                  /*!< PE PE_OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK5_Pos        (5UL)                     /*!< PE PE_OUTDMSK: OUTDMSK5 (Bit 5)                       */
+#define PE_PE_OUTDMSK_OUTDMSK5_Msk        (0x20UL)                  /*!< PE PE_OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK4_Pos        (4UL)                     /*!< PE PE_OUTDMSK: OUTDMSK4 (Bit 4)                       */
+#define PE_PE_OUTDMSK_OUTDMSK4_Msk        (0x10UL)                  /*!< PE PE_OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK3_Pos        (3UL)                     /*!< PE PE_OUTDMSK: OUTDMSK3 (Bit 3)                       */
+#define PE_PE_OUTDMSK_OUTDMSK3_Msk        (0x8UL)                   /*!< PE PE_OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK2_Pos        (2UL)                     /*!< PE PE_OUTDMSK: OUTDMSK2 (Bit 2)                       */
+#define PE_PE_OUTDMSK_OUTDMSK2_Msk        (0x4UL)                   /*!< PE PE_OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK1_Pos        (1UL)                     /*!< PE PE_OUTDMSK: OUTDMSK1 (Bit 1)                       */
+#define PE_PE_OUTDMSK_OUTDMSK1_Msk        (0x2UL)                   /*!< PE PE_OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)         */
+#define PE_PE_OUTDMSK_OUTDMSK0_Pos        (0UL)                     /*!< PE PE_OUTDMSK: OUTDMSK0 (Bit 0)                       */
+#define PE_PE_OUTDMSK_OUTDMSK0_Msk        (0x1UL)                   /*!< PE PE_OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)         */
+/* ========================================================  PE_DBCR  ======================================================== */
+#define PE_PE_DBCR_DBCLK_Pos              (16UL)                    /*!< PE PE_DBCR: DBCLK (Bit 16)                            */
+#define PE_PE_DBCR_DBCLK_Msk              (0x70000UL)               /*!< PE PE_DBCR: DBCLK (Bitfield-Mask: 0x07)               */
+#define PE_PE_DBCR_DBEN3_Pos              (3UL)                     /*!< PE PE_DBCR: DBEN3 (Bit 3)                             */
+#define PE_PE_DBCR_DBEN3_Msk              (0x8UL)                   /*!< PE PE_DBCR: DBEN3 (Bitfield-Mask: 0x01)               */
+#define PE_PE_DBCR_DBEN2_Pos              (2UL)                     /*!< PE PE_DBCR: DBEN2 (Bit 2)                             */
+#define PE_PE_DBCR_DBEN2_Msk              (0x4UL)                   /*!< PE PE_DBCR: DBEN2 (Bitfield-Mask: 0x01)               */
+#define PE_PE_DBCR_DBEN1_Pos              (1UL)                     /*!< PE PE_DBCR: DBEN1 (Bit 1)                             */
+#define PE_PE_DBCR_DBEN1_Msk              (0x2UL)                   /*!< PE PE_DBCR: DBEN1 (Bitfield-Mask: 0x01)               */
+#define PE_PE_DBCR_DBEN0_Pos              (0UL)                     /*!< PE PE_DBCR: DBEN0 (Bit 0)                             */
+#define PE_PE_DBCR_DBEN0_Msk              (0x1UL)                   /*!< PE PE_DBCR: DBEN0 (Bitfield-Mask: 0x01)               */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PF                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+#define PF_MOD_MODE15_Pos                 (30UL)                    /*!< PF MOD: MODE15 (Bit 30)                               */
+#define PF_MOD_MODE15_Msk                 (0xc0000000UL)            /*!< PF MOD: MODE15 (Bitfield-Mask: 0x03)                  */
+#define PF_MOD_MODE14_Pos                 (28UL)                    /*!< PF MOD: MODE14 (Bit 28)                               */
+#define PF_MOD_MODE14_Msk                 (0x30000000UL)            /*!< PF MOD: MODE14 (Bitfield-Mask: 0x03)                  */
+#define PF_MOD_MODE13_Pos                 (26UL)                    /*!< PF MOD: MODE13 (Bit 26)                               */
+#define PF_MOD_MODE13_Msk                 (0xc000000UL)             /*!< PF MOD: MODE13 (Bitfield-Mask: 0x03)                  */
+#define PF_MOD_MODE12_Pos                 (24UL)                    /*!< PF MOD: MODE12 (Bit 24)                               */
+#define PF_MOD_MODE12_Msk                 (0x3000000UL)             /*!< PF MOD: MODE12 (Bitfield-Mask: 0x03)                  */
+#define PF_MOD_MODE11_Pos                 (22UL)                    /*!< PF MOD: MODE11 (Bit 22)                               */
+#define PF_MOD_MODE11_Msk                 (0xc00000UL)              /*!< PF MOD: MODE11 (Bitfield-Mask: 0x03)                  */
+#define PF_MOD_MODE10_Pos                 (20UL)                    /*!< PF MOD: MODE10 (Bit 20)                               */
+#define PF_MOD_MODE10_Msk                 (0x300000UL)              /*!< PF MOD: MODE10 (Bitfield-Mask: 0x03)                  */
+#define PF_MOD_MODE9_Pos                  (18UL)                    /*!< PF MOD: MODE9 (Bit 18)                                */
+#define PF_MOD_MODE9_Msk                  (0xc0000UL)               /*!< PF MOD: MODE9 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE8_Pos                  (16UL)                    /*!< PF MOD: MODE8 (Bit 16)                                */
+#define PF_MOD_MODE8_Msk                  (0x30000UL)               /*!< PF MOD: MODE8 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE7_Pos                  (14UL)                    /*!< PF MOD: MODE7 (Bit 14)                                */
+#define PF_MOD_MODE7_Msk                  (0xc000UL)                /*!< PF MOD: MODE7 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE6_Pos                  (12UL)                    /*!< PF MOD: MODE6 (Bit 12)                                */
+#define PF_MOD_MODE6_Msk                  (0x3000UL)                /*!< PF MOD: MODE6 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE5_Pos                  (10UL)                    /*!< PF MOD: MODE5 (Bit 10)                                */
+#define PF_MOD_MODE5_Msk                  (0xc00UL)                 /*!< PF MOD: MODE5 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE4_Pos                  (8UL)                     /*!< PF MOD: MODE4 (Bit 8)                                 */
+#define PF_MOD_MODE4_Msk                  (0x300UL)                 /*!< PF MOD: MODE4 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE3_Pos                  (6UL)                     /*!< PF MOD: MODE3 (Bit 6)                                 */
+#define PF_MOD_MODE3_Msk                  (0xc0UL)                  /*!< PF MOD: MODE3 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE2_Pos                  (4UL)                     /*!< PF MOD: MODE2 (Bit 4)                                 */
+#define PF_MOD_MODE2_Msk                  (0x30UL)                  /*!< PF MOD: MODE2 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE1_Pos                  (2UL)                     /*!< PF MOD: MODE1 (Bit 2)                                 */
+#define PF_MOD_MODE1_Msk                  (0xcUL)                   /*!< PF MOD: MODE1 (Bitfield-Mask: 0x03)                   */
+#define PF_MOD_MODE0_Pos                  (0UL)                     /*!< PF MOD: MODE0 (Bit 0)                                 */
+#define PF_MOD_MODE0_Msk                  (0x3UL)                   /*!< PF MOD: MODE0 (Bitfield-Mask: 0x03)                   */
+/* ==========================================================  TYP  ========================================================== */
+#define PF_TYP_TYP15_Pos                  (15UL)                    /*!< PF TYP: TYP15 (Bit 15)                                */
+#define PF_TYP_TYP15_Msk                  (0x8000UL)                /*!< PF TYP: TYP15 (Bitfield-Mask: 0x01)                   */
+#define PF_TYP_TYP14_Pos                  (14UL)                    /*!< PF TYP: TYP14 (Bit 14)                                */
+#define PF_TYP_TYP14_Msk                  (0x4000UL)                /*!< PF TYP: TYP14 (Bitfield-Mask: 0x01)                   */
+#define PF_TYP_TYP13_Pos                  (13UL)                    /*!< PF TYP: TYP13 (Bit 13)                                */
+#define PF_TYP_TYP13_Msk                  (0x2000UL)                /*!< PF TYP: TYP13 (Bitfield-Mask: 0x01)                   */
+#define PF_TYP_TYP12_Pos                  (12UL)                    /*!< PF TYP: TYP12 (Bit 12)                                */
+#define PF_TYP_TYP12_Msk                  (0x1000UL)                /*!< PF TYP: TYP12 (Bitfield-Mask: 0x01)                   */
+#define PF_TYP_TYP11_Pos                  (11UL)                    /*!< PF TYP: TYP11 (Bit 11)                                */
+#define PF_TYP_TYP11_Msk                  (0x800UL)                 /*!< PF TYP: TYP11 (Bitfield-Mask: 0x01)                   */
+#define PF_TYP_TYP10_Pos                  (10UL)                    /*!< PF TYP: TYP10 (Bit 10)                                */
+#define PF_TYP_TYP10_Msk                  (0x400UL)                 /*!< PF TYP: TYP10 (Bitfield-Mask: 0x01)                   */
+#define PF_TYP_TYP9_Pos                   (9UL)                     /*!< PF TYP: TYP9 (Bit 9)                                  */
+#define PF_TYP_TYP9_Msk                   (0x200UL)                 /*!< PF TYP: TYP9 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP8_Pos                   (8UL)                     /*!< PF TYP: TYP8 (Bit 8)                                  */
+#define PF_TYP_TYP8_Msk                   (0x100UL)                 /*!< PF TYP: TYP8 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP7_Pos                   (7UL)                     /*!< PF TYP: TYP7 (Bit 7)                                  */
+#define PF_TYP_TYP7_Msk                   (0x80UL)                  /*!< PF TYP: TYP7 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP6_Pos                   (6UL)                     /*!< PF TYP: TYP6 (Bit 6)                                  */
+#define PF_TYP_TYP6_Msk                   (0x40UL)                  /*!< PF TYP: TYP6 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP5_Pos                   (5UL)                     /*!< PF TYP: TYP5 (Bit 5)                                  */
+#define PF_TYP_TYP5_Msk                   (0x20UL)                  /*!< PF TYP: TYP5 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP4_Pos                   (4UL)                     /*!< PF TYP: TYP4 (Bit 4)                                  */
+#define PF_TYP_TYP4_Msk                   (0x10UL)                  /*!< PF TYP: TYP4 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP3_Pos                   (3UL)                     /*!< PF TYP: TYP3 (Bit 3)                                  */
+#define PF_TYP_TYP3_Msk                   (0x8UL)                   /*!< PF TYP: TYP3 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP2_Pos                   (2UL)                     /*!< PF TYP: TYP2 (Bit 2)                                  */
+#define PF_TYP_TYP2_Msk                   (0x4UL)                   /*!< PF TYP: TYP2 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP1_Pos                   (1UL)                     /*!< PF TYP: TYP1 (Bit 1)                                  */
+#define PF_TYP_TYP1_Msk                   (0x2UL)                   /*!< PF TYP: TYP1 (Bitfield-Mask: 0x01)                    */
+#define PF_TYP_TYP0_Pos                   (0UL)                     /*!< PF TYP: TYP0 (Bit 0)                                  */
+#define PF_TYP_TYP0_Msk                   (0x1UL)                   /*!< PF TYP: TYP0 (Bitfield-Mask: 0x01)                    */
+/* =========================================================  AFSR1  ========================================================= */
+#define PF_AFSR1_AFSR7_Pos                (28UL)                    /*!< PF AFSR1: AFSR7 (Bit 28)                              */
+#define PF_AFSR1_AFSR7_Msk                (0xf0000000UL)            /*!< PF AFSR1: AFSR7 (Bitfield-Mask: 0x0f)                 */
+#define PF_AFSR1_AFSR6_Pos                (24UL)                    /*!< PF AFSR1: AFSR6 (Bit 24)                              */
+#define PF_AFSR1_AFSR6_Msk                (0xf000000UL)             /*!< PF AFSR1: AFSR6 (Bitfield-Mask: 0x0f)                 */
+#define PF_AFSR1_AFSR5_Pos                (20UL)                    /*!< PF AFSR1: AFSR5 (Bit 20)                              */
+#define PF_AFSR1_AFSR5_Msk                (0xf00000UL)              /*!< PF AFSR1: AFSR5 (Bitfield-Mask: 0x0f)                 */
+#define PF_AFSR1_AFSR4_Pos                (16UL)                    /*!< PF AFSR1: AFSR4 (Bit 16)                              */
+#define PF_AFSR1_AFSR4_Msk                (0xf0000UL)               /*!< PF AFSR1: AFSR4 (Bitfield-Mask: 0x0f)                 */
+#define PF_AFSR1_AFSR3_Pos                (12UL)                    /*!< PF AFSR1: AFSR3 (Bit 12)                              */
+#define PF_AFSR1_AFSR3_Msk                (0xf000UL)                /*!< PF AFSR1: AFSR3 (Bitfield-Mask: 0x0f)                 */
+#define PF_AFSR1_AFSR2_Pos                (8UL)                     /*!< PF AFSR1: AFSR2 (Bit 8)                               */
+#define PF_AFSR1_AFSR2_Msk                (0xf00UL)                 /*!< PF AFSR1: AFSR2 (Bitfield-Mask: 0x0f)                 */
+#define PF_AFSR1_AFSR1_Pos                (4UL)                     /*!< PF AFSR1: AFSR1 (Bit 4)                               */
+#define PF_AFSR1_AFSR1_Msk                (0xf0UL)                  /*!< PF AFSR1: AFSR1 (Bitfield-Mask: 0x0f)                 */
+#define PF_AFSR1_AFSR0_Pos                (0UL)                     /*!< PF AFSR1: AFSR0 (Bit 0)                               */
+#define PF_AFSR1_AFSR0_Msk                (0xfUL)                   /*!< PF AFSR1: AFSR0 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  AFSR2  ========================================================= */
+#define PF_AFSR2_AFSR15_Pos               (28UL)                    /*!< PF AFSR2: AFSR15 (Bit 28)                             */
+#define PF_AFSR2_AFSR15_Msk               (0xf0000000UL)            /*!< PF AFSR2: AFSR15 (Bitfield-Mask: 0x0f)                */
+#define PF_AFSR2_AFSR14_Pos               (24UL)                    /*!< PF AFSR2: AFSR14 (Bit 24)                             */
+#define PF_AFSR2_AFSR14_Msk               (0xf000000UL)             /*!< PF AFSR2: AFSR14 (Bitfield-Mask: 0x0f)                */
+#define PF_AFSR2_AFSR13_Pos               (20UL)                    /*!< PF AFSR2: AFSR13 (Bit 20)                             */
+#define PF_AFSR2_AFSR13_Msk               (0xf00000UL)              /*!< PF AFSR2: AFSR13 (Bitfield-Mask: 0x0f)                */
+#define PF_AFSR2_AFSR12_Pos               (16UL)                    /*!< PF AFSR2: AFSR12 (Bit 16)                             */
+#define PF_AFSR2_AFSR12_Msk               (0xf0000UL)               /*!< PF AFSR2: AFSR12 (Bitfield-Mask: 0x0f)                */
+#define PF_AFSR2_AFSR11_Pos               (12UL)                    /*!< PF AFSR2: AFSR11 (Bit 12)                             */
+#define PF_AFSR2_AFSR11_Msk               (0xf000UL)                /*!< PF AFSR2: AFSR11 (Bitfield-Mask: 0x0f)                */
+#define PF_AFSR2_AFSR10_Pos               (8UL)                     /*!< PF AFSR2: AFSR10 (Bit 8)                              */
+#define PF_AFSR2_AFSR10_Msk               (0xf00UL)                 /*!< PF AFSR2: AFSR10 (Bitfield-Mask: 0x0f)                */
+#define PF_AFSR2_AFSR9_Pos                (4UL)                     /*!< PF AFSR2: AFSR9 (Bit 4)                               */
+#define PF_AFSR2_AFSR9_Msk                (0xf0UL)                  /*!< PF AFSR2: AFSR9 (Bitfield-Mask: 0x0f)                 */
+#define PF_AFSR2_AFSR8_Pos                (0UL)                     /*!< PF AFSR2: AFSR8 (Bit 0)                               */
+#define PF_AFSR2_AFSR8_Msk                (0xfUL)                   /*!< PF AFSR2: AFSR8 (Bitfield-Mask: 0x0f)                 */
+/* =========================================================  PUPD  ========================================================== */
+#define PF_PUPD_PUPD15_Pos                (30UL)                    /*!< PF PUPD: PUPD15 (Bit 30)                              */
+#define PF_PUPD_PUPD15_Msk                (0xc0000000UL)            /*!< PF PUPD: PUPD15 (Bitfield-Mask: 0x03)                 */
+#define PF_PUPD_PUPD14_Pos                (28UL)                    /*!< PF PUPD: PUPD14 (Bit 28)                              */
+#define PF_PUPD_PUPD14_Msk                (0x30000000UL)            /*!< PF PUPD: PUPD14 (Bitfield-Mask: 0x03)                 */
+#define PF_PUPD_PUPD13_Pos                (26UL)                    /*!< PF PUPD: PUPD13 (Bit 26)                              */
+#define PF_PUPD_PUPD13_Msk                (0xc000000UL)             /*!< PF PUPD: PUPD13 (Bitfield-Mask: 0x03)                 */
+#define PF_PUPD_PUPD12_Pos                (24UL)                    /*!< PF PUPD: PUPD12 (Bit 24)                              */
+#define PF_PUPD_PUPD12_Msk                (0x3000000UL)             /*!< PF PUPD: PUPD12 (Bitfield-Mask: 0x03)                 */
+#define PF_PUPD_PUPD11_Pos                (22UL)                    /*!< PF PUPD: PUPD11 (Bit 22)                              */
+#define PF_PUPD_PUPD11_Msk                (0xc00000UL)              /*!< PF PUPD: PUPD11 (Bitfield-Mask: 0x03)                 */
+#define PF_PUPD_PUPD10_Pos                (20UL)                    /*!< PF PUPD: PUPD10 (Bit 20)                              */
+#define PF_PUPD_PUPD10_Msk                (0x300000UL)              /*!< PF PUPD: PUPD10 (Bitfield-Mask: 0x03)                 */
+#define PF_PUPD_PUPD9_Pos                 (18UL)                    /*!< PF PUPD: PUPD9 (Bit 18)                               */
+#define PF_PUPD_PUPD9_Msk                 (0xc0000UL)               /*!< PF PUPD: PUPD9 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD8_Pos                 (16UL)                    /*!< PF PUPD: PUPD8 (Bit 16)                               */
+#define PF_PUPD_PUPD8_Msk                 (0x30000UL)               /*!< PF PUPD: PUPD8 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD7_Pos                 (14UL)                    /*!< PF PUPD: PUPD7 (Bit 14)                               */
+#define PF_PUPD_PUPD7_Msk                 (0xc000UL)                /*!< PF PUPD: PUPD7 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD6_Pos                 (12UL)                    /*!< PF PUPD: PUPD6 (Bit 12)                               */
+#define PF_PUPD_PUPD6_Msk                 (0x3000UL)                /*!< PF PUPD: PUPD6 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD5_Pos                 (10UL)                    /*!< PF PUPD: PUPD5 (Bit 10)                               */
+#define PF_PUPD_PUPD5_Msk                 (0xc00UL)                 /*!< PF PUPD: PUPD5 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD4_Pos                 (8UL)                     /*!< PF PUPD: PUPD4 (Bit 8)                                */
+#define PF_PUPD_PUPD4_Msk                 (0x300UL)                 /*!< PF PUPD: PUPD4 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD3_Pos                 (6UL)                     /*!< PF PUPD: PUPD3 (Bit 6)                                */
+#define PF_PUPD_PUPD3_Msk                 (0xc0UL)                  /*!< PF PUPD: PUPD3 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD2_Pos                 (4UL)                     /*!< PF PUPD: PUPD2 (Bit 4)                                */
+#define PF_PUPD_PUPD2_Msk                 (0x30UL)                  /*!< PF PUPD: PUPD2 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD1_Pos                 (2UL)                     /*!< PF PUPD: PUPD1 (Bit 2)                                */
+#define PF_PUPD_PUPD1_Msk                 (0xcUL)                   /*!< PF PUPD: PUPD1 (Bitfield-Mask: 0x03)                  */
+#define PF_PUPD_PUPD0_Pos                 (0UL)                     /*!< PF PUPD: PUPD0 (Bit 0)                                */
+#define PF_PUPD_PUPD0_Msk                 (0x3UL)                   /*!< PF PUPD: PUPD0 (Bitfield-Mask: 0x03)                  */
+/* =========================================================  INDR  ========================================================== */
+#define PF_INDR_INDR15_Pos                (15UL)                    /*!< PF INDR: INDR15 (Bit 15)                              */
+#define PF_INDR_INDR15_Msk                (0x8000UL)                /*!< PF INDR: INDR15 (Bitfield-Mask: 0x01)                 */
+#define PF_INDR_INDR14_Pos                (14UL)                    /*!< PF INDR: INDR14 (Bit 14)                              */
+#define PF_INDR_INDR14_Msk                (0x4000UL)                /*!< PF INDR: INDR14 (Bitfield-Mask: 0x01)                 */
+#define PF_INDR_INDR13_Pos                (13UL)                    /*!< PF INDR: INDR13 (Bit 13)                              */
+#define PF_INDR_INDR13_Msk                (0x2000UL)                /*!< PF INDR: INDR13 (Bitfield-Mask: 0x01)                 */
+#define PF_INDR_INDR12_Pos                (12UL)                    /*!< PF INDR: INDR12 (Bit 12)                              */
+#define PF_INDR_INDR12_Msk                (0x1000UL)                /*!< PF INDR: INDR12 (Bitfield-Mask: 0x01)                 */
+#define PF_INDR_INDR11_Pos                (11UL)                    /*!< PF INDR: INDR11 (Bit 11)                              */
+#define PF_INDR_INDR11_Msk                (0x800UL)                 /*!< PF INDR: INDR11 (Bitfield-Mask: 0x01)                 */
+#define PF_INDR_INDR10_Pos                (10UL)                    /*!< PF INDR: INDR10 (Bit 10)                              */
+#define PF_INDR_INDR10_Msk                (0x400UL)                 /*!< PF INDR: INDR10 (Bitfield-Mask: 0x01)                 */
+#define PF_INDR_INDR9_Pos                 (9UL)                     /*!< PF INDR: INDR9 (Bit 9)                                */
+#define PF_INDR_INDR9_Msk                 (0x200UL)                 /*!< PF INDR: INDR9 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR8_Pos                 (8UL)                     /*!< PF INDR: INDR8 (Bit 8)                                */
+#define PF_INDR_INDR8_Msk                 (0x100UL)                 /*!< PF INDR: INDR8 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR7_Pos                 (7UL)                     /*!< PF INDR: INDR7 (Bit 7)                                */
+#define PF_INDR_INDR7_Msk                 (0x80UL)                  /*!< PF INDR: INDR7 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR6_Pos                 (6UL)                     /*!< PF INDR: INDR6 (Bit 6)                                */
+#define PF_INDR_INDR6_Msk                 (0x40UL)                  /*!< PF INDR: INDR6 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR5_Pos                 (5UL)                     /*!< PF INDR: INDR5 (Bit 5)                                */
+#define PF_INDR_INDR5_Msk                 (0x20UL)                  /*!< PF INDR: INDR5 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR4_Pos                 (4UL)                     /*!< PF INDR: INDR4 (Bit 4)                                */
+#define PF_INDR_INDR4_Msk                 (0x10UL)                  /*!< PF INDR: INDR4 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR3_Pos                 (3UL)                     /*!< PF INDR: INDR3 (Bit 3)                                */
+#define PF_INDR_INDR3_Msk                 (0x8UL)                   /*!< PF INDR: INDR3 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR2_Pos                 (2UL)                     /*!< PF INDR: INDR2 (Bit 2)                                */
+#define PF_INDR_INDR2_Msk                 (0x4UL)                   /*!< PF INDR: INDR2 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR1_Pos                 (1UL)                     /*!< PF INDR: INDR1 (Bit 1)                                */
+#define PF_INDR_INDR1_Msk                 (0x2UL)                   /*!< PF INDR: INDR1 (Bitfield-Mask: 0x01)                  */
+#define PF_INDR_INDR0_Pos                 (0UL)                     /*!< PF INDR: INDR0 (Bit 0)                                */
+#define PF_INDR_INDR0_Msk                 (0x1UL)                   /*!< PF INDR: INDR0 (Bitfield-Mask: 0x01)                  */
+/* =========================================================  OUTDR  ========================================================= */
+#define PF_OUTDR_OUTDR15_Pos              (15UL)                    /*!< PF OUTDR: OUTDR15 (Bit 15)                            */
+#define PF_OUTDR_OUTDR15_Msk              (0x8000UL)                /*!< PF OUTDR: OUTDR15 (Bitfield-Mask: 0x01)               */
+#define PF_OUTDR_OUTDR14_Pos              (14UL)                    /*!< PF OUTDR: OUTDR14 (Bit 14)                            */
+#define PF_OUTDR_OUTDR14_Msk              (0x4000UL)                /*!< PF OUTDR: OUTDR14 (Bitfield-Mask: 0x01)               */
+#define PF_OUTDR_OUTDR13_Pos              (13UL)                    /*!< PF OUTDR: OUTDR13 (Bit 13)                            */
+#define PF_OUTDR_OUTDR13_Msk              (0x2000UL)                /*!< PF OUTDR: OUTDR13 (Bitfield-Mask: 0x01)               */
+#define PF_OUTDR_OUTDR12_Pos              (12UL)                    /*!< PF OUTDR: OUTDR12 (Bit 12)                            */
+#define PF_OUTDR_OUTDR12_Msk              (0x1000UL)                /*!< PF OUTDR: OUTDR12 (Bitfield-Mask: 0x01)               */
+#define PF_OUTDR_OUTDR11_Pos              (11UL)                    /*!< PF OUTDR: OUTDR11 (Bit 11)                            */
+#define PF_OUTDR_OUTDR11_Msk              (0x800UL)                 /*!< PF OUTDR: OUTDR11 (Bitfield-Mask: 0x01)               */
+#define PF_OUTDR_OUTDR10_Pos              (10UL)                    /*!< PF OUTDR: OUTDR10 (Bit 10)                            */
+#define PF_OUTDR_OUTDR10_Msk              (0x400UL)                 /*!< PF OUTDR: OUTDR10 (Bitfield-Mask: 0x01)               */
+#define PF_OUTDR_OUTDR9_Pos               (9UL)                     /*!< PF OUTDR: OUTDR9 (Bit 9)                              */
+#define PF_OUTDR_OUTDR9_Msk               (0x200UL)                 /*!< PF OUTDR: OUTDR9 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR8_Pos               (8UL)                     /*!< PF OUTDR: OUTDR8 (Bit 8)                              */
+#define PF_OUTDR_OUTDR8_Msk               (0x100UL)                 /*!< PF OUTDR: OUTDR8 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR7_Pos               (7UL)                     /*!< PF OUTDR: OUTDR7 (Bit 7)                              */
+#define PF_OUTDR_OUTDR7_Msk               (0x80UL)                  /*!< PF OUTDR: OUTDR7 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR6_Pos               (6UL)                     /*!< PF OUTDR: OUTDR6 (Bit 6)                              */
+#define PF_OUTDR_OUTDR6_Msk               (0x40UL)                  /*!< PF OUTDR: OUTDR6 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR5_Pos               (5UL)                     /*!< PF OUTDR: OUTDR5 (Bit 5)                              */
+#define PF_OUTDR_OUTDR5_Msk               (0x20UL)                  /*!< PF OUTDR: OUTDR5 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR4_Pos               (4UL)                     /*!< PF OUTDR: OUTDR4 (Bit 4)                              */
+#define PF_OUTDR_OUTDR4_Msk               (0x10UL)                  /*!< PF OUTDR: OUTDR4 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR3_Pos               (3UL)                     /*!< PF OUTDR: OUTDR3 (Bit 3)                              */
+#define PF_OUTDR_OUTDR3_Msk               (0x8UL)                   /*!< PF OUTDR: OUTDR3 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR2_Pos               (2UL)                     /*!< PF OUTDR: OUTDR2 (Bit 2)                              */
+#define PF_OUTDR_OUTDR2_Msk               (0x4UL)                   /*!< PF OUTDR: OUTDR2 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR1_Pos               (1UL)                     /*!< PF OUTDR: OUTDR1 (Bit 1)                              */
+#define PF_OUTDR_OUTDR1_Msk               (0x2UL)                   /*!< PF OUTDR: OUTDR1 (Bitfield-Mask: 0x01)                */
+#define PF_OUTDR_OUTDR0_Pos               (0UL)                     /*!< PF OUTDR: OUTDR0 (Bit 0)                              */
+#define PF_OUTDR_OUTDR0_Msk               (0x1UL)                   /*!< PF OUTDR: OUTDR0 (Bitfield-Mask: 0x01)                */
+/* ==========================================================  BSR  ========================================================== */
+#define PF_BSR_BSR15_Pos                  (15UL)                    /*!< PF BSR: BSR15 (Bit 15)                                */
+#define PF_BSR_BSR15_Msk                  (0x8000UL)                /*!< PF BSR: BSR15 (Bitfield-Mask: 0x01)                   */
+#define PF_BSR_BSR14_Pos                  (14UL)                    /*!< PF BSR: BSR14 (Bit 14)                                */
+#define PF_BSR_BSR14_Msk                  (0x4000UL)                /*!< PF BSR: BSR14 (Bitfield-Mask: 0x01)                   */
+#define PF_BSR_BSR13_Pos                  (13UL)                    /*!< PF BSR: BSR13 (Bit 13)                                */
+#define PF_BSR_BSR13_Msk                  (0x2000UL)                /*!< PF BSR: BSR13 (Bitfield-Mask: 0x01)                   */
+#define PF_BSR_BSR12_Pos                  (12UL)                    /*!< PF BSR: BSR12 (Bit 12)                                */
+#define PF_BSR_BSR12_Msk                  (0x1000UL)                /*!< PF BSR: BSR12 (Bitfield-Mask: 0x01)                   */
+#define PF_BSR_BSR11_Pos                  (11UL)                    /*!< PF BSR: BSR11 (Bit 11)                                */
+#define PF_BSR_BSR11_Msk                  (0x800UL)                 /*!< PF BSR: BSR11 (Bitfield-Mask: 0x01)                   */
+#define PF_BSR_BSR10_Pos                  (10UL)                    /*!< PF BSR: BSR10 (Bit 10)                                */
+#define PF_BSR_BSR10_Msk                  (0x400UL)                 /*!< PF BSR: BSR10 (Bitfield-Mask: 0x01)                   */
+#define PF_BSR_BSR9_Pos                   (9UL)                     /*!< PF BSR: BSR9 (Bit 9)                                  */
+#define PF_BSR_BSR9_Msk                   (0x200UL)                 /*!< PF BSR: BSR9 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR8_Pos                   (8UL)                     /*!< PF BSR: BSR8 (Bit 8)                                  */
+#define PF_BSR_BSR8_Msk                   (0x100UL)                 /*!< PF BSR: BSR8 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR7_Pos                   (7UL)                     /*!< PF BSR: BSR7 (Bit 7)                                  */
+#define PF_BSR_BSR7_Msk                   (0x80UL)                  /*!< PF BSR: BSR7 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR6_Pos                   (6UL)                     /*!< PF BSR: BSR6 (Bit 6)                                  */
+#define PF_BSR_BSR6_Msk                   (0x40UL)                  /*!< PF BSR: BSR6 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR5_Pos                   (5UL)                     /*!< PF BSR: BSR5 (Bit 5)                                  */
+#define PF_BSR_BSR5_Msk                   (0x20UL)                  /*!< PF BSR: BSR5 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR4_Pos                   (4UL)                     /*!< PF BSR: BSR4 (Bit 4)                                  */
+#define PF_BSR_BSR4_Msk                   (0x10UL)                  /*!< PF BSR: BSR4 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR3_Pos                   (3UL)                     /*!< PF BSR: BSR3 (Bit 3)                                  */
+#define PF_BSR_BSR3_Msk                   (0x8UL)                   /*!< PF BSR: BSR3 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR2_Pos                   (2UL)                     /*!< PF BSR: BSR2 (Bit 2)                                  */
+#define PF_BSR_BSR2_Msk                   (0x4UL)                   /*!< PF BSR: BSR2 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR1_Pos                   (1UL)                     /*!< PF BSR: BSR1 (Bit 1)                                  */
+#define PF_BSR_BSR1_Msk                   (0x2UL)                   /*!< PF BSR: BSR1 (Bitfield-Mask: 0x01)                    */
+#define PF_BSR_BSR0_Pos                   (0UL)                     /*!< PF BSR: BSR0 (Bit 0)                                  */
+#define PF_BSR_BSR0_Msk                   (0x1UL)                   /*!< PF BSR: BSR0 (Bitfield-Mask: 0x01)                    */
+/* ==========================================================  BCR  ========================================================== */
+#define PF_BCR_BCR15_Pos                  (15UL)                    /*!< PF BCR: BCR15 (Bit 15)                                */
+#define PF_BCR_BCR15_Msk                  (0x8000UL)                /*!< PF BCR: BCR15 (Bitfield-Mask: 0x01)                   */
+#define PF_BCR_BCR14_Pos                  (14UL)                    /*!< PF BCR: BCR14 (Bit 14)                                */
+#define PF_BCR_BCR14_Msk                  (0x4000UL)                /*!< PF BCR: BCR14 (Bitfield-Mask: 0x01)                   */
+#define PF_BCR_BCR13_Pos                  (13UL)                    /*!< PF BCR: BCR13 (Bit 13)                                */
+#define PF_BCR_BCR13_Msk                  (0x2000UL)                /*!< PF BCR: BCR13 (Bitfield-Mask: 0x01)                   */
+#define PF_BCR_BCR12_Pos                  (12UL)                    /*!< PF BCR: BCR12 (Bit 12)                                */
+#define PF_BCR_BCR12_Msk                  (0x1000UL)                /*!< PF BCR: BCR12 (Bitfield-Mask: 0x01)                   */
+#define PF_BCR_BCR11_Pos                  (11UL)                    /*!< PF BCR: BCR11 (Bit 11)                                */
+#define PF_BCR_BCR11_Msk                  (0x800UL)                 /*!< PF BCR: BCR11 (Bitfield-Mask: 0x01)                   */
+#define PF_BCR_BCR10_Pos                  (10UL)                    /*!< PF BCR: BCR10 (Bit 10)                                */
+#define PF_BCR_BCR10_Msk                  (0x400UL)                 /*!< PF BCR: BCR10 (Bitfield-Mask: 0x01)                   */
+#define PF_BCR_BCR9_Pos                   (9UL)                     /*!< PF BCR: BCR9 (Bit 9)                                  */
+#define PF_BCR_BCR9_Msk                   (0x200UL)                 /*!< PF BCR: BCR9 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR8_Pos                   (8UL)                     /*!< PF BCR: BCR8 (Bit 8)                                  */
+#define PF_BCR_BCR8_Msk                   (0x100UL)                 /*!< PF BCR: BCR8 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR7_Pos                   (7UL)                     /*!< PF BCR: BCR7 (Bit 7)                                  */
+#define PF_BCR_BCR7_Msk                   (0x80UL)                  /*!< PF BCR: BCR7 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR6_Pos                   (6UL)                     /*!< PF BCR: BCR6 (Bit 6)                                  */
+#define PF_BCR_BCR6_Msk                   (0x40UL)                  /*!< PF BCR: BCR6 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR5_Pos                   (5UL)                     /*!< PF BCR: BCR5 (Bit 5)                                  */
+#define PF_BCR_BCR5_Msk                   (0x20UL)                  /*!< PF BCR: BCR5 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR4_Pos                   (4UL)                     /*!< PF BCR: BCR4 (Bit 4)                                  */
+#define PF_BCR_BCR4_Msk                   (0x10UL)                  /*!< PF BCR: BCR4 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR3_Pos                   (3UL)                     /*!< PF BCR: BCR3 (Bit 3)                                  */
+#define PF_BCR_BCR3_Msk                   (0x8UL)                   /*!< PF BCR: BCR3 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR2_Pos                   (2UL)                     /*!< PF BCR: BCR2 (Bit 2)                                  */
+#define PF_BCR_BCR2_Msk                   (0x4UL)                   /*!< PF BCR: BCR2 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR1_Pos                   (1UL)                     /*!< PF BCR: BCR1 (Bit 1)                                  */
+#define PF_BCR_BCR1_Msk                   (0x2UL)                   /*!< PF BCR: BCR1 (Bitfield-Mask: 0x01)                    */
+#define PF_BCR_BCR0_Pos                   (0UL)                     /*!< PF BCR: BCR0 (Bit 0)                                  */
+#define PF_BCR_BCR0_Msk                   (0x1UL)                   /*!< PF BCR: BCR0 (Bitfield-Mask: 0x01)                    */
+/* ========================================================  OUTDMSK  ======================================================== */
+#define PF_OUTDMSK_OUTDMSK15_Pos          (15UL)                    /*!< PF OUTDMSK: OUTDMSK15 (Bit 15)                        */
+#define PF_OUTDMSK_OUTDMSK15_Msk          (0x8000UL)                /*!< PF OUTDMSK: OUTDMSK15 (Bitfield-Mask: 0x01)           */
+#define PF_OUTDMSK_OUTDMSK14_Pos          (14UL)                    /*!< PF OUTDMSK: OUTDMSK14 (Bit 14)                        */
+#define PF_OUTDMSK_OUTDMSK14_Msk          (0x4000UL)                /*!< PF OUTDMSK: OUTDMSK14 (Bitfield-Mask: 0x01)           */
+#define PF_OUTDMSK_OUTDMSK13_Pos          (13UL)                    /*!< PF OUTDMSK: OUTDMSK13 (Bit 13)                        */
+#define PF_OUTDMSK_OUTDMSK13_Msk          (0x2000UL)                /*!< PF OUTDMSK: OUTDMSK13 (Bitfield-Mask: 0x01)           */
+#define PF_OUTDMSK_OUTDMSK12_Pos          (12UL)                    /*!< PF OUTDMSK: OUTDMSK12 (Bit 12)                        */
+#define PF_OUTDMSK_OUTDMSK12_Msk          (0x1000UL)                /*!< PF OUTDMSK: OUTDMSK12 (Bitfield-Mask: 0x01)           */
+#define PF_OUTDMSK_OUTDMSK11_Pos          (11UL)                    /*!< PF OUTDMSK: OUTDMSK11 (Bit 11)                        */
+#define PF_OUTDMSK_OUTDMSK11_Msk          (0x800UL)                 /*!< PF OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)           */
+#define PF_OUTDMSK_OUTDMSK10_Pos          (10UL)                    /*!< PF OUTDMSK: OUTDMSK10 (Bit 10)                        */
+#define PF_OUTDMSK_OUTDMSK10_Msk          (0x400UL)                 /*!< PF OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)           */
+#define PF_OUTDMSK_OUTDMSK9_Pos           (9UL)                     /*!< PF OUTDMSK: OUTDMSK9 (Bit 9)                          */
+#define PF_OUTDMSK_OUTDMSK9_Msk           (0x200UL)                 /*!< PF OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK8_Pos           (8UL)                     /*!< PF OUTDMSK: OUTDMSK8 (Bit 8)                          */
+#define PF_OUTDMSK_OUTDMSK8_Msk           (0x100UL)                 /*!< PF OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK7_Pos           (7UL)                     /*!< PF OUTDMSK: OUTDMSK7 (Bit 7)                          */
+#define PF_OUTDMSK_OUTDMSK7_Msk           (0x80UL)                  /*!< PF OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK6_Pos           (6UL)                     /*!< PF OUTDMSK: OUTDMSK6 (Bit 6)                          */
+#define PF_OUTDMSK_OUTDMSK6_Msk           (0x40UL)                  /*!< PF OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK5_Pos           (5UL)                     /*!< PF OUTDMSK: OUTDMSK5 (Bit 5)                          */
+#define PF_OUTDMSK_OUTDMSK5_Msk           (0x20UL)                  /*!< PF OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK4_Pos           (4UL)                     /*!< PF OUTDMSK: OUTDMSK4 (Bit 4)                          */
+#define PF_OUTDMSK_OUTDMSK4_Msk           (0x10UL)                  /*!< PF OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK3_Pos           (3UL)                     /*!< PF OUTDMSK: OUTDMSK3 (Bit 3)                          */
+#define PF_OUTDMSK_OUTDMSK3_Msk           (0x8UL)                   /*!< PF OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK2_Pos           (2UL)                     /*!< PF OUTDMSK: OUTDMSK2 (Bit 2)                          */
+#define PF_OUTDMSK_OUTDMSK2_Msk           (0x4UL)                   /*!< PF OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK1_Pos           (1UL)                     /*!< PF OUTDMSK: OUTDMSK1 (Bit 1)                          */
+#define PF_OUTDMSK_OUTDMSK1_Msk           (0x2UL)                   /*!< PF OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)            */
+#define PF_OUTDMSK_OUTDMSK0_Pos           (0UL)                     /*!< PF OUTDMSK: OUTDMSK0 (Bit 0)                          */
+#define PF_OUTDMSK_OUTDMSK0_Msk           (0x1UL)                   /*!< PF OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)            */
+/* =========================================================  DBCR  ========================================================== */
+#define PF_DBCR_DBCLK_Pos                 (16UL)                    /*!< PF DBCR: DBCLK (Bit 16)                               */
+#define PF_DBCR_DBCLK_Msk                 (0x70000UL)               /*!< PF DBCR: DBCLK (Bitfield-Mask: 0x07)                  */
+#define PF_DBCR_DBEN11_Pos                (11UL)                    /*!< PF DBCR: DBEN11 (Bit 11)                              */
+#define PF_DBCR_DBEN11_Msk                (0x800UL)                 /*!< PF DBCR: DBEN11 (Bitfield-Mask: 0x01)                 */
+#define PF_DBCR_DBEN10_Pos                (10UL)                    /*!< PF DBCR: DBEN10 (Bit 10)                              */
+#define PF_DBCR_DBEN10_Msk                (0x400UL)                 /*!< PF DBCR: DBEN10 (Bitfield-Mask: 0x01)                 */
+#define PF_DBCR_DBEN9_Pos                 (9UL)                     /*!< PF DBCR: DBEN9 (Bit 9)                                */
+#define PF_DBCR_DBEN9_Msk                 (0x200UL)                 /*!< PF DBCR: DBEN9 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN8_Pos                 (8UL)                     /*!< PF DBCR: DBEN8 (Bit 8)                                */
+#define PF_DBCR_DBEN8_Msk                 (0x100UL)                 /*!< PF DBCR: DBEN8 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN7_Pos                 (7UL)                     /*!< PF DBCR: DBEN7 (Bit 7)                                */
+#define PF_DBCR_DBEN7_Msk                 (0x80UL)                  /*!< PF DBCR: DBEN7 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN6_Pos                 (6UL)                     /*!< PF DBCR: DBEN6 (Bit 6)                                */
+#define PF_DBCR_DBEN6_Msk                 (0x40UL)                  /*!< PF DBCR: DBEN6 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN5_Pos                 (5UL)                     /*!< PF DBCR: DBEN5 (Bit 5)                                */
+#define PF_DBCR_DBEN5_Msk                 (0x20UL)                  /*!< PF DBCR: DBEN5 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN4_Pos                 (4UL)                     /*!< PF DBCR: DBEN4 (Bit 4)                                */
+#define PF_DBCR_DBEN4_Msk                 (0x10UL)                  /*!< PF DBCR: DBEN4 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN3_Pos                 (3UL)                     /*!< PF DBCR: DBEN3 (Bit 3)                                */
+#define PF_DBCR_DBEN3_Msk                 (0x8UL)                   /*!< PF DBCR: DBEN3 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN2_Pos                 (2UL)                     /*!< PF DBCR: DBEN2 (Bit 2)                                */
+#define PF_DBCR_DBEN2_Msk                 (0x4UL)                   /*!< PF DBCR: DBEN2 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN1_Pos                 (1UL)                     /*!< PF DBCR: DBEN1 (Bit 1)                                */
+#define PF_DBCR_DBEN1_Msk                 (0x2UL)                   /*!< PF DBCR: DBEN1 (Bitfield-Mask: 0x01)                  */
+#define PF_DBCR_DBEN0_Pos                 (0UL)                     /*!< PF DBCR: DBEN0 (Bit 0)                                */
+#define PF_DBCR_DBEN0_Msk                 (0x1UL)                   /*!< PF DBCR: DBEN0 (Bitfield-Mask: 0x01)                  */
+/* ========================================================  PF_MOD  ========================================================= */
+#define PF_PF_MOD_MODE11_Pos              (22UL)                    /*!< PF PF_MOD: MODE11 (Bit 22)                            */
+#define PF_PF_MOD_MODE11_Msk              (0xc00000UL)              /*!< PF PF_MOD: MODE11 (Bitfield-Mask: 0x03)               */
+#define PF_PF_MOD_MODE10_Pos              (20UL)                    /*!< PF PF_MOD: MODE10 (Bit 20)                            */
+#define PF_PF_MOD_MODE10_Msk              (0x300000UL)              /*!< PF PF_MOD: MODE10 (Bitfield-Mask: 0x03)               */
+#define PF_PF_MOD_MODE9_Pos               (18UL)                    /*!< PF PF_MOD: MODE9 (Bit 18)                             */
+#define PF_PF_MOD_MODE9_Msk               (0xc0000UL)               /*!< PF PF_MOD: MODE9 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE8_Pos               (16UL)                    /*!< PF PF_MOD: MODE8 (Bit 16)                             */
+#define PF_PF_MOD_MODE8_Msk               (0x30000UL)               /*!< PF PF_MOD: MODE8 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE7_Pos               (14UL)                    /*!< PF PF_MOD: MODE7 (Bit 14)                             */
+#define PF_PF_MOD_MODE7_Msk               (0xc000UL)                /*!< PF PF_MOD: MODE7 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE6_Pos               (12UL)                    /*!< PF PF_MOD: MODE6 (Bit 12)                             */
+#define PF_PF_MOD_MODE6_Msk               (0x3000UL)                /*!< PF PF_MOD: MODE6 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE5_Pos               (10UL)                    /*!< PF PF_MOD: MODE5 (Bit 10)                             */
+#define PF_PF_MOD_MODE5_Msk               (0xc00UL)                 /*!< PF PF_MOD: MODE5 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE4_Pos               (8UL)                     /*!< PF PF_MOD: MODE4 (Bit 8)                              */
+#define PF_PF_MOD_MODE4_Msk               (0x300UL)                 /*!< PF PF_MOD: MODE4 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE3_Pos               (6UL)                     /*!< PF PF_MOD: MODE3 (Bit 6)                              */
+#define PF_PF_MOD_MODE3_Msk               (0xc0UL)                  /*!< PF PF_MOD: MODE3 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE2_Pos               (4UL)                     /*!< PF PF_MOD: MODE2 (Bit 4)                              */
+#define PF_PF_MOD_MODE2_Msk               (0x30UL)                  /*!< PF PF_MOD: MODE2 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE1_Pos               (2UL)                     /*!< PF PF_MOD: MODE1 (Bit 2)                              */
+#define PF_PF_MOD_MODE1_Msk               (0xcUL)                   /*!< PF PF_MOD: MODE1 (Bitfield-Mask: 0x03)                */
+#define PF_PF_MOD_MODE0_Pos               (0UL)                     /*!< PF PF_MOD: MODE0 (Bit 0)                              */
+#define PF_PF_MOD_MODE0_Msk               (0x3UL)                   /*!< PF PF_MOD: MODE0 (Bitfield-Mask: 0x03)                */
+/* ========================================================  PF_TYP  ========================================================= */
+#define PF_PF_TYP_TYP11_Pos               (11UL)                    /*!< PF PF_TYP: TYP11 (Bit 11)                             */
+#define PF_PF_TYP_TYP11_Msk               (0x800UL)                 /*!< PF PF_TYP: TYP11 (Bitfield-Mask: 0x01)                */
+#define PF_PF_TYP_TYP10_Pos               (10UL)                    /*!< PF PF_TYP: TYP10 (Bit 10)                             */
+#define PF_PF_TYP_TYP10_Msk               (0x400UL)                 /*!< PF PF_TYP: TYP10 (Bitfield-Mask: 0x01)                */
+#define PF_PF_TYP_TYP9_Pos                (9UL)                     /*!< PF PF_TYP: TYP9 (Bit 9)                               */
+#define PF_PF_TYP_TYP9_Msk                (0x200UL)                 /*!< PF PF_TYP: TYP9 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP8_Pos                (8UL)                     /*!< PF PF_TYP: TYP8 (Bit 8)                               */
+#define PF_PF_TYP_TYP8_Msk                (0x100UL)                 /*!< PF PF_TYP: TYP8 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP7_Pos                (7UL)                     /*!< PF PF_TYP: TYP7 (Bit 7)                               */
+#define PF_PF_TYP_TYP7_Msk                (0x80UL)                  /*!< PF PF_TYP: TYP7 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP6_Pos                (6UL)                     /*!< PF PF_TYP: TYP6 (Bit 6)                               */
+#define PF_PF_TYP_TYP6_Msk                (0x40UL)                  /*!< PF PF_TYP: TYP6 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP5_Pos                (5UL)                     /*!< PF PF_TYP: TYP5 (Bit 5)                               */
+#define PF_PF_TYP_TYP5_Msk                (0x20UL)                  /*!< PF PF_TYP: TYP5 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP4_Pos                (4UL)                     /*!< PF PF_TYP: TYP4 (Bit 4)                               */
+#define PF_PF_TYP_TYP4_Msk                (0x10UL)                  /*!< PF PF_TYP: TYP4 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP3_Pos                (3UL)                     /*!< PF PF_TYP: TYP3 (Bit 3)                               */
+#define PF_PF_TYP_TYP3_Msk                (0x8UL)                   /*!< PF PF_TYP: TYP3 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP2_Pos                (2UL)                     /*!< PF PF_TYP: TYP2 (Bit 2)                               */
+#define PF_PF_TYP_TYP2_Msk                (0x4UL)                   /*!< PF PF_TYP: TYP2 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP1_Pos                (1UL)                     /*!< PF PF_TYP: TYP1 (Bit 1)                               */
+#define PF_PF_TYP_TYP1_Msk                (0x2UL)                   /*!< PF PF_TYP: TYP1 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_TYP_TYP0_Pos                (0UL)                     /*!< PF PF_TYP: TYP0 (Bit 0)                               */
+#define PF_PF_TYP_TYP0_Msk                (0x1UL)                   /*!< PF PF_TYP: TYP0 (Bitfield-Mask: 0x01)                 */
+/* =======================================================  PF_AFSR1  ======================================================== */
+#define PF_PF_AFSR1_AFSR7_Pos             (28UL)                    /*!< PF PF_AFSR1: AFSR7 (Bit 28)                           */
+#define PF_PF_AFSR1_AFSR7_Msk             (0xf0000000UL)            /*!< PF PF_AFSR1: AFSR7 (Bitfield-Mask: 0x0f)              */
+#define PF_PF_AFSR1_AFSR6_Pos             (24UL)                    /*!< PF PF_AFSR1: AFSR6 (Bit 24)                           */
+#define PF_PF_AFSR1_AFSR6_Msk             (0xf000000UL)             /*!< PF PF_AFSR1: AFSR6 (Bitfield-Mask: 0x0f)              */
+#define PF_PF_AFSR1_AFSR5_Pos             (20UL)                    /*!< PF PF_AFSR1: AFSR5 (Bit 20)                           */
+#define PF_PF_AFSR1_AFSR5_Msk             (0xf00000UL)              /*!< PF PF_AFSR1: AFSR5 (Bitfield-Mask: 0x0f)              */
+#define PF_PF_AFSR1_AFSR4_Pos             (16UL)                    /*!< PF PF_AFSR1: AFSR4 (Bit 16)                           */
+#define PF_PF_AFSR1_AFSR4_Msk             (0xf0000UL)               /*!< PF PF_AFSR1: AFSR4 (Bitfield-Mask: 0x0f)              */
+#define PF_PF_AFSR1_AFSR3_Pos             (12UL)                    /*!< PF PF_AFSR1: AFSR3 (Bit 12)                           */
+#define PF_PF_AFSR1_AFSR3_Msk             (0xf000UL)                /*!< PF PF_AFSR1: AFSR3 (Bitfield-Mask: 0x0f)              */
+#define PF_PF_AFSR1_AFSR2_Pos             (8UL)                     /*!< PF PF_AFSR1: AFSR2 (Bit 8)                            */
+#define PF_PF_AFSR1_AFSR2_Msk             (0xf00UL)                 /*!< PF PF_AFSR1: AFSR2 (Bitfield-Mask: 0x0f)              */
+#define PF_PF_AFSR1_AFSR1_Pos             (4UL)                     /*!< PF PF_AFSR1: AFSR1 (Bit 4)                            */
+#define PF_PF_AFSR1_AFSR1_Msk             (0xf0UL)                  /*!< PF PF_AFSR1: AFSR1 (Bitfield-Mask: 0x0f)              */
+#define PF_PF_AFSR1_AFSR0_Pos             (0UL)                     /*!< PF PF_AFSR1: AFSR0 (Bit 0)                            */
+#define PF_PF_AFSR1_AFSR0_Msk             (0xfUL)                   /*!< PF PF_AFSR1: AFSR0 (Bitfield-Mask: 0x0f)              */
+/* =======================================================  PF_AFSR2  ======================================================== */
+#define PF_PF_AFSR2_AFSR11_Pos            (12UL)                    /*!< PF PF_AFSR2: AFSR11 (Bit 12)                          */
+#define PF_PF_AFSR2_AFSR11_Msk            (0xf000UL)                /*!< PF PF_AFSR2: AFSR11 (Bitfield-Mask: 0x0f)             */
+#define PF_PF_AFSR2_AFSR10_Pos            (8UL)                     /*!< PF PF_AFSR2: AFSR10 (Bit 8)                           */
+#define PF_PF_AFSR2_AFSR10_Msk            (0xf00UL)                 /*!< PF PF_AFSR2: AFSR10 (Bitfield-Mask: 0x0f)             */
+#define PF_PF_AFSR2_AFSR9_Pos             (4UL)                     /*!< PF PF_AFSR2: AFSR9 (Bit 4)                            */
+#define PF_PF_AFSR2_AFSR9_Msk             (0xf0UL)                  /*!< PF PF_AFSR2: AFSR9 (Bitfield-Mask: 0x0f)              */
+#define PF_PF_AFSR2_AFSR8_Pos             (0UL)                     /*!< PF PF_AFSR2: AFSR8 (Bit 0)                            */
+#define PF_PF_AFSR2_AFSR8_Msk             (0xfUL)                   /*!< PF PF_AFSR2: AFSR8 (Bitfield-Mask: 0x0f)              */
+/* ========================================================  PF_PUPD  ======================================================== */
+#define PF_PF_PUPD_PUPD11_Pos             (22UL)                    /*!< PF PF_PUPD: PUPD11 (Bit 22)                           */
+#define PF_PF_PUPD_PUPD11_Msk             (0xc00000UL)              /*!< PF PF_PUPD: PUPD11 (Bitfield-Mask: 0x03)              */
+#define PF_PF_PUPD_PUPD10_Pos             (20UL)                    /*!< PF PF_PUPD: PUPD10 (Bit 20)                           */
+#define PF_PF_PUPD_PUPD10_Msk             (0x300000UL)              /*!< PF PF_PUPD: PUPD10 (Bitfield-Mask: 0x03)              */
+#define PF_PF_PUPD_PUPD9_Pos              (18UL)                    /*!< PF PF_PUPD: PUPD9 (Bit 18)                            */
+#define PF_PF_PUPD_PUPD9_Msk              (0xc0000UL)               /*!< PF PF_PUPD: PUPD9 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD8_Pos              (16UL)                    /*!< PF PF_PUPD: PUPD8 (Bit 16)                            */
+#define PF_PF_PUPD_PUPD8_Msk              (0x30000UL)               /*!< PF PF_PUPD: PUPD8 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD7_Pos              (14UL)                    /*!< PF PF_PUPD: PUPD7 (Bit 14)                            */
+#define PF_PF_PUPD_PUPD7_Msk              (0xc000UL)                /*!< PF PF_PUPD: PUPD7 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD6_Pos              (12UL)                    /*!< PF PF_PUPD: PUPD6 (Bit 12)                            */
+#define PF_PF_PUPD_PUPD6_Msk              (0x3000UL)                /*!< PF PF_PUPD: PUPD6 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD5_Pos              (10UL)                    /*!< PF PF_PUPD: PUPD5 (Bit 10)                            */
+#define PF_PF_PUPD_PUPD5_Msk              (0xc00UL)                 /*!< PF PF_PUPD: PUPD5 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD4_Pos              (8UL)                     /*!< PF PF_PUPD: PUPD4 (Bit 8)                             */
+#define PF_PF_PUPD_PUPD4_Msk              (0x300UL)                 /*!< PF PF_PUPD: PUPD4 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD3_Pos              (6UL)                     /*!< PF PF_PUPD: PUPD3 (Bit 6)                             */
+#define PF_PF_PUPD_PUPD3_Msk              (0xc0UL)                  /*!< PF PF_PUPD: PUPD3 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD2_Pos              (4UL)                     /*!< PF PF_PUPD: PUPD2 (Bit 4)                             */
+#define PF_PF_PUPD_PUPD2_Msk              (0x30UL)                  /*!< PF PF_PUPD: PUPD2 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD1_Pos              (2UL)                     /*!< PF PF_PUPD: PUPD1 (Bit 2)                             */
+#define PF_PF_PUPD_PUPD1_Msk              (0xcUL)                   /*!< PF PF_PUPD: PUPD1 (Bitfield-Mask: 0x03)               */
+#define PF_PF_PUPD_PUPD0_Pos              (0UL)                     /*!< PF PF_PUPD: PUPD0 (Bit 0)                             */
+#define PF_PF_PUPD_PUPD0_Msk              (0x3UL)                   /*!< PF PF_PUPD: PUPD0 (Bitfield-Mask: 0x03)               */
+/* ========================================================  PF_INDR  ======================================================== */
+#define PF_PF_INDR_INDR11_Pos             (11UL)                    /*!< PF PF_INDR: INDR11 (Bit 11)                           */
+#define PF_PF_INDR_INDR11_Msk             (0x800UL)                 /*!< PF PF_INDR: INDR11 (Bitfield-Mask: 0x01)              */
+#define PF_PF_INDR_INDR10_Pos             (10UL)                    /*!< PF PF_INDR: INDR10 (Bit 10)                           */
+#define PF_PF_INDR_INDR10_Msk             (0x400UL)                 /*!< PF PF_INDR: INDR10 (Bitfield-Mask: 0x01)              */
+#define PF_PF_INDR_INDR9_Pos              (9UL)                     /*!< PF PF_INDR: INDR9 (Bit 9)                             */
+#define PF_PF_INDR_INDR9_Msk              (0x200UL)                 /*!< PF PF_INDR: INDR9 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR8_Pos              (8UL)                     /*!< PF PF_INDR: INDR8 (Bit 8)                             */
+#define PF_PF_INDR_INDR8_Msk              (0x100UL)                 /*!< PF PF_INDR: INDR8 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR7_Pos              (7UL)                     /*!< PF PF_INDR: INDR7 (Bit 7)                             */
+#define PF_PF_INDR_INDR7_Msk              (0x80UL)                  /*!< PF PF_INDR: INDR7 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR6_Pos              (6UL)                     /*!< PF PF_INDR: INDR6 (Bit 6)                             */
+#define PF_PF_INDR_INDR6_Msk              (0x40UL)                  /*!< PF PF_INDR: INDR6 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR5_Pos              (5UL)                     /*!< PF PF_INDR: INDR5 (Bit 5)                             */
+#define PF_PF_INDR_INDR5_Msk              (0x20UL)                  /*!< PF PF_INDR: INDR5 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR4_Pos              (4UL)                     /*!< PF PF_INDR: INDR4 (Bit 4)                             */
+#define PF_PF_INDR_INDR4_Msk              (0x10UL)                  /*!< PF PF_INDR: INDR4 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR3_Pos              (3UL)                     /*!< PF PF_INDR: INDR3 (Bit 3)                             */
+#define PF_PF_INDR_INDR3_Msk              (0x8UL)                   /*!< PF PF_INDR: INDR3 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR2_Pos              (2UL)                     /*!< PF PF_INDR: INDR2 (Bit 2)                             */
+#define PF_PF_INDR_INDR2_Msk              (0x4UL)                   /*!< PF PF_INDR: INDR2 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR1_Pos              (1UL)                     /*!< PF PF_INDR: INDR1 (Bit 1)                             */
+#define PF_PF_INDR_INDR1_Msk              (0x2UL)                   /*!< PF PF_INDR: INDR1 (Bitfield-Mask: 0x01)               */
+#define PF_PF_INDR_INDR0_Pos              (0UL)                     /*!< PF PF_INDR: INDR0 (Bit 0)                             */
+#define PF_PF_INDR_INDR0_Msk              (0x1UL)                   /*!< PF PF_INDR: INDR0 (Bitfield-Mask: 0x01)               */
+/* =======================================================  PF_OUTDR  ======================================================== */
+#define PF_PF_OUTDR_OUTDR11_Pos           (11UL)                    /*!< PF PF_OUTDR: OUTDR11 (Bit 11)                         */
+#define PF_PF_OUTDR_OUTDR11_Msk           (0x800UL)                 /*!< PF PF_OUTDR: OUTDR11 (Bitfield-Mask: 0x01)            */
+#define PF_PF_OUTDR_OUTDR10_Pos           (10UL)                    /*!< PF PF_OUTDR: OUTDR10 (Bit 10)                         */
+#define PF_PF_OUTDR_OUTDR10_Msk           (0x400UL)                 /*!< PF PF_OUTDR: OUTDR10 (Bitfield-Mask: 0x01)            */
+#define PF_PF_OUTDR_OUTDR9_Pos            (9UL)                     /*!< PF PF_OUTDR: OUTDR9 (Bit 9)                           */
+#define PF_PF_OUTDR_OUTDR9_Msk            (0x200UL)                 /*!< PF PF_OUTDR: OUTDR9 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR8_Pos            (8UL)                     /*!< PF PF_OUTDR: OUTDR8 (Bit 8)                           */
+#define PF_PF_OUTDR_OUTDR8_Msk            (0x100UL)                 /*!< PF PF_OUTDR: OUTDR8 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR7_Pos            (7UL)                     /*!< PF PF_OUTDR: OUTDR7 (Bit 7)                           */
+#define PF_PF_OUTDR_OUTDR7_Msk            (0x80UL)                  /*!< PF PF_OUTDR: OUTDR7 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR6_Pos            (6UL)                     /*!< PF PF_OUTDR: OUTDR6 (Bit 6)                           */
+#define PF_PF_OUTDR_OUTDR6_Msk            (0x40UL)                  /*!< PF PF_OUTDR: OUTDR6 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR5_Pos            (5UL)                     /*!< PF PF_OUTDR: OUTDR5 (Bit 5)                           */
+#define PF_PF_OUTDR_OUTDR5_Msk            (0x20UL)                  /*!< PF PF_OUTDR: OUTDR5 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR4_Pos            (4UL)                     /*!< PF PF_OUTDR: OUTDR4 (Bit 4)                           */
+#define PF_PF_OUTDR_OUTDR4_Msk            (0x10UL)                  /*!< PF PF_OUTDR: OUTDR4 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR3_Pos            (3UL)                     /*!< PF PF_OUTDR: OUTDR3 (Bit 3)                           */
+#define PF_PF_OUTDR_OUTDR3_Msk            (0x8UL)                   /*!< PF PF_OUTDR: OUTDR3 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR2_Pos            (2UL)                     /*!< PF PF_OUTDR: OUTDR2 (Bit 2)                           */
+#define PF_PF_OUTDR_OUTDR2_Msk            (0x4UL)                   /*!< PF PF_OUTDR: OUTDR2 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR1_Pos            (1UL)                     /*!< PF PF_OUTDR: OUTDR1 (Bit 1)                           */
+#define PF_PF_OUTDR_OUTDR1_Msk            (0x2UL)                   /*!< PF PF_OUTDR: OUTDR1 (Bitfield-Mask: 0x01)             */
+#define PF_PF_OUTDR_OUTDR0_Pos            (0UL)                     /*!< PF PF_OUTDR: OUTDR0 (Bit 0)                           */
+#define PF_PF_OUTDR_OUTDR0_Msk            (0x1UL)                   /*!< PF PF_OUTDR: OUTDR0 (Bitfield-Mask: 0x01)             */
+/* ========================================================  PF_BSR  ========================================================= */
+#define PF_PF_BSR_BSR11_Pos               (11UL)                    /*!< PF PF_BSR: BSR11 (Bit 11)                             */
+#define PF_PF_BSR_BSR11_Msk               (0x800UL)                 /*!< PF PF_BSR: BSR11 (Bitfield-Mask: 0x01)                */
+#define PF_PF_BSR_BSR10_Pos               (10UL)                    /*!< PF PF_BSR: BSR10 (Bit 10)                             */
+#define PF_PF_BSR_BSR10_Msk               (0x400UL)                 /*!< PF PF_BSR: BSR10 (Bitfield-Mask: 0x01)                */
+#define PF_PF_BSR_BSR9_Pos                (9UL)                     /*!< PF PF_BSR: BSR9 (Bit 9)                               */
+#define PF_PF_BSR_BSR9_Msk                (0x200UL)                 /*!< PF PF_BSR: BSR9 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR8_Pos                (8UL)                     /*!< PF PF_BSR: BSR8 (Bit 8)                               */
+#define PF_PF_BSR_BSR8_Msk                (0x100UL)                 /*!< PF PF_BSR: BSR8 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR7_Pos                (7UL)                     /*!< PF PF_BSR: BSR7 (Bit 7)                               */
+#define PF_PF_BSR_BSR7_Msk                (0x80UL)                  /*!< PF PF_BSR: BSR7 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR6_Pos                (6UL)                     /*!< PF PF_BSR: BSR6 (Bit 6)                               */
+#define PF_PF_BSR_BSR6_Msk                (0x40UL)                  /*!< PF PF_BSR: BSR6 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR5_Pos                (5UL)                     /*!< PF PF_BSR: BSR5 (Bit 5)                               */
+#define PF_PF_BSR_BSR5_Msk                (0x20UL)                  /*!< PF PF_BSR: BSR5 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR4_Pos                (4UL)                     /*!< PF PF_BSR: BSR4 (Bit 4)                               */
+#define PF_PF_BSR_BSR4_Msk                (0x10UL)                  /*!< PF PF_BSR: BSR4 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR3_Pos                (3UL)                     /*!< PF PF_BSR: BSR3 (Bit 3)                               */
+#define PF_PF_BSR_BSR3_Msk                (0x8UL)                   /*!< PF PF_BSR: BSR3 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR2_Pos                (2UL)                     /*!< PF PF_BSR: BSR2 (Bit 2)                               */
+#define PF_PF_BSR_BSR2_Msk                (0x4UL)                   /*!< PF PF_BSR: BSR2 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR1_Pos                (1UL)                     /*!< PF PF_BSR: BSR1 (Bit 1)                               */
+#define PF_PF_BSR_BSR1_Msk                (0x2UL)                   /*!< PF PF_BSR: BSR1 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BSR_BSR0_Pos                (0UL)                     /*!< PF PF_BSR: BSR0 (Bit 0)                               */
+#define PF_PF_BSR_BSR0_Msk                (0x1UL)                   /*!< PF PF_BSR: BSR0 (Bitfield-Mask: 0x01)                 */
+/* ========================================================  PF_BCR  ========================================================= */
+#define PF_PF_BCR_BCR11_Pos               (11UL)                    /*!< PF PF_BCR: BCR11 (Bit 11)                             */
+#define PF_PF_BCR_BCR11_Msk               (0x800UL)                 /*!< PF PF_BCR: BCR11 (Bitfield-Mask: 0x01)                */
+#define PF_PF_BCR_BCR10_Pos               (10UL)                    /*!< PF PF_BCR: BCR10 (Bit 10)                             */
+#define PF_PF_BCR_BCR10_Msk               (0x400UL)                 /*!< PF PF_BCR: BCR10 (Bitfield-Mask: 0x01)                */
+#define PF_PF_BCR_BCR9_Pos                (9UL)                     /*!< PF PF_BCR: BCR9 (Bit 9)                               */
+#define PF_PF_BCR_BCR9_Msk                (0x200UL)                 /*!< PF PF_BCR: BCR9 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR8_Pos                (8UL)                     /*!< PF PF_BCR: BCR8 (Bit 8)                               */
+#define PF_PF_BCR_BCR8_Msk                (0x100UL)                 /*!< PF PF_BCR: BCR8 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR7_Pos                (7UL)                     /*!< PF PF_BCR: BCR7 (Bit 7)                               */
+#define PF_PF_BCR_BCR7_Msk                (0x80UL)                  /*!< PF PF_BCR: BCR7 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR6_Pos                (6UL)                     /*!< PF PF_BCR: BCR6 (Bit 6)                               */
+#define PF_PF_BCR_BCR6_Msk                (0x40UL)                  /*!< PF PF_BCR: BCR6 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR5_Pos                (5UL)                     /*!< PF PF_BCR: BCR5 (Bit 5)                               */
+#define PF_PF_BCR_BCR5_Msk                (0x20UL)                  /*!< PF PF_BCR: BCR5 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR4_Pos                (4UL)                     /*!< PF PF_BCR: BCR4 (Bit 4)                               */
+#define PF_PF_BCR_BCR4_Msk                (0x10UL)                  /*!< PF PF_BCR: BCR4 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR3_Pos                (3UL)                     /*!< PF PF_BCR: BCR3 (Bit 3)                               */
+#define PF_PF_BCR_BCR3_Msk                (0x8UL)                   /*!< PF PF_BCR: BCR3 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR2_Pos                (2UL)                     /*!< PF PF_BCR: BCR2 (Bit 2)                               */
+#define PF_PF_BCR_BCR2_Msk                (0x4UL)                   /*!< PF PF_BCR: BCR2 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR1_Pos                (1UL)                     /*!< PF PF_BCR: BCR1 (Bit 1)                               */
+#define PF_PF_BCR_BCR1_Msk                (0x2UL)                   /*!< PF PF_BCR: BCR1 (Bitfield-Mask: 0x01)                 */
+#define PF_PF_BCR_BCR0_Pos                (0UL)                     /*!< PF PF_BCR: BCR0 (Bit 0)                               */
+#define PF_PF_BCR_BCR0_Msk                (0x1UL)                   /*!< PF PF_BCR: BCR0 (Bitfield-Mask: 0x01)                 */
+/* ======================================================  PF_OUTDMSK  ======================================================= */
+#define PF_PF_OUTDMSK_OUTDMSK11_Pos       (11UL)                    /*!< PF PF_OUTDMSK: OUTDMSK11 (Bit 11)                     */
+#define PF_PF_OUTDMSK_OUTDMSK11_Msk       (0x800UL)                 /*!< PF PF_OUTDMSK: OUTDMSK11 (Bitfield-Mask: 0x01)        */
+#define PF_PF_OUTDMSK_OUTDMSK10_Pos       (10UL)                    /*!< PF PF_OUTDMSK: OUTDMSK10 (Bit 10)                     */
+#define PF_PF_OUTDMSK_OUTDMSK10_Msk       (0x400UL)                 /*!< PF PF_OUTDMSK: OUTDMSK10 (Bitfield-Mask: 0x01)        */
+#define PF_PF_OUTDMSK_OUTDMSK9_Pos        (9UL)                     /*!< PF PF_OUTDMSK: OUTDMSK9 (Bit 9)                       */
+#define PF_PF_OUTDMSK_OUTDMSK9_Msk        (0x200UL)                 /*!< PF PF_OUTDMSK: OUTDMSK9 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK8_Pos        (8UL)                     /*!< PF PF_OUTDMSK: OUTDMSK8 (Bit 8)                       */
+#define PF_PF_OUTDMSK_OUTDMSK8_Msk        (0x100UL)                 /*!< PF PF_OUTDMSK: OUTDMSK8 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK7_Pos        (7UL)                     /*!< PF PF_OUTDMSK: OUTDMSK7 (Bit 7)                       */
+#define PF_PF_OUTDMSK_OUTDMSK7_Msk        (0x80UL)                  /*!< PF PF_OUTDMSK: OUTDMSK7 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK6_Pos        (6UL)                     /*!< PF PF_OUTDMSK: OUTDMSK6 (Bit 6)                       */
+#define PF_PF_OUTDMSK_OUTDMSK6_Msk        (0x40UL)                  /*!< PF PF_OUTDMSK: OUTDMSK6 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK5_Pos        (5UL)                     /*!< PF PF_OUTDMSK: OUTDMSK5 (Bit 5)                       */
+#define PF_PF_OUTDMSK_OUTDMSK5_Msk        (0x20UL)                  /*!< PF PF_OUTDMSK: OUTDMSK5 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK4_Pos        (4UL)                     /*!< PF PF_OUTDMSK: OUTDMSK4 (Bit 4)                       */
+#define PF_PF_OUTDMSK_OUTDMSK4_Msk        (0x10UL)                  /*!< PF PF_OUTDMSK: OUTDMSK4 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK3_Pos        (3UL)                     /*!< PF PF_OUTDMSK: OUTDMSK3 (Bit 3)                       */
+#define PF_PF_OUTDMSK_OUTDMSK3_Msk        (0x8UL)                   /*!< PF PF_OUTDMSK: OUTDMSK3 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK2_Pos        (2UL)                     /*!< PF PF_OUTDMSK: OUTDMSK2 (Bit 2)                       */
+#define PF_PF_OUTDMSK_OUTDMSK2_Msk        (0x4UL)                   /*!< PF PF_OUTDMSK: OUTDMSK2 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK1_Pos        (1UL)                     /*!< PF PF_OUTDMSK: OUTDMSK1 (Bit 1)                       */
+#define PF_PF_OUTDMSK_OUTDMSK1_Msk        (0x2UL)                   /*!< PF PF_OUTDMSK: OUTDMSK1 (Bitfield-Mask: 0x01)         */
+#define PF_PF_OUTDMSK_OUTDMSK0_Pos        (0UL)                     /*!< PF PF_OUTDMSK: OUTDMSK0 (Bit 0)                       */
+#define PF_PF_OUTDMSK_OUTDMSK0_Msk        (0x1UL)                   /*!< PF PF_OUTDMSK: OUTDMSK0 (Bitfield-Mask: 0x01)         */
+
+
+/* =========================================================================================================================== */
+/* ================                                            FMC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ADR  ========================================================== */
+#define FMC_ADR_ADDR_Pos                  (0UL)                     /*!< FMC ADR: ADDR (Bit 0)                                 */
+#define FMC_ADR_ADDR_Msk                  (0xffffffffUL)            /*!< FMC ADR: ADDR (Bitfield-Mask: 0xffffffff)             */
+/* =========================================================  IDR1  ========================================================== */
+#define FMC_IDR1_ID1_Pos                  (0UL)                     /*!< FMC IDR1: ID1 (Bit 0)                                 */
+#define FMC_IDR1_ID1_Msk                  (0xffffffffUL)            /*!< FMC IDR1: ID1 (Bitfield-Mask: 0xffffffff)             */
+/* =========================================================  IDR2  ========================================================== */
+#define FMC_IDR2_ID2_Pos                  (0UL)                     /*!< FMC IDR2: ID2 (Bit 0)                                 */
+#define FMC_IDR2_ID2_Msk                  (0xffffffffUL)            /*!< FMC IDR2: ID2 (Bitfield-Mask: 0xffffffff)             */
+/* ==========================================================  CR  =========================================================== */
+#define FMC_CR_WTIDKY_Pos                 (16UL)                    /*!< FMC CR: WTIDKY (Bit 16)                               */
+#define FMC_CR_WTIDKY_Msk                 (0xffff0000UL)            /*!< FMC CR: WTIDKY (Bitfield-Mask: 0xffff)                */
+#define FMC_CR_FMKEY_Pos                  (8UL)                     /*!< FMC CR: FMKEY (Bit 8)                                 */
+#define FMC_CR_FMKEY_Msk                  (0xff00UL)                /*!< FMC CR: FMKEY (Bitfield-Mask: 0xff)                   */
+#define FMC_CR_FMBUSY_Pos                 (7UL)                     /*!< FMC CR: FMBUSY (Bit 7)                                */
+#define FMC_CR_FMBUSY_Msk                 (0x80UL)                  /*!< FMC CR: FMBUSY (Bitfield-Mask: 0x01)                  */
+#define FMC_CR_FMOD_Pos                   (0UL)                     /*!< FMC CR: FMOD (Bit 0)                                  */
+#define FMC_CR_FMOD_Msk                   (0xfUL)                   /*!< FMC CR: FMOD (Bitfield-Mask: 0x0f)                    */
+/* ==========================================================  BCR  ========================================================== */
+#define FMC_BCR_WTIDKY_Pos                (16UL)                    /*!< FMC BCR: WTIDKY (Bit 16)                              */
+#define FMC_BCR_WTIDKY_Msk                (0xffff0000UL)            /*!< FMC BCR: WTIDKY (Bitfield-Mask: 0xffff)               */
+#define FMC_BCR_CNF3BEN_Pos               (8UL)                     /*!< FMC BCR: CNF3BEN (Bit 8)                              */
+#define FMC_BCR_CNF3BEN_Msk               (0xf00UL)                 /*!< FMC BCR: CNF3BEN (Bitfield-Mask: 0x0f)                */
+#define FMC_BCR_CNF2BEN_Pos               (4UL)                     /*!< FMC BCR: CNF2BEN (Bit 4)                              */
+#define FMC_BCR_CNF2BEN_Msk               (0xf0UL)                  /*!< FMC BCR: CNF2BEN (Bitfield-Mask: 0x0f)                */
+#define FMC_BCR_CNF1BEN_Pos               (0UL)                     /*!< FMC BCR: CNF1BEN (Bit 0)                              */
+#define FMC_BCR_CNF1BEN_Msk               (0xfUL)                   /*!< FMC BCR: CNF1BEN (Bitfield-Mask: 0x0f)                */
+/* ========================================================  ERFLAG  ========================================================= */
+#define FMC_ERFLAG_INSTFLAG_Pos           (1UL)                     /*!< FMC ERFLAG: INSTFLAG (Bit 1)                          */
+#define FMC_ERFLAG_INSTFLAG_Msk           (0x2UL)                   /*!< FMC ERFLAG: INSTFLAG (Bitfield-Mask: 0x01)            */
+#define FMC_ERFLAG_FMOPFLAG_Pos           (0UL)                     /*!< FMC ERFLAG: FMOPFLAG (Bit 0)                          */
+#define FMC_ERFLAG_FMOPFLAG_Msk           (0x1UL)                   /*!< FMC ERFLAG: FMOPFLAG (Bitfield-Mask: 0x01)            */
+/* ========================================================  PAGEBUF  ======================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                            WDT                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define WDT_CR_WTIDKY_Pos                 (16UL)                    /*!< WDT CR: WTIDKY (Bit 16)                               */
+#define WDT_CR_WTIDKY_Msk                 (0xffff0000UL)            /*!< WDT CR: WTIDKY (Bitfield-Mask: 0xffff)                */
+#define WDT_CR_RSTEN_Pos                  (10UL)                    /*!< WDT CR: RSTEN (Bit 10)                                */
+#define WDT_CR_RSTEN_Msk                  (0xfc00UL)                /*!< WDT CR: RSTEN (Bitfield-Mask: 0x3f)                   */
+#define WDT_CR_CNTEN_Pos                  (4UL)                     /*!< WDT CR: CNTEN (Bit 4)                                 */
+#define WDT_CR_CNTEN_Msk                  (0x3f0UL)                 /*!< WDT CR: CNTEN (Bitfield-Mask: 0x3f)                   */
+#define WDT_CR_WINMIEN_Pos                (3UL)                     /*!< WDT CR: WINMIEN (Bit 3)                               */
+#define WDT_CR_WINMIEN_Msk                (0x8UL)                   /*!< WDT CR: WINMIEN (Bitfield-Mask: 0x01)                 */
+#define WDT_CR_UNFIEN_Pos                 (2UL)                     /*!< WDT CR: UNFIEN (Bit 2)                                */
+#define WDT_CR_UNFIEN_Msk                 (0x4UL)                   /*!< WDT CR: UNFIEN (Bitfield-Mask: 0x01)                  */
+#define WDT_CR_CLKDIV_Pos                 (0UL)                     /*!< WDT CR: CLKDIV (Bit 0)                                */
+#define WDT_CR_CLKDIV_Msk                 (0x3UL)                   /*!< WDT CR: CLKDIV (Bitfield-Mask: 0x03)                  */
+/* ==========================================================  SR  =========================================================== */
+#define WDT_SR_DBGCNTEN_Pos               (7UL)                     /*!< WDT SR: DBGCNTEN (Bit 7)                              */
+#define WDT_SR_DBGCNTEN_Msk               (0x80UL)                  /*!< WDT SR: DBGCNTEN (Bitfield-Mask: 0x01)                */
+#define WDT_SR_WINMIFLAG_Pos              (1UL)                     /*!< WDT SR: WINMIFLAG (Bit 1)                             */
+#define WDT_SR_WINMIFLAG_Msk              (0x2UL)                   /*!< WDT SR: WINMIFLAG (Bitfield-Mask: 0x01)               */
+#define WDT_SR_UNFIFLAG_Pos               (0UL)                     /*!< WDT SR: UNFIFLAG (Bit 0)                              */
+#define WDT_SR_UNFIFLAG_Msk               (0x1UL)                   /*!< WDT SR: UNFIFLAG (Bitfield-Mask: 0x01)                */
+/* ==========================================================  DR  =========================================================== */
+#define WDT_DR_DATA_Pos                   (0UL)                     /*!< WDT DR: DATA (Bit 0)                                  */
+#define WDT_DR_DATA_Msk                   (0xffffffUL)              /*!< WDT DR: DATA (Bitfield-Mask: 0xffffff)                */
+/* ==========================================================  CNT  ========================================================== */
+#define WDT_CNT_CNT_Pos                   (0UL)                     /*!< WDT CNT: CNT (Bit 0)                                  */
+#define WDT_CNT_CNT_Msk                   (0xffffffUL)              /*!< WDT CNT: CNT (Bitfield-Mask: 0xffffff)                */
+/* =========================================================  WINDR  ========================================================= */
+#define WDT_WINDR_WDATA_Pos               (0UL)                     /*!< WDT WINDR: WDATA (Bit 0)                              */
+#define WDT_WINDR_WDATA_Msk               (0xffffffUL)              /*!< WDT WINDR: WDATA (Bitfield-Mask: 0xffffff)            */
+/* =========================================================  CNTR  ========================================================== */
+#define WDT_CNTR_CNTR_Pos                 (0UL)                     /*!< WDT CNTR: CNTR (Bit 0)                                */
+#define WDT_CNTR_CNTR_Msk                 (0xffUL)                  /*!< WDT CNTR: CNTR (Bitfield-Mask: 0xff)                  */
+
+
+/* =========================================================================================================================== */
+/* ================                                            WT                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define WT_CR_WTEN_Pos                    (7UL)                     /*!< WT CR: WTEN (Bit 7)                                   */
+#define WT_CR_WTEN_Msk                    (0x80UL)                  /*!< WT CR: WTEN (Bitfield-Mask: 0x01)                     */
+#define WT_CR_WTINTV_Pos                  (4UL)                     /*!< WT CR: WTINTV (Bit 4)                                 */
+#define WT_CR_WTINTV_Msk                  (0x30UL)                  /*!< WT CR: WTINTV (Bitfield-Mask: 0x03)                   */
+#define WT_CR_WTIEN_Pos                   (3UL)                     /*!< WT CR: WTIEN (Bit 3)                                  */
+#define WT_CR_WTIEN_Msk                   (0x8UL)                   /*!< WT CR: WTIEN (Bitfield-Mask: 0x01)                    */
+#define WT_CR_WTIFLAG_Pos                 (1UL)                     /*!< WT CR: WTIFLAG (Bit 1)                                */
+#define WT_CR_WTIFLAG_Msk                 (0x2UL)                   /*!< WT CR: WTIFLAG (Bitfield-Mask: 0x01)                  */
+#define WT_CR_WTCLR_Pos                   (0UL)                     /*!< WT CR: WTCLR (Bit 0)                                  */
+#define WT_CR_WTCLR_Msk                   (0x1UL)                   /*!< WT CR: WTCLR (Bitfield-Mask: 0x01)                    */
+/* ==========================================================  DR  =========================================================== */
+#define WT_DR_WTDATA_Pos                  (0UL)                     /*!< WT DR: WTDATA (Bit 0)                                 */
+#define WT_DR_WTDATA_Msk                  (0xfffUL)                 /*!< WT DR: WTDATA (Bitfield-Mask: 0xfff)                  */
+/* ==========================================================  CNT  ========================================================== */
+#define WT_CNT_CNT_Pos                    (0UL)                     /*!< WT CNT: CNT (Bit 0)                                   */
+#define WT_CNT_CNT_Msk                    (0xfffUL)                 /*!< WT CNT: CNT (Bitfield-Mask: 0xfff)                    */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER1n                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER1n_CR_T1nEN_Pos              (15UL)                    /*!< TIMER1n CR: T1nEN (Bit 15)                            */
+#define TIMER1n_CR_T1nEN_Msk              (0x8000UL)                /*!< TIMER1n CR: T1nEN (Bitfield-Mask: 0x01)               */
+#define TIMER1n_CR_T1nCLK_Pos             (14UL)                    /*!< TIMER1n CR: T1nCLK (Bit 14)                           */
+#define TIMER1n_CR_T1nCLK_Msk             (0x4000UL)                /*!< TIMER1n CR: T1nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER1n_CR_T1nMS_Pos              (12UL)                    /*!< TIMER1n CR: T1nMS (Bit 12)                            */
+#define TIMER1n_CR_T1nMS_Msk              (0x3000UL)                /*!< TIMER1n CR: T1nMS (Bitfield-Mask: 0x03)               */
+#define TIMER1n_CR_T1nECE_Pos             (11UL)                    /*!< TIMER1n CR: T1nECE (Bit 11)                           */
+#define TIMER1n_CR_T1nECE_Msk             (0x800UL)                 /*!< TIMER1n CR: T1nECE (Bitfield-Mask: 0x01)              */
+#define TIMER1n_CR_T1nOPOL_Pos            (8UL)                     /*!< TIMER1n CR: T1nOPOL (Bit 8)                           */
+#define TIMER1n_CR_T1nOPOL_Msk            (0x100UL)                 /*!< TIMER1n CR: T1nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER1n_CR_T1nCPOL_Pos            (6UL)                     /*!< TIMER1n CR: T1nCPOL (Bit 6)                           */
+#define TIMER1n_CR_T1nCPOL_Msk            (0xc0UL)                  /*!< TIMER1n CR: T1nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER1n_CR_T1nMIEN_Pos            (5UL)                     /*!< TIMER1n CR: T1nMIEN (Bit 5)                           */
+#define TIMER1n_CR_T1nMIEN_Msk            (0x20UL)                  /*!< TIMER1n CR: T1nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER1n_CR_T1nCIEN_Pos            (4UL)                     /*!< TIMER1n CR: T1nCIEN (Bit 4)                           */
+#define TIMER1n_CR_T1nCIEN_Msk            (0x10UL)                  /*!< TIMER1n CR: T1nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER1n_CR_T1nMIFLAG_Pos          (3UL)                     /*!< TIMER1n CR: T1nMIFLAG (Bit 3)                         */
+#define TIMER1n_CR_T1nMIFLAG_Msk          (0x8UL)                   /*!< TIMER1n CR: T1nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER1n_CR_T1nCIFLAG_Pos          (2UL)                     /*!< TIMER1n CR: T1nCIFLAG (Bit 2)                         */
+#define TIMER1n_CR_T1nCIFLAG_Msk          (0x4UL)                   /*!< TIMER1n CR: T1nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER1n_CR_T1nPAU_Pos             (1UL)                     /*!< TIMER1n CR: T1nPAU (Bit 1)                            */
+#define TIMER1n_CR_T1nPAU_Msk             (0x2UL)                   /*!< TIMER1n CR: T1nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER1n_CR_T1nCLR_Pos             (0UL)                     /*!< TIMER1n CR: T1nCLR (Bit 0)                            */
+#define TIMER1n_CR_T1nCLR_Msk             (0x1UL)                   /*!< TIMER1n CR: T1nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER1n_ADR_ADATA_Pos             (0UL)                     /*!< TIMER1n ADR: ADATA (Bit 0)                            */
+#define TIMER1n_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER1n ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER1n_BDR_BDATA_Pos             (0UL)                     /*!< TIMER1n BDR: BDATA (Bit 0)                            */
+#define TIMER1n_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER1n BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER1n_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER1n CAPDR: CAPD (Bit 0)                           */
+#define TIMER1n_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER1n CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER1n_PREDR_PRED_Pos            (0UL)                     /*!< TIMER1n PREDR: PRED (Bit 0)                           */
+#define TIMER1n_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER1n PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER1n_CNT_CNT_Pos               (0UL)                     /*!< TIMER1n CNT: CNT (Bit 0)                              */
+#define TIMER1n_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER1n CNT: CNT (Bitfield-Mask: 0xffff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER10                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER10_CR_T1nEN_Pos              (15UL)                    /*!< TIMER10 CR: T1nEN (Bit 15)                            */
+#define TIMER10_CR_T1nEN_Msk              (0x8000UL)                /*!< TIMER10 CR: T1nEN (Bitfield-Mask: 0x01)               */
+#define TIMER10_CR_T1nCLK_Pos             (14UL)                    /*!< TIMER10 CR: T1nCLK (Bit 14)                           */
+#define TIMER10_CR_T1nCLK_Msk             (0x4000UL)                /*!< TIMER10 CR: T1nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER10_CR_T1nMS_Pos              (12UL)                    /*!< TIMER10 CR: T1nMS (Bit 12)                            */
+#define TIMER10_CR_T1nMS_Msk              (0x3000UL)                /*!< TIMER10 CR: T1nMS (Bitfield-Mask: 0x03)               */
+#define TIMER10_CR_T1nECE_Pos             (11UL)                    /*!< TIMER10 CR: T1nECE (Bit 11)                           */
+#define TIMER10_CR_T1nECE_Msk             (0x800UL)                 /*!< TIMER10 CR: T1nECE (Bitfield-Mask: 0x01)              */
+#define TIMER10_CR_T1nOPOL_Pos            (8UL)                     /*!< TIMER10 CR: T1nOPOL (Bit 8)                           */
+#define TIMER10_CR_T1nOPOL_Msk            (0x100UL)                 /*!< TIMER10 CR: T1nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER10_CR_T1nCPOL_Pos            (6UL)                     /*!< TIMER10 CR: T1nCPOL (Bit 6)                           */
+#define TIMER10_CR_T1nCPOL_Msk            (0xc0UL)                  /*!< TIMER10 CR: T1nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER10_CR_T1nMIEN_Pos            (5UL)                     /*!< TIMER10 CR: T1nMIEN (Bit 5)                           */
+#define TIMER10_CR_T1nMIEN_Msk            (0x20UL)                  /*!< TIMER10 CR: T1nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER10_CR_T1nCIEN_Pos            (4UL)                     /*!< TIMER10 CR: T1nCIEN (Bit 4)                           */
+#define TIMER10_CR_T1nCIEN_Msk            (0x10UL)                  /*!< TIMER10 CR: T1nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER10_CR_T1nMIFLAG_Pos          (3UL)                     /*!< TIMER10 CR: T1nMIFLAG (Bit 3)                         */
+#define TIMER10_CR_T1nMIFLAG_Msk          (0x8UL)                   /*!< TIMER10 CR: T1nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER10_CR_T1nCIFLAG_Pos          (2UL)                     /*!< TIMER10 CR: T1nCIFLAG (Bit 2)                         */
+#define TIMER10_CR_T1nCIFLAG_Msk          (0x4UL)                   /*!< TIMER10 CR: T1nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER10_CR_T1nPAU_Pos             (1UL)                     /*!< TIMER10 CR: T1nPAU (Bit 1)                            */
+#define TIMER10_CR_T1nPAU_Msk             (0x2UL)                   /*!< TIMER10 CR: T1nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER10_CR_T1nCLR_Pos             (0UL)                     /*!< TIMER10 CR: T1nCLR (Bit 0)                            */
+#define TIMER10_CR_T1nCLR_Msk             (0x1UL)                   /*!< TIMER10 CR: T1nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER10_ADR_ADATA_Pos             (0UL)                     /*!< TIMER10 ADR: ADATA (Bit 0)                            */
+#define TIMER10_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER10 ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER10_BDR_BDATA_Pos             (0UL)                     /*!< TIMER10 BDR: BDATA (Bit 0)                            */
+#define TIMER10_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER10 BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER10_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER10 CAPDR: CAPD (Bit 0)                           */
+#define TIMER10_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER10 CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER10_PREDR_PRED_Pos            (0UL)                     /*!< TIMER10 PREDR: PRED (Bit 0)                           */
+#define TIMER10_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER10 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER10_CNT_CNT_Pos               (0UL)                     /*!< TIMER10 CNT: CNT (Bit 0)                              */
+#define TIMER10_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER10 CNT: CNT (Bitfield-Mask: 0xffff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER11                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER11_CR_T1nEN_Pos              (15UL)                    /*!< TIMER11 CR: T1nEN (Bit 15)                            */
+#define TIMER11_CR_T1nEN_Msk              (0x8000UL)                /*!< TIMER11 CR: T1nEN (Bitfield-Mask: 0x01)               */
+#define TIMER11_CR_T1nCLK_Pos             (14UL)                    /*!< TIMER11 CR: T1nCLK (Bit 14)                           */
+#define TIMER11_CR_T1nCLK_Msk             (0x4000UL)                /*!< TIMER11 CR: T1nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER11_CR_T1nMS_Pos              (12UL)                    /*!< TIMER11 CR: T1nMS (Bit 12)                            */
+#define TIMER11_CR_T1nMS_Msk              (0x3000UL)                /*!< TIMER11 CR: T1nMS (Bitfield-Mask: 0x03)               */
+#define TIMER11_CR_T1nECE_Pos             (11UL)                    /*!< TIMER11 CR: T1nECE (Bit 11)                           */
+#define TIMER11_CR_T1nECE_Msk             (0x800UL)                 /*!< TIMER11 CR: T1nECE (Bitfield-Mask: 0x01)              */
+#define TIMER11_CR_T1nOPOL_Pos            (8UL)                     /*!< TIMER11 CR: T1nOPOL (Bit 8)                           */
+#define TIMER11_CR_T1nOPOL_Msk            (0x100UL)                 /*!< TIMER11 CR: T1nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER11_CR_T1nCPOL_Pos            (6UL)                     /*!< TIMER11 CR: T1nCPOL (Bit 6)                           */
+#define TIMER11_CR_T1nCPOL_Msk            (0xc0UL)                  /*!< TIMER11 CR: T1nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER11_CR_T1nMIEN_Pos            (5UL)                     /*!< TIMER11 CR: T1nMIEN (Bit 5)                           */
+#define TIMER11_CR_T1nMIEN_Msk            (0x20UL)                  /*!< TIMER11 CR: T1nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER11_CR_T1nCIEN_Pos            (4UL)                     /*!< TIMER11 CR: T1nCIEN (Bit 4)                           */
+#define TIMER11_CR_T1nCIEN_Msk            (0x10UL)                  /*!< TIMER11 CR: T1nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER11_CR_T1nMIFLAG_Pos          (3UL)                     /*!< TIMER11 CR: T1nMIFLAG (Bit 3)                         */
+#define TIMER11_CR_T1nMIFLAG_Msk          (0x8UL)                   /*!< TIMER11 CR: T1nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER11_CR_T1nCIFLAG_Pos          (2UL)                     /*!< TIMER11 CR: T1nCIFLAG (Bit 2)                         */
+#define TIMER11_CR_T1nCIFLAG_Msk          (0x4UL)                   /*!< TIMER11 CR: T1nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER11_CR_T1nPAU_Pos             (1UL)                     /*!< TIMER11 CR: T1nPAU (Bit 1)                            */
+#define TIMER11_CR_T1nPAU_Msk             (0x2UL)                   /*!< TIMER11 CR: T1nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER11_CR_T1nCLR_Pos             (0UL)                     /*!< TIMER11 CR: T1nCLR (Bit 0)                            */
+#define TIMER11_CR_T1nCLR_Msk             (0x1UL)                   /*!< TIMER11 CR: T1nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER11_ADR_ADATA_Pos             (0UL)                     /*!< TIMER11 ADR: ADATA (Bit 0)                            */
+#define TIMER11_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER11 ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER11_BDR_BDATA_Pos             (0UL)                     /*!< TIMER11 BDR: BDATA (Bit 0)                            */
+#define TIMER11_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER11 BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER11_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER11 CAPDR: CAPD (Bit 0)                           */
+#define TIMER11_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER11 CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER11_PREDR_PRED_Pos            (0UL)                     /*!< TIMER11 PREDR: PRED (Bit 0)                           */
+#define TIMER11_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER11 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER11_CNT_CNT_Pos               (0UL)                     /*!< TIMER11 CNT: CNT (Bit 0)                              */
+#define TIMER11_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER11 CNT: CNT (Bitfield-Mask: 0xffff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER12                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER12_CR_T1nEN_Pos              (15UL)                    /*!< TIMER12 CR: T1nEN (Bit 15)                            */
+#define TIMER12_CR_T1nEN_Msk              (0x8000UL)                /*!< TIMER12 CR: T1nEN (Bitfield-Mask: 0x01)               */
+#define TIMER12_CR_T1nCLK_Pos             (14UL)                    /*!< TIMER12 CR: T1nCLK (Bit 14)                           */
+#define TIMER12_CR_T1nCLK_Msk             (0x4000UL)                /*!< TIMER12 CR: T1nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER12_CR_T1nMS_Pos              (12UL)                    /*!< TIMER12 CR: T1nMS (Bit 12)                            */
+#define TIMER12_CR_T1nMS_Msk              (0x3000UL)                /*!< TIMER12 CR: T1nMS (Bitfield-Mask: 0x03)               */
+#define TIMER12_CR_T1nECE_Pos             (11UL)                    /*!< TIMER12 CR: T1nECE (Bit 11)                           */
+#define TIMER12_CR_T1nECE_Msk             (0x800UL)                 /*!< TIMER12 CR: T1nECE (Bitfield-Mask: 0x01)              */
+#define TIMER12_CR_T1nOPOL_Pos            (8UL)                     /*!< TIMER12 CR: T1nOPOL (Bit 8)                           */
+#define TIMER12_CR_T1nOPOL_Msk            (0x100UL)                 /*!< TIMER12 CR: T1nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER12_CR_T1nCPOL_Pos            (6UL)                     /*!< TIMER12 CR: T1nCPOL (Bit 6)                           */
+#define TIMER12_CR_T1nCPOL_Msk            (0xc0UL)                  /*!< TIMER12 CR: T1nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER12_CR_T1nMIEN_Pos            (5UL)                     /*!< TIMER12 CR: T1nMIEN (Bit 5)                           */
+#define TIMER12_CR_T1nMIEN_Msk            (0x20UL)                  /*!< TIMER12 CR: T1nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER12_CR_T1nCIEN_Pos            (4UL)                     /*!< TIMER12 CR: T1nCIEN (Bit 4)                           */
+#define TIMER12_CR_T1nCIEN_Msk            (0x10UL)                  /*!< TIMER12 CR: T1nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER12_CR_T1nMIFLAG_Pos          (3UL)                     /*!< TIMER12 CR: T1nMIFLAG (Bit 3)                         */
+#define TIMER12_CR_T1nMIFLAG_Msk          (0x8UL)                   /*!< TIMER12 CR: T1nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER12_CR_T1nCIFLAG_Pos          (2UL)                     /*!< TIMER12 CR: T1nCIFLAG (Bit 2)                         */
+#define TIMER12_CR_T1nCIFLAG_Msk          (0x4UL)                   /*!< TIMER12 CR: T1nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER12_CR_T1nPAU_Pos             (1UL)                     /*!< TIMER12 CR: T1nPAU (Bit 1)                            */
+#define TIMER12_CR_T1nPAU_Msk             (0x2UL)                   /*!< TIMER12 CR: T1nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER12_CR_T1nCLR_Pos             (0UL)                     /*!< TIMER12 CR: T1nCLR (Bit 0)                            */
+#define TIMER12_CR_T1nCLR_Msk             (0x1UL)                   /*!< TIMER12 CR: T1nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER12_ADR_ADATA_Pos             (0UL)                     /*!< TIMER12 ADR: ADATA (Bit 0)                            */
+#define TIMER12_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER12 ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER12_BDR_BDATA_Pos             (0UL)                     /*!< TIMER12 BDR: BDATA (Bit 0)                            */
+#define TIMER12_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER12 BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER12_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER12 CAPDR: CAPD (Bit 0)                           */
+#define TIMER12_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER12 CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER12_PREDR_PRED_Pos            (0UL)                     /*!< TIMER12 PREDR: PRED (Bit 0)                           */
+#define TIMER12_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER12 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER12_CNT_CNT_Pos               (0UL)                     /*!< TIMER12 CNT: CNT (Bit 0)                              */
+#define TIMER12_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER12 CNT: CNT (Bitfield-Mask: 0xffff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER13                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER13_CR_T1nEN_Pos              (15UL)                    /*!< TIMER13 CR: T1nEN (Bit 15)                            */
+#define TIMER13_CR_T1nEN_Msk              (0x8000UL)                /*!< TIMER13 CR: T1nEN (Bitfield-Mask: 0x01)               */
+#define TIMER13_CR_T1nCLK_Pos             (14UL)                    /*!< TIMER13 CR: T1nCLK (Bit 14)                           */
+#define TIMER13_CR_T1nCLK_Msk             (0x4000UL)                /*!< TIMER13 CR: T1nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER13_CR_T1nMS_Pos              (12UL)                    /*!< TIMER13 CR: T1nMS (Bit 12)                            */
+#define TIMER13_CR_T1nMS_Msk              (0x3000UL)                /*!< TIMER13 CR: T1nMS (Bitfield-Mask: 0x03)               */
+#define TIMER13_CR_T1nECE_Pos             (11UL)                    /*!< TIMER13 CR: T1nECE (Bit 11)                           */
+#define TIMER13_CR_T1nECE_Msk             (0x800UL)                 /*!< TIMER13 CR: T1nECE (Bitfield-Mask: 0x01)              */
+#define TIMER13_CR_T1nOPOL_Pos            (8UL)                     /*!< TIMER13 CR: T1nOPOL (Bit 8)                           */
+#define TIMER13_CR_T1nOPOL_Msk            (0x100UL)                 /*!< TIMER13 CR: T1nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER13_CR_T1nCPOL_Pos            (6UL)                     /*!< TIMER13 CR: T1nCPOL (Bit 6)                           */
+#define TIMER13_CR_T1nCPOL_Msk            (0xc0UL)                  /*!< TIMER13 CR: T1nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER13_CR_T1nMIEN_Pos            (5UL)                     /*!< TIMER13 CR: T1nMIEN (Bit 5)                           */
+#define TIMER13_CR_T1nMIEN_Msk            (0x20UL)                  /*!< TIMER13 CR: T1nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER13_CR_T1nCIEN_Pos            (4UL)                     /*!< TIMER13 CR: T1nCIEN (Bit 4)                           */
+#define TIMER13_CR_T1nCIEN_Msk            (0x10UL)                  /*!< TIMER13 CR: T1nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER13_CR_T1nMIFLAG_Pos          (3UL)                     /*!< TIMER13 CR: T1nMIFLAG (Bit 3)                         */
+#define TIMER13_CR_T1nMIFLAG_Msk          (0x8UL)                   /*!< TIMER13 CR: T1nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER13_CR_T1nCIFLAG_Pos          (2UL)                     /*!< TIMER13 CR: T1nCIFLAG (Bit 2)                         */
+#define TIMER13_CR_T1nCIFLAG_Msk          (0x4UL)                   /*!< TIMER13 CR: T1nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER13_CR_T1nPAU_Pos             (1UL)                     /*!< TIMER13 CR: T1nPAU (Bit 1)                            */
+#define TIMER13_CR_T1nPAU_Msk             (0x2UL)                   /*!< TIMER13 CR: T1nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER13_CR_T1nCLR_Pos             (0UL)                     /*!< TIMER13 CR: T1nCLR (Bit 0)                            */
+#define TIMER13_CR_T1nCLR_Msk             (0x1UL)                   /*!< TIMER13 CR: T1nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER13_ADR_ADATA_Pos             (0UL)                     /*!< TIMER13 ADR: ADATA (Bit 0)                            */
+#define TIMER13_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER13 ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER13_BDR_BDATA_Pos             (0UL)                     /*!< TIMER13 BDR: BDATA (Bit 0)                            */
+#define TIMER13_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER13 BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER13_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER13 CAPDR: CAPD (Bit 0)                           */
+#define TIMER13_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER13 CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER13_PREDR_PRED_Pos            (0UL)                     /*!< TIMER13 PREDR: PRED (Bit 0)                           */
+#define TIMER13_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER13 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER13_CNT_CNT_Pos               (0UL)                     /*!< TIMER13 CNT: CNT (Bit 0)                              */
+#define TIMER13_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER13 CNT: CNT (Bitfield-Mask: 0xffff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER14                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER14_CR_T1nEN_Pos              (15UL)                    /*!< TIMER14 CR: T1nEN (Bit 15)                            */
+#define TIMER14_CR_T1nEN_Msk              (0x8000UL)                /*!< TIMER14 CR: T1nEN (Bitfield-Mask: 0x01)               */
+#define TIMER14_CR_T1nCLK_Pos             (14UL)                    /*!< TIMER14 CR: T1nCLK (Bit 14)                           */
+#define TIMER14_CR_T1nCLK_Msk             (0x4000UL)                /*!< TIMER14 CR: T1nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER14_CR_T1nMS_Pos              (12UL)                    /*!< TIMER14 CR: T1nMS (Bit 12)                            */
+#define TIMER14_CR_T1nMS_Msk              (0x3000UL)                /*!< TIMER14 CR: T1nMS (Bitfield-Mask: 0x03)               */
+#define TIMER14_CR_T1nECE_Pos             (11UL)                    /*!< TIMER14 CR: T1nECE (Bit 11)                           */
+#define TIMER14_CR_T1nECE_Msk             (0x800UL)                 /*!< TIMER14 CR: T1nECE (Bitfield-Mask: 0x01)              */
+#define TIMER14_CR_T1nOPOL_Pos            (8UL)                     /*!< TIMER14 CR: T1nOPOL (Bit 8)                           */
+#define TIMER14_CR_T1nOPOL_Msk            (0x100UL)                 /*!< TIMER14 CR: T1nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER14_CR_T1nCPOL_Pos            (6UL)                     /*!< TIMER14 CR: T1nCPOL (Bit 6)                           */
+#define TIMER14_CR_T1nCPOL_Msk            (0xc0UL)                  /*!< TIMER14 CR: T1nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER14_CR_T1nMIEN_Pos            (5UL)                     /*!< TIMER14 CR: T1nMIEN (Bit 5)                           */
+#define TIMER14_CR_T1nMIEN_Msk            (0x20UL)                  /*!< TIMER14 CR: T1nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER14_CR_T1nCIEN_Pos            (4UL)                     /*!< TIMER14 CR: T1nCIEN (Bit 4)                           */
+#define TIMER14_CR_T1nCIEN_Msk            (0x10UL)                  /*!< TIMER14 CR: T1nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER14_CR_T1nMIFLAG_Pos          (3UL)                     /*!< TIMER14 CR: T1nMIFLAG (Bit 3)                         */
+#define TIMER14_CR_T1nMIFLAG_Msk          (0x8UL)                   /*!< TIMER14 CR: T1nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER14_CR_T1nCIFLAG_Pos          (2UL)                     /*!< TIMER14 CR: T1nCIFLAG (Bit 2)                         */
+#define TIMER14_CR_T1nCIFLAG_Msk          (0x4UL)                   /*!< TIMER14 CR: T1nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER14_CR_T1nPAU_Pos             (1UL)                     /*!< TIMER14 CR: T1nPAU (Bit 1)                            */
+#define TIMER14_CR_T1nPAU_Msk             (0x2UL)                   /*!< TIMER14 CR: T1nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER14_CR_T1nCLR_Pos             (0UL)                     /*!< TIMER14 CR: T1nCLR (Bit 0)                            */
+#define TIMER14_CR_T1nCLR_Msk             (0x1UL)                   /*!< TIMER14 CR: T1nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER14_ADR_ADATA_Pos             (0UL)                     /*!< TIMER14 ADR: ADATA (Bit 0)                            */
+#define TIMER14_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER14 ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER14_BDR_BDATA_Pos             (0UL)                     /*!< TIMER14 BDR: BDATA (Bit 0)                            */
+#define TIMER14_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER14 BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER14_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER14 CAPDR: CAPD (Bit 0)                           */
+#define TIMER14_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER14 CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER14_PREDR_PRED_Pos            (0UL)                     /*!< TIMER14 PREDR: PRED (Bit 0)                           */
+#define TIMER14_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER14 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER14_CNT_CNT_Pos               (0UL)                     /*!< TIMER14 CNT: CNT (Bit 0)                              */
+#define TIMER14_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER14 CNT: CNT (Bitfield-Mask: 0xffff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER15                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER15_CR_T1nEN_Pos              (15UL)                    /*!< TIMER15 CR: T1nEN (Bit 15)                            */
+#define TIMER15_CR_T1nEN_Msk              (0x8000UL)                /*!< TIMER15 CR: T1nEN (Bitfield-Mask: 0x01)               */
+#define TIMER15_CR_T1nCLK_Pos             (14UL)                    /*!< TIMER15 CR: T1nCLK (Bit 14)                           */
+#define TIMER15_CR_T1nCLK_Msk             (0x4000UL)                /*!< TIMER15 CR: T1nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER15_CR_T1nMS_Pos              (12UL)                    /*!< TIMER15 CR: T1nMS (Bit 12)                            */
+#define TIMER15_CR_T1nMS_Msk              (0x3000UL)                /*!< TIMER15 CR: T1nMS (Bitfield-Mask: 0x03)               */
+#define TIMER15_CR_T1nECE_Pos             (11UL)                    /*!< TIMER15 CR: T1nECE (Bit 11)                           */
+#define TIMER15_CR_T1nECE_Msk             (0x800UL)                 /*!< TIMER15 CR: T1nECE (Bitfield-Mask: 0x01)              */
+#define TIMER15_CR_T1nOPOL_Pos            (8UL)                     /*!< TIMER15 CR: T1nOPOL (Bit 8)                           */
+#define TIMER15_CR_T1nOPOL_Msk            (0x100UL)                 /*!< TIMER15 CR: T1nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER15_CR_T1nCPOL_Pos            (6UL)                     /*!< TIMER15 CR: T1nCPOL (Bit 6)                           */
+#define TIMER15_CR_T1nCPOL_Msk            (0xc0UL)                  /*!< TIMER15 CR: T1nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER15_CR_T1nMIEN_Pos            (5UL)                     /*!< TIMER15 CR: T1nMIEN (Bit 5)                           */
+#define TIMER15_CR_T1nMIEN_Msk            (0x20UL)                  /*!< TIMER15 CR: T1nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER15_CR_T1nCIEN_Pos            (4UL)                     /*!< TIMER15 CR: T1nCIEN (Bit 4)                           */
+#define TIMER15_CR_T1nCIEN_Msk            (0x10UL)                  /*!< TIMER15 CR: T1nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER15_CR_T1nMIFLAG_Pos          (3UL)                     /*!< TIMER15 CR: T1nMIFLAG (Bit 3)                         */
+#define TIMER15_CR_T1nMIFLAG_Msk          (0x8UL)                   /*!< TIMER15 CR: T1nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER15_CR_T1nCIFLAG_Pos          (2UL)                     /*!< TIMER15 CR: T1nCIFLAG (Bit 2)                         */
+#define TIMER15_CR_T1nCIFLAG_Msk          (0x4UL)                   /*!< TIMER15 CR: T1nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER15_CR_T1nPAU_Pos             (1UL)                     /*!< TIMER15 CR: T1nPAU (Bit 1)                            */
+#define TIMER15_CR_T1nPAU_Msk             (0x2UL)                   /*!< TIMER15 CR: T1nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER15_CR_T1nCLR_Pos             (0UL)                     /*!< TIMER15 CR: T1nCLR (Bit 0)                            */
+#define TIMER15_CR_T1nCLR_Msk             (0x1UL)                   /*!< TIMER15 CR: T1nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER15_ADR_ADATA_Pos             (0UL)                     /*!< TIMER15 ADR: ADATA (Bit 0)                            */
+#define TIMER15_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER15 ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER15_BDR_BDATA_Pos             (0UL)                     /*!< TIMER15 BDR: BDATA (Bit 0)                            */
+#define TIMER15_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER15 BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER15_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER15 CAPDR: CAPD (Bit 0)                           */
+#define TIMER15_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER15 CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER15_PREDR_PRED_Pos            (0UL)                     /*!< TIMER15 PREDR: PRED (Bit 0)                           */
+#define TIMER15_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER15 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER15_CNT_CNT_Pos               (0UL)                     /*!< TIMER15 CNT: CNT (Bit 0)                              */
+#define TIMER15_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER15 CNT: CNT (Bitfield-Mask: 0xffff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER16                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER16_CR_T1nEN_Pos              (15UL)                    /*!< TIMER16 CR: T1nEN (Bit 15)                            */
+#define TIMER16_CR_T1nEN_Msk              (0x8000UL)                /*!< TIMER16 CR: T1nEN (Bitfield-Mask: 0x01)               */
+#define TIMER16_CR_T1nCLK_Pos             (14UL)                    /*!< TIMER16 CR: T1nCLK (Bit 14)                           */
+#define TIMER16_CR_T1nCLK_Msk             (0x4000UL)                /*!< TIMER16 CR: T1nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER16_CR_T1nMS_Pos              (12UL)                    /*!< TIMER16 CR: T1nMS (Bit 12)                            */
+#define TIMER16_CR_T1nMS_Msk              (0x3000UL)                /*!< TIMER16 CR: T1nMS (Bitfield-Mask: 0x03)               */
+#define TIMER16_CR_T1nECE_Pos             (11UL)                    /*!< TIMER16 CR: T1nECE (Bit 11)                           */
+#define TIMER16_CR_T1nECE_Msk             (0x800UL)                 /*!< TIMER16 CR: T1nECE (Bitfield-Mask: 0x01)              */
+#define TIMER16_CR_T1nOPOL_Pos            (8UL)                     /*!< TIMER16 CR: T1nOPOL (Bit 8)                           */
+#define TIMER16_CR_T1nOPOL_Msk            (0x100UL)                 /*!< TIMER16 CR: T1nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER16_CR_T1nCPOL_Pos            (6UL)                     /*!< TIMER16 CR: T1nCPOL (Bit 6)                           */
+#define TIMER16_CR_T1nCPOL_Msk            (0xc0UL)                  /*!< TIMER16 CR: T1nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER16_CR_T1nMIEN_Pos            (5UL)                     /*!< TIMER16 CR: T1nMIEN (Bit 5)                           */
+#define TIMER16_CR_T1nMIEN_Msk            (0x20UL)                  /*!< TIMER16 CR: T1nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER16_CR_T1nCIEN_Pos            (4UL)                     /*!< TIMER16 CR: T1nCIEN (Bit 4)                           */
+#define TIMER16_CR_T1nCIEN_Msk            (0x10UL)                  /*!< TIMER16 CR: T1nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER16_CR_T1nMIFLAG_Pos          (3UL)                     /*!< TIMER16 CR: T1nMIFLAG (Bit 3)                         */
+#define TIMER16_CR_T1nMIFLAG_Msk          (0x8UL)                   /*!< TIMER16 CR: T1nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER16_CR_T1nCIFLAG_Pos          (2UL)                     /*!< TIMER16 CR: T1nCIFLAG (Bit 2)                         */
+#define TIMER16_CR_T1nCIFLAG_Msk          (0x4UL)                   /*!< TIMER16 CR: T1nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER16_CR_T1nPAU_Pos             (1UL)                     /*!< TIMER16 CR: T1nPAU (Bit 1)                            */
+#define TIMER16_CR_T1nPAU_Msk             (0x2UL)                   /*!< TIMER16 CR: T1nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER16_CR_T1nCLR_Pos             (0UL)                     /*!< TIMER16 CR: T1nCLR (Bit 0)                            */
+#define TIMER16_CR_T1nCLR_Msk             (0x1UL)                   /*!< TIMER16 CR: T1nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER16_ADR_ADATA_Pos             (0UL)                     /*!< TIMER16 ADR: ADATA (Bit 0)                            */
+#define TIMER16_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER16 ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER16_BDR_BDATA_Pos             (0UL)                     /*!< TIMER16 BDR: BDATA (Bit 0)                            */
+#define TIMER16_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER16 BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER16_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER16 CAPDR: CAPD (Bit 0)                           */
+#define TIMER16_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER16 CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER16_PREDR_PRED_Pos            (0UL)                     /*!< TIMER16 PREDR: PRED (Bit 0)                           */
+#define TIMER16_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER16 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER16_CNT_CNT_Pos               (0UL)                     /*!< TIMER16 CNT: CNT (Bit 0)                              */
+#define TIMER16_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER16 CNT: CNT (Bitfield-Mask: 0xffff)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER2n                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER2n_CR_T2nEN_Pos              (15UL)                    /*!< TIMER2n CR: T2nEN (Bit 15)                            */
+#define TIMER2n_CR_T2nEN_Msk              (0x8000UL)                /*!< TIMER2n CR: T2nEN (Bitfield-Mask: 0x01)               */
+#define TIMER2n_CR_T2nCLK_Pos             (14UL)                    /*!< TIMER2n CR: T2nCLK (Bit 14)                           */
+#define TIMER2n_CR_T2nCLK_Msk             (0x4000UL)                /*!< TIMER2n CR: T2nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER2n_CR_T2nMS_Pos              (12UL)                    /*!< TIMER2n CR: T2nMS (Bit 12)                            */
+#define TIMER2n_CR_T2nMS_Msk              (0x3000UL)                /*!< TIMER2n CR: T2nMS (Bitfield-Mask: 0x03)               */
+#define TIMER2n_CR_T2nECE_Pos             (11UL)                    /*!< TIMER2n CR: T2nECE (Bit 11)                           */
+#define TIMER2n_CR_T2nECE_Msk             (0x800UL)                 /*!< TIMER2n CR: T2nECE (Bitfield-Mask: 0x01)              */
+#define TIMER2n_CR_CAPSEL_Pos             (9UL)                     /*!< TIMER2n CR: CAPSEL (Bit 9)                            */
+#define TIMER2n_CR_CAPSEL_Msk             (0x600UL)                 /*!< TIMER2n CR: CAPSEL (Bitfield-Mask: 0x03)              */
+#define TIMER2n_CR_T2nOPOL_Pos            (8UL)                     /*!< TIMER2n CR: T2nOPOL (Bit 8)                           */
+#define TIMER2n_CR_T2nOPOL_Msk            (0x100UL)                 /*!< TIMER2n CR: T2nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER2n_CR_T2nCPOL_Pos            (6UL)                     /*!< TIMER2n CR: T2nCPOL (Bit 6)                           */
+#define TIMER2n_CR_T2nCPOL_Msk            (0xc0UL)                  /*!< TIMER2n CR: T2nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER2n_CR_T2nMIEN_Pos            (5UL)                     /*!< TIMER2n CR: T2nMIEN (Bit 5)                           */
+#define TIMER2n_CR_T2nMIEN_Msk            (0x20UL)                  /*!< TIMER2n CR: T2nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER2n_CR_T2nCIEN_Pos            (4UL)                     /*!< TIMER2n CR: T2nCIEN (Bit 4)                           */
+#define TIMER2n_CR_T2nCIEN_Msk            (0x10UL)                  /*!< TIMER2n CR: T2nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER2n_CR_T2nMIFLAG_Pos          (3UL)                     /*!< TIMER2n CR: T2nMIFLAG (Bit 3)                         */
+#define TIMER2n_CR_T2nMIFLAG_Msk          (0x8UL)                   /*!< TIMER2n CR: T2nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER2n_CR_T2nCIFLAG_Pos          (2UL)                     /*!< TIMER2n CR: T2nCIFLAG (Bit 2)                         */
+#define TIMER2n_CR_T2nCIFLAG_Msk          (0x4UL)                   /*!< TIMER2n CR: T2nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER2n_CR_T2nPAU_Pos             (1UL)                     /*!< TIMER2n CR: T2nPAU (Bit 1)                            */
+#define TIMER2n_CR_T2nPAU_Msk             (0x2UL)                   /*!< TIMER2n CR: T2nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER2n_CR_T2nCLR_Pos             (0UL)                     /*!< TIMER2n CR: T2nCLR (Bit 0)                            */
+#define TIMER2n_CR_T2nCLR_Msk             (0x1UL)                   /*!< TIMER2n CR: T2nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER2n_ADR_ADATA_Pos             (0UL)                     /*!< TIMER2n ADR: ADATA (Bit 0)                            */
+#define TIMER2n_ADR_ADATA_Msk             (0xffffffffUL)            /*!< TIMER2n ADR: ADATA (Bitfield-Mask: 0xffffffff)        */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER2n_BDR_BDATA_Pos             (0UL)                     /*!< TIMER2n BDR: BDATA (Bit 0)                            */
+#define TIMER2n_BDR_BDATA_Msk             (0xffffffffUL)            /*!< TIMER2n BDR: BDATA (Bitfield-Mask: 0xffffffff)        */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER2n_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER2n CAPDR: CAPD (Bit 0)                           */
+#define TIMER2n_CAPDR_CAPD_Msk            (0xffffffffUL)            /*!< TIMER2n CAPDR: CAPD (Bitfield-Mask: 0xffffffff)       */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER2n_PREDR_PRED_Pos            (0UL)                     /*!< TIMER2n PREDR: PRED (Bit 0)                           */
+#define TIMER2n_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER2n PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER2n_CNT_CNT_Pos               (0UL)                     /*!< TIMER2n CNT: CNT (Bit 0)                              */
+#define TIMER2n_CNT_CNT_Msk               (0xffffffffUL)            /*!< TIMER2n CNT: CNT (Bitfield-Mask: 0xffffffff)          */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER20                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER20_CR_T2nEN_Pos              (15UL)                    /*!< TIMER20 CR: T2nEN (Bit 15)                            */
+#define TIMER20_CR_T2nEN_Msk              (0x8000UL)                /*!< TIMER20 CR: T2nEN (Bitfield-Mask: 0x01)               */
+#define TIMER20_CR_T2nCLK_Pos             (14UL)                    /*!< TIMER20 CR: T2nCLK (Bit 14)                           */
+#define TIMER20_CR_T2nCLK_Msk             (0x4000UL)                /*!< TIMER20 CR: T2nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER20_CR_T2nMS_Pos              (12UL)                    /*!< TIMER20 CR: T2nMS (Bit 12)                            */
+#define TIMER20_CR_T2nMS_Msk              (0x3000UL)                /*!< TIMER20 CR: T2nMS (Bitfield-Mask: 0x03)               */
+#define TIMER20_CR_T2nECE_Pos             (11UL)                    /*!< TIMER20 CR: T2nECE (Bit 11)                           */
+#define TIMER20_CR_T2nECE_Msk             (0x800UL)                 /*!< TIMER20 CR: T2nECE (Bitfield-Mask: 0x01)              */
+#define TIMER20_CR_CAPSEL_Pos             (9UL)                     /*!< TIMER20 CR: CAPSEL (Bit 9)                            */
+#define TIMER20_CR_CAPSEL_Msk             (0x600UL)                 /*!< TIMER20 CR: CAPSEL (Bitfield-Mask: 0x03)              */
+#define TIMER20_CR_T2nOPOL_Pos            (8UL)                     /*!< TIMER20 CR: T2nOPOL (Bit 8)                           */
+#define TIMER20_CR_T2nOPOL_Msk            (0x100UL)                 /*!< TIMER20 CR: T2nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER20_CR_T2nCPOL_Pos            (6UL)                     /*!< TIMER20 CR: T2nCPOL (Bit 6)                           */
+#define TIMER20_CR_T2nCPOL_Msk            (0xc0UL)                  /*!< TIMER20 CR: T2nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER20_CR_T2nMIEN_Pos            (5UL)                     /*!< TIMER20 CR: T2nMIEN (Bit 5)                           */
+#define TIMER20_CR_T2nMIEN_Msk            (0x20UL)                  /*!< TIMER20 CR: T2nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER20_CR_T2nCIEN_Pos            (4UL)                     /*!< TIMER20 CR: T2nCIEN (Bit 4)                           */
+#define TIMER20_CR_T2nCIEN_Msk            (0x10UL)                  /*!< TIMER20 CR: T2nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER20_CR_T2nMIFLAG_Pos          (3UL)                     /*!< TIMER20 CR: T2nMIFLAG (Bit 3)                         */
+#define TIMER20_CR_T2nMIFLAG_Msk          (0x8UL)                   /*!< TIMER20 CR: T2nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER20_CR_T2nCIFLAG_Pos          (2UL)                     /*!< TIMER20 CR: T2nCIFLAG (Bit 2)                         */
+#define TIMER20_CR_T2nCIFLAG_Msk          (0x4UL)                   /*!< TIMER20 CR: T2nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER20_CR_T2nPAU_Pos             (1UL)                     /*!< TIMER20 CR: T2nPAU (Bit 1)                            */
+#define TIMER20_CR_T2nPAU_Msk             (0x2UL)                   /*!< TIMER20 CR: T2nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER20_CR_T2nCLR_Pos             (0UL)                     /*!< TIMER20 CR: T2nCLR (Bit 0)                            */
+#define TIMER20_CR_T2nCLR_Msk             (0x1UL)                   /*!< TIMER20 CR: T2nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER20_ADR_ADATA_Pos             (0UL)                     /*!< TIMER20 ADR: ADATA (Bit 0)                            */
+#define TIMER20_ADR_ADATA_Msk             (0xffffffffUL)            /*!< TIMER20 ADR: ADATA (Bitfield-Mask: 0xffffffff)        */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER20_BDR_BDATA_Pos             (0UL)                     /*!< TIMER20 BDR: BDATA (Bit 0)                            */
+#define TIMER20_BDR_BDATA_Msk             (0xffffffffUL)            /*!< TIMER20 BDR: BDATA (Bitfield-Mask: 0xffffffff)        */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER20_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER20 CAPDR: CAPD (Bit 0)                           */
+#define TIMER20_CAPDR_CAPD_Msk            (0xffffffffUL)            /*!< TIMER20 CAPDR: CAPD (Bitfield-Mask: 0xffffffff)       */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER20_PREDR_PRED_Pos            (0UL)                     /*!< TIMER20 PREDR: PRED (Bit 0)                           */
+#define TIMER20_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER20 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER20_CNT_CNT_Pos               (0UL)                     /*!< TIMER20 CNT: CNT (Bit 0)                              */
+#define TIMER20_CNT_CNT_Msk               (0xffffffffUL)            /*!< TIMER20 CNT: CNT (Bitfield-Mask: 0xffffffff)          */
+/* ======================================================  TIMER20_CR  ======================================================= */
+#define TIMER20_TIMER20_CR_T2nEN_Pos      (15UL)                    /*!< TIMER20 TIMER20_CR: T2nEN (Bit 15)                    */
+#define TIMER20_TIMER20_CR_T2nEN_Msk      (0x8000UL)                /*!< TIMER20 TIMER20_CR: T2nEN (Bitfield-Mask: 0x01)       */
+#define TIMER20_TIMER20_CR_T2nCLK_Pos     (14UL)                    /*!< TIMER20 TIMER20_CR: T2nCLK (Bit 14)                   */
+#define TIMER20_TIMER20_CR_T2nCLK_Msk     (0x4000UL)                /*!< TIMER20 TIMER20_CR: T2nCLK (Bitfield-Mask: 0x01)      */
+#define TIMER20_TIMER20_CR_T2nMS_Pos      (12UL)                    /*!< TIMER20 TIMER20_CR: T2nMS (Bit 12)                    */
+#define TIMER20_TIMER20_CR_T2nMS_Msk      (0x3000UL)                /*!< TIMER20 TIMER20_CR: T2nMS (Bitfield-Mask: 0x03)       */
+#define TIMER20_TIMER20_CR_T2nECE_Pos     (11UL)                    /*!< TIMER20 TIMER20_CR: T2nECE (Bit 11)                   */
+#define TIMER20_TIMER20_CR_T2nECE_Msk     (0x800UL)                 /*!< TIMER20 TIMER20_CR: T2nECE (Bitfield-Mask: 0x01)      */
+#define TIMER20_TIMER20_CR_CAPSEL_Pos     (9UL)                     /*!< TIMER20 TIMER20_CR: CAPSEL (Bit 9)                    */
+#define TIMER20_TIMER20_CR_CAPSEL_Msk     (0x600UL)                 /*!< TIMER20 TIMER20_CR: CAPSEL (Bitfield-Mask: 0x03)      */
+#define TIMER20_TIMER20_CR_T2nOPOL_Pos    (8UL)                     /*!< TIMER20 TIMER20_CR: T2nOPOL (Bit 8)                   */
+#define TIMER20_TIMER20_CR_T2nOPOL_Msk    (0x100UL)                 /*!< TIMER20 TIMER20_CR: T2nOPOL (Bitfield-Mask: 0x01)     */
+#define TIMER20_TIMER20_CR_T2nCPOL_Pos    (6UL)                     /*!< TIMER20 TIMER20_CR: T2nCPOL (Bit 6)                   */
+#define TIMER20_TIMER20_CR_T2nCPOL_Msk    (0xc0UL)                  /*!< TIMER20 TIMER20_CR: T2nCPOL (Bitfield-Mask: 0x03)     */
+#define TIMER20_TIMER20_CR_T2nMIEN_Pos    (5UL)                     /*!< TIMER20 TIMER20_CR: T2nMIEN (Bit 5)                   */
+#define TIMER20_TIMER20_CR_T2nMIEN_Msk    (0x20UL)                  /*!< TIMER20 TIMER20_CR: T2nMIEN (Bitfield-Mask: 0x01)     */
+#define TIMER20_TIMER20_CR_T2nCIEN_Pos    (4UL)                     /*!< TIMER20 TIMER20_CR: T2nCIEN (Bit 4)                   */
+#define TIMER20_TIMER20_CR_T2nCIEN_Msk    (0x10UL)                  /*!< TIMER20 TIMER20_CR: T2nCIEN (Bitfield-Mask: 0x01)     */
+#define TIMER20_TIMER20_CR_T2nMIFLAG_Pos  (3UL)                     /*!< TIMER20 TIMER20_CR: T2nMIFLAG (Bit 3)                 */
+#define TIMER20_TIMER20_CR_T2nMIFLAG_Msk  (0x8UL)                   /*!< TIMER20 TIMER20_CR: T2nMIFLAG (Bitfield-Mask: 0x01)   */
+#define TIMER20_TIMER20_CR_T2nCIFLAG_Pos  (2UL)                     /*!< TIMER20 TIMER20_CR: T2nCIFLAG (Bit 2)                 */
+#define TIMER20_TIMER20_CR_T2nCIFLAG_Msk  (0x4UL)                   /*!< TIMER20 TIMER20_CR: T2nCIFLAG (Bitfield-Mask: 0x01)   */
+#define TIMER20_TIMER20_CR_T2nPAU_Pos     (1UL)                     /*!< TIMER20 TIMER20_CR: T2nPAU (Bit 1)                    */
+#define TIMER20_TIMER20_CR_T2nPAU_Msk     (0x2UL)                   /*!< TIMER20 TIMER20_CR: T2nPAU (Bitfield-Mask: 0x01)      */
+#define TIMER20_TIMER20_CR_T2nCLR_Pos     (0UL)                     /*!< TIMER20 TIMER20_CR: T2nCLR (Bit 0)                    */
+#define TIMER20_TIMER20_CR_T2nCLR_Msk     (0x1UL)                   /*!< TIMER20 TIMER20_CR: T2nCLR (Bitfield-Mask: 0x01)      */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER21                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER21_CR_T2nEN_Pos              (15UL)                    /*!< TIMER21 CR: T2nEN (Bit 15)                            */
+#define TIMER21_CR_T2nEN_Msk              (0x8000UL)                /*!< TIMER21 CR: T2nEN (Bitfield-Mask: 0x01)               */
+#define TIMER21_CR_T2nCLK_Pos             (14UL)                    /*!< TIMER21 CR: T2nCLK (Bit 14)                           */
+#define TIMER21_CR_T2nCLK_Msk             (0x4000UL)                /*!< TIMER21 CR: T2nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER21_CR_T2nMS_Pos              (12UL)                    /*!< TIMER21 CR: T2nMS (Bit 12)                            */
+#define TIMER21_CR_T2nMS_Msk              (0x3000UL)                /*!< TIMER21 CR: T2nMS (Bitfield-Mask: 0x03)               */
+#define TIMER21_CR_T2nECE_Pos             (11UL)                    /*!< TIMER21 CR: T2nECE (Bit 11)                           */
+#define TIMER21_CR_T2nECE_Msk             (0x800UL)                 /*!< TIMER21 CR: T2nECE (Bitfield-Mask: 0x01)              */
+#define TIMER21_CR_CAPSEL_Pos             (9UL)                     /*!< TIMER21 CR: CAPSEL (Bit 9)                            */
+#define TIMER21_CR_CAPSEL_Msk             (0x600UL)                 /*!< TIMER21 CR: CAPSEL (Bitfield-Mask: 0x03)              */
+#define TIMER21_CR_T2nOPOL_Pos            (8UL)                     /*!< TIMER21 CR: T2nOPOL (Bit 8)                           */
+#define TIMER21_CR_T2nOPOL_Msk            (0x100UL)                 /*!< TIMER21 CR: T2nOPOL (Bitfield-Mask: 0x01)             */
+#define TIMER21_CR_T2nCPOL_Pos            (6UL)                     /*!< TIMER21 CR: T2nCPOL (Bit 6)                           */
+#define TIMER21_CR_T2nCPOL_Msk            (0xc0UL)                  /*!< TIMER21 CR: T2nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER21_CR_T2nMIEN_Pos            (5UL)                     /*!< TIMER21 CR: T2nMIEN (Bit 5)                           */
+#define TIMER21_CR_T2nMIEN_Msk            (0x20UL)                  /*!< TIMER21 CR: T2nMIEN (Bitfield-Mask: 0x01)             */
+#define TIMER21_CR_T2nCIEN_Pos            (4UL)                     /*!< TIMER21 CR: T2nCIEN (Bit 4)                           */
+#define TIMER21_CR_T2nCIEN_Msk            (0x10UL)                  /*!< TIMER21 CR: T2nCIEN (Bitfield-Mask: 0x01)             */
+#define TIMER21_CR_T2nMIFLAG_Pos          (3UL)                     /*!< TIMER21 CR: T2nMIFLAG (Bit 3)                         */
+#define TIMER21_CR_T2nMIFLAG_Msk          (0x8UL)                   /*!< TIMER21 CR: T2nMIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER21_CR_T2nCIFLAG_Pos          (2UL)                     /*!< TIMER21 CR: T2nCIFLAG (Bit 2)                         */
+#define TIMER21_CR_T2nCIFLAG_Msk          (0x4UL)                   /*!< TIMER21 CR: T2nCIFLAG (Bitfield-Mask: 0x01)           */
+#define TIMER21_CR_T2nPAU_Pos             (1UL)                     /*!< TIMER21 CR: T2nPAU (Bit 1)                            */
+#define TIMER21_CR_T2nPAU_Msk             (0x2UL)                   /*!< TIMER21 CR: T2nPAU (Bitfield-Mask: 0x01)              */
+#define TIMER21_CR_T2nCLR_Pos             (0UL)                     /*!< TIMER21 CR: T2nCLR (Bit 0)                            */
+#define TIMER21_CR_T2nCLR_Msk             (0x1UL)                   /*!< TIMER21 CR: T2nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER21_ADR_ADATA_Pos             (0UL)                     /*!< TIMER21 ADR: ADATA (Bit 0)                            */
+#define TIMER21_ADR_ADATA_Msk             (0xffffffffUL)            /*!< TIMER21 ADR: ADATA (Bitfield-Mask: 0xffffffff)        */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER21_BDR_BDATA_Pos             (0UL)                     /*!< TIMER21 BDR: BDATA (Bit 0)                            */
+#define TIMER21_BDR_BDATA_Msk             (0xffffffffUL)            /*!< TIMER21 BDR: BDATA (Bitfield-Mask: 0xffffffff)        */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER21_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER21 CAPDR: CAPD (Bit 0)                           */
+#define TIMER21_CAPDR_CAPD_Msk            (0xffffffffUL)            /*!< TIMER21 CAPDR: CAPD (Bitfield-Mask: 0xffffffff)       */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER21_PREDR_PRED_Pos            (0UL)                     /*!< TIMER21 PREDR: PRED (Bit 0)                           */
+#define TIMER21_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER21 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER21_CNT_CNT_Pos               (0UL)                     /*!< TIMER21 CNT: CNT (Bit 0)                              */
+#define TIMER21_CNT_CNT_Msk               (0xffffffffUL)            /*!< TIMER21 CNT: CNT (Bitfield-Mask: 0xffffffff)          */
+/* ======================================================  TIMER21_CR  ======================================================= */
+#define TIMER21_TIMER21_CR_T2nEN_Pos      (15UL)                    /*!< TIMER21 TIMER21_CR: T2nEN (Bit 15)                    */
+#define TIMER21_TIMER21_CR_T2nEN_Msk      (0x8000UL)                /*!< TIMER21 TIMER21_CR: T2nEN (Bitfield-Mask: 0x01)       */
+#define TIMER21_TIMER21_CR_T2nCLK_Pos     (14UL)                    /*!< TIMER21 TIMER21_CR: T2nCLK (Bit 14)                   */
+#define TIMER21_TIMER21_CR_T2nCLK_Msk     (0x4000UL)                /*!< TIMER21 TIMER21_CR: T2nCLK (Bitfield-Mask: 0x01)      */
+#define TIMER21_TIMER21_CR_T2nMS_Pos      (12UL)                    /*!< TIMER21 TIMER21_CR: T2nMS (Bit 12)                    */
+#define TIMER21_TIMER21_CR_T2nMS_Msk      (0x3000UL)                /*!< TIMER21 TIMER21_CR: T2nMS (Bitfield-Mask: 0x03)       */
+#define TIMER21_TIMER21_CR_T2nECE_Pos     (11UL)                    /*!< TIMER21 TIMER21_CR: T2nECE (Bit 11)                   */
+#define TIMER21_TIMER21_CR_T2nECE_Msk     (0x800UL)                 /*!< TIMER21 TIMER21_CR: T2nECE (Bitfield-Mask: 0x01)      */
+#define TIMER21_TIMER21_CR_T2nOPOL_Pos    (8UL)                     /*!< TIMER21 TIMER21_CR: T2nOPOL (Bit 8)                   */
+#define TIMER21_TIMER21_CR_T2nOPOL_Msk    (0x100UL)                 /*!< TIMER21 TIMER21_CR: T2nOPOL (Bitfield-Mask: 0x01)     */
+#define TIMER21_TIMER21_CR_T2nCPOL_Pos    (6UL)                     /*!< TIMER21 TIMER21_CR: T2nCPOL (Bit 6)                   */
+#define TIMER21_TIMER21_CR_T2nCPOL_Msk    (0xc0UL)                  /*!< TIMER21 TIMER21_CR: T2nCPOL (Bitfield-Mask: 0x03)     */
+#define TIMER21_TIMER21_CR_T2nMIEN_Pos    (5UL)                     /*!< TIMER21 TIMER21_CR: T2nMIEN (Bit 5)                   */
+#define TIMER21_TIMER21_CR_T2nMIEN_Msk    (0x20UL)                  /*!< TIMER21 TIMER21_CR: T2nMIEN (Bitfield-Mask: 0x01)     */
+#define TIMER21_TIMER21_CR_T2nCIEN_Pos    (4UL)                     /*!< TIMER21 TIMER21_CR: T2nCIEN (Bit 4)                   */
+#define TIMER21_TIMER21_CR_T2nCIEN_Msk    (0x10UL)                  /*!< TIMER21 TIMER21_CR: T2nCIEN (Bitfield-Mask: 0x01)     */
+#define TIMER21_TIMER21_CR_T2nMIFLAG_Pos  (3UL)                     /*!< TIMER21 TIMER21_CR: T2nMIFLAG (Bit 3)                 */
+#define TIMER21_TIMER21_CR_T2nMIFLAG_Msk  (0x8UL)                   /*!< TIMER21 TIMER21_CR: T2nMIFLAG (Bitfield-Mask: 0x01)   */
+#define TIMER21_TIMER21_CR_T2nCIFLAG_Pos  (2UL)                     /*!< TIMER21 TIMER21_CR: T2nCIFLAG (Bit 2)                 */
+#define TIMER21_TIMER21_CR_T2nCIFLAG_Msk  (0x4UL)                   /*!< TIMER21 TIMER21_CR: T2nCIFLAG (Bitfield-Mask: 0x01)   */
+#define TIMER21_TIMER21_CR_T2nPAU_Pos     (1UL)                     /*!< TIMER21 TIMER21_CR: T2nPAU (Bit 1)                    */
+#define TIMER21_TIMER21_CR_T2nPAU_Msk     (0x2UL)                   /*!< TIMER21 TIMER21_CR: T2nPAU (Bitfield-Mask: 0x01)      */
+#define TIMER21_TIMER21_CR_T2nCLR_Pos     (0UL)                     /*!< TIMER21 TIMER21_CR: T2nCLR (Bit 0)                    */
+#define TIMER21_TIMER21_CR_T2nCLR_Msk     (0x1UL)                   /*!< TIMER21 TIMER21_CR: T2nCLR (Bitfield-Mask: 0x01)      */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER3n                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER3n_CR_T3nEN_Pos              (15UL)                    /*!< TIMER3n CR: T3nEN (Bit 15)                            */
+#define TIMER3n_CR_T3nEN_Msk              (0x8000UL)                /*!< TIMER3n CR: T3nEN (Bitfield-Mask: 0x01)               */
+#define TIMER3n_CR_T3nCLK_Pos             (14UL)                    /*!< TIMER3n CR: T3nCLK (Bit 14)                           */
+#define TIMER3n_CR_T3nCLK_Msk             (0x4000UL)                /*!< TIMER3n CR: T3nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER3n_CR_T3nMS_Pos              (12UL)                    /*!< TIMER3n CR: T3nMS (Bit 12)                            */
+#define TIMER3n_CR_T3nMS_Msk              (0x3000UL)                /*!< TIMER3n CR: T3nMS (Bitfield-Mask: 0x03)               */
+#define TIMER3n_CR_T3nECE_Pos             (11UL)                    /*!< TIMER3n CR: T3nECE (Bit 11)                           */
+#define TIMER3n_CR_T3nECE_Msk             (0x800UL)                 /*!< TIMER3n CR: T3nECE (Bitfield-Mask: 0x01)              */
+#define TIMER3n_CR_FORCA_Pos              (10UL)                    /*!< TIMER3n CR: FORCA (Bit 10)                            */
+#define TIMER3n_CR_FORCA_Msk              (0x400UL)                 /*!< TIMER3n CR: FORCA (Bitfield-Mask: 0x01)               */
+#define TIMER3n_CR_DLYEN_Pos              (9UL)                     /*!< TIMER3n CR: DLYEN (Bit 9)                             */
+#define TIMER3n_CR_DLYEN_Msk              (0x200UL)                 /*!< TIMER3n CR: DLYEN (Bitfield-Mask: 0x01)               */
+#define TIMER3n_CR_DLYPOS_Pos             (8UL)                     /*!< TIMER3n CR: DLYPOS (Bit 8)                            */
+#define TIMER3n_CR_DLYPOS_Msk             (0x100UL)                 /*!< TIMER3n CR: DLYPOS (Bitfield-Mask: 0x01)              */
+#define TIMER3n_CR_T3nCPOL_Pos            (6UL)                     /*!< TIMER3n CR: T3nCPOL (Bit 6)                           */
+#define TIMER3n_CR_T3nCPOL_Msk            (0xc0UL)                  /*!< TIMER3n CR: T3nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER3n_CR_UPDT_Pos               (4UL)                     /*!< TIMER3n CR: UPDT (Bit 4)                              */
+#define TIMER3n_CR_UPDT_Msk               (0x30UL)                  /*!< TIMER3n CR: UPDT (Bitfield-Mask: 0x03)                */
+#define TIMER3n_CR_PMOC_Pos               (1UL)                     /*!< TIMER3n CR: PMOC (Bit 1)                              */
+#define TIMER3n_CR_PMOC_Msk               (0xeUL)                   /*!< TIMER3n CR: PMOC (Bitfield-Mask: 0x07)                */
+#define TIMER3n_CR_T3nCLR_Pos             (0UL)                     /*!< TIMER3n CR: T3nCLR (Bit 0)                            */
+#define TIMER3n_CR_T3nCLR_Msk             (0x1UL)                   /*!< TIMER3n CR: T3nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  PDR  ========================================================== */
+#define TIMER3n_PDR_PDATA_Pos             (0UL)                     /*!< TIMER3n PDR: PDATA (Bit 0)                            */
+#define TIMER3n_PDR_PDATA_Msk             (0xffffUL)                /*!< TIMER3n PDR: PDATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER3n_ADR_ADATA_Pos             (0UL)                     /*!< TIMER3n ADR: ADATA (Bit 0)                            */
+#define TIMER3n_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER3n ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER3n_BDR_BDATA_Pos             (0UL)                     /*!< TIMER3n BDR: BDATA (Bit 0)                            */
+#define TIMER3n_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER3n BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  CDR  ========================================================== */
+#define TIMER3n_CDR_CDATA_Pos             (0UL)                     /*!< TIMER3n CDR: CDATA (Bit 0)                            */
+#define TIMER3n_CDR_CDATA_Msk             (0xffffUL)                /*!< TIMER3n CDR: CDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER3n_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER3n CAPDR: CAPD (Bit 0)                           */
+#define TIMER3n_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER3n CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER3n_PREDR_PRED_Pos            (0UL)                     /*!< TIMER3n PREDR: PRED (Bit 0)                           */
+#define TIMER3n_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER3n PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER3n_CNT_CNT_Pos               (0UL)                     /*!< TIMER3n CNT: CNT (Bit 0)                              */
+#define TIMER3n_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER3n CNT: CNT (Bitfield-Mask: 0xffff)              */
+/* =========================================================  OUTCR  ========================================================= */
+#define TIMER3n_OUTCR_WTIDKY_Pos          (16UL)                    /*!< TIMER3n OUTCR: WTIDKY (Bit 16)                        */
+#define TIMER3n_OUTCR_WTIDKY_Msk          (0xffff0000UL)            /*!< TIMER3n OUTCR: WTIDKY (Bitfield-Mask: 0xffff)         */
+#define TIMER3n_OUTCR_POLB_Pos            (15UL)                    /*!< TIMER3n OUTCR: POLB (Bit 15)                          */
+#define TIMER3n_OUTCR_POLB_Msk            (0x8000UL)                /*!< TIMER3n OUTCR: POLB (Bitfield-Mask: 0x01)             */
+#define TIMER3n_OUTCR_POLA_Pos            (14UL)                    /*!< TIMER3n OUTCR: POLA (Bit 14)                          */
+#define TIMER3n_OUTCR_POLA_Msk            (0x4000UL)                /*!< TIMER3n OUTCR: POLA (Bitfield-Mask: 0x01)             */
+#define TIMER3n_OUTCR_PABOE_Pos           (13UL)                    /*!< TIMER3n OUTCR: PABOE (Bit 13)                         */
+#define TIMER3n_OUTCR_PABOE_Msk           (0x2000UL)                /*!< TIMER3n OUTCR: PABOE (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_PBBOE_Pos           (12UL)                    /*!< TIMER3n OUTCR: PBBOE (Bit 12)                         */
+#define TIMER3n_OUTCR_PBBOE_Msk           (0x1000UL)                /*!< TIMER3n OUTCR: PBBOE (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_PCBOE_Pos           (11UL)                    /*!< TIMER3n OUTCR: PCBOE (Bit 11)                         */
+#define TIMER3n_OUTCR_PCBOE_Msk           (0x800UL)                 /*!< TIMER3n OUTCR: PCBOE (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_PAAOE_Pos           (10UL)                    /*!< TIMER3n OUTCR: PAAOE (Bit 10)                         */
+#define TIMER3n_OUTCR_PAAOE_Msk           (0x400UL)                 /*!< TIMER3n OUTCR: PAAOE (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_PBAOE_Pos           (9UL)                     /*!< TIMER3n OUTCR: PBAOE (Bit 9)                          */
+#define TIMER3n_OUTCR_PBAOE_Msk           (0x200UL)                 /*!< TIMER3n OUTCR: PBAOE (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_PCAOE_Pos           (8UL)                     /*!< TIMER3n OUTCR: PCAOE (Bit 8)                          */
+#define TIMER3n_OUTCR_PCAOE_Msk           (0x100UL)                 /*!< TIMER3n OUTCR: PCAOE (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_LVLAB_Pos           (6UL)                     /*!< TIMER3n OUTCR: LVLAB (Bit 6)                          */
+#define TIMER3n_OUTCR_LVLAB_Msk           (0x40UL)                  /*!< TIMER3n OUTCR: LVLAB (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_LVLBB_Pos           (5UL)                     /*!< TIMER3n OUTCR: LVLBB (Bit 5)                          */
+#define TIMER3n_OUTCR_LVLBB_Msk           (0x20UL)                  /*!< TIMER3n OUTCR: LVLBB (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_LVLCB_Pos           (4UL)                     /*!< TIMER3n OUTCR: LVLCB (Bit 4)                          */
+#define TIMER3n_OUTCR_LVLCB_Msk           (0x10UL)                  /*!< TIMER3n OUTCR: LVLCB (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_LVLAA_Pos           (2UL)                     /*!< TIMER3n OUTCR: LVLAA (Bit 2)                          */
+#define TIMER3n_OUTCR_LVLAA_Msk           (0x4UL)                   /*!< TIMER3n OUTCR: LVLAA (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_LVLBA_Pos           (1UL)                     /*!< TIMER3n OUTCR: LVLBA (Bit 1)                          */
+#define TIMER3n_OUTCR_LVLBA_Msk           (0x2UL)                   /*!< TIMER3n OUTCR: LVLBA (Bitfield-Mask: 0x01)            */
+#define TIMER3n_OUTCR_LVLCA_Pos           (0UL)                     /*!< TIMER3n OUTCR: LVLCA (Bit 0)                          */
+#define TIMER3n_OUTCR_LVLCA_Msk           (0x1UL)                   /*!< TIMER3n OUTCR: LVLCA (Bitfield-Mask: 0x01)            */
+/* ==========================================================  DLY  ========================================================== */
+#define TIMER3n_DLY_DLY_Pos               (0UL)                     /*!< TIMER3n DLY: DLY (Bit 0)                              */
+#define TIMER3n_DLY_DLY_Msk               (0x3ffUL)                 /*!< TIMER3n DLY: DLY (Bitfield-Mask: 0x3ff)               */
+/* =========================================================  INTCR  ========================================================= */
+#define TIMER3n_INTCR_HIZIEN_Pos          (6UL)                     /*!< TIMER3n INTCR: HIZIEN (Bit 6)                         */
+#define TIMER3n_INTCR_HIZIEN_Msk          (0x40UL)                  /*!< TIMER3n INTCR: HIZIEN (Bitfield-Mask: 0x01)           */
+#define TIMER3n_INTCR_T3nCIEN_Pos         (5UL)                     /*!< TIMER3n INTCR: T3nCIEN (Bit 5)                        */
+#define TIMER3n_INTCR_T3nCIEN_Msk         (0x20UL)                  /*!< TIMER3n INTCR: T3nCIEN (Bitfield-Mask: 0x01)          */
+#define TIMER3n_INTCR_T3nBTIEN_Pos        (4UL)                     /*!< TIMER3n INTCR: T3nBTIEN (Bit 4)                       */
+#define TIMER3n_INTCR_T3nBTIEN_Msk        (0x10UL)                  /*!< TIMER3n INTCR: T3nBTIEN (Bitfield-Mask: 0x01)         */
+#define TIMER3n_INTCR_T3nPMIEN_Pos        (3UL)                     /*!< TIMER3n INTCR: T3nPMIEN (Bit 3)                       */
+#define TIMER3n_INTCR_T3nPMIEN_Msk        (0x8UL)                   /*!< TIMER3n INTCR: T3nPMIEN (Bitfield-Mask: 0x01)         */
+#define TIMER3n_INTCR_T3nAMIEN_Pos        (2UL)                     /*!< TIMER3n INTCR: T3nAMIEN (Bit 2)                       */
+#define TIMER3n_INTCR_T3nAMIEN_Msk        (0x4UL)                   /*!< TIMER3n INTCR: T3nAMIEN (Bitfield-Mask: 0x01)         */
+#define TIMER3n_INTCR_T3nBMIEN_Pos        (1UL)                     /*!< TIMER3n INTCR: T3nBMIEN (Bit 1)                       */
+#define TIMER3n_INTCR_T3nBMIEN_Msk        (0x2UL)                   /*!< TIMER3n INTCR: T3nBMIEN (Bitfield-Mask: 0x01)         */
+#define TIMER3n_INTCR_T3nCMIEN_Pos        (0UL)                     /*!< TIMER3n INTCR: T3nCMIEN (Bit 0)                       */
+#define TIMER3n_INTCR_T3nCMIEN_Msk        (0x1UL)                   /*!< TIMER3n INTCR: T3nCMIEN (Bitfield-Mask: 0x01)         */
+/* ========================================================  INTFLAG  ======================================================== */
+#define TIMER3n_INTFLAG_HIZIFLAG_Pos      (6UL)                     /*!< TIMER3n INTFLAG: HIZIFLAG (Bit 6)                     */
+#define TIMER3n_INTFLAG_HIZIFLAG_Msk      (0x40UL)                  /*!< TIMER3n INTFLAG: HIZIFLAG (Bitfield-Mask: 0x01)       */
+#define TIMER3n_INTFLAG_T3nCIFLAG_Pos     (5UL)                     /*!< TIMER3n INTFLAG: T3nCIFLAG (Bit 5)                    */
+#define TIMER3n_INTFLAG_T3nCIFLAG_Msk     (0x20UL)                  /*!< TIMER3n INTFLAG: T3nCIFLAG (Bitfield-Mask: 0x01)      */
+#define TIMER3n_INTFLAG_T3nBTIFLAG_Pos    (4UL)                     /*!< TIMER3n INTFLAG: T3nBTIFLAG (Bit 4)                   */
+#define TIMER3n_INTFLAG_T3nBTIFLAG_Msk    (0x10UL)                  /*!< TIMER3n INTFLAG: T3nBTIFLAG (Bitfield-Mask: 0x01)     */
+#define TIMER3n_INTFLAG_T3nPMIFLAG_Pos    (3UL)                     /*!< TIMER3n INTFLAG: T3nPMIFLAG (Bit 3)                   */
+#define TIMER3n_INTFLAG_T3nPMIFLAG_Msk    (0x8UL)                   /*!< TIMER3n INTFLAG: T3nPMIFLAG (Bitfield-Mask: 0x01)     */
+#define TIMER3n_INTFLAG_T3nAMIFLAG_Pos    (2UL)                     /*!< TIMER3n INTFLAG: T3nAMIFLAG (Bit 2)                   */
+#define TIMER3n_INTFLAG_T3nAMIFLAG_Msk    (0x4UL)                   /*!< TIMER3n INTFLAG: T3nAMIFLAG (Bitfield-Mask: 0x01)     */
+#define TIMER3n_INTFLAG_T3nBMIFLAG_Pos    (1UL)                     /*!< TIMER3n INTFLAG: T3nBMIFLAG (Bit 1)                   */
+#define TIMER3n_INTFLAG_T3nBMIFLAG_Msk    (0x2UL)                   /*!< TIMER3n INTFLAG: T3nBMIFLAG (Bitfield-Mask: 0x01)     */
+#define TIMER3n_INTFLAG_T3nCMIFLAG_Pos    (0UL)                     /*!< TIMER3n INTFLAG: T3nCMIFLAG (Bit 0)                   */
+#define TIMER3n_INTFLAG_T3nCMIFLAG_Msk    (0x1UL)                   /*!< TIMER3n INTFLAG: T3nCMIFLAG (Bitfield-Mask: 0x01)     */
+/* =========================================================  HIZCR  ========================================================= */
+#define TIMER3n_HIZCR_HIZEN_Pos           (7UL)                     /*!< TIMER3n HIZCR: HIZEN (Bit 7)                          */
+#define TIMER3n_HIZCR_HIZEN_Msk           (0x80UL)                  /*!< TIMER3n HIZCR: HIZEN (Bitfield-Mask: 0x01)            */
+#define TIMER3n_HIZCR_HIZSW_Pos           (4UL)                     /*!< TIMER3n HIZCR: HIZSW (Bit 4)                          */
+#define TIMER3n_HIZCR_HIZSW_Msk           (0x10UL)                  /*!< TIMER3n HIZCR: HIZSW (Bitfield-Mask: 0x01)            */
+#define TIMER3n_HIZCR_HEDGE_Pos           (2UL)                     /*!< TIMER3n HIZCR: HEDGE (Bit 2)                          */
+#define TIMER3n_HIZCR_HEDGE_Msk           (0x4UL)                   /*!< TIMER3n HIZCR: HEDGE (Bitfield-Mask: 0x01)            */
+#define TIMER3n_HIZCR_HIZSTA_Pos          (1UL)                     /*!< TIMER3n HIZCR: HIZSTA (Bit 1)                         */
+#define TIMER3n_HIZCR_HIZSTA_Msk          (0x2UL)                   /*!< TIMER3n HIZCR: HIZSTA (Bitfield-Mask: 0x01)           */
+#define TIMER3n_HIZCR_HIZCLR_Pos          (0UL)                     /*!< TIMER3n HIZCR: HIZCLR (Bit 0)                         */
+#define TIMER3n_HIZCR_HIZCLR_Msk          (0x1UL)                   /*!< TIMER3n HIZCR: HIZCLR (Bitfield-Mask: 0x01)           */
+/* =========================================================  ADTCR  ========================================================= */
+#define TIMER3n_ADTCR_T3nBTTG_Pos         (4UL)                     /*!< TIMER3n ADTCR: T3nBTTG (Bit 4)                        */
+#define TIMER3n_ADTCR_T3nBTTG_Msk         (0x10UL)                  /*!< TIMER3n ADTCR: T3nBTTG (Bitfield-Mask: 0x01)          */
+#define TIMER3n_ADTCR_T3nPMTG_Pos         (3UL)                     /*!< TIMER3n ADTCR: T3nPMTG (Bit 3)                        */
+#define TIMER3n_ADTCR_T3nPMTG_Msk         (0x8UL)                   /*!< TIMER3n ADTCR: T3nPMTG (Bitfield-Mask: 0x01)          */
+#define TIMER3n_ADTCR_T3nAMTG_Pos         (2UL)                     /*!< TIMER3n ADTCR: T3nAMTG (Bit 2)                        */
+#define TIMER3n_ADTCR_T3nAMTG_Msk         (0x4UL)                   /*!< TIMER3n ADTCR: T3nAMTG (Bitfield-Mask: 0x01)          */
+#define TIMER3n_ADTCR_T3nBMTG_Pos         (1UL)                     /*!< TIMER3n ADTCR: T3nBMTG (Bit 1)                        */
+#define TIMER3n_ADTCR_T3nBMTG_Msk         (0x2UL)                   /*!< TIMER3n ADTCR: T3nBMTG (Bitfield-Mask: 0x01)          */
+#define TIMER3n_ADTCR_T3nCMTG_Pos         (0UL)                     /*!< TIMER3n ADTCR: T3nCMTG (Bit 0)                        */
+#define TIMER3n_ADTCR_T3nCMTG_Msk         (0x1UL)                   /*!< TIMER3n ADTCR: T3nCMTG (Bitfield-Mask: 0x01)          */
+/* =========================================================  ADTDR  ========================================================= */
+#define TIMER3n_ADTDR_ADTDATA_Pos         (0UL)                     /*!< TIMER3n ADTDR: ADTDATA (Bit 0)                        */
+#define TIMER3n_ADTDR_ADTDATA_Msk         (0x3fffUL)                /*!< TIMER3n ADTDR: ADTDATA (Bitfield-Mask: 0x3fff)        */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER30                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define TIMER30_CR_T3nEN_Pos              (15UL)                    /*!< TIMER30 CR: T3nEN (Bit 15)                            */
+#define TIMER30_CR_T3nEN_Msk              (0x8000UL)                /*!< TIMER30 CR: T3nEN (Bitfield-Mask: 0x01)               */
+#define TIMER30_CR_T3nCLK_Pos             (14UL)                    /*!< TIMER30 CR: T3nCLK (Bit 14)                           */
+#define TIMER30_CR_T3nCLK_Msk             (0x4000UL)                /*!< TIMER30 CR: T3nCLK (Bitfield-Mask: 0x01)              */
+#define TIMER30_CR_T3nMS_Pos              (12UL)                    /*!< TIMER30 CR: T3nMS (Bit 12)                            */
+#define TIMER30_CR_T3nMS_Msk              (0x3000UL)                /*!< TIMER30 CR: T3nMS (Bitfield-Mask: 0x03)               */
+#define TIMER30_CR_T3nECE_Pos             (11UL)                    /*!< TIMER30 CR: T3nECE (Bit 11)                           */
+#define TIMER30_CR_T3nECE_Msk             (0x800UL)                 /*!< TIMER30 CR: T3nECE (Bitfield-Mask: 0x01)              */
+#define TIMER30_CR_FORCA_Pos              (10UL)                    /*!< TIMER30 CR: FORCA (Bit 10)                            */
+#define TIMER30_CR_FORCA_Msk              (0x400UL)                 /*!< TIMER30 CR: FORCA (Bitfield-Mask: 0x01)               */
+#define TIMER30_CR_DLYEN_Pos              (9UL)                     /*!< TIMER30 CR: DLYEN (Bit 9)                             */
+#define TIMER30_CR_DLYEN_Msk              (0x200UL)                 /*!< TIMER30 CR: DLYEN (Bitfield-Mask: 0x01)               */
+#define TIMER30_CR_DLYPOS_Pos             (8UL)                     /*!< TIMER30 CR: DLYPOS (Bit 8)                            */
+#define TIMER30_CR_DLYPOS_Msk             (0x100UL)                 /*!< TIMER30 CR: DLYPOS (Bitfield-Mask: 0x01)              */
+#define TIMER30_CR_T3nCPOL_Pos            (6UL)                     /*!< TIMER30 CR: T3nCPOL (Bit 6)                           */
+#define TIMER30_CR_T3nCPOL_Msk            (0xc0UL)                  /*!< TIMER30 CR: T3nCPOL (Bitfield-Mask: 0x03)             */
+#define TIMER30_CR_UPDT_Pos               (4UL)                     /*!< TIMER30 CR: UPDT (Bit 4)                              */
+#define TIMER30_CR_UPDT_Msk               (0x30UL)                  /*!< TIMER30 CR: UPDT (Bitfield-Mask: 0x03)                */
+#define TIMER30_CR_PMOC_Pos               (1UL)                     /*!< TIMER30 CR: PMOC (Bit 1)                              */
+#define TIMER30_CR_PMOC_Msk               (0xeUL)                   /*!< TIMER30 CR: PMOC (Bitfield-Mask: 0x07)                */
+#define TIMER30_CR_T3nCLR_Pos             (0UL)                     /*!< TIMER30 CR: T3nCLR (Bit 0)                            */
+#define TIMER30_CR_T3nCLR_Msk             (0x1UL)                   /*!< TIMER30 CR: T3nCLR (Bitfield-Mask: 0x01)              */
+/* ==========================================================  PDR  ========================================================== */
+#define TIMER30_PDR_PDATA_Pos             (0UL)                     /*!< TIMER30 PDR: PDATA (Bit 0)                            */
+#define TIMER30_PDR_PDATA_Msk             (0xffffUL)                /*!< TIMER30 PDR: PDATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  ADR  ========================================================== */
+#define TIMER30_ADR_ADATA_Pos             (0UL)                     /*!< TIMER30 ADR: ADATA (Bit 0)                            */
+#define TIMER30_ADR_ADATA_Msk             (0xffffUL)                /*!< TIMER30 ADR: ADATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  BDR  ========================================================== */
+#define TIMER30_BDR_BDATA_Pos             (0UL)                     /*!< TIMER30 BDR: BDATA (Bit 0)                            */
+#define TIMER30_BDR_BDATA_Msk             (0xffffUL)                /*!< TIMER30 BDR: BDATA (Bitfield-Mask: 0xffff)            */
+/* ==========================================================  CDR  ========================================================== */
+#define TIMER30_CDR_CDATA_Pos             (0UL)                     /*!< TIMER30 CDR: CDATA (Bit 0)                            */
+#define TIMER30_CDR_CDATA_Msk             (0xffffUL)                /*!< TIMER30 CDR: CDATA (Bitfield-Mask: 0xffff)            */
+/* =========================================================  CAPDR  ========================================================= */
+#define TIMER30_CAPDR_CAPD_Pos            (0UL)                     /*!< TIMER30 CAPDR: CAPD (Bit 0)                           */
+#define TIMER30_CAPDR_CAPD_Msk            (0xffffUL)                /*!< TIMER30 CAPDR: CAPD (Bitfield-Mask: 0xffff)           */
+/* =========================================================  PREDR  ========================================================= */
+#define TIMER30_PREDR_PRED_Pos            (0UL)                     /*!< TIMER30 PREDR: PRED (Bit 0)                           */
+#define TIMER30_PREDR_PRED_Msk            (0xfffUL)                 /*!< TIMER30 PREDR: PRED (Bitfield-Mask: 0xfff)            */
+/* ==========================================================  CNT  ========================================================== */
+#define TIMER30_CNT_CNT_Pos               (0UL)                     /*!< TIMER30 CNT: CNT (Bit 0)                              */
+#define TIMER30_CNT_CNT_Msk               (0xffffUL)                /*!< TIMER30 CNT: CNT (Bitfield-Mask: 0xffff)              */
+/* =========================================================  OUTCR  ========================================================= */
+#define TIMER30_OUTCR_WTIDKY_Pos          (16UL)                    /*!< TIMER30 OUTCR: WTIDKY (Bit 16)                        */
+#define TIMER30_OUTCR_WTIDKY_Msk          (0xffff0000UL)            /*!< TIMER30 OUTCR: WTIDKY (Bitfield-Mask: 0xffff)         */
+#define TIMER30_OUTCR_POLB_Pos            (15UL)                    /*!< TIMER30 OUTCR: POLB (Bit 15)                          */
+#define TIMER30_OUTCR_POLB_Msk            (0x8000UL)                /*!< TIMER30 OUTCR: POLB (Bitfield-Mask: 0x01)             */
+#define TIMER30_OUTCR_POLA_Pos            (14UL)                    /*!< TIMER30 OUTCR: POLA (Bit 14)                          */
+#define TIMER30_OUTCR_POLA_Msk            (0x4000UL)                /*!< TIMER30 OUTCR: POLA (Bitfield-Mask: 0x01)             */
+#define TIMER30_OUTCR_PABOE_Pos           (13UL)                    /*!< TIMER30 OUTCR: PABOE (Bit 13)                         */
+#define TIMER30_OUTCR_PABOE_Msk           (0x2000UL)                /*!< TIMER30 OUTCR: PABOE (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_PBBOE_Pos           (12UL)                    /*!< TIMER30 OUTCR: PBBOE (Bit 12)                         */
+#define TIMER30_OUTCR_PBBOE_Msk           (0x1000UL)                /*!< TIMER30 OUTCR: PBBOE (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_PCBOE_Pos           (11UL)                    /*!< TIMER30 OUTCR: PCBOE (Bit 11)                         */
+#define TIMER30_OUTCR_PCBOE_Msk           (0x800UL)                 /*!< TIMER30 OUTCR: PCBOE (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_PAAOE_Pos           (10UL)                    /*!< TIMER30 OUTCR: PAAOE (Bit 10)                         */
+#define TIMER30_OUTCR_PAAOE_Msk           (0x400UL)                 /*!< TIMER30 OUTCR: PAAOE (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_PBAOE_Pos           (9UL)                     /*!< TIMER30 OUTCR: PBAOE (Bit 9)                          */
+#define TIMER30_OUTCR_PBAOE_Msk           (0x200UL)                 /*!< TIMER30 OUTCR: PBAOE (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_PCAOE_Pos           (8UL)                     /*!< TIMER30 OUTCR: PCAOE (Bit 8)                          */
+#define TIMER30_OUTCR_PCAOE_Msk           (0x100UL)                 /*!< TIMER30 OUTCR: PCAOE (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_LVLAB_Pos           (6UL)                     /*!< TIMER30 OUTCR: LVLAB (Bit 6)                          */
+#define TIMER30_OUTCR_LVLAB_Msk           (0x40UL)                  /*!< TIMER30 OUTCR: LVLAB (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_LVLBB_Pos           (5UL)                     /*!< TIMER30 OUTCR: LVLBB (Bit 5)                          */
+#define TIMER30_OUTCR_LVLBB_Msk           (0x20UL)                  /*!< TIMER30 OUTCR: LVLBB (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_LVLCB_Pos           (4UL)                     /*!< TIMER30 OUTCR: LVLCB (Bit 4)                          */
+#define TIMER30_OUTCR_LVLCB_Msk           (0x10UL)                  /*!< TIMER30 OUTCR: LVLCB (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_LVLAA_Pos           (2UL)                     /*!< TIMER30 OUTCR: LVLAA (Bit 2)                          */
+#define TIMER30_OUTCR_LVLAA_Msk           (0x4UL)                   /*!< TIMER30 OUTCR: LVLAA (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_LVLBA_Pos           (1UL)                     /*!< TIMER30 OUTCR: LVLBA (Bit 1)                          */
+#define TIMER30_OUTCR_LVLBA_Msk           (0x2UL)                   /*!< TIMER30 OUTCR: LVLBA (Bitfield-Mask: 0x01)            */
+#define TIMER30_OUTCR_LVLCA_Pos           (0UL)                     /*!< TIMER30 OUTCR: LVLCA (Bit 0)                          */
+#define TIMER30_OUTCR_LVLCA_Msk           (0x1UL)                   /*!< TIMER30 OUTCR: LVLCA (Bitfield-Mask: 0x01)            */
+/* ==========================================================  DLY  ========================================================== */
+#define TIMER30_DLY_DLY_Pos               (0UL)                     /*!< TIMER30 DLY: DLY (Bit 0)                              */
+#define TIMER30_DLY_DLY_Msk               (0x3ffUL)                 /*!< TIMER30 DLY: DLY (Bitfield-Mask: 0x3ff)               */
+/* =========================================================  INTCR  ========================================================= */
+#define TIMER30_INTCR_HIZIEN_Pos          (6UL)                     /*!< TIMER30 INTCR: HIZIEN (Bit 6)                         */
+#define TIMER30_INTCR_HIZIEN_Msk          (0x40UL)                  /*!< TIMER30 INTCR: HIZIEN (Bitfield-Mask: 0x01)           */
+#define TIMER30_INTCR_T3nCIEN_Pos         (5UL)                     /*!< TIMER30 INTCR: T3nCIEN (Bit 5)                        */
+#define TIMER30_INTCR_T3nCIEN_Msk         (0x20UL)                  /*!< TIMER30 INTCR: T3nCIEN (Bitfield-Mask: 0x01)          */
+#define TIMER30_INTCR_T3nBTIEN_Pos        (4UL)                     /*!< TIMER30 INTCR: T3nBTIEN (Bit 4)                       */
+#define TIMER30_INTCR_T3nBTIEN_Msk        (0x10UL)                  /*!< TIMER30 INTCR: T3nBTIEN (Bitfield-Mask: 0x01)         */
+#define TIMER30_INTCR_T3nPMIEN_Pos        (3UL)                     /*!< TIMER30 INTCR: T3nPMIEN (Bit 3)                       */
+#define TIMER30_INTCR_T3nPMIEN_Msk        (0x8UL)                   /*!< TIMER30 INTCR: T3nPMIEN (Bitfield-Mask: 0x01)         */
+#define TIMER30_INTCR_T3nAMIEN_Pos        (2UL)                     /*!< TIMER30 INTCR: T3nAMIEN (Bit 2)                       */
+#define TIMER30_INTCR_T3nAMIEN_Msk        (0x4UL)                   /*!< TIMER30 INTCR: T3nAMIEN (Bitfield-Mask: 0x01)         */
+#define TIMER30_INTCR_T3nBMIEN_Pos        (1UL)                     /*!< TIMER30 INTCR: T3nBMIEN (Bit 1)                       */
+#define TIMER30_INTCR_T3nBMIEN_Msk        (0x2UL)                   /*!< TIMER30 INTCR: T3nBMIEN (Bitfield-Mask: 0x01)         */
+#define TIMER30_INTCR_T3nCMIEN_Pos        (0UL)                     /*!< TIMER30 INTCR: T3nCMIEN (Bit 0)                       */
+#define TIMER30_INTCR_T3nCMIEN_Msk        (0x1UL)                   /*!< TIMER30 INTCR: T3nCMIEN (Bitfield-Mask: 0x01)         */
+/* ========================================================  INTFLAG  ======================================================== */
+#define TIMER30_INTFLAG_HIZIFLAG_Pos      (6UL)                     /*!< TIMER30 INTFLAG: HIZIFLAG (Bit 6)                     */
+#define TIMER30_INTFLAG_HIZIFLAG_Msk      (0x40UL)                  /*!< TIMER30 INTFLAG: HIZIFLAG (Bitfield-Mask: 0x01)       */
+#define TIMER30_INTFLAG_T3nCIFLAG_Pos     (5UL)                     /*!< TIMER30 INTFLAG: T3nCIFLAG (Bit 5)                    */
+#define TIMER30_INTFLAG_T3nCIFLAG_Msk     (0x20UL)                  /*!< TIMER30 INTFLAG: T3nCIFLAG (Bitfield-Mask: 0x01)      */
+#define TIMER30_INTFLAG_T3nBTIFLAG_Pos    (4UL)                     /*!< TIMER30 INTFLAG: T3nBTIFLAG (Bit 4)                   */
+#define TIMER30_INTFLAG_T3nBTIFLAG_Msk    (0x10UL)                  /*!< TIMER30 INTFLAG: T3nBTIFLAG (Bitfield-Mask: 0x01)     */
+#define TIMER30_INTFLAG_T3nPMIFLAG_Pos    (3UL)                     /*!< TIMER30 INTFLAG: T3nPMIFLAG (Bit 3)                   */
+#define TIMER30_INTFLAG_T3nPMIFLAG_Msk    (0x8UL)                   /*!< TIMER30 INTFLAG: T3nPMIFLAG (Bitfield-Mask: 0x01)     */
+#define TIMER30_INTFLAG_T3nAMIFLAG_Pos    (2UL)                     /*!< TIMER30 INTFLAG: T3nAMIFLAG (Bit 2)                   */
+#define TIMER30_INTFLAG_T3nAMIFLAG_Msk    (0x4UL)                   /*!< TIMER30 INTFLAG: T3nAMIFLAG (Bitfield-Mask: 0x01)     */
+#define TIMER30_INTFLAG_T3nBMIFLAG_Pos    (1UL)                     /*!< TIMER30 INTFLAG: T3nBMIFLAG (Bit 1)                   */
+#define TIMER30_INTFLAG_T3nBMIFLAG_Msk    (0x2UL)                   /*!< TIMER30 INTFLAG: T3nBMIFLAG (Bitfield-Mask: 0x01)     */
+#define TIMER30_INTFLAG_T3nCMIFLAG_Pos    (0UL)                     /*!< TIMER30 INTFLAG: T3nCMIFLAG (Bit 0)                   */
+#define TIMER30_INTFLAG_T3nCMIFLAG_Msk    (0x1UL)                   /*!< TIMER30 INTFLAG: T3nCMIFLAG (Bitfield-Mask: 0x01)     */
+/* =========================================================  HIZCR  ========================================================= */
+#define TIMER30_HIZCR_HIZEN_Pos           (7UL)                     /*!< TIMER30 HIZCR: HIZEN (Bit 7)                          */
+#define TIMER30_HIZCR_HIZEN_Msk           (0x80UL)                  /*!< TIMER30 HIZCR: HIZEN (Bitfield-Mask: 0x01)            */
+#define TIMER30_HIZCR_HIZSW_Pos           (4UL)                     /*!< TIMER30 HIZCR: HIZSW (Bit 4)                          */
+#define TIMER30_HIZCR_HIZSW_Msk           (0x10UL)                  /*!< TIMER30 HIZCR: HIZSW (Bitfield-Mask: 0x01)            */
+#define TIMER30_HIZCR_HEDGE_Pos           (2UL)                     /*!< TIMER30 HIZCR: HEDGE (Bit 2)                          */
+#define TIMER30_HIZCR_HEDGE_Msk           (0x4UL)                   /*!< TIMER30 HIZCR: HEDGE (Bitfield-Mask: 0x01)            */
+#define TIMER30_HIZCR_HIZSTA_Pos          (1UL)                     /*!< TIMER30 HIZCR: HIZSTA (Bit 1)                         */
+#define TIMER30_HIZCR_HIZSTA_Msk          (0x2UL)                   /*!< TIMER30 HIZCR: HIZSTA (Bitfield-Mask: 0x01)           */
+#define TIMER30_HIZCR_HIZCLR_Pos          (0UL)                     /*!< TIMER30 HIZCR: HIZCLR (Bit 0)                         */
+#define TIMER30_HIZCR_HIZCLR_Msk          (0x1UL)                   /*!< TIMER30 HIZCR: HIZCLR (Bitfield-Mask: 0x01)           */
+/* =========================================================  ADTCR  ========================================================= */
+#define TIMER30_ADTCR_T3nBTTG_Pos         (4UL)                     /*!< TIMER30 ADTCR: T3nBTTG (Bit 4)                        */
+#define TIMER30_ADTCR_T3nBTTG_Msk         (0x10UL)                  /*!< TIMER30 ADTCR: T3nBTTG (Bitfield-Mask: 0x01)          */
+#define TIMER30_ADTCR_T3nPMTG_Pos         (3UL)                     /*!< TIMER30 ADTCR: T3nPMTG (Bit 3)                        */
+#define TIMER30_ADTCR_T3nPMTG_Msk         (0x8UL)                   /*!< TIMER30 ADTCR: T3nPMTG (Bitfield-Mask: 0x01)          */
+#define TIMER30_ADTCR_T3nAMTG_Pos         (2UL)                     /*!< TIMER30 ADTCR: T3nAMTG (Bit 2)                        */
+#define TIMER30_ADTCR_T3nAMTG_Msk         (0x4UL)                   /*!< TIMER30 ADTCR: T3nAMTG (Bitfield-Mask: 0x01)          */
+#define TIMER30_ADTCR_T3nBMTG_Pos         (1UL)                     /*!< TIMER30 ADTCR: T3nBMTG (Bit 1)                        */
+#define TIMER30_ADTCR_T3nBMTG_Msk         (0x2UL)                   /*!< TIMER30 ADTCR: T3nBMTG (Bitfield-Mask: 0x01)          */
+#define TIMER30_ADTCR_T3nCMTG_Pos         (0UL)                     /*!< TIMER30 ADTCR: T3nCMTG (Bit 0)                        */
+#define TIMER30_ADTCR_T3nCMTG_Msk         (0x1UL)                   /*!< TIMER30 ADTCR: T3nCMTG (Bitfield-Mask: 0x01)          */
+/* =========================================================  ADTDR  ========================================================= */
+#define TIMER30_ADTDR_ADTDATA_Pos         (0UL)                     /*!< TIMER30 ADTDR: ADTDATA (Bit 0)                        */
+#define TIMER30_ADTDR_ADTDATA_Msk         (0x3fffUL)                /*!< TIMER30 ADTDR: ADTDATA (Bitfield-Mask: 0x3fff)        */
+/* =======================================================  T30_OUTCR  ======================================================= */
+#define TIMER30_T30_OUTCR_WTIDKY_Pos      (16UL)                    /*!< TIMER30 T30_OUTCR: WTIDKY (Bit 16)                    */
+#define TIMER30_T30_OUTCR_WTIDKY_Msk      (0xffff0000UL)            /*!< TIMER30 T30_OUTCR: WTIDKY (Bitfield-Mask: 0xffff)     */
+#define TIMER30_T30_OUTCR_POLB_Pos        (15UL)                    /*!< TIMER30 T30_OUTCR: POLB (Bit 15)                      */
+#define TIMER30_T30_OUTCR_POLB_Msk        (0x8000UL)                /*!< TIMER30 T30_OUTCR: POLB (Bitfield-Mask: 0x01)         */
+#define TIMER30_T30_OUTCR_POLA_Pos        (14UL)                    /*!< TIMER30 T30_OUTCR: POLA (Bit 14)                      */
+#define TIMER30_T30_OUTCR_POLA_Msk        (0x4000UL)                /*!< TIMER30 T30_OUTCR: POLA (Bitfield-Mask: 0x01)         */
+#define TIMER30_T30_OUTCR_PABOE_Pos       (13UL)                    /*!< TIMER30 T30_OUTCR: PABOE (Bit 13)                     */
+#define TIMER30_T30_OUTCR_PABOE_Msk       (0x2000UL)                /*!< TIMER30 T30_OUTCR: PABOE (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_PBBOE_Pos       (12UL)                    /*!< TIMER30 T30_OUTCR: PBBOE (Bit 12)                     */
+#define TIMER30_T30_OUTCR_PBBOE_Msk       (0x1000UL)                /*!< TIMER30 T30_OUTCR: PBBOE (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_PCBOE_Pos       (11UL)                    /*!< TIMER30 T30_OUTCR: PCBOE (Bit 11)                     */
+#define TIMER30_T30_OUTCR_PCBOE_Msk       (0x800UL)                 /*!< TIMER30 T30_OUTCR: PCBOE (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_PAAOE_Pos       (10UL)                    /*!< TIMER30 T30_OUTCR: PAAOE (Bit 10)                     */
+#define TIMER30_T30_OUTCR_PAAOE_Msk       (0x400UL)                 /*!< TIMER30 T30_OUTCR: PAAOE (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_PBAOE_Pos       (9UL)                     /*!< TIMER30 T30_OUTCR: PBAOE (Bit 9)                      */
+#define TIMER30_T30_OUTCR_PBAOE_Msk       (0x200UL)                 /*!< TIMER30 T30_OUTCR: PBAOE (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_PCAOE_Pos       (8UL)                     /*!< TIMER30 T30_OUTCR: PCAOE (Bit 8)                      */
+#define TIMER30_T30_OUTCR_PCAOE_Msk       (0x100UL)                 /*!< TIMER30 T30_OUTCR: PCAOE (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_LVLAB_Pos       (6UL)                     /*!< TIMER30 T30_OUTCR: LVLAB (Bit 6)                      */
+#define TIMER30_T30_OUTCR_LVLAB_Msk       (0x40UL)                  /*!< TIMER30 T30_OUTCR: LVLAB (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_LVLBB_Pos       (5UL)                     /*!< TIMER30 T30_OUTCR: LVLBB (Bit 5)                      */
+#define TIMER30_T30_OUTCR_LVLBB_Msk       (0x20UL)                  /*!< TIMER30 T30_OUTCR: LVLBB (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_LVLCB_Pos       (4UL)                     /*!< TIMER30 T30_OUTCR: LVLCB (Bit 4)                      */
+#define TIMER30_T30_OUTCR_LVLCB_Msk       (0x10UL)                  /*!< TIMER30 T30_OUTCR: LVLCB (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_LVLAA_Pos       (2UL)                     /*!< TIMER30 T30_OUTCR: LVLAA (Bit 2)                      */
+#define TIMER30_T30_OUTCR_LVLAA_Msk       (0x4UL)                   /*!< TIMER30 T30_OUTCR: LVLAA (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_LVLBA_Pos       (1UL)                     /*!< TIMER30 T30_OUTCR: LVLBA (Bit 1)                      */
+#define TIMER30_T30_OUTCR_LVLBA_Msk       (0x2UL)                   /*!< TIMER30 T30_OUTCR: LVLBA (Bitfield-Mask: 0x01)        */
+#define TIMER30_T30_OUTCR_LVLCA_Pos       (0UL)                     /*!< TIMER30 T30_OUTCR: LVLCA (Bit 0)                      */
+#define TIMER30_T30_OUTCR_LVLCA_Msk       (0x1UL)                   /*!< TIMER30 T30_OUTCR: LVLCA (Bitfield-Mask: 0x01)        */
+
+
+/* =========================================================================================================================== */
+/* ================                                            ADC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define ADC_CR_ADCEN_Pos                  (15UL)                    /*!< ADC CR: ADCEN (Bit 15)                                */
+#define ADC_CR_ADCEN_Msk                  (0x8000UL)                /*!< ADC CR: ADCEN (Bitfield-Mask: 0x01)                   */
+#define ADC_CR_TRIG_Pos                   (11UL)                    /*!< ADC CR: TRIG (Bit 11)                                 */
+#define ADC_CR_TRIG_Msk                   (0x3800UL)                /*!< ADC CR: TRIG (Bitfield-Mask: 0x07)                    */
+#define ADC_CR_REFSEL_Pos                 (10UL)                    /*!< ADC CR: REFSEL (Bit 10)                               */
+#define ADC_CR_REFSEL_Msk                 (0x400UL)                 /*!< ADC CR: REFSEL (Bitfield-Mask: 0x01)                  */
+#define ADC_CR_ADST_Pos                   (8UL)                     /*!< ADC CR: ADST (Bit 8)                                  */
+#define ADC_CR_ADST_Msk                   (0x100UL)                 /*!< ADC CR: ADST (Bitfield-Mask: 0x01)                    */
+#define ADC_CR_ADCIEN_Pos                 (5UL)                     /*!< ADC CR: ADCIEN (Bit 5)                                */
+#define ADC_CR_ADCIEN_Msk                 (0x20UL)                  /*!< ADC CR: ADCIEN (Bitfield-Mask: 0x01)                  */
+#define ADC_CR_ADCIFLAG_Pos               (4UL)                     /*!< ADC CR: ADCIFLAG (Bit 4)                              */
+#define ADC_CR_ADCIFLAG_Msk               (0x10UL)                  /*!< ADC CR: ADCIFLAG (Bitfield-Mask: 0x01)                */
+#define ADC_CR_ADSEL_Pos                  (0UL)                     /*!< ADC CR: ADSEL (Bit 0)                                 */
+#define ADC_CR_ADSEL_Msk                  (0xfUL)                   /*!< ADC CR: ADSEL (Bitfield-Mask: 0x0f)                   */
+/* ==========================================================  DR  =========================================================== */
+#define ADC_DR_ADDATA_Pos                 (0UL)                     /*!< ADC DR: ADDATA (Bit 0)                                */
+#define ADC_DR_ADDATA_Msk                 (0xfffUL)                 /*!< ADC DR: ADDATA (Bitfield-Mask: 0xfff)                 */
+/* =========================================================  PREDR  ========================================================= */
+#define ADC_PREDR_PRED_Pos                (0UL)                     /*!< ADC PREDR: PRED (Bit 0)                               */
+#define ADC_PREDR_PRED_Msk                (0x1fUL)                  /*!< ADC PREDR: PRED (Bitfield-Mask: 0x1f)                 */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART1n                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+#define USART1n_CR1_USTnMS_Pos            (14UL)                    /*!< USART1n CR1: USTnMS (Bit 14)                          */
+#define USART1n_CR1_USTnMS_Msk            (0xc000UL)                /*!< USART1n CR1: USTnMS (Bitfield-Mask: 0x03)             */
+#define USART1n_CR1_USTnP_Pos             (12UL)                    /*!< USART1n CR1: USTnP (Bit 12)                           */
+#define USART1n_CR1_USTnP_Msk             (0x3000UL)                /*!< USART1n CR1: USTnP (Bitfield-Mask: 0x03)              */
+#define USART1n_CR1_USTnS_Pos             (9UL)                     /*!< USART1n CR1: USTnS (Bit 9)                            */
+#define USART1n_CR1_USTnS_Msk             (0xe00UL)                 /*!< USART1n CR1: USTnS (Bitfield-Mask: 0x07)              */
+#define USART1n_CR1_ORDn_Pos              (8UL)                     /*!< USART1n CR1: ORDn (Bit 8)                             */
+#define USART1n_CR1_ORDn_Msk              (0x100UL)                 /*!< USART1n CR1: ORDn (Bitfield-Mask: 0x01)               */
+#define USART1n_CR1_CPOLn_Pos             (7UL)                     /*!< USART1n CR1: CPOLn (Bit 7)                            */
+#define USART1n_CR1_CPOLn_Msk             (0x80UL)                  /*!< USART1n CR1: CPOLn (Bitfield-Mask: 0x01)              */
+#define USART1n_CR1_CPHAn_Pos             (6UL)                     /*!< USART1n CR1: CPHAn (Bit 6)                            */
+#define USART1n_CR1_CPHAn_Msk             (0x40UL)                  /*!< USART1n CR1: CPHAn (Bitfield-Mask: 0x01)              */
+#define USART1n_CR1_DRIEn_Pos             (5UL)                     /*!< USART1n CR1: DRIEn (Bit 5)                            */
+#define USART1n_CR1_DRIEn_Msk             (0x20UL)                  /*!< USART1n CR1: DRIEn (Bitfield-Mask: 0x01)              */
+#define USART1n_CR1_TXCIEn_Pos            (4UL)                     /*!< USART1n CR1: TXCIEn (Bit 4)                           */
+#define USART1n_CR1_TXCIEn_Msk            (0x10UL)                  /*!< USART1n CR1: TXCIEn (Bitfield-Mask: 0x01)             */
+#define USART1n_CR1_RXCIEn_Pos            (3UL)                     /*!< USART1n CR1: RXCIEn (Bit 3)                           */
+#define USART1n_CR1_RXCIEn_Msk            (0x8UL)                   /*!< USART1n CR1: RXCIEn (Bitfield-Mask: 0x01)             */
+#define USART1n_CR1_WAKEIEn_Pos           (2UL)                     /*!< USART1n CR1: WAKEIEn (Bit 2)                          */
+#define USART1n_CR1_WAKEIEn_Msk           (0x4UL)                   /*!< USART1n CR1: WAKEIEn (Bitfield-Mask: 0x01)            */
+#define USART1n_CR1_TXEn_Pos              (1UL)                     /*!< USART1n CR1: TXEn (Bit 1)                             */
+#define USART1n_CR1_TXEn_Msk              (0x2UL)                   /*!< USART1n CR1: TXEn (Bitfield-Mask: 0x01)               */
+#define USART1n_CR1_RXEn_Pos              (0UL)                     /*!< USART1n CR1: RXEn (Bit 0)                             */
+#define USART1n_CR1_RXEn_Msk              (0x1UL)                   /*!< USART1n CR1: RXEn (Bitfield-Mask: 0x01)               */
+/* ==========================================================  CR2  ========================================================== */
+#define USART1n_CR2_USTnEN_Pos            (9UL)                     /*!< USART1n CR2: USTnEN (Bit 9)                           */
+#define USART1n_CR2_USTnEN_Msk            (0x200UL)                 /*!< USART1n CR2: USTnEN (Bitfield-Mask: 0x01)             */
+#define USART1n_CR2_DBLSn_Pos             (8UL)                     /*!< USART1n CR2: DBLSn (Bit 8)                            */
+#define USART1n_CR2_DBLSn_Msk             (0x100UL)                 /*!< USART1n CR2: DBLSn (Bitfield-Mask: 0x01)              */
+#define USART1n_CR2_MASTERn_Pos           (7UL)                     /*!< USART1n CR2: MASTERn (Bit 7)                          */
+#define USART1n_CR2_MASTERn_Msk           (0x80UL)                  /*!< USART1n CR2: MASTERn (Bitfield-Mask: 0x01)            */
+#define USART1n_CR2_LOOPSn_Pos            (6UL)                     /*!< USART1n CR2: LOOPSn (Bit 6)                           */
+#define USART1n_CR2_LOOPSn_Msk            (0x40UL)                  /*!< USART1n CR2: LOOPSn (Bitfield-Mask: 0x01)             */
+#define USART1n_CR2_DISSCKn_Pos           (5UL)                     /*!< USART1n CR2: DISSCKn (Bit 5)                          */
+#define USART1n_CR2_DISSCKn_Msk           (0x20UL)                  /*!< USART1n CR2: DISSCKn (Bitfield-Mask: 0x01)            */
+#define USART1n_CR2_USTnSSEN_Pos          (4UL)                     /*!< USART1n CR2: USTnSSEN (Bit 4)                         */
+#define USART1n_CR2_USTnSSEN_Msk          (0x10UL)                  /*!< USART1n CR2: USTnSSEN (Bitfield-Mask: 0x01)           */
+#define USART1n_CR2_FXCHn_Pos             (3UL)                     /*!< USART1n CR2: FXCHn (Bit 3)                            */
+#define USART1n_CR2_FXCHn_Msk             (0x8UL)                   /*!< USART1n CR2: FXCHn (Bitfield-Mask: 0x01)              */
+#define USART1n_CR2_USTnSB_Pos            (2UL)                     /*!< USART1n CR2: USTnSB (Bit 2)                           */
+#define USART1n_CR2_USTnSB_Msk            (0x4UL)                   /*!< USART1n CR2: USTnSB (Bitfield-Mask: 0x01)             */
+#define USART1n_CR2_USTnTX8_Pos           (1UL)                     /*!< USART1n CR2: USTnTX8 (Bit 1)                          */
+#define USART1n_CR2_USTnTX8_Msk           (0x2UL)                   /*!< USART1n CR2: USTnTX8 (Bitfield-Mask: 0x01)            */
+#define USART1n_CR2_USTnRX8_Pos           (0UL)                     /*!< USART1n CR2: USTnRX8 (Bit 0)                          */
+#define USART1n_CR2_USTnRX8_Msk           (0x1UL)                   /*!< USART1n CR2: USTnRX8 (Bitfield-Mask: 0x01)            */
+/* ==========================================================  ST  =========================================================== */
+#define USART1n_ST_DREn_Pos               (7UL)                     /*!< USART1n ST: DREn (Bit 7)                              */
+#define USART1n_ST_DREn_Msk               (0x80UL)                  /*!< USART1n ST: DREn (Bitfield-Mask: 0x01)                */
+#define USART1n_ST_TXCn_Pos               (6UL)                     /*!< USART1n ST: TXCn (Bit 6)                              */
+#define USART1n_ST_TXCn_Msk               (0x40UL)                  /*!< USART1n ST: TXCn (Bitfield-Mask: 0x01)                */
+#define USART1n_ST_RXCn_Pos               (5UL)                     /*!< USART1n ST: RXCn (Bit 5)                              */
+#define USART1n_ST_RXCn_Msk               (0x20UL)                  /*!< USART1n ST: RXCn (Bitfield-Mask: 0x01)                */
+#define USART1n_ST_WAKEn_Pos              (4UL)                     /*!< USART1n ST: WAKEn (Bit 4)                             */
+#define USART1n_ST_WAKEn_Msk              (0x10UL)                  /*!< USART1n ST: WAKEn (Bitfield-Mask: 0x01)               */
+#define USART1n_ST_DORn_Pos               (2UL)                     /*!< USART1n ST: DORn (Bit 2)                              */
+#define USART1n_ST_DORn_Msk               (0x4UL)                   /*!< USART1n ST: DORn (Bitfield-Mask: 0x01)                */
+#define USART1n_ST_FEn_Pos                (1UL)                     /*!< USART1n ST: FEn (Bit 1)                               */
+#define USART1n_ST_FEn_Msk                (0x2UL)                   /*!< USART1n ST: FEn (Bitfield-Mask: 0x01)                 */
+#define USART1n_ST_PEn_Pos                (0UL)                     /*!< USART1n ST: PEn (Bit 0)                               */
+#define USART1n_ST_PEn_Msk                (0x1UL)                   /*!< USART1n ST: PEn (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  BDR  ========================================================== */
+#define USART1n_BDR_BDATA_Pos             (0UL)                     /*!< USART1n BDR: BDATA (Bit 0)                            */
+#define USART1n_BDR_BDATA_Msk             (0xfffUL)                 /*!< USART1n BDR: BDATA (Bitfield-Mask: 0xfff)             */
+/* ==========================================================  DR  =========================================================== */
+#define USART1n_DR_DATA_Pos               (0UL)                     /*!< USART1n DR: DATA (Bit 0)                              */
+#define USART1n_DR_DATA_Msk               (0xffUL)                  /*!< USART1n DR: DATA (Bitfield-Mask: 0xff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART10                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+#define USART10_CR1_USTnMS_Pos            (14UL)                    /*!< USART10 CR1: USTnMS (Bit 14)                          */
+#define USART10_CR1_USTnMS_Msk            (0xc000UL)                /*!< USART10 CR1: USTnMS (Bitfield-Mask: 0x03)             */
+#define USART10_CR1_USTnP_Pos             (12UL)                    /*!< USART10 CR1: USTnP (Bit 12)                           */
+#define USART10_CR1_USTnP_Msk             (0x3000UL)                /*!< USART10 CR1: USTnP (Bitfield-Mask: 0x03)              */
+#define USART10_CR1_USTnS_Pos             (9UL)                     /*!< USART10 CR1: USTnS (Bit 9)                            */
+#define USART10_CR1_USTnS_Msk             (0xe00UL)                 /*!< USART10 CR1: USTnS (Bitfield-Mask: 0x07)              */
+#define USART10_CR1_ORDn_Pos              (8UL)                     /*!< USART10 CR1: ORDn (Bit 8)                             */
+#define USART10_CR1_ORDn_Msk              (0x100UL)                 /*!< USART10 CR1: ORDn (Bitfield-Mask: 0x01)               */
+#define USART10_CR1_CPOLn_Pos             (7UL)                     /*!< USART10 CR1: CPOLn (Bit 7)                            */
+#define USART10_CR1_CPOLn_Msk             (0x80UL)                  /*!< USART10 CR1: CPOLn (Bitfield-Mask: 0x01)              */
+#define USART10_CR1_CPHAn_Pos             (6UL)                     /*!< USART10 CR1: CPHAn (Bit 6)                            */
+#define USART10_CR1_CPHAn_Msk             (0x40UL)                  /*!< USART10 CR1: CPHAn (Bitfield-Mask: 0x01)              */
+#define USART10_CR1_DRIEn_Pos             (5UL)                     /*!< USART10 CR1: DRIEn (Bit 5)                            */
+#define USART10_CR1_DRIEn_Msk             (0x20UL)                  /*!< USART10 CR1: DRIEn (Bitfield-Mask: 0x01)              */
+#define USART10_CR1_TXCIEn_Pos            (4UL)                     /*!< USART10 CR1: TXCIEn (Bit 4)                           */
+#define USART10_CR1_TXCIEn_Msk            (0x10UL)                  /*!< USART10 CR1: TXCIEn (Bitfield-Mask: 0x01)             */
+#define USART10_CR1_RXCIEn_Pos            (3UL)                     /*!< USART10 CR1: RXCIEn (Bit 3)                           */
+#define USART10_CR1_RXCIEn_Msk            (0x8UL)                   /*!< USART10 CR1: RXCIEn (Bitfield-Mask: 0x01)             */
+#define USART10_CR1_WAKEIEn_Pos           (2UL)                     /*!< USART10 CR1: WAKEIEn (Bit 2)                          */
+#define USART10_CR1_WAKEIEn_Msk           (0x4UL)                   /*!< USART10 CR1: WAKEIEn (Bitfield-Mask: 0x01)            */
+#define USART10_CR1_TXEn_Pos              (1UL)                     /*!< USART10 CR1: TXEn (Bit 1)                             */
+#define USART10_CR1_TXEn_Msk              (0x2UL)                   /*!< USART10 CR1: TXEn (Bitfield-Mask: 0x01)               */
+#define USART10_CR1_RXEn_Pos              (0UL)                     /*!< USART10 CR1: RXEn (Bit 0)                             */
+#define USART10_CR1_RXEn_Msk              (0x1UL)                   /*!< USART10 CR1: RXEn (Bitfield-Mask: 0x01)               */
+/* ==========================================================  CR2  ========================================================== */
+#define USART10_CR2_USTnEN_Pos            (9UL)                     /*!< USART10 CR2: USTnEN (Bit 9)                           */
+#define USART10_CR2_USTnEN_Msk            (0x200UL)                 /*!< USART10 CR2: USTnEN (Bitfield-Mask: 0x01)             */
+#define USART10_CR2_DBLSn_Pos             (8UL)                     /*!< USART10 CR2: DBLSn (Bit 8)                            */
+#define USART10_CR2_DBLSn_Msk             (0x100UL)                 /*!< USART10 CR2: DBLSn (Bitfield-Mask: 0x01)              */
+#define USART10_CR2_MASTERn_Pos           (7UL)                     /*!< USART10 CR2: MASTERn (Bit 7)                          */
+#define USART10_CR2_MASTERn_Msk           (0x80UL)                  /*!< USART10 CR2: MASTERn (Bitfield-Mask: 0x01)            */
+#define USART10_CR2_LOOPSn_Pos            (6UL)                     /*!< USART10 CR2: LOOPSn (Bit 6)                           */
+#define USART10_CR2_LOOPSn_Msk            (0x40UL)                  /*!< USART10 CR2: LOOPSn (Bitfield-Mask: 0x01)             */
+#define USART10_CR2_DISSCKn_Pos           (5UL)                     /*!< USART10 CR2: DISSCKn (Bit 5)                          */
+#define USART10_CR2_DISSCKn_Msk           (0x20UL)                  /*!< USART10 CR2: DISSCKn (Bitfield-Mask: 0x01)            */
+#define USART10_CR2_USTnSSEN_Pos          (4UL)                     /*!< USART10 CR2: USTnSSEN (Bit 4)                         */
+#define USART10_CR2_USTnSSEN_Msk          (0x10UL)                  /*!< USART10 CR2: USTnSSEN (Bitfield-Mask: 0x01)           */
+#define USART10_CR2_FXCHn_Pos             (3UL)                     /*!< USART10 CR2: FXCHn (Bit 3)                            */
+#define USART10_CR2_FXCHn_Msk             (0x8UL)                   /*!< USART10 CR2: FXCHn (Bitfield-Mask: 0x01)              */
+#define USART10_CR2_USTnSB_Pos            (2UL)                     /*!< USART10 CR2: USTnSB (Bit 2)                           */
+#define USART10_CR2_USTnSB_Msk            (0x4UL)                   /*!< USART10 CR2: USTnSB (Bitfield-Mask: 0x01)             */
+#define USART10_CR2_USTnTX8_Pos           (1UL)                     /*!< USART10 CR2: USTnTX8 (Bit 1)                          */
+#define USART10_CR2_USTnTX8_Msk           (0x2UL)                   /*!< USART10 CR2: USTnTX8 (Bitfield-Mask: 0x01)            */
+#define USART10_CR2_USTnRX8_Pos           (0UL)                     /*!< USART10 CR2: USTnRX8 (Bit 0)                          */
+#define USART10_CR2_USTnRX8_Msk           (0x1UL)                   /*!< USART10 CR2: USTnRX8 (Bitfield-Mask: 0x01)            */
+/* ==========================================================  ST  =========================================================== */
+#define USART10_ST_DREn_Pos               (7UL)                     /*!< USART10 ST: DREn (Bit 7)                              */
+#define USART10_ST_DREn_Msk               (0x80UL)                  /*!< USART10 ST: DREn (Bitfield-Mask: 0x01)                */
+#define USART10_ST_TXCn_Pos               (6UL)                     /*!< USART10 ST: TXCn (Bit 6)                              */
+#define USART10_ST_TXCn_Msk               (0x40UL)                  /*!< USART10 ST: TXCn (Bitfield-Mask: 0x01)                */
+#define USART10_ST_RXCn_Pos               (5UL)                     /*!< USART10 ST: RXCn (Bit 5)                              */
+#define USART10_ST_RXCn_Msk               (0x20UL)                  /*!< USART10 ST: RXCn (Bitfield-Mask: 0x01)                */
+#define USART10_ST_WAKEn_Pos              (4UL)                     /*!< USART10 ST: WAKEn (Bit 4)                             */
+#define USART10_ST_WAKEn_Msk              (0x10UL)                  /*!< USART10 ST: WAKEn (Bitfield-Mask: 0x01)               */
+#define USART10_ST_DORn_Pos               (2UL)                     /*!< USART10 ST: DORn (Bit 2)                              */
+#define USART10_ST_DORn_Msk               (0x4UL)                   /*!< USART10 ST: DORn (Bitfield-Mask: 0x01)                */
+#define USART10_ST_FEn_Pos                (1UL)                     /*!< USART10 ST: FEn (Bit 1)                               */
+#define USART10_ST_FEn_Msk                (0x2UL)                   /*!< USART10 ST: FEn (Bitfield-Mask: 0x01)                 */
+#define USART10_ST_PEn_Pos                (0UL)                     /*!< USART10 ST: PEn (Bit 0)                               */
+#define USART10_ST_PEn_Msk                (0x1UL)                   /*!< USART10 ST: PEn (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  BDR  ========================================================== */
+#define USART10_BDR_BDATA_Pos             (0UL)                     /*!< USART10 BDR: BDATA (Bit 0)                            */
+#define USART10_BDR_BDATA_Msk             (0xfffUL)                 /*!< USART10 BDR: BDATA (Bitfield-Mask: 0xfff)             */
+/* ==========================================================  DR  =========================================================== */
+#define USART10_DR_DATA_Pos               (0UL)                     /*!< USART10 DR: DATA (Bit 0)                              */
+#define USART10_DR_DATA_Msk               (0xffUL)                  /*!< USART10 DR: DATA (Bitfield-Mask: 0xff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART11                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+#define USART11_CR1_USTnMS_Pos            (14UL)                    /*!< USART11 CR1: USTnMS (Bit 14)                          */
+#define USART11_CR1_USTnMS_Msk            (0xc000UL)                /*!< USART11 CR1: USTnMS (Bitfield-Mask: 0x03)             */
+#define USART11_CR1_USTnP_Pos             (12UL)                    /*!< USART11 CR1: USTnP (Bit 12)                           */
+#define USART11_CR1_USTnP_Msk             (0x3000UL)                /*!< USART11 CR1: USTnP (Bitfield-Mask: 0x03)              */
+#define USART11_CR1_USTnS_Pos             (9UL)                     /*!< USART11 CR1: USTnS (Bit 9)                            */
+#define USART11_CR1_USTnS_Msk             (0xe00UL)                 /*!< USART11 CR1: USTnS (Bitfield-Mask: 0x07)              */
+#define USART11_CR1_ORDn_Pos              (8UL)                     /*!< USART11 CR1: ORDn (Bit 8)                             */
+#define USART11_CR1_ORDn_Msk              (0x100UL)                 /*!< USART11 CR1: ORDn (Bitfield-Mask: 0x01)               */
+#define USART11_CR1_CPOLn_Pos             (7UL)                     /*!< USART11 CR1: CPOLn (Bit 7)                            */
+#define USART11_CR1_CPOLn_Msk             (0x80UL)                  /*!< USART11 CR1: CPOLn (Bitfield-Mask: 0x01)              */
+#define USART11_CR1_CPHAn_Pos             (6UL)                     /*!< USART11 CR1: CPHAn (Bit 6)                            */
+#define USART11_CR1_CPHAn_Msk             (0x40UL)                  /*!< USART11 CR1: CPHAn (Bitfield-Mask: 0x01)              */
+#define USART11_CR1_DRIEn_Pos             (5UL)                     /*!< USART11 CR1: DRIEn (Bit 5)                            */
+#define USART11_CR1_DRIEn_Msk             (0x20UL)                  /*!< USART11 CR1: DRIEn (Bitfield-Mask: 0x01)              */
+#define USART11_CR1_TXCIEn_Pos            (4UL)                     /*!< USART11 CR1: TXCIEn (Bit 4)                           */
+#define USART11_CR1_TXCIEn_Msk            (0x10UL)                  /*!< USART11 CR1: TXCIEn (Bitfield-Mask: 0x01)             */
+#define USART11_CR1_RXCIEn_Pos            (3UL)                     /*!< USART11 CR1: RXCIEn (Bit 3)                           */
+#define USART11_CR1_RXCIEn_Msk            (0x8UL)                   /*!< USART11 CR1: RXCIEn (Bitfield-Mask: 0x01)             */
+#define USART11_CR1_WAKEIEn_Pos           (2UL)                     /*!< USART11 CR1: WAKEIEn (Bit 2)                          */
+#define USART11_CR1_WAKEIEn_Msk           (0x4UL)                   /*!< USART11 CR1: WAKEIEn (Bitfield-Mask: 0x01)            */
+#define USART11_CR1_TXEn_Pos              (1UL)                     /*!< USART11 CR1: TXEn (Bit 1)                             */
+#define USART11_CR1_TXEn_Msk              (0x2UL)                   /*!< USART11 CR1: TXEn (Bitfield-Mask: 0x01)               */
+#define USART11_CR1_RXEn_Pos              (0UL)                     /*!< USART11 CR1: RXEn (Bit 0)                             */
+#define USART11_CR1_RXEn_Msk              (0x1UL)                   /*!< USART11 CR1: RXEn (Bitfield-Mask: 0x01)               */
+/* ==========================================================  CR2  ========================================================== */
+#define USART11_CR2_USTnEN_Pos            (9UL)                     /*!< USART11 CR2: USTnEN (Bit 9)                           */
+#define USART11_CR2_USTnEN_Msk            (0x200UL)                 /*!< USART11 CR2: USTnEN (Bitfield-Mask: 0x01)             */
+#define USART11_CR2_DBLSn_Pos             (8UL)                     /*!< USART11 CR2: DBLSn (Bit 8)                            */
+#define USART11_CR2_DBLSn_Msk             (0x100UL)                 /*!< USART11 CR2: DBLSn (Bitfield-Mask: 0x01)              */
+#define USART11_CR2_MASTERn_Pos           (7UL)                     /*!< USART11 CR2: MASTERn (Bit 7)                          */
+#define USART11_CR2_MASTERn_Msk           (0x80UL)                  /*!< USART11 CR2: MASTERn (Bitfield-Mask: 0x01)            */
+#define USART11_CR2_LOOPSn_Pos            (6UL)                     /*!< USART11 CR2: LOOPSn (Bit 6)                           */
+#define USART11_CR2_LOOPSn_Msk            (0x40UL)                  /*!< USART11 CR2: LOOPSn (Bitfield-Mask: 0x01)             */
+#define USART11_CR2_DISSCKn_Pos           (5UL)                     /*!< USART11 CR2: DISSCKn (Bit 5)                          */
+#define USART11_CR2_DISSCKn_Msk           (0x20UL)                  /*!< USART11 CR2: DISSCKn (Bitfield-Mask: 0x01)            */
+#define USART11_CR2_USTnSSEN_Pos          (4UL)                     /*!< USART11 CR2: USTnSSEN (Bit 4)                         */
+#define USART11_CR2_USTnSSEN_Msk          (0x10UL)                  /*!< USART11 CR2: USTnSSEN (Bitfield-Mask: 0x01)           */
+#define USART11_CR2_FXCHn_Pos             (3UL)                     /*!< USART11 CR2: FXCHn (Bit 3)                            */
+#define USART11_CR2_FXCHn_Msk             (0x8UL)                   /*!< USART11 CR2: FXCHn (Bitfield-Mask: 0x01)              */
+#define USART11_CR2_USTnSB_Pos            (2UL)                     /*!< USART11 CR2: USTnSB (Bit 2)                           */
+#define USART11_CR2_USTnSB_Msk            (0x4UL)                   /*!< USART11 CR2: USTnSB (Bitfield-Mask: 0x01)             */
+#define USART11_CR2_USTnTX8_Pos           (1UL)                     /*!< USART11 CR2: USTnTX8 (Bit 1)                          */
+#define USART11_CR2_USTnTX8_Msk           (0x2UL)                   /*!< USART11 CR2: USTnTX8 (Bitfield-Mask: 0x01)            */
+#define USART11_CR2_USTnRX8_Pos           (0UL)                     /*!< USART11 CR2: USTnRX8 (Bit 0)                          */
+#define USART11_CR2_USTnRX8_Msk           (0x1UL)                   /*!< USART11 CR2: USTnRX8 (Bitfield-Mask: 0x01)            */
+/* ==========================================================  ST  =========================================================== */
+#define USART11_ST_DREn_Pos               (7UL)                     /*!< USART11 ST: DREn (Bit 7)                              */
+#define USART11_ST_DREn_Msk               (0x80UL)                  /*!< USART11 ST: DREn (Bitfield-Mask: 0x01)                */
+#define USART11_ST_TXCn_Pos               (6UL)                     /*!< USART11 ST: TXCn (Bit 6)                              */
+#define USART11_ST_TXCn_Msk               (0x40UL)                  /*!< USART11 ST: TXCn (Bitfield-Mask: 0x01)                */
+#define USART11_ST_RXCn_Pos               (5UL)                     /*!< USART11 ST: RXCn (Bit 5)                              */
+#define USART11_ST_RXCn_Msk               (0x20UL)                  /*!< USART11 ST: RXCn (Bitfield-Mask: 0x01)                */
+#define USART11_ST_WAKEn_Pos              (4UL)                     /*!< USART11 ST: WAKEn (Bit 4)                             */
+#define USART11_ST_WAKEn_Msk              (0x10UL)                  /*!< USART11 ST: WAKEn (Bitfield-Mask: 0x01)               */
+#define USART11_ST_DORn_Pos               (2UL)                     /*!< USART11 ST: DORn (Bit 2)                              */
+#define USART11_ST_DORn_Msk               (0x4UL)                   /*!< USART11 ST: DORn (Bitfield-Mask: 0x01)                */
+#define USART11_ST_FEn_Pos                (1UL)                     /*!< USART11 ST: FEn (Bit 1)                               */
+#define USART11_ST_FEn_Msk                (0x2UL)                   /*!< USART11 ST: FEn (Bitfield-Mask: 0x01)                 */
+#define USART11_ST_PEn_Pos                (0UL)                     /*!< USART11 ST: PEn (Bit 0)                               */
+#define USART11_ST_PEn_Msk                (0x1UL)                   /*!< USART11 ST: PEn (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  BDR  ========================================================== */
+#define USART11_BDR_BDATA_Pos             (0UL)                     /*!< USART11 BDR: BDATA (Bit 0)                            */
+#define USART11_BDR_BDATA_Msk             (0xfffUL)                 /*!< USART11 BDR: BDATA (Bitfield-Mask: 0xfff)             */
+/* ==========================================================  DR  =========================================================== */
+#define USART11_DR_DATA_Pos               (0UL)                     /*!< USART11 DR: DATA (Bit 0)                              */
+#define USART11_DR_DATA_Msk               (0xffUL)                  /*!< USART11 DR: DATA (Bitfield-Mask: 0xff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART12                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+#define USART12_CR1_USTnMS_Pos            (14UL)                    /*!< USART12 CR1: USTnMS (Bit 14)                          */
+#define USART12_CR1_USTnMS_Msk            (0xc000UL)                /*!< USART12 CR1: USTnMS (Bitfield-Mask: 0x03)             */
+#define USART12_CR1_USTnP_Pos             (12UL)                    /*!< USART12 CR1: USTnP (Bit 12)                           */
+#define USART12_CR1_USTnP_Msk             (0x3000UL)                /*!< USART12 CR1: USTnP (Bitfield-Mask: 0x03)              */
+#define USART12_CR1_USTnS_Pos             (9UL)                     /*!< USART12 CR1: USTnS (Bit 9)                            */
+#define USART12_CR1_USTnS_Msk             (0xe00UL)                 /*!< USART12 CR1: USTnS (Bitfield-Mask: 0x07)              */
+#define USART12_CR1_ORDn_Pos              (8UL)                     /*!< USART12 CR1: ORDn (Bit 8)                             */
+#define USART12_CR1_ORDn_Msk              (0x100UL)                 /*!< USART12 CR1: ORDn (Bitfield-Mask: 0x01)               */
+#define USART12_CR1_CPOLn_Pos             (7UL)                     /*!< USART12 CR1: CPOLn (Bit 7)                            */
+#define USART12_CR1_CPOLn_Msk             (0x80UL)                  /*!< USART12 CR1: CPOLn (Bitfield-Mask: 0x01)              */
+#define USART12_CR1_CPHAn_Pos             (6UL)                     /*!< USART12 CR1: CPHAn (Bit 6)                            */
+#define USART12_CR1_CPHAn_Msk             (0x40UL)                  /*!< USART12 CR1: CPHAn (Bitfield-Mask: 0x01)              */
+#define USART12_CR1_DRIEn_Pos             (5UL)                     /*!< USART12 CR1: DRIEn (Bit 5)                            */
+#define USART12_CR1_DRIEn_Msk             (0x20UL)                  /*!< USART12 CR1: DRIEn (Bitfield-Mask: 0x01)              */
+#define USART12_CR1_TXCIEn_Pos            (4UL)                     /*!< USART12 CR1: TXCIEn (Bit 4)                           */
+#define USART12_CR1_TXCIEn_Msk            (0x10UL)                  /*!< USART12 CR1: TXCIEn (Bitfield-Mask: 0x01)             */
+#define USART12_CR1_RXCIEn_Pos            (3UL)                     /*!< USART12 CR1: RXCIEn (Bit 3)                           */
+#define USART12_CR1_RXCIEn_Msk            (0x8UL)                   /*!< USART12 CR1: RXCIEn (Bitfield-Mask: 0x01)             */
+#define USART12_CR1_WAKEIEn_Pos           (2UL)                     /*!< USART12 CR1: WAKEIEn (Bit 2)                          */
+#define USART12_CR1_WAKEIEn_Msk           (0x4UL)                   /*!< USART12 CR1: WAKEIEn (Bitfield-Mask: 0x01)            */
+#define USART12_CR1_TXEn_Pos              (1UL)                     /*!< USART12 CR1: TXEn (Bit 1)                             */
+#define USART12_CR1_TXEn_Msk              (0x2UL)                   /*!< USART12 CR1: TXEn (Bitfield-Mask: 0x01)               */
+#define USART12_CR1_RXEn_Pos              (0UL)                     /*!< USART12 CR1: RXEn (Bit 0)                             */
+#define USART12_CR1_RXEn_Msk              (0x1UL)                   /*!< USART12 CR1: RXEn (Bitfield-Mask: 0x01)               */
+/* ==========================================================  CR2  ========================================================== */
+#define USART12_CR2_USTnEN_Pos            (9UL)                     /*!< USART12 CR2: USTnEN (Bit 9)                           */
+#define USART12_CR2_USTnEN_Msk            (0x200UL)                 /*!< USART12 CR2: USTnEN (Bitfield-Mask: 0x01)             */
+#define USART12_CR2_DBLSn_Pos             (8UL)                     /*!< USART12 CR2: DBLSn (Bit 8)                            */
+#define USART12_CR2_DBLSn_Msk             (0x100UL)                 /*!< USART12 CR2: DBLSn (Bitfield-Mask: 0x01)              */
+#define USART12_CR2_MASTERn_Pos           (7UL)                     /*!< USART12 CR2: MASTERn (Bit 7)                          */
+#define USART12_CR2_MASTERn_Msk           (0x80UL)                  /*!< USART12 CR2: MASTERn (Bitfield-Mask: 0x01)            */
+#define USART12_CR2_LOOPSn_Pos            (6UL)                     /*!< USART12 CR2: LOOPSn (Bit 6)                           */
+#define USART12_CR2_LOOPSn_Msk            (0x40UL)                  /*!< USART12 CR2: LOOPSn (Bitfield-Mask: 0x01)             */
+#define USART12_CR2_DISSCKn_Pos           (5UL)                     /*!< USART12 CR2: DISSCKn (Bit 5)                          */
+#define USART12_CR2_DISSCKn_Msk           (0x20UL)                  /*!< USART12 CR2: DISSCKn (Bitfield-Mask: 0x01)            */
+#define USART12_CR2_USTnSSEN_Pos          (4UL)                     /*!< USART12 CR2: USTnSSEN (Bit 4)                         */
+#define USART12_CR2_USTnSSEN_Msk          (0x10UL)                  /*!< USART12 CR2: USTnSSEN (Bitfield-Mask: 0x01)           */
+#define USART12_CR2_FXCHn_Pos             (3UL)                     /*!< USART12 CR2: FXCHn (Bit 3)                            */
+#define USART12_CR2_FXCHn_Msk             (0x8UL)                   /*!< USART12 CR2: FXCHn (Bitfield-Mask: 0x01)              */
+#define USART12_CR2_USTnSB_Pos            (2UL)                     /*!< USART12 CR2: USTnSB (Bit 2)                           */
+#define USART12_CR2_USTnSB_Msk            (0x4UL)                   /*!< USART12 CR2: USTnSB (Bitfield-Mask: 0x01)             */
+#define USART12_CR2_USTnTX8_Pos           (1UL)                     /*!< USART12 CR2: USTnTX8 (Bit 1)                          */
+#define USART12_CR2_USTnTX8_Msk           (0x2UL)                   /*!< USART12 CR2: USTnTX8 (Bitfield-Mask: 0x01)            */
+#define USART12_CR2_USTnRX8_Pos           (0UL)                     /*!< USART12 CR2: USTnRX8 (Bit 0)                          */
+#define USART12_CR2_USTnRX8_Msk           (0x1UL)                   /*!< USART12 CR2: USTnRX8 (Bitfield-Mask: 0x01)            */
+/* ==========================================================  ST  =========================================================== */
+#define USART12_ST_DREn_Pos               (7UL)                     /*!< USART12 ST: DREn (Bit 7)                              */
+#define USART12_ST_DREn_Msk               (0x80UL)                  /*!< USART12 ST: DREn (Bitfield-Mask: 0x01)                */
+#define USART12_ST_TXCn_Pos               (6UL)                     /*!< USART12 ST: TXCn (Bit 6)                              */
+#define USART12_ST_TXCn_Msk               (0x40UL)                  /*!< USART12 ST: TXCn (Bitfield-Mask: 0x01)                */
+#define USART12_ST_RXCn_Pos               (5UL)                     /*!< USART12 ST: RXCn (Bit 5)                              */
+#define USART12_ST_RXCn_Msk               (0x20UL)                  /*!< USART12 ST: RXCn (Bitfield-Mask: 0x01)                */
+#define USART12_ST_WAKEn_Pos              (4UL)                     /*!< USART12 ST: WAKEn (Bit 4)                             */
+#define USART12_ST_WAKEn_Msk              (0x10UL)                  /*!< USART12 ST: WAKEn (Bitfield-Mask: 0x01)               */
+#define USART12_ST_DORn_Pos               (2UL)                     /*!< USART12 ST: DORn (Bit 2)                              */
+#define USART12_ST_DORn_Msk               (0x4UL)                   /*!< USART12 ST: DORn (Bitfield-Mask: 0x01)                */
+#define USART12_ST_FEn_Pos                (1UL)                     /*!< USART12 ST: FEn (Bit 1)                               */
+#define USART12_ST_FEn_Msk                (0x2UL)                   /*!< USART12 ST: FEn (Bitfield-Mask: 0x01)                 */
+#define USART12_ST_PEn_Pos                (0UL)                     /*!< USART12 ST: PEn (Bit 0)                               */
+#define USART12_ST_PEn_Msk                (0x1UL)                   /*!< USART12 ST: PEn (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  BDR  ========================================================== */
+#define USART12_BDR_BDATA_Pos             (0UL)                     /*!< USART12 BDR: BDATA (Bit 0)                            */
+#define USART12_BDR_BDATA_Msk             (0xfffUL)                 /*!< USART12 BDR: BDATA (Bitfield-Mask: 0xfff)             */
+/* ==========================================================  DR  =========================================================== */
+#define USART12_DR_DATA_Pos               (0UL)                     /*!< USART12 DR: DATA (Bit 0)                              */
+#define USART12_DR_DATA_Msk               (0xffUL)                  /*!< USART12 DR: DATA (Bitfield-Mask: 0xff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART13                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+#define USART13_CR1_USTnMS_Pos            (14UL)                    /*!< USART13 CR1: USTnMS (Bit 14)                          */
+#define USART13_CR1_USTnMS_Msk            (0xc000UL)                /*!< USART13 CR1: USTnMS (Bitfield-Mask: 0x03)             */
+#define USART13_CR1_USTnP_Pos             (12UL)                    /*!< USART13 CR1: USTnP (Bit 12)                           */
+#define USART13_CR1_USTnP_Msk             (0x3000UL)                /*!< USART13 CR1: USTnP (Bitfield-Mask: 0x03)              */
+#define USART13_CR1_USTnS_Pos             (9UL)                     /*!< USART13 CR1: USTnS (Bit 9)                            */
+#define USART13_CR1_USTnS_Msk             (0xe00UL)                 /*!< USART13 CR1: USTnS (Bitfield-Mask: 0x07)              */
+#define USART13_CR1_ORDn_Pos              (8UL)                     /*!< USART13 CR1: ORDn (Bit 8)                             */
+#define USART13_CR1_ORDn_Msk              (0x100UL)                 /*!< USART13 CR1: ORDn (Bitfield-Mask: 0x01)               */
+#define USART13_CR1_CPOLn_Pos             (7UL)                     /*!< USART13 CR1: CPOLn (Bit 7)                            */
+#define USART13_CR1_CPOLn_Msk             (0x80UL)                  /*!< USART13 CR1: CPOLn (Bitfield-Mask: 0x01)              */
+#define USART13_CR1_CPHAn_Pos             (6UL)                     /*!< USART13 CR1: CPHAn (Bit 6)                            */
+#define USART13_CR1_CPHAn_Msk             (0x40UL)                  /*!< USART13 CR1: CPHAn (Bitfield-Mask: 0x01)              */
+#define USART13_CR1_DRIEn_Pos             (5UL)                     /*!< USART13 CR1: DRIEn (Bit 5)                            */
+#define USART13_CR1_DRIEn_Msk             (0x20UL)                  /*!< USART13 CR1: DRIEn (Bitfield-Mask: 0x01)              */
+#define USART13_CR1_TXCIEn_Pos            (4UL)                     /*!< USART13 CR1: TXCIEn (Bit 4)                           */
+#define USART13_CR1_TXCIEn_Msk            (0x10UL)                  /*!< USART13 CR1: TXCIEn (Bitfield-Mask: 0x01)             */
+#define USART13_CR1_RXCIEn_Pos            (3UL)                     /*!< USART13 CR1: RXCIEn (Bit 3)                           */
+#define USART13_CR1_RXCIEn_Msk            (0x8UL)                   /*!< USART13 CR1: RXCIEn (Bitfield-Mask: 0x01)             */
+#define USART13_CR1_WAKEIEn_Pos           (2UL)                     /*!< USART13 CR1: WAKEIEn (Bit 2)                          */
+#define USART13_CR1_WAKEIEn_Msk           (0x4UL)                   /*!< USART13 CR1: WAKEIEn (Bitfield-Mask: 0x01)            */
+#define USART13_CR1_TXEn_Pos              (1UL)                     /*!< USART13 CR1: TXEn (Bit 1)                             */
+#define USART13_CR1_TXEn_Msk              (0x2UL)                   /*!< USART13 CR1: TXEn (Bitfield-Mask: 0x01)               */
+#define USART13_CR1_RXEn_Pos              (0UL)                     /*!< USART13 CR1: RXEn (Bit 0)                             */
+#define USART13_CR1_RXEn_Msk              (0x1UL)                   /*!< USART13 CR1: RXEn (Bitfield-Mask: 0x01)               */
+/* ==========================================================  CR2  ========================================================== */
+#define USART13_CR2_USTnEN_Pos            (9UL)                     /*!< USART13 CR2: USTnEN (Bit 9)                           */
+#define USART13_CR2_USTnEN_Msk            (0x200UL)                 /*!< USART13 CR2: USTnEN (Bitfield-Mask: 0x01)             */
+#define USART13_CR2_DBLSn_Pos             (8UL)                     /*!< USART13 CR2: DBLSn (Bit 8)                            */
+#define USART13_CR2_DBLSn_Msk             (0x100UL)                 /*!< USART13 CR2: DBLSn (Bitfield-Mask: 0x01)              */
+#define USART13_CR2_MASTERn_Pos           (7UL)                     /*!< USART13 CR2: MASTERn (Bit 7)                          */
+#define USART13_CR2_MASTERn_Msk           (0x80UL)                  /*!< USART13 CR2: MASTERn (Bitfield-Mask: 0x01)            */
+#define USART13_CR2_LOOPSn_Pos            (6UL)                     /*!< USART13 CR2: LOOPSn (Bit 6)                           */
+#define USART13_CR2_LOOPSn_Msk            (0x40UL)                  /*!< USART13 CR2: LOOPSn (Bitfield-Mask: 0x01)             */
+#define USART13_CR2_DISSCKn_Pos           (5UL)                     /*!< USART13 CR2: DISSCKn (Bit 5)                          */
+#define USART13_CR2_DISSCKn_Msk           (0x20UL)                  /*!< USART13 CR2: DISSCKn (Bitfield-Mask: 0x01)            */
+#define USART13_CR2_USTnSSEN_Pos          (4UL)                     /*!< USART13 CR2: USTnSSEN (Bit 4)                         */
+#define USART13_CR2_USTnSSEN_Msk          (0x10UL)                  /*!< USART13 CR2: USTnSSEN (Bitfield-Mask: 0x01)           */
+#define USART13_CR2_FXCHn_Pos             (3UL)                     /*!< USART13 CR2: FXCHn (Bit 3)                            */
+#define USART13_CR2_FXCHn_Msk             (0x8UL)                   /*!< USART13 CR2: FXCHn (Bitfield-Mask: 0x01)              */
+#define USART13_CR2_USTnSB_Pos            (2UL)                     /*!< USART13 CR2: USTnSB (Bit 2)                           */
+#define USART13_CR2_USTnSB_Msk            (0x4UL)                   /*!< USART13 CR2: USTnSB (Bitfield-Mask: 0x01)             */
+#define USART13_CR2_USTnTX8_Pos           (1UL)                     /*!< USART13 CR2: USTnTX8 (Bit 1)                          */
+#define USART13_CR2_USTnTX8_Msk           (0x2UL)                   /*!< USART13 CR2: USTnTX8 (Bitfield-Mask: 0x01)            */
+#define USART13_CR2_USTnRX8_Pos           (0UL)                     /*!< USART13 CR2: USTnRX8 (Bit 0)                          */
+#define USART13_CR2_USTnRX8_Msk           (0x1UL)                   /*!< USART13 CR2: USTnRX8 (Bitfield-Mask: 0x01)            */
+/* ==========================================================  ST  =========================================================== */
+#define USART13_ST_DREn_Pos               (7UL)                     /*!< USART13 ST: DREn (Bit 7)                              */
+#define USART13_ST_DREn_Msk               (0x80UL)                  /*!< USART13 ST: DREn (Bitfield-Mask: 0x01)                */
+#define USART13_ST_TXCn_Pos               (6UL)                     /*!< USART13 ST: TXCn (Bit 6)                              */
+#define USART13_ST_TXCn_Msk               (0x40UL)                  /*!< USART13 ST: TXCn (Bitfield-Mask: 0x01)                */
+#define USART13_ST_RXCn_Pos               (5UL)                     /*!< USART13 ST: RXCn (Bit 5)                              */
+#define USART13_ST_RXCn_Msk               (0x20UL)                  /*!< USART13 ST: RXCn (Bitfield-Mask: 0x01)                */
+#define USART13_ST_WAKEn_Pos              (4UL)                     /*!< USART13 ST: WAKEn (Bit 4)                             */
+#define USART13_ST_WAKEn_Msk              (0x10UL)                  /*!< USART13 ST: WAKEn (Bitfield-Mask: 0x01)               */
+#define USART13_ST_DORn_Pos               (2UL)                     /*!< USART13 ST: DORn (Bit 2)                              */
+#define USART13_ST_DORn_Msk               (0x4UL)                   /*!< USART13 ST: DORn (Bitfield-Mask: 0x01)                */
+#define USART13_ST_FEn_Pos                (1UL)                     /*!< USART13 ST: FEn (Bit 1)                               */
+#define USART13_ST_FEn_Msk                (0x2UL)                   /*!< USART13 ST: FEn (Bitfield-Mask: 0x01)                 */
+#define USART13_ST_PEn_Pos                (0UL)                     /*!< USART13 ST: PEn (Bit 0)                               */
+#define USART13_ST_PEn_Msk                (0x1UL)                   /*!< USART13 ST: PEn (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  BDR  ========================================================== */
+#define USART13_BDR_BDATA_Pos             (0UL)                     /*!< USART13 BDR: BDATA (Bit 0)                            */
+#define USART13_BDR_BDATA_Msk             (0xfffUL)                 /*!< USART13 BDR: BDATA (Bitfield-Mask: 0xfff)             */
+/* ==========================================================  DR  =========================================================== */
+#define USART13_DR_DATA_Pos               (0UL)                     /*!< USART13 DR: DATA (Bit 0)                              */
+#define USART13_DR_DATA_Msk               (0xffUL)                  /*!< USART13 DR: DATA (Bitfield-Mask: 0xff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                           UARTn                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  RBR  ========================================================== */
+#define UARTn_RBR_RBR_Pos                 (0UL)                     /*!< UARTn RBR: RBR (Bit 0)                                */
+#define UARTn_RBR_RBR_Msk                 (0xffUL)                  /*!< UARTn RBR: RBR (Bitfield-Mask: 0xff)                  */
+/* ==========================================================  THR  ========================================================== */
+#define UARTn_THR_THR_Pos                 (0UL)                     /*!< UARTn THR: THR (Bit 0)                                */
+#define UARTn_THR_THR_Msk                 (0xffUL)                  /*!< UARTn THR: THR (Bitfield-Mask: 0xff)                  */
+/* ==========================================================  IER  ========================================================== */
+#define UARTn_IER_TXEIE_Pos               (3UL)                     /*!< UARTn IER: TXEIE (Bit 3)                              */
+#define UARTn_IER_TXEIE_Msk               (0x8UL)                   /*!< UARTn IER: TXEIE (Bitfield-Mask: 0x01)                */
+#define UARTn_IER_RLSIE_Pos               (2UL)                     /*!< UARTn IER: RLSIE (Bit 2)                              */
+#define UARTn_IER_RLSIE_Msk               (0x4UL)                   /*!< UARTn IER: RLSIE (Bitfield-Mask: 0x01)                */
+#define UARTn_IER_THREIE_Pos              (1UL)                     /*!< UARTn IER: THREIE (Bit 1)                             */
+#define UARTn_IER_THREIE_Msk              (0x2UL)                   /*!< UARTn IER: THREIE (Bitfield-Mask: 0x01)               */
+#define UARTn_IER_DRIE_Pos                (0UL)                     /*!< UARTn IER: DRIE (Bit 0)                               */
+#define UARTn_IER_DRIE_Msk                (0x1UL)                   /*!< UARTn IER: DRIE (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  IIR  ========================================================== */
+#define UARTn_IIR_TXE_Pos                 (4UL)                     /*!< UARTn IIR: TXE (Bit 4)                                */
+#define UARTn_IIR_TXE_Msk                 (0x10UL)                  /*!< UARTn IIR: TXE (Bitfield-Mask: 0x01)                  */
+#define UARTn_IIR_IID_Pos                 (1UL)                     /*!< UARTn IIR: IID (Bit 1)                                */
+#define UARTn_IIR_IID_Msk                 (0x6UL)                   /*!< UARTn IIR: IID (Bitfield-Mask: 0x03)                  */
+#define UARTn_IIR_IPEN_Pos                (0UL)                     /*!< UARTn IIR: IPEN (Bit 0)                               */
+#define UARTn_IIR_IPEN_Msk                (0x1UL)                   /*!< UARTn IIR: IPEN (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  LCR  ========================================================== */
+#define UARTn_LCR_BREAK_Pos               (6UL)                     /*!< UARTn LCR: BREAK (Bit 6)                              */
+#define UARTn_LCR_BREAK_Msk               (0x40UL)                  /*!< UARTn LCR: BREAK (Bitfield-Mask: 0x01)                */
+#define UARTn_LCR_STICKP_Pos              (5UL)                     /*!< UARTn LCR: STICKP (Bit 5)                             */
+#define UARTn_LCR_STICKP_Msk              (0x20UL)                  /*!< UARTn LCR: STICKP (Bitfield-Mask: 0x01)               */
+#define UARTn_LCR_PARITY_Pos              (4UL)                     /*!< UARTn LCR: PARITY (Bit 4)                             */
+#define UARTn_LCR_PARITY_Msk              (0x10UL)                  /*!< UARTn LCR: PARITY (Bitfield-Mask: 0x01)               */
+#define UARTn_LCR_PEN_Pos                 (3UL)                     /*!< UARTn LCR: PEN (Bit 3)                                */
+#define UARTn_LCR_PEN_Msk                 (0x8UL)                   /*!< UARTn LCR: PEN (Bitfield-Mask: 0x01)                  */
+#define UARTn_LCR_STOPBIT_Pos             (2UL)                     /*!< UARTn LCR: STOPBIT (Bit 2)                            */
+#define UARTn_LCR_STOPBIT_Msk             (0x4UL)                   /*!< UARTn LCR: STOPBIT (Bitfield-Mask: 0x01)              */
+#define UARTn_LCR_DLEN_Pos                (0UL)                     /*!< UARTn LCR: DLEN (Bit 0)                               */
+#define UARTn_LCR_DLEN_Msk                (0x3UL)                   /*!< UARTn LCR: DLEN (Bitfield-Mask: 0x03)                 */
+/* ==========================================================  DCR  ========================================================== */
+#define UARTn_DCR_LBON_Pos                (4UL)                     /*!< UARTn DCR: LBON (Bit 4)                               */
+#define UARTn_DCR_LBON_Msk                (0x10UL)                  /*!< UARTn DCR: LBON (Bitfield-Mask: 0x01)                 */
+#define UARTn_DCR_RXINV_Pos               (3UL)                     /*!< UARTn DCR: RXINV (Bit 3)                              */
+#define UARTn_DCR_RXINV_Msk               (0x8UL)                   /*!< UARTn DCR: RXINV (Bitfield-Mask: 0x01)                */
+#define UARTn_DCR_TXINV_Pos               (2UL)                     /*!< UARTn DCR: TXINV (Bit 2)                              */
+#define UARTn_DCR_TXINV_Msk               (0x4UL)                   /*!< UARTn DCR: TXINV (Bitfield-Mask: 0x01)                */
+/* ==========================================================  LSR  ========================================================== */
+#define UARTn_LSR_TEMT_Pos                (6UL)                     /*!< UARTn LSR: TEMT (Bit 6)                               */
+#define UARTn_LSR_TEMT_Msk                (0x40UL)                  /*!< UARTn LSR: TEMT (Bitfield-Mask: 0x01)                 */
+#define UARTn_LSR_THRE_Pos                (5UL)                     /*!< UARTn LSR: THRE (Bit 5)                               */
+#define UARTn_LSR_THRE_Msk                (0x20UL)                  /*!< UARTn LSR: THRE (Bitfield-Mask: 0x01)                 */
+#define UARTn_LSR_BI_Pos                  (4UL)                     /*!< UARTn LSR: BI (Bit 4)                                 */
+#define UARTn_LSR_BI_Msk                  (0x10UL)                  /*!< UARTn LSR: BI (Bitfield-Mask: 0x01)                   */
+#define UARTn_LSR_FE_Pos                  (3UL)                     /*!< UARTn LSR: FE (Bit 3)                                 */
+#define UARTn_LSR_FE_Msk                  (0x8UL)                   /*!< UARTn LSR: FE (Bitfield-Mask: 0x01)                   */
+#define UARTn_LSR_PE_Pos                  (2UL)                     /*!< UARTn LSR: PE (Bit 2)                                 */
+#define UARTn_LSR_PE_Msk                  (0x4UL)                   /*!< UARTn LSR: PE (Bitfield-Mask: 0x01)                   */
+#define UARTn_LSR_OE_Pos                  (1UL)                     /*!< UARTn LSR: OE (Bit 1)                                 */
+#define UARTn_LSR_OE_Msk                  (0x2UL)                   /*!< UARTn LSR: OE (Bitfield-Mask: 0x01)                   */
+#define UARTn_LSR_DR_Pos                  (0UL)                     /*!< UARTn LSR: DR (Bit 0)                                 */
+#define UARTn_LSR_DR_Msk                  (0x1UL)                   /*!< UARTn LSR: DR (Bitfield-Mask: 0x01)                   */
+/* ==========================================================  BDR  ========================================================== */
+#define UARTn_BDR_BDR_Pos                 (0UL)                     /*!< UARTn BDR: BDR (Bit 0)                                */
+#define UARTn_BDR_BDR_Msk                 (0xffffUL)                /*!< UARTn BDR: BDR (Bitfield-Mask: 0xffff)                */
+/* ==========================================================  BFR  ========================================================== */
+#define UARTn_BFR_BFR_Pos                 (0UL)                     /*!< UARTn BFR: BFR (Bit 0)                                */
+#define UARTn_BFR_BFR_Msk                 (0xffUL)                  /*!< UARTn BFR: BFR (Bitfield-Mask: 0xff)                  */
+/* =========================================================  IDTR  ========================================================== */
+#define UARTn_IDTR_SMS_Pos                (7UL)                     /*!< UARTn IDTR: SMS (Bit 7)                               */
+#define UARTn_IDTR_SMS_Msk                (0x80UL)                  /*!< UARTn IDTR: SMS (Bitfield-Mask: 0x01)                 */
+#define UARTn_IDTR_DMS_Pos                (6UL)                     /*!< UARTn IDTR: DMS (Bit 6)                               */
+#define UARTn_IDTR_DMS_Msk                (0x40UL)                  /*!< UARTn IDTR: DMS (Bitfield-Mask: 0x01)                 */
+#define UARTn_IDTR_WAITVAL_Pos            (0UL)                     /*!< UARTn IDTR: WAITVAL (Bit 0)                           */
+#define UARTn_IDTR_WAITVAL_Msk            (0x7UL)                   /*!< UARTn IDTR: WAITVAL (Bitfield-Mask: 0x07)             */
+
+
+/* =========================================================================================================================== */
+/* ================                                           UART0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  RBR  ========================================================== */
+#define UART0_RBR_RBR_Pos                 (0UL)                     /*!< UART0 RBR: RBR (Bit 0)                                */
+#define UART0_RBR_RBR_Msk                 (0xffUL)                  /*!< UART0 RBR: RBR (Bitfield-Mask: 0xff)                  */
+/* ==========================================================  THR  ========================================================== */
+#define UART0_THR_THR_Pos                 (0UL)                     /*!< UART0 THR: THR (Bit 0)                                */
+#define UART0_THR_THR_Msk                 (0xffUL)                  /*!< UART0 THR: THR (Bitfield-Mask: 0xff)                  */
+/* ==========================================================  IER  ========================================================== */
+#define UART0_IER_TXEIE_Pos               (3UL)                     /*!< UART0 IER: TXEIE (Bit 3)                              */
+#define UART0_IER_TXEIE_Msk               (0x8UL)                   /*!< UART0 IER: TXEIE (Bitfield-Mask: 0x01)                */
+#define UART0_IER_RLSIE_Pos               (2UL)                     /*!< UART0 IER: RLSIE (Bit 2)                              */
+#define UART0_IER_RLSIE_Msk               (0x4UL)                   /*!< UART0 IER: RLSIE (Bitfield-Mask: 0x01)                */
+#define UART0_IER_THREIE_Pos              (1UL)                     /*!< UART0 IER: THREIE (Bit 1)                             */
+#define UART0_IER_THREIE_Msk              (0x2UL)                   /*!< UART0 IER: THREIE (Bitfield-Mask: 0x01)               */
+#define UART0_IER_DRIE_Pos                (0UL)                     /*!< UART0 IER: DRIE (Bit 0)                               */
+#define UART0_IER_DRIE_Msk                (0x1UL)                   /*!< UART0 IER: DRIE (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  IIR  ========================================================== */
+#define UART0_IIR_TXE_Pos                 (4UL)                     /*!< UART0 IIR: TXE (Bit 4)                                */
+#define UART0_IIR_TXE_Msk                 (0x10UL)                  /*!< UART0 IIR: TXE (Bitfield-Mask: 0x01)                  */
+#define UART0_IIR_IID_Pos                 (1UL)                     /*!< UART0 IIR: IID (Bit 1)                                */
+#define UART0_IIR_IID_Msk                 (0x6UL)                   /*!< UART0 IIR: IID (Bitfield-Mask: 0x03)                  */
+#define UART0_IIR_IPEN_Pos                (0UL)                     /*!< UART0 IIR: IPEN (Bit 0)                               */
+#define UART0_IIR_IPEN_Msk                (0x1UL)                   /*!< UART0 IIR: IPEN (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  LCR  ========================================================== */
+#define UART0_LCR_BREAK_Pos               (6UL)                     /*!< UART0 LCR: BREAK (Bit 6)                              */
+#define UART0_LCR_BREAK_Msk               (0x40UL)                  /*!< UART0 LCR: BREAK (Bitfield-Mask: 0x01)                */
+#define UART0_LCR_STICKP_Pos              (5UL)                     /*!< UART0 LCR: STICKP (Bit 5)                             */
+#define UART0_LCR_STICKP_Msk              (0x20UL)                  /*!< UART0 LCR: STICKP (Bitfield-Mask: 0x01)               */
+#define UART0_LCR_PARITY_Pos              (4UL)                     /*!< UART0 LCR: PARITY (Bit 4)                             */
+#define UART0_LCR_PARITY_Msk              (0x10UL)                  /*!< UART0 LCR: PARITY (Bitfield-Mask: 0x01)               */
+#define UART0_LCR_PEN_Pos                 (3UL)                     /*!< UART0 LCR: PEN (Bit 3)                                */
+#define UART0_LCR_PEN_Msk                 (0x8UL)                   /*!< UART0 LCR: PEN (Bitfield-Mask: 0x01)                  */
+#define UART0_LCR_STOPBIT_Pos             (2UL)                     /*!< UART0 LCR: STOPBIT (Bit 2)                            */
+#define UART0_LCR_STOPBIT_Msk             (0x4UL)                   /*!< UART0 LCR: STOPBIT (Bitfield-Mask: 0x01)              */
+#define UART0_LCR_DLEN_Pos                (0UL)                     /*!< UART0 LCR: DLEN (Bit 0)                               */
+#define UART0_LCR_DLEN_Msk                (0x3UL)                   /*!< UART0 LCR: DLEN (Bitfield-Mask: 0x03)                 */
+/* ==========================================================  DCR  ========================================================== */
+#define UART0_DCR_LBON_Pos                (4UL)                     /*!< UART0 DCR: LBON (Bit 4)                               */
+#define UART0_DCR_LBON_Msk                (0x10UL)                  /*!< UART0 DCR: LBON (Bitfield-Mask: 0x01)                 */
+#define UART0_DCR_RXINV_Pos               (3UL)                     /*!< UART0 DCR: RXINV (Bit 3)                              */
+#define UART0_DCR_RXINV_Msk               (0x8UL)                   /*!< UART0 DCR: RXINV (Bitfield-Mask: 0x01)                */
+#define UART0_DCR_TXINV_Pos               (2UL)                     /*!< UART0 DCR: TXINV (Bit 2)                              */
+#define UART0_DCR_TXINV_Msk               (0x4UL)                   /*!< UART0 DCR: TXINV (Bitfield-Mask: 0x01)                */
+/* ==========================================================  LSR  ========================================================== */
+#define UART0_LSR_TEMT_Pos                (6UL)                     /*!< UART0 LSR: TEMT (Bit 6)                               */
+#define UART0_LSR_TEMT_Msk                (0x40UL)                  /*!< UART0 LSR: TEMT (Bitfield-Mask: 0x01)                 */
+#define UART0_LSR_THRE_Pos                (5UL)                     /*!< UART0 LSR: THRE (Bit 5)                               */
+#define UART0_LSR_THRE_Msk                (0x20UL)                  /*!< UART0 LSR: THRE (Bitfield-Mask: 0x01)                 */
+#define UART0_LSR_BI_Pos                  (4UL)                     /*!< UART0 LSR: BI (Bit 4)                                 */
+#define UART0_LSR_BI_Msk                  (0x10UL)                  /*!< UART0 LSR: BI (Bitfield-Mask: 0x01)                   */
+#define UART0_LSR_FE_Pos                  (3UL)                     /*!< UART0 LSR: FE (Bit 3)                                 */
+#define UART0_LSR_FE_Msk                  (0x8UL)                   /*!< UART0 LSR: FE (Bitfield-Mask: 0x01)                   */
+#define UART0_LSR_PE_Pos                  (2UL)                     /*!< UART0 LSR: PE (Bit 2)                                 */
+#define UART0_LSR_PE_Msk                  (0x4UL)                   /*!< UART0 LSR: PE (Bitfield-Mask: 0x01)                   */
+#define UART0_LSR_OE_Pos                  (1UL)                     /*!< UART0 LSR: OE (Bit 1)                                 */
+#define UART0_LSR_OE_Msk                  (0x2UL)                   /*!< UART0 LSR: OE (Bitfield-Mask: 0x01)                   */
+#define UART0_LSR_DR_Pos                  (0UL)                     /*!< UART0 LSR: DR (Bit 0)                                 */
+#define UART0_LSR_DR_Msk                  (0x1UL)                   /*!< UART0 LSR: DR (Bitfield-Mask: 0x01)                   */
+/* ==========================================================  BDR  ========================================================== */
+#define UART0_BDR_BDR_Pos                 (0UL)                     /*!< UART0 BDR: BDR (Bit 0)                                */
+#define UART0_BDR_BDR_Msk                 (0xffffUL)                /*!< UART0 BDR: BDR (Bitfield-Mask: 0xffff)                */
+/* ==========================================================  BFR  ========================================================== */
+#define UART0_BFR_BFR_Pos                 (0UL)                     /*!< UART0 BFR: BFR (Bit 0)                                */
+#define UART0_BFR_BFR_Msk                 (0xffUL)                  /*!< UART0 BFR: BFR (Bitfield-Mask: 0xff)                  */
+/* =========================================================  IDTR  ========================================================== */
+#define UART0_IDTR_SMS_Pos                (7UL)                     /*!< UART0 IDTR: SMS (Bit 7)                               */
+#define UART0_IDTR_SMS_Msk                (0x80UL)                  /*!< UART0 IDTR: SMS (Bitfield-Mask: 0x01)                 */
+#define UART0_IDTR_DMS_Pos                (6UL)                     /*!< UART0 IDTR: DMS (Bit 6)                               */
+#define UART0_IDTR_DMS_Msk                (0x40UL)                  /*!< UART0 IDTR: DMS (Bitfield-Mask: 0x01)                 */
+#define UART0_IDTR_WAITVAL_Pos            (0UL)                     /*!< UART0 IDTR: WAITVAL (Bit 0)                           */
+#define UART0_IDTR_WAITVAL_Msk            (0x7UL)                   /*!< UART0 IDTR: WAITVAL (Bitfield-Mask: 0x07)             */
+
+
+/* =========================================================================================================================== */
+/* ================                                           UART1                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  RBR  ========================================================== */
+#define UART1_RBR_RBR_Pos                 (0UL)                     /*!< UART1 RBR: RBR (Bit 0)                                */
+#define UART1_RBR_RBR_Msk                 (0xffUL)                  /*!< UART1 RBR: RBR (Bitfield-Mask: 0xff)                  */
+/* ==========================================================  THR  ========================================================== */
+#define UART1_THR_THR_Pos                 (0UL)                     /*!< UART1 THR: THR (Bit 0)                                */
+#define UART1_THR_THR_Msk                 (0xffUL)                  /*!< UART1 THR: THR (Bitfield-Mask: 0xff)                  */
+/* ==========================================================  IER  ========================================================== */
+#define UART1_IER_TXEIE_Pos               (3UL)                     /*!< UART1 IER: TXEIE (Bit 3)                              */
+#define UART1_IER_TXEIE_Msk               (0x8UL)                   /*!< UART1 IER: TXEIE (Bitfield-Mask: 0x01)                */
+#define UART1_IER_RLSIE_Pos               (2UL)                     /*!< UART1 IER: RLSIE (Bit 2)                              */
+#define UART1_IER_RLSIE_Msk               (0x4UL)                   /*!< UART1 IER: RLSIE (Bitfield-Mask: 0x01)                */
+#define UART1_IER_THREIE_Pos              (1UL)                     /*!< UART1 IER: THREIE (Bit 1)                             */
+#define UART1_IER_THREIE_Msk              (0x2UL)                   /*!< UART1 IER: THREIE (Bitfield-Mask: 0x01)               */
+#define UART1_IER_DRIE_Pos                (0UL)                     /*!< UART1 IER: DRIE (Bit 0)                               */
+#define UART1_IER_DRIE_Msk                (0x1UL)                   /*!< UART1 IER: DRIE (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  IIR  ========================================================== */
+#define UART1_IIR_TXE_Pos                 (4UL)                     /*!< UART1 IIR: TXE (Bit 4)                                */
+#define UART1_IIR_TXE_Msk                 (0x10UL)                  /*!< UART1 IIR: TXE (Bitfield-Mask: 0x01)                  */
+#define UART1_IIR_IID_Pos                 (1UL)                     /*!< UART1 IIR: IID (Bit 1)                                */
+#define UART1_IIR_IID_Msk                 (0x6UL)                   /*!< UART1 IIR: IID (Bitfield-Mask: 0x03)                  */
+#define UART1_IIR_IPEN_Pos                (0UL)                     /*!< UART1 IIR: IPEN (Bit 0)                               */
+#define UART1_IIR_IPEN_Msk                (0x1UL)                   /*!< UART1 IIR: IPEN (Bitfield-Mask: 0x01)                 */
+/* ==========================================================  LCR  ========================================================== */
+#define UART1_LCR_BREAK_Pos               (6UL)                     /*!< UART1 LCR: BREAK (Bit 6)                              */
+#define UART1_LCR_BREAK_Msk               (0x40UL)                  /*!< UART1 LCR: BREAK (Bitfield-Mask: 0x01)                */
+#define UART1_LCR_STICKP_Pos              (5UL)                     /*!< UART1 LCR: STICKP (Bit 5)                             */
+#define UART1_LCR_STICKP_Msk              (0x20UL)                  /*!< UART1 LCR: STICKP (Bitfield-Mask: 0x01)               */
+#define UART1_LCR_PARITY_Pos              (4UL)                     /*!< UART1 LCR: PARITY (Bit 4)                             */
+#define UART1_LCR_PARITY_Msk              (0x10UL)                  /*!< UART1 LCR: PARITY (Bitfield-Mask: 0x01)               */
+#define UART1_LCR_PEN_Pos                 (3UL)                     /*!< UART1 LCR: PEN (Bit 3)                                */
+#define UART1_LCR_PEN_Msk                 (0x8UL)                   /*!< UART1 LCR: PEN (Bitfield-Mask: 0x01)                  */
+#define UART1_LCR_STOPBIT_Pos             (2UL)                     /*!< UART1 LCR: STOPBIT (Bit 2)                            */
+#define UART1_LCR_STOPBIT_Msk             (0x4UL)                   /*!< UART1 LCR: STOPBIT (Bitfield-Mask: 0x01)              */
+#define UART1_LCR_DLEN_Pos                (0UL)                     /*!< UART1 LCR: DLEN (Bit 0)                               */
+#define UART1_LCR_DLEN_Msk                (0x3UL)                   /*!< UART1 LCR: DLEN (Bitfield-Mask: 0x03)                 */
+/* ==========================================================  DCR  ========================================================== */
+#define UART1_DCR_LBON_Pos                (4UL)                     /*!< UART1 DCR: LBON (Bit 4)                               */
+#define UART1_DCR_LBON_Msk                (0x10UL)                  /*!< UART1 DCR: LBON (Bitfield-Mask: 0x01)                 */
+#define UART1_DCR_RXINV_Pos               (3UL)                     /*!< UART1 DCR: RXINV (Bit 3)                              */
+#define UART1_DCR_RXINV_Msk               (0x8UL)                   /*!< UART1 DCR: RXINV (Bitfield-Mask: 0x01)                */
+#define UART1_DCR_TXINV_Pos               (2UL)                     /*!< UART1 DCR: TXINV (Bit 2)                              */
+#define UART1_DCR_TXINV_Msk               (0x4UL)                   /*!< UART1 DCR: TXINV (Bitfield-Mask: 0x01)                */
+/* ==========================================================  LSR  ========================================================== */
+#define UART1_LSR_TEMT_Pos                (6UL)                     /*!< UART1 LSR: TEMT (Bit 6)                               */
+#define UART1_LSR_TEMT_Msk                (0x40UL)                  /*!< UART1 LSR: TEMT (Bitfield-Mask: 0x01)                 */
+#define UART1_LSR_THRE_Pos                (5UL)                     /*!< UART1 LSR: THRE (Bit 5)                               */
+#define UART1_LSR_THRE_Msk                (0x20UL)                  /*!< UART1 LSR: THRE (Bitfield-Mask: 0x01)                 */
+#define UART1_LSR_BI_Pos                  (4UL)                     /*!< UART1 LSR: BI (Bit 4)                                 */
+#define UART1_LSR_BI_Msk                  (0x10UL)                  /*!< UART1 LSR: BI (Bitfield-Mask: 0x01)                   */
+#define UART1_LSR_FE_Pos                  (3UL)                     /*!< UART1 LSR: FE (Bit 3)                                 */
+#define UART1_LSR_FE_Msk                  (0x8UL)                   /*!< UART1 LSR: FE (Bitfield-Mask: 0x01)                   */
+#define UART1_LSR_PE_Pos                  (2UL)                     /*!< UART1 LSR: PE (Bit 2)                                 */
+#define UART1_LSR_PE_Msk                  (0x4UL)                   /*!< UART1 LSR: PE (Bitfield-Mask: 0x01)                   */
+#define UART1_LSR_OE_Pos                  (1UL)                     /*!< UART1 LSR: OE (Bit 1)                                 */
+#define UART1_LSR_OE_Msk                  (0x2UL)                   /*!< UART1 LSR: OE (Bitfield-Mask: 0x01)                   */
+#define UART1_LSR_DR_Pos                  (0UL)                     /*!< UART1 LSR: DR (Bit 0)                                 */
+#define UART1_LSR_DR_Msk                  (0x1UL)                   /*!< UART1 LSR: DR (Bitfield-Mask: 0x01)                   */
+/* ==========================================================  BDR  ========================================================== */
+#define UART1_BDR_BDR_Pos                 (0UL)                     /*!< UART1 BDR: BDR (Bit 0)                                */
+#define UART1_BDR_BDR_Msk                 (0xffffUL)                /*!< UART1 BDR: BDR (Bitfield-Mask: 0xffff)                */
+/* ==========================================================  BFR  ========================================================== */
+#define UART1_BFR_BFR_Pos                 (0UL)                     /*!< UART1 BFR: BFR (Bit 0)                                */
+#define UART1_BFR_BFR_Msk                 (0xffUL)                  /*!< UART1 BFR: BFR (Bitfield-Mask: 0xff)                  */
+/* =========================================================  IDTR  ========================================================== */
+#define UART1_IDTR_SMS_Pos                (7UL)                     /*!< UART1 IDTR: SMS (Bit 7)                               */
+#define UART1_IDTR_SMS_Msk                (0x80UL)                  /*!< UART1 IDTR: SMS (Bitfield-Mask: 0x01)                 */
+#define UART1_IDTR_DMS_Pos                (6UL)                     /*!< UART1 IDTR: DMS (Bit 6)                               */
+#define UART1_IDTR_DMS_Msk                (0x40UL)                  /*!< UART1 IDTR: DMS (Bitfield-Mask: 0x01)                 */
+#define UART1_IDTR_WAITVAL_Pos            (0UL)                     /*!< UART1 IDTR: WAITVAL (Bit 0)                           */
+#define UART1_IDTR_WAITVAL_Msk            (0x7UL)                   /*!< UART1 IDTR: WAITVAL (Bitfield-Mask: 0x07)             */
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2Cn                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define I2Cn_CR_I2CnEN_Pos                (7UL)                     /*!< I2Cn CR: I2CnEN (Bit 7)                               */
+#define I2Cn_CR_I2CnEN_Msk                (0x80UL)                  /*!< I2Cn CR: I2CnEN (Bitfield-Mask: 0x01)                 */
+#define I2Cn_CR_TXDLYENBn_Pos             (6UL)                     /*!< I2Cn CR: TXDLYENBn (Bit 6)                            */
+#define I2Cn_CR_TXDLYENBn_Msk             (0x40UL)                  /*!< I2Cn CR: TXDLYENBn (Bitfield-Mask: 0x01)              */
+#define I2Cn_CR_I2CnIEN_Pos               (5UL)                     /*!< I2Cn CR: I2CnIEN (Bit 5)                              */
+#define I2Cn_CR_I2CnIEN_Msk               (0x20UL)                  /*!< I2Cn CR: I2CnIEN (Bitfield-Mask: 0x01)                */
+#define I2Cn_CR_I2CnIFLAG_Pos             (4UL)                     /*!< I2Cn CR: I2CnIFLAG (Bit 4)                            */
+#define I2Cn_CR_I2CnIFLAG_Msk             (0x10UL)                  /*!< I2Cn CR: I2CnIFLAG (Bitfield-Mask: 0x01)              */
+#define I2Cn_CR_ACKnEN_Pos                (3UL)                     /*!< I2Cn CR: ACKnEN (Bit 3)                               */
+#define I2Cn_CR_ACKnEN_Msk                (0x8UL)                   /*!< I2Cn CR: ACKnEN (Bitfield-Mask: 0x01)                 */
+#define I2Cn_CR_IMASTERn_Pos              (2UL)                     /*!< I2Cn CR: IMASTERn (Bit 2)                             */
+#define I2Cn_CR_IMASTERn_Msk              (0x4UL)                   /*!< I2Cn CR: IMASTERn (Bitfield-Mask: 0x01)               */
+#define I2Cn_CR_STOPCn_Pos                (1UL)                     /*!< I2Cn CR: STOPCn (Bit 1)                               */
+#define I2Cn_CR_STOPCn_Msk                (0x2UL)                   /*!< I2Cn CR: STOPCn (Bitfield-Mask: 0x01)                 */
+#define I2Cn_CR_STARTCn_Pos               (0UL)                     /*!< I2Cn CR: STARTCn (Bit 0)                              */
+#define I2Cn_CR_STARTCn_Msk               (0x1UL)                   /*!< I2Cn CR: STARTCn (Bitfield-Mask: 0x01)                */
+/* ==========================================================  ST  =========================================================== */
+#define I2Cn_ST_GCALLn_Pos                (7UL)                     /*!< I2Cn ST: GCALLn (Bit 7)                               */
+#define I2Cn_ST_GCALLn_Msk                (0x80UL)                  /*!< I2Cn ST: GCALLn (Bitfield-Mask: 0x01)                 */
+#define I2Cn_ST_TENDn_Pos                 (6UL)                     /*!< I2Cn ST: TENDn (Bit 6)                                */
+#define I2Cn_ST_TENDn_Msk                 (0x40UL)                  /*!< I2Cn ST: TENDn (Bitfield-Mask: 0x01)                  */
+#define I2Cn_ST_STOPDn_Pos                (5UL)                     /*!< I2Cn ST: STOPDn (Bit 5)                               */
+#define I2Cn_ST_STOPDn_Msk                (0x20UL)                  /*!< I2Cn ST: STOPDn (Bitfield-Mask: 0x01)                 */
+#define I2Cn_ST_SSELn_Pos                 (4UL)                     /*!< I2Cn ST: SSELn (Bit 4)                                */
+#define I2Cn_ST_SSELn_Msk                 (0x10UL)                  /*!< I2Cn ST: SSELn (Bitfield-Mask: 0x01)                  */
+#define I2Cn_ST_MLOSTn_Pos                (3UL)                     /*!< I2Cn ST: MLOSTn (Bit 3)                               */
+#define I2Cn_ST_MLOSTn_Msk                (0x8UL)                   /*!< I2Cn ST: MLOSTn (Bitfield-Mask: 0x01)                 */
+#define I2Cn_ST_BUSYn_Pos                 (2UL)                     /*!< I2Cn ST: BUSYn (Bit 2)                                */
+#define I2Cn_ST_BUSYn_Msk                 (0x4UL)                   /*!< I2Cn ST: BUSYn (Bitfield-Mask: 0x01)                  */
+#define I2Cn_ST_TMODEn_Pos                (1UL)                     /*!< I2Cn ST: TMODEn (Bit 1)                               */
+#define I2Cn_ST_TMODEn_Msk                (0x2UL)                   /*!< I2Cn ST: TMODEn (Bitfield-Mask: 0x01)                 */
+#define I2Cn_ST_RXACKn_Pos                (0UL)                     /*!< I2Cn ST: RXACKn (Bit 0)                               */
+#define I2Cn_ST_RXACKn_Msk                (0x1UL)                   /*!< I2Cn ST: RXACKn (Bitfield-Mask: 0x01)                 */
+/* =========================================================  SAR1  ========================================================== */
+#define I2Cn_SAR1_SLAn_Pos                (1UL)                     /*!< I2Cn SAR1: SLAn (Bit 1)                               */
+#define I2Cn_SAR1_SLAn_Msk                (0xfeUL)                  /*!< I2Cn SAR1: SLAn (Bitfield-Mask: 0x7f)                 */
+#define I2Cn_SAR1_GCALLnEN_Pos            (0UL)                     /*!< I2Cn SAR1: GCALLnEN (Bit 0)                           */
+#define I2Cn_SAR1_GCALLnEN_Msk            (0x1UL)                   /*!< I2Cn SAR1: GCALLnEN (Bitfield-Mask: 0x01)             */
+/* =========================================================  SAR2  ========================================================== */
+#define I2Cn_SAR2_SLAn_Pos                (1UL)                     /*!< I2Cn SAR2: SLAn (Bit 1)                               */
+#define I2Cn_SAR2_SLAn_Msk                (0xfeUL)                  /*!< I2Cn SAR2: SLAn (Bitfield-Mask: 0x7f)                 */
+#define I2Cn_SAR2_GCALLnEN_Pos            (0UL)                     /*!< I2Cn SAR2: GCALLnEN (Bit 0)                           */
+#define I2Cn_SAR2_GCALLnEN_Msk            (0x1UL)                   /*!< I2Cn SAR2: GCALLnEN (Bitfield-Mask: 0x01)             */
+/* ==========================================================  DR  =========================================================== */
+#define I2Cn_DR_DATA_Pos                  (0UL)                     /*!< I2Cn DR: DATA (Bit 0)                                 */
+#define I2Cn_DR_DATA_Msk                  (0xffUL)                  /*!< I2Cn DR: DATA (Bitfield-Mask: 0xff)                   */
+/* =========================================================  SDHR  ========================================================== */
+#define I2Cn_SDHR_HLDT_Pos                (0UL)                     /*!< I2Cn SDHR: HLDT (Bit 0)                               */
+#define I2Cn_SDHR_HLDT_Msk                (0xfffUL)                 /*!< I2Cn SDHR: HLDT (Bitfield-Mask: 0xfff)                */
+/* =========================================================  SCLR  ========================================================== */
+#define I2Cn_SCLR_SCLL_Pos                (0UL)                     /*!< I2Cn SCLR: SCLL (Bit 0)                               */
+#define I2Cn_SCLR_SCLL_Msk                (0xfffUL)                 /*!< I2Cn SCLR: SCLL (Bitfield-Mask: 0xfff)                */
+/* =========================================================  SCHR  ========================================================== */
+#define I2Cn_SCHR_SCLH_Pos                (0UL)                     /*!< I2Cn SCHR: SCLH (Bit 0)                               */
+#define I2Cn_SCHR_SCLH_Msk                (0xfffUL)                 /*!< I2Cn SCHR: SCLH (Bitfield-Mask: 0xfff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C0                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define I2C0_CR_I2CnEN_Pos                (7UL)                     /*!< I2C0 CR: I2CnEN (Bit 7)                               */
+#define I2C0_CR_I2CnEN_Msk                (0x80UL)                  /*!< I2C0 CR: I2CnEN (Bitfield-Mask: 0x01)                 */
+#define I2C0_CR_TXDLYENBn_Pos             (6UL)                     /*!< I2C0 CR: TXDLYENBn (Bit 6)                            */
+#define I2C0_CR_TXDLYENBn_Msk             (0x40UL)                  /*!< I2C0 CR: TXDLYENBn (Bitfield-Mask: 0x01)              */
+#define I2C0_CR_I2CnIEN_Pos               (5UL)                     /*!< I2C0 CR: I2CnIEN (Bit 5)                              */
+#define I2C0_CR_I2CnIEN_Msk               (0x20UL)                  /*!< I2C0 CR: I2CnIEN (Bitfield-Mask: 0x01)                */
+#define I2C0_CR_I2CnIFLAG_Pos             (4UL)                     /*!< I2C0 CR: I2CnIFLAG (Bit 4)                            */
+#define I2C0_CR_I2CnIFLAG_Msk             (0x10UL)                  /*!< I2C0 CR: I2CnIFLAG (Bitfield-Mask: 0x01)              */
+#define I2C0_CR_ACKnEN_Pos                (3UL)                     /*!< I2C0 CR: ACKnEN (Bit 3)                               */
+#define I2C0_CR_ACKnEN_Msk                (0x8UL)                   /*!< I2C0 CR: ACKnEN (Bitfield-Mask: 0x01)                 */
+#define I2C0_CR_IMASTERn_Pos              (2UL)                     /*!< I2C0 CR: IMASTERn (Bit 2)                             */
+#define I2C0_CR_IMASTERn_Msk              (0x4UL)                   /*!< I2C0 CR: IMASTERn (Bitfield-Mask: 0x01)               */
+#define I2C0_CR_STOPCn_Pos                (1UL)                     /*!< I2C0 CR: STOPCn (Bit 1)                               */
+#define I2C0_CR_STOPCn_Msk                (0x2UL)                   /*!< I2C0 CR: STOPCn (Bitfield-Mask: 0x01)                 */
+#define I2C0_CR_STARTCn_Pos               (0UL)                     /*!< I2C0 CR: STARTCn (Bit 0)                              */
+#define I2C0_CR_STARTCn_Msk               (0x1UL)                   /*!< I2C0 CR: STARTCn (Bitfield-Mask: 0x01)                */
+/* ==========================================================  ST  =========================================================== */
+#define I2C0_ST_GCALLn_Pos                (7UL)                     /*!< I2C0 ST: GCALLn (Bit 7)                               */
+#define I2C0_ST_GCALLn_Msk                (0x80UL)                  /*!< I2C0 ST: GCALLn (Bitfield-Mask: 0x01)                 */
+#define I2C0_ST_TENDn_Pos                 (6UL)                     /*!< I2C0 ST: TENDn (Bit 6)                                */
+#define I2C0_ST_TENDn_Msk                 (0x40UL)                  /*!< I2C0 ST: TENDn (Bitfield-Mask: 0x01)                  */
+#define I2C0_ST_STOPDn_Pos                (5UL)                     /*!< I2C0 ST: STOPDn (Bit 5)                               */
+#define I2C0_ST_STOPDn_Msk                (0x20UL)                  /*!< I2C0 ST: STOPDn (Bitfield-Mask: 0x01)                 */
+#define I2C0_ST_SSELn_Pos                 (4UL)                     /*!< I2C0 ST: SSELn (Bit 4)                                */
+#define I2C0_ST_SSELn_Msk                 (0x10UL)                  /*!< I2C0 ST: SSELn (Bitfield-Mask: 0x01)                  */
+#define I2C0_ST_MLOSTn_Pos                (3UL)                     /*!< I2C0 ST: MLOSTn (Bit 3)                               */
+#define I2C0_ST_MLOSTn_Msk                (0x8UL)                   /*!< I2C0 ST: MLOSTn (Bitfield-Mask: 0x01)                 */
+#define I2C0_ST_BUSYn_Pos                 (2UL)                     /*!< I2C0 ST: BUSYn (Bit 2)                                */
+#define I2C0_ST_BUSYn_Msk                 (0x4UL)                   /*!< I2C0 ST: BUSYn (Bitfield-Mask: 0x01)                  */
+#define I2C0_ST_TMODEn_Pos                (1UL)                     /*!< I2C0 ST: TMODEn (Bit 1)                               */
+#define I2C0_ST_TMODEn_Msk                (0x2UL)                   /*!< I2C0 ST: TMODEn (Bitfield-Mask: 0x01)                 */
+#define I2C0_ST_RXACKn_Pos                (0UL)                     /*!< I2C0 ST: RXACKn (Bit 0)                               */
+#define I2C0_ST_RXACKn_Msk                (0x1UL)                   /*!< I2C0 ST: RXACKn (Bitfield-Mask: 0x01)                 */
+/* =========================================================  SAR1  ========================================================== */
+#define I2C0_SAR1_SLAn_Pos                (1UL)                     /*!< I2C0 SAR1: SLAn (Bit 1)                               */
+#define I2C0_SAR1_SLAn_Msk                (0xfeUL)                  /*!< I2C0 SAR1: SLAn (Bitfield-Mask: 0x7f)                 */
+#define I2C0_SAR1_GCALLnEN_Pos            (0UL)                     /*!< I2C0 SAR1: GCALLnEN (Bit 0)                           */
+#define I2C0_SAR1_GCALLnEN_Msk            (0x1UL)                   /*!< I2C0 SAR1: GCALLnEN (Bitfield-Mask: 0x01)             */
+/* =========================================================  SAR2  ========================================================== */
+#define I2C0_SAR2_SLAn_Pos                (1UL)                     /*!< I2C0 SAR2: SLAn (Bit 1)                               */
+#define I2C0_SAR2_SLAn_Msk                (0xfeUL)                  /*!< I2C0 SAR2: SLAn (Bitfield-Mask: 0x7f)                 */
+#define I2C0_SAR2_GCALLnEN_Pos            (0UL)                     /*!< I2C0 SAR2: GCALLnEN (Bit 0)                           */
+#define I2C0_SAR2_GCALLnEN_Msk            (0x1UL)                   /*!< I2C0 SAR2: GCALLnEN (Bitfield-Mask: 0x01)             */
+/* ==========================================================  DR  =========================================================== */
+#define I2C0_DR_DATA_Pos                  (0UL)                     /*!< I2C0 DR: DATA (Bit 0)                                 */
+#define I2C0_DR_DATA_Msk                  (0xffUL)                  /*!< I2C0 DR: DATA (Bitfield-Mask: 0xff)                   */
+/* =========================================================  SDHR  ========================================================== */
+#define I2C0_SDHR_HLDT_Pos                (0UL)                     /*!< I2C0 SDHR: HLDT (Bit 0)                               */
+#define I2C0_SDHR_HLDT_Msk                (0xfffUL)                 /*!< I2C0 SDHR: HLDT (Bitfield-Mask: 0xfff)                */
+/* =========================================================  SCLR  ========================================================== */
+#define I2C0_SCLR_SCLL_Pos                (0UL)                     /*!< I2C0 SCLR: SCLL (Bit 0)                               */
+#define I2C0_SCLR_SCLL_Msk                (0xfffUL)                 /*!< I2C0 SCLR: SCLL (Bitfield-Mask: 0xfff)                */
+/* =========================================================  SCHR  ========================================================== */
+#define I2C0_SCHR_SCLH_Pos                (0UL)                     /*!< I2C0 SCHR: SCLH (Bit 0)                               */
+#define I2C0_SCHR_SCLH_Msk                (0xfffUL)                 /*!< I2C0 SCHR: SCLH (Bitfield-Mask: 0xfff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C1                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define I2C1_CR_I2CnEN_Pos                (7UL)                     /*!< I2C1 CR: I2CnEN (Bit 7)                               */
+#define I2C1_CR_I2CnEN_Msk                (0x80UL)                  /*!< I2C1 CR: I2CnEN (Bitfield-Mask: 0x01)                 */
+#define I2C1_CR_TXDLYENBn_Pos             (6UL)                     /*!< I2C1 CR: TXDLYENBn (Bit 6)                            */
+#define I2C1_CR_TXDLYENBn_Msk             (0x40UL)                  /*!< I2C1 CR: TXDLYENBn (Bitfield-Mask: 0x01)              */
+#define I2C1_CR_I2CnIEN_Pos               (5UL)                     /*!< I2C1 CR: I2CnIEN (Bit 5)                              */
+#define I2C1_CR_I2CnIEN_Msk               (0x20UL)                  /*!< I2C1 CR: I2CnIEN (Bitfield-Mask: 0x01)                */
+#define I2C1_CR_I2CnIFLAG_Pos             (4UL)                     /*!< I2C1 CR: I2CnIFLAG (Bit 4)                            */
+#define I2C1_CR_I2CnIFLAG_Msk             (0x10UL)                  /*!< I2C1 CR: I2CnIFLAG (Bitfield-Mask: 0x01)              */
+#define I2C1_CR_ACKnEN_Pos                (3UL)                     /*!< I2C1 CR: ACKnEN (Bit 3)                               */
+#define I2C1_CR_ACKnEN_Msk                (0x8UL)                   /*!< I2C1 CR: ACKnEN (Bitfield-Mask: 0x01)                 */
+#define I2C1_CR_IMASTERn_Pos              (2UL)                     /*!< I2C1 CR: IMASTERn (Bit 2)                             */
+#define I2C1_CR_IMASTERn_Msk              (0x4UL)                   /*!< I2C1 CR: IMASTERn (Bitfield-Mask: 0x01)               */
+#define I2C1_CR_STOPCn_Pos                (1UL)                     /*!< I2C1 CR: STOPCn (Bit 1)                               */
+#define I2C1_CR_STOPCn_Msk                (0x2UL)                   /*!< I2C1 CR: STOPCn (Bitfield-Mask: 0x01)                 */
+#define I2C1_CR_STARTCn_Pos               (0UL)                     /*!< I2C1 CR: STARTCn (Bit 0)                              */
+#define I2C1_CR_STARTCn_Msk               (0x1UL)                   /*!< I2C1 CR: STARTCn (Bitfield-Mask: 0x01)                */
+/* ==========================================================  ST  =========================================================== */
+#define I2C1_ST_GCALLn_Pos                (7UL)                     /*!< I2C1 ST: GCALLn (Bit 7)                               */
+#define I2C1_ST_GCALLn_Msk                (0x80UL)                  /*!< I2C1 ST: GCALLn (Bitfield-Mask: 0x01)                 */
+#define I2C1_ST_TENDn_Pos                 (6UL)                     /*!< I2C1 ST: TENDn (Bit 6)                                */
+#define I2C1_ST_TENDn_Msk                 (0x40UL)                  /*!< I2C1 ST: TENDn (Bitfield-Mask: 0x01)                  */
+#define I2C1_ST_STOPDn_Pos                (5UL)                     /*!< I2C1 ST: STOPDn (Bit 5)                               */
+#define I2C1_ST_STOPDn_Msk                (0x20UL)                  /*!< I2C1 ST: STOPDn (Bitfield-Mask: 0x01)                 */
+#define I2C1_ST_SSELn_Pos                 (4UL)                     /*!< I2C1 ST: SSELn (Bit 4)                                */
+#define I2C1_ST_SSELn_Msk                 (0x10UL)                  /*!< I2C1 ST: SSELn (Bitfield-Mask: 0x01)                  */
+#define I2C1_ST_MLOSTn_Pos                (3UL)                     /*!< I2C1 ST: MLOSTn (Bit 3)                               */
+#define I2C1_ST_MLOSTn_Msk                (0x8UL)                   /*!< I2C1 ST: MLOSTn (Bitfield-Mask: 0x01)                 */
+#define I2C1_ST_BUSYn_Pos                 (2UL)                     /*!< I2C1 ST: BUSYn (Bit 2)                                */
+#define I2C1_ST_BUSYn_Msk                 (0x4UL)                   /*!< I2C1 ST: BUSYn (Bitfield-Mask: 0x01)                  */
+#define I2C1_ST_TMODEn_Pos                (1UL)                     /*!< I2C1 ST: TMODEn (Bit 1)                               */
+#define I2C1_ST_TMODEn_Msk                (0x2UL)                   /*!< I2C1 ST: TMODEn (Bitfield-Mask: 0x01)                 */
+#define I2C1_ST_RXACKn_Pos                (0UL)                     /*!< I2C1 ST: RXACKn (Bit 0)                               */
+#define I2C1_ST_RXACKn_Msk                (0x1UL)                   /*!< I2C1 ST: RXACKn (Bitfield-Mask: 0x01)                 */
+/* =========================================================  SAR1  ========================================================== */
+#define I2C1_SAR1_SLAn_Pos                (1UL)                     /*!< I2C1 SAR1: SLAn (Bit 1)                               */
+#define I2C1_SAR1_SLAn_Msk                (0xfeUL)                  /*!< I2C1 SAR1: SLAn (Bitfield-Mask: 0x7f)                 */
+#define I2C1_SAR1_GCALLnEN_Pos            (0UL)                     /*!< I2C1 SAR1: GCALLnEN (Bit 0)                           */
+#define I2C1_SAR1_GCALLnEN_Msk            (0x1UL)                   /*!< I2C1 SAR1: GCALLnEN (Bitfield-Mask: 0x01)             */
+/* =========================================================  SAR2  ========================================================== */
+#define I2C1_SAR2_SLAn_Pos                (1UL)                     /*!< I2C1 SAR2: SLAn (Bit 1)                               */
+#define I2C1_SAR2_SLAn_Msk                (0xfeUL)                  /*!< I2C1 SAR2: SLAn (Bitfield-Mask: 0x7f)                 */
+#define I2C1_SAR2_GCALLnEN_Pos            (0UL)                     /*!< I2C1 SAR2: GCALLnEN (Bit 0)                           */
+#define I2C1_SAR2_GCALLnEN_Msk            (0x1UL)                   /*!< I2C1 SAR2: GCALLnEN (Bitfield-Mask: 0x01)             */
+/* ==========================================================  DR  =========================================================== */
+#define I2C1_DR_DATA_Pos                  (0UL)                     /*!< I2C1 DR: DATA (Bit 0)                                 */
+#define I2C1_DR_DATA_Msk                  (0xffUL)                  /*!< I2C1 DR: DATA (Bitfield-Mask: 0xff)                   */
+/* =========================================================  SDHR  ========================================================== */
+#define I2C1_SDHR_HLDT_Pos                (0UL)                     /*!< I2C1 SDHR: HLDT (Bit 0)                               */
+#define I2C1_SDHR_HLDT_Msk                (0xfffUL)                 /*!< I2C1 SDHR: HLDT (Bitfield-Mask: 0xfff)                */
+/* =========================================================  SCLR  ========================================================== */
+#define I2C1_SCLR_SCLL_Pos                (0UL)                     /*!< I2C1 SCLR: SCLL (Bit 0)                               */
+#define I2C1_SCLR_SCLL_Msk                (0xfffUL)                 /*!< I2C1 SCLR: SCLL (Bitfield-Mask: 0xfff)                */
+/* =========================================================  SCHR  ========================================================== */
+#define I2C1_SCHR_SCLH_Pos                (0UL)                     /*!< I2C1 SCHR: SCLH (Bit 0)                               */
+#define I2C1_SCHR_SCLH_Msk                (0xfffUL)                 /*!< I2C1 SCHR: SCLH (Bitfield-Mask: 0xfff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C2                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define I2C2_CR_I2CnEN_Pos                (7UL)                     /*!< I2C2 CR: I2CnEN (Bit 7)                               */
+#define I2C2_CR_I2CnEN_Msk                (0x80UL)                  /*!< I2C2 CR: I2CnEN (Bitfield-Mask: 0x01)                 */
+#define I2C2_CR_TXDLYENBn_Pos             (6UL)                     /*!< I2C2 CR: TXDLYENBn (Bit 6)                            */
+#define I2C2_CR_TXDLYENBn_Msk             (0x40UL)                  /*!< I2C2 CR: TXDLYENBn (Bitfield-Mask: 0x01)              */
+#define I2C2_CR_I2CnIEN_Pos               (5UL)                     /*!< I2C2 CR: I2CnIEN (Bit 5)                              */
+#define I2C2_CR_I2CnIEN_Msk               (0x20UL)                  /*!< I2C2 CR: I2CnIEN (Bitfield-Mask: 0x01)                */
+#define I2C2_CR_I2CnIFLAG_Pos             (4UL)                     /*!< I2C2 CR: I2CnIFLAG (Bit 4)                            */
+#define I2C2_CR_I2CnIFLAG_Msk             (0x10UL)                  /*!< I2C2 CR: I2CnIFLAG (Bitfield-Mask: 0x01)              */
+#define I2C2_CR_ACKnEN_Pos                (3UL)                     /*!< I2C2 CR: ACKnEN (Bit 3)                               */
+#define I2C2_CR_ACKnEN_Msk                (0x8UL)                   /*!< I2C2 CR: ACKnEN (Bitfield-Mask: 0x01)                 */
+#define I2C2_CR_IMASTERn_Pos              (2UL)                     /*!< I2C2 CR: IMASTERn (Bit 2)                             */
+#define I2C2_CR_IMASTERn_Msk              (0x4UL)                   /*!< I2C2 CR: IMASTERn (Bitfield-Mask: 0x01)               */
+#define I2C2_CR_STOPCn_Pos                (1UL)                     /*!< I2C2 CR: STOPCn (Bit 1)                               */
+#define I2C2_CR_STOPCn_Msk                (0x2UL)                   /*!< I2C2 CR: STOPCn (Bitfield-Mask: 0x01)                 */
+#define I2C2_CR_STARTCn_Pos               (0UL)                     /*!< I2C2 CR: STARTCn (Bit 0)                              */
+#define I2C2_CR_STARTCn_Msk               (0x1UL)                   /*!< I2C2 CR: STARTCn (Bitfield-Mask: 0x01)                */
+/* ==========================================================  ST  =========================================================== */
+#define I2C2_ST_GCALLn_Pos                (7UL)                     /*!< I2C2 ST: GCALLn (Bit 7)                               */
+#define I2C2_ST_GCALLn_Msk                (0x80UL)                  /*!< I2C2 ST: GCALLn (Bitfield-Mask: 0x01)                 */
+#define I2C2_ST_TENDn_Pos                 (6UL)                     /*!< I2C2 ST: TENDn (Bit 6)                                */
+#define I2C2_ST_TENDn_Msk                 (0x40UL)                  /*!< I2C2 ST: TENDn (Bitfield-Mask: 0x01)                  */
+#define I2C2_ST_STOPDn_Pos                (5UL)                     /*!< I2C2 ST: STOPDn (Bit 5)                               */
+#define I2C2_ST_STOPDn_Msk                (0x20UL)                  /*!< I2C2 ST: STOPDn (Bitfield-Mask: 0x01)                 */
+#define I2C2_ST_SSELn_Pos                 (4UL)                     /*!< I2C2 ST: SSELn (Bit 4)                                */
+#define I2C2_ST_SSELn_Msk                 (0x10UL)                  /*!< I2C2 ST: SSELn (Bitfield-Mask: 0x01)                  */
+#define I2C2_ST_MLOSTn_Pos                (3UL)                     /*!< I2C2 ST: MLOSTn (Bit 3)                               */
+#define I2C2_ST_MLOSTn_Msk                (0x8UL)                   /*!< I2C2 ST: MLOSTn (Bitfield-Mask: 0x01)                 */
+#define I2C2_ST_BUSYn_Pos                 (2UL)                     /*!< I2C2 ST: BUSYn (Bit 2)                                */
+#define I2C2_ST_BUSYn_Msk                 (0x4UL)                   /*!< I2C2 ST: BUSYn (Bitfield-Mask: 0x01)                  */
+#define I2C2_ST_TMODEn_Pos                (1UL)                     /*!< I2C2 ST: TMODEn (Bit 1)                               */
+#define I2C2_ST_TMODEn_Msk                (0x2UL)                   /*!< I2C2 ST: TMODEn (Bitfield-Mask: 0x01)                 */
+#define I2C2_ST_RXACKn_Pos                (0UL)                     /*!< I2C2 ST: RXACKn (Bit 0)                               */
+#define I2C2_ST_RXACKn_Msk                (0x1UL)                   /*!< I2C2 ST: RXACKn (Bitfield-Mask: 0x01)                 */
+/* =========================================================  SAR1  ========================================================== */
+#define I2C2_SAR1_SLAn_Pos                (1UL)                     /*!< I2C2 SAR1: SLAn (Bit 1)                               */
+#define I2C2_SAR1_SLAn_Msk                (0xfeUL)                  /*!< I2C2 SAR1: SLAn (Bitfield-Mask: 0x7f)                 */
+#define I2C2_SAR1_GCALLnEN_Pos            (0UL)                     /*!< I2C2 SAR1: GCALLnEN (Bit 0)                           */
+#define I2C2_SAR1_GCALLnEN_Msk            (0x1UL)                   /*!< I2C2 SAR1: GCALLnEN (Bitfield-Mask: 0x01)             */
+/* =========================================================  SAR2  ========================================================== */
+#define I2C2_SAR2_SLAn_Pos                (1UL)                     /*!< I2C2 SAR2: SLAn (Bit 1)                               */
+#define I2C2_SAR2_SLAn_Msk                (0xfeUL)                  /*!< I2C2 SAR2: SLAn (Bitfield-Mask: 0x7f)                 */
+#define I2C2_SAR2_GCALLnEN_Pos            (0UL)                     /*!< I2C2 SAR2: GCALLnEN (Bit 0)                           */
+#define I2C2_SAR2_GCALLnEN_Msk            (0x1UL)                   /*!< I2C2 SAR2: GCALLnEN (Bitfield-Mask: 0x01)             */
+/* ==========================================================  DR  =========================================================== */
+#define I2C2_DR_DATA_Pos                  (0UL)                     /*!< I2C2 DR: DATA (Bit 0)                                 */
+#define I2C2_DR_DATA_Msk                  (0xffUL)                  /*!< I2C2 DR: DATA (Bitfield-Mask: 0xff)                   */
+/* =========================================================  SDHR  ========================================================== */
+#define I2C2_SDHR_HLDT_Pos                (0UL)                     /*!< I2C2 SDHR: HLDT (Bit 0)                               */
+#define I2C2_SDHR_HLDT_Msk                (0xfffUL)                 /*!< I2C2 SDHR: HLDT (Bitfield-Mask: 0xfff)                */
+/* =========================================================  SCLR  ========================================================== */
+#define I2C2_SCLR_SCLL_Pos                (0UL)                     /*!< I2C2 SCLR: SCLL (Bit 0)                               */
+#define I2C2_SCLR_SCLL_Msk                (0xfffUL)                 /*!< I2C2 SCLR: SCLL (Bitfield-Mask: 0xfff)                */
+/* =========================================================  SCHR  ========================================================== */
+#define I2C2_SCHR_SCLH_Pos                (0UL)                     /*!< I2C2 SCHR: SCLH (Bit 0)                               */
+#define I2C2_SCHR_SCLH_Msk                (0xfffUL)                 /*!< I2C2 SCHR: SCLH (Bitfield-Mask: 0xfff)                */
+
+
+/* =========================================================================================================================== */
+/* ================                                            LCD                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define LCD_CR_IRSEL_Pos                  (6UL)                     /*!< LCD CR: IRSEL (Bit 6)                                 */
+#define LCD_CR_IRSEL_Msk                  (0xc0UL)                  /*!< LCD CR: IRSEL (Bitfield-Mask: 0x03)                   */
+#define LCD_CR_DBS_Pos                    (3UL)                     /*!< LCD CR: DBS (Bit 3)                                   */
+#define LCD_CR_DBS_Msk                    (0x38UL)                  /*!< LCD CR: DBS (Bitfield-Mask: 0x07)                     */
+#define LCD_CR_LCLK_Pos                   (1UL)                     /*!< LCD CR: LCLK (Bit 1)                                  */
+#define LCD_CR_LCLK_Msk                   (0x6UL)                   /*!< LCD CR: LCLK (Bitfield-Mask: 0x03)                    */
+#define LCD_CR_DISP_Pos                   (0UL)                     /*!< LCD CR: DISP (Bit 0)                                  */
+#define LCD_CR_DISP_Msk                   (0x1UL)                   /*!< LCD CR: DISP (Bitfield-Mask: 0x01)                    */
+/* =========================================================  BCCR  ========================================================== */
+#define LCD_BCCR_LCDABC_Pos               (12UL)                    /*!< LCD BCCR: LCDABC (Bit 12)                             */
+#define LCD_BCCR_LCDABC_Msk               (0x1000UL)                /*!< LCD BCCR: LCDABC (Bitfield-Mask: 0x01)                */
+#define LCD_BCCR_BMSEL_Pos                (8UL)                     /*!< LCD BCCR: BMSEL (Bit 8)                               */
+#define LCD_BCCR_BMSEL_Msk                (0x700UL)                 /*!< LCD BCCR: BMSEL (Bitfield-Mask: 0x07)                 */
+#define LCD_BCCR_LCTEN_Pos                (5UL)                     /*!< LCD BCCR: LCTEN (Bit 5)                               */
+#define LCD_BCCR_LCTEN_Msk                (0x20UL)                  /*!< LCD BCCR: LCTEN (Bitfield-Mask: 0x01)                 */
+#define LCD_BCCR_VLCD_Pos                 (0UL)                     /*!< LCD BCCR: VLCD (Bit 0)                                */
+#define LCD_BCCR_VLCD_Msk                 (0xfUL)                   /*!< LCD BCCR: VLCD (Bitfield-Mask: 0x0f)                  */
+/* ==========================================================  DR0  ========================================================== */
+/* ==========================================================  DR1  ========================================================== */
+/* ==========================================================  DR2  ========================================================== */
+/* ==========================================================  DR3  ========================================================== */
+/* ==========================================================  DR4  ========================================================== */
+/* ==========================================================  DR5  ========================================================== */
+/* ==========================================================  DR6  ========================================================== */
+/* ==========================================================  DR7  ========================================================== */
+/* ==========================================================  DR8  ========================================================== */
+/* ==========================================================  DR9  ========================================================== */
+/* =========================================================  DR10  ========================================================== */
+/* =========================================================  DR11  ========================================================== */
+/* =========================================================  DR12  ========================================================== */
+/* =========================================================  DR13  ========================================================== */
+/* =========================================================  DR14  ========================================================== */
+/* =========================================================  DR15  ========================================================== */
+/* =========================================================  DR16  ========================================================== */
+/* =========================================================  DR17  ========================================================== */
+/* =========================================================  DR18  ========================================================== */
+/* =========================================================  DR19  ========================================================== */
+/* =========================================================  DR20  ========================================================== */
+/* =========================================================  DR21  ========================================================== */
+/* =========================================================  DR22  ========================================================== */
+/* =========================================================  DR23  ========================================================== */
+/* =========================================================  DR24  ========================================================== */
+/* =========================================================  DR25  ========================================================== */
+/* =========================================================  DR26  ========================================================== */
+/* =========================================================  DR27  ========================================================== */
+/* =========================================================  DR28  ========================================================== */
+/* =========================================================  DR29  ========================================================== */
+/* =========================================================  DR30  ========================================================== */
+/* =========================================================  DR31  ========================================================== */
+/* =========================================================  DR32  ========================================================== */
+/* =========================================================  DR33  ========================================================== */
+/* =========================================================  DR34  ========================================================== */
+/* =========================================================  DR35  ========================================================== */
+/* =========================================================  DR36  ========================================================== */
+/* =========================================================  DR37  ========================================================== */
+/* =========================================================  DR38  ========================================================== */
+/* =========================================================  DR39  ========================================================== */
+/* =========================================================  DR40  ========================================================== */
+/* =========================================================  DR41  ========================================================== */
+/* =========================================================  DR42  ========================================================== */
+/* =========================================================  DR43  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                            CRC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+#define CRC_CR_MODS_Pos                   (7UL)                     /*!< CRC CR: MODS (Bit 7)                                  */
+#define CRC_CR_MODS_Msk                   (0x80UL)                  /*!< CRC CR: MODS (Bitfield-Mask: 0x01)                    */
+#define CRC_CR_RLTCLR_Pos                 (6UL)                     /*!< CRC CR: RLTCLR (Bit 6)                                */
+#define CRC_CR_RLTCLR_Msk                 (0x40UL)                  /*!< CRC CR: RLTCLR (Bitfield-Mask: 0x01)                  */
+#define CRC_CR_MDSEL_Pos                  (5UL)                     /*!< CRC CR: MDSEL (Bit 5)                                 */
+#define CRC_CR_MDSEL_Msk                  (0x20UL)                  /*!< CRC CR: MDSEL (Bitfield-Mask: 0x01)                   */
+#define CRC_CR_POLYS_Pos                  (4UL)                     /*!< CRC CR: POLYS (Bit 4)                                 */
+#define CRC_CR_POLYS_Msk                  (0x10UL)                  /*!< CRC CR: POLYS (Bitfield-Mask: 0x01)                   */
+#define CRC_CR_SARINC_Pos                 (3UL)                     /*!< CRC CR: SARINC (Bit 3)                                */
+#define CRC_CR_SARINC_Msk                 (0x8UL)                   /*!< CRC CR: SARINC (Bitfield-Mask: 0x01)                  */
+#define CRC_CR_FIRSTBS_Pos                (1UL)                     /*!< CRC CR: FIRSTBS (Bit 1)                               */
+#define CRC_CR_FIRSTBS_Msk                (0x2UL)                   /*!< CRC CR: FIRSTBS (Bitfield-Mask: 0x01)                 */
+#define CRC_CR_CRCRUN_Pos                 (0UL)                     /*!< CRC CR: CRCRUN (Bit 0)                                */
+#define CRC_CR_CRCRUN_Msk                 (0x1UL)                   /*!< CRC CR: CRCRUN (Bitfield-Mask: 0x01)                  */
+/* ==========================================================  IN  =========================================================== */
+#define CRC_IN_INDATA_Pos                 (0UL)                     /*!< CRC IN: INDATA (Bit 0)                                */
+#define CRC_IN_INDATA_Msk                 (0xffffffffUL)            /*!< CRC IN: INDATA (Bitfield-Mask: 0xffffffff)            */
+/* ==========================================================  RLT  ========================================================== */
+#define CRC_RLT_RLTDATA_Pos               (0UL)                     /*!< CRC RLT: RLTDATA (Bit 0)                              */
+#define CRC_RLT_RLTDATA_Msk               (0xffffUL)                /*!< CRC RLT: RLTDATA (Bitfield-Mask: 0xffff)              */
+/* =========================================================  INIT  ========================================================== */
+#define CRC_INIT_INIDATA_Pos              (0UL)                     /*!< CRC INIT: INIDATA (Bit 0)                             */
+#define CRC_INIT_INIDATA_Msk              (0xffffUL)                /*!< CRC INIT: INIDATA (Bitfield-Mask: 0xffff)             */
+/* =========================================================  SADR  ========================================================== */
+#define CRC_SADR_SADR_Pos                 (2UL)                     /*!< CRC SADR: SADR (Bit 2)                                */
+#define CRC_SADR_SADR_Msk                 (0xfffffffcUL)            /*!< CRC SADR: SADR (Bitfield-Mask: 0x3fffffff)            */
+/* =========================================================  EADR  ========================================================== */
+#define CRC_EADR_EADR_Pos                 (2UL)                     /*!< CRC EADR: EADR (Bit 2)                                */
+#define CRC_EADR_EADR_Msk                 (0xfffffffcUL)            /*!< CRC EADR: EADR (Bitfield-Mask: 0x3fffffff)            */
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA0                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  TRIM00  ========================================================= */
+/* ========================================================  TRIM01  ========================================================= */
+/* ========================================================  TRIM02  ========================================================= */
+/* ========================================================  TRIM03  ========================================================= */
+/* ========================================================  TRIM04  ========================================================= */
+/* ========================================================  TRIM05  ========================================================= */
+/* ========================================================  TRIM06  ========================================================= */
+/* ========================================================  TRIM07  ========================================================= */
+/* ========================================================  TRIM08  ========================================================= */
+/* ========================================================  TRIM09  ========================================================= */
+/* ========================================================  TRIM10  ========================================================= */
+/* ========================================================  TRIM11  ========================================================= */
+/* ========================================================  TRIM12  ========================================================= */
+/* ========================================================  TRIM13  ========================================================= */
+/* ========================================================  TRIM14  ========================================================= */
+/* ========================================================  TRIM15  ========================================================= */
+/* ========================================================  TRIM16  ========================================================= */
+/* ========================================================  TRIM17  ========================================================= */
+/* ========================================================  TRIM18  ========================================================= */
+/* ========================================================  TRIM19  ========================================================= */
+/* =====================================================  CONF_MF1CNFIG  ===================================================== */
+#define COA0_CONF_MF1CNFIG_XYCDN_Pos      (0UL)                     /*!< COA0 CONF_MF1CNFIG: XYCDN (Bit 0)                     */
+#define COA0_CONF_MF1CNFIG_XYCDN_Msk      (0xffffffffUL)            /*!< COA0 CONF_MF1CNFIG: XYCDN (Bitfield-Mask: 0xffffffff) */
+/* =====================================================  CONF_MF2CNFIG  ===================================================== */
+#define COA0_CONF_MF2CNFIG_LOTNO_Pos      (8UL)                     /*!< COA0 CONF_MF2CNFIG: LOTNO (Bit 8)                     */
+#define COA0_CONF_MF2CNFIG_LOTNO_Msk      (0xffffff00UL)            /*!< COA0 CONF_MF2CNFIG: LOTNO (Bitfield-Mask: 0xffffff)   */
+#define COA0_CONF_MF2CNFIG_WAFNO_Pos      (0UL)                     /*!< COA0 CONF_MF2CNFIG: WAFNO (Bit 0)                     */
+#define COA0_CONF_MF2CNFIG_WAFNO_Msk      (0xffUL)                  /*!< COA0 CONF_MF2CNFIG: WAFNO (Bitfield-Mask: 0xff)       */
+/* =====================================================  CONF_MF3CNFIG  ===================================================== */
+#define COA0_CONF_MF3CNFIG_LOTNO_Pos      (0UL)                     /*!< COA0 CONF_MF3CNFIG: LOTNO (Bit 0)                     */
+#define COA0_CONF_MF3CNFIG_LOTNO_Msk      (0xffffffffUL)            /*!< COA0 CONF_MF3CNFIG: LOTNO (Bitfield-Mask: 0xffffffff) */
+/* =====================================================  CONF_MF4CNFIG  ===================================================== */
+#define COA0_CONF_MF4CNFIG_LOTNO_Pos      (0UL)                     /*!< COA0 CONF_MF4CNFIG: LOTNO (Bit 0)                     */
+#define COA0_CONF_MF4CNFIG_LOTNO_Msk      (0xffffffffUL)            /*!< COA0 CONF_MF4CNFIG: LOTNO (Bitfield-Mask: 0xffffffff) */
+/* ========================================================  TRIM24  ========================================================= */
+/* ========================================================  TRIM25  ========================================================= */
+/* ========================================================  TRIM26  ========================================================= */
+/* ========================================================  TRIM27  ========================================================= */
+/* ========================================================  TRIM28  ========================================================= */
+/* ========================================================  TRIM29  ========================================================= */
+/* ========================================================  TRIM30  ========================================================= */
+/* ========================================================  TRIM31  ========================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA1                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  RPCNFIG  ======================================================== */
+#define COA1_RPCNFIG_WTIDKY_Pos           (4UL)                     /*!< COA1 RPCNFIG: WTIDKY (Bit 4)                          */
+#define COA1_RPCNFIG_WTIDKY_Msk           (0xfffffff0UL)            /*!< COA1 RPCNFIG: WTIDKY (Bitfield-Mask: 0xfffffff)       */
+#define COA1_RPCNFIG_READP_Pos            (0UL)                     /*!< COA1 RPCNFIG: READP (Bit 0)                           */
+#define COA1_RPCNFIG_READP_Msk            (0x3UL)                   /*!< COA1 RPCNFIG: READP (Bitfield-Mask: 0x03)             */
+/* =======================================================  WDTCNFIG  ======================================================== */
+#define COA1_WDTCNFIG_WRCMF_Pos           (4UL)                     /*!< COA1 WDTCNFIG: WRCMF (Bit 4)                          */
+#define COA1_WDTCNFIG_WRCMF_Msk           (0xfff0UL)                /*!< COA1 WDTCNFIG: WRCMF (Bitfield-Mask: 0xfff)           */
+#define COA1_WDTCNFIG_WCLKMF_Pos          (2UL)                     /*!< COA1 WDTCNFIG: WCLKMF (Bit 2)                         */
+#define COA1_WDTCNFIG_WCLKMF_Msk          (0x4UL)                   /*!< COA1 WDTCNFIG: WCLKMF (Bitfield-Mask: 0x01)           */
+#define COA1_WDTCNFIG_WRSTMF_Pos          (1UL)                     /*!< COA1 WDTCNFIG: WRSTMF (Bit 1)                         */
+#define COA1_WDTCNFIG_WRSTMF_Msk          (0x2UL)                   /*!< COA1 WDTCNFIG: WRSTMF (Bitfield-Mask: 0x01)           */
+#define COA1_WDTCNFIG_WCNTMF_Pos          (0UL)                     /*!< COA1 WDTCNFIG: WCNTMF (Bit 0)                         */
+#define COA1_WDTCNFIG_WCNTMF_Msk          (0x1UL)                   /*!< COA1 WDTCNFIG: WCNTMF (Bitfield-Mask: 0x01)           */
+/* =======================================================  LVRCNFIG  ======================================================== */
+#define COA1_LVRCNFIG_LVRENM_Pos          (8UL)                     /*!< COA1 LVRCNFIG: LVRENM (Bit 8)                         */
+#define COA1_LVRCNFIG_LVRENM_Msk          (0xff00UL)                /*!< COA1 LVRCNFIG: LVRENM (Bitfield-Mask: 0xff)           */
+#define COA1_LVRCNFIG_LVRVS_Pos           (0UL)                     /*!< COA1 LVRCNFIG: LVRVS (Bit 0)                          */
+#define COA1_LVRCNFIG_LVRVS_Msk           (0xfUL)                   /*!< COA1 LVRCNFIG: LVRVS (Bitfield-Mask: 0x0f)            */
+/* =======================================================  CNFIGWTP1  ======================================================= */
+#define COA1_CNFIGWTP1_CP3WP_Pos          (2UL)                     /*!< COA1 CNFIGWTP1: CP3WP (Bit 2)                         */
+#define COA1_CNFIGWTP1_CP3WP_Msk          (0x4UL)                   /*!< COA1 CNFIGWTP1: CP3WP (Bitfield-Mask: 0x01)           */
+#define COA1_CNFIGWTP1_CP2WP_Pos          (1UL)                     /*!< COA1 CNFIGWTP1: CP2WP (Bit 1)                         */
+#define COA1_CNFIGWTP1_CP2WP_Msk          (0x2UL)                   /*!< COA1 CNFIGWTP1: CP2WP (Bitfield-Mask: 0x01)           */
+#define COA1_CNFIGWTP1_CP1WP_Pos          (0UL)                     /*!< COA1 CNFIGWTP1: CP1WP (Bit 0)                         */
+#define COA1_CNFIGWTP1_CP1WP_Msk          (0x1UL)                   /*!< COA1 CNFIGWTP1: CP1WP (Bitfield-Mask: 0x01)           */
+/* ========================================================  FMWTP1  ========================================================= */
+#define COA1_FMWTP1_SWTP31_Pos            (31UL)                    /*!< COA1 FMWTP1: SWTP31 (Bit 31)                          */
+#define COA1_FMWTP1_SWTP31_Msk            (0x80000000UL)            /*!< COA1 FMWTP1: SWTP31 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP30_Pos            (30UL)                    /*!< COA1 FMWTP1: SWTP30 (Bit 30)                          */
+#define COA1_FMWTP1_SWTP30_Msk            (0x40000000UL)            /*!< COA1 FMWTP1: SWTP30 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP29_Pos            (29UL)                    /*!< COA1 FMWTP1: SWTP29 (Bit 29)                          */
+#define COA1_FMWTP1_SWTP29_Msk            (0x20000000UL)            /*!< COA1 FMWTP1: SWTP29 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP28_Pos            (28UL)                    /*!< COA1 FMWTP1: SWTP28 (Bit 28)                          */
+#define COA1_FMWTP1_SWTP28_Msk            (0x10000000UL)            /*!< COA1 FMWTP1: SWTP28 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP27_Pos            (27UL)                    /*!< COA1 FMWTP1: SWTP27 (Bit 27)                          */
+#define COA1_FMWTP1_SWTP27_Msk            (0x8000000UL)             /*!< COA1 FMWTP1: SWTP27 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP26_Pos            (26UL)                    /*!< COA1 FMWTP1: SWTP26 (Bit 26)                          */
+#define COA1_FMWTP1_SWTP26_Msk            (0x4000000UL)             /*!< COA1 FMWTP1: SWTP26 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP25_Pos            (25UL)                    /*!< COA1 FMWTP1: SWTP25 (Bit 25)                          */
+#define COA1_FMWTP1_SWTP25_Msk            (0x2000000UL)             /*!< COA1 FMWTP1: SWTP25 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP24_Pos            (24UL)                    /*!< COA1 FMWTP1: SWTP24 (Bit 24)                          */
+#define COA1_FMWTP1_SWTP24_Msk            (0x1000000UL)             /*!< COA1 FMWTP1: SWTP24 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP23_Pos            (23UL)                    /*!< COA1 FMWTP1: SWTP23 (Bit 23)                          */
+#define COA1_FMWTP1_SWTP23_Msk            (0x800000UL)              /*!< COA1 FMWTP1: SWTP23 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP22_Pos            (22UL)                    /*!< COA1 FMWTP1: SWTP22 (Bit 22)                          */
+#define COA1_FMWTP1_SWTP22_Msk            (0x400000UL)              /*!< COA1 FMWTP1: SWTP22 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP21_Pos            (21UL)                    /*!< COA1 FMWTP1: SWTP21 (Bit 21)                          */
+#define COA1_FMWTP1_SWTP21_Msk            (0x200000UL)              /*!< COA1 FMWTP1: SWTP21 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP20_Pos            (20UL)                    /*!< COA1 FMWTP1: SWTP20 (Bit 20)                          */
+#define COA1_FMWTP1_SWTP20_Msk            (0x100000UL)              /*!< COA1 FMWTP1: SWTP20 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP19_Pos            (19UL)                    /*!< COA1 FMWTP1: SWTP19 (Bit 19)                          */
+#define COA1_FMWTP1_SWTP19_Msk            (0x80000UL)               /*!< COA1 FMWTP1: SWTP19 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP18_Pos            (18UL)                    /*!< COA1 FMWTP1: SWTP18 (Bit 18)                          */
+#define COA1_FMWTP1_SWTP18_Msk            (0x40000UL)               /*!< COA1 FMWTP1: SWTP18 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP17_Pos            (17UL)                    /*!< COA1 FMWTP1: SWTP17 (Bit 17)                          */
+#define COA1_FMWTP1_SWTP17_Msk            (0x20000UL)               /*!< COA1 FMWTP1: SWTP17 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP16_Pos            (16UL)                    /*!< COA1 FMWTP1: SWTP16 (Bit 16)                          */
+#define COA1_FMWTP1_SWTP16_Msk            (0x10000UL)               /*!< COA1 FMWTP1: SWTP16 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP15_Pos            (15UL)                    /*!< COA1 FMWTP1: SWTP15 (Bit 15)                          */
+#define COA1_FMWTP1_SWTP15_Msk            (0x8000UL)                /*!< COA1 FMWTP1: SWTP15 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP14_Pos            (14UL)                    /*!< COA1 FMWTP1: SWTP14 (Bit 14)                          */
+#define COA1_FMWTP1_SWTP14_Msk            (0x4000UL)                /*!< COA1 FMWTP1: SWTP14 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP13_Pos            (13UL)                    /*!< COA1 FMWTP1: SWTP13 (Bit 13)                          */
+#define COA1_FMWTP1_SWTP13_Msk            (0x2000UL)                /*!< COA1 FMWTP1: SWTP13 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP12_Pos            (12UL)                    /*!< COA1 FMWTP1: SWTP12 (Bit 12)                          */
+#define COA1_FMWTP1_SWTP12_Msk            (0x1000UL)                /*!< COA1 FMWTP1: SWTP12 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP11_Pos            (11UL)                    /*!< COA1 FMWTP1: SWTP11 (Bit 11)                          */
+#define COA1_FMWTP1_SWTP11_Msk            (0x800UL)                 /*!< COA1 FMWTP1: SWTP11 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP10_Pos            (10UL)                    /*!< COA1 FMWTP1: SWTP10 (Bit 10)                          */
+#define COA1_FMWTP1_SWTP10_Msk            (0x400UL)                 /*!< COA1 FMWTP1: SWTP10 (Bitfield-Mask: 0x01)             */
+#define COA1_FMWTP1_SWTP9_Pos             (9UL)                     /*!< COA1 FMWTP1: SWTP9 (Bit 9)                            */
+#define COA1_FMWTP1_SWTP9_Msk             (0x200UL)                 /*!< COA1 FMWTP1: SWTP9 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP8_Pos             (8UL)                     /*!< COA1 FMWTP1: SWTP8 (Bit 8)                            */
+#define COA1_FMWTP1_SWTP8_Msk             (0x100UL)                 /*!< COA1 FMWTP1: SWTP8 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP7_Pos             (7UL)                     /*!< COA1 FMWTP1: SWTP7 (Bit 7)                            */
+#define COA1_FMWTP1_SWTP7_Msk             (0x80UL)                  /*!< COA1 FMWTP1: SWTP7 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP6_Pos             (6UL)                     /*!< COA1 FMWTP1: SWTP6 (Bit 6)                            */
+#define COA1_FMWTP1_SWTP6_Msk             (0x40UL)                  /*!< COA1 FMWTP1: SWTP6 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP5_Pos             (5UL)                     /*!< COA1 FMWTP1: SWTP5 (Bit 5)                            */
+#define COA1_FMWTP1_SWTP5_Msk             (0x20UL)                  /*!< COA1 FMWTP1: SWTP5 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP4_Pos             (4UL)                     /*!< COA1 FMWTP1: SWTP4 (Bit 4)                            */
+#define COA1_FMWTP1_SWTP4_Msk             (0x10UL)                  /*!< COA1 FMWTP1: SWTP4 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP3_Pos             (3UL)                     /*!< COA1 FMWTP1: SWTP3 (Bit 3)                            */
+#define COA1_FMWTP1_SWTP3_Msk             (0x8UL)                   /*!< COA1 FMWTP1: SWTP3 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP2_Pos             (2UL)                     /*!< COA1 FMWTP1: SWTP2 (Bit 2)                            */
+#define COA1_FMWTP1_SWTP2_Msk             (0x4UL)                   /*!< COA1 FMWTP1: SWTP2 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP1_Pos             (1UL)                     /*!< COA1 FMWTP1: SWTP1 (Bit 1)                            */
+#define COA1_FMWTP1_SWTP1_Msk             (0x2UL)                   /*!< COA1 FMWTP1: SWTP1 (Bitfield-Mask: 0x01)              */
+#define COA1_FMWTP1_SWTP0_Pos             (0UL)                     /*!< COA1 FMWTP1: SWTP0 (Bit 0)                            */
+#define COA1_FMWTP1_SWTP0_Msk             (0x1UL)                   /*!< COA1 FMWTP1: SWTP0 (Bitfield-Mask: 0x01)              */
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA2                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  UDATA00  ======================================================== */
+/* ========================================================  UDATA01  ======================================================== */
+/* ========================================================  UDATA02  ======================================================== */
+/* ========================================================  UDATA03  ======================================================== */
+/* ========================================================  UDATA04  ======================================================== */
+/* ========================================================  UDATA05  ======================================================== */
+/* ========================================================  UDATA06  ======================================================== */
+/* ========================================================  UDATA07  ======================================================== */
+/* ========================================================  UDATA08  ======================================================== */
+/* ========================================================  UDATA09  ======================================================== */
+/* ========================================================  UDATA10  ======================================================== */
+/* ========================================================  UDATA11  ======================================================== */
+/* ========================================================  UDATA12  ======================================================== */
+/* ========================================================  UDATA13  ======================================================== */
+/* ========================================================  UDATA14  ======================================================== */
+/* ========================================================  UDATA15  ======================================================== */
+/* ========================================================  UDATA16  ======================================================== */
+/* ========================================================  UDATA17  ======================================================== */
+/* ========================================================  UDATA18  ======================================================== */
+/* ========================================================  UDATA19  ======================================================== */
+/* ========================================================  UDATA20  ======================================================== */
+/* ========================================================  UDATA21  ======================================================== */
+/* ========================================================  UDATA22  ======================================================== */
+/* ========================================================  UDATA23  ======================================================== */
+/* ========================================================  UDATA24  ======================================================== */
+/* ========================================================  UDATA25  ======================================================== */
+/* ========================================================  UDATA26  ======================================================== */
+/* ========================================================  UDATA27  ======================================================== */
+/* ========================================================  UDATA28  ======================================================== */
+/* ========================================================  UDATA29  ======================================================== */
+/* ========================================================  UDATA30  ======================================================== */
+/* ========================================================  UDATA31  ======================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA3                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  UDATA00  ======================================================== */
+/* ========================================================  UDATA01  ======================================================== */
+/* ========================================================  UDATA02  ======================================================== */
+/* ========================================================  UDATA03  ======================================================== */
+/* ========================================================  UDATA04  ======================================================== */
+/* ========================================================  UDATA05  ======================================================== */
+/* ========================================================  UDATA06  ======================================================== */
+/* ========================================================  UDATA07  ======================================================== */
+/* ========================================================  UDATA08  ======================================================== */
+/* ========================================================  UDATA09  ======================================================== */
+/* ========================================================  UDATA10  ======================================================== */
+/* ========================================================  UDATA11  ======================================================== */
+/* ========================================================  UDATA12  ======================================================== */
+/* ========================================================  UDATA13  ======================================================== */
+/* ========================================================  UDATA14  ======================================================== */
+/* ========================================================  UDATA15  ======================================================== */
+/* ========================================================  UDATA16  ======================================================== */
+/* ========================================================  UDATA17  ======================================================== */
+/* ========================================================  UDATA18  ======================================================== */
+/* ========================================================  UDATA19  ======================================================== */
+/* ========================================================  UDATA20  ======================================================== */
+/* ========================================================  UDATA21  ======================================================== */
+/* ========================================================  UDATA22  ======================================================== */
+/* ========================================================  UDATA23  ======================================================== */
+/* ========================================================  UDATA24  ======================================================== */
+/* ========================================================  UDATA25  ======================================================== */
+/* ========================================================  UDATA26  ======================================================== */
+/* ========================================================  UDATA27  ======================================================== */
+/* ========================================================  UDATA28  ======================================================== */
+/* ========================================================  UDATA29  ======================================================== */
+/* ========================================================  UDATA30  ======================================================== */
+/* ========================================================  UDATA31  ======================================================== */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================                           Enumerated Values Peripheral Section                            ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup EnumValue_peripherals
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           INTC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PBTRIG  ========================================================= */
+/* =============================================  INTC PBTRIG ITRIG11 [11..11]  ============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG11                                                       */
+  INTC_PBTRIG_ITRIG11_Edge             = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG11_Level            = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG11_Enum;
+
+/* =============================================  INTC PBTRIG ITRIG10 [10..10]  ============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG10                                                       */
+  INTC_PBTRIG_ITRIG10_Edge             = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG10_Level            = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG10_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG9 [9..9]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG9                                                        */
+  INTC_PBTRIG_ITRIG9_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG9_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG9_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG8 [8..8]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG8                                                        */
+  INTC_PBTRIG_ITRIG8_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG8_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG8_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG7 [7..7]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG7                                                        */
+  INTC_PBTRIG_ITRIG7_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG7_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG7_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG6 [6..6]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG6                                                        */
+  INTC_PBTRIG_ITRIG6_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG6_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG6_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG5 [5..5]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG5                                                        */
+  INTC_PBTRIG_ITRIG5_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG5_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG5_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG4 [4..4]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG4                                                        */
+  INTC_PBTRIG_ITRIG4_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG4_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG4_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG3 [3..3]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG3                                                        */
+  INTC_PBTRIG_ITRIG3_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG3_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG3_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG2 [2..2]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG2                                                        */
+  INTC_PBTRIG_ITRIG2_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG2_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG2_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG1 [1..1]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG1                                                        */
+  INTC_PBTRIG_ITRIG1_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG1_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG1_Enum;
+
+/* ===============================================  INTC PBTRIG ITRIG0 [0..0]  =============================================== */
+typedef enum {                                  /*!< INTC_PBTRIG_ITRIG0                                                        */
+  INTC_PBTRIG_ITRIG0_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PBTRIG_ITRIG0_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PBTRIG_ITRIG0_Enum;
+
+/* ========================================================  PCTRIG  ========================================================= */
+/* ===============================================  INTC PCTRIG ITRIG3 [3..3]  =============================================== */
+typedef enum {                                  /*!< INTC_PCTRIG_ITRIG3                                                        */
+  INTC_PCTRIG_ITRIG3_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PCTRIG_ITRIG3_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PCTRIG_ITRIG3_Enum;
+
+/* ===============================================  INTC PCTRIG ITRIG2 [2..2]  =============================================== */
+typedef enum {                                  /*!< INTC_PCTRIG_ITRIG2                                                        */
+  INTC_PCTRIG_ITRIG2_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PCTRIG_ITRIG2_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PCTRIG_ITRIG2_Enum;
+
+/* ===============================================  INTC PCTRIG ITRIG1 [1..1]  =============================================== */
+typedef enum {                                  /*!< INTC_PCTRIG_ITRIG1                                                        */
+  INTC_PCTRIG_ITRIG1_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PCTRIG_ITRIG1_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PCTRIG_ITRIG1_Enum;
+
+/* ===============================================  INTC PCTRIG ITRIG0 [0..0]  =============================================== */
+typedef enum {                                  /*!< INTC_PCTRIG_ITRIG0                                                        */
+  INTC_PCTRIG_ITRIG0_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PCTRIG_ITRIG0_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PCTRIG_ITRIG0_Enum;
+
+/* ========================================================  PETRIG  ========================================================= */
+/* ===============================================  INTC PETRIG ITRIG3 [3..3]  =============================================== */
+typedef enum {                                  /*!< INTC_PETRIG_ITRIG3                                                        */
+  INTC_PETRIG_ITRIG3_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PETRIG_ITRIG3_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PETRIG_ITRIG3_Enum;
+
+/* ===============================================  INTC PETRIG ITRIG2 [2..2]  =============================================== */
+typedef enum {                                  /*!< INTC_PETRIG_ITRIG2                                                        */
+  INTC_PETRIG_ITRIG2_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PETRIG_ITRIG2_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PETRIG_ITRIG2_Enum;
+
+/* ===============================================  INTC PETRIG ITRIG1 [1..1]  =============================================== */
+typedef enum {                                  /*!< INTC_PETRIG_ITRIG1                                                        */
+  INTC_PETRIG_ITRIG1_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PETRIG_ITRIG1_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PETRIG_ITRIG1_Enum;
+
+/* ===============================================  INTC PETRIG ITRIG0 [0..0]  =============================================== */
+typedef enum {                                  /*!< INTC_PETRIG_ITRIG0                                                        */
+  INTC_PETRIG_ITRIG0_Edge              = 0,     /*!< Edge : Edge trigger interrupt                                             */
+  INTC_PETRIG_ITRIG0_Level             = 1,     /*!< Level : Level trigger interrupt                                           */
+} INTC_PETRIG_ITRIG0_Enum;
+
+/* =========================================================  PBCR  ========================================================== */
+/* ==============================================  INTC PBCR INTCTL11 [22..23]  ============================================== */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL11                                                        */
+  INTC_PBCR_INTCTL11_Disable           = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL11_FallingEdgeLowLevel = 1,   /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL11_RisingEdgeHighLevel = 2,   /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL11_BothEdgeNoLevel   = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                                    No level interrupt                                         */
+} INTC_PBCR_INTCTL11_Enum;
+
+/* ==============================================  INTC PBCR INTCTL10 [20..21]  ============================================== */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL10                                                        */
+  INTC_PBCR_INTCTL10_Disable           = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL10_FallingEdgeLowLevel = 1,   /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL10_RisingEdgeHighLevel = 2,   /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL10_BothEdgeNoLevel   = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL10_Enum;
+
+/* ==============================================  INTC PBCR INTCTL9 [18..19]  =============================================== */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL9                                                         */
+  INTC_PBCR_INTCTL9_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL9_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL9_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL9_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL9_Enum;
+
+/* ==============================================  INTC PBCR INTCTL8 [16..17]  =============================================== */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL8                                                         */
+  INTC_PBCR_INTCTL8_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL8_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL8_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL8_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL8_Enum;
+
+/* ==============================================  INTC PBCR INTCTL7 [14..15]  =============================================== */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL7                                                         */
+  INTC_PBCR_INTCTL7_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL7_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL7_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL7_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL7_Enum;
+
+/* ==============================================  INTC PBCR INTCTL6 [12..13]  =============================================== */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL6                                                         */
+  INTC_PBCR_INTCTL6_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL6_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL6_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL6_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL6_Enum;
+
+/* ==============================================  INTC PBCR INTCTL5 [10..11]  =============================================== */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL5                                                         */
+  INTC_PBCR_INTCTL5_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL5_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL5_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL5_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL5_Enum;
+
+/* ===============================================  INTC PBCR INTCTL4 [8..9]  ================================================ */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL4                                                         */
+  INTC_PBCR_INTCTL4_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL4_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL4_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL4_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL4_Enum;
+
+/* ===============================================  INTC PBCR INTCTL3 [6..7]  ================================================ */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL3                                                         */
+  INTC_PBCR_INTCTL3_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL3_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL3_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL3_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL3_Enum;
+
+/* ===============================================  INTC PBCR INTCTL2 [4..5]  ================================================ */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL2                                                         */
+  INTC_PBCR_INTCTL2_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL2_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL2_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL2_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL2_Enum;
+
+/* ===============================================  INTC PBCR INTCTL1 [2..3]  ================================================ */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL1                                                         */
+  INTC_PBCR_INTCTL1_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL1_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL1_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL1_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL1_Enum;
+
+/* ===============================================  INTC PBCR INTCTL0 [0..1]  ================================================ */
+typedef enum {                                  /*!< INTC_PBCR_INTCTL0                                                         */
+  INTC_PBCR_INTCTL0_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PBCR_INTCTL0_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PBCR_INTCTL0_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PBCR_INTCTL0_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PBCR_INTCTL0_Enum;
+
+/* =========================================================  PCCR  ========================================================== */
+/* ===============================================  INTC PCCR INTCTL3 [6..7]  ================================================ */
+typedef enum {                                  /*!< INTC_PCCR_INTCTL3                                                         */
+  INTC_PCCR_INTCTL3_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PCCR_INTCTL3_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PCCR_INTCTL3_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PCCR_INTCTL3_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PCCR_INTCTL3_Enum;
+
+/* ===============================================  INTC PCCR INTCTL2 [4..5]  ================================================ */
+typedef enum {                                  /*!< INTC_PCCR_INTCTL2                                                         */
+  INTC_PCCR_INTCTL2_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PCCR_INTCTL2_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PCCR_INTCTL2_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PCCR_INTCTL2_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PCCR_INTCTL2_Enum;
+
+/* ===============================================  INTC PCCR INTCTL1 [2..3]  ================================================ */
+typedef enum {                                  /*!< INTC_PCCR_INTCTL1                                                         */
+  INTC_PCCR_INTCTL1_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PCCR_INTCTL1_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PCCR_INTCTL1_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PCCR_INTCTL1_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PCCR_INTCTL1_Enum;
+
+/* ===============================================  INTC PCCR INTCTL0 [0..1]  ================================================ */
+typedef enum {                                  /*!< INTC_PCCR_INTCTL0                                                         */
+  INTC_PCCR_INTCTL0_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PCCR_INTCTL0_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PCCR_INTCTL0_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PCCR_INTCTL0_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PCCR_INTCTL0_Enum;
+
+/* =========================================================  PECR  ========================================================== */
+/* ===============================================  INTC PECR INTCTL3 [6..7]  ================================================ */
+typedef enum {                                  /*!< INTC_PECR_INTCTL3                                                         */
+  INTC_PECR_INTCTL3_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PECR_INTCTL3_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PECR_INTCTL3_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PECR_INTCTL3_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PECR_INTCTL3_Enum;
+
+/* ===============================================  INTC PECR INTCTL2 [4..5]  ================================================ */
+typedef enum {                                  /*!< INTC_PECR_INTCTL2                                                         */
+  INTC_PECR_INTCTL2_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PECR_INTCTL2_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PECR_INTCTL2_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PECR_INTCTL2_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PECR_INTCTL2_Enum;
+
+/* ===============================================  INTC PECR INTCTL1 [2..3]  ================================================ */
+typedef enum {                                  /*!< INTC_PECR_INTCTL1                                                         */
+  INTC_PECR_INTCTL1_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PECR_INTCTL1_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PECR_INTCTL1_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PECR_INTCTL1_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PECR_INTCTL1_Enum;
+
+/* ===============================================  INTC PECR INTCTL0 [0..1]  ================================================ */
+typedef enum {                                  /*!< INTC_PECR_INTCTL0                                                         */
+  INTC_PECR_INTCTL0_Disable            = 0,     /*!< Disable : Disable external interrupt.                                     */
+  INTC_PECR_INTCTL0_FallingEdgeLowLevel = 1,    /*!< FallingEdgeLowLevel : Interrupt on falling edge or on low level           */
+  INTC_PECR_INTCTL0_RisingEdgeHighLevel = 2,    /*!< RisingEdgeHighLevel : Interrupt on rising edge or on high level           */
+  INTC_PECR_INTCTL0_BothEdgeNoLevel    = 3,     /*!< BothEdgeNoLevel : Interrupt on both falling and rising edge,
+                                                     No level interrupt                                                        */
+} INTC_PECR_INTCTL0_Enum;
+
+/* ========================================================  PBFLAG  ========================================================= */
+/* ==============================================  INTC PBFLAG FLAG11 [11..11]  ============================================== */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG11                                                        */
+  INTC_PBFLAG_FLAG11_NoRequest         = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG11_Request           = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG11_Enum;
+
+/* ==============================================  INTC PBFLAG FLAG10 [10..10]  ============================================== */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG10                                                        */
+  INTC_PBFLAG_FLAG10_NoRequest         = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG10_Request           = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG10_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG9 [9..9]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG9                                                         */
+  INTC_PBFLAG_FLAG9_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG9_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG9_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG8 [8..8]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG8                                                         */
+  INTC_PBFLAG_FLAG8_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG8_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG8_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG7 [7..7]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG7                                                         */
+  INTC_PBFLAG_FLAG7_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG7_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG7_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG6 [6..6]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG6                                                         */
+  INTC_PBFLAG_FLAG6_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG6_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG6_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG5 [5..5]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG5                                                         */
+  INTC_PBFLAG_FLAG5_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG5_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG5_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG4 [4..4]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG4                                                         */
+  INTC_PBFLAG_FLAG4_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG4_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG4_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG3 [3..3]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG3                                                         */
+  INTC_PBFLAG_FLAG3_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG3_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG3_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG2 [2..2]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG2                                                         */
+  INTC_PBFLAG_FLAG2_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG2_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG2_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG1 [1..1]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG1                                                         */
+  INTC_PBFLAG_FLAG1_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG1_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG1_Enum;
+
+/* ===============================================  INTC PBFLAG FLAG0 [0..0]  ================================================ */
+typedef enum {                                  /*!< INTC_PBFLAG_FLAG0                                                         */
+  INTC_PBFLAG_FLAG0_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PBFLAG_FLAG0_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PBFLAG_FLAG0_Enum;
+
+/* ========================================================  PCFLAG  ========================================================= */
+/* ===============================================  INTC PCFLAG FLAG3 [3..3]  ================================================ */
+typedef enum {                                  /*!< INTC_PCFLAG_FLAG3                                                         */
+  INTC_PCFLAG_FLAG3_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PCFLAG_FLAG3_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PCFLAG_FLAG3_Enum;
+
+/* ===============================================  INTC PCFLAG FLAG2 [2..2]  ================================================ */
+typedef enum {                                  /*!< INTC_PCFLAG_FLAG2                                                         */
+  INTC_PCFLAG_FLAG2_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PCFLAG_FLAG2_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PCFLAG_FLAG2_Enum;
+
+/* ===============================================  INTC PCFLAG FLAG1 [1..1]  ================================================ */
+typedef enum {                                  /*!< INTC_PCFLAG_FLAG1                                                         */
+  INTC_PCFLAG_FLAG1_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PCFLAG_FLAG1_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PCFLAG_FLAG1_Enum;
+
+/* ===============================================  INTC PCFLAG FLAG0 [0..0]  ================================================ */
+typedef enum {                                  /*!< INTC_PCFLAG_FLAG0                                                         */
+  INTC_PCFLAG_FLAG0_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PCFLAG_FLAG0_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PCFLAG_FLAG0_Enum;
+
+/* ========================================================  PEFLAG  ========================================================= */
+/* ===============================================  INTC PEFLAG FLAG3 [3..3]  ================================================ */
+typedef enum {                                  /*!< INTC_PEFLAG_FLAG3                                                         */
+  INTC_PEFLAG_FLAG3_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PEFLAG_FLAG3_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PEFLAG_FLAG3_Enum;
+
+/* ===============================================  INTC PEFLAG FLAG2 [2..2]  ================================================ */
+typedef enum {                                  /*!< INTC_PEFLAG_FLAG2                                                         */
+  INTC_PEFLAG_FLAG2_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PEFLAG_FLAG2_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PEFLAG_FLAG2_Enum;
+
+/* ===============================================  INTC PEFLAG FLAG1 [1..1]  ================================================ */
+typedef enum {                                  /*!< INTC_PEFLAG_FLAG1                                                         */
+  INTC_PEFLAG_FLAG1_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PEFLAG_FLAG1_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PEFLAG_FLAG1_Enum;
+
+/* ===============================================  INTC PEFLAG FLAG0 [0..0]  ================================================ */
+typedef enum {                                  /*!< INTC_PEFLAG_FLAG0                                                         */
+  INTC_PEFLAG_FLAG0_NoRequest          = 0,     /*!< NoRequest : No request occurred.                                          */
+  INTC_PEFLAG_FLAG0_Request            = 1,     /*!< Request : Request occurred.                                               */
+} INTC_PEFLAG_FLAG0_Enum;
+
+/* ======================================================  EINT0CONF1  ======================================================= */
+/* ============================================  INTC EINT0CONF1 CONF7 [28..31]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT0CONF1_CONF7                                                     */
+  INTC_EINT0CONF1_CONF7_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF1_CONF7_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF1_CONF7_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF1_CONF7_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF1_CONF7_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF1_CONF7_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF1_CONF7_Enum;
+
+/* ============================================  INTC EINT0CONF1 CONF6 [24..27]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT0CONF1_CONF6                                                     */
+  INTC_EINT0CONF1_CONF6_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF1_CONF6_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF1_CONF6_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF1_CONF6_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF1_CONF6_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF1_CONF6_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF1_CONF6_Enum;
+
+/* ============================================  INTC EINT0CONF1 CONF5 [20..23]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT0CONF1_CONF5                                                     */
+  INTC_EINT0CONF1_CONF5_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF1_CONF5_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF1_CONF5_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF1_CONF5_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF1_CONF5_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF1_CONF5_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF1_CONF5_Enum;
+
+/* ============================================  INTC EINT0CONF1 CONF4 [16..19]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT0CONF1_CONF4                                                     */
+  INTC_EINT0CONF1_CONF4_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF1_CONF4_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF1_CONF4_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF1_CONF4_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF1_CONF4_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF1_CONF4_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF1_CONF4_Enum;
+
+/* ============================================  INTC EINT0CONF1 CONF3 [12..15]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT0CONF1_CONF3                                                     */
+  INTC_EINT0CONF1_CONF3_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF1_CONF3_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF1_CONF3_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF1_CONF3_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF1_CONF3_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF1_CONF3_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF1_CONF3_Enum;
+
+/* =============================================  INTC EINT0CONF1 CONF2 [8..11]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT0CONF1_CONF2                                                     */
+  INTC_EINT0CONF1_CONF2_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF1_CONF2_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF1_CONF2_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF1_CONF2_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF1_CONF2_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF1_CONF2_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF1_CONF2_Enum;
+
+/* =============================================  INTC EINT0CONF1 CONF1 [4..7]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT0CONF1_CONF1                                                     */
+  INTC_EINT0CONF1_CONF1_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF1_CONF1_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF1_CONF1_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF1_CONF1_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF1_CONF1_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF1_CONF1_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF1_CONF1_Enum;
+
+/* =============================================  INTC EINT0CONF1 CONF0 [0..3]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT0CONF1_CONF0                                                     */
+  INTC_EINT0CONF1_CONF0_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF1_CONF0_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF1_CONF0_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF1_CONF0_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF1_CONF0_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF1_CONF0_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF1_CONF0_Enum;
+
+/* ======================================================  EINT1CONF1  ======================================================= */
+/* ============================================  INTC EINT1CONF1 CONF7 [28..31]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT1CONF1_CONF7                                                     */
+  INTC_EINT1CONF1_CONF7_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF1_CONF7_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF1_CONF7_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF1_CONF7_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF1_CONF7_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF1_CONF7_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF1_CONF7_Enum;
+
+/* ============================================  INTC EINT1CONF1 CONF6 [24..27]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT1CONF1_CONF6                                                     */
+  INTC_EINT1CONF1_CONF6_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF1_CONF6_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF1_CONF6_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF1_CONF6_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF1_CONF6_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF1_CONF6_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF1_CONF6_Enum;
+
+/* ============================================  INTC EINT1CONF1 CONF5 [20..23]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT1CONF1_CONF5                                                     */
+  INTC_EINT1CONF1_CONF5_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF1_CONF5_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF1_CONF5_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF1_CONF5_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF1_CONF5_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF1_CONF5_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF1_CONF5_Enum;
+
+/* ============================================  INTC EINT1CONF1 CONF4 [16..19]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT1CONF1_CONF4                                                     */
+  INTC_EINT1CONF1_CONF4_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF1_CONF4_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF1_CONF4_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF1_CONF4_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF1_CONF4_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF1_CONF4_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF1_CONF4_Enum;
+
+/* ============================================  INTC EINT1CONF1 CONF3 [12..15]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT1CONF1_CONF3                                                     */
+  INTC_EINT1CONF1_CONF3_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF1_CONF3_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF1_CONF3_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF1_CONF3_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF1_CONF3_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF1_CONF3_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF1_CONF3_Enum;
+
+/* =============================================  INTC EINT1CONF1 CONF2 [8..11]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT1CONF1_CONF2                                                     */
+  INTC_EINT1CONF1_CONF2_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF1_CONF2_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF1_CONF2_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF1_CONF2_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF1_CONF2_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF1_CONF2_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF1_CONF2_Enum;
+
+/* =============================================  INTC EINT1CONF1 CONF1 [4..7]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT1CONF1_CONF1                                                     */
+  INTC_EINT1CONF1_CONF1_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF1_CONF1_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF1_CONF1_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF1_CONF1_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF1_CONF1_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF1_CONF1_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF1_CONF1_Enum;
+
+/* =============================================  INTC EINT1CONF1 CONF0 [0..3]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT1CONF1_CONF0                                                     */
+  INTC_EINT1CONF1_CONF0_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF1_CONF0_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF1_CONF0_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF1_CONF0_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF1_CONF0_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF1_CONF0_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF1_CONF0_Enum;
+
+/* ======================================================  EINT2CONF1  ======================================================= */
+/* ============================================  INTC EINT2CONF1 CONF7 [28..31]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT2CONF1_CONF7                                                     */
+  INTC_EINT2CONF1_CONF7_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF1_CONF7_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF1_CONF7_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF1_CONF7_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF1_CONF7_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF1_CONF7_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF1_CONF7_Enum;
+
+/* ============================================  INTC EINT2CONF1 CONF6 [24..27]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT2CONF1_CONF6                                                     */
+  INTC_EINT2CONF1_CONF6_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF1_CONF6_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF1_CONF6_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF1_CONF6_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF1_CONF6_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF1_CONF6_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF1_CONF6_Enum;
+
+/* ============================================  INTC EINT2CONF1 CONF5 [20..23]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT2CONF1_CONF5                                                     */
+  INTC_EINT2CONF1_CONF5_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF1_CONF5_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF1_CONF5_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF1_CONF5_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF1_CONF5_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF1_CONF5_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF1_CONF5_Enum;
+
+/* ============================================  INTC EINT2CONF1 CONF4 [16..19]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT2CONF1_CONF4                                                     */
+  INTC_EINT2CONF1_CONF4_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF1_CONF4_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF1_CONF4_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF1_CONF4_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF1_CONF4_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF1_CONF4_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF1_CONF4_Enum;
+
+/* ============================================  INTC EINT2CONF1 CONF3 [12..15]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT2CONF1_CONF3                                                     */
+  INTC_EINT2CONF1_CONF3_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF1_CONF3_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF1_CONF3_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF1_CONF3_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF1_CONF3_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF1_CONF3_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF1_CONF3_Enum;
+
+/* =============================================  INTC EINT2CONF1 CONF2 [8..11]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT2CONF1_CONF2                                                     */
+  INTC_EINT2CONF1_CONF2_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF1_CONF2_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF1_CONF2_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF1_CONF2_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF1_CONF2_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF1_CONF2_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF1_CONF2_Enum;
+
+/* =============================================  INTC EINT2CONF1 CONF1 [4..7]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT2CONF1_CONF1                                                     */
+  INTC_EINT2CONF1_CONF1_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF1_CONF1_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF1_CONF1_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF1_CONF1_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF1_CONF1_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF1_CONF1_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF1_CONF1_Enum;
+
+/* =============================================  INTC EINT2CONF1 CONF0 [0..3]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT2CONF1_CONF0                                                     */
+  INTC_EINT2CONF1_CONF0_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF1_CONF0_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF1_CONF0_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF1_CONF0_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF1_CONF0_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF1_CONF0_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF1_CONF0_Enum;
+
+/* ======================================================  EINT3CONF1  ======================================================= */
+/* ============================================  INTC EINT3CONF1 CONF7 [28..31]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT3CONF1_CONF7                                                     */
+  INTC_EINT3CONF1_CONF7_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF1_CONF7_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF1_CONF7_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF1_CONF7_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF1_CONF7_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF1_CONF7_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF1_CONF7_Enum;
+
+/* ============================================  INTC EINT3CONF1 CONF6 [24..27]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT3CONF1_CONF6                                                     */
+  INTC_EINT3CONF1_CONF6_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF1_CONF6_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF1_CONF6_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF1_CONF6_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF1_CONF6_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF1_CONF6_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF1_CONF6_Enum;
+
+/* ============================================  INTC EINT3CONF1 CONF5 [20..23]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT3CONF1_CONF5                                                     */
+  INTC_EINT3CONF1_CONF5_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF1_CONF5_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF1_CONF5_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF1_CONF5_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF1_CONF5_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF1_CONF5_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF1_CONF5_Enum;
+
+/* ============================================  INTC EINT3CONF1 CONF4 [16..19]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT3CONF1_CONF4                                                     */
+  INTC_EINT3CONF1_CONF4_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF1_CONF4_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF1_CONF4_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF1_CONF4_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF1_CONF4_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF1_CONF4_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF1_CONF4_Enum;
+
+/* ============================================  INTC EINT3CONF1 CONF3 [12..15]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT3CONF1_CONF3                                                     */
+  INTC_EINT3CONF1_CONF3_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF1_CONF3_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF1_CONF3_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF1_CONF3_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF1_CONF3_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF1_CONF3_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF1_CONF3_Enum;
+
+/* =============================================  INTC EINT3CONF1 CONF2 [8..11]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT3CONF1_CONF2                                                     */
+  INTC_EINT3CONF1_CONF2_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF1_CONF2_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF1_CONF2_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF1_CONF2_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF1_CONF2_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF1_CONF2_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF1_CONF2_Enum;
+
+/* =============================================  INTC EINT3CONF1 CONF1 [4..7]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT3CONF1_CONF1                                                     */
+  INTC_EINT3CONF1_CONF1_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF1_CONF1_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF1_CONF1_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF1_CONF1_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF1_CONF1_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF1_CONF1_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF1_CONF1_Enum;
+
+/* =============================================  INTC EINT3CONF1 CONF0 [0..3]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT3CONF1_CONF0                                                     */
+  INTC_EINT3CONF1_CONF0_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF1_CONF0_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF1_CONF0_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF1_CONF0_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF1_CONF0_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF1_CONF0_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF1_CONF0_Enum;
+
+/* ======================================================  EINT0CONF2  ======================================================= */
+/* ============================================  INTC EINT0CONF2 CONF11 [12..15]  ============================================ */
+typedef enum {                                  /*!< INTC_EINT0CONF2_CONF11                                                    */
+  INTC_EINT0CONF2_CONF11_PA            = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF2_CONF11_PB            = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF2_CONF11_PC            = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF2_CONF11_PD            = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF2_CONF11_PE            = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF2_CONF11_PF            = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF2_CONF11_Enum;
+
+/* ============================================  INTC EINT0CONF2 CONF10 [8..11]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT0CONF2_CONF10                                                    */
+  INTC_EINT0CONF2_CONF10_PA            = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF2_CONF10_PB            = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF2_CONF10_PC            = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF2_CONF10_PD            = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF2_CONF10_PE            = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF2_CONF10_PF            = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF2_CONF10_Enum;
+
+/* =============================================  INTC EINT0CONF2 CONF9 [4..7]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT0CONF2_CONF9                                                     */
+  INTC_EINT0CONF2_CONF9_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF2_CONF9_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF2_CONF9_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF2_CONF9_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF2_CONF9_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF2_CONF9_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF2_CONF9_Enum;
+
+/* =============================================  INTC EINT0CONF2 CONF8 [0..3]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT0CONF2_CONF8                                                     */
+  INTC_EINT0CONF2_CONF8_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT0CONF2_CONF8_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT0CONF2_CONF8_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT0CONF2_CONF8_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT0CONF2_CONF8_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT0CONF2_CONF8_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT0CONF2_CONF8_Enum;
+
+/* ======================================================  EINT1CONF2  ======================================================= */
+/* ============================================  INTC EINT1CONF2 CONF11 [12..15]  ============================================ */
+typedef enum {                                  /*!< INTC_EINT1CONF2_CONF11                                                    */
+  INTC_EINT1CONF2_CONF11_PA            = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF2_CONF11_PB            = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF2_CONF11_PC            = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF2_CONF11_PD            = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF2_CONF11_PE            = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF2_CONF11_PF            = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF2_CONF11_Enum;
+
+/* ============================================  INTC EINT1CONF2 CONF10 [8..11]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT1CONF2_CONF10                                                    */
+  INTC_EINT1CONF2_CONF10_PA            = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF2_CONF10_PB            = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF2_CONF10_PC            = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF2_CONF10_PD            = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF2_CONF10_PE            = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF2_CONF10_PF            = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF2_CONF10_Enum;
+
+/* =============================================  INTC EINT1CONF2 CONF9 [4..7]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT1CONF2_CONF9                                                     */
+  INTC_EINT1CONF2_CONF9_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF2_CONF9_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF2_CONF9_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF2_CONF9_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF2_CONF9_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF2_CONF9_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF2_CONF9_Enum;
+
+/* =============================================  INTC EINT1CONF2 CONF8 [0..3]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT1CONF2_CONF8                                                     */
+  INTC_EINT1CONF2_CONF8_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT1CONF2_CONF8_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT1CONF2_CONF8_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT1CONF2_CONF8_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT1CONF2_CONF8_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT1CONF2_CONF8_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT1CONF2_CONF8_Enum;
+
+/* ======================================================  EINT2CONF2  ======================================================= */
+/* ============================================  INTC EINT2CONF2 CONF11 [12..15]  ============================================ */
+typedef enum {                                  /*!< INTC_EINT2CONF2_CONF11                                                    */
+  INTC_EINT2CONF2_CONF11_PA            = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF2_CONF11_PB            = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF2_CONF11_PC            = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF2_CONF11_PD            = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF2_CONF11_PE            = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF2_CONF11_PF            = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF2_CONF11_Enum;
+
+/* ============================================  INTC EINT2CONF2 CONF10 [8..11]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT2CONF2_CONF10                                                    */
+  INTC_EINT2CONF2_CONF10_PA            = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF2_CONF10_PB            = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF2_CONF10_PC            = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF2_CONF10_PD            = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF2_CONF10_PE            = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF2_CONF10_PF            = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF2_CONF10_Enum;
+
+/* =============================================  INTC EINT2CONF2 CONF9 [4..7]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT2CONF2_CONF9                                                     */
+  INTC_EINT2CONF2_CONF9_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF2_CONF9_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF2_CONF9_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF2_CONF9_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF2_CONF9_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF2_CONF9_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF2_CONF9_Enum;
+
+/* =============================================  INTC EINT2CONF2 CONF8 [0..3]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT2CONF2_CONF8                                                     */
+  INTC_EINT2CONF2_CONF8_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT2CONF2_CONF8_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT2CONF2_CONF8_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT2CONF2_CONF8_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT2CONF2_CONF8_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT2CONF2_CONF8_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT2CONF2_CONF8_Enum;
+
+/* ======================================================  EINT3CONF2  ======================================================= */
+/* ============================================  INTC EINT3CONF2 CONF11 [12..15]  ============================================ */
+typedef enum {                                  /*!< INTC_EINT3CONF2_CONF11                                                    */
+  INTC_EINT3CONF2_CONF11_PA            = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF2_CONF11_PB            = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF2_CONF11_PC            = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF2_CONF11_PD            = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF2_CONF11_PE            = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF2_CONF11_PF            = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF2_CONF11_Enum;
+
+/* ============================================  INTC EINT3CONF2 CONF10 [8..11]  ============================================= */
+typedef enum {                                  /*!< INTC_EINT3CONF2_CONF10                                                    */
+  INTC_EINT3CONF2_CONF10_PA            = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF2_CONF10_PB            = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF2_CONF10_PC            = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF2_CONF10_PD            = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF2_CONF10_PE            = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF2_CONF10_PF            = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF2_CONF10_Enum;
+
+/* =============================================  INTC EINT3CONF2 CONF9 [4..7]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT3CONF2_CONF9                                                     */
+  INTC_EINT3CONF2_CONF9_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF2_CONF9_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF2_CONF9_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF2_CONF9_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF2_CONF9_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF2_CONF9_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF2_CONF9_Enum;
+
+/* =============================================  INTC EINT3CONF2 CONF8 [0..3]  ============================================== */
+typedef enum {                                  /*!< INTC_EINT3CONF2_CONF8                                                     */
+  INTC_EINT3CONF2_CONF8_PA             = 0,     /*!< PA : Select PA.                                                           */
+  INTC_EINT3CONF2_CONF8_PB             = 1,     /*!< PB : Select PB.                                                           */
+  INTC_EINT3CONF2_CONF8_PC             = 2,     /*!< PC : Select PC.                                                           */
+  INTC_EINT3CONF2_CONF8_PD             = 3,     /*!< PD : Select PD.                                                           */
+  INTC_EINT3CONF2_CONF8_PE             = 4,     /*!< PE : Select PE.                                                           */
+  INTC_EINT3CONF2_CONF8_PF             = 5,     /*!< PF : Select PF.                                                           */
+} INTC_EINT3CONF2_CONF8_Enum;
+
+/* ==========================================================  MSK  ========================================================== */
+/* =============================================  INTC MSK IMSK31_NULL [31..31]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK31_NULL                                                      */
+  INTC_MSK_IMSK31_NULL_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK31_NULL_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK31_NULL_Enum;
+
+/* =============================================  INTC MSK IMSK30_NULL [30..30]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK30_NULL                                                      */
+  INTC_MSK_IMSK30_NULL_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK30_NULL_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK30_NULL_Enum;
+
+/* =============================================  INTC MSK IMSK29_NULL [29..29]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK29_NULL                                                      */
+  INTC_MSK_IMSK29_NULL_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK29_NULL_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK29_NULL_Enum;
+
+/* =============================================  INTC MSK IMSK28_NULL [28..28]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK28_NULL                                                      */
+  INTC_MSK_IMSK28_NULL_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK28_NULL_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK28_NULL_Enum;
+
+/* ===========================================  INTC MSK IMSK27_USART13 [27..27]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK27_USART13                                                   */
+  INTC_MSK_IMSK27_USART13_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK27_USART13_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK27_USART13_Enum;
+
+/* ===========================================  INTC MSK IMSK26_USART12 [26..26]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK26_USART12                                                   */
+  INTC_MSK_IMSK26_USART12_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK26_USART12_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK26_USART12_Enum;
+
+/* =============================================  INTC MSK IMSK25_I2C2 [25..25]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK25_I2C2                                                      */
+  INTC_MSK_IMSK25_I2C2_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK25_I2C2_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK25_I2C2_Enum;
+
+/* ===========================================  INTC MSK IMSK24_TIMER16 [24..24]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK24_TIMER16                                                   */
+  INTC_MSK_IMSK24_TIMER16_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK24_TIMER16_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK24_TIMER16_Enum;
+
+/* ===========================================  INTC MSK IMSK23_TIMER15 [23..23]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK23_TIMER15                                                   */
+  INTC_MSK_IMSK23_TIMER15_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK23_TIMER15_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK23_TIMER15_Enum;
+
+/* ===========================================  INTC MSK IMSK22_TIMER14 [22..22]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK22_TIMER14                                                   */
+  INTC_MSK_IMSK22_TIMER14_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK22_TIMER14_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK22_TIMER14_Enum;
+
+/* ===========================================  INTC MSK IMSK21_TIMER13 [21..21]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK21_TIMER13                                                   */
+  INTC_MSK_IMSK21_TIMER13_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK21_TIMER13_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK21_TIMER13_Enum;
+
+/* ============================================  INTC MSK IMSK20_UART1 [20..20]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK20_UART1                                                     */
+  INTC_MSK_IMSK20_UART1_Mask           = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK20_UART1_Unmask         = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK20_UART1_Enum;
+
+/* ============================================  INTC MSK IMSK19_UART0 [19..19]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK19_UART0                                                     */
+  INTC_MSK_IMSK19_UART0_Mask           = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK19_UART0_Unmask         = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK19_UART0_Enum;
+
+/* =============================================  INTC MSK IMSK18_ADC [18..18]  ============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK18_ADC                                                       */
+  INTC_MSK_IMSK18_ADC_Mask             = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK18_ADC_Unmask           = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK18_ADC_Enum;
+
+/* ===========================================  INTC MSK IMSK17_USART11 [17..17]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK17_USART11                                                   */
+  INTC_MSK_IMSK17_USART11_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK17_USART11_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK17_USART11_Enum;
+
+/* ===========================================  INTC MSK IMSK16_TIMER21 [16..16]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK16_TIMER21                                                   */
+  INTC_MSK_IMSK16_TIMER21_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK16_TIMER21_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK16_TIMER21_Enum;
+
+/* ===========================================  INTC MSK IMSK15_TIMER20 [15..15]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK15_TIMER20                                                   */
+  INTC_MSK_IMSK15_TIMER20_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK15_TIMER20_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK15_TIMER20_Enum;
+
+/* =============================================  INTC MSK IMSK14_I2C1 [14..14]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK14_I2C1                                                      */
+  INTC_MSK_IMSK14_I2C1_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK14_I2C1_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK14_I2C1_Enum;
+
+/* ===========================================  INTC MSK IMSK13_TIMER30 [13..13]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK13_TIMER30                                                   */
+  INTC_MSK_IMSK13_TIMER30_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK13_TIMER30_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK13_TIMER30_Enum;
+
+/* ==============================================  INTC MSK IMSK12_WT [12..12]  ============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK12_WT                                                        */
+  INTC_MSK_IMSK12_WT_Mask              = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK12_WT_Unmask            = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK12_WT_Enum;
+
+/* ===========================================  INTC MSK IMSK11_USART10 [11..11]  ============================================ */
+typedef enum {                                  /*!< INTC_MSK_IMSK11_USART10                                                   */
+  INTC_MSK_IMSK11_USART10_Mask         = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK11_USART10_Unmask       = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK11_USART10_Enum;
+
+/* =============================================  INTC MSK IMSK10_I2C0 [10..10]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK10_I2C0                                                      */
+  INTC_MSK_IMSK10_I2C0_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK10_I2C0_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK10_I2C0_Enum;
+
+/* =============================================  INTC MSK IMSK9_TIMER12 [9..9]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK9_TIMER12                                                    */
+  INTC_MSK_IMSK9_TIMER12_Mask          = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK9_TIMER12_Unmask        = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK9_TIMER12_Enum;
+
+/* =============================================  INTC MSK IMSK8_TIMER11 [8..8]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK8_TIMER11                                                    */
+  INTC_MSK_IMSK8_TIMER11_Mask          = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK8_TIMER11_Unmask        = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK8_TIMER11_Enum;
+
+/* =============================================  INTC MSK IMSK7_TIMER10 [7..7]  ============================================= */
+typedef enum {                                  /*!< INTC_MSK_IMSK7_TIMER10                                                    */
+  INTC_MSK_IMSK7_TIMER10_Mask          = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK7_TIMER10_Unmask        = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK7_TIMER10_Enum;
+
+/* ==============================================  INTC MSK IMSK6_EINT3 [6..6]  ============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK6_EINT3                                                      */
+  INTC_MSK_IMSK6_EINT3_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK6_EINT3_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK6_EINT3_Enum;
+
+/* ==============================================  INTC MSK IMSK5_EINT2 [5..5]  ============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK5_EINT2                                                      */
+  INTC_MSK_IMSK5_EINT2_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK5_EINT2_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK5_EINT2_Enum;
+
+/* ==============================================  INTC MSK IMSK4_EINT1 [4..4]  ============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK4_EINT1                                                      */
+  INTC_MSK_IMSK4_EINT1_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK4_EINT1_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK4_EINT1_Enum;
+
+/* ==============================================  INTC MSK IMSK3_EINT0 [3..3]  ============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK3_EINT0                                                      */
+  INTC_MSK_IMSK3_EINT0_Mask            = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK3_EINT0_Unmask          = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK3_EINT0_Enum;
+
+/* ===============================================  INTC MSK IMSK2_WDT [2..2]  =============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK2_WDT                                                        */
+  INTC_MSK_IMSK2_WDT_Mask              = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK2_WDT_Unmask            = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK2_WDT_Enum;
+
+/* ===============================================  INTC MSK IMSK1_WUT [1..1]  =============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK1_WUT                                                        */
+  INTC_MSK_IMSK1_WUT_Mask              = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK1_WUT_Unmask            = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK1_WUT_Enum;
+
+/* ===============================================  INTC MSK IMSK0_LVI [0..0]  =============================================== */
+typedef enum {                                  /*!< INTC_MSK_IMSK0_LVI                                                        */
+  INTC_MSK_IMSK0_LVI_Mask              = 0,     /*!< Mask : Mask Interrupt Source                                              */
+  INTC_MSK_IMSK0_LVI_Unmask            = 1,     /*!< Unmask : Unmask Interrupt Source                                          */
+} INTC_MSK_IMSK0_LVI_Enum;
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCUCC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  VENDORID  ======================================================== */
+/* ========================================================  CHIPID  ========================================================= */
+/* =========================================================  REVNR  ========================================================= */
+/* ========================================================  PMREMAP  ======================================================== */
+/* =============================================  SCUCC PMREMAP WTIDKY [16..31]  ============================================= */
+typedef enum {                                  /*!< SCUCC_PMREMAP_WTIDKY                                                      */
+  SCUCC_PMREMAP_WTIDKY_Value           = 58097, /*!< Value : Key Value (0xe2f1)                                                */
+} SCUCC_PMREMAP_WTIDKY_Enum;
+
+/* =============================================  SCUCC PMREMAP nPMREM [8..15]  ============================================== */
+typedef enum {                                  /*!< SCUCC_PMREMAP_nPMREM                                                      */
+  SCUCC_PMREMAP_nPMREM_BootROM         = 150,   /*!< BootROM : Boot ROM is re-mapped to address 0x0. (0x96)                    */
+  SCUCC_PMREMAP_nPMREM_FlashMemory     = 0,     /*!< FlashMemory : Flash Memory is re-mapped to address 0x0.                   */
+} SCUCC_PMREMAP_nPMREM_Enum;
+
+/* ==============================================  SCUCC PMREMAP PMREM [0..7]  =============================================== */
+typedef enum {                                  /*!< SCUCC_PMREMAP_PMREM                                                       */
+  SCUCC_PMREMAP_PMREM_BootROM          = 105,   /*!< BootROM : Boot ROM is re-mapped to address 0x0. (0x69)                    */
+  SCUCC_PMREMAP_PMREM_FlashMemory      = 0,     /*!< FlashMemory : Flash Memory is re-mapped to address 0x0.                   */
+} SCUCC_PMREMAP_PMREM_Enum;
+
+/* ========================================================  BTPSCR  ========================================================= */
+/* ===============================================  SCUCC BTPSCR BFIND [5..6]  =============================================== */
+typedef enum {                                  /*!< SCUCC_BTPSCR_BFIND                                                        */
+  SCUCC_BTPSCR_BFIND_PORorEXTR         = 2,     /*!< PORorEXTR : Check the BOOT pin when a system reset occurs by
+                                                     nRESET including POR.                                                     */
+  SCUCC_BTPSCR_BFIND_POR               = 3,     /*!< POR : Check the BOOT pin when a system reset occurs only by
+                                                     POR.                                                                      */
+} SCUCC_BTPSCR_BFIND_Enum;
+
+/* ==============================================  SCUCC BTPSCR BTPSTA [0..0]  =============================================== */
+typedef enum {                                  /*!< SCUCC_BTPSCR_BTPSTA                                                       */
+  SCUCC_BTPSCR_BTPSTA_Low              = 0,     /*!< Low : The BOOT pin is low level.                                          */
+  SCUCC_BTPSCR_BTPSTA_High             = 1,     /*!< High : The BOOT pin is high level.                                        */
+} SCUCC_BTPSCR_BTPSTA_Enum;
+
+/* ========================================================  RSTSSR  ========================================================= */
+/* ==============================================  SCUCC RSTSSR MONSTA [5..5]  =============================================== */
+typedef enum {                                  /*!< SCUCC_RSTSSR_MONSTA                                                       */
+  SCUCC_RSTSSR_MONSTA_NotDetected      = 0,     /*!< NotDetected : Not detected.                                               */
+  SCUCC_RSTSSR_MONSTA_Detected         = 1,     /*!< Detected : CMR was detected.                                              */
+} SCUCC_RSTSSR_MONSTA_Enum;
+
+/* ===============================================  SCUCC RSTSSR SWSTA [4..4]  =============================================== */
+typedef enum {                                  /*!< SCUCC_RSTSSR_SWSTA                                                        */
+  SCUCC_RSTSSR_SWSTA_NotDetected       = 0,     /*!< NotDetected : Not detected.                                               */
+  SCUCC_RSTSSR_SWSTA_Detected          = 1,     /*!< Detected : SWR was detected.                                              */
+} SCUCC_RSTSSR_SWSTA_Enum;
+
+/* ==============================================  SCUCC RSTSSR EXTSTA [3..3]  =============================================== */
+typedef enum {                                  /*!< SCUCC_RSTSSR_EXTSTA                                                       */
+  SCUCC_RSTSSR_EXTSTA_NotDetected      = 0,     /*!< NotDetected : Not detected.                                               */
+  SCUCC_RSTSSR_EXTSTA_Detected         = 1,     /*!< Detected : EXTR was detected.                                             */
+} SCUCC_RSTSSR_EXTSTA_Enum;
+
+/* ==============================================  SCUCC RSTSSR WDTSTA [2..2]  =============================================== */
+typedef enum {                                  /*!< SCUCC_RSTSSR_WDTSTA                                                       */
+  SCUCC_RSTSSR_WDTSTA_NotDetected      = 0,     /*!< NotDetected : Not detected.                                               */
+  SCUCC_RSTSSR_WDTSTA_Detected         = 1,     /*!< Detected : WDTR was detected.                                             */
+} SCUCC_RSTSSR_WDTSTA_Enum;
+
+/* ==============================================  SCUCC RSTSSR LVRSTA [1..1]  =============================================== */
+typedef enum {                                  /*!< SCUCC_RSTSSR_LVRSTA                                                       */
+  SCUCC_RSTSSR_LVRSTA_NotDetected      = 0,     /*!< NotDetected : Not detected.                                               */
+  SCUCC_RSTSSR_LVRSTA_Detected         = 1,     /*!< Detected : LVR was detected.                                              */
+} SCUCC_RSTSSR_LVRSTA_Enum;
+
+/* ==============================================  SCUCC RSTSSR PORSTA [0..0]  =============================================== */
+typedef enum {                                  /*!< SCUCC_RSTSSR_PORSTA                                                       */
+  SCUCC_RSTSSR_PORSTA_NotDetected      = 0,     /*!< NotDetected : Not detected.                                               */
+  SCUCC_RSTSSR_PORSTA_Detected         = 1,     /*!< Detected : POR was detected.                                              */
+} SCUCC_RSTSSR_PORSTA_Enum;
+
+/* ========================================================  NMISRCR  ======================================================== */
+/* ==============================================  SCUCC NMISRCR NMICON [7..7]  ============================================== */
+typedef enum {                                  /*!< SCUCC_NMISRCR_NMICON                                                      */
+  SCUCC_NMISRCR_NMICON_Disable         = 0,     /*!< Disable : Disable NMI.                                                    */
+  SCUCC_NMISRCR_NMICON_Enable          = 1,     /*!< Enable : Enable NMI.                                                      */
+} SCUCC_NMISRCR_NMICON_Enum;
+
+/* ==============================================  SCUCC NMISRCR MONINT [6..6]  ============================================== */
+typedef enum {                                  /*!< SCUCC_NMISRCR_MONINT                                                      */
+  SCUCC_NMISRCR_MONINT_NotSelect       = 0,     /*!< NotSelect : Non-select clock monitoring interrupt for NMI source.         */
+  SCUCC_NMISRCR_MONINT_Select          = 1,     /*!< Select : Select clock monitoring interrupt for NMI source.                */
+} SCUCC_NMISRCR_MONINT_Enum;
+
+/* ========================================================  SWRSTR  ========================================================= */
+/* =============================================  SCUCC SWRSTR WTIDKY [16..31]  ============================================== */
+typedef enum {                                  /*!< SCUCC_SWRSTR_WTIDKY                                                       */
+  SCUCC_SWRSTR_WTIDKY_Value            = 40627, /*!< Value : Key Value (0x9eb3)                                                */
+} SCUCC_SWRSTR_WTIDKY_Enum;
+
+/* ===============================================  SCUCC SWRSTR SWRST [0..7]  =============================================== */
+typedef enum {                                  /*!< SCUCC_SWRSTR_SWRST                                                        */
+  SCUCC_SWRSTR_SWRST_Generate          = 45,    /*!< Generate : A software reset will be generated for all peripheral
+                                                     and core. (0x2d)                                                          */
+  SCUCC_SWRSTR_SWRST_NoEffect          = 0,     /*!< NoEffect : No effect.                                                     */
+} SCUCC_SWRSTR_SWRST_Enum;
+
+/* ========================================================  SRSTVR  ========================================================= */
+/* =========================================================  WUTCR  ========================================================= */
+/* ===============================================  SCUCC WUTCR WUTIEN [7..7]  =============================================== */
+typedef enum {                                  /*!< SCUCC_WUTCR_WUTIEN                                                        */
+  SCUCC_WUTCR_WUTIEN_Disable           = 0,     /*!< Disable : Disable Wake-Up Timer interrupt.                                */
+  SCUCC_WUTCR_WUTIEN_Enable            = 1,     /*!< Enable : Enable Wake-Up Timer interrupt.                                  */
+} SCUCC_WUTCR_WUTIEN_Enum;
+
+/* ===============================================  SCUCC WUTCR CNTRLD [1..1]  =============================================== */
+typedef enum {                                  /*!< SCUCC_WUTCR_CNTRLD                                                        */
+  SCUCC_WUTCR_CNTRLD_NoEffect          = 0,     /*!< NoEffect : No effect.                                                     */
+  SCUCC_WUTCR_CNTRLD_Reload            = 1,     /*!< Reload : Reload data to counter.                                          */
+} SCUCC_WUTCR_CNTRLD_Enum;
+
+/* ==============================================  SCUCC WUTCR WUTIFLAG [0..0]  ============================================== */
+typedef enum {                                  /*!< SCUCC_WUTCR_WUTIFLAG                                                      */
+  SCUCC_WUTCR_WUTIFLAG_NoRequest       = 0,     /*!< NoRequest : No request occurred.                                          */
+  SCUCC_WUTCR_WUTIFLAG_Request         = 1,     /*!< Request : Request occurred.                                               */
+} SCUCC_WUTCR_WUTIFLAG_Enum;
+
+/* =========================================================  WUTDR  ========================================================= */
+/* ========================================================  HIRCTRM  ======================================================== */
+/* =============================================  SCUCC HIRCTRM WTIDKY [16..31]  ============================================= */
+typedef enum {                                  /*!< SCUCC_HIRCTRM_WTIDKY                                                      */
+  SCUCC_HIRCTRM_WTIDKY_Value           = 42677, /*!< Value : Key Value (0xa6b5)                                                */
+} SCUCC_HIRCTRM_WTIDKY_Enum;
+
+/* =======================================================  WDTRCTRM  ======================================================== */
+/* ============================================  SCUCC WDTRCTRM WTIDKY [16..31]  ============================================= */
+typedef enum {                                  /*!< SCUCC_WDTRCTRM_WTIDKY                                                     */
+  SCUCC_WDTRCTRM_WTIDKY_Value          = 19517, /*!< Value : Key Value (0x4c3d)                                                */
+} SCUCC_WDTRCTRM_WTIDKY_Enum;
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCUCG                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SCCR  ========================================================== */
+/* ==============================================  SCUCG SCCR WTIDKY [16..31]  =============================================== */
+typedef enum {                                  /*!< SCUCG_SCCR_WTIDKY                                                         */
+  SCUCG_SCCR_WTIDKY_Value              = 22282, /*!< Value : Key Value (0x570a)                                                */
+} SCUCG_SCCR_WTIDKY_Enum;
+
+/* ===============================================  SCUCG SCCR MCLKSEL [0..1]  =============================================== */
+typedef enum {                                  /*!< SCUCG_SCCR_MCLKSEL                                                        */
+  SCUCG_SCCR_MCLKSEL_HIRC              = 0,     /*!< HIRC : High Frequency Internal RC Oscillator (40MHz), HIRC                */
+  SCUCG_SCCR_MCLKSEL_XMOSC             = 1,     /*!< XMOSC : External Main Oscillator (2 - 40MHz), XMOSC                       */
+  SCUCG_SCCR_MCLKSEL_XSOSC             = 2,     /*!< XSOSC : External Sub Oscillator (32.768kHz), XSOSC                        */
+  SCUCG_SCCR_MCLKSEL_WDTRC             = 3,     /*!< WDTRC : Internal Watch-Dog Timer RC Oscillator (40kHz), WDTRC             */
+} SCUCG_SCCR_MCLKSEL_Enum;
+
+/* ========================================================  CLKSRCR  ======================================================== */
+/* =============================================  SCUCG CLKSRCR WTIDKY [16..31]  ============================================= */
+typedef enum {                                  /*!< SCUCG_CLKSRCR_WTIDKY                                                      */
+  SCUCG_CLKSRCR_WTIDKY_Value           = 42247, /*!< Value : Key Value (0xa507)                                                */
+} SCUCG_CLKSRCR_WTIDKY_Enum;
+
+/* ============================================  SCUCG CLKSRCR HIRCSEL [12..13]  ============================================= */
+typedef enum {                                  /*!< SCUCG_CLKSRCR_HIRCSEL                                                     */
+  SCUCG_CLKSRCR_HIRCSEL_HIRC1          = 0,     /*!< HIRC1 : 40MHz HIRC                                                        */
+  SCUCG_CLKSRCR_HIRCSEL_HIRC2          = 1,     /*!< HIRC2 : 20MHz HIRC                                                        */
+  SCUCG_CLKSRCR_HIRCSEL_HIRC4          = 2,     /*!< HIRC4 : 10MHz HIRC                                                        */
+  SCUCG_CLKSRCR_HIRCSEL_HIRC8          = 3,     /*!< HIRC8 : 5MHz HIRC                                                         */
+} SCUCG_CLKSRCR_HIRCSEL_Enum;
+
+/* ==============================================  SCUCG CLKSRCR XMFRNG [8..8]  ============================================== */
+typedef enum {                                  /*!< SCUCG_CLKSRCR_XMFRNG                                                      */
+  SCUCG_CLKSRCR_XMFRNG_Xtal            = 0,     /*!< Xtal : X-tal for XMOSC, 2 to 16MHz                                        */
+  SCUCG_CLKSRCR_XMFRNG_Clock           = 1,     /*!< Clock : External Clock for XMOSC, 2MHz to 40MHz                           */
+} SCUCG_CLKSRCR_XMFRNG_Enum;
+
+/* =============================================  SCUCG CLKSRCR WDTRCEN [3..3]  ============================================== */
+typedef enum {                                  /*!< SCUCG_CLKSRCR_WDTRCEN                                                     */
+  SCUCG_CLKSRCR_WDTRCEN_Disable        = 0,     /*!< Disable : Disable WDTRC.                                                  */
+  SCUCG_CLKSRCR_WDTRCEN_Enable         = 1,     /*!< Enable : Enable WDTRC.                                                    */
+} SCUCG_CLKSRCR_WDTRCEN_Enum;
+
+/* ==============================================  SCUCG CLKSRCR HIRCEN [2..2]  ============================================== */
+typedef enum {                                  /*!< SCUCG_CLKSRCR_HIRCEN                                                      */
+  SCUCG_CLKSRCR_HIRCEN_Disable         = 0,     /*!< Disable : Disable HIRC.                                                   */
+  SCUCG_CLKSRCR_HIRCEN_Enable          = 1,     /*!< Enable : Enable HIRC.                                                     */
+} SCUCG_CLKSRCR_HIRCEN_Enum;
+
+/* =============================================  SCUCG CLKSRCR XMOSCEN [1..1]  ============================================== */
+typedef enum {                                  /*!< SCUCG_CLKSRCR_XMOSCEN                                                     */
+  SCUCG_CLKSRCR_XMOSCEN_Disable        = 0,     /*!< Disable : Disable XMOSC.                                                  */
+  SCUCG_CLKSRCR_XMOSCEN_Enable         = 1,     /*!< Enable : Enable XMOSC.                                                    */
+} SCUCG_CLKSRCR_XMOSCEN_Enum;
+
+/* =============================================  SCUCG CLKSRCR XSOSCEN [0..0]  ============================================== */
+typedef enum {                                  /*!< SCUCG_CLKSRCR_XSOSCEN                                                     */
+  SCUCG_CLKSRCR_XSOSCEN_Disable        = 0,     /*!< Disable : Disable XSOSC.                                                  */
+  SCUCG_CLKSRCR_XSOSCEN_Enable         = 1,     /*!< Enable : Enable XSOSC.                                                    */
+} SCUCG_CLKSRCR_XSOSCEN_Enum;
+
+/* ========================================================  SCDIVR1  ======================================================== */
+/* ==============================================  SCUCG SCDIVR1 WLDIV [4..6]  =============================================== */
+typedef enum {                                  /*!< SCUCG_SCDIVR1_WLDIV                                                       */
+  SCUCG_SCDIVR1_WLDIV_MCLK64           = 0,     /*!< MCLK64 : MCLK/64                                                          */
+  SCUCG_SCDIVR1_WLDIV_MCLK128          = 1,     /*!< MCLK128 : MCLK/128                                                        */
+  SCUCG_SCDIVR1_WLDIV_MCLK256          = 2,     /*!< MCLK256 : MCLK/256                                                        */
+  SCUCG_SCDIVR1_WLDIV_MCLK512          = 3,     /*!< MCLK512 : MCLK/512                                                        */
+  SCUCG_SCDIVR1_WLDIV_MCLK1024         = 4,     /*!< MCLK1024 : MCLK/1024                                                      */
+} SCUCG_SCDIVR1_WLDIV_Enum;
+
+/* ===============================================  SCUCG SCDIVR1 HDIV [0..2]  =============================================== */
+typedef enum {                                  /*!< SCUCG_SCDIVR1_HDIV                                                        */
+  SCUCG_SCDIVR1_HDIV_MCLK16            = 0,     /*!< MCLK16 : MCLK/16                                                          */
+  SCUCG_SCDIVR1_HDIV_MCLK8             = 1,     /*!< MCLK8 : MCLK/8                                                            */
+  SCUCG_SCDIVR1_HDIV_MCLK4             = 2,     /*!< MCLK4 : MCLK/4                                                            */
+  SCUCG_SCDIVR1_HDIV_MCLK2             = 3,     /*!< MCLK2 : MCLK/2                                                            */
+  SCUCG_SCDIVR1_HDIV_MCLK1             = 4,     /*!< MCLK1 : MCLK/1                                                            */
+} SCUCG_SCDIVR1_HDIV_Enum;
+
+/* ========================================================  SCDIVR2  ======================================================== */
+/* =============================================  SCUCG SCDIVR2 SYSTDIV [4..5]  ============================================== */
+typedef enum {                                  /*!< SCUCG_SCDIVR2_SYSTDIV                                                     */
+  SCUCG_SCDIVR2_SYSTDIV_HCLK1          = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  SCUCG_SCDIVR2_SYSTDIV_HCLK2          = 1,     /*!< HCLK2 : HCLK/2                                                            */
+  SCUCG_SCDIVR2_SYSTDIV_HCLK4          = 2,     /*!< HCLK4 : HCLK/4                                                            */
+  SCUCG_SCDIVR2_SYSTDIV_HCLK8          = 3,     /*!< HCLK8 : HCLK/8                                                            */
+} SCUCG_SCDIVR2_SYSTDIV_Enum;
+
+/* ===============================================  SCUCG SCDIVR2 PDIV [0..1]  =============================================== */
+typedef enum {                                  /*!< SCUCG_SCDIVR2_PDIV                                                        */
+  SCUCG_SCDIVR2_PDIV_HCLK1             = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  SCUCG_SCDIVR2_PDIV_HCLK2             = 1,     /*!< HCLK2 : HCLK/2                                                            */
+  SCUCG_SCDIVR2_PDIV_HCLK4             = 2,     /*!< HCLK4 : HCLK/4                                                            */
+  SCUCG_SCDIVR2_PDIV_HCLK8             = 3,     /*!< HCLK8 : HCLK/8                                                            */
+} SCUCG_SCDIVR2_PDIV_Enum;
+
+/* ========================================================  CLKOCR  ========================================================= */
+/* ==============================================  SCUCG CLKOCR CLKOEN [7..7]  =============================================== */
+typedef enum {                                  /*!< SCUCG_CLKOCR_CLKOEN                                                       */
+  SCUCG_CLKOCR_CLKOEN_Disable          = 0,     /*!< Disable : Disable clock output.                                           */
+  SCUCG_CLKOCR_CLKOEN_Enable           = 1,     /*!< Enable : Enable clock output.                                             */
+} SCUCG_CLKOCR_CLKOEN_Enum;
+
+/* ==============================================  SCUCG CLKOCR POLSEL [6..6]  =============================================== */
+typedef enum {                                  /*!< SCUCG_CLKOCR_POLSEL                                                       */
+  SCUCG_CLKOCR_POLSEL_Low              = 0,     /*!< Low : Low level during disable                                            */
+  SCUCG_CLKOCR_POLSEL_High             = 1,     /*!< High : High level during disable                                          */
+} SCUCG_CLKOCR_POLSEL_Enum;
+
+/* ==============================================  SCUCG CLKOCR CLKODIV [3..5]  ============================================== */
+typedef enum {                                  /*!< SCUCG_CLKOCR_CLKODIV                                                      */
+  SCUCG_CLKOCR_CLKODIV_SelectedClock1  = 0,     /*!< SelectedClock1 : Selected Clock/1                                         */
+  SCUCG_CLKOCR_CLKODIV_SelectedClock2  = 1,     /*!< SelectedClock2 : Selected Clock/2                                         */
+  SCUCG_CLKOCR_CLKODIV_SelectedClock4  = 2,     /*!< SelectedClock4 : Selected Clock/4                                         */
+  SCUCG_CLKOCR_CLKODIV_SelectedClock8  = 3,     /*!< SelectedClock8 : Selected Clock/8                                         */
+  SCUCG_CLKOCR_CLKODIV_SelectedClock16 = 4,     /*!< SelectedClock16 : Selected Clock/16                                       */
+  SCUCG_CLKOCR_CLKODIV_SelectedClock32 = 5,     /*!< SelectedClock32 : Selected Clock/32                                       */
+  SCUCG_CLKOCR_CLKODIV_SelectedClock64 = 6,     /*!< SelectedClock64 : Selected Clock/64                                       */
+  SCUCG_CLKOCR_CLKODIV_SelectedClock128 = 7,    /*!< SelectedClock128 : Selected Clock/128                                     */
+} SCUCG_CLKOCR_CLKODIV_Enum;
+
+/* ===============================================  SCUCG CLKOCR CLKOS [0..2]  =============================================== */
+typedef enum {                                  /*!< SCUCG_CLKOCR_CLKOS                                                        */
+  SCUCG_CLKOCR_CLKOS_MCLK              = 0,     /*!< MCLK : Select MCLK.                                                       */
+  SCUCG_CLKOCR_CLKOS_WDTRC             = 1,     /*!< WDTRC : Select WDTRC.                                                     */
+  SCUCG_CLKOCR_CLKOS_HIRC              = 2,     /*!< HIRC : Select HIRC.                                                       */
+  SCUCG_CLKOCR_CLKOS_HCLK              = 3,     /*!< HCLK : Select HCLK.                                                       */
+  SCUCG_CLKOCR_CLKOS_PCLK              = 4,     /*!< PCLK : Select PCLK.                                                       */
+} SCUCG_CLKOCR_CLKOS_Enum;
+
+/* ========================================================  CMONCR  ========================================================= */
+/* ===============================================  SCUCG CMONCR MONEN [7..7]  =============================================== */
+typedef enum {                                  /*!< SCUCG_CMONCR_MONEN                                                        */
+  SCUCG_CMONCR_MONEN_Disable           = 0,     /*!< Disable : Disable clock monitoring.                                       */
+  SCUCG_CMONCR_MONEN_Enable            = 1,     /*!< Enable : Enable clock monitoring.                                         */
+} SCUCG_CMONCR_MONEN_Enum;
+
+/* ===============================================  SCUCG CMONCR MACTS [5..6]  =============================================== */
+typedef enum {                                  /*!< SCUCG_CMONCR_MACTS                                                        */
+  SCUCG_CMONCR_MACTS_FlagChk           = 0,     /*!< FlagChk : No action by clock monitoring, but flags will be set/cleared
+                                                     on condition                                                              */
+  SCUCG_CMONCR_MACTS_RstGen            = 1,     /*!< RstGen : Reset generation by clock monitoring                             */
+  SCUCG_CMONCR_MACTS_SysClkChg         = 2,     /*!< SysClkChg : The system clock will be changed to the WDTRC regardless
+                                                     of MCLKSEL[1:0] bits of system clock control register (SCU_SCCR)
+                                                     only when the MCLK is selected for monitoring                             */
+} SCUCG_CMONCR_MACTS_Enum;
+
+/* ==============================================  SCUCG CMONCR MONFLAG [3..3]  ============================================== */
+typedef enum {                                  /*!< SCUCG_CMONCR_MONFLAG                                                      */
+  SCUCG_CMONCR_MONFLAG_NotReady        = 0,     /*!< NotReady : The clock to be monitored is not ready                         */
+  SCUCG_CMONCR_MONFLAG_Ready           = 1,     /*!< Ready : The clock to be monitored is ready                                */
+} SCUCG_CMONCR_MONFLAG_Enum;
+
+/* ==============================================  SCUCG CMONCR NMINTFG [2..2]  ============================================== */
+typedef enum {                                  /*!< SCUCG_CMONCR_NMINTFG                                                      */
+  SCUCG_CMONCR_NMINTFG_NoRequest       = 0,     /*!< NoRequest : No request occurred.                                          */
+  SCUCG_CMONCR_NMINTFG_Request         = 1,     /*!< Request : Request occurred.                                               */
+} SCUCG_CMONCR_NMINTFG_Enum;
+
+/* ===============================================  SCUCG CMONCR MONCS [0..1]  =============================================== */
+typedef enum {                                  /*!< SCUCG_CMONCR_MONCS                                                        */
+  SCUCG_CMONCR_MONCS_MCLK              = 0,     /*!< MCLK : Select MCLK.                                                       */
+  SCUCG_CMONCR_MONCS_HIRC              = 1,     /*!< HIRC : Select HIRC.                                                       */
+  SCUCG_CMONCR_MONCS_XMOSC             = 2,     /*!< XMOSC : Select XMOSC.                                                     */
+  SCUCG_CMONCR_MONCS_XSOSC             = 3,     /*!< XSOSC : Select XSOSC.                                                     */
+} SCUCG_CMONCR_MONCS_Enum;
+
+/* =======================================================  PPCLKEN1  ======================================================== */
+/* ============================================  SCUCG PPCLKEN1 T21CLKE [21..21]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T21CLKE                                                    */
+  SCUCG_PPCLKEN1_T21CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T21CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T21CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN1 T20CLKE [20..20]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T20CLKE                                                    */
+  SCUCG_PPCLKEN1_T20CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T20CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T20CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN1 T30CLKE [19..19]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T30CLKE                                                    */
+  SCUCG_PPCLKEN1_T30CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T30CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T30CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN1 T12CLKE [18..18]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T12CLKE                                                    */
+  SCUCG_PPCLKEN1_T12CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T12CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T12CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN1 T11CLKE [17..17]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T11CLKE                                                    */
+  SCUCG_PPCLKEN1_T11CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T11CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T11CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN1 T10CLKE [16..16]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T10CLKE                                                    */
+  SCUCG_PPCLKEN1_T10CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T10CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T10CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN1 T16CLKE [11..11]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T16CLKE                                                    */
+  SCUCG_PPCLKEN1_T16CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T16CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T16CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN1 T15CLKE [10..10]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T15CLKE                                                    */
+  SCUCG_PPCLKEN1_T15CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T15CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T15CLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN1 T14CLKE [9..9]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T14CLKE                                                    */
+  SCUCG_PPCLKEN1_T14CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T14CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T14CLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN1 T13CLKE [8..8]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_T13CLKE                                                    */
+  SCUCG_PPCLKEN1_T13CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_T13CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_T13CLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN1 PFCLKE [5..5]  ============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_PFCLKE                                                     */
+  SCUCG_PPCLKEN1_PFCLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_PFCLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_PFCLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN1 PECLKE [4..4]  ============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_PECLKE                                                     */
+  SCUCG_PPCLKEN1_PECLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_PECLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_PECLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN1 PDCLKE [3..3]  ============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_PDCLKE                                                     */
+  SCUCG_PPCLKEN1_PDCLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_PDCLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_PDCLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN1 PCCLKE [2..2]  ============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_PCCLKE                                                     */
+  SCUCG_PPCLKEN1_PCCLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_PCCLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_PCCLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN1 PBCLKE [1..1]  ============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_PBCLKE                                                     */
+  SCUCG_PPCLKEN1_PBCLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_PBCLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_PBCLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN1 PACLKE [0..0]  ============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKEN1_PACLKE                                                     */
+  SCUCG_PPCLKEN1_PACLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN1_PACLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN1_PACLKE_Enum;
+
+/* =======================================================  PPCLKEN2  ======================================================== */
+/* ============================================  SCUCG PPCLKEN2 FMCLKE [19..19]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_FMCLKE                                                     */
+  SCUCG_PPCLKEN2_FMCLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_FMCLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_FMCLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 LVICLKE [18..18]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_LVICLKE                                                    */
+  SCUCG_PPCLKEN2_LVICLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_LVICLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_LVICLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 WDTCLKE [17..17]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_WDTCLKE                                                    */
+  SCUCG_PPCLKEN2_WDTCLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_WDTCLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_WDTCLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 WTCLKE [16..16]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_WTCLKE                                                     */
+  SCUCG_PPCLKEN2_WTCLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_WTCLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_WTCLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 LCDCLKE [13..13]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_LCDCLKE                                                    */
+  SCUCG_PPCLKEN2_LCDCLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_LCDCLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_LCDCLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 CRCLKE [12..12]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_CRCLKE                                                     */
+  SCUCG_PPCLKEN2_CRCLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_CRCLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_CRCLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 ADCLKE [10..10]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_ADCLKE                                                     */
+  SCUCG_PPCLKEN2_ADCLKE_Disable        = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_ADCLKE_Enable         = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_ADCLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 I2C2CLKE [8..8]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_I2C2CLKE                                                   */
+  SCUCG_PPCLKEN2_I2C2CLKE_Disable      = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_I2C2CLKE_Enable       = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_I2C2CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 I2C1CLKE [7..7]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_I2C1CLKE                                                   */
+  SCUCG_PPCLKEN2_I2C1CLKE_Disable      = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_I2C1CLKE_Enable       = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_I2C1CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 I2C0CLKE [6..6]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_I2C0CLKE                                                   */
+  SCUCG_PPCLKEN2_I2C0CLKE_Disable      = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_I2C0CLKE_Enable       = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_I2C0CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 UST13CLKE [5..5]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_UST13CLKE                                                  */
+  SCUCG_PPCLKEN2_UST13CLKE_Disable     = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_UST13CLKE_Enable      = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_UST13CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 UST12CLKE [4..4]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_UST12CLKE                                                  */
+  SCUCG_PPCLKEN2_UST12CLKE_Disable     = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_UST12CLKE_Enable      = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_UST12CLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN2 UT1CLKE [3..3]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_UT1CLKE                                                    */
+  SCUCG_PPCLKEN2_UT1CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_UT1CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_UT1CLKE_Enum;
+
+/* =============================================  SCUCG PPCLKEN2 UT0CLKE [2..2]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_UT0CLKE                                                    */
+  SCUCG_PPCLKEN2_UT0CLKE_Disable       = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_UT0CLKE_Enable        = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_UT0CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 UST11CLKE [1..1]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_UST11CLKE                                                  */
+  SCUCG_PPCLKEN2_UST11CLKE_Disable     = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_UST11CLKE_Enable      = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_UST11CLKE_Enum;
+
+/* ============================================  SCUCG PPCLKEN2 UST10CLKE [0..0]  ============================================ */
+typedef enum {                                  /*!< SCUCG_PPCLKEN2_UST10CLKE                                                  */
+  SCUCG_PPCLKEN2_UST10CLKE_Disable     = 0,     /*!< Disable : Disable clock.                                                  */
+  SCUCG_PPCLKEN2_UST10CLKE_Enable      = 1,     /*!< Enable : Enable clock.                                                    */
+} SCUCG_PPCLKEN2_UST10CLKE_Enum;
+
+/* ========================================================  PPCLKSR  ======================================================== */
+/* =============================================  SCUCG PPCLKSR T20CLK [20..20]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKSR_T20CLK                                                      */
+  SCUCG_PPCLKSR_T20CLK_XSOSC           = 0,     /*!< XSOSC : XSOSC clock                                                       */
+  SCUCG_PPCLKSR_T20CLK_PCLK            = 1,     /*!< PCLK : PCLK clock                                                         */
+} SCUCG_PPCLKSR_T20CLK_Enum;
+
+/* =============================================  SCUCG PPCLKSR T30CLK [17..17]  ============================================= */
+typedef enum {                                  /*!< SCUCG_PPCLKSR_T30CLK                                                      */
+  SCUCG_PPCLKSR_T30CLK_MCLK            = 0,     /*!< MCLK : MCLK clock                                                         */
+  SCUCG_PPCLKSR_T30CLK_PCLK            = 1,     /*!< PCLK : PCLK clock                                                         */
+} SCUCG_PPCLKSR_T30CLK_Enum;
+
+/* ==============================================  SCUCG PPCLKSR LCDCLK [6..7]  ============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKSR_LCDCLK                                                      */
+  SCUCG_PPCLKSR_LCDCLK_DividedMCLK     = 0,     /*!< DividedMCLK : A clock of the MCLK which is divided by divider
+                                                     2                                                                         */
+  SCUCG_PPCLKSR_LCDCLK_XSOSC           = 1,     /*!< XSOSC : XSOSC clock                                                       */
+  SCUCG_PPCLKSR_LCDCLK_WDTRC           = 2,     /*!< WDTRC : WDTRC clock                                                       */
+} SCUCG_PPCLKSR_LCDCLK_Enum;
+
+/* ==============================================  SCUCG PPCLKSR WTCLK [3..4]  =============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKSR_WTCLK                                                       */
+  SCUCG_PPCLKSR_WTCLK_DividedMCLK      = 0,     /*!< DividedMCLK : A clock of the MCLK which is divided by divider
+                                                     2                                                                         */
+  SCUCG_PPCLKSR_WTCLK_XSOSC            = 1,     /*!< XSOSC : XSOSC clock                                                       */
+  SCUCG_PPCLKSR_WTCLK_WDTRC            = 2,     /*!< WDTRC : WDTRC clock                                                       */
+} SCUCG_PPCLKSR_WTCLK_Enum;
+
+/* ==============================================  SCUCG PPCLKSR WDTCLK [0..0]  ============================================== */
+typedef enum {                                  /*!< SCUCG_PPCLKSR_WDTCLK                                                      */
+  SCUCG_PPCLKSR_WDTCLK_WDTRC           = 0,     /*!< WDTRC : WDTRC clock                                                       */
+  SCUCG_PPCLKSR_WDTCLK_PCLK            = 1,     /*!< PCLK : PCLK clock                                                         */
+} SCUCG_PPCLKSR_WDTCLK_Enum;
+
+/* ========================================================  PPRST1  ========================================================= */
+/* ========================================================  PPRST2  ========================================================= */
+/* ========================================================  XTFLSR  ========================================================= */
+/* =============================================  SCUCG XTFLSR WTIDKY [16..31]  ============================================== */
+typedef enum {                                  /*!< SCUCG_XTFLSR_WTIDKY                                                       */
+  SCUCG_XTFLSR_WTIDKY_Value            = 39735, /*!< Value : Key Value (0x9b37)                                                */
+} SCUCG_XTFLSR_WTIDKY_Enum;
+
+/* ===============================================  SCUCG XTFLSR XRNS [0..2]  ================================================ */
+typedef enum {                                  /*!< SCUCG_XTFLSR_XRNS                                                         */
+  SCUCG_XTFLSR_XRNS_LE4p5MHz           = 0,     /*!< LE4p5MHz : x-tal LE 4.5MHz                                                */
+  SCUCG_XTFLSR_XRNS_LE6p5MHz           = 1,     /*!< LE6p5MHz : 4.5MHz GT x-tal LE 6.5MHz                                      */
+  SCUCG_XTFLSR_XRNS_LE8p5MHz           = 2,     /*!< LE8p5MHz : 6.5MHz GT x-tal LE 8.5MHz                                      */
+  SCUCG_XTFLSR_XRNS_LE10p5MHz          = 3,     /*!< LE10p5MHz : 8.5MHz GT x-tal LE 10.5MHz                                    */
+  SCUCG_XTFLSR_XRNS_LE12p5MHz          = 4,     /*!< LE12p5MHz : 10.5MHz GT x-tal LE 12.5MHz                                   */
+  SCUCG_XTFLSR_XRNS_LE16p5MHz          = 5,     /*!< LE16p5MHz : 12.5MHz GT x-tal LE 16.5MHz                                   */
+} SCUCG_XTFLSR_XRNS_Enum;
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           SCULV                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  LVICR  ========================================================= */
+/* ===============================================  SCULV LVICR LVIEN [7..7]  ================================================ */
+typedef enum {                                  /*!< SCULV_LVICR_LVIEN                                                         */
+  SCULV_LVICR_LVIEN_Disable            = 0,     /*!< Disable : Disable low voltage indicator.                                  */
+  SCULV_LVICR_LVIEN_Enable             = 1,     /*!< Enable : Enable low voltage indicator.                                    */
+} SCULV_LVICR_LVIEN_Enum;
+
+/* ==============================================  SCULV LVICR LVINTEN [5..5]  =============================================== */
+typedef enum {                                  /*!< SCULV_LVICR_LVINTEN                                                       */
+  SCULV_LVICR_LVINTEN_Disable          = 0,     /*!< Disable : Disable low voltage indicator interrupt.                        */
+  SCULV_LVICR_LVINTEN_Enable           = 1,     /*!< Enable : Enable low voltage indicator interrupt.                          */
+} SCULV_LVICR_LVINTEN_Enum;
+
+/* ==============================================  SCULV LVICR LVIFLAG [4..4]  =============================================== */
+typedef enum {                                  /*!< SCULV_LVICR_LVIFLAG                                                       */
+  SCULV_LVICR_LVIFLAG_NoRequest        = 0,     /*!< NoRequest : No request occurred.                                          */
+  SCULV_LVICR_LVIFLAG_Request          = 1,     /*!< Request : Request occurred.                                               */
+} SCULV_LVICR_LVIFLAG_Enum;
+
+/* ===============================================  SCULV LVICR LVIVS [0..3]  ================================================ */
+typedef enum {                                  /*!< SCULV_LVICR_LVIVS                                                         */
+  SCULV_LVICR_LVIVS_DNW3               = 3,     /*!< DNW3 : Do not write.                                                      */
+  SCULV_LVICR_LVIVS_2p00V              = 4,     /*!< 2p00V : 2.00V                                                             */
+  SCULV_LVICR_LVIVS_2p13V              = 5,     /*!< 2p13V : 2.13V                                                             */
+  SCULV_LVICR_LVIVS_2p28V              = 6,     /*!< 2p28V : 2.28V                                                             */
+  SCULV_LVICR_LVIVS_2p46V              = 7,     /*!< 2p46V : 2.46V                                                             */
+  SCULV_LVICR_LVIVS_2p67V              = 8,     /*!< 2p67V : 2.67V                                                             */
+  SCULV_LVICR_LVIVS_3p04V              = 9,     /*!< 3p04V : 3.04V                                                             */
+  SCULV_LVICR_LVIVS_3p20V              = 10,    /*!< 3p20V : 3.20V                                                             */
+  SCULV_LVICR_LVIVS_3p55V              = 11,    /*!< 3p55V : 3.55V                                                             */
+  SCULV_LVICR_LVIVS_3p75V              = 12,    /*!< 3p75V : 3.75V                                                             */
+  SCULV_LVICR_LVIVS_3p99V              = 13,    /*!< 3p99V : 3.99V                                                             */
+  SCULV_LVICR_LVIVS_4p25V              = 14,    /*!< 4p25V : 4.25V                                                             */
+  SCULV_LVICR_LVIVS_4p55V              = 15,    /*!< 4p55V : 4.55V                                                             */
+} SCULV_LVICR_LVIVS_Enum;
+
+/* =========================================================  LVRCR  ========================================================= */
+/* ===============================================  SCULV LVRCR LVREN [0..7]  ================================================ */
+typedef enum {                                  /*!< SCULV_LVRCR_LVREN                                                         */
+  SCULV_LVRCR_LVREN_Disable            = 85,    /*!< Disable : Disable low voltage reset. (0x55)                               */
+  SCULV_LVRCR_LVREN_Enable             = 0,     /*!< Enable : Enable low voltage reset.                                        */
+} SCULV_LVRCR_LVREN_Enum;
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            Pn                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+/* ================================================  Pn MOD MODE15 [30..31]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE15                                                             */
+  Pn_MOD_MODE15_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE15_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE15_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE15_Enum;
+
+/* ================================================  Pn MOD MODE14 [28..29]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE14                                                             */
+  Pn_MOD_MODE14_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE14_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE14_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE14_Enum;
+
+/* ================================================  Pn MOD MODE13 [26..27]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE13                                                             */
+  Pn_MOD_MODE13_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE13_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE13_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE13_Enum;
+
+/* ================================================  Pn MOD MODE12 [24..25]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE12                                                             */
+  Pn_MOD_MODE12_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE12_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE12_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE12_Enum;
+
+/* ================================================  Pn MOD MODE11 [22..23]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE11                                                             */
+  Pn_MOD_MODE11_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE11_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE11_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE11_Enum;
+
+/* ================================================  Pn MOD MODE10 [20..21]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE10                                                             */
+  Pn_MOD_MODE10_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE10_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE10_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE10_Enum;
+
+/* =================================================  Pn MOD MODE9 [18..19]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE9                                                              */
+  Pn_MOD_MODE9_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE9_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE9_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE9_Enum;
+
+/* =================================================  Pn MOD MODE8 [16..17]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE8                                                              */
+  Pn_MOD_MODE8_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE8_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE8_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE8_Enum;
+
+/* =================================================  Pn MOD MODE7 [14..15]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE7                                                              */
+  Pn_MOD_MODE7_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE7_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE7_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE7_Enum;
+
+/* =================================================  Pn MOD MODE6 [12..13]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE6                                                              */
+  Pn_MOD_MODE6_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE6_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE6_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE6_Enum;
+
+/* =================================================  Pn MOD MODE5 [10..11]  ================================================= */
+typedef enum {                                  /*!< Pn_MOD_MODE5                                                              */
+  Pn_MOD_MODE5_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE5_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE5_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE5_Enum;
+
+/* ==================================================  Pn MOD MODE4 [8..9]  ================================================== */
+typedef enum {                                  /*!< Pn_MOD_MODE4                                                              */
+  Pn_MOD_MODE4_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE4_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE4_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE4_Enum;
+
+/* ==================================================  Pn MOD MODE3 [6..7]  ================================================== */
+typedef enum {                                  /*!< Pn_MOD_MODE3                                                              */
+  Pn_MOD_MODE3_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE3_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE3_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE3_Enum;
+
+/* ==================================================  Pn MOD MODE2 [4..5]  ================================================== */
+typedef enum {                                  /*!< Pn_MOD_MODE2                                                              */
+  Pn_MOD_MODE2_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE2_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE2_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE2_Enum;
+
+/* ==================================================  Pn MOD MODE1 [2..3]  ================================================== */
+typedef enum {                                  /*!< Pn_MOD_MODE1                                                              */
+  Pn_MOD_MODE1_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE1_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE1_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE1_Enum;
+
+/* ==================================================  Pn MOD MODE0 [0..1]  ================================================== */
+typedef enum {                                  /*!< Pn_MOD_MODE0                                                              */
+  Pn_MOD_MODE0_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  Pn_MOD_MODE0_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  Pn_MOD_MODE0_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} Pn_MOD_MODE0_Enum;
+
+/* ==========================================================  TYP  ========================================================== */
+/* =================================================  Pn TYP TYP15 [15..15]  ================================================= */
+typedef enum {                                  /*!< Pn_TYP_TYP15                                                              */
+  Pn_TYP_TYP15_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP15_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP15_Enum;
+
+/* =================================================  Pn TYP TYP14 [14..14]  ================================================= */
+typedef enum {                                  /*!< Pn_TYP_TYP14                                                              */
+  Pn_TYP_TYP14_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP14_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP14_Enum;
+
+/* =================================================  Pn TYP TYP13 [13..13]  ================================================= */
+typedef enum {                                  /*!< Pn_TYP_TYP13                                                              */
+  Pn_TYP_TYP13_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP13_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP13_Enum;
+
+/* =================================================  Pn TYP TYP12 [12..12]  ================================================= */
+typedef enum {                                  /*!< Pn_TYP_TYP12                                                              */
+  Pn_TYP_TYP12_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP12_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP12_Enum;
+
+/* =================================================  Pn TYP TYP11 [11..11]  ================================================= */
+typedef enum {                                  /*!< Pn_TYP_TYP11                                                              */
+  Pn_TYP_TYP11_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP11_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP11_Enum;
+
+/* =================================================  Pn TYP TYP10 [10..10]  ================================================= */
+typedef enum {                                  /*!< Pn_TYP_TYP10                                                              */
+  Pn_TYP_TYP10_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP10_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP10_Enum;
+
+/* ==================================================  Pn TYP TYP9 [9..9]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP9                                                               */
+  Pn_TYP_TYP9_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP9_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP9_Enum;
+
+/* ==================================================  Pn TYP TYP8 [8..8]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP8                                                               */
+  Pn_TYP_TYP8_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP8_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP8_Enum;
+
+/* ==================================================  Pn TYP TYP7 [7..7]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP7                                                               */
+  Pn_TYP_TYP7_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP7_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP7_Enum;
+
+/* ==================================================  Pn TYP TYP6 [6..6]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP6                                                               */
+  Pn_TYP_TYP6_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP6_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP6_Enum;
+
+/* ==================================================  Pn TYP TYP5 [5..5]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP5                                                               */
+  Pn_TYP_TYP5_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP5_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP5_Enum;
+
+/* ==================================================  Pn TYP TYP4 [4..4]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP4                                                               */
+  Pn_TYP_TYP4_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP4_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP4_Enum;
+
+/* ==================================================  Pn TYP TYP3 [3..3]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP3                                                               */
+  Pn_TYP_TYP3_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP3_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP3_Enum;
+
+/* ==================================================  Pn TYP TYP2 [2..2]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP2                                                               */
+  Pn_TYP_TYP2_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP2_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP2_Enum;
+
+/* ==================================================  Pn TYP TYP1 [1..1]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP1                                                               */
+  Pn_TYP_TYP1_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP1_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP1_Enum;
+
+/* ==================================================  Pn TYP TYP0 [0..0]  =================================================== */
+typedef enum {                                  /*!< Pn_TYP_TYP0                                                               */
+  Pn_TYP_TYP0_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  Pn_TYP_TYP0_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} Pn_TYP_TYP0_Enum;
+
+/* =========================================================  AFSR1  ========================================================= */
+/* ================================================  Pn AFSR1 AFSR7 [28..31]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR1_AFSR7                                                            */
+  Pn_AFSR1_AFSR7_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR1_AFSR7_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR1_AFSR7_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR1_AFSR7_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR1_AFSR7_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR1_AFSR7_Enum;
+
+/* ================================================  Pn AFSR1 AFSR6 [24..27]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR1_AFSR6                                                            */
+  Pn_AFSR1_AFSR6_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR1_AFSR6_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR1_AFSR6_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR1_AFSR6_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR1_AFSR6_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR1_AFSR6_Enum;
+
+/* ================================================  Pn AFSR1 AFSR5 [20..23]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR1_AFSR5                                                            */
+  Pn_AFSR1_AFSR5_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR1_AFSR5_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR1_AFSR5_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR1_AFSR5_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR1_AFSR5_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR1_AFSR5_Enum;
+
+/* ================================================  Pn AFSR1 AFSR4 [16..19]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR1_AFSR4                                                            */
+  Pn_AFSR1_AFSR4_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR1_AFSR4_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR1_AFSR4_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR1_AFSR4_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR1_AFSR4_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR1_AFSR4_Enum;
+
+/* ================================================  Pn AFSR1 AFSR3 [12..15]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR1_AFSR3                                                            */
+  Pn_AFSR1_AFSR3_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR1_AFSR3_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR1_AFSR3_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR1_AFSR3_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR1_AFSR3_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR1_AFSR3_Enum;
+
+/* ================================================  Pn AFSR1 AFSR2 [8..11]  ================================================= */
+typedef enum {                                  /*!< Pn_AFSR1_AFSR2                                                            */
+  Pn_AFSR1_AFSR2_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR1_AFSR2_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR1_AFSR2_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR1_AFSR2_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR1_AFSR2_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR1_AFSR2_Enum;
+
+/* =================================================  Pn AFSR1 AFSR1 [4..7]  ================================================= */
+typedef enum {                                  /*!< Pn_AFSR1_AFSR1                                                            */
+  Pn_AFSR1_AFSR1_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR1_AFSR1_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR1_AFSR1_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR1_AFSR1_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR1_AFSR1_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR1_AFSR1_Enum;
+
+/* =================================================  Pn AFSR1 AFSR0 [0..3]  ================================================= */
+typedef enum {                                  /*!< Pn_AFSR1_AFSR0                                                            */
+  Pn_AFSR1_AFSR0_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR1_AFSR0_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR1_AFSR0_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR1_AFSR0_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR1_AFSR0_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR1_AFSR0_Enum;
+
+/* =========================================================  AFSR2  ========================================================= */
+/* ===============================================  Pn AFSR2 AFSR15 [28..31]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR2_AFSR15                                                           */
+  Pn_AFSR2_AFSR15_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR2_AFSR15_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR2_AFSR15_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR2_AFSR15_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR2_AFSR15_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR2_AFSR15_Enum;
+
+/* ===============================================  Pn AFSR2 AFSR14 [24..27]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR2_AFSR14                                                           */
+  Pn_AFSR2_AFSR14_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR2_AFSR14_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR2_AFSR14_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR2_AFSR14_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR2_AFSR14_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR2_AFSR14_Enum;
+
+/* ===============================================  Pn AFSR2 AFSR13 [20..23]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR2_AFSR13                                                           */
+  Pn_AFSR2_AFSR13_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR2_AFSR13_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR2_AFSR13_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR2_AFSR13_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR2_AFSR13_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR2_AFSR13_Enum;
+
+/* ===============================================  Pn AFSR2 AFSR12 [16..19]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR2_AFSR12                                                           */
+  Pn_AFSR2_AFSR12_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR2_AFSR12_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR2_AFSR12_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR2_AFSR12_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR2_AFSR12_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR2_AFSR12_Enum;
+
+/* ===============================================  Pn AFSR2 AFSR11 [12..15]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR2_AFSR11                                                           */
+  Pn_AFSR2_AFSR11_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR2_AFSR11_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR2_AFSR11_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR2_AFSR11_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR2_AFSR11_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR2_AFSR11_Enum;
+
+/* ================================================  Pn AFSR2 AFSR10 [8..11]  ================================================ */
+typedef enum {                                  /*!< Pn_AFSR2_AFSR10                                                           */
+  Pn_AFSR2_AFSR10_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR2_AFSR10_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR2_AFSR10_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR2_AFSR10_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR2_AFSR10_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR2_AFSR10_Enum;
+
+/* =================================================  Pn AFSR2 AFSR9 [4..7]  ================================================= */
+typedef enum {                                  /*!< Pn_AFSR2_AFSR9                                                            */
+  Pn_AFSR2_AFSR9_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR2_AFSR9_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR2_AFSR9_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR2_AFSR9_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR2_AFSR9_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR2_AFSR9_Enum;
+
+/* =================================================  Pn AFSR2 AFSR8 [0..3]  ================================================= */
+typedef enum {                                  /*!< Pn_AFSR2_AFSR8                                                            */
+  Pn_AFSR2_AFSR8_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  Pn_AFSR2_AFSR8_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  Pn_AFSR2_AFSR8_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  Pn_AFSR2_AFSR8_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  Pn_AFSR2_AFSR8_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} Pn_AFSR2_AFSR8_Enum;
+
+/* =========================================================  PUPD  ========================================================== */
+/* ================================================  Pn PUPD PUPD15 [30..31]  ================================================ */
+typedef enum {                                  /*!< Pn_PUPD_PUPD15                                                            */
+  Pn_PUPD_PUPD15_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD15_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD15_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD15_Enum;
+
+/* ================================================  Pn PUPD PUPD14 [28..29]  ================================================ */
+typedef enum {                                  /*!< Pn_PUPD_PUPD14                                                            */
+  Pn_PUPD_PUPD14_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD14_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD14_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD14_Enum;
+
+/* ================================================  Pn PUPD PUPD13 [26..27]  ================================================ */
+typedef enum {                                  /*!< Pn_PUPD_PUPD13                                                            */
+  Pn_PUPD_PUPD13_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD13_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD13_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD13_Enum;
+
+/* ================================================  Pn PUPD PUPD12 [24..25]  ================================================ */
+typedef enum {                                  /*!< Pn_PUPD_PUPD12                                                            */
+  Pn_PUPD_PUPD12_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD12_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD12_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD12_Enum;
+
+/* ================================================  Pn PUPD PUPD11 [22..23]  ================================================ */
+typedef enum {                                  /*!< Pn_PUPD_PUPD11                                                            */
+  Pn_PUPD_PUPD11_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD11_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD11_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD11_Enum;
+
+/* ================================================  Pn PUPD PUPD10 [20..21]  ================================================ */
+typedef enum {                                  /*!< Pn_PUPD_PUPD10                                                            */
+  Pn_PUPD_PUPD10_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD10_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD10_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD10_Enum;
+
+/* ================================================  Pn PUPD PUPD9 [18..19]  ================================================= */
+typedef enum {                                  /*!< Pn_PUPD_PUPD9                                                             */
+  Pn_PUPD_PUPD9_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD9_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD9_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD9_Enum;
+
+/* ================================================  Pn PUPD PUPD8 [16..17]  ================================================= */
+typedef enum {                                  /*!< Pn_PUPD_PUPD8                                                             */
+  Pn_PUPD_PUPD8_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD8_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD8_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD8_Enum;
+
+/* ================================================  Pn PUPD PUPD7 [14..15]  ================================================= */
+typedef enum {                                  /*!< Pn_PUPD_PUPD7                                                             */
+  Pn_PUPD_PUPD7_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD7_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD7_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD7_Enum;
+
+/* ================================================  Pn PUPD PUPD6 [12..13]  ================================================= */
+typedef enum {                                  /*!< Pn_PUPD_PUPD6                                                             */
+  Pn_PUPD_PUPD6_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD6_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD6_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD6_Enum;
+
+/* ================================================  Pn PUPD PUPD5 [10..11]  ================================================= */
+typedef enum {                                  /*!< Pn_PUPD_PUPD5                                                             */
+  Pn_PUPD_PUPD5_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD5_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD5_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD5_Enum;
+
+/* =================================================  Pn PUPD PUPD4 [8..9]  ================================================== */
+typedef enum {                                  /*!< Pn_PUPD_PUPD4                                                             */
+  Pn_PUPD_PUPD4_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD4_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD4_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD4_Enum;
+
+/* =================================================  Pn PUPD PUPD3 [6..7]  ================================================== */
+typedef enum {                                  /*!< Pn_PUPD_PUPD3                                                             */
+  Pn_PUPD_PUPD3_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD3_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD3_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD3_Enum;
+
+/* =================================================  Pn PUPD PUPD2 [4..5]  ================================================== */
+typedef enum {                                  /*!< Pn_PUPD_PUPD2                                                             */
+  Pn_PUPD_PUPD2_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD2_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD2_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD2_Enum;
+
+/* =================================================  Pn PUPD PUPD1 [2..3]  ================================================== */
+typedef enum {                                  /*!< Pn_PUPD_PUPD1                                                             */
+  Pn_PUPD_PUPD1_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD1_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD1_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD1_Enum;
+
+/* =================================================  Pn PUPD PUPD0 [0..1]  ================================================== */
+typedef enum {                                  /*!< Pn_PUPD_PUPD0                                                             */
+  Pn_PUPD_PUPD0_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  Pn_PUPD_PUPD0_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  Pn_PUPD_PUPD0_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} Pn_PUPD_PUPD0_Enum;
+
+/* =========================================================  INDR  ========================================================== */
+/* =========================================================  OUTDR  ========================================================= */
+/* ==========================================================  BSR  ========================================================== */
+/* =================================================  Pn BSR BSR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< Pn_BSR_BSR15                                                              */
+  Pn_BSR_BSR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR15_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR15_Enum;
+
+/* =================================================  Pn BSR BSR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< Pn_BSR_BSR14                                                              */
+  Pn_BSR_BSR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR14_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR14_Enum;
+
+/* =================================================  Pn BSR BSR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< Pn_BSR_BSR13                                                              */
+  Pn_BSR_BSR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR13_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR13_Enum;
+
+/* =================================================  Pn BSR BSR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< Pn_BSR_BSR12                                                              */
+  Pn_BSR_BSR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR12_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR12_Enum;
+
+/* =================================================  Pn BSR BSR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< Pn_BSR_BSR11                                                              */
+  Pn_BSR_BSR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR11_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR11_Enum;
+
+/* =================================================  Pn BSR BSR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< Pn_BSR_BSR10                                                              */
+  Pn_BSR_BSR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR10_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR10_Enum;
+
+/* ==================================================  Pn BSR BSR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR9                                                               */
+  Pn_BSR_BSR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR9_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR9_Enum;
+
+/* ==================================================  Pn BSR BSR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR8                                                               */
+  Pn_BSR_BSR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR8_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR8_Enum;
+
+/* ==================================================  Pn BSR BSR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR7                                                               */
+  Pn_BSR_BSR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR7_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR7_Enum;
+
+/* ==================================================  Pn BSR BSR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR6                                                               */
+  Pn_BSR_BSR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR6_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR6_Enum;
+
+/* ==================================================  Pn BSR BSR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR5                                                               */
+  Pn_BSR_BSR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR5_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR5_Enum;
+
+/* ==================================================  Pn BSR BSR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR4                                                               */
+  Pn_BSR_BSR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR4_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR4_Enum;
+
+/* ==================================================  Pn BSR BSR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR3                                                               */
+  Pn_BSR_BSR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR3_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR3_Enum;
+
+/* ==================================================  Pn BSR BSR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR2                                                               */
+  Pn_BSR_BSR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR2_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR2_Enum;
+
+/* ==================================================  Pn BSR BSR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR1                                                               */
+  Pn_BSR_BSR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR1_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR1_Enum;
+
+/* ==================================================  Pn BSR BSR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< Pn_BSR_BSR0                                                               */
+  Pn_BSR_BSR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BSR_BSR0_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BSR_BSR0_Enum;
+
+/* ==========================================================  BCR  ========================================================== */
+/* =================================================  Pn BCR BCR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< Pn_BCR_BCR15                                                              */
+  Pn_BCR_BCR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR15_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR15_Enum;
+
+/* =================================================  Pn BCR BCR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< Pn_BCR_BCR14                                                              */
+  Pn_BCR_BCR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR14_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR14_Enum;
+
+/* =================================================  Pn BCR BCR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< Pn_BCR_BCR13                                                              */
+  Pn_BCR_BCR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR13_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR13_Enum;
+
+/* =================================================  Pn BCR BCR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< Pn_BCR_BCR12                                                              */
+  Pn_BCR_BCR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR12_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR12_Enum;
+
+/* =================================================  Pn BCR BCR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< Pn_BCR_BCR11                                                              */
+  Pn_BCR_BCR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR11_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR11_Enum;
+
+/* =================================================  Pn BCR BCR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< Pn_BCR_BCR10                                                              */
+  Pn_BCR_BCR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR10_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR10_Enum;
+
+/* ==================================================  Pn BCR BCR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR9                                                               */
+  Pn_BCR_BCR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR9_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR9_Enum;
+
+/* ==================================================  Pn BCR BCR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR8                                                               */
+  Pn_BCR_BCR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR8_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR8_Enum;
+
+/* ==================================================  Pn BCR BCR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR7                                                               */
+  Pn_BCR_BCR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR7_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR7_Enum;
+
+/* ==================================================  Pn BCR BCR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR6                                                               */
+  Pn_BCR_BCR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR6_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR6_Enum;
+
+/* ==================================================  Pn BCR BCR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR5                                                               */
+  Pn_BCR_BCR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR5_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR5_Enum;
+
+/* ==================================================  Pn BCR BCR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR4                                                               */
+  Pn_BCR_BCR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR4_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR4_Enum;
+
+/* ==================================================  Pn BCR BCR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR3                                                               */
+  Pn_BCR_BCR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR3_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR3_Enum;
+
+/* ==================================================  Pn BCR BCR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR2                                                               */
+  Pn_BCR_BCR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR2_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR2_Enum;
+
+/* ==================================================  Pn BCR BCR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR1                                                               */
+  Pn_BCR_BCR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR1_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR1_Enum;
+
+/* ==================================================  Pn BCR BCR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< Pn_BCR_BCR0                                                               */
+  Pn_BCR_BCR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  Pn_BCR_BCR0_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} Pn_BCR_BCR0_Enum;
+
+/* ========================================================  OUTDMSK  ======================================================== */
+/* =============================================  Pn OUTDMSK OUTDMSK15 [15..15]  ============================================= */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK15                                                      */
+  Pn_OUTDMSK_OUTDMSK15_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK15_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK15_Enum;
+
+/* =============================================  Pn OUTDMSK OUTDMSK14 [14..14]  ============================================= */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK14                                                      */
+  Pn_OUTDMSK_OUTDMSK14_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK14_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK14_Enum;
+
+/* =============================================  Pn OUTDMSK OUTDMSK13 [13..13]  ============================================= */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK13                                                      */
+  Pn_OUTDMSK_OUTDMSK13_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK13_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK13_Enum;
+
+/* =============================================  Pn OUTDMSK OUTDMSK12 [12..12]  ============================================= */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK12                                                      */
+  Pn_OUTDMSK_OUTDMSK12_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK12_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK12_Enum;
+
+/* =============================================  Pn OUTDMSK OUTDMSK11 [11..11]  ============================================= */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK11                                                      */
+  Pn_OUTDMSK_OUTDMSK11_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK11_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK11_Enum;
+
+/* =============================================  Pn OUTDMSK OUTDMSK10 [10..10]  ============================================= */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK10                                                      */
+  Pn_OUTDMSK_OUTDMSK10_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK10_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK10_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK9 [9..9]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK9                                                       */
+  Pn_OUTDMSK_OUTDMSK9_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK9_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK9_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK8 [8..8]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK8                                                       */
+  Pn_OUTDMSK_OUTDMSK8_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK8_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK8_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK7 [7..7]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK7                                                       */
+  Pn_OUTDMSK_OUTDMSK7_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK7_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK7_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK6 [6..6]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK6                                                       */
+  Pn_OUTDMSK_OUTDMSK6_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK6_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK6_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK5 [5..5]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK5                                                       */
+  Pn_OUTDMSK_OUTDMSK5_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK5_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK5_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK4 [4..4]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK4                                                       */
+  Pn_OUTDMSK_OUTDMSK4_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK4_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK4_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK3 [3..3]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK3                                                       */
+  Pn_OUTDMSK_OUTDMSK3_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK3_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK3_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK2 [2..2]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK2                                                       */
+  Pn_OUTDMSK_OUTDMSK2_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK2_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK2_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK1 [1..1]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK1                                                       */
+  Pn_OUTDMSK_OUTDMSK1_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK1_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK1_Enum;
+
+/* ==============================================  Pn OUTDMSK OUTDMSK0 [0..0]  =============================================== */
+typedef enum {                                  /*!< Pn_OUTDMSK_OUTDMSK0                                                       */
+  Pn_OUTDMSK_OUTDMSK0_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  Pn_OUTDMSK_OUTDMSK0_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} Pn_OUTDMSK_OUTDMSK0_Enum;
+
+/* =========================================================  DBCR  ========================================================== */
+/* ================================================  Pn DBCR DBCLK [16..18]  ================================================= */
+typedef enum {                                  /*!< Pn_DBCR_DBCLK                                                             */
+  Pn_DBCR_DBCLK_HCLK1                  = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  Pn_DBCR_DBCLK_HCLK4                  = 1,     /*!< HCLK4 : HCLK/4                                                            */
+  Pn_DBCR_DBCLK_HCLK16                 = 2,     /*!< HCLK16 : HCLK/16                                                          */
+  Pn_DBCR_DBCLK_HCLK64                 = 3,     /*!< HCLK64 : HCLK/64                                                          */
+  Pn_DBCR_DBCLK_HCLK256                = 4,     /*!< HCLK256 : HCLK/256                                                        */
+  Pn_DBCR_DBCLK_HCLK1024               = 5,     /*!< HCLK1024 : HCLK/1024                                                      */
+} Pn_DBCR_DBCLK_Enum;
+
+/* ================================================  Pn DBCR DBEN11 [11..11]  ================================================ */
+typedef enum {                                  /*!< Pn_DBCR_DBEN11                                                            */
+  Pn_DBCR_DBEN11_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN11_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN11_Enum;
+
+/* ================================================  Pn DBCR DBEN10 [10..10]  ================================================ */
+typedef enum {                                  /*!< Pn_DBCR_DBEN10                                                            */
+  Pn_DBCR_DBEN10_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN10_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN10_Enum;
+
+/* =================================================  Pn DBCR DBEN9 [9..9]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN9                                                             */
+  Pn_DBCR_DBEN9_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN9_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN9_Enum;
+
+/* =================================================  Pn DBCR DBEN8 [8..8]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN8                                                             */
+  Pn_DBCR_DBEN8_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN8_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN8_Enum;
+
+/* =================================================  Pn DBCR DBEN7 [7..7]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN7                                                             */
+  Pn_DBCR_DBEN7_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN7_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN7_Enum;
+
+/* =================================================  Pn DBCR DBEN6 [6..6]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN6                                                             */
+  Pn_DBCR_DBEN6_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN6_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN6_Enum;
+
+/* =================================================  Pn DBCR DBEN5 [5..5]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN5                                                             */
+  Pn_DBCR_DBEN5_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN5_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN5_Enum;
+
+/* =================================================  Pn DBCR DBEN4 [4..4]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN4                                                             */
+  Pn_DBCR_DBEN4_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN4_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN4_Enum;
+
+/* =================================================  Pn DBCR DBEN3 [3..3]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN3                                                             */
+  Pn_DBCR_DBEN3_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN3_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN3_Enum;
+
+/* =================================================  Pn DBCR DBEN2 [2..2]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN2                                                             */
+  Pn_DBCR_DBEN2_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN2_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN2_Enum;
+
+/* =================================================  Pn DBCR DBEN1 [1..1]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN1                                                             */
+  Pn_DBCR_DBEN1_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN1_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN1_Enum;
+
+/* =================================================  Pn DBCR DBEN0 [0..0]  ================================================== */
+typedef enum {                                  /*!< Pn_DBCR_DBEN0                                                             */
+  Pn_DBCR_DBEN0_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  Pn_DBCR_DBEN0_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} Pn_DBCR_DBEN0_Enum;
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            PA                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+/* ================================================  PA MOD MODE15 [30..31]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE15                                                             */
+  PA_MOD_MODE15_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE15_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE15_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE15_Enum;
+
+/* ================================================  PA MOD MODE14 [28..29]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE14                                                             */
+  PA_MOD_MODE14_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE14_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE14_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE14_Enum;
+
+/* ================================================  PA MOD MODE13 [26..27]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE13                                                             */
+  PA_MOD_MODE13_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE13_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE13_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE13_Enum;
+
+/* ================================================  PA MOD MODE12 [24..25]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE12                                                             */
+  PA_MOD_MODE12_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE12_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE12_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE12_Enum;
+
+/* ================================================  PA MOD MODE11 [22..23]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE11                                                             */
+  PA_MOD_MODE11_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE11_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE11_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE11_Enum;
+
+/* ================================================  PA MOD MODE10 [20..21]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE10                                                             */
+  PA_MOD_MODE10_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE10_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE10_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE10_Enum;
+
+/* =================================================  PA MOD MODE9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE9                                                              */
+  PA_MOD_MODE9_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE9_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE9_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE9_Enum;
+
+/* =================================================  PA MOD MODE8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE8                                                              */
+  PA_MOD_MODE8_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE8_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE8_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE8_Enum;
+
+/* =================================================  PA MOD MODE7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE7                                                              */
+  PA_MOD_MODE7_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE7_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE7_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE7_Enum;
+
+/* =================================================  PA MOD MODE6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE6                                                              */
+  PA_MOD_MODE6_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE6_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE6_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE6_Enum;
+
+/* =================================================  PA MOD MODE5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PA_MOD_MODE5                                                              */
+  PA_MOD_MODE5_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE5_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE5_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE5_Enum;
+
+/* ==================================================  PA MOD MODE4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PA_MOD_MODE4                                                              */
+  PA_MOD_MODE4_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE4_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE4_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE4_Enum;
+
+/* ==================================================  PA MOD MODE3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PA_MOD_MODE3                                                              */
+  PA_MOD_MODE3_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE3_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE3_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE3_Enum;
+
+/* ==================================================  PA MOD MODE2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PA_MOD_MODE2                                                              */
+  PA_MOD_MODE2_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE2_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE2_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE2_Enum;
+
+/* ==================================================  PA MOD MODE1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PA_MOD_MODE1                                                              */
+  PA_MOD_MODE1_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE1_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE1_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE1_Enum;
+
+/* ==================================================  PA MOD MODE0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PA_MOD_MODE0                                                              */
+  PA_MOD_MODE0_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PA_MOD_MODE0_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PA_MOD_MODE0_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PA_MOD_MODE0_Enum;
+
+/* ==========================================================  TYP  ========================================================== */
+/* =================================================  PA TYP TYP15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PA_TYP_TYP15                                                              */
+  PA_TYP_TYP15_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP15_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP15_Enum;
+
+/* =================================================  PA TYP TYP14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PA_TYP_TYP14                                                              */
+  PA_TYP_TYP14_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP14_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP14_Enum;
+
+/* =================================================  PA TYP TYP13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PA_TYP_TYP13                                                              */
+  PA_TYP_TYP13_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP13_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP13_Enum;
+
+/* =================================================  PA TYP TYP12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PA_TYP_TYP12                                                              */
+  PA_TYP_TYP12_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP12_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP12_Enum;
+
+/* =================================================  PA TYP TYP11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PA_TYP_TYP11                                                              */
+  PA_TYP_TYP11_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP11_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP11_Enum;
+
+/* =================================================  PA TYP TYP10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PA_TYP_TYP10                                                              */
+  PA_TYP_TYP10_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP10_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP10_Enum;
+
+/* ==================================================  PA TYP TYP9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP9                                                               */
+  PA_TYP_TYP9_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP9_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP9_Enum;
+
+/* ==================================================  PA TYP TYP8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP8                                                               */
+  PA_TYP_TYP8_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP8_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP8_Enum;
+
+/* ==================================================  PA TYP TYP7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP7                                                               */
+  PA_TYP_TYP7_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP7_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP7_Enum;
+
+/* ==================================================  PA TYP TYP6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP6                                                               */
+  PA_TYP_TYP6_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP6_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP6_Enum;
+
+/* ==================================================  PA TYP TYP5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP5                                                               */
+  PA_TYP_TYP5_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP5_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP5_Enum;
+
+/* ==================================================  PA TYP TYP4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP4                                                               */
+  PA_TYP_TYP4_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP4_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP4_Enum;
+
+/* ==================================================  PA TYP TYP3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP3                                                               */
+  PA_TYP_TYP3_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP3_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP3_Enum;
+
+/* ==================================================  PA TYP TYP2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP2                                                               */
+  PA_TYP_TYP2_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP2_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP2_Enum;
+
+/* ==================================================  PA TYP TYP1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP1                                                               */
+  PA_TYP_TYP1_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP1_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP1_Enum;
+
+/* ==================================================  PA TYP TYP0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PA_TYP_TYP0                                                               */
+  PA_TYP_TYP0_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PA_TYP_TYP0_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PA_TYP_TYP0_Enum;
+
+/* =========================================================  AFSR1  ========================================================= */
+/* ================================================  PA AFSR1 AFSR7 [28..31]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR1_AFSR7                                                            */
+  PA_AFSR1_AFSR7_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR1_AFSR7_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR1_AFSR7_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR1_AFSR7_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR1_AFSR7_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR1_AFSR7_Enum;
+
+/* ================================================  PA AFSR1 AFSR6 [24..27]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR1_AFSR6                                                            */
+  PA_AFSR1_AFSR6_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR1_AFSR6_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR1_AFSR6_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR1_AFSR6_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR1_AFSR6_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR1_AFSR6_Enum;
+
+/* ================================================  PA AFSR1 AFSR5 [20..23]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR1_AFSR5                                                            */
+  PA_AFSR1_AFSR5_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR1_AFSR5_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR1_AFSR5_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR1_AFSR5_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR1_AFSR5_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR1_AFSR5_Enum;
+
+/* ================================================  PA AFSR1 AFSR4 [16..19]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR1_AFSR4                                                            */
+  PA_AFSR1_AFSR4_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR1_AFSR4_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR1_AFSR4_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR1_AFSR4_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR1_AFSR4_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR1_AFSR4_Enum;
+
+/* ================================================  PA AFSR1 AFSR3 [12..15]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR1_AFSR3                                                            */
+  PA_AFSR1_AFSR3_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR1_AFSR3_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR1_AFSR3_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR1_AFSR3_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR1_AFSR3_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR1_AFSR3_Enum;
+
+/* ================================================  PA AFSR1 AFSR2 [8..11]  ================================================= */
+typedef enum {                                  /*!< PA_AFSR1_AFSR2                                                            */
+  PA_AFSR1_AFSR2_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR1_AFSR2_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR1_AFSR2_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR1_AFSR2_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR1_AFSR2_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR1_AFSR2_Enum;
+
+/* =================================================  PA AFSR1 AFSR1 [4..7]  ================================================= */
+typedef enum {                                  /*!< PA_AFSR1_AFSR1                                                            */
+  PA_AFSR1_AFSR1_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR1_AFSR1_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR1_AFSR1_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR1_AFSR1_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR1_AFSR1_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR1_AFSR1_Enum;
+
+/* =================================================  PA AFSR1 AFSR0 [0..3]  ================================================= */
+typedef enum {                                  /*!< PA_AFSR1_AFSR0                                                            */
+  PA_AFSR1_AFSR0_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR1_AFSR0_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR1_AFSR0_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR1_AFSR0_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR1_AFSR0_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR1_AFSR0_Enum;
+
+/* =========================================================  AFSR2  ========================================================= */
+/* ===============================================  PA AFSR2 AFSR15 [28..31]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR2_AFSR15                                                           */
+  PA_AFSR2_AFSR15_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR2_AFSR15_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR2_AFSR15_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR2_AFSR15_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR2_AFSR15_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR2_AFSR15_Enum;
+
+/* ===============================================  PA AFSR2 AFSR14 [24..27]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR2_AFSR14                                                           */
+  PA_AFSR2_AFSR14_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR2_AFSR14_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR2_AFSR14_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR2_AFSR14_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR2_AFSR14_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR2_AFSR14_Enum;
+
+/* ===============================================  PA AFSR2 AFSR13 [20..23]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR2_AFSR13                                                           */
+  PA_AFSR2_AFSR13_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR2_AFSR13_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR2_AFSR13_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR2_AFSR13_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR2_AFSR13_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR2_AFSR13_Enum;
+
+/* ===============================================  PA AFSR2 AFSR12 [16..19]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR2_AFSR12                                                           */
+  PA_AFSR2_AFSR12_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR2_AFSR12_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR2_AFSR12_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR2_AFSR12_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR2_AFSR12_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR2_AFSR12_Enum;
+
+/* ===============================================  PA AFSR2 AFSR11 [12..15]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR2_AFSR11                                                           */
+  PA_AFSR2_AFSR11_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR2_AFSR11_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR2_AFSR11_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR2_AFSR11_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR2_AFSR11_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR2_AFSR11_Enum;
+
+/* ================================================  PA AFSR2 AFSR10 [8..11]  ================================================ */
+typedef enum {                                  /*!< PA_AFSR2_AFSR10                                                           */
+  PA_AFSR2_AFSR10_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR2_AFSR10_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR2_AFSR10_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR2_AFSR10_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR2_AFSR10_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR2_AFSR10_Enum;
+
+/* =================================================  PA AFSR2 AFSR9 [4..7]  ================================================= */
+typedef enum {                                  /*!< PA_AFSR2_AFSR9                                                            */
+  PA_AFSR2_AFSR9_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR2_AFSR9_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR2_AFSR9_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR2_AFSR9_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR2_AFSR9_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR2_AFSR9_Enum;
+
+/* =================================================  PA AFSR2 AFSR8 [0..3]  ================================================= */
+typedef enum {                                  /*!< PA_AFSR2_AFSR8                                                            */
+  PA_AFSR2_AFSR8_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PA_AFSR2_AFSR8_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PA_AFSR2_AFSR8_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PA_AFSR2_AFSR8_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PA_AFSR2_AFSR8_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PA_AFSR2_AFSR8_Enum;
+
+/* =========================================================  PUPD  ========================================================== */
+/* ================================================  PA PUPD PUPD15 [30..31]  ================================================ */
+typedef enum {                                  /*!< PA_PUPD_PUPD15                                                            */
+  PA_PUPD_PUPD15_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD15_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD15_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD15_Enum;
+
+/* ================================================  PA PUPD PUPD14 [28..29]  ================================================ */
+typedef enum {                                  /*!< PA_PUPD_PUPD14                                                            */
+  PA_PUPD_PUPD14_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD14_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD14_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD14_Enum;
+
+/* ================================================  PA PUPD PUPD13 [26..27]  ================================================ */
+typedef enum {                                  /*!< PA_PUPD_PUPD13                                                            */
+  PA_PUPD_PUPD13_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD13_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD13_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD13_Enum;
+
+/* ================================================  PA PUPD PUPD12 [24..25]  ================================================ */
+typedef enum {                                  /*!< PA_PUPD_PUPD12                                                            */
+  PA_PUPD_PUPD12_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD12_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD12_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD12_Enum;
+
+/* ================================================  PA PUPD PUPD11 [22..23]  ================================================ */
+typedef enum {                                  /*!< PA_PUPD_PUPD11                                                            */
+  PA_PUPD_PUPD11_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD11_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD11_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD11_Enum;
+
+/* ================================================  PA PUPD PUPD10 [20..21]  ================================================ */
+typedef enum {                                  /*!< PA_PUPD_PUPD10                                                            */
+  PA_PUPD_PUPD10_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD10_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD10_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD10_Enum;
+
+/* ================================================  PA PUPD PUPD9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PA_PUPD_PUPD9                                                             */
+  PA_PUPD_PUPD9_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD9_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD9_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD9_Enum;
+
+/* ================================================  PA PUPD PUPD8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PA_PUPD_PUPD8                                                             */
+  PA_PUPD_PUPD8_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD8_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD8_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD8_Enum;
+
+/* ================================================  PA PUPD PUPD7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PA_PUPD_PUPD7                                                             */
+  PA_PUPD_PUPD7_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD7_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD7_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD7_Enum;
+
+/* ================================================  PA PUPD PUPD6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PA_PUPD_PUPD6                                                             */
+  PA_PUPD_PUPD6_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD6_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD6_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD6_Enum;
+
+/* ================================================  PA PUPD PUPD5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PA_PUPD_PUPD5                                                             */
+  PA_PUPD_PUPD5_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD5_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD5_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD5_Enum;
+
+/* =================================================  PA PUPD PUPD4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PA_PUPD_PUPD4                                                             */
+  PA_PUPD_PUPD4_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD4_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD4_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD4_Enum;
+
+/* =================================================  PA PUPD PUPD3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PA_PUPD_PUPD3                                                             */
+  PA_PUPD_PUPD3_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD3_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD3_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD3_Enum;
+
+/* =================================================  PA PUPD PUPD2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PA_PUPD_PUPD2                                                             */
+  PA_PUPD_PUPD2_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD2_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD2_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD2_Enum;
+
+/* =================================================  PA PUPD PUPD1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PA_PUPD_PUPD1                                                             */
+  PA_PUPD_PUPD1_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD1_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD1_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD1_Enum;
+
+/* =================================================  PA PUPD PUPD0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PA_PUPD_PUPD0                                                             */
+  PA_PUPD_PUPD0_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PA_PUPD_PUPD0_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PA_PUPD_PUPD0_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PA_PUPD_PUPD0_Enum;
+
+/* =========================================================  INDR  ========================================================== */
+/* =========================================================  OUTDR  ========================================================= */
+/* ==========================================================  BSR  ========================================================== */
+/* =================================================  PA BSR BSR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PA_BSR_BSR15                                                              */
+  PA_BSR_BSR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR15_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR15_Enum;
+
+/* =================================================  PA BSR BSR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PA_BSR_BSR14                                                              */
+  PA_BSR_BSR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR14_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR14_Enum;
+
+/* =================================================  PA BSR BSR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PA_BSR_BSR13                                                              */
+  PA_BSR_BSR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR13_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR13_Enum;
+
+/* =================================================  PA BSR BSR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PA_BSR_BSR12                                                              */
+  PA_BSR_BSR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR12_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR12_Enum;
+
+/* =================================================  PA BSR BSR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PA_BSR_BSR11                                                              */
+  PA_BSR_BSR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR11_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR11_Enum;
+
+/* =================================================  PA BSR BSR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PA_BSR_BSR10                                                              */
+  PA_BSR_BSR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR10_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR10_Enum;
+
+/* ==================================================  PA BSR BSR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR9                                                               */
+  PA_BSR_BSR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR9_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR9_Enum;
+
+/* ==================================================  PA BSR BSR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR8                                                               */
+  PA_BSR_BSR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR8_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR8_Enum;
+
+/* ==================================================  PA BSR BSR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR7                                                               */
+  PA_BSR_BSR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR7_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR7_Enum;
+
+/* ==================================================  PA BSR BSR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR6                                                               */
+  PA_BSR_BSR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR6_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR6_Enum;
+
+/* ==================================================  PA BSR BSR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR5                                                               */
+  PA_BSR_BSR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR5_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR5_Enum;
+
+/* ==================================================  PA BSR BSR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR4                                                               */
+  PA_BSR_BSR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR4_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR4_Enum;
+
+/* ==================================================  PA BSR BSR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR3                                                               */
+  PA_BSR_BSR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR3_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR3_Enum;
+
+/* ==================================================  PA BSR BSR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR2                                                               */
+  PA_BSR_BSR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR2_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR2_Enum;
+
+/* ==================================================  PA BSR BSR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR1                                                               */
+  PA_BSR_BSR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR1_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR1_Enum;
+
+/* ==================================================  PA BSR BSR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PA_BSR_BSR0                                                               */
+  PA_BSR_BSR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BSR_BSR0_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BSR_BSR0_Enum;
+
+/* ==========================================================  BCR  ========================================================== */
+/* =================================================  PA BCR BCR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PA_BCR_BCR15                                                              */
+  PA_BCR_BCR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR15_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR15_Enum;
+
+/* =================================================  PA BCR BCR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PA_BCR_BCR14                                                              */
+  PA_BCR_BCR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR14_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR14_Enum;
+
+/* =================================================  PA BCR BCR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PA_BCR_BCR13                                                              */
+  PA_BCR_BCR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR13_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR13_Enum;
+
+/* =================================================  PA BCR BCR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PA_BCR_BCR12                                                              */
+  PA_BCR_BCR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR12_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR12_Enum;
+
+/* =================================================  PA BCR BCR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PA_BCR_BCR11                                                              */
+  PA_BCR_BCR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR11_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR11_Enum;
+
+/* =================================================  PA BCR BCR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PA_BCR_BCR10                                                              */
+  PA_BCR_BCR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR10_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR10_Enum;
+
+/* ==================================================  PA BCR BCR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR9                                                               */
+  PA_BCR_BCR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR9_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR9_Enum;
+
+/* ==================================================  PA BCR BCR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR8                                                               */
+  PA_BCR_BCR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR8_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR8_Enum;
+
+/* ==================================================  PA BCR BCR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR7                                                               */
+  PA_BCR_BCR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR7_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR7_Enum;
+
+/* ==================================================  PA BCR BCR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR6                                                               */
+  PA_BCR_BCR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR6_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR6_Enum;
+
+/* ==================================================  PA BCR BCR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR5                                                               */
+  PA_BCR_BCR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR5_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR5_Enum;
+
+/* ==================================================  PA BCR BCR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR4                                                               */
+  PA_BCR_BCR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR4_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR4_Enum;
+
+/* ==================================================  PA BCR BCR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR3                                                               */
+  PA_BCR_BCR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR3_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR3_Enum;
+
+/* ==================================================  PA BCR BCR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR2                                                               */
+  PA_BCR_BCR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR2_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR2_Enum;
+
+/* ==================================================  PA BCR BCR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR1                                                               */
+  PA_BCR_BCR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR1_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR1_Enum;
+
+/* ==================================================  PA BCR BCR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PA_BCR_BCR0                                                               */
+  PA_BCR_BCR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PA_BCR_BCR0_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PA_BCR_BCR0_Enum;
+
+/* ========================================================  OUTDMSK  ======================================================== */
+/* =============================================  PA OUTDMSK OUTDMSK15 [15..15]  ============================================= */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK15                                                      */
+  PA_OUTDMSK_OUTDMSK15_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK15_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK15_Enum;
+
+/* =============================================  PA OUTDMSK OUTDMSK14 [14..14]  ============================================= */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK14                                                      */
+  PA_OUTDMSK_OUTDMSK14_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK14_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK14_Enum;
+
+/* =============================================  PA OUTDMSK OUTDMSK13 [13..13]  ============================================= */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK13                                                      */
+  PA_OUTDMSK_OUTDMSK13_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK13_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK13_Enum;
+
+/* =============================================  PA OUTDMSK OUTDMSK12 [12..12]  ============================================= */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK12                                                      */
+  PA_OUTDMSK_OUTDMSK12_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK12_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK12_Enum;
+
+/* =============================================  PA OUTDMSK OUTDMSK11 [11..11]  ============================================= */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK11                                                      */
+  PA_OUTDMSK_OUTDMSK11_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK11_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK11_Enum;
+
+/* =============================================  PA OUTDMSK OUTDMSK10 [10..10]  ============================================= */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK10                                                      */
+  PA_OUTDMSK_OUTDMSK10_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK10_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK10_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK9 [9..9]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK9                                                       */
+  PA_OUTDMSK_OUTDMSK9_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK9_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK9_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK8 [8..8]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK8                                                       */
+  PA_OUTDMSK_OUTDMSK8_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK8_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK8_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK7 [7..7]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK7                                                       */
+  PA_OUTDMSK_OUTDMSK7_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK7_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK7_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK6 [6..6]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK6                                                       */
+  PA_OUTDMSK_OUTDMSK6_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK6_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK6_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK5 [5..5]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK5                                                       */
+  PA_OUTDMSK_OUTDMSK5_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK5_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK5_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK4 [4..4]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK4                                                       */
+  PA_OUTDMSK_OUTDMSK4_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK4_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK4_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK3 [3..3]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK3                                                       */
+  PA_OUTDMSK_OUTDMSK3_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK3_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK3_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK2 [2..2]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK2                                                       */
+  PA_OUTDMSK_OUTDMSK2_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK2_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK2_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK1 [1..1]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK1                                                       */
+  PA_OUTDMSK_OUTDMSK1_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK1_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK1_Enum;
+
+/* ==============================================  PA OUTDMSK OUTDMSK0 [0..0]  =============================================== */
+typedef enum {                                  /*!< PA_OUTDMSK_OUTDMSK0                                                       */
+  PA_OUTDMSK_OUTDMSK0_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PA_OUTDMSK_OUTDMSK0_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PA_OUTDMSK_OUTDMSK0_Enum;
+
+/* =========================================================  DBCR  ========================================================== */
+/* ================================================  PA DBCR DBCLK [16..18]  ================================================= */
+typedef enum {                                  /*!< PA_DBCR_DBCLK                                                             */
+  PA_DBCR_DBCLK_HCLK1                  = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  PA_DBCR_DBCLK_HCLK4                  = 1,     /*!< HCLK4 : HCLK/4                                                            */
+  PA_DBCR_DBCLK_HCLK16                 = 2,     /*!< HCLK16 : HCLK/16                                                          */
+  PA_DBCR_DBCLK_HCLK64                 = 3,     /*!< HCLK64 : HCLK/64                                                          */
+  PA_DBCR_DBCLK_HCLK256                = 4,     /*!< HCLK256 : HCLK/256                                                        */
+  PA_DBCR_DBCLK_HCLK1024               = 5,     /*!< HCLK1024 : HCLK/1024                                                      */
+} PA_DBCR_DBCLK_Enum;
+
+/* ================================================  PA DBCR DBEN11 [11..11]  ================================================ */
+typedef enum {                                  /*!< PA_DBCR_DBEN11                                                            */
+  PA_DBCR_DBEN11_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN11_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN11_Enum;
+
+/* ================================================  PA DBCR DBEN10 [10..10]  ================================================ */
+typedef enum {                                  /*!< PA_DBCR_DBEN10                                                            */
+  PA_DBCR_DBEN10_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN10_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN10_Enum;
+
+/* =================================================  PA DBCR DBEN9 [9..9]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN9                                                             */
+  PA_DBCR_DBEN9_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN9_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN9_Enum;
+
+/* =================================================  PA DBCR DBEN8 [8..8]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN8                                                             */
+  PA_DBCR_DBEN8_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN8_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN8_Enum;
+
+/* =================================================  PA DBCR DBEN7 [7..7]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN7                                                             */
+  PA_DBCR_DBEN7_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN7_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN7_Enum;
+
+/* =================================================  PA DBCR DBEN6 [6..6]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN6                                                             */
+  PA_DBCR_DBEN6_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN6_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN6_Enum;
+
+/* =================================================  PA DBCR DBEN5 [5..5]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN5                                                             */
+  PA_DBCR_DBEN5_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN5_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN5_Enum;
+
+/* =================================================  PA DBCR DBEN4 [4..4]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN4                                                             */
+  PA_DBCR_DBEN4_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN4_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN4_Enum;
+
+/* =================================================  PA DBCR DBEN3 [3..3]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN3                                                             */
+  PA_DBCR_DBEN3_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN3_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN3_Enum;
+
+/* =================================================  PA DBCR DBEN2 [2..2]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN2                                                             */
+  PA_DBCR_DBEN2_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN2_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN2_Enum;
+
+/* =================================================  PA DBCR DBEN1 [1..1]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN1                                                             */
+  PA_DBCR_DBEN1_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN1_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN1_Enum;
+
+/* =================================================  PA DBCR DBEN0 [0..0]  ================================================== */
+typedef enum {                                  /*!< PA_DBCR_DBEN0                                                             */
+  PA_DBCR_DBEN0_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PA_DBCR_DBEN0_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PA_DBCR_DBEN0_Enum;
+
+/* ========================================================  PA_MOD  ========================================================= */
+/* ========================================================  PA_TYP  ========================================================= */
+/* =======================================================  PA_AFSR1  ======================================================== */
+/* =======================================================  PA_AFSR2  ======================================================== */
+/* ========================================================  PA_PUPD  ======================================================== */
+/* ========================================================  PA_INDR  ======================================================== */
+/* =======================================================  PA_OUTDR  ======================================================== */
+/* ========================================================  PA_BSR  ========================================================= */
+/* ========================================================  PA_BCR  ========================================================= */
+/* ======================================================  PA_OUTDMSK  ======================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PB                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+/* ================================================  PB MOD MODE15 [30..31]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE15                                                             */
+  PB_MOD_MODE15_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE15_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE15_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE15_Enum;
+
+/* ================================================  PB MOD MODE14 [28..29]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE14                                                             */
+  PB_MOD_MODE14_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE14_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE14_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE14_Enum;
+
+/* ================================================  PB MOD MODE13 [26..27]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE13                                                             */
+  PB_MOD_MODE13_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE13_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE13_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE13_Enum;
+
+/* ================================================  PB MOD MODE12 [24..25]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE12                                                             */
+  PB_MOD_MODE12_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE12_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE12_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE12_Enum;
+
+/* ================================================  PB MOD MODE11 [22..23]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE11                                                             */
+  PB_MOD_MODE11_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE11_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE11_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE11_Enum;
+
+/* ================================================  PB MOD MODE10 [20..21]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE10                                                             */
+  PB_MOD_MODE10_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE10_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE10_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE10_Enum;
+
+/* =================================================  PB MOD MODE9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE9                                                              */
+  PB_MOD_MODE9_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE9_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE9_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE9_Enum;
+
+/* =================================================  PB MOD MODE8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE8                                                              */
+  PB_MOD_MODE8_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE8_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE8_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE8_Enum;
+
+/* =================================================  PB MOD MODE7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE7                                                              */
+  PB_MOD_MODE7_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE7_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE7_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE7_Enum;
+
+/* =================================================  PB MOD MODE6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE6                                                              */
+  PB_MOD_MODE6_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE6_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE6_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE6_Enum;
+
+/* =================================================  PB MOD MODE5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PB_MOD_MODE5                                                              */
+  PB_MOD_MODE5_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE5_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE5_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE5_Enum;
+
+/* ==================================================  PB MOD MODE4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PB_MOD_MODE4                                                              */
+  PB_MOD_MODE4_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE4_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE4_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE4_Enum;
+
+/* ==================================================  PB MOD MODE3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PB_MOD_MODE3                                                              */
+  PB_MOD_MODE3_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE3_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE3_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE3_Enum;
+
+/* ==================================================  PB MOD MODE2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PB_MOD_MODE2                                                              */
+  PB_MOD_MODE2_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE2_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE2_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE2_Enum;
+
+/* ==================================================  PB MOD MODE1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PB_MOD_MODE1                                                              */
+  PB_MOD_MODE1_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE1_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE1_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE1_Enum;
+
+/* ==================================================  PB MOD MODE0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PB_MOD_MODE0                                                              */
+  PB_MOD_MODE0_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PB_MOD_MODE0_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PB_MOD_MODE0_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PB_MOD_MODE0_Enum;
+
+/* ==========================================================  TYP  ========================================================== */
+/* =================================================  PB TYP TYP15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PB_TYP_TYP15                                                              */
+  PB_TYP_TYP15_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP15_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP15_Enum;
+
+/* =================================================  PB TYP TYP14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PB_TYP_TYP14                                                              */
+  PB_TYP_TYP14_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP14_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP14_Enum;
+
+/* =================================================  PB TYP TYP13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PB_TYP_TYP13                                                              */
+  PB_TYP_TYP13_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP13_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP13_Enum;
+
+/* =================================================  PB TYP TYP12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PB_TYP_TYP12                                                              */
+  PB_TYP_TYP12_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP12_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP12_Enum;
+
+/* =================================================  PB TYP TYP11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PB_TYP_TYP11                                                              */
+  PB_TYP_TYP11_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP11_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP11_Enum;
+
+/* =================================================  PB TYP TYP10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PB_TYP_TYP10                                                              */
+  PB_TYP_TYP10_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP10_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP10_Enum;
+
+/* ==================================================  PB TYP TYP9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP9                                                               */
+  PB_TYP_TYP9_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP9_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP9_Enum;
+
+/* ==================================================  PB TYP TYP8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP8                                                               */
+  PB_TYP_TYP8_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP8_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP8_Enum;
+
+/* ==================================================  PB TYP TYP7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP7                                                               */
+  PB_TYP_TYP7_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP7_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP7_Enum;
+
+/* ==================================================  PB TYP TYP6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP6                                                               */
+  PB_TYP_TYP6_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP6_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP6_Enum;
+
+/* ==================================================  PB TYP TYP5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP5                                                               */
+  PB_TYP_TYP5_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP5_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP5_Enum;
+
+/* ==================================================  PB TYP TYP4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP4                                                               */
+  PB_TYP_TYP4_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP4_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP4_Enum;
+
+/* ==================================================  PB TYP TYP3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP3                                                               */
+  PB_TYP_TYP3_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP3_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP3_Enum;
+
+/* ==================================================  PB TYP TYP2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP2                                                               */
+  PB_TYP_TYP2_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP2_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP2_Enum;
+
+/* ==================================================  PB TYP TYP1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP1                                                               */
+  PB_TYP_TYP1_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP1_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP1_Enum;
+
+/* ==================================================  PB TYP TYP0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PB_TYP_TYP0                                                               */
+  PB_TYP_TYP0_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PB_TYP_TYP0_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PB_TYP_TYP0_Enum;
+
+/* =========================================================  AFSR1  ========================================================= */
+/* ================================================  PB AFSR1 AFSR7 [28..31]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR1_AFSR7                                                            */
+  PB_AFSR1_AFSR7_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR1_AFSR7_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR1_AFSR7_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR1_AFSR7_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR1_AFSR7_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR1_AFSR7_Enum;
+
+/* ================================================  PB AFSR1 AFSR6 [24..27]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR1_AFSR6                                                            */
+  PB_AFSR1_AFSR6_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR1_AFSR6_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR1_AFSR6_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR1_AFSR6_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR1_AFSR6_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR1_AFSR6_Enum;
+
+/* ================================================  PB AFSR1 AFSR5 [20..23]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR1_AFSR5                                                            */
+  PB_AFSR1_AFSR5_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR1_AFSR5_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR1_AFSR5_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR1_AFSR5_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR1_AFSR5_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR1_AFSR5_Enum;
+
+/* ================================================  PB AFSR1 AFSR4 [16..19]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR1_AFSR4                                                            */
+  PB_AFSR1_AFSR4_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR1_AFSR4_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR1_AFSR4_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR1_AFSR4_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR1_AFSR4_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR1_AFSR4_Enum;
+
+/* ================================================  PB AFSR1 AFSR3 [12..15]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR1_AFSR3                                                            */
+  PB_AFSR1_AFSR3_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR1_AFSR3_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR1_AFSR3_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR1_AFSR3_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR1_AFSR3_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR1_AFSR3_Enum;
+
+/* ================================================  PB AFSR1 AFSR2 [8..11]  ================================================= */
+typedef enum {                                  /*!< PB_AFSR1_AFSR2                                                            */
+  PB_AFSR1_AFSR2_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR1_AFSR2_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR1_AFSR2_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR1_AFSR2_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR1_AFSR2_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR1_AFSR2_Enum;
+
+/* =================================================  PB AFSR1 AFSR1 [4..7]  ================================================= */
+typedef enum {                                  /*!< PB_AFSR1_AFSR1                                                            */
+  PB_AFSR1_AFSR1_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR1_AFSR1_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR1_AFSR1_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR1_AFSR1_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR1_AFSR1_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR1_AFSR1_Enum;
+
+/* =================================================  PB AFSR1 AFSR0 [0..3]  ================================================= */
+typedef enum {                                  /*!< PB_AFSR1_AFSR0                                                            */
+  PB_AFSR1_AFSR0_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR1_AFSR0_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR1_AFSR0_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR1_AFSR0_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR1_AFSR0_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR1_AFSR0_Enum;
+
+/* =========================================================  AFSR2  ========================================================= */
+/* ===============================================  PB AFSR2 AFSR15 [28..31]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR2_AFSR15                                                           */
+  PB_AFSR2_AFSR15_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR2_AFSR15_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR2_AFSR15_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR2_AFSR15_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR2_AFSR15_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR2_AFSR15_Enum;
+
+/* ===============================================  PB AFSR2 AFSR14 [24..27]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR2_AFSR14                                                           */
+  PB_AFSR2_AFSR14_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR2_AFSR14_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR2_AFSR14_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR2_AFSR14_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR2_AFSR14_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR2_AFSR14_Enum;
+
+/* ===============================================  PB AFSR2 AFSR13 [20..23]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR2_AFSR13                                                           */
+  PB_AFSR2_AFSR13_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR2_AFSR13_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR2_AFSR13_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR2_AFSR13_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR2_AFSR13_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR2_AFSR13_Enum;
+
+/* ===============================================  PB AFSR2 AFSR12 [16..19]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR2_AFSR12                                                           */
+  PB_AFSR2_AFSR12_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR2_AFSR12_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR2_AFSR12_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR2_AFSR12_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR2_AFSR12_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR2_AFSR12_Enum;
+
+/* ===============================================  PB AFSR2 AFSR11 [12..15]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR2_AFSR11                                                           */
+  PB_AFSR2_AFSR11_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR2_AFSR11_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR2_AFSR11_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR2_AFSR11_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR2_AFSR11_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR2_AFSR11_Enum;
+
+/* ================================================  PB AFSR2 AFSR10 [8..11]  ================================================ */
+typedef enum {                                  /*!< PB_AFSR2_AFSR10                                                           */
+  PB_AFSR2_AFSR10_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR2_AFSR10_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR2_AFSR10_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR2_AFSR10_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR2_AFSR10_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR2_AFSR10_Enum;
+
+/* =================================================  PB AFSR2 AFSR9 [4..7]  ================================================= */
+typedef enum {                                  /*!< PB_AFSR2_AFSR9                                                            */
+  PB_AFSR2_AFSR9_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR2_AFSR9_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR2_AFSR9_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR2_AFSR9_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR2_AFSR9_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR2_AFSR9_Enum;
+
+/* =================================================  PB AFSR2 AFSR8 [0..3]  ================================================= */
+typedef enum {                                  /*!< PB_AFSR2_AFSR8                                                            */
+  PB_AFSR2_AFSR8_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PB_AFSR2_AFSR8_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PB_AFSR2_AFSR8_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PB_AFSR2_AFSR8_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PB_AFSR2_AFSR8_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PB_AFSR2_AFSR8_Enum;
+
+/* =========================================================  PUPD  ========================================================== */
+/* ================================================  PB PUPD PUPD15 [30..31]  ================================================ */
+typedef enum {                                  /*!< PB_PUPD_PUPD15                                                            */
+  PB_PUPD_PUPD15_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD15_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD15_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD15_Enum;
+
+/* ================================================  PB PUPD PUPD14 [28..29]  ================================================ */
+typedef enum {                                  /*!< PB_PUPD_PUPD14                                                            */
+  PB_PUPD_PUPD14_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD14_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD14_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD14_Enum;
+
+/* ================================================  PB PUPD PUPD13 [26..27]  ================================================ */
+typedef enum {                                  /*!< PB_PUPD_PUPD13                                                            */
+  PB_PUPD_PUPD13_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD13_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD13_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD13_Enum;
+
+/* ================================================  PB PUPD PUPD12 [24..25]  ================================================ */
+typedef enum {                                  /*!< PB_PUPD_PUPD12                                                            */
+  PB_PUPD_PUPD12_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD12_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD12_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD12_Enum;
+
+/* ================================================  PB PUPD PUPD11 [22..23]  ================================================ */
+typedef enum {                                  /*!< PB_PUPD_PUPD11                                                            */
+  PB_PUPD_PUPD11_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD11_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD11_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD11_Enum;
+
+/* ================================================  PB PUPD PUPD10 [20..21]  ================================================ */
+typedef enum {                                  /*!< PB_PUPD_PUPD10                                                            */
+  PB_PUPD_PUPD10_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD10_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD10_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD10_Enum;
+
+/* ================================================  PB PUPD PUPD9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PB_PUPD_PUPD9                                                             */
+  PB_PUPD_PUPD9_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD9_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD9_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD9_Enum;
+
+/* ================================================  PB PUPD PUPD8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PB_PUPD_PUPD8                                                             */
+  PB_PUPD_PUPD8_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD8_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD8_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD8_Enum;
+
+/* ================================================  PB PUPD PUPD7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PB_PUPD_PUPD7                                                             */
+  PB_PUPD_PUPD7_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD7_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD7_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD7_Enum;
+
+/* ================================================  PB PUPD PUPD6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PB_PUPD_PUPD6                                                             */
+  PB_PUPD_PUPD6_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD6_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD6_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD6_Enum;
+
+/* ================================================  PB PUPD PUPD5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PB_PUPD_PUPD5                                                             */
+  PB_PUPD_PUPD5_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD5_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD5_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD5_Enum;
+
+/* =================================================  PB PUPD PUPD4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PB_PUPD_PUPD4                                                             */
+  PB_PUPD_PUPD4_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD4_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD4_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD4_Enum;
+
+/* =================================================  PB PUPD PUPD3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PB_PUPD_PUPD3                                                             */
+  PB_PUPD_PUPD3_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD3_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD3_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD3_Enum;
+
+/* =================================================  PB PUPD PUPD2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PB_PUPD_PUPD2                                                             */
+  PB_PUPD_PUPD2_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD2_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD2_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD2_Enum;
+
+/* =================================================  PB PUPD PUPD1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PB_PUPD_PUPD1                                                             */
+  PB_PUPD_PUPD1_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD1_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD1_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD1_Enum;
+
+/* =================================================  PB PUPD PUPD0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PB_PUPD_PUPD0                                                             */
+  PB_PUPD_PUPD0_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PB_PUPD_PUPD0_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PB_PUPD_PUPD0_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PB_PUPD_PUPD0_Enum;
+
+/* =========================================================  INDR  ========================================================== */
+/* =========================================================  OUTDR  ========================================================= */
+/* ==========================================================  BSR  ========================================================== */
+/* =================================================  PB BSR BSR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PB_BSR_BSR15                                                              */
+  PB_BSR_BSR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR15_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR15_Enum;
+
+/* =================================================  PB BSR BSR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PB_BSR_BSR14                                                              */
+  PB_BSR_BSR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR14_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR14_Enum;
+
+/* =================================================  PB BSR BSR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PB_BSR_BSR13                                                              */
+  PB_BSR_BSR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR13_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR13_Enum;
+
+/* =================================================  PB BSR BSR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PB_BSR_BSR12                                                              */
+  PB_BSR_BSR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR12_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR12_Enum;
+
+/* =================================================  PB BSR BSR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PB_BSR_BSR11                                                              */
+  PB_BSR_BSR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR11_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR11_Enum;
+
+/* =================================================  PB BSR BSR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PB_BSR_BSR10                                                              */
+  PB_BSR_BSR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR10_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR10_Enum;
+
+/* ==================================================  PB BSR BSR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR9                                                               */
+  PB_BSR_BSR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR9_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR9_Enum;
+
+/* ==================================================  PB BSR BSR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR8                                                               */
+  PB_BSR_BSR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR8_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR8_Enum;
+
+/* ==================================================  PB BSR BSR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR7                                                               */
+  PB_BSR_BSR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR7_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR7_Enum;
+
+/* ==================================================  PB BSR BSR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR6                                                               */
+  PB_BSR_BSR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR6_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR6_Enum;
+
+/* ==================================================  PB BSR BSR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR5                                                               */
+  PB_BSR_BSR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR5_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR5_Enum;
+
+/* ==================================================  PB BSR BSR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR4                                                               */
+  PB_BSR_BSR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR4_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR4_Enum;
+
+/* ==================================================  PB BSR BSR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR3                                                               */
+  PB_BSR_BSR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR3_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR3_Enum;
+
+/* ==================================================  PB BSR BSR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR2                                                               */
+  PB_BSR_BSR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR2_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR2_Enum;
+
+/* ==================================================  PB BSR BSR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR1                                                               */
+  PB_BSR_BSR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR1_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR1_Enum;
+
+/* ==================================================  PB BSR BSR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PB_BSR_BSR0                                                               */
+  PB_BSR_BSR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BSR_BSR0_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BSR_BSR0_Enum;
+
+/* ==========================================================  BCR  ========================================================== */
+/* =================================================  PB BCR BCR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PB_BCR_BCR15                                                              */
+  PB_BCR_BCR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR15_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR15_Enum;
+
+/* =================================================  PB BCR BCR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PB_BCR_BCR14                                                              */
+  PB_BCR_BCR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR14_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR14_Enum;
+
+/* =================================================  PB BCR BCR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PB_BCR_BCR13                                                              */
+  PB_BCR_BCR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR13_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR13_Enum;
+
+/* =================================================  PB BCR BCR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PB_BCR_BCR12                                                              */
+  PB_BCR_BCR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR12_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR12_Enum;
+
+/* =================================================  PB BCR BCR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PB_BCR_BCR11                                                              */
+  PB_BCR_BCR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR11_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR11_Enum;
+
+/* =================================================  PB BCR BCR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PB_BCR_BCR10                                                              */
+  PB_BCR_BCR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR10_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR10_Enum;
+
+/* ==================================================  PB BCR BCR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR9                                                               */
+  PB_BCR_BCR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR9_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR9_Enum;
+
+/* ==================================================  PB BCR BCR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR8                                                               */
+  PB_BCR_BCR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR8_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR8_Enum;
+
+/* ==================================================  PB BCR BCR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR7                                                               */
+  PB_BCR_BCR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR7_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR7_Enum;
+
+/* ==================================================  PB BCR BCR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR6                                                               */
+  PB_BCR_BCR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR6_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR6_Enum;
+
+/* ==================================================  PB BCR BCR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR5                                                               */
+  PB_BCR_BCR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR5_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR5_Enum;
+
+/* ==================================================  PB BCR BCR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR4                                                               */
+  PB_BCR_BCR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR4_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR4_Enum;
+
+/* ==================================================  PB BCR BCR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR3                                                               */
+  PB_BCR_BCR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR3_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR3_Enum;
+
+/* ==================================================  PB BCR BCR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR2                                                               */
+  PB_BCR_BCR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR2_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR2_Enum;
+
+/* ==================================================  PB BCR BCR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR1                                                               */
+  PB_BCR_BCR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR1_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR1_Enum;
+
+/* ==================================================  PB BCR BCR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PB_BCR_BCR0                                                               */
+  PB_BCR_BCR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PB_BCR_BCR0_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PB_BCR_BCR0_Enum;
+
+/* ========================================================  OUTDMSK  ======================================================== */
+/* =============================================  PB OUTDMSK OUTDMSK15 [15..15]  ============================================= */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK15                                                      */
+  PB_OUTDMSK_OUTDMSK15_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK15_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK15_Enum;
+
+/* =============================================  PB OUTDMSK OUTDMSK14 [14..14]  ============================================= */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK14                                                      */
+  PB_OUTDMSK_OUTDMSK14_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK14_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK14_Enum;
+
+/* =============================================  PB OUTDMSK OUTDMSK13 [13..13]  ============================================= */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK13                                                      */
+  PB_OUTDMSK_OUTDMSK13_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK13_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK13_Enum;
+
+/* =============================================  PB OUTDMSK OUTDMSK12 [12..12]  ============================================= */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK12                                                      */
+  PB_OUTDMSK_OUTDMSK12_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK12_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK12_Enum;
+
+/* =============================================  PB OUTDMSK OUTDMSK11 [11..11]  ============================================= */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK11                                                      */
+  PB_OUTDMSK_OUTDMSK11_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK11_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK11_Enum;
+
+/* =============================================  PB OUTDMSK OUTDMSK10 [10..10]  ============================================= */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK10                                                      */
+  PB_OUTDMSK_OUTDMSK10_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK10_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK10_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK9 [9..9]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK9                                                       */
+  PB_OUTDMSK_OUTDMSK9_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK9_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK9_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK8 [8..8]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK8                                                       */
+  PB_OUTDMSK_OUTDMSK8_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK8_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK8_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK7 [7..7]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK7                                                       */
+  PB_OUTDMSK_OUTDMSK7_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK7_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK7_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK6 [6..6]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK6                                                       */
+  PB_OUTDMSK_OUTDMSK6_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK6_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK6_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK5 [5..5]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK5                                                       */
+  PB_OUTDMSK_OUTDMSK5_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK5_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK5_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK4 [4..4]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK4                                                       */
+  PB_OUTDMSK_OUTDMSK4_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK4_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK4_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK3 [3..3]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK3                                                       */
+  PB_OUTDMSK_OUTDMSK3_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK3_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK3_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK2 [2..2]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK2                                                       */
+  PB_OUTDMSK_OUTDMSK2_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK2_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK2_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK1 [1..1]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK1                                                       */
+  PB_OUTDMSK_OUTDMSK1_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK1_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK1_Enum;
+
+/* ==============================================  PB OUTDMSK OUTDMSK0 [0..0]  =============================================== */
+typedef enum {                                  /*!< PB_OUTDMSK_OUTDMSK0                                                       */
+  PB_OUTDMSK_OUTDMSK0_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PB_OUTDMSK_OUTDMSK0_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PB_OUTDMSK_OUTDMSK0_Enum;
+
+/* =========================================================  DBCR  ========================================================== */
+/* ================================================  PB DBCR DBCLK [16..18]  ================================================= */
+typedef enum {                                  /*!< PB_DBCR_DBCLK                                                             */
+  PB_DBCR_DBCLK_HCLK1                  = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  PB_DBCR_DBCLK_HCLK4                  = 1,     /*!< HCLK4 : HCLK/4                                                            */
+  PB_DBCR_DBCLK_HCLK16                 = 2,     /*!< HCLK16 : HCLK/16                                                          */
+  PB_DBCR_DBCLK_HCLK64                 = 3,     /*!< HCLK64 : HCLK/64                                                          */
+  PB_DBCR_DBCLK_HCLK256                = 4,     /*!< HCLK256 : HCLK/256                                                        */
+  PB_DBCR_DBCLK_HCLK1024               = 5,     /*!< HCLK1024 : HCLK/1024                                                      */
+} PB_DBCR_DBCLK_Enum;
+
+/* ================================================  PB DBCR DBEN11 [11..11]  ================================================ */
+typedef enum {                                  /*!< PB_DBCR_DBEN11                                                            */
+  PB_DBCR_DBEN11_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN11_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN11_Enum;
+
+/* ================================================  PB DBCR DBEN10 [10..10]  ================================================ */
+typedef enum {                                  /*!< PB_DBCR_DBEN10                                                            */
+  PB_DBCR_DBEN10_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN10_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN10_Enum;
+
+/* =================================================  PB DBCR DBEN9 [9..9]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN9                                                             */
+  PB_DBCR_DBEN9_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN9_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN9_Enum;
+
+/* =================================================  PB DBCR DBEN8 [8..8]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN8                                                             */
+  PB_DBCR_DBEN8_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN8_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN8_Enum;
+
+/* =================================================  PB DBCR DBEN7 [7..7]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN7                                                             */
+  PB_DBCR_DBEN7_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN7_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN7_Enum;
+
+/* =================================================  PB DBCR DBEN6 [6..6]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN6                                                             */
+  PB_DBCR_DBEN6_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN6_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN6_Enum;
+
+/* =================================================  PB DBCR DBEN5 [5..5]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN5                                                             */
+  PB_DBCR_DBEN5_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN5_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN5_Enum;
+
+/* =================================================  PB DBCR DBEN4 [4..4]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN4                                                             */
+  PB_DBCR_DBEN4_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN4_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN4_Enum;
+
+/* =================================================  PB DBCR DBEN3 [3..3]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN3                                                             */
+  PB_DBCR_DBEN3_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN3_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN3_Enum;
+
+/* =================================================  PB DBCR DBEN2 [2..2]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN2                                                             */
+  PB_DBCR_DBEN2_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN2_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN2_Enum;
+
+/* =================================================  PB DBCR DBEN1 [1..1]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN1                                                             */
+  PB_DBCR_DBEN1_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN1_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN1_Enum;
+
+/* =================================================  PB DBCR DBEN0 [0..0]  ================================================== */
+typedef enum {                                  /*!< PB_DBCR_DBEN0                                                             */
+  PB_DBCR_DBEN0_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PB_DBCR_DBEN0_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PB_DBCR_DBEN0_Enum;
+
+/* ========================================================  PB_MOD  ========================================================= */
+/* ========================================================  PB_TYP  ========================================================= */
+/* =======================================================  PB_AFSR1  ======================================================== */
+/* =======================================================  PB_AFSR2  ======================================================== */
+/* ========================================================  PB_PUPD  ======================================================== */
+/* ========================================================  PB_INDR  ======================================================== */
+/* =======================================================  PB_OUTDR  ======================================================== */
+/* ========================================================  PB_BSR  ========================================================= */
+/* ========================================================  PB_BCR  ========================================================= */
+/* ======================================================  PB_OUTDMSK  ======================================================= */
+/* ========================================================  PB_DBCR  ======================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PC                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+/* ================================================  PC MOD MODE15 [30..31]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE15                                                             */
+  PC_MOD_MODE15_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE15_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE15_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE15_Enum;
+
+/* ================================================  PC MOD MODE14 [28..29]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE14                                                             */
+  PC_MOD_MODE14_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE14_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE14_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE14_Enum;
+
+/* ================================================  PC MOD MODE13 [26..27]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE13                                                             */
+  PC_MOD_MODE13_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE13_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE13_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE13_Enum;
+
+/* ================================================  PC MOD MODE12 [24..25]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE12                                                             */
+  PC_MOD_MODE12_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE12_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE12_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE12_Enum;
+
+/* ================================================  PC MOD MODE11 [22..23]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE11                                                             */
+  PC_MOD_MODE11_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE11_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE11_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE11_Enum;
+
+/* ================================================  PC MOD MODE10 [20..21]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE10                                                             */
+  PC_MOD_MODE10_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE10_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE10_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE10_Enum;
+
+/* =================================================  PC MOD MODE9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE9                                                              */
+  PC_MOD_MODE9_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE9_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE9_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE9_Enum;
+
+/* =================================================  PC MOD MODE8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE8                                                              */
+  PC_MOD_MODE8_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE8_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE8_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE8_Enum;
+
+/* =================================================  PC MOD MODE7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE7                                                              */
+  PC_MOD_MODE7_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE7_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE7_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE7_Enum;
+
+/* =================================================  PC MOD MODE6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE6                                                              */
+  PC_MOD_MODE6_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE6_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE6_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE6_Enum;
+
+/* =================================================  PC MOD MODE5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PC_MOD_MODE5                                                              */
+  PC_MOD_MODE5_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE5_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE5_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE5_Enum;
+
+/* ==================================================  PC MOD MODE4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PC_MOD_MODE4                                                              */
+  PC_MOD_MODE4_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE4_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE4_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE4_Enum;
+
+/* ==================================================  PC MOD MODE3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PC_MOD_MODE3                                                              */
+  PC_MOD_MODE3_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE3_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE3_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE3_Enum;
+
+/* ==================================================  PC MOD MODE2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PC_MOD_MODE2                                                              */
+  PC_MOD_MODE2_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE2_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE2_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE2_Enum;
+
+/* ==================================================  PC MOD MODE1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PC_MOD_MODE1                                                              */
+  PC_MOD_MODE1_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE1_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE1_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE1_Enum;
+
+/* ==================================================  PC MOD MODE0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PC_MOD_MODE0                                                              */
+  PC_MOD_MODE0_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PC_MOD_MODE0_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PC_MOD_MODE0_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PC_MOD_MODE0_Enum;
+
+/* ==========================================================  TYP  ========================================================== */
+/* =================================================  PC TYP TYP15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PC_TYP_TYP15                                                              */
+  PC_TYP_TYP15_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP15_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP15_Enum;
+
+/* =================================================  PC TYP TYP14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PC_TYP_TYP14                                                              */
+  PC_TYP_TYP14_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP14_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP14_Enum;
+
+/* =================================================  PC TYP TYP13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PC_TYP_TYP13                                                              */
+  PC_TYP_TYP13_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP13_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP13_Enum;
+
+/* =================================================  PC TYP TYP12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PC_TYP_TYP12                                                              */
+  PC_TYP_TYP12_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP12_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP12_Enum;
+
+/* =================================================  PC TYP TYP11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PC_TYP_TYP11                                                              */
+  PC_TYP_TYP11_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP11_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP11_Enum;
+
+/* =================================================  PC TYP TYP10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PC_TYP_TYP10                                                              */
+  PC_TYP_TYP10_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP10_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP10_Enum;
+
+/* ==================================================  PC TYP TYP9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP9                                                               */
+  PC_TYP_TYP9_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP9_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP9_Enum;
+
+/* ==================================================  PC TYP TYP8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP8                                                               */
+  PC_TYP_TYP8_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP8_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP8_Enum;
+
+/* ==================================================  PC TYP TYP7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP7                                                               */
+  PC_TYP_TYP7_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP7_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP7_Enum;
+
+/* ==================================================  PC TYP TYP6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP6                                                               */
+  PC_TYP_TYP6_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP6_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP6_Enum;
+
+/* ==================================================  PC TYP TYP5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP5                                                               */
+  PC_TYP_TYP5_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP5_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP5_Enum;
+
+/* ==================================================  PC TYP TYP4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP4                                                               */
+  PC_TYP_TYP4_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP4_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP4_Enum;
+
+/* ==================================================  PC TYP TYP3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP3                                                               */
+  PC_TYP_TYP3_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP3_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP3_Enum;
+
+/* ==================================================  PC TYP TYP2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP2                                                               */
+  PC_TYP_TYP2_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP2_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP2_Enum;
+
+/* ==================================================  PC TYP TYP1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP1                                                               */
+  PC_TYP_TYP1_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP1_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP1_Enum;
+
+/* ==================================================  PC TYP TYP0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PC_TYP_TYP0                                                               */
+  PC_TYP_TYP0_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PC_TYP_TYP0_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PC_TYP_TYP0_Enum;
+
+/* =========================================================  AFSR1  ========================================================= */
+/* ================================================  PC AFSR1 AFSR7 [28..31]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR1_AFSR7                                                            */
+  PC_AFSR1_AFSR7_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR1_AFSR7_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR1_AFSR7_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR1_AFSR7_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR1_AFSR7_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR1_AFSR7_Enum;
+
+/* ================================================  PC AFSR1 AFSR6 [24..27]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR1_AFSR6                                                            */
+  PC_AFSR1_AFSR6_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR1_AFSR6_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR1_AFSR6_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR1_AFSR6_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR1_AFSR6_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR1_AFSR6_Enum;
+
+/* ================================================  PC AFSR1 AFSR5 [20..23]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR1_AFSR5                                                            */
+  PC_AFSR1_AFSR5_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR1_AFSR5_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR1_AFSR5_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR1_AFSR5_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR1_AFSR5_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR1_AFSR5_Enum;
+
+/* ================================================  PC AFSR1 AFSR4 [16..19]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR1_AFSR4                                                            */
+  PC_AFSR1_AFSR4_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR1_AFSR4_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR1_AFSR4_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR1_AFSR4_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR1_AFSR4_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR1_AFSR4_Enum;
+
+/* ================================================  PC AFSR1 AFSR3 [12..15]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR1_AFSR3                                                            */
+  PC_AFSR1_AFSR3_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR1_AFSR3_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR1_AFSR3_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR1_AFSR3_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR1_AFSR3_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR1_AFSR3_Enum;
+
+/* ================================================  PC AFSR1 AFSR2 [8..11]  ================================================= */
+typedef enum {                                  /*!< PC_AFSR1_AFSR2                                                            */
+  PC_AFSR1_AFSR2_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR1_AFSR2_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR1_AFSR2_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR1_AFSR2_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR1_AFSR2_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR1_AFSR2_Enum;
+
+/* =================================================  PC AFSR1 AFSR1 [4..7]  ================================================= */
+typedef enum {                                  /*!< PC_AFSR1_AFSR1                                                            */
+  PC_AFSR1_AFSR1_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR1_AFSR1_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR1_AFSR1_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR1_AFSR1_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR1_AFSR1_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR1_AFSR1_Enum;
+
+/* =================================================  PC AFSR1 AFSR0 [0..3]  ================================================= */
+typedef enum {                                  /*!< PC_AFSR1_AFSR0                                                            */
+  PC_AFSR1_AFSR0_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR1_AFSR0_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR1_AFSR0_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR1_AFSR0_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR1_AFSR0_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR1_AFSR0_Enum;
+
+/* =========================================================  AFSR2  ========================================================= */
+/* ===============================================  PC AFSR2 AFSR15 [28..31]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR2_AFSR15                                                           */
+  PC_AFSR2_AFSR15_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR2_AFSR15_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR2_AFSR15_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR2_AFSR15_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR2_AFSR15_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR2_AFSR15_Enum;
+
+/* ===============================================  PC AFSR2 AFSR14 [24..27]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR2_AFSR14                                                           */
+  PC_AFSR2_AFSR14_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR2_AFSR14_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR2_AFSR14_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR2_AFSR14_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR2_AFSR14_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR2_AFSR14_Enum;
+
+/* ===============================================  PC AFSR2 AFSR13 [20..23]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR2_AFSR13                                                           */
+  PC_AFSR2_AFSR13_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR2_AFSR13_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR2_AFSR13_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR2_AFSR13_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR2_AFSR13_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR2_AFSR13_Enum;
+
+/* ===============================================  PC AFSR2 AFSR12 [16..19]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR2_AFSR12                                                           */
+  PC_AFSR2_AFSR12_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR2_AFSR12_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR2_AFSR12_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR2_AFSR12_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR2_AFSR12_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR2_AFSR12_Enum;
+
+/* ===============================================  PC AFSR2 AFSR11 [12..15]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR2_AFSR11                                                           */
+  PC_AFSR2_AFSR11_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR2_AFSR11_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR2_AFSR11_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR2_AFSR11_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR2_AFSR11_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR2_AFSR11_Enum;
+
+/* ================================================  PC AFSR2 AFSR10 [8..11]  ================================================ */
+typedef enum {                                  /*!< PC_AFSR2_AFSR10                                                           */
+  PC_AFSR2_AFSR10_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR2_AFSR10_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR2_AFSR10_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR2_AFSR10_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR2_AFSR10_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR2_AFSR10_Enum;
+
+/* =================================================  PC AFSR2 AFSR9 [4..7]  ================================================= */
+typedef enum {                                  /*!< PC_AFSR2_AFSR9                                                            */
+  PC_AFSR2_AFSR9_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR2_AFSR9_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR2_AFSR9_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR2_AFSR9_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR2_AFSR9_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR2_AFSR9_Enum;
+
+/* =================================================  PC AFSR2 AFSR8 [0..3]  ================================================= */
+typedef enum {                                  /*!< PC_AFSR2_AFSR8                                                            */
+  PC_AFSR2_AFSR8_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PC_AFSR2_AFSR8_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PC_AFSR2_AFSR8_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PC_AFSR2_AFSR8_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PC_AFSR2_AFSR8_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PC_AFSR2_AFSR8_Enum;
+
+/* =========================================================  PUPD  ========================================================== */
+/* ================================================  PC PUPD PUPD15 [30..31]  ================================================ */
+typedef enum {                                  /*!< PC_PUPD_PUPD15                                                            */
+  PC_PUPD_PUPD15_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD15_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD15_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD15_Enum;
+
+/* ================================================  PC PUPD PUPD14 [28..29]  ================================================ */
+typedef enum {                                  /*!< PC_PUPD_PUPD14                                                            */
+  PC_PUPD_PUPD14_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD14_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD14_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD14_Enum;
+
+/* ================================================  PC PUPD PUPD13 [26..27]  ================================================ */
+typedef enum {                                  /*!< PC_PUPD_PUPD13                                                            */
+  PC_PUPD_PUPD13_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD13_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD13_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD13_Enum;
+
+/* ================================================  PC PUPD PUPD12 [24..25]  ================================================ */
+typedef enum {                                  /*!< PC_PUPD_PUPD12                                                            */
+  PC_PUPD_PUPD12_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD12_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD12_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD12_Enum;
+
+/* ================================================  PC PUPD PUPD11 [22..23]  ================================================ */
+typedef enum {                                  /*!< PC_PUPD_PUPD11                                                            */
+  PC_PUPD_PUPD11_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD11_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD11_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD11_Enum;
+
+/* ================================================  PC PUPD PUPD10 [20..21]  ================================================ */
+typedef enum {                                  /*!< PC_PUPD_PUPD10                                                            */
+  PC_PUPD_PUPD10_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD10_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD10_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD10_Enum;
+
+/* ================================================  PC PUPD PUPD9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PC_PUPD_PUPD9                                                             */
+  PC_PUPD_PUPD9_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD9_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD9_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD9_Enum;
+
+/* ================================================  PC PUPD PUPD8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PC_PUPD_PUPD8                                                             */
+  PC_PUPD_PUPD8_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD8_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD8_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD8_Enum;
+
+/* ================================================  PC PUPD PUPD7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PC_PUPD_PUPD7                                                             */
+  PC_PUPD_PUPD7_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD7_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD7_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD7_Enum;
+
+/* ================================================  PC PUPD PUPD6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PC_PUPD_PUPD6                                                             */
+  PC_PUPD_PUPD6_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD6_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD6_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD6_Enum;
+
+/* ================================================  PC PUPD PUPD5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PC_PUPD_PUPD5                                                             */
+  PC_PUPD_PUPD5_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD5_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD5_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD5_Enum;
+
+/* =================================================  PC PUPD PUPD4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PC_PUPD_PUPD4                                                             */
+  PC_PUPD_PUPD4_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD4_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD4_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD4_Enum;
+
+/* =================================================  PC PUPD PUPD3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PC_PUPD_PUPD3                                                             */
+  PC_PUPD_PUPD3_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD3_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD3_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD3_Enum;
+
+/* =================================================  PC PUPD PUPD2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PC_PUPD_PUPD2                                                             */
+  PC_PUPD_PUPD2_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD2_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD2_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD2_Enum;
+
+/* =================================================  PC PUPD PUPD1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PC_PUPD_PUPD1                                                             */
+  PC_PUPD_PUPD1_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD1_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD1_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD1_Enum;
+
+/* =================================================  PC PUPD PUPD0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PC_PUPD_PUPD0                                                             */
+  PC_PUPD_PUPD0_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PC_PUPD_PUPD0_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PC_PUPD_PUPD0_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PC_PUPD_PUPD0_Enum;
+
+/* =========================================================  INDR  ========================================================== */
+/* =========================================================  OUTDR  ========================================================= */
+/* ==========================================================  BSR  ========================================================== */
+/* =================================================  PC BSR BSR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PC_BSR_BSR15                                                              */
+  PC_BSR_BSR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR15_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR15_Enum;
+
+/* =================================================  PC BSR BSR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PC_BSR_BSR14                                                              */
+  PC_BSR_BSR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR14_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR14_Enum;
+
+/* =================================================  PC BSR BSR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PC_BSR_BSR13                                                              */
+  PC_BSR_BSR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR13_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR13_Enum;
+
+/* =================================================  PC BSR BSR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PC_BSR_BSR12                                                              */
+  PC_BSR_BSR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR12_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR12_Enum;
+
+/* =================================================  PC BSR BSR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PC_BSR_BSR11                                                              */
+  PC_BSR_BSR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR11_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR11_Enum;
+
+/* =================================================  PC BSR BSR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PC_BSR_BSR10                                                              */
+  PC_BSR_BSR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR10_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR10_Enum;
+
+/* ==================================================  PC BSR BSR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR9                                                               */
+  PC_BSR_BSR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR9_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR9_Enum;
+
+/* ==================================================  PC BSR BSR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR8                                                               */
+  PC_BSR_BSR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR8_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR8_Enum;
+
+/* ==================================================  PC BSR BSR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR7                                                               */
+  PC_BSR_BSR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR7_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR7_Enum;
+
+/* ==================================================  PC BSR BSR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR6                                                               */
+  PC_BSR_BSR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR6_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR6_Enum;
+
+/* ==================================================  PC BSR BSR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR5                                                               */
+  PC_BSR_BSR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR5_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR5_Enum;
+
+/* ==================================================  PC BSR BSR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR4                                                               */
+  PC_BSR_BSR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR4_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR4_Enum;
+
+/* ==================================================  PC BSR BSR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR3                                                               */
+  PC_BSR_BSR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR3_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR3_Enum;
+
+/* ==================================================  PC BSR BSR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR2                                                               */
+  PC_BSR_BSR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR2_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR2_Enum;
+
+/* ==================================================  PC BSR BSR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR1                                                               */
+  PC_BSR_BSR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR1_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR1_Enum;
+
+/* ==================================================  PC BSR BSR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PC_BSR_BSR0                                                               */
+  PC_BSR_BSR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BSR_BSR0_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BSR_BSR0_Enum;
+
+/* ==========================================================  BCR  ========================================================== */
+/* =================================================  PC BCR BCR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PC_BCR_BCR15                                                              */
+  PC_BCR_BCR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR15_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR15_Enum;
+
+/* =================================================  PC BCR BCR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PC_BCR_BCR14                                                              */
+  PC_BCR_BCR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR14_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR14_Enum;
+
+/* =================================================  PC BCR BCR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PC_BCR_BCR13                                                              */
+  PC_BCR_BCR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR13_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR13_Enum;
+
+/* =================================================  PC BCR BCR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PC_BCR_BCR12                                                              */
+  PC_BCR_BCR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR12_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR12_Enum;
+
+/* =================================================  PC BCR BCR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PC_BCR_BCR11                                                              */
+  PC_BCR_BCR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR11_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR11_Enum;
+
+/* =================================================  PC BCR BCR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PC_BCR_BCR10                                                              */
+  PC_BCR_BCR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR10_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR10_Enum;
+
+/* ==================================================  PC BCR BCR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR9                                                               */
+  PC_BCR_BCR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR9_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR9_Enum;
+
+/* ==================================================  PC BCR BCR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR8                                                               */
+  PC_BCR_BCR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR8_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR8_Enum;
+
+/* ==================================================  PC BCR BCR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR7                                                               */
+  PC_BCR_BCR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR7_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR7_Enum;
+
+/* ==================================================  PC BCR BCR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR6                                                               */
+  PC_BCR_BCR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR6_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR6_Enum;
+
+/* ==================================================  PC BCR BCR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR5                                                               */
+  PC_BCR_BCR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR5_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR5_Enum;
+
+/* ==================================================  PC BCR BCR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR4                                                               */
+  PC_BCR_BCR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR4_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR4_Enum;
+
+/* ==================================================  PC BCR BCR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR3                                                               */
+  PC_BCR_BCR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR3_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR3_Enum;
+
+/* ==================================================  PC BCR BCR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR2                                                               */
+  PC_BCR_BCR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR2_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR2_Enum;
+
+/* ==================================================  PC BCR BCR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR1                                                               */
+  PC_BCR_BCR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR1_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR1_Enum;
+
+/* ==================================================  PC BCR BCR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PC_BCR_BCR0                                                               */
+  PC_BCR_BCR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PC_BCR_BCR0_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PC_BCR_BCR0_Enum;
+
+/* ========================================================  OUTDMSK  ======================================================== */
+/* =============================================  PC OUTDMSK OUTDMSK15 [15..15]  ============================================= */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK15                                                      */
+  PC_OUTDMSK_OUTDMSK15_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK15_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK15_Enum;
+
+/* =============================================  PC OUTDMSK OUTDMSK14 [14..14]  ============================================= */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK14                                                      */
+  PC_OUTDMSK_OUTDMSK14_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK14_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK14_Enum;
+
+/* =============================================  PC OUTDMSK OUTDMSK13 [13..13]  ============================================= */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK13                                                      */
+  PC_OUTDMSK_OUTDMSK13_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK13_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK13_Enum;
+
+/* =============================================  PC OUTDMSK OUTDMSK12 [12..12]  ============================================= */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK12                                                      */
+  PC_OUTDMSK_OUTDMSK12_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK12_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK12_Enum;
+
+/* =============================================  PC OUTDMSK OUTDMSK11 [11..11]  ============================================= */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK11                                                      */
+  PC_OUTDMSK_OUTDMSK11_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK11_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK11_Enum;
+
+/* =============================================  PC OUTDMSK OUTDMSK10 [10..10]  ============================================= */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK10                                                      */
+  PC_OUTDMSK_OUTDMSK10_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK10_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK10_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK9 [9..9]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK9                                                       */
+  PC_OUTDMSK_OUTDMSK9_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK9_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK9_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK8 [8..8]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK8                                                       */
+  PC_OUTDMSK_OUTDMSK8_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK8_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK8_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK7 [7..7]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK7                                                       */
+  PC_OUTDMSK_OUTDMSK7_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK7_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK7_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK6 [6..6]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK6                                                       */
+  PC_OUTDMSK_OUTDMSK6_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK6_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK6_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK5 [5..5]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK5                                                       */
+  PC_OUTDMSK_OUTDMSK5_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK5_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK5_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK4 [4..4]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK4                                                       */
+  PC_OUTDMSK_OUTDMSK4_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK4_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK4_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK3 [3..3]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK3                                                       */
+  PC_OUTDMSK_OUTDMSK3_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK3_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK3_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK2 [2..2]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK2                                                       */
+  PC_OUTDMSK_OUTDMSK2_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK2_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK2_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK1 [1..1]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK1                                                       */
+  PC_OUTDMSK_OUTDMSK1_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK1_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK1_Enum;
+
+/* ==============================================  PC OUTDMSK OUTDMSK0 [0..0]  =============================================== */
+typedef enum {                                  /*!< PC_OUTDMSK_OUTDMSK0                                                       */
+  PC_OUTDMSK_OUTDMSK0_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PC_OUTDMSK_OUTDMSK0_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PC_OUTDMSK_OUTDMSK0_Enum;
+
+/* =========================================================  DBCR  ========================================================== */
+/* ================================================  PC DBCR DBCLK [16..18]  ================================================= */
+typedef enum {                                  /*!< PC_DBCR_DBCLK                                                             */
+  PC_DBCR_DBCLK_HCLK1                  = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  PC_DBCR_DBCLK_HCLK4                  = 1,     /*!< HCLK4 : HCLK/4                                                            */
+  PC_DBCR_DBCLK_HCLK16                 = 2,     /*!< HCLK16 : HCLK/16                                                          */
+  PC_DBCR_DBCLK_HCLK64                 = 3,     /*!< HCLK64 : HCLK/64                                                          */
+  PC_DBCR_DBCLK_HCLK256                = 4,     /*!< HCLK256 : HCLK/256                                                        */
+  PC_DBCR_DBCLK_HCLK1024               = 5,     /*!< HCLK1024 : HCLK/1024                                                      */
+} PC_DBCR_DBCLK_Enum;
+
+/* ================================================  PC DBCR DBEN11 [11..11]  ================================================ */
+typedef enum {                                  /*!< PC_DBCR_DBEN11                                                            */
+  PC_DBCR_DBEN11_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN11_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN11_Enum;
+
+/* ================================================  PC DBCR DBEN10 [10..10]  ================================================ */
+typedef enum {                                  /*!< PC_DBCR_DBEN10                                                            */
+  PC_DBCR_DBEN10_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN10_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN10_Enum;
+
+/* =================================================  PC DBCR DBEN9 [9..9]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN9                                                             */
+  PC_DBCR_DBEN9_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN9_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN9_Enum;
+
+/* =================================================  PC DBCR DBEN8 [8..8]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN8                                                             */
+  PC_DBCR_DBEN8_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN8_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN8_Enum;
+
+/* =================================================  PC DBCR DBEN7 [7..7]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN7                                                             */
+  PC_DBCR_DBEN7_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN7_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN7_Enum;
+
+/* =================================================  PC DBCR DBEN6 [6..6]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN6                                                             */
+  PC_DBCR_DBEN6_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN6_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN6_Enum;
+
+/* =================================================  PC DBCR DBEN5 [5..5]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN5                                                             */
+  PC_DBCR_DBEN5_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN5_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN5_Enum;
+
+/* =================================================  PC DBCR DBEN4 [4..4]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN4                                                             */
+  PC_DBCR_DBEN4_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN4_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN4_Enum;
+
+/* =================================================  PC DBCR DBEN3 [3..3]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN3                                                             */
+  PC_DBCR_DBEN3_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN3_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN3_Enum;
+
+/* =================================================  PC DBCR DBEN2 [2..2]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN2                                                             */
+  PC_DBCR_DBEN2_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN2_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN2_Enum;
+
+/* =================================================  PC DBCR DBEN1 [1..1]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN1                                                             */
+  PC_DBCR_DBEN1_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN1_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN1_Enum;
+
+/* =================================================  PC DBCR DBEN0 [0..0]  ================================================== */
+typedef enum {                                  /*!< PC_DBCR_DBEN0                                                             */
+  PC_DBCR_DBEN0_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PC_DBCR_DBEN0_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PC_DBCR_DBEN0_Enum;
+
+/* ========================================================  PC_MOD  ========================================================= */
+/* ========================================================  PC_TYP  ========================================================= */
+/* =======================================================  PC_AFSR1  ======================================================== */
+/* =======================================================  PC_AFSR2  ======================================================== */
+/* ========================================================  PC_PUPD  ======================================================== */
+/* ========================================================  PC_INDR  ======================================================== */
+/* =======================================================  PC_OUTDR  ======================================================== */
+/* ========================================================  PC_BSR  ========================================================= */
+/* ========================================================  PC_BCR  ========================================================= */
+/* ======================================================  PC_OUTDMSK  ======================================================= */
+/* ========================================================  PC_DBCR  ======================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PD                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+/* ================================================  PD MOD MODE15 [30..31]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE15                                                             */
+  PD_MOD_MODE15_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE15_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE15_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE15_Enum;
+
+/* ================================================  PD MOD MODE14 [28..29]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE14                                                             */
+  PD_MOD_MODE14_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE14_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE14_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE14_Enum;
+
+/* ================================================  PD MOD MODE13 [26..27]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE13                                                             */
+  PD_MOD_MODE13_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE13_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE13_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE13_Enum;
+
+/* ================================================  PD MOD MODE12 [24..25]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE12                                                             */
+  PD_MOD_MODE12_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE12_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE12_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE12_Enum;
+
+/* ================================================  PD MOD MODE11 [22..23]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE11                                                             */
+  PD_MOD_MODE11_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE11_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE11_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE11_Enum;
+
+/* ================================================  PD MOD MODE10 [20..21]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE10                                                             */
+  PD_MOD_MODE10_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE10_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE10_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE10_Enum;
+
+/* =================================================  PD MOD MODE9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE9                                                              */
+  PD_MOD_MODE9_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE9_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE9_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE9_Enum;
+
+/* =================================================  PD MOD MODE8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE8                                                              */
+  PD_MOD_MODE8_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE8_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE8_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE8_Enum;
+
+/* =================================================  PD MOD MODE7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE7                                                              */
+  PD_MOD_MODE7_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE7_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE7_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE7_Enum;
+
+/* =================================================  PD MOD MODE6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE6                                                              */
+  PD_MOD_MODE6_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE6_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE6_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE6_Enum;
+
+/* =================================================  PD MOD MODE5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PD_MOD_MODE5                                                              */
+  PD_MOD_MODE5_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE5_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE5_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE5_Enum;
+
+/* ==================================================  PD MOD MODE4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PD_MOD_MODE4                                                              */
+  PD_MOD_MODE4_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE4_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE4_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE4_Enum;
+
+/* ==================================================  PD MOD MODE3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PD_MOD_MODE3                                                              */
+  PD_MOD_MODE3_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE3_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE3_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE3_Enum;
+
+/* ==================================================  PD MOD MODE2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PD_MOD_MODE2                                                              */
+  PD_MOD_MODE2_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE2_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE2_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE2_Enum;
+
+/* ==================================================  PD MOD MODE1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PD_MOD_MODE1                                                              */
+  PD_MOD_MODE1_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE1_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE1_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE1_Enum;
+
+/* ==================================================  PD MOD MODE0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PD_MOD_MODE0                                                              */
+  PD_MOD_MODE0_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PD_MOD_MODE0_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PD_MOD_MODE0_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PD_MOD_MODE0_Enum;
+
+/* ==========================================================  TYP  ========================================================== */
+/* =================================================  PD TYP TYP15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PD_TYP_TYP15                                                              */
+  PD_TYP_TYP15_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP15_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP15_Enum;
+
+/* =================================================  PD TYP TYP14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PD_TYP_TYP14                                                              */
+  PD_TYP_TYP14_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP14_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP14_Enum;
+
+/* =================================================  PD TYP TYP13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PD_TYP_TYP13                                                              */
+  PD_TYP_TYP13_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP13_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP13_Enum;
+
+/* =================================================  PD TYP TYP12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PD_TYP_TYP12                                                              */
+  PD_TYP_TYP12_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP12_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP12_Enum;
+
+/* =================================================  PD TYP TYP11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PD_TYP_TYP11                                                              */
+  PD_TYP_TYP11_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP11_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP11_Enum;
+
+/* =================================================  PD TYP TYP10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PD_TYP_TYP10                                                              */
+  PD_TYP_TYP10_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP10_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP10_Enum;
+
+/* ==================================================  PD TYP TYP9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP9                                                               */
+  PD_TYP_TYP9_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP9_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP9_Enum;
+
+/* ==================================================  PD TYP TYP8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP8                                                               */
+  PD_TYP_TYP8_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP8_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP8_Enum;
+
+/* ==================================================  PD TYP TYP7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP7                                                               */
+  PD_TYP_TYP7_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP7_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP7_Enum;
+
+/* ==================================================  PD TYP TYP6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP6                                                               */
+  PD_TYP_TYP6_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP6_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP6_Enum;
+
+/* ==================================================  PD TYP TYP5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP5                                                               */
+  PD_TYP_TYP5_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP5_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP5_Enum;
+
+/* ==================================================  PD TYP TYP4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP4                                                               */
+  PD_TYP_TYP4_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP4_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP4_Enum;
+
+/* ==================================================  PD TYP TYP3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP3                                                               */
+  PD_TYP_TYP3_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP3_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP3_Enum;
+
+/* ==================================================  PD TYP TYP2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP2                                                               */
+  PD_TYP_TYP2_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP2_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP2_Enum;
+
+/* ==================================================  PD TYP TYP1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP1                                                               */
+  PD_TYP_TYP1_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP1_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP1_Enum;
+
+/* ==================================================  PD TYP TYP0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PD_TYP_TYP0                                                               */
+  PD_TYP_TYP0_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PD_TYP_TYP0_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PD_TYP_TYP0_Enum;
+
+/* =========================================================  AFSR1  ========================================================= */
+/* ================================================  PD AFSR1 AFSR7 [28..31]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR1_AFSR7                                                            */
+  PD_AFSR1_AFSR7_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR1_AFSR7_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR1_AFSR7_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR1_AFSR7_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR1_AFSR7_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR1_AFSR7_Enum;
+
+/* ================================================  PD AFSR1 AFSR6 [24..27]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR1_AFSR6                                                            */
+  PD_AFSR1_AFSR6_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR1_AFSR6_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR1_AFSR6_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR1_AFSR6_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR1_AFSR6_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR1_AFSR6_Enum;
+
+/* ================================================  PD AFSR1 AFSR5 [20..23]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR1_AFSR5                                                            */
+  PD_AFSR1_AFSR5_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR1_AFSR5_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR1_AFSR5_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR1_AFSR5_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR1_AFSR5_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR1_AFSR5_Enum;
+
+/* ================================================  PD AFSR1 AFSR4 [16..19]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR1_AFSR4                                                            */
+  PD_AFSR1_AFSR4_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR1_AFSR4_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR1_AFSR4_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR1_AFSR4_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR1_AFSR4_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR1_AFSR4_Enum;
+
+/* ================================================  PD AFSR1 AFSR3 [12..15]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR1_AFSR3                                                            */
+  PD_AFSR1_AFSR3_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR1_AFSR3_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR1_AFSR3_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR1_AFSR3_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR1_AFSR3_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR1_AFSR3_Enum;
+
+/* ================================================  PD AFSR1 AFSR2 [8..11]  ================================================= */
+typedef enum {                                  /*!< PD_AFSR1_AFSR2                                                            */
+  PD_AFSR1_AFSR2_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR1_AFSR2_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR1_AFSR2_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR1_AFSR2_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR1_AFSR2_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR1_AFSR2_Enum;
+
+/* =================================================  PD AFSR1 AFSR1 [4..7]  ================================================= */
+typedef enum {                                  /*!< PD_AFSR1_AFSR1                                                            */
+  PD_AFSR1_AFSR1_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR1_AFSR1_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR1_AFSR1_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR1_AFSR1_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR1_AFSR1_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR1_AFSR1_Enum;
+
+/* =================================================  PD AFSR1 AFSR0 [0..3]  ================================================= */
+typedef enum {                                  /*!< PD_AFSR1_AFSR0                                                            */
+  PD_AFSR1_AFSR0_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR1_AFSR0_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR1_AFSR0_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR1_AFSR0_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR1_AFSR0_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR1_AFSR0_Enum;
+
+/* =========================================================  AFSR2  ========================================================= */
+/* ===============================================  PD AFSR2 AFSR15 [28..31]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR2_AFSR15                                                           */
+  PD_AFSR2_AFSR15_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR2_AFSR15_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR2_AFSR15_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR2_AFSR15_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR2_AFSR15_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR2_AFSR15_Enum;
+
+/* ===============================================  PD AFSR2 AFSR14 [24..27]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR2_AFSR14                                                           */
+  PD_AFSR2_AFSR14_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR2_AFSR14_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR2_AFSR14_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR2_AFSR14_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR2_AFSR14_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR2_AFSR14_Enum;
+
+/* ===============================================  PD AFSR2 AFSR13 [20..23]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR2_AFSR13                                                           */
+  PD_AFSR2_AFSR13_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR2_AFSR13_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR2_AFSR13_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR2_AFSR13_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR2_AFSR13_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR2_AFSR13_Enum;
+
+/* ===============================================  PD AFSR2 AFSR12 [16..19]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR2_AFSR12                                                           */
+  PD_AFSR2_AFSR12_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR2_AFSR12_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR2_AFSR12_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR2_AFSR12_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR2_AFSR12_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR2_AFSR12_Enum;
+
+/* ===============================================  PD AFSR2 AFSR11 [12..15]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR2_AFSR11                                                           */
+  PD_AFSR2_AFSR11_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR2_AFSR11_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR2_AFSR11_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR2_AFSR11_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR2_AFSR11_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR2_AFSR11_Enum;
+
+/* ================================================  PD AFSR2 AFSR10 [8..11]  ================================================ */
+typedef enum {                                  /*!< PD_AFSR2_AFSR10                                                           */
+  PD_AFSR2_AFSR10_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR2_AFSR10_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR2_AFSR10_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR2_AFSR10_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR2_AFSR10_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR2_AFSR10_Enum;
+
+/* =================================================  PD AFSR2 AFSR9 [4..7]  ================================================= */
+typedef enum {                                  /*!< PD_AFSR2_AFSR9                                                            */
+  PD_AFSR2_AFSR9_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR2_AFSR9_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR2_AFSR9_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR2_AFSR9_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR2_AFSR9_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR2_AFSR9_Enum;
+
+/* =================================================  PD AFSR2 AFSR8 [0..3]  ================================================= */
+typedef enum {                                  /*!< PD_AFSR2_AFSR8                                                            */
+  PD_AFSR2_AFSR8_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PD_AFSR2_AFSR8_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PD_AFSR2_AFSR8_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PD_AFSR2_AFSR8_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PD_AFSR2_AFSR8_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PD_AFSR2_AFSR8_Enum;
+
+/* =========================================================  PUPD  ========================================================== */
+/* ================================================  PD PUPD PUPD15 [30..31]  ================================================ */
+typedef enum {                                  /*!< PD_PUPD_PUPD15                                                            */
+  PD_PUPD_PUPD15_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD15_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD15_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD15_Enum;
+
+/* ================================================  PD PUPD PUPD14 [28..29]  ================================================ */
+typedef enum {                                  /*!< PD_PUPD_PUPD14                                                            */
+  PD_PUPD_PUPD14_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD14_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD14_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD14_Enum;
+
+/* ================================================  PD PUPD PUPD13 [26..27]  ================================================ */
+typedef enum {                                  /*!< PD_PUPD_PUPD13                                                            */
+  PD_PUPD_PUPD13_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD13_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD13_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD13_Enum;
+
+/* ================================================  PD PUPD PUPD12 [24..25]  ================================================ */
+typedef enum {                                  /*!< PD_PUPD_PUPD12                                                            */
+  PD_PUPD_PUPD12_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD12_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD12_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD12_Enum;
+
+/* ================================================  PD PUPD PUPD11 [22..23]  ================================================ */
+typedef enum {                                  /*!< PD_PUPD_PUPD11                                                            */
+  PD_PUPD_PUPD11_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD11_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD11_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD11_Enum;
+
+/* ================================================  PD PUPD PUPD10 [20..21]  ================================================ */
+typedef enum {                                  /*!< PD_PUPD_PUPD10                                                            */
+  PD_PUPD_PUPD10_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD10_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD10_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD10_Enum;
+
+/* ================================================  PD PUPD PUPD9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PD_PUPD_PUPD9                                                             */
+  PD_PUPD_PUPD9_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD9_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD9_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD9_Enum;
+
+/* ================================================  PD PUPD PUPD8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PD_PUPD_PUPD8                                                             */
+  PD_PUPD_PUPD8_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD8_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD8_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD8_Enum;
+
+/* ================================================  PD PUPD PUPD7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PD_PUPD_PUPD7                                                             */
+  PD_PUPD_PUPD7_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD7_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD7_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD7_Enum;
+
+/* ================================================  PD PUPD PUPD6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PD_PUPD_PUPD6                                                             */
+  PD_PUPD_PUPD6_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD6_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD6_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD6_Enum;
+
+/* ================================================  PD PUPD PUPD5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PD_PUPD_PUPD5                                                             */
+  PD_PUPD_PUPD5_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD5_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD5_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD5_Enum;
+
+/* =================================================  PD PUPD PUPD4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PD_PUPD_PUPD4                                                             */
+  PD_PUPD_PUPD4_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD4_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD4_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD4_Enum;
+
+/* =================================================  PD PUPD PUPD3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PD_PUPD_PUPD3                                                             */
+  PD_PUPD_PUPD3_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD3_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD3_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD3_Enum;
+
+/* =================================================  PD PUPD PUPD2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PD_PUPD_PUPD2                                                             */
+  PD_PUPD_PUPD2_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD2_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD2_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD2_Enum;
+
+/* =================================================  PD PUPD PUPD1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PD_PUPD_PUPD1                                                             */
+  PD_PUPD_PUPD1_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD1_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD1_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD1_Enum;
+
+/* =================================================  PD PUPD PUPD0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PD_PUPD_PUPD0                                                             */
+  PD_PUPD_PUPD0_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PD_PUPD_PUPD0_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PD_PUPD_PUPD0_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PD_PUPD_PUPD0_Enum;
+
+/* =========================================================  INDR  ========================================================== */
+/* =========================================================  OUTDR  ========================================================= */
+/* ==========================================================  BSR  ========================================================== */
+/* =================================================  PD BSR BSR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PD_BSR_BSR15                                                              */
+  PD_BSR_BSR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR15_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR15_Enum;
+
+/* =================================================  PD BSR BSR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PD_BSR_BSR14                                                              */
+  PD_BSR_BSR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR14_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR14_Enum;
+
+/* =================================================  PD BSR BSR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PD_BSR_BSR13                                                              */
+  PD_BSR_BSR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR13_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR13_Enum;
+
+/* =================================================  PD BSR BSR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PD_BSR_BSR12                                                              */
+  PD_BSR_BSR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR12_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR12_Enum;
+
+/* =================================================  PD BSR BSR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PD_BSR_BSR11                                                              */
+  PD_BSR_BSR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR11_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR11_Enum;
+
+/* =================================================  PD BSR BSR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PD_BSR_BSR10                                                              */
+  PD_BSR_BSR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR10_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR10_Enum;
+
+/* ==================================================  PD BSR BSR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR9                                                               */
+  PD_BSR_BSR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR9_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR9_Enum;
+
+/* ==================================================  PD BSR BSR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR8                                                               */
+  PD_BSR_BSR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR8_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR8_Enum;
+
+/* ==================================================  PD BSR BSR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR7                                                               */
+  PD_BSR_BSR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR7_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR7_Enum;
+
+/* ==================================================  PD BSR BSR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR6                                                               */
+  PD_BSR_BSR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR6_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR6_Enum;
+
+/* ==================================================  PD BSR BSR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR5                                                               */
+  PD_BSR_BSR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR5_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR5_Enum;
+
+/* ==================================================  PD BSR BSR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR4                                                               */
+  PD_BSR_BSR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR4_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR4_Enum;
+
+/* ==================================================  PD BSR BSR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR3                                                               */
+  PD_BSR_BSR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR3_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR3_Enum;
+
+/* ==================================================  PD BSR BSR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR2                                                               */
+  PD_BSR_BSR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR2_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR2_Enum;
+
+/* ==================================================  PD BSR BSR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR1                                                               */
+  PD_BSR_BSR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR1_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR1_Enum;
+
+/* ==================================================  PD BSR BSR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PD_BSR_BSR0                                                               */
+  PD_BSR_BSR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BSR_BSR0_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BSR_BSR0_Enum;
+
+/* ==========================================================  BCR  ========================================================== */
+/* =================================================  PD BCR BCR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PD_BCR_BCR15                                                              */
+  PD_BCR_BCR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR15_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR15_Enum;
+
+/* =================================================  PD BCR BCR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PD_BCR_BCR14                                                              */
+  PD_BCR_BCR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR14_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR14_Enum;
+
+/* =================================================  PD BCR BCR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PD_BCR_BCR13                                                              */
+  PD_BCR_BCR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR13_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR13_Enum;
+
+/* =================================================  PD BCR BCR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PD_BCR_BCR12                                                              */
+  PD_BCR_BCR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR12_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR12_Enum;
+
+/* =================================================  PD BCR BCR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PD_BCR_BCR11                                                              */
+  PD_BCR_BCR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR11_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR11_Enum;
+
+/* =================================================  PD BCR BCR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PD_BCR_BCR10                                                              */
+  PD_BCR_BCR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR10_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR10_Enum;
+
+/* ==================================================  PD BCR BCR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR9                                                               */
+  PD_BCR_BCR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR9_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR9_Enum;
+
+/* ==================================================  PD BCR BCR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR8                                                               */
+  PD_BCR_BCR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR8_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR8_Enum;
+
+/* ==================================================  PD BCR BCR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR7                                                               */
+  PD_BCR_BCR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR7_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR7_Enum;
+
+/* ==================================================  PD BCR BCR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR6                                                               */
+  PD_BCR_BCR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR6_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR6_Enum;
+
+/* ==================================================  PD BCR BCR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR5                                                               */
+  PD_BCR_BCR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR5_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR5_Enum;
+
+/* ==================================================  PD BCR BCR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR4                                                               */
+  PD_BCR_BCR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR4_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR4_Enum;
+
+/* ==================================================  PD BCR BCR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR3                                                               */
+  PD_BCR_BCR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR3_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR3_Enum;
+
+/* ==================================================  PD BCR BCR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR2                                                               */
+  PD_BCR_BCR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR2_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR2_Enum;
+
+/* ==================================================  PD BCR BCR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR1                                                               */
+  PD_BCR_BCR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR1_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR1_Enum;
+
+/* ==================================================  PD BCR BCR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PD_BCR_BCR0                                                               */
+  PD_BCR_BCR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PD_BCR_BCR0_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PD_BCR_BCR0_Enum;
+
+/* ========================================================  OUTDMSK  ======================================================== */
+/* =============================================  PD OUTDMSK OUTDMSK15 [15..15]  ============================================= */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK15                                                      */
+  PD_OUTDMSK_OUTDMSK15_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK15_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK15_Enum;
+
+/* =============================================  PD OUTDMSK OUTDMSK14 [14..14]  ============================================= */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK14                                                      */
+  PD_OUTDMSK_OUTDMSK14_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK14_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK14_Enum;
+
+/* =============================================  PD OUTDMSK OUTDMSK13 [13..13]  ============================================= */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK13                                                      */
+  PD_OUTDMSK_OUTDMSK13_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK13_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK13_Enum;
+
+/* =============================================  PD OUTDMSK OUTDMSK12 [12..12]  ============================================= */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK12                                                      */
+  PD_OUTDMSK_OUTDMSK12_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK12_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK12_Enum;
+
+/* =============================================  PD OUTDMSK OUTDMSK11 [11..11]  ============================================= */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK11                                                      */
+  PD_OUTDMSK_OUTDMSK11_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK11_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK11_Enum;
+
+/* =============================================  PD OUTDMSK OUTDMSK10 [10..10]  ============================================= */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK10                                                      */
+  PD_OUTDMSK_OUTDMSK10_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK10_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK10_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK9 [9..9]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK9                                                       */
+  PD_OUTDMSK_OUTDMSK9_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK9_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK9_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK8 [8..8]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK8                                                       */
+  PD_OUTDMSK_OUTDMSK8_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK8_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK8_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK7 [7..7]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK7                                                       */
+  PD_OUTDMSK_OUTDMSK7_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK7_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK7_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK6 [6..6]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK6                                                       */
+  PD_OUTDMSK_OUTDMSK6_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK6_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK6_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK5 [5..5]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK5                                                       */
+  PD_OUTDMSK_OUTDMSK5_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK5_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK5_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK4 [4..4]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK4                                                       */
+  PD_OUTDMSK_OUTDMSK4_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK4_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK4_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK3 [3..3]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK3                                                       */
+  PD_OUTDMSK_OUTDMSK3_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK3_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK3_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK2 [2..2]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK2                                                       */
+  PD_OUTDMSK_OUTDMSK2_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK2_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK2_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK1 [1..1]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK1                                                       */
+  PD_OUTDMSK_OUTDMSK1_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK1_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK1_Enum;
+
+/* ==============================================  PD OUTDMSK OUTDMSK0 [0..0]  =============================================== */
+typedef enum {                                  /*!< PD_OUTDMSK_OUTDMSK0                                                       */
+  PD_OUTDMSK_OUTDMSK0_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PD_OUTDMSK_OUTDMSK0_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PD_OUTDMSK_OUTDMSK0_Enum;
+
+/* =========================================================  DBCR  ========================================================== */
+/* ================================================  PD DBCR DBCLK [16..18]  ================================================= */
+typedef enum {                                  /*!< PD_DBCR_DBCLK                                                             */
+  PD_DBCR_DBCLK_HCLK1                  = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  PD_DBCR_DBCLK_HCLK4                  = 1,     /*!< HCLK4 : HCLK/4                                                            */
+  PD_DBCR_DBCLK_HCLK16                 = 2,     /*!< HCLK16 : HCLK/16                                                          */
+  PD_DBCR_DBCLK_HCLK64                 = 3,     /*!< HCLK64 : HCLK/64                                                          */
+  PD_DBCR_DBCLK_HCLK256                = 4,     /*!< HCLK256 : HCLK/256                                                        */
+  PD_DBCR_DBCLK_HCLK1024               = 5,     /*!< HCLK1024 : HCLK/1024                                                      */
+} PD_DBCR_DBCLK_Enum;
+
+/* ================================================  PD DBCR DBEN11 [11..11]  ================================================ */
+typedef enum {                                  /*!< PD_DBCR_DBEN11                                                            */
+  PD_DBCR_DBEN11_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN11_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN11_Enum;
+
+/* ================================================  PD DBCR DBEN10 [10..10]  ================================================ */
+typedef enum {                                  /*!< PD_DBCR_DBEN10                                                            */
+  PD_DBCR_DBEN10_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN10_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN10_Enum;
+
+/* =================================================  PD DBCR DBEN9 [9..9]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN9                                                             */
+  PD_DBCR_DBEN9_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN9_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN9_Enum;
+
+/* =================================================  PD DBCR DBEN8 [8..8]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN8                                                             */
+  PD_DBCR_DBEN8_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN8_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN8_Enum;
+
+/* =================================================  PD DBCR DBEN7 [7..7]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN7                                                             */
+  PD_DBCR_DBEN7_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN7_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN7_Enum;
+
+/* =================================================  PD DBCR DBEN6 [6..6]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN6                                                             */
+  PD_DBCR_DBEN6_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN6_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN6_Enum;
+
+/* =================================================  PD DBCR DBEN5 [5..5]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN5                                                             */
+  PD_DBCR_DBEN5_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN5_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN5_Enum;
+
+/* =================================================  PD DBCR DBEN4 [4..4]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN4                                                             */
+  PD_DBCR_DBEN4_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN4_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN4_Enum;
+
+/* =================================================  PD DBCR DBEN3 [3..3]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN3                                                             */
+  PD_DBCR_DBEN3_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN3_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN3_Enum;
+
+/* =================================================  PD DBCR DBEN2 [2..2]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN2                                                             */
+  PD_DBCR_DBEN2_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN2_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN2_Enum;
+
+/* =================================================  PD DBCR DBEN1 [1..1]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN1                                                             */
+  PD_DBCR_DBEN1_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN1_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN1_Enum;
+
+/* =================================================  PD DBCR DBEN0 [0..0]  ================================================== */
+typedef enum {                                  /*!< PD_DBCR_DBEN0                                                             */
+  PD_DBCR_DBEN0_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PD_DBCR_DBEN0_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PD_DBCR_DBEN0_Enum;
+
+/* ========================================================  PD_MOD  ========================================================= */
+/* ========================================================  PD_TYP  ========================================================= */
+/* =======================================================  PD_AFSR1  ======================================================== */
+/* =======================================================  PD_AFSR2  ======================================================== */
+/* ========================================================  PD_PUPD  ======================================================== */
+/* ========================================================  PD_INDR  ======================================================== */
+/* =======================================================  PD_OUTDR  ======================================================== */
+/* ========================================================  PD_BSR  ========================================================= */
+/* ========================================================  PD_BCR  ========================================================= */
+/* ======================================================  PD_OUTDMSK  ======================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PE                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+/* ================================================  PE MOD MODE15 [30..31]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE15                                                             */
+  PE_MOD_MODE15_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE15_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE15_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE15_Enum;
+
+/* ================================================  PE MOD MODE14 [28..29]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE14                                                             */
+  PE_MOD_MODE14_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE14_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE14_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE14_Enum;
+
+/* ================================================  PE MOD MODE13 [26..27]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE13                                                             */
+  PE_MOD_MODE13_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE13_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE13_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE13_Enum;
+
+/* ================================================  PE MOD MODE12 [24..25]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE12                                                             */
+  PE_MOD_MODE12_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE12_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE12_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE12_Enum;
+
+/* ================================================  PE MOD MODE11 [22..23]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE11                                                             */
+  PE_MOD_MODE11_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE11_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE11_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE11_Enum;
+
+/* ================================================  PE MOD MODE10 [20..21]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE10                                                             */
+  PE_MOD_MODE10_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE10_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE10_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE10_Enum;
+
+/* =================================================  PE MOD MODE9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE9                                                              */
+  PE_MOD_MODE9_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE9_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE9_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE9_Enum;
+
+/* =================================================  PE MOD MODE8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE8                                                              */
+  PE_MOD_MODE8_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE8_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE8_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE8_Enum;
+
+/* =================================================  PE MOD MODE7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE7                                                              */
+  PE_MOD_MODE7_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE7_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE7_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE7_Enum;
+
+/* =================================================  PE MOD MODE6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE6                                                              */
+  PE_MOD_MODE6_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE6_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE6_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE6_Enum;
+
+/* =================================================  PE MOD MODE5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PE_MOD_MODE5                                                              */
+  PE_MOD_MODE5_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE5_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE5_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE5_Enum;
+
+/* ==================================================  PE MOD MODE4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PE_MOD_MODE4                                                              */
+  PE_MOD_MODE4_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE4_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE4_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE4_Enum;
+
+/* ==================================================  PE MOD MODE3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PE_MOD_MODE3                                                              */
+  PE_MOD_MODE3_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE3_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE3_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE3_Enum;
+
+/* ==================================================  PE MOD MODE2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PE_MOD_MODE2                                                              */
+  PE_MOD_MODE2_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE2_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE2_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE2_Enum;
+
+/* ==================================================  PE MOD MODE1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PE_MOD_MODE1                                                              */
+  PE_MOD_MODE1_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE1_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE1_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE1_Enum;
+
+/* ==================================================  PE MOD MODE0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PE_MOD_MODE0                                                              */
+  PE_MOD_MODE0_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PE_MOD_MODE0_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PE_MOD_MODE0_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PE_MOD_MODE0_Enum;
+
+/* ==========================================================  TYP  ========================================================== */
+/* =================================================  PE TYP TYP15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PE_TYP_TYP15                                                              */
+  PE_TYP_TYP15_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP15_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP15_Enum;
+
+/* =================================================  PE TYP TYP14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PE_TYP_TYP14                                                              */
+  PE_TYP_TYP14_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP14_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP14_Enum;
+
+/* =================================================  PE TYP TYP13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PE_TYP_TYP13                                                              */
+  PE_TYP_TYP13_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP13_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP13_Enum;
+
+/* =================================================  PE TYP TYP12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PE_TYP_TYP12                                                              */
+  PE_TYP_TYP12_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP12_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP12_Enum;
+
+/* =================================================  PE TYP TYP11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PE_TYP_TYP11                                                              */
+  PE_TYP_TYP11_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP11_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP11_Enum;
+
+/* =================================================  PE TYP TYP10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PE_TYP_TYP10                                                              */
+  PE_TYP_TYP10_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP10_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP10_Enum;
+
+/* ==================================================  PE TYP TYP9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP9                                                               */
+  PE_TYP_TYP9_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP9_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP9_Enum;
+
+/* ==================================================  PE TYP TYP8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP8                                                               */
+  PE_TYP_TYP8_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP8_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP8_Enum;
+
+/* ==================================================  PE TYP TYP7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP7                                                               */
+  PE_TYP_TYP7_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP7_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP7_Enum;
+
+/* ==================================================  PE TYP TYP6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP6                                                               */
+  PE_TYP_TYP6_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP6_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP6_Enum;
+
+/* ==================================================  PE TYP TYP5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP5                                                               */
+  PE_TYP_TYP5_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP5_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP5_Enum;
+
+/* ==================================================  PE TYP TYP4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP4                                                               */
+  PE_TYP_TYP4_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP4_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP4_Enum;
+
+/* ==================================================  PE TYP TYP3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP3                                                               */
+  PE_TYP_TYP3_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP3_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP3_Enum;
+
+/* ==================================================  PE TYP TYP2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP2                                                               */
+  PE_TYP_TYP2_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP2_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP2_Enum;
+
+/* ==================================================  PE TYP TYP1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP1                                                               */
+  PE_TYP_TYP1_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP1_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP1_Enum;
+
+/* ==================================================  PE TYP TYP0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PE_TYP_TYP0                                                               */
+  PE_TYP_TYP0_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PE_TYP_TYP0_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PE_TYP_TYP0_Enum;
+
+/* =========================================================  AFSR1  ========================================================= */
+/* ================================================  PE AFSR1 AFSR7 [28..31]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR1_AFSR7                                                            */
+  PE_AFSR1_AFSR7_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR1_AFSR7_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR1_AFSR7_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR1_AFSR7_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR1_AFSR7_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR1_AFSR7_Enum;
+
+/* ================================================  PE AFSR1 AFSR6 [24..27]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR1_AFSR6                                                            */
+  PE_AFSR1_AFSR6_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR1_AFSR6_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR1_AFSR6_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR1_AFSR6_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR1_AFSR6_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR1_AFSR6_Enum;
+
+/* ================================================  PE AFSR1 AFSR5 [20..23]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR1_AFSR5                                                            */
+  PE_AFSR1_AFSR5_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR1_AFSR5_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR1_AFSR5_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR1_AFSR5_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR1_AFSR5_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR1_AFSR5_Enum;
+
+/* ================================================  PE AFSR1 AFSR4 [16..19]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR1_AFSR4                                                            */
+  PE_AFSR1_AFSR4_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR1_AFSR4_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR1_AFSR4_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR1_AFSR4_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR1_AFSR4_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR1_AFSR4_Enum;
+
+/* ================================================  PE AFSR1 AFSR3 [12..15]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR1_AFSR3                                                            */
+  PE_AFSR1_AFSR3_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR1_AFSR3_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR1_AFSR3_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR1_AFSR3_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR1_AFSR3_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR1_AFSR3_Enum;
+
+/* ================================================  PE AFSR1 AFSR2 [8..11]  ================================================= */
+typedef enum {                                  /*!< PE_AFSR1_AFSR2                                                            */
+  PE_AFSR1_AFSR2_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR1_AFSR2_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR1_AFSR2_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR1_AFSR2_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR1_AFSR2_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR1_AFSR2_Enum;
+
+/* =================================================  PE AFSR1 AFSR1 [4..7]  ================================================= */
+typedef enum {                                  /*!< PE_AFSR1_AFSR1                                                            */
+  PE_AFSR1_AFSR1_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR1_AFSR1_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR1_AFSR1_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR1_AFSR1_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR1_AFSR1_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR1_AFSR1_Enum;
+
+/* =================================================  PE AFSR1 AFSR0 [0..3]  ================================================= */
+typedef enum {                                  /*!< PE_AFSR1_AFSR0                                                            */
+  PE_AFSR1_AFSR0_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR1_AFSR0_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR1_AFSR0_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR1_AFSR0_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR1_AFSR0_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR1_AFSR0_Enum;
+
+/* =========================================================  AFSR2  ========================================================= */
+/* ===============================================  PE AFSR2 AFSR15 [28..31]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR2_AFSR15                                                           */
+  PE_AFSR2_AFSR15_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR2_AFSR15_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR2_AFSR15_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR2_AFSR15_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR2_AFSR15_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR2_AFSR15_Enum;
+
+/* ===============================================  PE AFSR2 AFSR14 [24..27]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR2_AFSR14                                                           */
+  PE_AFSR2_AFSR14_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR2_AFSR14_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR2_AFSR14_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR2_AFSR14_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR2_AFSR14_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR2_AFSR14_Enum;
+
+/* ===============================================  PE AFSR2 AFSR13 [20..23]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR2_AFSR13                                                           */
+  PE_AFSR2_AFSR13_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR2_AFSR13_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR2_AFSR13_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR2_AFSR13_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR2_AFSR13_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR2_AFSR13_Enum;
+
+/* ===============================================  PE AFSR2 AFSR12 [16..19]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR2_AFSR12                                                           */
+  PE_AFSR2_AFSR12_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR2_AFSR12_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR2_AFSR12_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR2_AFSR12_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR2_AFSR12_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR2_AFSR12_Enum;
+
+/* ===============================================  PE AFSR2 AFSR11 [12..15]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR2_AFSR11                                                           */
+  PE_AFSR2_AFSR11_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR2_AFSR11_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR2_AFSR11_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR2_AFSR11_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR2_AFSR11_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR2_AFSR11_Enum;
+
+/* ================================================  PE AFSR2 AFSR10 [8..11]  ================================================ */
+typedef enum {                                  /*!< PE_AFSR2_AFSR10                                                           */
+  PE_AFSR2_AFSR10_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR2_AFSR10_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR2_AFSR10_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR2_AFSR10_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR2_AFSR10_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR2_AFSR10_Enum;
+
+/* =================================================  PE AFSR2 AFSR9 [4..7]  ================================================= */
+typedef enum {                                  /*!< PE_AFSR2_AFSR9                                                            */
+  PE_AFSR2_AFSR9_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR2_AFSR9_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR2_AFSR9_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR2_AFSR9_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR2_AFSR9_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR2_AFSR9_Enum;
+
+/* =================================================  PE AFSR2 AFSR8 [0..3]  ================================================= */
+typedef enum {                                  /*!< PE_AFSR2_AFSR8                                                            */
+  PE_AFSR2_AFSR8_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PE_AFSR2_AFSR8_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PE_AFSR2_AFSR8_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PE_AFSR2_AFSR8_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PE_AFSR2_AFSR8_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PE_AFSR2_AFSR8_Enum;
+
+/* =========================================================  PUPD  ========================================================== */
+/* ================================================  PE PUPD PUPD15 [30..31]  ================================================ */
+typedef enum {                                  /*!< PE_PUPD_PUPD15                                                            */
+  PE_PUPD_PUPD15_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD15_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD15_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD15_Enum;
+
+/* ================================================  PE PUPD PUPD14 [28..29]  ================================================ */
+typedef enum {                                  /*!< PE_PUPD_PUPD14                                                            */
+  PE_PUPD_PUPD14_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD14_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD14_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD14_Enum;
+
+/* ================================================  PE PUPD PUPD13 [26..27]  ================================================ */
+typedef enum {                                  /*!< PE_PUPD_PUPD13                                                            */
+  PE_PUPD_PUPD13_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD13_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD13_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD13_Enum;
+
+/* ================================================  PE PUPD PUPD12 [24..25]  ================================================ */
+typedef enum {                                  /*!< PE_PUPD_PUPD12                                                            */
+  PE_PUPD_PUPD12_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD12_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD12_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD12_Enum;
+
+/* ================================================  PE PUPD PUPD11 [22..23]  ================================================ */
+typedef enum {                                  /*!< PE_PUPD_PUPD11                                                            */
+  PE_PUPD_PUPD11_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD11_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD11_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD11_Enum;
+
+/* ================================================  PE PUPD PUPD10 [20..21]  ================================================ */
+typedef enum {                                  /*!< PE_PUPD_PUPD10                                                            */
+  PE_PUPD_PUPD10_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD10_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD10_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD10_Enum;
+
+/* ================================================  PE PUPD PUPD9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PE_PUPD_PUPD9                                                             */
+  PE_PUPD_PUPD9_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD9_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD9_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD9_Enum;
+
+/* ================================================  PE PUPD PUPD8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PE_PUPD_PUPD8                                                             */
+  PE_PUPD_PUPD8_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD8_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD8_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD8_Enum;
+
+/* ================================================  PE PUPD PUPD7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PE_PUPD_PUPD7                                                             */
+  PE_PUPD_PUPD7_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD7_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD7_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD7_Enum;
+
+/* ================================================  PE PUPD PUPD6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PE_PUPD_PUPD6                                                             */
+  PE_PUPD_PUPD6_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD6_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD6_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD6_Enum;
+
+/* ================================================  PE PUPD PUPD5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PE_PUPD_PUPD5                                                             */
+  PE_PUPD_PUPD5_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD5_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD5_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD5_Enum;
+
+/* =================================================  PE PUPD PUPD4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PE_PUPD_PUPD4                                                             */
+  PE_PUPD_PUPD4_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD4_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD4_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD4_Enum;
+
+/* =================================================  PE PUPD PUPD3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PE_PUPD_PUPD3                                                             */
+  PE_PUPD_PUPD3_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD3_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD3_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD3_Enum;
+
+/* =================================================  PE PUPD PUPD2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PE_PUPD_PUPD2                                                             */
+  PE_PUPD_PUPD2_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD2_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD2_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD2_Enum;
+
+/* =================================================  PE PUPD PUPD1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PE_PUPD_PUPD1                                                             */
+  PE_PUPD_PUPD1_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD1_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD1_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD1_Enum;
+
+/* =================================================  PE PUPD PUPD0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PE_PUPD_PUPD0                                                             */
+  PE_PUPD_PUPD0_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PE_PUPD_PUPD0_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PE_PUPD_PUPD0_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PE_PUPD_PUPD0_Enum;
+
+/* =========================================================  INDR  ========================================================== */
+/* =========================================================  OUTDR  ========================================================= */
+/* ==========================================================  BSR  ========================================================== */
+/* =================================================  PE BSR BSR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PE_BSR_BSR15                                                              */
+  PE_BSR_BSR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR15_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR15_Enum;
+
+/* =================================================  PE BSR BSR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PE_BSR_BSR14                                                              */
+  PE_BSR_BSR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR14_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR14_Enum;
+
+/* =================================================  PE BSR BSR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PE_BSR_BSR13                                                              */
+  PE_BSR_BSR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR13_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR13_Enum;
+
+/* =================================================  PE BSR BSR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PE_BSR_BSR12                                                              */
+  PE_BSR_BSR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR12_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR12_Enum;
+
+/* =================================================  PE BSR BSR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PE_BSR_BSR11                                                              */
+  PE_BSR_BSR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR11_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR11_Enum;
+
+/* =================================================  PE BSR BSR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PE_BSR_BSR10                                                              */
+  PE_BSR_BSR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR10_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR10_Enum;
+
+/* ==================================================  PE BSR BSR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR9                                                               */
+  PE_BSR_BSR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR9_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR9_Enum;
+
+/* ==================================================  PE BSR BSR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR8                                                               */
+  PE_BSR_BSR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR8_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR8_Enum;
+
+/* ==================================================  PE BSR BSR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR7                                                               */
+  PE_BSR_BSR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR7_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR7_Enum;
+
+/* ==================================================  PE BSR BSR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR6                                                               */
+  PE_BSR_BSR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR6_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR6_Enum;
+
+/* ==================================================  PE BSR BSR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR5                                                               */
+  PE_BSR_BSR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR5_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR5_Enum;
+
+/* ==================================================  PE BSR BSR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR4                                                               */
+  PE_BSR_BSR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR4_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR4_Enum;
+
+/* ==================================================  PE BSR BSR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR3                                                               */
+  PE_BSR_BSR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR3_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR3_Enum;
+
+/* ==================================================  PE BSR BSR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR2                                                               */
+  PE_BSR_BSR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR2_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR2_Enum;
+
+/* ==================================================  PE BSR BSR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR1                                                               */
+  PE_BSR_BSR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR1_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR1_Enum;
+
+/* ==================================================  PE BSR BSR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PE_BSR_BSR0                                                               */
+  PE_BSR_BSR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BSR_BSR0_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BSR_BSR0_Enum;
+
+/* ==========================================================  BCR  ========================================================== */
+/* =================================================  PE BCR BCR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PE_BCR_BCR15                                                              */
+  PE_BCR_BCR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR15_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR15_Enum;
+
+/* =================================================  PE BCR BCR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PE_BCR_BCR14                                                              */
+  PE_BCR_BCR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR14_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR14_Enum;
+
+/* =================================================  PE BCR BCR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PE_BCR_BCR13                                                              */
+  PE_BCR_BCR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR13_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR13_Enum;
+
+/* =================================================  PE BCR BCR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PE_BCR_BCR12                                                              */
+  PE_BCR_BCR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR12_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR12_Enum;
+
+/* =================================================  PE BCR BCR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PE_BCR_BCR11                                                              */
+  PE_BCR_BCR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR11_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR11_Enum;
+
+/* =================================================  PE BCR BCR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PE_BCR_BCR10                                                              */
+  PE_BCR_BCR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR10_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR10_Enum;
+
+/* ==================================================  PE BCR BCR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR9                                                               */
+  PE_BCR_BCR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR9_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR9_Enum;
+
+/* ==================================================  PE BCR BCR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR8                                                               */
+  PE_BCR_BCR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR8_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR8_Enum;
+
+/* ==================================================  PE BCR BCR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR7                                                               */
+  PE_BCR_BCR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR7_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR7_Enum;
+
+/* ==================================================  PE BCR BCR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR6                                                               */
+  PE_BCR_BCR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR6_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR6_Enum;
+
+/* ==================================================  PE BCR BCR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR5                                                               */
+  PE_BCR_BCR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR5_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR5_Enum;
+
+/* ==================================================  PE BCR BCR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR4                                                               */
+  PE_BCR_BCR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR4_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR4_Enum;
+
+/* ==================================================  PE BCR BCR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR3                                                               */
+  PE_BCR_BCR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR3_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR3_Enum;
+
+/* ==================================================  PE BCR BCR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR2                                                               */
+  PE_BCR_BCR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR2_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR2_Enum;
+
+/* ==================================================  PE BCR BCR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR1                                                               */
+  PE_BCR_BCR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR1_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR1_Enum;
+
+/* ==================================================  PE BCR BCR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PE_BCR_BCR0                                                               */
+  PE_BCR_BCR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PE_BCR_BCR0_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PE_BCR_BCR0_Enum;
+
+/* ========================================================  OUTDMSK  ======================================================== */
+/* =============================================  PE OUTDMSK OUTDMSK15 [15..15]  ============================================= */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK15                                                      */
+  PE_OUTDMSK_OUTDMSK15_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK15_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK15_Enum;
+
+/* =============================================  PE OUTDMSK OUTDMSK14 [14..14]  ============================================= */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK14                                                      */
+  PE_OUTDMSK_OUTDMSK14_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK14_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK14_Enum;
+
+/* =============================================  PE OUTDMSK OUTDMSK13 [13..13]  ============================================= */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK13                                                      */
+  PE_OUTDMSK_OUTDMSK13_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK13_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK13_Enum;
+
+/* =============================================  PE OUTDMSK OUTDMSK12 [12..12]  ============================================= */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK12                                                      */
+  PE_OUTDMSK_OUTDMSK12_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK12_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK12_Enum;
+
+/* =============================================  PE OUTDMSK OUTDMSK11 [11..11]  ============================================= */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK11                                                      */
+  PE_OUTDMSK_OUTDMSK11_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK11_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK11_Enum;
+
+/* =============================================  PE OUTDMSK OUTDMSK10 [10..10]  ============================================= */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK10                                                      */
+  PE_OUTDMSK_OUTDMSK10_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK10_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK10_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK9 [9..9]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK9                                                       */
+  PE_OUTDMSK_OUTDMSK9_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK9_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK9_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK8 [8..8]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK8                                                       */
+  PE_OUTDMSK_OUTDMSK8_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK8_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK8_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK7 [7..7]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK7                                                       */
+  PE_OUTDMSK_OUTDMSK7_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK7_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK7_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK6 [6..6]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK6                                                       */
+  PE_OUTDMSK_OUTDMSK6_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK6_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK6_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK5 [5..5]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK5                                                       */
+  PE_OUTDMSK_OUTDMSK5_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK5_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK5_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK4 [4..4]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK4                                                       */
+  PE_OUTDMSK_OUTDMSK4_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK4_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK4_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK3 [3..3]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK3                                                       */
+  PE_OUTDMSK_OUTDMSK3_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK3_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK3_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK2 [2..2]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK2                                                       */
+  PE_OUTDMSK_OUTDMSK2_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK2_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK2_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK1 [1..1]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK1                                                       */
+  PE_OUTDMSK_OUTDMSK1_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK1_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK1_Enum;
+
+/* ==============================================  PE OUTDMSK OUTDMSK0 [0..0]  =============================================== */
+typedef enum {                                  /*!< PE_OUTDMSK_OUTDMSK0                                                       */
+  PE_OUTDMSK_OUTDMSK0_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PE_OUTDMSK_OUTDMSK0_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PE_OUTDMSK_OUTDMSK0_Enum;
+
+/* =========================================================  DBCR  ========================================================== */
+/* ================================================  PE DBCR DBCLK [16..18]  ================================================= */
+typedef enum {                                  /*!< PE_DBCR_DBCLK                                                             */
+  PE_DBCR_DBCLK_HCLK1                  = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  PE_DBCR_DBCLK_HCLK4                  = 1,     /*!< HCLK4 : HCLK/4                                                            */
+  PE_DBCR_DBCLK_HCLK16                 = 2,     /*!< HCLK16 : HCLK/16                                                          */
+  PE_DBCR_DBCLK_HCLK64                 = 3,     /*!< HCLK64 : HCLK/64                                                          */
+  PE_DBCR_DBCLK_HCLK256                = 4,     /*!< HCLK256 : HCLK/256                                                        */
+  PE_DBCR_DBCLK_HCLK1024               = 5,     /*!< HCLK1024 : HCLK/1024                                                      */
+} PE_DBCR_DBCLK_Enum;
+
+/* ================================================  PE DBCR DBEN11 [11..11]  ================================================ */
+typedef enum {                                  /*!< PE_DBCR_DBEN11                                                            */
+  PE_DBCR_DBEN11_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN11_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN11_Enum;
+
+/* ================================================  PE DBCR DBEN10 [10..10]  ================================================ */
+typedef enum {                                  /*!< PE_DBCR_DBEN10                                                            */
+  PE_DBCR_DBEN10_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN10_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN10_Enum;
+
+/* =================================================  PE DBCR DBEN9 [9..9]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN9                                                             */
+  PE_DBCR_DBEN9_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN9_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN9_Enum;
+
+/* =================================================  PE DBCR DBEN8 [8..8]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN8                                                             */
+  PE_DBCR_DBEN8_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN8_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN8_Enum;
+
+/* =================================================  PE DBCR DBEN7 [7..7]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN7                                                             */
+  PE_DBCR_DBEN7_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN7_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN7_Enum;
+
+/* =================================================  PE DBCR DBEN6 [6..6]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN6                                                             */
+  PE_DBCR_DBEN6_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN6_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN6_Enum;
+
+/* =================================================  PE DBCR DBEN5 [5..5]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN5                                                             */
+  PE_DBCR_DBEN5_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN5_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN5_Enum;
+
+/* =================================================  PE DBCR DBEN4 [4..4]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN4                                                             */
+  PE_DBCR_DBEN4_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN4_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN4_Enum;
+
+/* =================================================  PE DBCR DBEN3 [3..3]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN3                                                             */
+  PE_DBCR_DBEN3_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN3_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN3_Enum;
+
+/* =================================================  PE DBCR DBEN2 [2..2]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN2                                                             */
+  PE_DBCR_DBEN2_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN2_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN2_Enum;
+
+/* =================================================  PE DBCR DBEN1 [1..1]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN1                                                             */
+  PE_DBCR_DBEN1_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN1_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN1_Enum;
+
+/* =================================================  PE DBCR DBEN0 [0..0]  ================================================== */
+typedef enum {                                  /*!< PE_DBCR_DBEN0                                                             */
+  PE_DBCR_DBEN0_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PE_DBCR_DBEN0_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PE_DBCR_DBEN0_Enum;
+
+/* ========================================================  PE_MOD  ========================================================= */
+/* ========================================================  PE_TYP  ========================================================= */
+/* =======================================================  PE_AFSR1  ======================================================== */
+/* =======================================================  PE_AFSR2  ======================================================== */
+/* ========================================================  PE_PUPD  ======================================================== */
+/* ========================================================  PE_INDR  ======================================================== */
+/* =======================================================  PE_OUTDR  ======================================================== */
+/* ========================================================  PE_BSR  ========================================================= */
+/* ========================================================  PE_BCR  ========================================================= */
+/* ======================================================  PE_OUTDMSK  ======================================================= */
+/* ========================================================  PE_DBCR  ======================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                            PF                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+/* ================================================  PF MOD MODE15 [30..31]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE15                                                             */
+  PF_MOD_MODE15_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE15_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE15_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE15_Enum;
+
+/* ================================================  PF MOD MODE14 [28..29]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE14                                                             */
+  PF_MOD_MODE14_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE14_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE14_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE14_Enum;
+
+/* ================================================  PF MOD MODE13 [26..27]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE13                                                             */
+  PF_MOD_MODE13_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE13_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE13_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE13_Enum;
+
+/* ================================================  PF MOD MODE12 [24..25]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE12                                                             */
+  PF_MOD_MODE12_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE12_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE12_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE12_Enum;
+
+/* ================================================  PF MOD MODE11 [22..23]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE11                                                             */
+  PF_MOD_MODE11_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE11_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE11_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE11_Enum;
+
+/* ================================================  PF MOD MODE10 [20..21]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE10                                                             */
+  PF_MOD_MODE10_Input                  = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE10_Output                 = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE10_Alternative            = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE10_Enum;
+
+/* =================================================  PF MOD MODE9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE9                                                              */
+  PF_MOD_MODE9_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE9_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE9_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE9_Enum;
+
+/* =================================================  PF MOD MODE8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE8                                                              */
+  PF_MOD_MODE8_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE8_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE8_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE8_Enum;
+
+/* =================================================  PF MOD MODE7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE7                                                              */
+  PF_MOD_MODE7_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE7_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE7_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE7_Enum;
+
+/* =================================================  PF MOD MODE6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE6                                                              */
+  PF_MOD_MODE6_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE6_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE6_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE6_Enum;
+
+/* =================================================  PF MOD MODE5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PF_MOD_MODE5                                                              */
+  PF_MOD_MODE5_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE5_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE5_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE5_Enum;
+
+/* ==================================================  PF MOD MODE4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PF_MOD_MODE4                                                              */
+  PF_MOD_MODE4_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE4_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE4_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE4_Enum;
+
+/* ==================================================  PF MOD MODE3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PF_MOD_MODE3                                                              */
+  PF_MOD_MODE3_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE3_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE3_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE3_Enum;
+
+/* ==================================================  PF MOD MODE2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PF_MOD_MODE2                                                              */
+  PF_MOD_MODE2_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE2_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE2_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE2_Enum;
+
+/* ==================================================  PF MOD MODE1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PF_MOD_MODE1                                                              */
+  PF_MOD_MODE1_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE1_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE1_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE1_Enum;
+
+/* ==================================================  PF MOD MODE0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PF_MOD_MODE0                                                              */
+  PF_MOD_MODE0_Input                   = 0,     /*!< Input : Input Mode                                                        */
+  PF_MOD_MODE0_Output                  = 1,     /*!< Output : Output Mode                                                      */
+  PF_MOD_MODE0_Alternative             = 2,     /*!< Alternative : Alternative Function Mode                                   */
+} PF_MOD_MODE0_Enum;
+
+/* ==========================================================  TYP  ========================================================== */
+/* =================================================  PF TYP TYP15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PF_TYP_TYP15                                                              */
+  PF_TYP_TYP15_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP15_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP15_Enum;
+
+/* =================================================  PF TYP TYP14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PF_TYP_TYP14                                                              */
+  PF_TYP_TYP14_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP14_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP14_Enum;
+
+/* =================================================  PF TYP TYP13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PF_TYP_TYP13                                                              */
+  PF_TYP_TYP13_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP13_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP13_Enum;
+
+/* =================================================  PF TYP TYP12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PF_TYP_TYP12                                                              */
+  PF_TYP_TYP12_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP12_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP12_Enum;
+
+/* =================================================  PF TYP TYP11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PF_TYP_TYP11                                                              */
+  PF_TYP_TYP11_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP11_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP11_Enum;
+
+/* =================================================  PF TYP TYP10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PF_TYP_TYP10                                                              */
+  PF_TYP_TYP10_PushPull                = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP10_OpenDrain               = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP10_Enum;
+
+/* ==================================================  PF TYP TYP9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP9                                                               */
+  PF_TYP_TYP9_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP9_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP9_Enum;
+
+/* ==================================================  PF TYP TYP8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP8                                                               */
+  PF_TYP_TYP8_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP8_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP8_Enum;
+
+/* ==================================================  PF TYP TYP7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP7                                                               */
+  PF_TYP_TYP7_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP7_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP7_Enum;
+
+/* ==================================================  PF TYP TYP6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP6                                                               */
+  PF_TYP_TYP6_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP6_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP6_Enum;
+
+/* ==================================================  PF TYP TYP5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP5                                                               */
+  PF_TYP_TYP5_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP5_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP5_Enum;
+
+/* ==================================================  PF TYP TYP4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP4                                                               */
+  PF_TYP_TYP4_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP4_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP4_Enum;
+
+/* ==================================================  PF TYP TYP3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP3                                                               */
+  PF_TYP_TYP3_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP3_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP3_Enum;
+
+/* ==================================================  PF TYP TYP2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP2                                                               */
+  PF_TYP_TYP2_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP2_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP2_Enum;
+
+/* ==================================================  PF TYP TYP1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP1                                                               */
+  PF_TYP_TYP1_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP1_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP1_Enum;
+
+/* ==================================================  PF TYP TYP0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PF_TYP_TYP0                                                               */
+  PF_TYP_TYP0_PushPull                 = 0,     /*!< PushPull : Push-Pull Output                                               */
+  PF_TYP_TYP0_OpenDrain                = 1,     /*!< OpenDrain : Open-Drain Output                                             */
+} PF_TYP_TYP0_Enum;
+
+/* =========================================================  AFSR1  ========================================================= */
+/* ================================================  PF AFSR1 AFSR7 [28..31]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR1_AFSR7                                                            */
+  PF_AFSR1_AFSR7_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR1_AFSR7_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR1_AFSR7_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR1_AFSR7_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR1_AFSR7_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR1_AFSR7_Enum;
+
+/* ================================================  PF AFSR1 AFSR6 [24..27]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR1_AFSR6                                                            */
+  PF_AFSR1_AFSR6_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR1_AFSR6_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR1_AFSR6_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR1_AFSR6_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR1_AFSR6_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR1_AFSR6_Enum;
+
+/* ================================================  PF AFSR1 AFSR5 [20..23]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR1_AFSR5                                                            */
+  PF_AFSR1_AFSR5_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR1_AFSR5_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR1_AFSR5_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR1_AFSR5_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR1_AFSR5_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR1_AFSR5_Enum;
+
+/* ================================================  PF AFSR1 AFSR4 [16..19]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR1_AFSR4                                                            */
+  PF_AFSR1_AFSR4_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR1_AFSR4_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR1_AFSR4_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR1_AFSR4_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR1_AFSR4_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR1_AFSR4_Enum;
+
+/* ================================================  PF AFSR1 AFSR3 [12..15]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR1_AFSR3                                                            */
+  PF_AFSR1_AFSR3_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR1_AFSR3_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR1_AFSR3_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR1_AFSR3_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR1_AFSR3_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR1_AFSR3_Enum;
+
+/* ================================================  PF AFSR1 AFSR2 [8..11]  ================================================= */
+typedef enum {                                  /*!< PF_AFSR1_AFSR2                                                            */
+  PF_AFSR1_AFSR2_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR1_AFSR2_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR1_AFSR2_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR1_AFSR2_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR1_AFSR2_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR1_AFSR2_Enum;
+
+/* =================================================  PF AFSR1 AFSR1 [4..7]  ================================================= */
+typedef enum {                                  /*!< PF_AFSR1_AFSR1                                                            */
+  PF_AFSR1_AFSR1_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR1_AFSR1_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR1_AFSR1_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR1_AFSR1_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR1_AFSR1_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR1_AFSR1_Enum;
+
+/* =================================================  PF AFSR1 AFSR0 [0..3]  ================================================= */
+typedef enum {                                  /*!< PF_AFSR1_AFSR0                                                            */
+  PF_AFSR1_AFSR0_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR1_AFSR0_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR1_AFSR0_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR1_AFSR0_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR1_AFSR0_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR1_AFSR0_Enum;
+
+/* =========================================================  AFSR2  ========================================================= */
+/* ===============================================  PF AFSR2 AFSR15 [28..31]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR2_AFSR15                                                           */
+  PF_AFSR2_AFSR15_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR2_AFSR15_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR2_AFSR15_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR2_AFSR15_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR2_AFSR15_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR2_AFSR15_Enum;
+
+/* ===============================================  PF AFSR2 AFSR14 [24..27]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR2_AFSR14                                                           */
+  PF_AFSR2_AFSR14_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR2_AFSR14_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR2_AFSR14_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR2_AFSR14_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR2_AFSR14_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR2_AFSR14_Enum;
+
+/* ===============================================  PF AFSR2 AFSR13 [20..23]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR2_AFSR13                                                           */
+  PF_AFSR2_AFSR13_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR2_AFSR13_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR2_AFSR13_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR2_AFSR13_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR2_AFSR13_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR2_AFSR13_Enum;
+
+/* ===============================================  PF AFSR2 AFSR12 [16..19]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR2_AFSR12                                                           */
+  PF_AFSR2_AFSR12_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR2_AFSR12_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR2_AFSR12_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR2_AFSR12_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR2_AFSR12_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR2_AFSR12_Enum;
+
+/* ===============================================  PF AFSR2 AFSR11 [12..15]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR2_AFSR11                                                           */
+  PF_AFSR2_AFSR11_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR2_AFSR11_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR2_AFSR11_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR2_AFSR11_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR2_AFSR11_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR2_AFSR11_Enum;
+
+/* ================================================  PF AFSR2 AFSR10 [8..11]  ================================================ */
+typedef enum {                                  /*!< PF_AFSR2_AFSR10                                                           */
+  PF_AFSR2_AFSR10_AF0                  = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR2_AFSR10_AF1                  = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR2_AFSR10_AF2                  = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR2_AFSR10_AF3                  = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR2_AFSR10_AF4                  = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR2_AFSR10_Enum;
+
+/* =================================================  PF AFSR2 AFSR9 [4..7]  ================================================= */
+typedef enum {                                  /*!< PF_AFSR2_AFSR9                                                            */
+  PF_AFSR2_AFSR9_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR2_AFSR9_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR2_AFSR9_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR2_AFSR9_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR2_AFSR9_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR2_AFSR9_Enum;
+
+/* =================================================  PF AFSR2 AFSR8 [0..3]  ================================================= */
+typedef enum {                                  /*!< PF_AFSR2_AFSR8                                                            */
+  PF_AFSR2_AFSR8_AF0                   = 0,     /*!< AF0 : Alternative Function 0 (AF0)                                        */
+  PF_AFSR2_AFSR8_AF1                   = 1,     /*!< AF1 : Alternative Function 1 (AF1)                                        */
+  PF_AFSR2_AFSR8_AF2                   = 2,     /*!< AF2 : Alternative Function 2 (AF2)                                        */
+  PF_AFSR2_AFSR8_AF3                   = 3,     /*!< AF3 : Alternative Function 3 (AF3)                                        */
+  PF_AFSR2_AFSR8_AF4                   = 4,     /*!< AF4 : Alternative Function 4 (AF4)                                        */
+} PF_AFSR2_AFSR8_Enum;
+
+/* =========================================================  PUPD  ========================================================== */
+/* ================================================  PF PUPD PUPD15 [30..31]  ================================================ */
+typedef enum {                                  /*!< PF_PUPD_PUPD15                                                            */
+  PF_PUPD_PUPD15_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD15_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD15_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD15_Enum;
+
+/* ================================================  PF PUPD PUPD14 [28..29]  ================================================ */
+typedef enum {                                  /*!< PF_PUPD_PUPD14                                                            */
+  PF_PUPD_PUPD14_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD14_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD14_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD14_Enum;
+
+/* ================================================  PF PUPD PUPD13 [26..27]  ================================================ */
+typedef enum {                                  /*!< PF_PUPD_PUPD13                                                            */
+  PF_PUPD_PUPD13_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD13_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD13_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD13_Enum;
+
+/* ================================================  PF PUPD PUPD12 [24..25]  ================================================ */
+typedef enum {                                  /*!< PF_PUPD_PUPD12                                                            */
+  PF_PUPD_PUPD12_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD12_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD12_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD12_Enum;
+
+/* ================================================  PF PUPD PUPD11 [22..23]  ================================================ */
+typedef enum {                                  /*!< PF_PUPD_PUPD11                                                            */
+  PF_PUPD_PUPD11_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD11_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD11_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD11_Enum;
+
+/* ================================================  PF PUPD PUPD10 [20..21]  ================================================ */
+typedef enum {                                  /*!< PF_PUPD_PUPD10                                                            */
+  PF_PUPD_PUPD10_Disable               = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD10_EnablePU              = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD10_EnablePD              = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD10_Enum;
+
+/* ================================================  PF PUPD PUPD9 [18..19]  ================================================= */
+typedef enum {                                  /*!< PF_PUPD_PUPD9                                                             */
+  PF_PUPD_PUPD9_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD9_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD9_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD9_Enum;
+
+/* ================================================  PF PUPD PUPD8 [16..17]  ================================================= */
+typedef enum {                                  /*!< PF_PUPD_PUPD8                                                             */
+  PF_PUPD_PUPD8_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD8_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD8_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD8_Enum;
+
+/* ================================================  PF PUPD PUPD7 [14..15]  ================================================= */
+typedef enum {                                  /*!< PF_PUPD_PUPD7                                                             */
+  PF_PUPD_PUPD7_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD7_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD7_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD7_Enum;
+
+/* ================================================  PF PUPD PUPD6 [12..13]  ================================================= */
+typedef enum {                                  /*!< PF_PUPD_PUPD6                                                             */
+  PF_PUPD_PUPD6_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD6_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD6_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD6_Enum;
+
+/* ================================================  PF PUPD PUPD5 [10..11]  ================================================= */
+typedef enum {                                  /*!< PF_PUPD_PUPD5                                                             */
+  PF_PUPD_PUPD5_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD5_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD5_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD5_Enum;
+
+/* =================================================  PF PUPD PUPD4 [8..9]  ================================================== */
+typedef enum {                                  /*!< PF_PUPD_PUPD4                                                             */
+  PF_PUPD_PUPD4_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD4_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD4_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD4_Enum;
+
+/* =================================================  PF PUPD PUPD3 [6..7]  ================================================== */
+typedef enum {                                  /*!< PF_PUPD_PUPD3                                                             */
+  PF_PUPD_PUPD3_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD3_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD3_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD3_Enum;
+
+/* =================================================  PF PUPD PUPD2 [4..5]  ================================================== */
+typedef enum {                                  /*!< PF_PUPD_PUPD2                                                             */
+  PF_PUPD_PUPD2_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD2_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD2_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD2_Enum;
+
+/* =================================================  PF PUPD PUPD1 [2..3]  ================================================== */
+typedef enum {                                  /*!< PF_PUPD_PUPD1                                                             */
+  PF_PUPD_PUPD1_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD1_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD1_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD1_Enum;
+
+/* =================================================  PF PUPD PUPD0 [0..1]  ================================================== */
+typedef enum {                                  /*!< PF_PUPD_PUPD0                                                             */
+  PF_PUPD_PUPD0_Disable                = 0,     /*!< Disable : Disable pull-up/down resistor.                                  */
+  PF_PUPD_PUPD0_EnablePU               = 1,     /*!< EnablePU : Enable pull-up resistor.                                       */
+  PF_PUPD_PUPD0_EnablePD               = 2,     /*!< EnablePD : Enable pull-down resistor.                                     */
+} PF_PUPD_PUPD0_Enum;
+
+/* =========================================================  INDR  ========================================================== */
+/* =========================================================  OUTDR  ========================================================= */
+/* ==========================================================  BSR  ========================================================== */
+/* =================================================  PF BSR BSR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PF_BSR_BSR15                                                              */
+  PF_BSR_BSR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR15_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR15_Enum;
+
+/* =================================================  PF BSR BSR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PF_BSR_BSR14                                                              */
+  PF_BSR_BSR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR14_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR14_Enum;
+
+/* =================================================  PF BSR BSR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PF_BSR_BSR13                                                              */
+  PF_BSR_BSR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR13_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR13_Enum;
+
+/* =================================================  PF BSR BSR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PF_BSR_BSR12                                                              */
+  PF_BSR_BSR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR12_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR12_Enum;
+
+/* =================================================  PF BSR BSR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PF_BSR_BSR11                                                              */
+  PF_BSR_BSR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR11_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR11_Enum;
+
+/* =================================================  PF BSR BSR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PF_BSR_BSR10                                                              */
+  PF_BSR_BSR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR10_Set                     = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR10_Enum;
+
+/* ==================================================  PF BSR BSR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR9                                                               */
+  PF_BSR_BSR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR9_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR9_Enum;
+
+/* ==================================================  PF BSR BSR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR8                                                               */
+  PF_BSR_BSR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR8_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR8_Enum;
+
+/* ==================================================  PF BSR BSR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR7                                                               */
+  PF_BSR_BSR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR7_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR7_Enum;
+
+/* ==================================================  PF BSR BSR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR6                                                               */
+  PF_BSR_BSR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR6_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR6_Enum;
+
+/* ==================================================  PF BSR BSR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR5                                                               */
+  PF_BSR_BSR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR5_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR5_Enum;
+
+/* ==================================================  PF BSR BSR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR4                                                               */
+  PF_BSR_BSR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR4_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR4_Enum;
+
+/* ==================================================  PF BSR BSR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR3                                                               */
+  PF_BSR_BSR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR3_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR3_Enum;
+
+/* ==================================================  PF BSR BSR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR2                                                               */
+  PF_BSR_BSR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR2_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR2_Enum;
+
+/* ==================================================  PF BSR BSR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR1                                                               */
+  PF_BSR_BSR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR1_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR1_Enum;
+
+/* ==================================================  PF BSR BSR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PF_BSR_BSR0                                                               */
+  PF_BSR_BSR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BSR_BSR0_Set                      = 1,     /*!< Set : Set the corresponding OUTDRx bit (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BSR_BSR0_Enum;
+
+/* ==========================================================  BCR  ========================================================== */
+/* =================================================  PF BCR BCR15 [15..15]  ================================================= */
+typedef enum {                                  /*!< PF_BCR_BCR15                                                              */
+  PF_BCR_BCR15_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR15_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR15_Enum;
+
+/* =================================================  PF BCR BCR14 [14..14]  ================================================= */
+typedef enum {                                  /*!< PF_BCR_BCR14                                                              */
+  PF_BCR_BCR14_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR14_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR14_Enum;
+
+/* =================================================  PF BCR BCR13 [13..13]  ================================================= */
+typedef enum {                                  /*!< PF_BCR_BCR13                                                              */
+  PF_BCR_BCR13_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR13_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR13_Enum;
+
+/* =================================================  PF BCR BCR12 [12..12]  ================================================= */
+typedef enum {                                  /*!< PF_BCR_BCR12                                                              */
+  PF_BCR_BCR12_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR12_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR12_Enum;
+
+/* =================================================  PF BCR BCR11 [11..11]  ================================================= */
+typedef enum {                                  /*!< PF_BCR_BCR11                                                              */
+  PF_BCR_BCR11_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR11_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR11_Enum;
+
+/* =================================================  PF BCR BCR10 [10..10]  ================================================= */
+typedef enum {                                  /*!< PF_BCR_BCR10                                                              */
+  PF_BCR_BCR10_NoEffect                = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR10_Clear                   = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR10_Enum;
+
+/* ==================================================  PF BCR BCR9 [9..9]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR9                                                               */
+  PF_BCR_BCR9_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR9_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR9_Enum;
+
+/* ==================================================  PF BCR BCR8 [8..8]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR8                                                               */
+  PF_BCR_BCR8_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR8_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR8_Enum;
+
+/* ==================================================  PF BCR BCR7 [7..7]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR7                                                               */
+  PF_BCR_BCR7_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR7_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR7_Enum;
+
+/* ==================================================  PF BCR BCR6 [6..6]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR6                                                               */
+  PF_BCR_BCR6_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR6_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR6_Enum;
+
+/* ==================================================  PF BCR BCR5 [5..5]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR5                                                               */
+  PF_BCR_BCR5_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR5_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR5_Enum;
+
+/* ==================================================  PF BCR BCR4 [4..4]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR4                                                               */
+  PF_BCR_BCR4_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR4_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR4_Enum;
+
+/* ==================================================  PF BCR BCR3 [3..3]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR3                                                               */
+  PF_BCR_BCR3_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR3_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR3_Enum;
+
+/* ==================================================  PF BCR BCR2 [2..2]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR2                                                               */
+  PF_BCR_BCR2_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR2_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR2_Enum;
+
+/* ==================================================  PF BCR BCR1 [1..1]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR1                                                               */
+  PF_BCR_BCR1_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR1_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR1_Enum;
+
+/* ==================================================  PF BCR BCR0 [0..0]  =================================================== */
+typedef enum {                                  /*!< PF_BCR_BCR0                                                               */
+  PF_BCR_BCR0_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  PF_BCR_BCR0_Clear                    = 1,     /*!< Clear : Clear the corresponding OUTDRx bit. (Automatically cleared
+                                                     to 0.)                                                                    */
+} PF_BCR_BCR0_Enum;
+
+/* ========================================================  OUTDMSK  ======================================================== */
+/* =============================================  PF OUTDMSK OUTDMSK15 [15..15]  ============================================= */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK15                                                      */
+  PF_OUTDMSK_OUTDMSK15_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK15_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK15_Enum;
+
+/* =============================================  PF OUTDMSK OUTDMSK14 [14..14]  ============================================= */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK14                                                      */
+  PF_OUTDMSK_OUTDMSK14_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK14_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK14_Enum;
+
+/* =============================================  PF OUTDMSK OUTDMSK13 [13..13]  ============================================= */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK13                                                      */
+  PF_OUTDMSK_OUTDMSK13_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK13_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK13_Enum;
+
+/* =============================================  PF OUTDMSK OUTDMSK12 [12..12]  ============================================= */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK12                                                      */
+  PF_OUTDMSK_OUTDMSK12_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK12_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK12_Enum;
+
+/* =============================================  PF OUTDMSK OUTDMSK11 [11..11]  ============================================= */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK11                                                      */
+  PF_OUTDMSK_OUTDMSK11_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK11_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK11_Enum;
+
+/* =============================================  PF OUTDMSK OUTDMSK10 [10..10]  ============================================= */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK10                                                      */
+  PF_OUTDMSK_OUTDMSK10_Unmask          = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK10_Mask            = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK10_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK9 [9..9]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK9                                                       */
+  PF_OUTDMSK_OUTDMSK9_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK9_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK9_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK8 [8..8]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK8                                                       */
+  PF_OUTDMSK_OUTDMSK8_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK8_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK8_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK7 [7..7]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK7                                                       */
+  PF_OUTDMSK_OUTDMSK7_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK7_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK7_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK6 [6..6]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK6                                                       */
+  PF_OUTDMSK_OUTDMSK6_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK6_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK6_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK5 [5..5]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK5                                                       */
+  PF_OUTDMSK_OUTDMSK5_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK5_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK5_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK4 [4..4]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK4                                                       */
+  PF_OUTDMSK_OUTDMSK4_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK4_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK4_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK3 [3..3]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK3                                                       */
+  PF_OUTDMSK_OUTDMSK3_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK3_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK3_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK2 [2..2]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK2                                                       */
+  PF_OUTDMSK_OUTDMSK2_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK2_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK2_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK1 [1..1]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK1                                                       */
+  PF_OUTDMSK_OUTDMSK1_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK1_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK1_Enum;
+
+/* ==============================================  PF OUTDMSK OUTDMSK0 [0..0]  =============================================== */
+typedef enum {                                  /*!< PF_OUTDMSK_OUTDMSK0                                                       */
+  PF_OUTDMSK_OUTDMSK0_Unmask           = 0,     /*!< Unmask : Unmask. The corresponding OUTDRx bit can be changed.             */
+  PF_OUTDMSK_OUTDMSK0_Mask             = 1,     /*!< Mask : Mask. The corresponding OUTDRx bit is protected.                   */
+} PF_OUTDMSK_OUTDMSK0_Enum;
+
+/* =========================================================  DBCR  ========================================================== */
+/* ================================================  PF DBCR DBCLK [16..18]  ================================================= */
+typedef enum {                                  /*!< PF_DBCR_DBCLK                                                             */
+  PF_DBCR_DBCLK_HCLK1                  = 0,     /*!< HCLK1 : HCLK/1                                                            */
+  PF_DBCR_DBCLK_HCLK4                  = 1,     /*!< HCLK4 : HCLK/4                                                            */
+  PF_DBCR_DBCLK_HCLK16                 = 2,     /*!< HCLK16 : HCLK/16                                                          */
+  PF_DBCR_DBCLK_HCLK64                 = 3,     /*!< HCLK64 : HCLK/64                                                          */
+  PF_DBCR_DBCLK_HCLK256                = 4,     /*!< HCLK256 : HCLK/256                                                        */
+  PF_DBCR_DBCLK_HCLK1024               = 5,     /*!< HCLK1024 : HCLK/1024                                                      */
+} PF_DBCR_DBCLK_Enum;
+
+/* ================================================  PF DBCR DBEN11 [11..11]  ================================================ */
+typedef enum {                                  /*!< PF_DBCR_DBEN11                                                            */
+  PF_DBCR_DBEN11_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN11_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN11_Enum;
+
+/* ================================================  PF DBCR DBEN10 [10..10]  ================================================ */
+typedef enum {                                  /*!< PF_DBCR_DBEN10                                                            */
+  PF_DBCR_DBEN10_Disable               = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN10_Enable                = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN10_Enum;
+
+/* =================================================  PF DBCR DBEN9 [9..9]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN9                                                             */
+  PF_DBCR_DBEN9_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN9_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN9_Enum;
+
+/* =================================================  PF DBCR DBEN8 [8..8]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN8                                                             */
+  PF_DBCR_DBEN8_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN8_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN8_Enum;
+
+/* =================================================  PF DBCR DBEN7 [7..7]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN7                                                             */
+  PF_DBCR_DBEN7_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN7_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN7_Enum;
+
+/* =================================================  PF DBCR DBEN6 [6..6]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN6                                                             */
+  PF_DBCR_DBEN6_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN6_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN6_Enum;
+
+/* =================================================  PF DBCR DBEN5 [5..5]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN5                                                             */
+  PF_DBCR_DBEN5_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN5_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN5_Enum;
+
+/* =================================================  PF DBCR DBEN4 [4..4]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN4                                                             */
+  PF_DBCR_DBEN4_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN4_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN4_Enum;
+
+/* =================================================  PF DBCR DBEN3 [3..3]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN3                                                             */
+  PF_DBCR_DBEN3_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN3_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN3_Enum;
+
+/* =================================================  PF DBCR DBEN2 [2..2]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN2                                                             */
+  PF_DBCR_DBEN2_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN2_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN2_Enum;
+
+/* =================================================  PF DBCR DBEN1 [1..1]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN1                                                             */
+  PF_DBCR_DBEN1_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN1_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN1_Enum;
+
+/* =================================================  PF DBCR DBEN0 [0..0]  ================================================== */
+typedef enum {                                  /*!< PF_DBCR_DBEN0                                                             */
+  PF_DBCR_DBEN0_Disable                = 0,     /*!< Disable : Disable debounce filter.                                        */
+  PF_DBCR_DBEN0_Enable                 = 1,     /*!< Enable : Enable debounce filter.                                          */
+} PF_DBCR_DBEN0_Enum;
+
+/* ========================================================  PF_MOD  ========================================================= */
+/* ========================================================  PF_TYP  ========================================================= */
+/* =======================================================  PF_AFSR1  ======================================================== */
+/* =======================================================  PF_AFSR2  ======================================================== */
+/* ========================================================  PF_PUPD  ======================================================== */
+/* ========================================================  PF_INDR  ======================================================== */
+/* =======================================================  PF_OUTDR  ======================================================== */
+/* ========================================================  PF_BSR  ========================================================= */
+/* ========================================================  PF_BCR  ========================================================= */
+/* ======================================================  PF_OUTDMSK  ======================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                            FMC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ADR  ========================================================== */
+/* =========================================================  IDR1  ========================================================== */
+/* =========================================================  IDR2  ========================================================== */
+/* ==========================================================  CR  =========================================================== */
+/* ================================================  FMC CR WTIDKY [16..31]  ================================================= */
+typedef enum {                                  /*!< FMC_CR_WTIDKY                                                             */
+  FMC_CR_WTIDKY_Value                  = 27795, /*!< Value : Key Value (0x6c93)                                                */
+} FMC_CR_WTIDKY_Enum;
+
+/* ==========================================================  BCR  ========================================================== */
+/* ================================================  FMC BCR WTIDKY [16..31]  ================================================ */
+typedef enum {                                  /*!< FMC_BCR_WTIDKY                                                            */
+  FMC_BCR_WTIDKY_Value                 = 49598, /*!< Value : Key Value (0xc1be)                                                */
+} FMC_BCR_WTIDKY_Enum;
+
+/* ========================================================  ERFLAG  ========================================================= */
+/* ========================================================  PAGEBUF  ======================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                            WDT                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ================================================  WDT CR WTIDKY [16..31]  ================================================= */
+typedef enum {                                  /*!< WDT_CR_WTIDKY                                                             */
+  WDT_CR_WTIDKY_Value                  = 23145, /*!< Value : Key Value (0x5a69)                                                */
+} WDT_CR_WTIDKY_Enum;
+
+/* =================================================  WDT CR RSTEN [10..15]  ================================================= */
+typedef enum {                                  /*!< WDT_CR_RSTEN                                                              */
+  WDT_CR_RSTEN_Disable                 = 37,    /*!< Disable : Disable Watch-Dog Timer reset. (0x25)                           */
+  WDT_CR_RSTEN_Enable                  = 0,     /*!< Enable : Enable Watch-Dog Timer reset.                                    */
+} WDT_CR_RSTEN_Enum;
+
+/* ==================================================  WDT CR CNTEN [4..9]  ================================================== */
+typedef enum {                                  /*!< WDT_CR_CNTEN                                                              */
+  WDT_CR_CNTEN_Disable                 = 26,    /*!< Disable : Disable Watch-Dog Timer counter. (0x1a)                         */
+  WDT_CR_CNTEN_Enable                  = 0,     /*!< Enable : Enable Watch-Dog Timer counter.                                  */
+} WDT_CR_CNTEN_Enum;
+
+/* =================================================  WDT CR WINMIEN [3..3]  ================================================= */
+typedef enum {                                  /*!< WDT_CR_WINMIEN                                                            */
+  WDT_CR_WINMIEN_Disable               = 0,     /*!< Disable : Disable window data match interrupt.                            */
+  WDT_CR_WINMIEN_Enable                = 1,     /*!< Enable : Enable window data match interrupt.                              */
+} WDT_CR_WINMIEN_Enum;
+
+/* =================================================  WDT CR UNFIEN [2..2]  ================================================== */
+typedef enum {                                  /*!< WDT_CR_UNFIEN                                                             */
+  WDT_CR_UNFIEN_Disable                = 0,     /*!< Disable : Disable Watch-Dog Timer underflow interrupt.                    */
+  WDT_CR_UNFIEN_Enable                 = 1,     /*!< Enable : Enable Watch-Dog Timer underflow interrupt.                      */
+} WDT_CR_UNFIEN_Enum;
+
+/* =================================================  WDT CR CLKDIV [0..1]  ================================================== */
+typedef enum {                                  /*!< WDT_CR_CLKDIV                                                             */
+  WDT_CR_CLKDIV_fWDT4                  = 0,     /*!< fWDT4 : fWDT/4                                                            */
+  WDT_CR_CLKDIV_fWDT16                 = 1,     /*!< fWDT16 : fWDT/16                                                          */
+  WDT_CR_CLKDIV_fWDT64                 = 2,     /*!< fWDT64 : fWDT/64                                                          */
+  WDT_CR_CLKDIV_fWDT256                = 3,     /*!< fWDT256 : fWDT/256                                                        */
+} WDT_CR_CLKDIV_Enum;
+
+/* ==========================================================  SR  =========================================================== */
+/* ================================================  WDT SR DBGCNTEN [7..7]  ================================================= */
+typedef enum {                                  /*!< WDT_SR_DBGCNTEN                                                           */
+  WDT_SR_DBGCNTEN_Run                  = 0,     /*!< Run : The Watch-Dog Timer counter continues even if the core
+                                                     is halted                                                                 */
+  WDT_SR_DBGCNTEN_Stop                 = 1,     /*!< Stop : The Watch-Dog Timer counter is stopped when the core
+                                                     is halted                                                                 */
+} WDT_SR_DBGCNTEN_Enum;
+
+/* ================================================  WDT SR WINMIFLAG [1..1]  ================================================ */
+typedef enum {                                  /*!< WDT_SR_WINMIFLAG                                                          */
+  WDT_SR_WINMIFLAG_NoRequest           = 0,     /*!< NoRequest : No request occurred.                                          */
+  WDT_SR_WINMIFLAG_Request             = 1,     /*!< Request : Request occurred.                                               */
+} WDT_SR_WINMIFLAG_Enum;
+
+/* ================================================  WDT SR UNFIFLAG [0..0]  ================================================= */
+typedef enum {                                  /*!< WDT_SR_UNFIFLAG                                                           */
+  WDT_SR_UNFIFLAG_NoRequest            = 0,     /*!< NoRequest : No request occurred.                                          */
+  WDT_SR_UNFIFLAG_Request              = 1,     /*!< Request : Request occurred.                                               */
+} WDT_SR_UNFIFLAG_Enum;
+
+/* ==========================================================  DR  =========================================================== */
+/* ==========================================================  CNT  ========================================================== */
+/* =========================================================  WINDR  ========================================================= */
+/* =========================================================  CNTR  ========================================================== */
+/* =================================================  WDT CNTR CNTR [0..7]  ================================================== */
+typedef enum {                                  /*!< WDT_CNTR_CNTR                                                             */
+  WDT_CNTR_CNTR_Reload                 = 106,   /*!< Reload : Reload the WDTDR value to Watch-Dog Timer counter and
+                                                     re-start. (0x6a) (Automatically cleared to '0x00' after
+                                                     operation.)                                                               */
+  WDT_CNTR_CNTR_NoEffect               = 0,     /*!< NoEffect : No effect.                                                     */
+} WDT_CNTR_CNTR_Enum;
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            WT                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ===================================================  WT CR WTEN [7..7]  =================================================== */
+typedef enum {                                  /*!< WT_CR_WTEN                                                                */
+  WT_CR_WTEN_Disable                   = 0,     /*!< Disable : Disable watch timer operation.                                  */
+  WT_CR_WTEN_Enable                    = 1,     /*!< Enable : Enable watch timer operation.                                    */
+} WT_CR_WTEN_Enum;
+
+/* ==================================================  WT CR WTINTV [4..5]  ================================================== */
+typedef enum {                                  /*!< WT_CR_WTINTV                                                              */
+  WT_CR_WTINTV_fWT2Pow7                = 0,     /*!< fWT2Pow7 : fWT/2^7                                                        */
+  WT_CR_WTINTV_fWT2Pow13               = 1,     /*!< fWT2Pow13 : fWT/2^13                                                      */
+  WT_CR_WTINTV_fWT2Pow14               = 2,     /*!< fWT2Pow14 : fWT/2^14                                                      */
+  WT_CR_WTINTV_fWT2Pow14DR             = 3,     /*!< fWT2Pow14DR : fWT/(2^14x(WTDR value + 1))                                 */
+} WT_CR_WTINTV_Enum;
+
+/* ==================================================  WT CR WTIEN [3..3]  =================================================== */
+typedef enum {                                  /*!< WT_CR_WTIEN                                                               */
+  WT_CR_WTIEN_Disable                  = 0,     /*!< Disable : Disable watch timer interrupt.                                  */
+  WT_CR_WTIEN_Enable                   = 1,     /*!< Enable : Enable watch timer interrupt.                                    */
+} WT_CR_WTIEN_Enum;
+
+/* =================================================  WT CR WTIFLAG [1..1]  ================================================== */
+typedef enum {                                  /*!< WT_CR_WTIFLAG                                                             */
+  WT_CR_WTIFLAG_NoRequest              = 0,     /*!< NoRequest : No request occurred.                                          */
+  WT_CR_WTIFLAG_Request                = 1,     /*!< Request : Request occurred.                                               */
+} WT_CR_WTIFLAG_Enum;
+
+/* ==================================================  WT CR WTCLR [0..0]  =================================================== */
+typedef enum {                                  /*!< WT_CR_WTCLR                                                               */
+  WT_CR_WTCLR_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  WT_CR_WTCLR_Clear                    = 1,     /*!< Clear : Clear the counter and divider. (Automatically cleared
+                                                     to '0b' after operation)                                                  */
+} WT_CR_WTCLR_Enum;
+
+/* ==========================================================  DR  =========================================================== */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER1n                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER10                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER11                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER12                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER13                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER14                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER15                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER16                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER2n                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER20                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+/* ======================================================  TIMER20_CR  ======================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER21                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+/* ======================================================  TIMER21_CR  ======================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER3n                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ===============================================  TIMER3n CR T3nEN [15..15]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_CR_T3nEN                                                          */
+  TIMER3n_CR_T3nEN_Disable             = 0,     /*!< Disable : Disable TIMER3n Operation.                                      */
+  TIMER3n_CR_T3nEN_Enable              = 1,     /*!< Enable : Enable TIMER3n Operation. (Counter Clear and Start)              */
+} TIMER3n_CR_T3nEN_Enum;
+
+/* ==============================================  TIMER3n CR T3nCLK [14..14]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_CR_T3nCLK                                                         */
+  TIMER3n_CR_T3nCLK_IntPrescaledClock  = 0,     /*!< IntPrescaledClock : Select an Internal Prescaler Clock.                   */
+  TIMER3n_CR_T3nCLK_ExtClock           = 1,     /*!< ExtClock : Select an External Clock.                                      */
+} TIMER3n_CR_T3nCLK_Enum;
+
+/* ===============================================  TIMER3n CR T3nMS [12..13]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_CR_T3nMS                                                          */
+  TIMER3n_CR_T3nMS_IntervalMode        = 0,     /*!< IntervalMode : Interval mode. (All match interrupts can occur)            */
+  TIMER3n_CR_T3nMS_CaptureMode         = 1,     /*!< CaptureMode : Capture mode. (The Period-match interrupt can
+                                                     occur)                                                                    */
+  TIMER3n_CR_T3nMS_BackToBackMode      = 2,     /*!< BackToBackMode : Back-to-back mode. (All interrupts can occur)            */
+} TIMER3n_CR_T3nMS_Enum;
+
+/* ==============================================  TIMER3n CR T3nECE [11..11]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_CR_T3nECE                                                         */
+  TIMER3n_CR_T3nECE_FallingEdge        = 0,     /*!< FallingEdge : Select falling edge of external clock.                      */
+  TIMER3n_CR_T3nECE_RisingEdge         = 1,     /*!< RisingEdge : Select rising edge of external clock.                        */
+} TIMER3n_CR_T3nECE_Enum;
+
+/* ===============================================  TIMER3n CR FORCA [10..10]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_CR_FORCA                                                          */
+  TIMER3n_CR_FORCA_AllChannelMode      = 0,     /*!< AllChannelMode : 6-Channel mode. (The PWM3nxA/PWM3nxB pins are
+                                                     outputs according to the TIMER30_xDR registers, respectively.)            */
+  TIMER3n_CR_FORCA_AChannelMode        = 1,     /*!< AChannelMode : Force A-Channel mode. (All PWM3nxA/PWM3nxB pins
+                                                     are outputs according only to the TIMER30_ADR register.)                  */
+} TIMER3n_CR_FORCA_Enum;
+
+/* ================================================  TIMER3n CR DLYEN [9..9]  ================================================ */
+typedef enum {                                  /*!< TIMER3n_CR_DLYEN                                                          */
+  TIMER3n_CR_DLYEN_Disable             = 0,     /*!< Disable : Disable delay time insertion to the PWM3nxA/PWM3nxB.            */
+  TIMER3n_CR_DLYEN_Enable              = 1,     /*!< Enable : Enable delay time insertion to the PWM3nxA/PWM3nxB.              */
+} TIMER3n_CR_DLYEN_Enum;
+
+/* ===============================================  TIMER3n CR DLYPOS [8..8]  ================================================ */
+typedef enum {                                  /*!< TIMER3n_CR_DLYPOS                                                         */
+  TIMER3n_CR_DLYPOS_FrontABehindB      = 0,     /*!< FrontABehindB : Insert in front of PWM3nxA and behind PWM3nxB
+                                                     pins.                                                                     */
+  TIMER3n_CR_DLYPOS_BehindAFrontB      = 1,     /*!< BehindAFrontB : Insert behind PWM3nxA and in front of PWM3nxB
+                                                     pins.                                                                     */
+} TIMER3n_CR_DLYPOS_Enum;
+
+/* ===============================================  TIMER3n CR T3nCPOL [6..7]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_CR_T3nCPOL                                                        */
+  TIMER3n_CR_T3nCPOL_FallingEdge       = 0,     /*!< FallingEdge : Capture on falling edge.                                    */
+  TIMER3n_CR_T3nCPOL_RisingEdge        = 1,     /*!< RisingEdge : Capture on rising edge.                                      */
+  TIMER3n_CR_T3nCPOL_BothEdge          = 2,     /*!< BothEdge : Capture on both falling and rising edge.                       */
+} TIMER3n_CR_T3nCPOL_Enum;
+
+/* ================================================  TIMER3n CR UPDT [4..5]  ================================================= */
+typedef enum {                                  /*!< TIMER3n_CR_UPDT                                                           */
+  TIMER3n_CR_UPDT_AtWriting            = 0,     /*!< AtWriting : Update data to buffer at the time of writing.                 */
+  TIMER3n_CR_UPDT_AtPeriodMatch        = 1,     /*!< AtPeriodMatch : Update data to buffer at period match.                    */
+  TIMER3n_CR_UPDT_AtBottom             = 2,     /*!< AtBottom : Update data to buffer at bottom.                               */
+} TIMER3n_CR_UPDT_Enum;
+
+/* ================================================  TIMER3n CR PMOC [1..3]  ================================================= */
+typedef enum {                                  /*!< TIMER3n_CR_PMOC                                                           */
+  TIMER3n_CR_PMOC_Every1PeriodMatch    = 0,     /*!< Every1PeriodMatch : Once every 1 period match.                            */
+  TIMER3n_CR_PMOC_Every2PeriodMatch    = 1,     /*!< Every2PeriodMatch : Once every 2 period match.                            */
+  TIMER3n_CR_PMOC_Every3PeriodMatch    = 2,     /*!< Every3PeriodMatch : Once every 3 period match.                            */
+  TIMER3n_CR_PMOC_Every4PeriodMatch    = 3,     /*!< Every4PeriodMatch : Once every 4 period match.                            */
+  TIMER3n_CR_PMOC_Every5PeriodMatch    = 4,     /*!< Every5PeriodMatch : Once every 5 period match.                            */
+  TIMER3n_CR_PMOC_Every6PeriodMatch    = 5,     /*!< Every6PeriodMatch : Once every 6 period match.                            */
+  TIMER3n_CR_PMOC_Every7PeriodMatch    = 6,     /*!< Every7PeriodMatch : Once every 7 period match.                            */
+  TIMER3n_CR_PMOC_Every8PeriodMatch    = 7,     /*!< Every8PeriodMatch : Once every 8 period match.                            */
+} TIMER3n_CR_PMOC_Enum;
+
+/* ===============================================  TIMER3n CR T3nCLR [0..0]  ================================================ */
+typedef enum {                                  /*!< TIMER3n_CR_T3nCLR                                                         */
+  TIMER3n_CR_T3nCLR_NoEffect           = 0,     /*!< NoEffect : No effect.                                                     */
+  TIMER3n_CR_T3nCLR_Clear              = 1,     /*!< Clear : Clear TIMER3n counter and prescaler. (Automatically
+                                                     cleared to '0b' after operation)                                          */
+} TIMER3n_CR_T3nCLR_Enum;
+
+/* ==========================================================  PDR  ========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  CDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+/* =========================================================  OUTCR  ========================================================= */
+/* ==============================================  TIMER3n OUTCR POLB [15..15]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_POLB                                                        */
+  TIMER3n_OUTCR_POLB_StartLow          = 0,     /*!< StartLow : Low level start. (The PWM3nxB pins are started with
+                                                     low level after counting.)                                                */
+  TIMER3n_OUTCR_POLB_StartHigh         = 1,     /*!< StartHigh : High level start. (The PWM3nxB pins are started
+                                                     with high level after counting)                                           */
+} TIMER3n_OUTCR_POLB_Enum;
+
+/* ==============================================  TIMER3n OUTCR POLA [14..14]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_POLA                                                        */
+  TIMER3n_OUTCR_POLA_StartLow          = 0,     /*!< StartLow : Low level start. (The PWM3nxA pins are started with
+                                                     low level after counting.)                                                */
+  TIMER3n_OUTCR_POLA_StartHigh         = 1,     /*!< StartHigh : High level start. (The PWM3nxA pins are started
+                                                     with high level after counting)                                           */
+} TIMER3n_OUTCR_POLA_Enum;
+
+/* =============================================  TIMER3n OUTCR PABOE [13..13]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_PABOE                                                       */
+  TIMER3n_OUTCR_PABOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER3n_OUTCR_PABOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER3n_OUTCR_PABOE_Enum;
+
+/* =============================================  TIMER3n OUTCR PBBOE [12..12]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_PBBOE                                                       */
+  TIMER3n_OUTCR_PBBOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER3n_OUTCR_PBBOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER3n_OUTCR_PBBOE_Enum;
+
+/* =============================================  TIMER3n OUTCR PCBOE [11..11]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_PCBOE                                                       */
+  TIMER3n_OUTCR_PCBOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER3n_OUTCR_PCBOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER3n_OUTCR_PCBOE_Enum;
+
+/* =============================================  TIMER3n OUTCR PAAOE [10..10]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_PAAOE                                                       */
+  TIMER3n_OUTCR_PAAOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER3n_OUTCR_PAAOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER3n_OUTCR_PAAOE_Enum;
+
+/* ==============================================  TIMER3n OUTCR PBAOE [9..9]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_PBAOE                                                       */
+  TIMER3n_OUTCR_PBAOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER3n_OUTCR_PBAOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER3n_OUTCR_PBAOE_Enum;
+
+/* ==============================================  TIMER3n OUTCR PCAOE [8..8]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_PCAOE                                                       */
+  TIMER3n_OUTCR_PCAOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER3n_OUTCR_PCAOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER3n_OUTCR_PCAOE_Enum;
+
+/* ==============================================  TIMER3n OUTCR LVLAB [6..6]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_LVLAB                                                       */
+  TIMER3n_OUTCR_LVLAB_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER3n_OUTCR_LVLAB_High             = 1,     /*!< High : High level.                                                        */
+} TIMER3n_OUTCR_LVLAB_Enum;
+
+/* ==============================================  TIMER3n OUTCR LVLBB [5..5]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_LVLBB                                                       */
+  TIMER3n_OUTCR_LVLBB_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER3n_OUTCR_LVLBB_High             = 1,     /*!< High : High level.                                                        */
+} TIMER3n_OUTCR_LVLBB_Enum;
+
+/* ==============================================  TIMER3n OUTCR LVLCB [4..4]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_LVLCB                                                       */
+  TIMER3n_OUTCR_LVLCB_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER3n_OUTCR_LVLCB_High             = 1,     /*!< High : High level.                                                        */
+} TIMER3n_OUTCR_LVLCB_Enum;
+
+/* ==============================================  TIMER3n OUTCR LVLAA [2..2]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_LVLAA                                                       */
+  TIMER3n_OUTCR_LVLAA_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER3n_OUTCR_LVLAA_High             = 1,     /*!< High : High level.                                                        */
+} TIMER3n_OUTCR_LVLAA_Enum;
+
+/* ==============================================  TIMER3n OUTCR LVLBA [1..1]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_LVLBA                                                       */
+  TIMER3n_OUTCR_LVLBA_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER3n_OUTCR_LVLBA_High             = 1,     /*!< High : High level.                                                        */
+} TIMER3n_OUTCR_LVLBA_Enum;
+
+/* ==============================================  TIMER3n OUTCR LVLCA [0..0]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_OUTCR_LVLCA                                                       */
+  TIMER3n_OUTCR_LVLCA_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER3n_OUTCR_LVLCA_High             = 1,     /*!< High : High level.                                                        */
+} TIMER3n_OUTCR_LVLCA_Enum;
+
+/* ==========================================================  DLY  ========================================================== */
+/* =========================================================  INTCR  ========================================================= */
+/* ==============================================  TIMER3n INTCR HIZIEN [6..6]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_INTCR_HIZIEN                                                      */
+  TIMER3n_INTCR_HIZIEN_Disable         = 0,     /*!< Disable : Disable TIMER3n output high-impedance interrupt.                */
+  TIMER3n_INTCR_HIZIEN_Enable          = 1,     /*!< Enable : Enable TIMER3n output high-impedance interrupt.                  */
+} TIMER3n_INTCR_HIZIEN_Enum;
+
+/* =============================================  TIMER3n INTCR T3nCIEN [5..5]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_INTCR_T3nCIEN                                                     */
+  TIMER3n_INTCR_T3nCIEN_Disable        = 0,     /*!< Disable : Disable TIMER3n capture interrupt.                              */
+  TIMER3n_INTCR_T3nCIEN_Enable         = 1,     /*!< Enable : Enable TIMER3n capture interrupt.                                */
+} TIMER3n_INTCR_T3nCIEN_Enum;
+
+/* =============================================  TIMER3n INTCR T3nBTIEN [4..4]  ============================================= */
+typedef enum {                                  /*!< TIMER3n_INTCR_T3nBTIEN                                                    */
+  TIMER3n_INTCR_T3nBTIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n bottom interrupt.                               */
+  TIMER3n_INTCR_T3nBTIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n bottom interrupt.                                 */
+} TIMER3n_INTCR_T3nBTIEN_Enum;
+
+/* =============================================  TIMER3n INTCR T3nPMIEN [3..3]  ============================================= */
+typedef enum {                                  /*!< TIMER3n_INTCR_T3nPMIEN                                                    */
+  TIMER3n_INTCR_T3nPMIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n period interrupt.                               */
+  TIMER3n_INTCR_T3nPMIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n period interrupt.                                 */
+} TIMER3n_INTCR_T3nPMIEN_Enum;
+
+/* =============================================  TIMER3n INTCR T3nAMIEN [2..2]  ============================================= */
+typedef enum {                                  /*!< TIMER3n_INTCR_T3nAMIEN                                                    */
+  TIMER3n_INTCR_T3nAMIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n A-ch match interrupt.                           */
+  TIMER3n_INTCR_T3nAMIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n A-ch match interrupt.                             */
+} TIMER3n_INTCR_T3nAMIEN_Enum;
+
+/* =============================================  TIMER3n INTCR T3nBMIEN [1..1]  ============================================= */
+typedef enum {                                  /*!< TIMER3n_INTCR_T3nBMIEN                                                    */
+  TIMER3n_INTCR_T3nBMIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n B-ch match interrupt.                           */
+  TIMER3n_INTCR_T3nBMIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n B-ch match interrupt.                             */
+} TIMER3n_INTCR_T3nBMIEN_Enum;
+
+/* =============================================  TIMER3n INTCR T3nCMIEN [0..0]  ============================================= */
+typedef enum {                                  /*!< TIMER3n_INTCR_T3nCMIEN                                                    */
+  TIMER3n_INTCR_T3nCMIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n C-ch match interrupt.                           */
+  TIMER3n_INTCR_T3nCMIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n C-ch match interrupt.                             */
+} TIMER3n_INTCR_T3nCMIEN_Enum;
+
+/* ========================================================  INTFLAG  ======================================================== */
+/* ============================================  TIMER3n INTFLAG HIZIFLAG [6..6]  ============================================ */
+typedef enum {                                  /*!< TIMER3n_INTFLAG_HIZIFLAG                                                  */
+  TIMER3n_INTFLAG_HIZIFLAG_NoRequest   = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER3n_INTFLAG_HIZIFLAG_Request     = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER3n_INTFLAG_HIZIFLAG_Enum;
+
+/* ===========================================  TIMER3n INTFLAG T3nCIFLAG [5..5]  ============================================ */
+typedef enum {                                  /*!< TIMER3n_INTFLAG_T3nCIFLAG                                                 */
+  TIMER3n_INTFLAG_T3nCIFLAG_NoRequest  = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER3n_INTFLAG_T3nCIFLAG_Request    = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER3n_INTFLAG_T3nCIFLAG_Enum;
+
+/* ===========================================  TIMER3n INTFLAG T3nBTIFLAG [4..4]  =========================================== */
+typedef enum {                                  /*!< TIMER3n_INTFLAG_T3nBTIFLAG                                                */
+  TIMER3n_INTFLAG_T3nBTIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER3n_INTFLAG_T3nBTIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER3n_INTFLAG_T3nBTIFLAG_Enum;
+
+/* ===========================================  TIMER3n INTFLAG T3nPMIFLAG [3..3]  =========================================== */
+typedef enum {                                  /*!< TIMER3n_INTFLAG_T3nPMIFLAG                                                */
+  TIMER3n_INTFLAG_T3nPMIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER3n_INTFLAG_T3nPMIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER3n_INTFLAG_T3nPMIFLAG_Enum;
+
+/* ===========================================  TIMER3n INTFLAG T3nAMIFLAG [2..2]  =========================================== */
+typedef enum {                                  /*!< TIMER3n_INTFLAG_T3nAMIFLAG                                                */
+  TIMER3n_INTFLAG_T3nAMIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER3n_INTFLAG_T3nAMIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER3n_INTFLAG_T3nAMIFLAG_Enum;
+
+/* ===========================================  TIMER3n INTFLAG T3nBMIFLAG [1..1]  =========================================== */
+typedef enum {                                  /*!< TIMER3n_INTFLAG_T3nBMIFLAG                                                */
+  TIMER3n_INTFLAG_T3nBMIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER3n_INTFLAG_T3nBMIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER3n_INTFLAG_T3nBMIFLAG_Enum;
+
+/* ===========================================  TIMER3n INTFLAG T3nCMIFLAG [0..0]  =========================================== */
+typedef enum {                                  /*!< TIMER3n_INTFLAG_T3nCMIFLAG                                                */
+  TIMER3n_INTFLAG_T3nCMIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER3n_INTFLAG_T3nCMIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER3n_INTFLAG_T3nCMIFLAG_Enum;
+
+/* =========================================================  HIZCR  ========================================================= */
+/* ==============================================  TIMER3n HIZCR HIZEN [7..7]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_HIZCR_HIZEN                                                       */
+  TIMER3n_HIZCR_HIZEN_Disable          = 0,     /*!< Disable : Disable to control the output high-impedance.                   */
+  TIMER3n_HIZCR_HIZEN_Enable           = 1,     /*!< Enable : Enable to control the output high-impedance.                     */
+} TIMER3n_HIZCR_HIZEN_Enum;
+
+/* ==============================================  TIMER3n HIZCR HIZSW [4..4]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_HIZCR_HIZSW                                                       */
+  TIMER3n_HIZCR_HIZSW_NoEffect         = 0,     /*!< NoEffect : No effect.                                                     */
+  TIMER3n_HIZCR_HIZSW_HiZ              = 1,     /*!< HiZ : PWM3nxA/PWM3nxB pins go into high impedance. (Automatically
+                                                     cleared to '0' after operation)                                           */
+} TIMER3n_HIZCR_HIZSW_Enum;
+
+/* ==============================================  TIMER3n HIZCR HEDGE [2..2]  =============================================== */
+typedef enum {                                  /*!< TIMER3n_HIZCR_HEDGE                                                       */
+  TIMER3n_HIZCR_HEDGE_FallingEdge      = 0,     /*!< FallingEdge : Falling edge of the BLNK pin.                               */
+  TIMER3n_HIZCR_HEDGE_RisingEdge       = 1,     /*!< RisingEdge : Rising edge of the BLNK pin.                                 */
+} TIMER3n_HIZCR_HEDGE_Enum;
+
+/* ==============================================  TIMER3n HIZCR HIZSTA [1..1]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_HIZCR_HIZSTA                                                      */
+  TIMER3n_HIZCR_HIZSTA_NoHiZ           = 0,     /*!< NoHiZ : Indicates that the pins are not under a Hi-Z state.               */
+  TIMER3n_HIZCR_HIZSTA_HiZ             = 1,     /*!< HiZ : Indicates that the pins are under a Hi-Z state.                     */
+} TIMER3n_HIZCR_HIZSTA_Enum;
+
+/* ==============================================  TIMER3n HIZCR HIZCLR [0..0]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_HIZCR_HIZCLR                                                      */
+  TIMER3n_HIZCR_HIZCLR_NoEffect        = 0,     /*!< NoEffect : No effect.                                                     */
+  TIMER3n_HIZCR_HIZCLR_Clear           = 1,     /*!< Clear : Clear high-impedance output. (The PWM3nxA/PWM3nxB pins
+                                                     returns as output and this bit is automatically cleared
+                                                     to '0' after operation.)                                                  */
+} TIMER3n_HIZCR_HIZCLR_Enum;
+
+/* =========================================================  ADTCR  ========================================================= */
+/* =============================================  TIMER3n ADTCR T3nBTTG [4..4]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_ADTCR_T3nBTTG                                                     */
+  TIMER3n_ADTCR_T3nBTTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by bottom.                 */
+  TIMER3n_ADTCR_T3nBTTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by bottom.                   */
+} TIMER3n_ADTCR_T3nBTTG_Enum;
+
+/* =============================================  TIMER3n ADTCR T3nPMTG [3..3]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_ADTCR_T3nPMTG                                                     */
+  TIMER3n_ADTCR_T3nPMTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by period match.           */
+  TIMER3n_ADTCR_T3nPMTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by period match.             */
+} TIMER3n_ADTCR_T3nPMTG_Enum;
+
+/* =============================================  TIMER3n ADTCR T3nAMTG [2..2]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_ADTCR_T3nAMTG                                                     */
+  TIMER3n_ADTCR_T3nAMTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by A-ch match.             */
+  TIMER3n_ADTCR_T3nAMTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by A-ch match.               */
+} TIMER3n_ADTCR_T3nAMTG_Enum;
+
+/* =============================================  TIMER3n ADTCR T3nBMTG [1..1]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_ADTCR_T3nBMTG                                                     */
+  TIMER3n_ADTCR_T3nBMTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by B-ch match.             */
+  TIMER3n_ADTCR_T3nBMTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by B-ch match.               */
+} TIMER3n_ADTCR_T3nBMTG_Enum;
+
+/* =============================================  TIMER3n ADTCR T3nCMTG [0..0]  ============================================== */
+typedef enum {                                  /*!< TIMER3n_ADTCR_T3nCMTG                                                     */
+  TIMER3n_ADTCR_T3nCMTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by C-ch match.             */
+  TIMER3n_ADTCR_T3nCMTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by C-ch match.               */
+} TIMER3n_ADTCR_T3nCMTG_Enum;
+
+/* =========================================================  ADTDR  ========================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                          TIMER30                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ===============================================  TIMER30 CR T3nEN [15..15]  =============================================== */
+typedef enum {                                  /*!< TIMER30_CR_T3nEN                                                          */
+  TIMER30_CR_T3nEN_Disable             = 0,     /*!< Disable : Disable TIMER3n Operation.                                      */
+  TIMER30_CR_T3nEN_Enable              = 1,     /*!< Enable : Enable TIMER3n Operation. (Counter Clear and Start)              */
+} TIMER30_CR_T3nEN_Enum;
+
+/* ==============================================  TIMER30 CR T3nCLK [14..14]  =============================================== */
+typedef enum {                                  /*!< TIMER30_CR_T3nCLK                                                         */
+  TIMER30_CR_T3nCLK_IntPrescaledClock  = 0,     /*!< IntPrescaledClock : Select an Internal Prescaler Clock.                   */
+  TIMER30_CR_T3nCLK_ExtClock           = 1,     /*!< ExtClock : Select an External Clock.                                      */
+} TIMER30_CR_T3nCLK_Enum;
+
+/* ===============================================  TIMER30 CR T3nMS [12..13]  =============================================== */
+typedef enum {                                  /*!< TIMER30_CR_T3nMS                                                          */
+  TIMER30_CR_T3nMS_IntervalMode        = 0,     /*!< IntervalMode : Interval mode. (All match interrupts can occur)            */
+  TIMER30_CR_T3nMS_CaptureMode         = 1,     /*!< CaptureMode : Capture mode. (The Period-match interrupt can
+                                                     occur)                                                                    */
+  TIMER30_CR_T3nMS_BackToBackMode      = 2,     /*!< BackToBackMode : Back-to-back mode. (All interrupts can occur)            */
+} TIMER30_CR_T3nMS_Enum;
+
+/* ==============================================  TIMER30 CR T3nECE [11..11]  =============================================== */
+typedef enum {                                  /*!< TIMER30_CR_T3nECE                                                         */
+  TIMER30_CR_T3nECE_FallingEdge        = 0,     /*!< FallingEdge : Select falling edge of external clock.                      */
+  TIMER30_CR_T3nECE_RisingEdge         = 1,     /*!< RisingEdge : Select rising edge of external clock.                        */
+} TIMER30_CR_T3nECE_Enum;
+
+/* ===============================================  TIMER30 CR FORCA [10..10]  =============================================== */
+typedef enum {                                  /*!< TIMER30_CR_FORCA                                                          */
+  TIMER30_CR_FORCA_AllChannelMode      = 0,     /*!< AllChannelMode : 6-Channel mode. (The PWM3nxA/PWM3nxB pins are
+                                                     outputs according to the TIMER30_xDR registers, respectively.)            */
+  TIMER30_CR_FORCA_AChannelMode        = 1,     /*!< AChannelMode : Force A-Channel mode. (All PWM3nxA/PWM3nxB pins
+                                                     are outputs according only to the TIMER30_ADR register.)                  */
+} TIMER30_CR_FORCA_Enum;
+
+/* ================================================  TIMER30 CR DLYEN [9..9]  ================================================ */
+typedef enum {                                  /*!< TIMER30_CR_DLYEN                                                          */
+  TIMER30_CR_DLYEN_Disable             = 0,     /*!< Disable : Disable delay time insertion to the PWM3nxA/PWM3nxB.            */
+  TIMER30_CR_DLYEN_Enable              = 1,     /*!< Enable : Enable delay time insertion to the PWM3nxA/PWM3nxB.              */
+} TIMER30_CR_DLYEN_Enum;
+
+/* ===============================================  TIMER30 CR DLYPOS [8..8]  ================================================ */
+typedef enum {                                  /*!< TIMER30_CR_DLYPOS                                                         */
+  TIMER30_CR_DLYPOS_FrontABehindB      = 0,     /*!< FrontABehindB : Insert in front of PWM3nxA and behind PWM3nxB
+                                                     pins.                                                                     */
+  TIMER30_CR_DLYPOS_BehindAFrontB      = 1,     /*!< BehindAFrontB : Insert behind PWM3nxA and in front of PWM3nxB
+                                                     pins.                                                                     */
+} TIMER30_CR_DLYPOS_Enum;
+
+/* ===============================================  TIMER30 CR T3nCPOL [6..7]  =============================================== */
+typedef enum {                                  /*!< TIMER30_CR_T3nCPOL                                                        */
+  TIMER30_CR_T3nCPOL_FallingEdge       = 0,     /*!< FallingEdge : Capture on falling edge.                                    */
+  TIMER30_CR_T3nCPOL_RisingEdge        = 1,     /*!< RisingEdge : Capture on rising edge.                                      */
+  TIMER30_CR_T3nCPOL_BothEdge          = 2,     /*!< BothEdge : Capture on both falling and rising edge.                       */
+} TIMER30_CR_T3nCPOL_Enum;
+
+/* ================================================  TIMER30 CR UPDT [4..5]  ================================================= */
+typedef enum {                                  /*!< TIMER30_CR_UPDT                                                           */
+  TIMER30_CR_UPDT_AtWriting            = 0,     /*!< AtWriting : Update data to buffer at the time of writing.                 */
+  TIMER30_CR_UPDT_AtPeriodMatch        = 1,     /*!< AtPeriodMatch : Update data to buffer at period match.                    */
+  TIMER30_CR_UPDT_AtBottom             = 2,     /*!< AtBottom : Update data to buffer at bottom.                               */
+} TIMER30_CR_UPDT_Enum;
+
+/* ================================================  TIMER30 CR PMOC [1..3]  ================================================= */
+typedef enum {                                  /*!< TIMER30_CR_PMOC                                                           */
+  TIMER30_CR_PMOC_Every1PeriodMatch    = 0,     /*!< Every1PeriodMatch : Once every 1 period match.                            */
+  TIMER30_CR_PMOC_Every2PeriodMatch    = 1,     /*!< Every2PeriodMatch : Once every 2 period match.                            */
+  TIMER30_CR_PMOC_Every3PeriodMatch    = 2,     /*!< Every3PeriodMatch : Once every 3 period match.                            */
+  TIMER30_CR_PMOC_Every4PeriodMatch    = 3,     /*!< Every4PeriodMatch : Once every 4 period match.                            */
+  TIMER30_CR_PMOC_Every5PeriodMatch    = 4,     /*!< Every5PeriodMatch : Once every 5 period match.                            */
+  TIMER30_CR_PMOC_Every6PeriodMatch    = 5,     /*!< Every6PeriodMatch : Once every 6 period match.                            */
+  TIMER30_CR_PMOC_Every7PeriodMatch    = 6,     /*!< Every7PeriodMatch : Once every 7 period match.                            */
+  TIMER30_CR_PMOC_Every8PeriodMatch    = 7,     /*!< Every8PeriodMatch : Once every 8 period match.                            */
+} TIMER30_CR_PMOC_Enum;
+
+/* ===============================================  TIMER30 CR T3nCLR [0..0]  ================================================ */
+typedef enum {                                  /*!< TIMER30_CR_T3nCLR                                                         */
+  TIMER30_CR_T3nCLR_NoEffect           = 0,     /*!< NoEffect : No effect.                                                     */
+  TIMER30_CR_T3nCLR_Clear              = 1,     /*!< Clear : Clear TIMER3n counter and prescaler. (Automatically
+                                                     cleared to '0b' after operation)                                          */
+} TIMER30_CR_T3nCLR_Enum;
+
+/* ==========================================================  PDR  ========================================================== */
+/* ==========================================================  ADR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  CDR  ========================================================== */
+/* =========================================================  CAPDR  ========================================================= */
+/* =========================================================  PREDR  ========================================================= */
+/* ==========================================================  CNT  ========================================================== */
+/* =========================================================  OUTCR  ========================================================= */
+/* ==============================================  TIMER30 OUTCR POLB [15..15]  ============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_POLB                                                        */
+  TIMER30_OUTCR_POLB_StartLow          = 0,     /*!< StartLow : Low level start. (The PWM3nxB pins are started with
+                                                     low level after counting.)                                                */
+  TIMER30_OUTCR_POLB_StartHigh         = 1,     /*!< StartHigh : High level start. (The PWM3nxB pins are started
+                                                     with high level after counting)                                           */
+} TIMER30_OUTCR_POLB_Enum;
+
+/* ==============================================  TIMER30 OUTCR POLA [14..14]  ============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_POLA                                                        */
+  TIMER30_OUTCR_POLA_StartLow          = 0,     /*!< StartLow : Low level start. (The PWM3nxA pins are started with
+                                                     low level after counting.)                                                */
+  TIMER30_OUTCR_POLA_StartHigh         = 1,     /*!< StartHigh : High level start. (The PWM3nxA pins are started
+                                                     with high level after counting)                                           */
+} TIMER30_OUTCR_POLA_Enum;
+
+/* =============================================  TIMER30 OUTCR PABOE [13..13]  ============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_PABOE                                                       */
+  TIMER30_OUTCR_PABOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER30_OUTCR_PABOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER30_OUTCR_PABOE_Enum;
+
+/* =============================================  TIMER30 OUTCR PBBOE [12..12]  ============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_PBBOE                                                       */
+  TIMER30_OUTCR_PBBOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER30_OUTCR_PBBOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER30_OUTCR_PBBOE_Enum;
+
+/* =============================================  TIMER30 OUTCR PCBOE [11..11]  ============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_PCBOE                                                       */
+  TIMER30_OUTCR_PCBOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER30_OUTCR_PCBOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER30_OUTCR_PCBOE_Enum;
+
+/* =============================================  TIMER30 OUTCR PAAOE [10..10]  ============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_PAAOE                                                       */
+  TIMER30_OUTCR_PAAOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER30_OUTCR_PAAOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER30_OUTCR_PAAOE_Enum;
+
+/* ==============================================  TIMER30 OUTCR PBAOE [9..9]  =============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_PBAOE                                                       */
+  TIMER30_OUTCR_PBAOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER30_OUTCR_PBAOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER30_OUTCR_PBAOE_Enum;
+
+/* ==============================================  TIMER30 OUTCR PCAOE [8..8]  =============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_PCAOE                                                       */
+  TIMER30_OUTCR_PCAOE_Disable          = 0,     /*!< Disable : Disable output.                                                 */
+  TIMER30_OUTCR_PCAOE_Enable           = 1,     /*!< Enable : Enable output.                                                   */
+} TIMER30_OUTCR_PCAOE_Enum;
+
+/* ==============================================  TIMER30 OUTCR LVLAB [6..6]  =============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_LVLAB                                                       */
+  TIMER30_OUTCR_LVLAB_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER30_OUTCR_LVLAB_High             = 1,     /*!< High : High level.                                                        */
+} TIMER30_OUTCR_LVLAB_Enum;
+
+/* ==============================================  TIMER30 OUTCR LVLBB [5..5]  =============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_LVLBB                                                       */
+  TIMER30_OUTCR_LVLBB_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER30_OUTCR_LVLBB_High             = 1,     /*!< High : High level.                                                        */
+} TIMER30_OUTCR_LVLBB_Enum;
+
+/* ==============================================  TIMER30 OUTCR LVLCB [4..4]  =============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_LVLCB                                                       */
+  TIMER30_OUTCR_LVLCB_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER30_OUTCR_LVLCB_High             = 1,     /*!< High : High level.                                                        */
+} TIMER30_OUTCR_LVLCB_Enum;
+
+/* ==============================================  TIMER30 OUTCR LVLAA [2..2]  =============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_LVLAA                                                       */
+  TIMER30_OUTCR_LVLAA_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER30_OUTCR_LVLAA_High             = 1,     /*!< High : High level.                                                        */
+} TIMER30_OUTCR_LVLAA_Enum;
+
+/* ==============================================  TIMER30 OUTCR LVLBA [1..1]  =============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_LVLBA                                                       */
+  TIMER30_OUTCR_LVLBA_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER30_OUTCR_LVLBA_High             = 1,     /*!< High : High level.                                                        */
+} TIMER30_OUTCR_LVLBA_Enum;
+
+/* ==============================================  TIMER30 OUTCR LVLCA [0..0]  =============================================== */
+typedef enum {                                  /*!< TIMER30_OUTCR_LVLCA                                                       */
+  TIMER30_OUTCR_LVLCA_Low              = 0,     /*!< Low : Low level.                                                          */
+  TIMER30_OUTCR_LVLCA_High             = 1,     /*!< High : High level.                                                        */
+} TIMER30_OUTCR_LVLCA_Enum;
+
+/* ==========================================================  DLY  ========================================================== */
+/* =========================================================  INTCR  ========================================================= */
+/* ==============================================  TIMER30 INTCR HIZIEN [6..6]  ============================================== */
+typedef enum {                                  /*!< TIMER30_INTCR_HIZIEN                                                      */
+  TIMER30_INTCR_HIZIEN_Disable         = 0,     /*!< Disable : Disable TIMER3n output high-impedance interrupt.                */
+  TIMER30_INTCR_HIZIEN_Enable          = 1,     /*!< Enable : Enable TIMER3n output high-impedance interrupt.                  */
+} TIMER30_INTCR_HIZIEN_Enum;
+
+/* =============================================  TIMER30 INTCR T3nCIEN [5..5]  ============================================== */
+typedef enum {                                  /*!< TIMER30_INTCR_T3nCIEN                                                     */
+  TIMER30_INTCR_T3nCIEN_Disable        = 0,     /*!< Disable : Disable TIMER3n capture interrupt.                              */
+  TIMER30_INTCR_T3nCIEN_Enable         = 1,     /*!< Enable : Enable TIMER3n capture interrupt.                                */
+} TIMER30_INTCR_T3nCIEN_Enum;
+
+/* =============================================  TIMER30 INTCR T3nBTIEN [4..4]  ============================================= */
+typedef enum {                                  /*!< TIMER30_INTCR_T3nBTIEN                                                    */
+  TIMER30_INTCR_T3nBTIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n bottom interrupt.                               */
+  TIMER30_INTCR_T3nBTIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n bottom interrupt.                                 */
+} TIMER30_INTCR_T3nBTIEN_Enum;
+
+/* =============================================  TIMER30 INTCR T3nPMIEN [3..3]  ============================================= */
+typedef enum {                                  /*!< TIMER30_INTCR_T3nPMIEN                                                    */
+  TIMER30_INTCR_T3nPMIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n period interrupt.                               */
+  TIMER30_INTCR_T3nPMIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n period interrupt.                                 */
+} TIMER30_INTCR_T3nPMIEN_Enum;
+
+/* =============================================  TIMER30 INTCR T3nAMIEN [2..2]  ============================================= */
+typedef enum {                                  /*!< TIMER30_INTCR_T3nAMIEN                                                    */
+  TIMER30_INTCR_T3nAMIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n A-ch match interrupt.                           */
+  TIMER30_INTCR_T3nAMIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n A-ch match interrupt.                             */
+} TIMER30_INTCR_T3nAMIEN_Enum;
+
+/* =============================================  TIMER30 INTCR T3nBMIEN [1..1]  ============================================= */
+typedef enum {                                  /*!< TIMER30_INTCR_T3nBMIEN                                                    */
+  TIMER30_INTCR_T3nBMIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n B-ch match interrupt.                           */
+  TIMER30_INTCR_T3nBMIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n B-ch match interrupt.                             */
+} TIMER30_INTCR_T3nBMIEN_Enum;
+
+/* =============================================  TIMER30 INTCR T3nCMIEN [0..0]  ============================================= */
+typedef enum {                                  /*!< TIMER30_INTCR_T3nCMIEN                                                    */
+  TIMER30_INTCR_T3nCMIEN_Disable       = 0,     /*!< Disable : Disable TIMER3n C-ch match interrupt.                           */
+  TIMER30_INTCR_T3nCMIEN_Enable        = 1,     /*!< Enable : Enable TIMER3n C-ch match interrupt.                             */
+} TIMER30_INTCR_T3nCMIEN_Enum;
+
+/* ========================================================  INTFLAG  ======================================================== */
+/* ============================================  TIMER30 INTFLAG HIZIFLAG [6..6]  ============================================ */
+typedef enum {                                  /*!< TIMER30_INTFLAG_HIZIFLAG                                                  */
+  TIMER30_INTFLAG_HIZIFLAG_NoRequest   = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER30_INTFLAG_HIZIFLAG_Request     = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER30_INTFLAG_HIZIFLAG_Enum;
+
+/* ===========================================  TIMER30 INTFLAG T3nCIFLAG [5..5]  ============================================ */
+typedef enum {                                  /*!< TIMER30_INTFLAG_T3nCIFLAG                                                 */
+  TIMER30_INTFLAG_T3nCIFLAG_NoRequest  = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER30_INTFLAG_T3nCIFLAG_Request    = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER30_INTFLAG_T3nCIFLAG_Enum;
+
+/* ===========================================  TIMER30 INTFLAG T3nBTIFLAG [4..4]  =========================================== */
+typedef enum {                                  /*!< TIMER30_INTFLAG_T3nBTIFLAG                                                */
+  TIMER30_INTFLAG_T3nBTIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER30_INTFLAG_T3nBTIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER30_INTFLAG_T3nBTIFLAG_Enum;
+
+/* ===========================================  TIMER30 INTFLAG T3nPMIFLAG [3..3]  =========================================== */
+typedef enum {                                  /*!< TIMER30_INTFLAG_T3nPMIFLAG                                                */
+  TIMER30_INTFLAG_T3nPMIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER30_INTFLAG_T3nPMIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER30_INTFLAG_T3nPMIFLAG_Enum;
+
+/* ===========================================  TIMER30 INTFLAG T3nAMIFLAG [2..2]  =========================================== */
+typedef enum {                                  /*!< TIMER30_INTFLAG_T3nAMIFLAG                                                */
+  TIMER30_INTFLAG_T3nAMIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER30_INTFLAG_T3nAMIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER30_INTFLAG_T3nAMIFLAG_Enum;
+
+/* ===========================================  TIMER30 INTFLAG T3nBMIFLAG [1..1]  =========================================== */
+typedef enum {                                  /*!< TIMER30_INTFLAG_T3nBMIFLAG                                                */
+  TIMER30_INTFLAG_T3nBMIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER30_INTFLAG_T3nBMIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER30_INTFLAG_T3nBMIFLAG_Enum;
+
+/* ===========================================  TIMER30 INTFLAG T3nCMIFLAG [0..0]  =========================================== */
+typedef enum {                                  /*!< TIMER30_INTFLAG_T3nCMIFLAG                                                */
+  TIMER30_INTFLAG_T3nCMIFLAG_NoRequest = 0,     /*!< NoRequest : No request occurred.                                          */
+  TIMER30_INTFLAG_T3nCMIFLAG_Request   = 1,     /*!< Request : Request occurred. The bit will be cleared to '0' when
+                                                     '1' is written to this bit.                                               */
+} TIMER30_INTFLAG_T3nCMIFLAG_Enum;
+
+/* =========================================================  HIZCR  ========================================================= */
+/* ==============================================  TIMER30 HIZCR HIZEN [7..7]  =============================================== */
+typedef enum {                                  /*!< TIMER30_HIZCR_HIZEN                                                       */
+  TIMER30_HIZCR_HIZEN_Disable          = 0,     /*!< Disable : Disable to control the output high-impedance.                   */
+  TIMER30_HIZCR_HIZEN_Enable           = 1,     /*!< Enable : Enable to control the output high-impedance.                     */
+} TIMER30_HIZCR_HIZEN_Enum;
+
+/* ==============================================  TIMER30 HIZCR HIZSW [4..4]  =============================================== */
+typedef enum {                                  /*!< TIMER30_HIZCR_HIZSW                                                       */
+  TIMER30_HIZCR_HIZSW_NoEffect         = 0,     /*!< NoEffect : No effect.                                                     */
+  TIMER30_HIZCR_HIZSW_HiZ              = 1,     /*!< HiZ : PWM3nxA/PWM3nxB pins go into high impedance. (Automatically
+                                                     cleared to '0' after operation)                                           */
+} TIMER30_HIZCR_HIZSW_Enum;
+
+/* ==============================================  TIMER30 HIZCR HEDGE [2..2]  =============================================== */
+typedef enum {                                  /*!< TIMER30_HIZCR_HEDGE                                                       */
+  TIMER30_HIZCR_HEDGE_FallingEdge      = 0,     /*!< FallingEdge : Falling edge of the BLNK pin.                               */
+  TIMER30_HIZCR_HEDGE_RisingEdge       = 1,     /*!< RisingEdge : Rising edge of the BLNK pin.                                 */
+} TIMER30_HIZCR_HEDGE_Enum;
+
+/* ==============================================  TIMER30 HIZCR HIZSTA [1..1]  ============================================== */
+typedef enum {                                  /*!< TIMER30_HIZCR_HIZSTA                                                      */
+  TIMER30_HIZCR_HIZSTA_NoHiZ           = 0,     /*!< NoHiZ : Indicates that the pins are not under a Hi-Z state.               */
+  TIMER30_HIZCR_HIZSTA_HiZ             = 1,     /*!< HiZ : Indicates that the pins are under a Hi-Z state.                     */
+} TIMER30_HIZCR_HIZSTA_Enum;
+
+/* ==============================================  TIMER30 HIZCR HIZCLR [0..0]  ============================================== */
+typedef enum {                                  /*!< TIMER30_HIZCR_HIZCLR                                                      */
+  TIMER30_HIZCR_HIZCLR_NoEffect        = 0,     /*!< NoEffect : No effect.                                                     */
+  TIMER30_HIZCR_HIZCLR_Clear           = 1,     /*!< Clear : Clear high-impedance output. (The PWM3nxA/PWM3nxB pins
+                                                     returns as output and this bit is automatically cleared
+                                                     to '0' after operation.)                                                  */
+} TIMER30_HIZCR_HIZCLR_Enum;
+
+/* =========================================================  ADTCR  ========================================================= */
+/* =============================================  TIMER30 ADTCR T3nBTTG [4..4]  ============================================== */
+typedef enum {                                  /*!< TIMER30_ADTCR_T3nBTTG                                                     */
+  TIMER30_ADTCR_T3nBTTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by bottom.                 */
+  TIMER30_ADTCR_T3nBTTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by bottom.                   */
+} TIMER30_ADTCR_T3nBTTG_Enum;
+
+/* =============================================  TIMER30 ADTCR T3nPMTG [3..3]  ============================================== */
+typedef enum {                                  /*!< TIMER30_ADTCR_T3nPMTG                                                     */
+  TIMER30_ADTCR_T3nPMTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by period match.           */
+  TIMER30_ADTCR_T3nPMTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by period match.             */
+} TIMER30_ADTCR_T3nPMTG_Enum;
+
+/* =============================================  TIMER30 ADTCR T3nAMTG [2..2]  ============================================== */
+typedef enum {                                  /*!< TIMER30_ADTCR_T3nAMTG                                                     */
+  TIMER30_ADTCR_T3nAMTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by A-ch match.             */
+  TIMER30_ADTCR_T3nAMTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by A-ch match.               */
+} TIMER30_ADTCR_T3nAMTG_Enum;
+
+/* =============================================  TIMER30 ADTCR T3nBMTG [1..1]  ============================================== */
+typedef enum {                                  /*!< TIMER30_ADTCR_T3nBMTG                                                     */
+  TIMER30_ADTCR_T3nBMTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by B-ch match.             */
+  TIMER30_ADTCR_T3nBMTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by B-ch match.               */
+} TIMER30_ADTCR_T3nBMTG_Enum;
+
+/* =============================================  TIMER30 ADTCR T3nCMTG [0..0]  ============================================== */
+typedef enum {                                  /*!< TIMER30_ADTCR_T3nCMTG                                                     */
+  TIMER30_ADTCR_T3nCMTG_Disable        = 0,     /*!< Disable : Disable ADC trigger signal generator by C-ch match.             */
+  TIMER30_ADTCR_T3nCMTG_Enable         = 1,     /*!< Enable : Enable ADC trigger signal generator by C-ch match.               */
+} TIMER30_ADTCR_T3nCMTG_Enum;
+
+/* =========================================================  ADTDR  ========================================================= */
+/* =======================================================  T30_OUTCR  ======================================================= */
+/* ===========================================  TIMER30 T30_OUTCR WTIDKY [16..31]  =========================================== */
+typedef enum {                                  /*!< TIMER30_T30_OUTCR_WTIDKY                                                  */
+  TIMER30_T30_OUTCR_WTIDKY_Value       = 57452, /*!< Value : Key Value (0xe06c)                                                */
+} TIMER30_T30_OUTCR_WTIDKY_Enum;
+
+
+
+/* =========================================================================================================================== */
+/* ================                                            ADC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* =================================================  ADC CR ADCEN [15..15]  ================================================= */
+typedef enum {                                  /*!< ADC_CR_ADCEN                                                              */
+  ADC_CR_ADCEN_Disable                 = 0,     /*!< Disable : Disable ADC module operation.                                   */
+  ADC_CR_ADCEN_Enable                  = 1,     /*!< Enable : Enable ADC module operation.                                     */
+} ADC_CR_ADCEN_Enum;
+
+/* =================================================  ADC CR TRIG [11..13]  ================================================== */
+typedef enum {                                  /*!< ADC_CR_TRIG                                                               */
+  ADC_CR_TRIG_ADST                     = 0,     /*!< ADST : Select ADST.                                                       */
+  ADC_CR_TRIG_TIMER10                  = 1,     /*!< TIMER10 : Select TIMER10 A-Match Signal.                                  */
+  ADC_CR_TRIG_TIMER11                  = 2,     /*!< TIMER11 : Select TIMER11 A-Match Signal.                                  */
+  ADC_CR_TRIG_TIMER12                  = 3,     /*!< TIMER12 : Select TIMER12 A-Match Signal.                                  */
+  ADC_CR_TRIG_TIMER30                  = 4,     /*!< TIMER30 : Select ADC Trigger Signal from TIMER30.                         */
+} ADC_CR_TRIG_Enum;
+
+/* ================================================  ADC CR REFSEL [10..10]  ================================================= */
+typedef enum {                                  /*!< ADC_CR_REFSEL                                                             */
+  ADC_CR_REFSEL_Vdd                    = 0,     /*!< Vdd : Select analog power (VDD).                                          */
+  ADC_CR_REFSEL_AVref                  = 1,     /*!< AVref : Select external reference (AVREF).                                */
+} ADC_CR_REFSEL_Enum;
+
+/* ==================================================  ADC CR ADST [8..8]  =================================================== */
+typedef enum {                                  /*!< ADC_CR_ADST                                                               */
+  ADC_CR_ADST_NoEffect                 = 0,     /*!< NoEffect : No effect.                                                     */
+  ADC_CR_ADST_Start                    = 1,     /*!< Start : Trigger signal generation for conversion start.                   */
+} ADC_CR_ADST_Enum;
+
+/* =================================================  ADC CR ADCIEN [5..5]  ================================================== */
+typedef enum {                                  /*!< ADC_CR_ADCIEN                                                             */
+  ADC_CR_ADCIEN_Disable                = 0,     /*!< Disable : Disable ADC interrupt.                                          */
+  ADC_CR_ADCIEN_Enable                 = 1,     /*!< Enable : Enable ADC interrupt.                                            */
+} ADC_CR_ADCIEN_Enum;
+
+/* ================================================  ADC CR ADCIFLAG [4..4]  ================================================= */
+typedef enum {                                  /*!< ADC_CR_ADCIFLAG                                                           */
+  ADC_CR_ADCIFLAG_NoRequest            = 0,     /*!< NoRequest : No request occurred.                                          */
+  ADC_CR_ADCIFLAG_Request              = 1,     /*!< Request : Request occurred.                                               */
+} ADC_CR_ADCIFLAG_Enum;
+
+/* ==================================================  ADC CR ADSEL [0..3]  ================================================== */
+typedef enum {                                  /*!< ADC_CR_ADSEL                                                              */
+  ADC_CR_ADSEL_AN0                     = 0,     /*!< AN0 : Select AN0.                                                         */
+  ADC_CR_ADSEL_AN1                     = 1,     /*!< AN1 : Select AN1.                                                         */
+  ADC_CR_ADSEL_AN2                     = 2,     /*!< AN2 : Select AN2.                                                         */
+  ADC_CR_ADSEL_AN3                     = 3,     /*!< AN3 : Select AN3.                                                         */
+  ADC_CR_ADSEL_AN4                     = 4,     /*!< AN4 : Select AN4.                                                         */
+  ADC_CR_ADSEL_AN5                     = 5,     /*!< AN5 : Select AN5.                                                         */
+  ADC_CR_ADSEL_AN6                     = 6,     /*!< AN6 : Select AN6.                                                         */
+  ADC_CR_ADSEL_AN7                     = 7,     /*!< AN7 : Select AN7.                                                         */
+  ADC_CR_ADSEL_AN8                     = 8,     /*!< AN8 : Select AN8.                                                         */
+  ADC_CR_ADSEL_AN9                     = 9,     /*!< AN9 : Select AN9.                                                         */
+  ADC_CR_ADSEL_AN10                    = 10,    /*!< AN10 : Select AN10.                                                       */
+  ADC_CR_ADSEL_AN11                    = 11,    /*!< AN11 : Select AN11                                                        */
+  ADC_CR_ADSEL_AN12                    = 12,    /*!< AN12 : Select AN12                                                        */
+  ADC_CR_ADSEL_AN13                    = 13,    /*!< AN13 : Select AN13                                                        */
+} ADC_CR_ADSEL_Enum;
+
+/* ==========================================================  DR  =========================================================== */
+/* =========================================================  PREDR  ========================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART1n                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+/* ==============================================  USART1n CR1 USTnMS [14..15]  ============================================== */
+typedef enum {                                  /*!< USART1n_CR1_USTnMS                                                        */
+  USART1n_CR1_USTnMS_Async             = 0,     /*!< Async : Asynchronous Mode (UART)                                          */
+  USART1n_CR1_USTnMS_Sync              = 1,     /*!< Sync : Synchronous Mode (USRT)                                            */
+  USART1n_CR1_USTnMS_SPI               = 3,     /*!< SPI : SPI Mode                                                            */
+} USART1n_CR1_USTnMS_Enum;
+
+/* ==============================================  USART1n CR1 USTnP [12..13]  =============================================== */
+typedef enum {                                  /*!< USART1n_CR1_USTnP                                                         */
+  USART1n_CR1_USTnP_No                 = 0,     /*!< No : No Parity                                                            */
+  USART1n_CR1_USTnP_Even               = 2,     /*!< Even : Even Parity                                                        */
+  USART1n_CR1_USTnP_Odd                = 3,     /*!< Odd : Odd Parity                                                          */
+} USART1n_CR1_USTnP_Enum;
+
+/* ===============================================  USART1n CR1 USTnS [9..11]  =============================================== */
+typedef enum {                                  /*!< USART1n_CR1_USTnS                                                         */
+  USART1n_CR1_USTnS_5bit               = 0,     /*!< 5bit : 5 bit                                                              */
+  USART1n_CR1_USTnS_6bit               = 1,     /*!< 6bit : 6 bit                                                              */
+  USART1n_CR1_USTnS_7bit               = 2,     /*!< 7bit : 7 bit                                                              */
+  USART1n_CR1_USTnS_8bit               = 3,     /*!< 8bit : 8 bit                                                              */
+  USART1n_CR1_USTnS_9bit               = 7,     /*!< 9bit : 9 bit                                                              */
+} USART1n_CR1_USTnS_Enum;
+
+/* ================================================  USART1n CR1 ORDn [8..8]  ================================================ */
+typedef enum {                                  /*!< USART1n_CR1_ORDn                                                          */
+  USART1n_CR1_ORDn_lsbFirst            = 0,     /*!< lsbFirst : LSB First                                                      */
+  USART1n_CR1_ORDn_msbFirst            = 1,     /*!< msbFirst : MSB First                                                      */
+} USART1n_CR1_ORDn_Enum;
+
+/* ===============================================  USART1n CR1 CPOLn [7..7]  ================================================ */
+typedef enum {                                  /*!< USART1n_CR1_CPOLn                                                         */
+  USART1n_CR1_CPOLn_IdleLow            = 0,     /*!< IdleLow : TXD Change @Rising Edge, RXD Change @Falling Edge               */
+  USART1n_CR1_CPOLn_IdleHigh           = 1,     /*!< IdleHigh : TXD Change @Falling Edge, RXD Change @Rising Edge              */
+} USART1n_CR1_CPOLn_Enum;
+
+/* ===============================================  USART1n CR1 CPHAn [6..6]  ================================================ */
+typedef enum {                                  /*!< USART1n_CR1_CPHAn                                                         */
+  USART1n_CR1_CPHAn_StartIdle          = 0,     /*!< StartIdle : Start with idle state.                                        */
+  USART1n_CR1_CPHAn_StartInverted      = 1,     /*!< StartInverted : Start with inverted idle state.                           */
+} USART1n_CR1_CPHAn_Enum;
+
+/* ==========================================================  CR2  ========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART10                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+/* ==============================================  USART10 CR1 USTnMS [14..15]  ============================================== */
+typedef enum {                                  /*!< USART10_CR1_USTnMS                                                        */
+  USART10_CR1_USTnMS_Async             = 0,     /*!< Async : Asynchronous Mode (UART)                                          */
+  USART10_CR1_USTnMS_Sync              = 1,     /*!< Sync : Synchronous Mode (USRT)                                            */
+  USART10_CR1_USTnMS_SPI               = 3,     /*!< SPI : SPI Mode                                                            */
+} USART10_CR1_USTnMS_Enum;
+
+/* ==============================================  USART10 CR1 USTnP [12..13]  =============================================== */
+typedef enum {                                  /*!< USART10_CR1_USTnP                                                         */
+  USART10_CR1_USTnP_No                 = 0,     /*!< No : No Parity                                                            */
+  USART10_CR1_USTnP_Even               = 2,     /*!< Even : Even Parity                                                        */
+  USART10_CR1_USTnP_Odd                = 3,     /*!< Odd : Odd Parity                                                          */
+} USART10_CR1_USTnP_Enum;
+
+/* ===============================================  USART10 CR1 USTnS [9..11]  =============================================== */
+typedef enum {                                  /*!< USART10_CR1_USTnS                                                         */
+  USART10_CR1_USTnS_5bit               = 0,     /*!< 5bit : 5 bit                                                              */
+  USART10_CR1_USTnS_6bit               = 1,     /*!< 6bit : 6 bit                                                              */
+  USART10_CR1_USTnS_7bit               = 2,     /*!< 7bit : 7 bit                                                              */
+  USART10_CR1_USTnS_8bit               = 3,     /*!< 8bit : 8 bit                                                              */
+  USART10_CR1_USTnS_9bit               = 7,     /*!< 9bit : 9 bit                                                              */
+} USART10_CR1_USTnS_Enum;
+
+/* ================================================  USART10 CR1 ORDn [8..8]  ================================================ */
+typedef enum {                                  /*!< USART10_CR1_ORDn                                                          */
+  USART10_CR1_ORDn_lsbFirst            = 0,     /*!< lsbFirst : LSB First                                                      */
+  USART10_CR1_ORDn_msbFirst            = 1,     /*!< msbFirst : MSB First                                                      */
+} USART10_CR1_ORDn_Enum;
+
+/* ===============================================  USART10 CR1 CPOLn [7..7]  ================================================ */
+typedef enum {                                  /*!< USART10_CR1_CPOLn                                                         */
+  USART10_CR1_CPOLn_IdleLow            = 0,     /*!< IdleLow : TXD Change @Rising Edge, RXD Change @Falling Edge               */
+  USART10_CR1_CPOLn_IdleHigh           = 1,     /*!< IdleHigh : TXD Change @Falling Edge, RXD Change @Rising Edge              */
+} USART10_CR1_CPOLn_Enum;
+
+/* ===============================================  USART10 CR1 CPHAn [6..6]  ================================================ */
+typedef enum {                                  /*!< USART10_CR1_CPHAn                                                         */
+  USART10_CR1_CPHAn_StartIdle          = 0,     /*!< StartIdle : Start with idle state.                                        */
+  USART10_CR1_CPHAn_StartInverted      = 1,     /*!< StartInverted : Start with inverted idle state.                           */
+} USART10_CR1_CPHAn_Enum;
+
+/* ==========================================================  CR2  ========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART11                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+/* ==============================================  USART11 CR1 USTnMS [14..15]  ============================================== */
+typedef enum {                                  /*!< USART11_CR1_USTnMS                                                        */
+  USART11_CR1_USTnMS_Async             = 0,     /*!< Async : Asynchronous Mode (UART)                                          */
+  USART11_CR1_USTnMS_Sync              = 1,     /*!< Sync : Synchronous Mode (USRT)                                            */
+  USART11_CR1_USTnMS_SPI               = 3,     /*!< SPI : SPI Mode                                                            */
+} USART11_CR1_USTnMS_Enum;
+
+/* ==============================================  USART11 CR1 USTnP [12..13]  =============================================== */
+typedef enum {                                  /*!< USART11_CR1_USTnP                                                         */
+  USART11_CR1_USTnP_No                 = 0,     /*!< No : No Parity                                                            */
+  USART11_CR1_USTnP_Even               = 2,     /*!< Even : Even Parity                                                        */
+  USART11_CR1_USTnP_Odd                = 3,     /*!< Odd : Odd Parity                                                          */
+} USART11_CR1_USTnP_Enum;
+
+/* ===============================================  USART11 CR1 USTnS [9..11]  =============================================== */
+typedef enum {                                  /*!< USART11_CR1_USTnS                                                         */
+  USART11_CR1_USTnS_5bit               = 0,     /*!< 5bit : 5 bit                                                              */
+  USART11_CR1_USTnS_6bit               = 1,     /*!< 6bit : 6 bit                                                              */
+  USART11_CR1_USTnS_7bit               = 2,     /*!< 7bit : 7 bit                                                              */
+  USART11_CR1_USTnS_8bit               = 3,     /*!< 8bit : 8 bit                                                              */
+  USART11_CR1_USTnS_9bit               = 7,     /*!< 9bit : 9 bit                                                              */
+} USART11_CR1_USTnS_Enum;
+
+/* ================================================  USART11 CR1 ORDn [8..8]  ================================================ */
+typedef enum {                                  /*!< USART11_CR1_ORDn                                                          */
+  USART11_CR1_ORDn_lsbFirst            = 0,     /*!< lsbFirst : LSB First                                                      */
+  USART11_CR1_ORDn_msbFirst            = 1,     /*!< msbFirst : MSB First                                                      */
+} USART11_CR1_ORDn_Enum;
+
+/* ===============================================  USART11 CR1 CPOLn [7..7]  ================================================ */
+typedef enum {                                  /*!< USART11_CR1_CPOLn                                                         */
+  USART11_CR1_CPOLn_IdleLow            = 0,     /*!< IdleLow : TXD Change @Rising Edge, RXD Change @Falling Edge               */
+  USART11_CR1_CPOLn_IdleHigh           = 1,     /*!< IdleHigh : TXD Change @Falling Edge, RXD Change @Rising Edge              */
+} USART11_CR1_CPOLn_Enum;
+
+/* ===============================================  USART11 CR1 CPHAn [6..6]  ================================================ */
+typedef enum {                                  /*!< USART11_CR1_CPHAn                                                         */
+  USART11_CR1_CPHAn_StartIdle          = 0,     /*!< StartIdle : Start with idle state.                                        */
+  USART11_CR1_CPHAn_StartInverted      = 1,     /*!< StartInverted : Start with inverted idle state.                           */
+} USART11_CR1_CPHAn_Enum;
+
+/* ==========================================================  CR2  ========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART12                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+/* ==============================================  USART12 CR1 USTnMS [14..15]  ============================================== */
+typedef enum {                                  /*!< USART12_CR1_USTnMS                                                        */
+  USART12_CR1_USTnMS_Async             = 0,     /*!< Async : Asynchronous Mode (UART)                                          */
+  USART12_CR1_USTnMS_Sync              = 1,     /*!< Sync : Synchronous Mode (USRT)                                            */
+  USART12_CR1_USTnMS_SPI               = 3,     /*!< SPI : SPI Mode                                                            */
+} USART12_CR1_USTnMS_Enum;
+
+/* ==============================================  USART12 CR1 USTnP [12..13]  =============================================== */
+typedef enum {                                  /*!< USART12_CR1_USTnP                                                         */
+  USART12_CR1_USTnP_No                 = 0,     /*!< No : No Parity                                                            */
+  USART12_CR1_USTnP_Even               = 2,     /*!< Even : Even Parity                                                        */
+  USART12_CR1_USTnP_Odd                = 3,     /*!< Odd : Odd Parity                                                          */
+} USART12_CR1_USTnP_Enum;
+
+/* ===============================================  USART12 CR1 USTnS [9..11]  =============================================== */
+typedef enum {                                  /*!< USART12_CR1_USTnS                                                         */
+  USART12_CR1_USTnS_5bit               = 0,     /*!< 5bit : 5 bit                                                              */
+  USART12_CR1_USTnS_6bit               = 1,     /*!< 6bit : 6 bit                                                              */
+  USART12_CR1_USTnS_7bit               = 2,     /*!< 7bit : 7 bit                                                              */
+  USART12_CR1_USTnS_8bit               = 3,     /*!< 8bit : 8 bit                                                              */
+  USART12_CR1_USTnS_9bit               = 7,     /*!< 9bit : 9 bit                                                              */
+} USART12_CR1_USTnS_Enum;
+
+/* ================================================  USART12 CR1 ORDn [8..8]  ================================================ */
+typedef enum {                                  /*!< USART12_CR1_ORDn                                                          */
+  USART12_CR1_ORDn_lsbFirst            = 0,     /*!< lsbFirst : LSB First                                                      */
+  USART12_CR1_ORDn_msbFirst            = 1,     /*!< msbFirst : MSB First                                                      */
+} USART12_CR1_ORDn_Enum;
+
+/* ===============================================  USART12 CR1 CPOLn [7..7]  ================================================ */
+typedef enum {                                  /*!< USART12_CR1_CPOLn                                                         */
+  USART12_CR1_CPOLn_IdleLow            = 0,     /*!< IdleLow : TXD Change @Rising Edge, RXD Change @Falling Edge               */
+  USART12_CR1_CPOLn_IdleHigh           = 1,     /*!< IdleHigh : TXD Change @Falling Edge, RXD Change @Rising Edge              */
+} USART12_CR1_CPOLn_Enum;
+
+/* ===============================================  USART12 CR1 CPHAn [6..6]  ================================================ */
+typedef enum {                                  /*!< USART12_CR1_CPHAn                                                         */
+  USART12_CR1_CPHAn_StartIdle          = 0,     /*!< StartIdle : Start with idle state.                                        */
+  USART12_CR1_CPHAn_StartInverted      = 1,     /*!< StartInverted : Start with inverted idle state.                           */
+} USART12_CR1_CPHAn_Enum;
+
+/* ==========================================================  CR2  ========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                          USART13                                          ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR1  ========================================================== */
+/* ==============================================  USART13 CR1 USTnMS [14..15]  ============================================== */
+typedef enum {                                  /*!< USART13_CR1_USTnMS                                                        */
+  USART13_CR1_USTnMS_Async             = 0,     /*!< Async : Asynchronous Mode (UART)                                          */
+  USART13_CR1_USTnMS_Sync              = 1,     /*!< Sync : Synchronous Mode (USRT)                                            */
+  USART13_CR1_USTnMS_SPI               = 3,     /*!< SPI : SPI Mode                                                            */
+} USART13_CR1_USTnMS_Enum;
+
+/* ==============================================  USART13 CR1 USTnP [12..13]  =============================================== */
+typedef enum {                                  /*!< USART13_CR1_USTnP                                                         */
+  USART13_CR1_USTnP_No                 = 0,     /*!< No : No Parity                                                            */
+  USART13_CR1_USTnP_Even               = 2,     /*!< Even : Even Parity                                                        */
+  USART13_CR1_USTnP_Odd                = 3,     /*!< Odd : Odd Parity                                                          */
+} USART13_CR1_USTnP_Enum;
+
+/* ===============================================  USART13 CR1 USTnS [9..11]  =============================================== */
+typedef enum {                                  /*!< USART13_CR1_USTnS                                                         */
+  USART13_CR1_USTnS_5bit               = 0,     /*!< 5bit : 5 bit                                                              */
+  USART13_CR1_USTnS_6bit               = 1,     /*!< 6bit : 6 bit                                                              */
+  USART13_CR1_USTnS_7bit               = 2,     /*!< 7bit : 7 bit                                                              */
+  USART13_CR1_USTnS_8bit               = 3,     /*!< 8bit : 8 bit                                                              */
+  USART13_CR1_USTnS_9bit               = 7,     /*!< 9bit : 9 bit                                                              */
+} USART13_CR1_USTnS_Enum;
+
+/* ================================================  USART13 CR1 ORDn [8..8]  ================================================ */
+typedef enum {                                  /*!< USART13_CR1_ORDn                                                          */
+  USART13_CR1_ORDn_lsbFirst            = 0,     /*!< lsbFirst : LSB First                                                      */
+  USART13_CR1_ORDn_msbFirst            = 1,     /*!< msbFirst : MSB First                                                      */
+} USART13_CR1_ORDn_Enum;
+
+/* ===============================================  USART13 CR1 CPOLn [7..7]  ================================================ */
+typedef enum {                                  /*!< USART13_CR1_CPOLn                                                         */
+  USART13_CR1_CPOLn_IdleLow            = 0,     /*!< IdleLow : TXD Change @Rising Edge, RXD Change @Falling Edge               */
+  USART13_CR1_CPOLn_IdleHigh           = 1,     /*!< IdleHigh : TXD Change @Falling Edge, RXD Change @Rising Edge              */
+} USART13_CR1_CPOLn_Enum;
+
+/* ===============================================  USART13 CR1 CPHAn [6..6]  ================================================ */
+typedef enum {                                  /*!< USART13_CR1_CPHAn                                                         */
+  USART13_CR1_CPHAn_StartIdle          = 0,     /*!< StartIdle : Start with idle state.                                        */
+  USART13_CR1_CPHAn_StartInverted      = 1,     /*!< StartInverted : Start with inverted idle state.                           */
+} USART13_CR1_CPHAn_Enum;
+
+/* ==========================================================  CR2  ========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           UARTn                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  RBR  ========================================================== */
+/* ==========================================================  THR  ========================================================== */
+/* ==========================================================  IER  ========================================================== */
+/* ==========================================================  IIR  ========================================================== */
+/* ==========================================================  LCR  ========================================================== */
+/* ==========================================================  DCR  ========================================================== */
+/* ==========================================================  LSR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  BFR  ========================================================== */
+/* =================================================  UARTn BFR BFR [0..7]  ================================================== */
+typedef enum {                                  /*!< UARTn_BFR_BFR                                                             */
+  UARTn_BFR_BFR_Disable                = 0,     /*!< Disable : Disable fraction counter.                                       */
+} UARTn_BFR_BFR_Enum;
+
+/* =========================================================  IDTR  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           UART0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  RBR  ========================================================== */
+/* ==========================================================  THR  ========================================================== */
+/* ==========================================================  IER  ========================================================== */
+/* ==========================================================  IIR  ========================================================== */
+/* ==========================================================  LCR  ========================================================== */
+/* ==========================================================  DCR  ========================================================== */
+/* ==========================================================  LSR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  BFR  ========================================================== */
+/* =================================================  UART0 BFR BFR [0..7]  ================================================== */
+typedef enum {                                  /*!< UART0_BFR_BFR                                                             */
+  UART0_BFR_BFR_Disable                = 0,     /*!< Disable : Disable fraction counter.                                       */
+} UART0_BFR_BFR_Enum;
+
+/* =========================================================  IDTR  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           UART1                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  RBR  ========================================================== */
+/* ==========================================================  THR  ========================================================== */
+/* ==========================================================  IER  ========================================================== */
+/* ==========================================================  IIR  ========================================================== */
+/* ==========================================================  LCR  ========================================================== */
+/* ==========================================================  DCR  ========================================================== */
+/* ==========================================================  LSR  ========================================================== */
+/* ==========================================================  BDR  ========================================================== */
+/* ==========================================================  BFR  ========================================================== */
+/* =================================================  UART1 BFR BFR [0..7]  ================================================== */
+typedef enum {                                  /*!< UART1_BFR_BFR                                                             */
+  UART1_BFR_BFR_Disable                = 0,     /*!< Disable : Disable fraction counter.                                       */
+} UART1_BFR_BFR_Enum;
+
+/* =========================================================  IDTR  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2Cn                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* =========================================================  SAR1  ========================================================== */
+/* =========================================================  SAR2  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+/* =========================================================  SDHR  ========================================================== */
+/* =========================================================  SCLR  ========================================================== */
+/* =========================================================  SCHR  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C0                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* =========================================================  SAR1  ========================================================== */
+/* =========================================================  SAR2  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+/* =========================================================  SDHR  ========================================================== */
+/* =========================================================  SCLR  ========================================================== */
+/* =========================================================  SCHR  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C1                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* =========================================================  SAR1  ========================================================== */
+/* =========================================================  SAR2  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+/* =========================================================  SDHR  ========================================================== */
+/* =========================================================  SCLR  ========================================================== */
+/* =========================================================  SCHR  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           I2C2                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==========================================================  ST  =========================================================== */
+/* =========================================================  SAR1  ========================================================== */
+/* =========================================================  SAR2  ========================================================== */
+/* ==========================================================  DR  =========================================================== */
+/* =========================================================  SDHR  ========================================================== */
+/* =========================================================  SCLR  ========================================================== */
+/* =========================================================  SCHR  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                            LCD                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==================================================  LCD CR IRSEL [6..7]  ================================================== */
+typedef enum {                                  /*!< LCD_CR_IRSEL                                                              */
+  LCD_CR_IRSEL_RLCD3                   = 0,     /*!< RLCD3 : RLCD3: 105/105/80[kohm] @(1/2)/(1/3)/(1/4) bias                   */
+  LCD_CR_IRSEL_RLCD1                   = 1,     /*!< RLCD1 : RLCD1: 10/10/10[kohm] @(1/2)/(1/3)/(1/4) bias                     */
+  LCD_CR_IRSEL_RLCD2                   = 2,     /*!< RLCD2 : RLCD2: 66/66/50[kohm] @(1/2)/(1/3)/(1/4) bias                     */
+  LCD_CR_IRSEL_RLCD4                   = 3,     /*!< RLCD4 : RLCD4: 320/320/240[kohm] @(1/2)/(1/3)/(1/4) bias                  */
+} LCD_CR_IRSEL_Enum;
+
+/* ===================================================  LCD CR DBS [3..5]  =================================================== */
+typedef enum {                                  /*!< LCD_CR_DBS                                                                */
+  LCD_CR_DBS_Duty8Bias4                = 0,     /*!< Duty8Bias4 : 1/8 duty, 1/4 bias                                           */
+  LCD_CR_DBS_Duty6Bias4                = 1,     /*!< Duty6Bias4 : 1/6 duty, 1/4 bias                                           */
+  LCD_CR_DBS_Duty5Bias3                = 2,     /*!< Duty5Bias3 : 1/5 duty, 1/3 bias                                           */
+  LCD_CR_DBS_Duty4Bias3                = 3,     /*!< Duty4Bias3 : 1/4 duty, 1/3 bias                                           */
+  LCD_CR_DBS_Duty3Bias3                = 4,     /*!< Duty3Bias3 : 1/3 duty, 1/3 bias                                           */
+  LCD_CR_DBS_Duty3Bias2                = 5,     /*!< Duty3Bias2 : 1/3 duty, 1/2 bias                                           */
+} LCD_CR_DBS_Enum;
+
+/* ==================================================  LCD CR LCLK [1..2]  =================================================== */
+typedef enum {                                  /*!< LCD_CR_LCLK                                                               */
+  LCD_CR_LCLK_fLCD256                  = 0,     /*!< fLCD256 : 128Hz                                                           */
+  LCD_CR_LCLK_fLCD128                  = 1,     /*!< fLCD128 : 256Hz                                                           */
+  LCD_CR_LCLK_fLCD64                   = 2,     /*!< fLCD64 : 512Hz                                                            */
+  LCD_CR_LCLK_fLCD32                   = 3,     /*!< fLCD32 : 1024Hz                                                           */
+} LCD_CR_LCLK_Enum;
+
+/* ==================================================  LCD CR DISP [0..0]  =================================================== */
+typedef enum {                                  /*!< LCD_CR_DISP                                                               */
+  LCD_CR_DISP_Off                      = 0,     /*!< Off : Display off                                                         */
+  LCD_CR_DISP_On                       = 1,     /*!< On : Normal display on                                                    */
+} LCD_CR_DISP_Enum;
+
+/* =========================================================  BCCR  ========================================================== */
+/* ===============================================  LCD BCCR LCDABC [12..12]  ================================================ */
+typedef enum {                                  /*!< LCD_BCCR_LCDABC                                                           */
+  LCD_BCCR_LCDABC_Off                  = 0,     /*!< Off : LCD automatic bias is off                                           */
+  LCD_BCCR_LCDABC_On                   = 1,     /*!< On : LCD automatic bias is on                                             */
+} LCD_BCCR_LCDABC_Enum;
+
+/* ================================================  LCD BCCR BMSEL [8..10]  ================================================= */
+typedef enum {                                  /*!< LCD_BCCR_BMSEL                                                            */
+  LCD_BCCR_BMSEL_BMA1Clk               = 0,     /*!< BMA1Clk : 'Bias Mode A' for 1-clock of fLCD                               */
+  LCD_BCCR_BMSEL_BMA2Clk               = 1,     /*!< BMA2Clk : 'Bias Mode A' for 2-clock of fLCD                               */
+  LCD_BCCR_BMSEL_BMA3Clk               = 2,     /*!< BMA3Clk : 'Bias Mode A' for 3-clock of fLCD                               */
+  LCD_BCCR_BMSEL_BMA4Clk               = 3,     /*!< BMA4Clk : 'Bias Mode A' for 4-clock of fLCD                               */
+  LCD_BCCR_BMSEL_BMA5Clk               = 4,     /*!< BMA5Clk : 'Bias Mode A' for 5-clock of fLCD                               */
+  LCD_BCCR_BMSEL_BMA6Clk               = 5,     /*!< BMA6Clk : 'Bias Mode A' for 6-clock of fLCD                               */
+  LCD_BCCR_BMSEL_BMA7Clk               = 6,     /*!< BMA7Clk : 'Bias Mode A' for 7-clock of fLCD                               */
+  LCD_BCCR_BMSEL_BMA8Clk               = 7,     /*!< BMA8Clk : 'Bias Mode A' for 8-clock of fLCD                               */
+} LCD_BCCR_BMSEL_Enum;
+
+/* =================================================  LCD BCCR LCTEN [5..5]  ================================================= */
+typedef enum {                                  /*!< LCD_BCCR_LCTEN                                                            */
+  LCD_BCCR_LCTEN_Disable               = 0,     /*!< Disable : Disable LCD driver contrast.                                    */
+  LCD_BCCR_LCTEN_Enable                = 1,     /*!< Enable : Enable LCD driver contrast.                                      */
+} LCD_BCCR_LCTEN_Enum;
+
+/* =================================================  LCD BCCR VLCD [0..3]  ================================================== */
+typedef enum {                                  /*!< LCD_BCCR_VLCD                                                             */
+  LCD_BCCR_VLCD_Step0                  = 0,     /*!< Step0 : VDD x 16/31 Step                                                  */
+  LCD_BCCR_VLCD_Step1                  = 1,     /*!< Step1 : VDD x 16/30 Step                                                  */
+  LCD_BCCR_VLCD_Step2                  = 2,     /*!< Step2 : VDD x 16/29 Step                                                  */
+  LCD_BCCR_VLCD_Step3                  = 3,     /*!< Step3 : VDD x 16/28 Step                                                  */
+  LCD_BCCR_VLCD_Step4                  = 4,     /*!< Step4 : VDD x 16/27 Step                                                  */
+  LCD_BCCR_VLCD_Step5                  = 5,     /*!< Step5 : VDD x 16/26 Step                                                  */
+  LCD_BCCR_VLCD_Step6                  = 6,     /*!< Step6 : VDD x 16/25 Step                                                  */
+  LCD_BCCR_VLCD_Step7                  = 7,     /*!< Step7 : VDD x 16/24 Step                                                  */
+  LCD_BCCR_VLCD_Step8                  = 8,     /*!< Step8 : VDD x 16/23 Step                                                  */
+  LCD_BCCR_VLCD_Step9                  = 9,     /*!< Step9 : VDD x 16/22 Step                                                  */
+  LCD_BCCR_VLCD_Step10                 = 10,    /*!< Step10 : VDD x 16/21 Step                                                 */
+  LCD_BCCR_VLCD_Step11                 = 11,    /*!< Step11 : VDD x 16/20 Step                                                 */
+  LCD_BCCR_VLCD_Step12                 = 12,    /*!< Step12 : VDD x 16/19 Step                                                 */
+  LCD_BCCR_VLCD_Step13                 = 13,    /*!< Step13 : VDD x 16/18 Step                                                 */
+  LCD_BCCR_VLCD_Step14                 = 14,    /*!< Step14 : VDD x 16/17 Step                                                 */
+  LCD_BCCR_VLCD_Step15                 = 15,    /*!< Step15 : VDD x 16/16 Step                                                 */
+} LCD_BCCR_VLCD_Enum;
+
+/* ==========================================================  DR0  ========================================================== */
+/* ==========================================================  DR1  ========================================================== */
+/* ==========================================================  DR2  ========================================================== */
+/* ==========================================================  DR3  ========================================================== */
+/* ==========================================================  DR4  ========================================================== */
+/* ==========================================================  DR5  ========================================================== */
+/* ==========================================================  DR6  ========================================================== */
+/* ==========================================================  DR7  ========================================================== */
+/* ==========================================================  DR8  ========================================================== */
+/* ==========================================================  DR9  ========================================================== */
+/* =========================================================  DR10  ========================================================== */
+/* =========================================================  DR11  ========================================================== */
+/* =========================================================  DR12  ========================================================== */
+/* =========================================================  DR13  ========================================================== */
+/* =========================================================  DR14  ========================================================== */
+/* =========================================================  DR15  ========================================================== */
+/* =========================================================  DR16  ========================================================== */
+/* =========================================================  DR17  ========================================================== */
+/* =========================================================  DR18  ========================================================== */
+/* =========================================================  DR19  ========================================================== */
+/* =========================================================  DR20  ========================================================== */
+/* =========================================================  DR21  ========================================================== */
+/* =========================================================  DR22  ========================================================== */
+/* =========================================================  DR23  ========================================================== */
+/* =========================================================  DR24  ========================================================== */
+/* =========================================================  DR25  ========================================================== */
+/* =========================================================  DR26  ========================================================== */
+/* =========================================================  DR27  ========================================================== */
+/* =========================================================  DR28  ========================================================== */
+/* =========================================================  DR29  ========================================================== */
+/* =========================================================  DR30  ========================================================== */
+/* =========================================================  DR31  ========================================================== */
+/* =========================================================  DR32  ========================================================== */
+/* =========================================================  DR33  ========================================================== */
+/* =========================================================  DR34  ========================================================== */
+/* =========================================================  DR35  ========================================================== */
+/* =========================================================  DR36  ========================================================== */
+/* =========================================================  DR37  ========================================================== */
+/* =========================================================  DR38  ========================================================== */
+/* =========================================================  DR39  ========================================================== */
+/* =========================================================  DR40  ========================================================== */
+/* =========================================================  DR41  ========================================================== */
+/* =========================================================  DR42  ========================================================== */
+/* =========================================================  DR43  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                            CRC                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+/* ==================================================  CRC CR MODS [7..7]  =================================================== */
+typedef enum {                                  /*!< CRC_CR_MODS                                                               */
+  CRC_CR_MODS_UserMode                 = 0,     /*!< UserMode : User Mode (Calculate every data written to the CRC_IN
+                                                     register)                                                                 */
+  CRC_CR_MODS_AutoMode                 = 1,     /*!< AutoMode : Auto Mode (Calculate till CRC_SADR == CRC_EADR)                */
+} CRC_CR_MODS_Enum;
+
+/* =================================================  CRC CR RLTCLR [6..6]  ================================================== */
+typedef enum {                                  /*!< CRC_CR_RLTCLR                                                             */
+  CRC_CR_RLTCLR_NoEffect               = 0,     /*!< NoEffect : No effect.                                                     */
+  CRC_CR_RLTCLR_Init                   = 1,     /*!< Init : Initialize the CRC_RLT register with the value of CRC_INIT.
+                                                     (This bit is automatically cleared to '0' after operation.)               */
+} CRC_CR_RLTCLR_Enum;
+
+/* ==================================================  CRC CR MDSEL [5..5]  ================================================== */
+typedef enum {                                  /*!< CRC_CR_MDSEL                                                              */
+  CRC_CR_MDSEL_CRC                     = 0,     /*!< CRC : Select CRC.                                                         */
+  CRC_CR_MDSEL_Checksum                = 1,     /*!< Checksum : Select Checksum.                                               */
+} CRC_CR_MDSEL_Enum;
+
+/* ==================================================  CRC CR POLYS [4..4]  ================================================== */
+typedef enum {                                  /*!< CRC_CR_POLYS                                                              */
+  CRC_CR_POLYS_CRC16_CCITT             = 0,     /*!< CRC16_CCITT : CRC16-CCITT (G1(x) = x16 + x12 + x5 + 1)                    */
+  CRC_CR_POLYS_CRC16                   = 1,     /*!< CRC16 : CRC16 (G2(x) = x16 + x15 + x2 + 1)                                */
+} CRC_CR_POLYS_Enum;
+
+/* =================================================  CRC CR SARINC [3..3]  ================================================== */
+typedef enum {                                  /*!< CRC_CR_SARINC                                                             */
+  CRC_CR_SARINC_Disable                = 0,     /*!< Disable : No effect.                                                      */
+  CRC_CR_SARINC_Enable                 = 1,     /*!< Enable : The CRC/Checksum start address register is incremented
+                                                     as the selected input size every writing to the CRC_IN
+                                                     register.                                                                 */
+} CRC_CR_SARINC_Enum;
+
+/* =================================================  CRC CR FIRSTBS [1..1]  ================================================= */
+typedef enum {                                  /*!< CRC_CR_FIRSTBS                                                            */
+  CRC_CR_FIRSTBS_msbFirst              = 0,     /*!< msbFirst : msb first                                                      */
+  CRC_CR_FIRSTBS_lsbFirst              = 1,     /*!< lsbFirst : lsb first                                                      */
+} CRC_CR_FIRSTBS_Enum;
+
+/* =================================================  CRC CR CRCRUN [0..0]  ================================================== */
+typedef enum {                                  /*!< CRC_CR_CRCRUN                                                             */
+  CRC_CR_CRCRUN_Stop                   = 0,     /*!< Stop : Not busy. The CRC operation can be finished by writing
+                                                     '0' to this bit while running.                                            */
+  CRC_CR_CRCRUN_Start                  = 1,     /*!< Start : Start CRC operation. This bit is automatically cleared
+                                                     to '0' when the value of CRC_SADR register reaches the
+                                                     value of CRC_EADR register.                                               */
+} CRC_CR_CRCRUN_Enum;
+
+/* ==========================================================  IN  =========================================================== */
+/* ==========================================================  RLT  ========================================================== */
+/* =========================================================  INIT  ========================================================== */
+/* =========================================================  SADR  ========================================================== */
+/* =========================================================  EADR  ========================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA0                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  TRIM00  ========================================================= */
+/* ========================================================  TRIM01  ========================================================= */
+/* ========================================================  TRIM02  ========================================================= */
+/* ========================================================  TRIM03  ========================================================= */
+/* ========================================================  TRIM04  ========================================================= */
+/* ========================================================  TRIM05  ========================================================= */
+/* ========================================================  TRIM06  ========================================================= */
+/* ========================================================  TRIM07  ========================================================= */
+/* ========================================================  TRIM08  ========================================================= */
+/* ========================================================  TRIM09  ========================================================= */
+/* ========================================================  TRIM10  ========================================================= */
+/* ========================================================  TRIM11  ========================================================= */
+/* ========================================================  TRIM12  ========================================================= */
+/* ========================================================  TRIM13  ========================================================= */
+/* ========================================================  TRIM14  ========================================================= */
+/* ========================================================  TRIM15  ========================================================= */
+/* ========================================================  TRIM16  ========================================================= */
+/* ========================================================  TRIM17  ========================================================= */
+/* ========================================================  TRIM18  ========================================================= */
+/* ========================================================  TRIM19  ========================================================= */
+/* =====================================================  CONF_MF1CNFIG  ===================================================== */
+/* =====================================================  CONF_MF2CNFIG  ===================================================== */
+/* =====================================================  CONF_MF3CNFIG  ===================================================== */
+/* =====================================================  CONF_MF4CNFIG  ===================================================== */
+/* ========================================================  TRIM24  ========================================================= */
+/* ========================================================  TRIM25  ========================================================= */
+/* ========================================================  TRIM26  ========================================================= */
+/* ========================================================  TRIM27  ========================================================= */
+/* ========================================================  TRIM28  ========================================================= */
+/* ========================================================  TRIM29  ========================================================= */
+/* ========================================================  TRIM30  ========================================================= */
+/* ========================================================  TRIM31  ========================================================= */
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA1                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  RPCNFIG  ======================================================== */
+/* ==============================================  COA1 RPCNFIG WTIDKY [4..31]  ============================================== */
+typedef enum {                                  /*!< COA1_RPCNFIG_WTIDKY                                                       */
+  COA1_RPCNFIG_WTIDKY_Value            = 110922279,/*!< Value : Key Value (0x69c8a27)                                          */
+} COA1_RPCNFIG_WTIDKY_Enum;
+
+/* ===============================================  COA1 RPCNFIG READP [0..1]  =============================================== */
+typedef enum {                                  /*!< COA1_RPCNFIG_READP                                                        */
+  COA1_RPCNFIG_READP_Level0            = 3,     /*!< Level0 : No restriction for read/erase/write.                             */
+  COA1_RPCNFIG_READP_Level1            = 2,     /*!< Level1 : 1. Not readable/erasable/writable by 'Debug' 2. Bulk
+                                                     erasable only by 'Debug' 3. Readable/erasable/writable
+                                                     by 'Instruction from Flash Memory and RAM'                                */
+  COA1_RPCNFIG_READP_Level2            = 0,     /*!< Level2 : 1. Not readable/erasable/writable by 'Debug' / 'Instruction
+                                                     from RAM' 2. Bulk erasable only by 'Instruction from RAM'
+                                                     / 'Debug' 3. Readable/erasable/writable by 'Instruction
+                                                     from Flash Memory'                                                        */
+} COA1_RPCNFIG_READP_Enum;
+
+/* =======================================================  WDTCNFIG  ======================================================== */
+/* ==============================================  COA1 WDTCNFIG WRCMF [4..15]  ============================================== */
+typedef enum {                                  /*!< COA1_WDTCNFIG_WRCMF                                                       */
+  COA1_WDTCNFIG_WRCMF_BySW             = 2413,  /*!< BySW : By S/W (CLKSRCR Register) (0x96d)                                  */
+  COA1_WDTCNFIG_WRCMF_AlwaysEnableExceptDeepSleep = 679,/*!< AlwaysEnableExceptDeepSleep : Always Enable Except for Deep
+                                                     Sleep (0x2a7)                                                             */
+  COA1_WDTCNFIG_WRCMF_AlwaysEnable     = 4095,  /*!< AlwaysEnable : Always Enable                                              */
+} COA1_WDTCNFIG_WRCMF_Enum;
+
+/* ==============================================  COA1 WDTCNFIG WCLKMF [2..2]  ============================================== */
+typedef enum {                                  /*!< COA1_WDTCNFIG_WCLKMF                                                      */
+  COA1_WDTCNFIG_WCLKMF_BySW            = 0,     /*!< BySW : By S/W (PPCLKSR Register)                                          */
+  COA1_WDTCNFIG_WCLKMF_AlwaysWDTRC     = 1,     /*!< AlwaysWDTRC : Always WDTRC                                                */
+} COA1_WDTCNFIG_WCLKMF_Enum;
+
+/* ==============================================  COA1 WDTCNFIG WRSTMF [1..1]  ============================================== */
+typedef enum {                                  /*!< COA1_WDTCNFIG_WRSTMF                                                      */
+  COA1_WDTCNFIG_WRSTMF_AlwaysEnable    = 0,     /*!< AlwaysEnable : Always Enable                                              */
+  COA1_WDTCNFIG_WRSTMF_BySW            = 1,     /*!< BySW : By S/W (WDTCR Register)                                            */
+} COA1_WDTCNFIG_WRSTMF_Enum;
+
+/* ==============================================  COA1 WDTCNFIG WCNTMF [0..0]  ============================================== */
+typedef enum {                                  /*!< COA1_WDTCNFIG_WCNTMF                                                      */
+  COA1_WDTCNFIG_WCNTMF_AlwaysEnable    = 0,     /*!< AlwaysEnable : Always Enable                                              */
+  COA1_WDTCNFIG_WCNTMF_BySW            = 1,     /*!< BySW : By S/W (WDTCR Register)                                            */
+} COA1_WDTCNFIG_WCNTMF_Enum;
+
+/* =======================================================  LVRCNFIG  ======================================================== */
+/* =============================================  COA1 LVRCNFIG LVRENM [8..15]  ============================================== */
+typedef enum {                                  /*!< COA1_LVRCNFIG_LVRENM                                                      */
+  COA1_LVRCNFIG_LVRENM_BySW            = 170,   /*!< BySW : By S/W (LVRCR Register) (0xaa)                                     */
+  COA1_LVRCNFIG_LVRENM_AlwaysEnable    = 255,   /*!< AlwaysEnable : Always Enable (0xff)                                       */
+} COA1_LVRCNFIG_LVRENM_Enum;
+
+/* ==============================================  COA1 LVRCNFIG LVRVS [0..3]  =============================================== */
+typedef enum {                                  /*!< COA1_LVRCNFIG_LVRVS                                                       */
+  COA1_LVRCNFIG_LVRVS_1p62V            = 15,    /*!< 1p62V : 1.62V                                                             */
+  COA1_LVRCNFIG_LVRVS_DNW14            = 14,    /*!< DNW14 : Do not write.                                                     */
+  COA1_LVRCNFIG_LVRVS_DNW13            = 13,    /*!< DNW13 : Do not write.                                                     */
+  COA1_LVRCNFIG_LVRVS_DNW12            = 12,    /*!< DNW12 : Do not write.                                                     */
+  COA1_LVRCNFIG_LVRVS_2p00V            = 11,    /*!< 2p00V : 2.00V                                                             */
+  COA1_LVRCNFIG_LVRVS_2p13V            = 10,    /*!< 2p13V : 2.13V                                                             */
+  COA1_LVRCNFIG_LVRVS_2p28V            = 9,     /*!< 2p28V : 2.28V                                                             */
+  COA1_LVRCNFIG_LVRVS_2p46V            = 8,     /*!< 2p46V : 2.46V                                                             */
+  COA1_LVRCNFIG_LVRVS_2p67V            = 7,     /*!< 2p67V : 2.67V                                                             */
+  COA1_LVRCNFIG_LVRVS_3p04V            = 6,     /*!< 3p04V : 3.04V                                                             */
+  COA1_LVRCNFIG_LVRVS_3p20V            = 5,     /*!< 3p20V : 3.20V                                                             */
+  COA1_LVRCNFIG_LVRVS_3p55V            = 4,     /*!< 3p55V : 3.55V                                                             */
+  COA1_LVRCNFIG_LVRVS_3p75V            = 3,     /*!< 3p75V : 3.75V                                                             */
+  COA1_LVRCNFIG_LVRVS_3p99V            = 2,     /*!< 3p99V : 3.99V                                                             */
+  COA1_LVRCNFIG_LVRVS_4p25V            = 1,     /*!< 4p25V : 4.25V                                                             */
+  COA1_LVRCNFIG_LVRVS_4p55             = 0,     /*!< 4p55 : 4.55V                                                              */
+} COA1_LVRCNFIG_LVRVS_Enum;
+
+/* =======================================================  CNFIGWTP1  ======================================================= */
+/* ==============================================  COA1 CNFIGWTP1 CP3WP [2..2]  ============================================== */
+typedef enum {                                  /*!< COA1_CNFIGWTP1_CP3WP                                                      */
+  COA1_CNFIGWTP1_CP3WP_Enable          = 0,     /*!< Enable : Enable protection. (Not erasable/writable by instruction)        */
+  COA1_CNFIGWTP1_CP3WP_Disable         = 1,     /*!< Disable : Disable protection. (Erasable/writable by instruction)          */
+} COA1_CNFIGWTP1_CP3WP_Enum;
+
+/* ==============================================  COA1 CNFIGWTP1 CP2WP [1..1]  ============================================== */
+typedef enum {                                  /*!< COA1_CNFIGWTP1_CP2WP                                                      */
+  COA1_CNFIGWTP1_CP2WP_Enable          = 0,     /*!< Enable : Enable protection. (Not erasable/writable by instruction)        */
+  COA1_CNFIGWTP1_CP2WP_Disable         = 1,     /*!< Disable : Disable protection. (Erasable/writable by instruction)          */
+} COA1_CNFIGWTP1_CP2WP_Enum;
+
+/* ==============================================  COA1 CNFIGWTP1 CP1WP [0..0]  ============================================== */
+typedef enum {                                  /*!< COA1_CNFIGWTP1_CP1WP                                                      */
+  COA1_CNFIGWTP1_CP1WP_Enable          = 0,     /*!< Enable : Enable protection. (Not erasable/writable by instruction)        */
+  COA1_CNFIGWTP1_CP1WP_Disable         = 1,     /*!< Disable : Disable protection. (Erasable/writable by instruction)          */
+} COA1_CNFIGWTP1_CP1WP_Enum;
+
+/* ========================================================  FMWTP1  ========================================================= */
+/* ==============================================  COA1 FMWTP1 SWTP31 [31..31]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP31                                                        */
+  COA1_FMWTP1_SWTP31_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP31_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP31_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP30 [30..30]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP30                                                        */
+  COA1_FMWTP1_SWTP30_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP30_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP30_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP29 [29..29]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP29                                                        */
+  COA1_FMWTP1_SWTP29_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP29_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP29_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP28 [28..28]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP28                                                        */
+  COA1_FMWTP1_SWTP28_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP28_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP28_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP27 [27..27]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP27                                                        */
+  COA1_FMWTP1_SWTP27_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP27_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP27_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP26 [26..26]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP26                                                        */
+  COA1_FMWTP1_SWTP26_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP26_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP26_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP25 [25..25]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP25                                                        */
+  COA1_FMWTP1_SWTP25_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP25_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP25_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP24 [24..24]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP24                                                        */
+  COA1_FMWTP1_SWTP24_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP24_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP24_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP23 [23..23]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP23                                                        */
+  COA1_FMWTP1_SWTP23_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP23_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP23_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP22 [22..22]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP22                                                        */
+  COA1_FMWTP1_SWTP22_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP22_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP22_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP21 [21..21]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP21                                                        */
+  COA1_FMWTP1_SWTP21_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP21_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP21_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP20 [20..20]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP20                                                        */
+  COA1_FMWTP1_SWTP20_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP20_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP20_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP19 [19..19]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP19                                                        */
+  COA1_FMWTP1_SWTP19_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP19_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP19_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP18 [18..18]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP18                                                        */
+  COA1_FMWTP1_SWTP18_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP18_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP18_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP17 [17..17]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP17                                                        */
+  COA1_FMWTP1_SWTP17_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP17_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP17_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP16 [16..16]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP16                                                        */
+  COA1_FMWTP1_SWTP16_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP16_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP16_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP15 [15..15]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP15                                                        */
+  COA1_FMWTP1_SWTP15_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP15_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP15_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP14 [14..14]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP14                                                        */
+  COA1_FMWTP1_SWTP14_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP14_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP14_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP13 [13..13]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP13                                                        */
+  COA1_FMWTP1_SWTP13_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP13_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP13_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP12 [12..12]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP12                                                        */
+  COA1_FMWTP1_SWTP12_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP12_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP12_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP11 [11..11]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP11                                                        */
+  COA1_FMWTP1_SWTP11_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP11_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP11_Enum;
+
+/* ==============================================  COA1 FMWTP1 SWTP10 [10..10]  ============================================== */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP10                                                        */
+  COA1_FMWTP1_SWTP10_Enable            = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP10_Disable           = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP10_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP9 [9..9]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP9                                                         */
+  COA1_FMWTP1_SWTP9_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP9_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP9_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP8 [8..8]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP8                                                         */
+  COA1_FMWTP1_SWTP8_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP8_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP8_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP7 [7..7]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP7                                                         */
+  COA1_FMWTP1_SWTP7_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP7_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP7_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP6 [6..6]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP6                                                         */
+  COA1_FMWTP1_SWTP6_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP6_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP6_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP5 [5..5]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP5                                                         */
+  COA1_FMWTP1_SWTP5_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP5_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP5_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP4 [4..4]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP4                                                         */
+  COA1_FMWTP1_SWTP4_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP4_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP4_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP3 [3..3]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP3                                                         */
+  COA1_FMWTP1_SWTP3_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP3_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP3_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP2 [2..2]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP2                                                         */
+  COA1_FMWTP1_SWTP2_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP2_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP2_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP1 [1..1]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP1                                                         */
+  COA1_FMWTP1_SWTP1_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP1_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP1_Enum;
+
+/* ===============================================  COA1 FMWTP1 SWTP0 [0..0]  ================================================ */
+typedef enum {                                  /*!< COA1_FMWTP1_SWTP0                                                         */
+  COA1_FMWTP1_SWTP0_Enable             = 0,     /*!< Enable : Protect 'flash memory sector n erase/write'                      */
+  COA1_FMWTP1_SWTP0_Disable            = 1,     /*!< Disable : Permit 'flash memory sector n erase/write'                      */
+} COA1_FMWTP1_SWTP0_Enum;
+
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA2                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  UDATA00  ======================================================== */
+/* ========================================================  UDATA01  ======================================================== */
+/* ========================================================  UDATA02  ======================================================== */
+/* ========================================================  UDATA03  ======================================================== */
+/* ========================================================  UDATA04  ======================================================== */
+/* ========================================================  UDATA05  ======================================================== */
+/* ========================================================  UDATA06  ======================================================== */
+/* ========================================================  UDATA07  ======================================================== */
+/* ========================================================  UDATA08  ======================================================== */
+/* ========================================================  UDATA09  ======================================================== */
+/* ========================================================  UDATA10  ======================================================== */
+/* ========================================================  UDATA11  ======================================================== */
+/* ========================================================  UDATA12  ======================================================== */
+/* ========================================================  UDATA13  ======================================================== */
+/* ========================================================  UDATA14  ======================================================== */
+/* ========================================================  UDATA15  ======================================================== */
+/* ========================================================  UDATA16  ======================================================== */
+/* ========================================================  UDATA17  ======================================================== */
+/* ========================================================  UDATA18  ======================================================== */
+/* ========================================================  UDATA19  ======================================================== */
+/* ========================================================  UDATA20  ======================================================== */
+/* ========================================================  UDATA21  ======================================================== */
+/* ========================================================  UDATA22  ======================================================== */
+/* ========================================================  UDATA23  ======================================================== */
+/* ========================================================  UDATA24  ======================================================== */
+/* ========================================================  UDATA25  ======================================================== */
+/* ========================================================  UDATA26  ======================================================== */
+/* ========================================================  UDATA27  ======================================================== */
+/* ========================================================  UDATA28  ======================================================== */
+/* ========================================================  UDATA29  ======================================================== */
+/* ========================================================  UDATA30  ======================================================== */
+/* ========================================================  UDATA31  ======================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================                                           COA3                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  UDATA00  ======================================================== */
+/* ========================================================  UDATA01  ======================================================== */
+/* ========================================================  UDATA02  ======================================================== */
+/* ========================================================  UDATA03  ======================================================== */
+/* ========================================================  UDATA04  ======================================================== */
+/* ========================================================  UDATA05  ======================================================== */
+/* ========================================================  UDATA06  ======================================================== */
+/* ========================================================  UDATA07  ======================================================== */
+/* ========================================================  UDATA08  ======================================================== */
+/* ========================================================  UDATA09  ======================================================== */
+/* ========================================================  UDATA10  ======================================================== */
+/* ========================================================  UDATA11  ======================================================== */
+/* ========================================================  UDATA12  ======================================================== */
+/* ========================================================  UDATA13  ======================================================== */
+/* ========================================================  UDATA14  ======================================================== */
+/* ========================================================  UDATA15  ======================================================== */
+/* ========================================================  UDATA16  ======================================================== */
+/* ========================================================  UDATA17  ======================================================== */
+/* ========================================================  UDATA18  ======================================================== */
+/* ========================================================  UDATA19  ======================================================== */
+/* ========================================================  UDATA20  ======================================================== */
+/* ========================================================  UDATA21  ======================================================== */
+/* ========================================================  UDATA22  ======================================================== */
+/* ========================================================  UDATA23  ======================================================== */
+/* ========================================================  UDATA24  ======================================================== */
+/* ========================================================  UDATA25  ======================================================== */
+/* ========================================================  UDATA26  ======================================================== */
+/* ========================================================  UDATA27  ======================================================== */
+/* ========================================================  UDATA28  ======================================================== */
+/* ========================================================  UDATA29  ======================================================== */
+/* ========================================================  UDATA30  ======================================================== */
+/* ========================================================  UDATA31  ======================================================== */
+
+/** @} */ /* End of group EnumValue_peripherals */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* A31G12X_H */
+
+
+/** @} */ /* End of group A31G12x */
+
+/** @} */ /* End of group VENDOR ABOV Semiconductor Co., Ltd. */
diff --git a/Project/SDK_V2_5_0/Device/Startup/startup_A31G12x.s b/Project/SDK_V2_5_0/Device/Startup/startup_A31G12x.s
new file mode 100644
index 0000000..352f770
--- /dev/null
+++ b/Project/SDK_V2_5_0/Device/Startup/startup_A31G12x.s
@@ -0,0 +1,253 @@
+;/**************************************************************************//**
+; * @file     startup_A31G12x.s
+; * @brief    CMSIS Core Device Startup File for
+; *           A31G12x Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000500
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000080
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     LVI_Handler               ; IRQ 0
+                DCD     WUT_Handler               ; IRQ 1
+                DCD     WDT_Handler               ; IRQ 2
+                DCD     EINT0_Handler             ; IRQ 3
+                DCD     EINT1_Handler             ; IRQ 4
+                DCD     EINT2_Handler             ; IRQ 5
+                DCD     EINT3_Handler             ; IRQ 6
+                DCD     TIMER10_Handler           ; IRQ 7
+                DCD     TIMER11_Handler           ; IRQ 8
+                DCD     TIMER12_Handler           ; IRQ 9
+                DCD     I2C0_Handler              ; IRQ 10
+                DCD     USART10_Handler           ; IRQ 11
+                DCD     WT_Handler                ; IRQ 12
+                DCD     TIMER30_Handler           ; IRQ 13
+                DCD     I2C1_Handler              ; IRQ 14
+                DCD     TIMER20_Handler           ; IRQ 15
+                DCD     TIMER21_Handler           ; IRQ 16
+                DCD     USART11_Handler           ; IRQ 17
+                DCD     ADC_Handler               ; IRQ 18
+                DCD     UART0_Handler             ; IRQ 19
+                DCD     UART1_Handler             ; IRQ 20
+                DCD     TIMER13_Handler           ; IRQ 21
+                DCD     TIMER14_Handler           ; IRQ 22
+                DCD     TIMER15_Handler           ; IRQ 23
+                DCD     TIMER16_Handler           ; IRQ 24
+                DCD     I2C2_Handler              ; IRQ 25
+                DCD     USART12_Handler           ; IRQ 26
+                DCD     USART13_Handler           ; IRQ 27
+               ;DCD     RESERVED_Handler          ; IRQ 28
+               ;DCD     RESERVED_Handler          ; IRQ 29
+               ;DCD     RESERVED_Handler          ; IRQ 30
+               ;DCD     RESERVED_Handler          ; IRQ 31
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+DEVICE_Handler  PROC
+
+                EXPORT  LVI_Handler               [WEAK]
+                EXPORT  WUT_Handler               [WEAK]
+                EXPORT  WDT_Handler               [WEAK]
+                EXPORT  EINT0_Handler             [WEAK]
+                EXPORT  EINT1_Handler             [WEAK]
+                EXPORT  EINT2_Handler             [WEAK]
+                EXPORT  EINT3_Handler             [WEAK]
+                EXPORT  TIMER10_Handler           [WEAK]
+                EXPORT  TIMER11_Handler           [WEAK]
+                EXPORT  TIMER12_Handler           [WEAK]
+                EXPORT  I2C0_Handler              [WEAK]
+                EXPORT  USART10_Handler           [WEAK]
+                EXPORT  WT_Handler                [WEAK]
+                EXPORT  TIMER30_Handler           [WEAK]
+                EXPORT  I2C1_Handler              [WEAK]
+                EXPORT  TIMER20_Handler           [WEAK]
+                EXPORT  TIMER21_Handler           [WEAK]
+                EXPORT  USART11_Handler           [WEAK]
+                EXPORT  ADC_Handler               [WEAK]
+                EXPORT  UART0_Handler             [WEAK]
+                EXPORT  UART1_Handler             [WEAK]
+                EXPORT  TIMER13_Handler           [WEAK]
+                EXPORT  TIMER14_Handler           [WEAK]
+                EXPORT  TIMER15_Handler           [WEAK]
+                EXPORT  TIMER16_Handler           [WEAK]
+                EXPORT  I2C2_Handler              [WEAK]
+                EXPORT  USART12_Handler           [WEAK]
+                EXPORT  USART13_Handler           [WEAK]
+
+LVI_Handler
+WUT_Handler
+WDT_Handler
+EINT0_Handler
+EINT1_Handler
+EINT2_Handler
+EINT3_Handler
+TIMER10_Handler
+TIMER11_Handler
+TIMER12_Handler
+I2C0_Handler
+USART10_Handler
+WT_Handler
+TIMER30_Handler
+I2C1_Handler
+TIMER20_Handler
+TIMER21_Handler
+USART11_Handler
+ADC_Handler
+UART0_Handler
+UART1_Handler
+TIMER13_Handler
+TIMER14_Handler
+TIMER15_Handler
+TIMER16_Handler
+I2C2_Handler
+USART12_Handler
+USART13_Handler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
+
diff --git a/Project/SDK_V2_5_0/Device/Startup/system_A31G12x.c b/Project/SDK_V2_5_0/Device/Startup/system_A31G12x.c
new file mode 100644
index 0000000..578bae5
--- /dev/null
+++ b/Project/SDK_V2_5_0/Device/Startup/system_A31G12x.c
@@ -0,0 +1,82 @@
+/***************************************************************************//**
+ * @file     system_A31G12x.c
+ * @brief    CMSIS Device System Source File for
+ *           A31G12x Device Series
+ * @version  V5.00
+ * @date     10. January 2018
+ *//***************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "A31G12x.h"
+
+//==============================================================================
+// System Core Clock Variable
+//==============================================================================
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit() */
+uint32_t    mclk;                /**<  Main Clock Frequency (MCLK) */
+uint32_t    SystemCoreClock;     /**<  System Core Clock Frequency (Core Clock & HCLK) */
+uint32_t    SystemPeriClock;     /**<  System Peripheral Clock Frequency (PCLK) */
+uint32_t    ClkSrcTbl[] = { __HIRC, __XMOSC, __XSOSC, __WDTRC };
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Update SystemCoreClock variable.
+ * @return        None
+ * @details       Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ * @note          This function should be executed whenever the clock is changed.
+ *//*-------------------------------------------------------------------------*/
+void SystemCoreClockUpdate( void )      /* Get Core Clock Frequency */
+{
+   mclk = ClkSrcTbl[SCUCG->SCCR_b.MCLKSEL];
+   if( SCUCG->SCCR_b.MCLKSEL == 0 ) mclk >>= SCUCG->CLKSRCR_b.HIRCSEL;  // MCLK
+
+   if( SCUCG->SCDIVR1_b.HDIV > 4 ) SCUCG->SCDIVR1_b.HDIV = 4;
+   SystemCoreClock = mclk >> (4 - SCUCG->SCDIVR1_b.HDIV);               // HCLK
+   SystemPeriClock = SystemCoreClock >> SCUCG->SCDIVR2_b.PDIV;          // PCLK
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Setup the microcontroller system.
+ * @return        None
+ * @details       Initialize the System and update the SystemCoreClock variable.
+ *//*-------------------------------------------------------------------------*/
+void SystemInit( void )
+{
+   /* ToDo: add code to initialize the system
+            do not use global variables because this function is called before
+            reaching pre-main. RW section maybe overwritten afterwards. */
+
+   while( SCUCC->SRSTVR_b.VALID != 0x55 ) {}
+
+   // disable interrupt
+   __disable_irq();
+
+   // disable WDT
+   WDT->CR  =  0
+               | ( 0x5A69uL             << WDT_CR_WTIDKY_Pos )
+               | ( WDT_CR_RSTEN_Disable << WDT_CR_RSTEN_Pos )     // added by lms
+               | ( WDT_CR_CNTEN_Disable << WDT_CR_CNTEN_Pos )
+               ;
+
+#ifndef __ON_DEBUG__
+   WDT->SR_b.DBGCNTEN = 0 << WDT_SR_DBGCNTEN_Pos;
+#endif
+}
+
diff --git a/Project/SDK_V2_5_0/Device/Startup/system_A31G12x.h b/Project/SDK_V2_5_0/Device/Startup/system_A31G12x.h
new file mode 100644
index 0000000..14775bc
--- /dev/null
+++ b/Project/SDK_V2_5_0/Device/Startup/system_A31G12x.h
@@ -0,0 +1,72 @@
+/***************************************************************************//**
+ * @file     system_A31G12x.h
+ * @brief    CMSIS Device System Header File for
+ *           A31G12x Device Series
+ * @version  V5.00
+ * @date     10. January 2018
+ *//***************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_A31G12x_H
+#define SYSTEM_A31G12x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//==============================================================================
+// Define Debug mode or not
+//==============================================================================
+#define __ON_DEBUG__                 // This line should be defined on debug mode only.
+ 
+//==============================================================================
+// Define clocks
+//==============================================================================
+/* ToDo: add here your necessary defines for device initialization
+         following is an example for different system frequencies */
+
+#define __HIRC    (40000000uL)      /**<  Internal RC Oscillator Frequency */
+#define __XMOSC   (16000000uL)      /**<  External Main Crystal Oscillator Frequency */
+#define __XSOSC   (32768uL)         /**<  External Sub Crystal Oscillator Frequency */
+#define __WDTRC   (40000uL)         /**<  Watch-Dog Timer RC Oscillator Frequency */
+
+extern uint32_t mclk;               /**<  Main Clock Frequency (MCLK) */
+extern uint32_t SystemCoreClock;    /**<  System Core Clock Frequency (Core Clock & HCLK) */
+extern uint32_t SystemPeriClock;    /**<  System Peripheral Clock Frequency (PCLK) */
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Setup the microcontroller system.
+ * @return        None
+ * @details       Initialize the System and update the SystemCoreClock variable.
+ *//*-------------------------------------------------------------------------*/
+extern void SystemInit( void );
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Update SystemCoreClock variable.
+ * @return        None
+ * @details       Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ *//*-------------------------------------------------------------------------*/
+extern void SystemCoreClockUpdate( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_A31G12x_H */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_aa_types.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_aa_types.h
new file mode 100644
index 0000000..df93d53
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_aa_types.h
@@ -0,0 +1,264 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_aa_types.h
+* @brief    Contains the ABOV typedefs for C standard types.
+*           It is intended to be used in ISO C conforming development
+*           environments and checks for this insofar as it is possible
+*           to do so.
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef AA_TYPES_H
+#define AA_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL            ((void*) 0)
+#endif
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+/**   HAL Status Type Definition */
+typedef enum
+{
+   HAL_OK       = 0x00U,
+   HAL_ERROR    = 0x01U,
+   HAL_BUSY     = 0x02U,
+   HAL_TIMEOUT  = 0x03U
+} HAL_Status_Type;
+
+/**   Boolean Type Definition */
+typedef enum
+{
+   FALSE = 0,
+   TRUE = !FALSE
+} Bool;
+
+/**   Flag Status and Interrupt Flag Status Type Definition */
+typedef enum
+{
+   RESET = 0,
+   SET = !RESET
+} FlagStatus, IntStatus, SetState;
+
+/**   Functional State Definition */
+typedef enum
+{
+   DISABLE = 0,
+   ENABLE = !DISABLE
+} FunctionalState;
+
+/**   Status Type Definition */
+typedef enum
+{
+   ERROR = 0,
+   SUCCESS = !ERROR
+} Status;
+
+/**   Read/Write Transfer Mode Type */
+typedef enum
+{
+   NONE_BLOCKING = 0,   /**<  Non-Blocking Mode */
+   BLOCKING,            /**<  Blocking Mode */
+} TRANSFER_BLOCK_Type;
+
+//==============================================================================
+// Generic
+//==============================================================================
+
+typedef unsigned            char    b8;      // boolean type
+typedef                     char    c8;      // character type
+typedef unsigned            char    u8;      //  8-bit unsigned integer type
+typedef signed              char    s8;      //  8-bit   signed integer type
+typedef unsigned short      int     u16;     // 16-bit unsigned integer type
+typedef signed   short      int     s16;     // 16-bit   signed integer type
+// typedef unsigned            int     u32;     // 32-bit unsigned integer type
+// typedef signed              int     s32;     // 32-bit   signed integer type
+typedef unsigned long       int     u32;     // 32-bit unsigned integer type
+typedef signed   long       int     s32;     // 32-bit   signed integer type
+typedef unsigned long  long int     u64;     // 64-bit unsigned integer type
+typedef signed   long  long int     s64;     // 64-bit   signed integer type
+typedef                     float   f32;     // 32-bit floating point type
+typedef                     double  f64;     // 64-bit floating point type
+
+typedef volatile unsigned            char    vb8;      // boolean type
+typedef volatile                     char    vc8;      // character type
+typedef volatile unsigned            char    vu8;      //  8-bit unsigned integer type
+typedef volatile signed              char    vs8;      //  8-bit   signed integer type
+typedef volatile unsigned short      int     vu16;     // 16-bit unsigned integer type
+typedef volatile signed   short      int     vs16;     // 16-bit   signed integer type
+// typedef volatile unsigned            int     vu32;     // 32-bit unsigned integer type
+// typedef volatile signed              int     vs32;     // 32-bit   signed integer type
+typedef volatile unsigned long       int     vu32;     // 32-bit unsigned integer type
+typedef volatile signed   long       int     vs32;     // 32-bit   signed integer type
+typedef volatile unsigned long  long int     vu64;     // 64-bit unsigned integer type
+typedef volatile signed   long  long int     vs64;     // 64-bit   signed integer type
+typedef volatile                     float   vf32;     // 32-bit floating point type
+typedef volatile                     double  vf64;     // 64-bit floating point type
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+//==============================================================================
+// bit operation
+//==============================================================================
+
+#define bitm( p )             ((u32)1<<(p))
+#define bitp( r, p, v )       {                                   \
+                                 r &= ~bitm( p );                 \
+                                 r |= (((v) & bitm(0)) << (p));   \
+                              }
+#define bits( r, p )          r |= bitm( p )
+#define bitr( r, p )          r &= ~bitm( p )
+#define bitc( r, p )          r ^= bitm( p )
+#define bitg( r, p )          ((r&bitm( p )) >> (p))
+#define bitt( r, p, v )       ((r&bitm( p )) == ((v)<<(p)))
+
+#define bitsm( p, s )         ((((u64)1<<(s))-1) << (p))
+#define bitsp( r, p, s, v )   {                                      \
+                                 r &= ~bitsm( p, s );                \
+                                 r |= (((v) & bitsm(0,s)) << (p));   \
+                              }
+#define bitss( r, p, s )      r |= bitsm( p, s )
+#define bitsr( r, p, s )      r &= ~bitsm( p, s )
+#define bitsc( r, p, s )      r ^= bitsm( p, s )
+#define bitsg( r, p, s )      ((r&bitsm( p, s )) >> (p))
+#define bitst( r, p, s, v )   ((r&bitsm( p, s )) == ((v)<<(p)))
+
+//==============================================================================
+// bit operation
+//==============================================================================
+
+/*-------------------------------------------------------------------------*//**
+ * _BIT( n ) sets the bit at position "n"
+ * _BIT( n ) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ *//*-------------------------------------------------------------------------*/
+#undef _BIT
+// Set bit macro
+#define _BIT( n )          (1 << (n))
+
+/*-------------------------------------------------------------------------*//**
+ * _SBF( f, v ) sets the bit field starting at position "f" to value "v".
+ * _SBF( f, v ) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ *//*-------------------------------------------------------------------------*/
+#undef _SBF
+// Set bit field macro
+#define _SBF( f, v )       ((v) << (f))
+
+/*-------------------------------------------------------------------------*//**
+ * _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ *//*-------------------------------------------------------------------------*/
+#undef _BITMASK
+// Bitmask creation macro
+#define _BITMASK( field_width )        (_BIT(field_width) - 1)
+
+//==============================================================================
+// array
+//==============================================================================
+
+// Number of elements in an array
+#define NELEMENTS( array )             (sizeof (array) / sizeof (array[0]))
+
+//==============================================================================
+// max/min
+//==============================================================================
+
+// max
+#if !defined( MAX )
+#define MAX( a, b )     (((a) > (b)) ? (a) : (b))
+#endif
+
+// min
+#if !defined( MIN )
+#define MIN( a, b )     (((a) < (b)) ? (a) : (b))
+#endif
+
+//==============================================================================
+// instruction
+//==============================================================================
+
+#define SYS_RESET()              NVIC_SystemReset()
+
+#define NOP()                    __NOP()
+#define WFI()                    __WFI()
+#define WFE()                    __WFE()
+#define DI()                     __disable_irq()   // reset value is "interrupt enable".
+#define EI()                     __enable_irq()    // reset value is "interrupt enable".
+
+#define APB_NOP                  {unsigned long tmp = CIDR;}
+
+//==============================================================================
+// directive
+//==============================================================================
+
+// Static data/function define
+#define STATIC          static
+
+// External data/function define
+#define EXTERN          extern
+
+// inline function
+#ifdef __CC_ARM
+#define INLINE          __inline
+#else
+#define INLINE          inline
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* AA_TYPES_H */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_adc.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_adc.h
new file mode 100644
index 0000000..0e55dfc
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_adc.h
@@ -0,0 +1,185 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_adc.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for adc firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _ADC_H_
+#define _ADC_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+//----------   ADC Trigger Signal Definition   ----------
+#define ADC_ADST                    (0x0uL << 11)
+#define ADC_T10M                    (0x1uL << 11)
+#define ADC_T11M                    (0x2uL << 11)
+#define ADC_T12M                    (0x3uL << 11)
+#define ADC_T30                     (0x4uL << 11)
+
+//----------   ADC Reference Selection Definition   ----------
+#define ADC_VDD                     (0x0uL << 10)
+#define ADC_AVREF                   (0x1uL << 10)
+
+//----------   ADC Convesion Start Definition   ----------
+//#define ADC_ADST                  (0x1uL << 8)
+
+//----------   ADC Interrupt Enable/Disable Definition   ----------
+#define ADC_INTDIS                  (0x0uL << 5)
+#define ADC_INTEN                   (0x1uL << 5)
+
+//----------   ADC Channel Selection Definition   ----------
+#define ADC_AN0                     (0x00uL << 0)
+#define ADC_AN1                     (0x01uL << 0)
+#define ADC_AN2                     (0x02uL << 0)
+#define ADC_AN3                     (0x03uL << 0)
+#define ADC_AN4                     (0x04uL << 0)
+#define ADC_AN5                     (0x05uL << 0)
+#define ADC_AN6                     (0x06uL << 0)
+#define ADC_AN7                     (0x07uL << 0)
+#define ADC_AN8                     (0x08uL << 0)
+#define ADC_AN9                     (0x09uL << 0)
+#define ADC_AN10                    (0x0auL << 0)
+
+/*-------------------------------------------------------------------------*//**
+ * Macro defines for ADC Status register
+ *//*-------------------------------------------------------------------------*/
+#define ADC_STAT_END                ((1uL << 4))
+
+#define ADC_REF_VDD                 0  /**<  ADC ref source VDD */
+#define ADC_REF_AVREF               1  /**<  ADC ref source AVREF */
+
+#define ADC_TRIGGER_DISABLE         0  /**<  Event Trigger Disabled/Soft-Trigger Only */
+#define ADC_TRIGGER_TIMER10         1  /**<  Timer10 Event Trigger */
+#define ADC_TRIGGER_TIMER11         2  /**<  Timer11 Event Trigger */
+#define ADC_TRIGGER_TIMER12         3  /**<  Timer12 Event Trigger */
+#define ADC_TRIGGER_TIMER30         4  /**<  Timer30 Event Trigger */
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+typedef struct
+{
+   /* ADC_CR */
+   uint32_t    RefSel;           /**<  RestartEn = ENABLE or DISABLE */
+   uint32_t    TrgSel;
+
+   /* ADC_PREDR */
+   uint32_t    InClkDiv;
+} ADC_CFG_Type;
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         ADC Enable
+ * @details       This macro Enable ADC Block
+ *//*-------------------------------------------------------------------------*/
+#define ADCEN()                     (ADC->CR_b.ADCEN = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         ADC Disable
+ * @details       This macro Disable ADC Block
+ *//*-------------------------------------------------------------------------*/
+#define ADCDIS()                    (ADC->CR_b.ADCEN = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         ADC Start bit set
+ * @details       This macro starts ADC conversion
+ *//*-------------------------------------------------------------------------*/
+#define ADCADST_Set()               (ADC->CR_b.ADST = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         ADC Start bit get
+ * @details       This macro gets ADST bit
+ *//*-------------------------------------------------------------------------*/
+#define ADCADST_Get()               (ADC->CR_b.ADST)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of ADC Interrupt
+ * @details       This macro gets interrupt flag of ADC
+ *//*-------------------------------------------------------------------------*/
+#define ADCInt_GetFg()              (ADC->CR_b.ADCIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of ADC Interrupt
+ * @details       This macro gets interrupt flag of ADC
+ *//*-------------------------------------------------------------------------*/
+#define ADCInt_ClrFg()              (ADC->CR_b.ADCIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get data of ADC Conversion
+ * @details       This macro gets data of ADC Conversion
+ *//*-------------------------------------------------------------------------*/
+#define ADCData_Get()               (ADC->DR)
+
+/*-------------------------------------------------------------------------*//**
+ * Macro defines for ADC Data register
+ *//*-------------------------------------------------------------------------*/
+/**   When DONE is 1, this field contains result value of ADC conversion */
+#define ADC_DR_RESULT( n )          ((n) & ADC_DR_ADDATA_Msk)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_ADC_Init( ADC_Type* ADCx, ADC_CFG_Type* ADC_Config );
+HAL_Status_Type HAL_ADC_DeInit( ADC_Type* ADCx );
+
+HAL_Status_Type HAL_ADC_ConfigInterrupt( ADC_Type* ADCx, FunctionalState NewState );
+HAL_Status_Type HAL_ADC_ChannelSel( ADC_Type* ADCx, uint32_t Channel );
+HAL_Status_Type HAL_ADC_Start( ADC_Type* ADCx );
+HAL_Status_Type HAL_ADC_Stop( ADC_Type* ADCx );
+HAL_Status_Type HAL_ADC_ClearStatus( ADC_Type* ADCx );
+uint32_t HAL_ADC_GetStatus( ADC_Type* ADCx );
+
+uint16_t HAL_ADC_GetData( ADC_Type* ADCx );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _ADC_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_crc.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_crc.h
new file mode 100644
index 0000000..456d388
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_crc.h
@@ -0,0 +1,124 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_crc.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for crc firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _CRC_H_
+#define _CRC_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+// User/Auto Mode Selection Control
+/*
+#define CRC_USER_M               (0x0uL << 7)
+#define CRC_AUTO_M               (0x1uL << 7)
+*/
+#define MODS_UserMode            (CRC_CR_MODS_UserMode << CRC_CR_MODS_Pos)
+#define MODS_AutoMode            (CRC_CR_MODS_AutoMode << CRC_CR_MODS_Pos)
+
+//----------   CRC/Checksum RLT Clear Constant Definition   ----------
+#define CRC_RLTCLR               (0x1uL << 6)
+
+//----------   CRC/Checksum Selection Constant Definition   ----------
+#define CRC_CRC                  (0x0uL << 5)
+#define CRC_CHECKSUM             (0x1uL << 5)
+
+//----------   CRC Polynominal Constant Definition   ----------
+#define CRC_CCITT                (0x0uL << 4)
+#define CRC_16                   (0x1uL << 4)
+
+//----------   CRC/Checksum Start Address Auto Increment Constant Definition   ----------
+#define CRC_NOINC                (0x0uL << 3)
+#define CRC_AUTOINC              (0x1uL << 3)
+
+//----------   CRC/Checksum 1st Shifted-in Bit Constant Definition   ----------
+#define CRC_MSB                  (0x0uL << 1)
+#define CRC_LSB                  (0x1uL << 1)
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         CRC In Data
+ * @param[in]     u32InData
+ *                CRC/Checksum Input Data
+ * @details       This macro puts input data for calculation
+ *//*-------------------------------------------------------------------------*/
+#define CRC_InData( u32InData )  (CRC->IN = u32InData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         CRC/Checksum Run
+ * @details       This macro starts CRC/Checksum calculation
+ *//*-------------------------------------------------------------------------*/
+#define CRCRun()                 { CRC->CR_b.CRCRUN = 1; NOP(); NOP(); NOP(); NOP(); }
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         CRC/Checksum Stop
+ * @details       This macro stops forcingly CRC/Checksum calculation
+ *//*-------------------------------------------------------------------------*/
+#define CRCStop()                (CRC->CR_b.CRCRUN = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         CRC/Checksum Finish Check
+ * @details       This macro checks CRC/Checksum finish
+ *//*-------------------------------------------------------------------------*/
+#define ChkCRCFinish()           (CRC->CR_b.CRCRUN)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_CRC_Init( void );
+HAL_Status_Type HAL_CRC_DeInit( void );
+
+HAL_Status_Type HAL_CRC_SetAddress( uint32_t u32SAdr, uint32_t u32EAdr, uint32_t u32IniD );
+
+uint32_t HAL_CRC_ConfigAutoMode( uint32_t u32SEL, uint32_t u32POLY, uint32_t u32FirstBit );
+HAL_Status_Type HAL_CRC_ConfigUserMode( uint32_t u32SEL, uint32_t u32POLY, uint32_t u32AdrInc, uint32_t u32FirstBit );
+uint32_t HAL_CRC_UserInput( uint32_t u32Input );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _CRC_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_debug_frmwrk.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_debug_frmwrk.h
new file mode 100644
index 0000000..19a5285
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_debug_frmwrk.h
@@ -0,0 +1,117 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_debug_frmwrk.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for debug_frmwrk firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _DEBUG_FRMWRK_H_
+#define _DEBUG_FRMWRK_H_
+
+#include "A31G12x_hal_uartn.h"
+#include "A31G12x_hal_libcfg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef _DEBUG_MSG
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+#define USED_UART_DEBUG_PORT     1
+
+#if (USED_UART_DEBUG_PORT == 0)
+#define DEBUG_UART_PORT          UART0
+#elif (USED_UART_DEBUG_PORT == 1)
+#define DEBUG_UART_PORT          UART1
+#endif
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+#define _DBG( x )       _db_msg( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DBG_( x )      _db_msg_( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DBC( x )       _db_char( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DBD( x )       _db_dec( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DBD16( x )     _db_dec_16( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DBD32( x )     _db_dec_32( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DBH( x )       _db_hex( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DBH16( x )     _db_hex_16( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DBH32( x )     _db_hex_32( (UARTn_Type*)DEBUG_UART_PORT, x )
+#define _DG()           _db_get_char( (UARTn_Type*)DEBUG_UART_PORT )
+#define _DG_( x )       _db_get_ch( (UARTn_Type*)DEBUG_UART_PORT, x )
+
+//******************************************************************************
+// Variable
+//******************************************************************************
+
+extern void ( *_db_msg )( UARTn_Type* UARTx, const void* s );
+extern void ( *_db_msg_ )( UARTn_Type* UARTx, const void* s );
+extern void ( *_db_char )( UARTn_Type* UARTx, uint8_t ch );
+extern void ( *_db_dec )( UARTn_Type* UARTx, uint8_t decn );
+extern void ( *_db_dec_16 )( UARTn_Type* UARTx, uint16_t decn );
+extern void ( *_db_dec_32 )( UARTn_Type* UARTx, uint32_t decn );
+extern void ( *_db_hex )( UARTn_Type* UARTx, uint8_t hexn );
+extern void ( *_db_hex_16 )( UARTn_Type* UARTx, uint16_t hexn );
+extern void ( *_db_hex_32 )( UARTn_Type* UARTx, uint32_t hexn );
+extern uint8_t ( *_db_get_char )( UARTn_Type* UARTx );
+extern uint8_t ( *_db_get_ch )( UARTn_Type* UARTx, uint8_t* ch );
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+void UARTPutChar( UARTn_Type* UARTx, uint8_t ch );
+void UARTPuts( UARTn_Type* UARTx, const void* str );
+void UARTPuts_( UARTn_Type* UARTx, const void* str );
+void UARTPutDec( UARTn_Type* UARTx, uint8_t decnum );
+void UARTPutDec16( UARTn_Type* UARTx, uint16_t decnum );
+void UARTPutDec32( UARTn_Type* UARTx, uint32_t decnum );
+void UARTPutHex( UARTn_Type* UARTx, uint8_t hexnum );
+void UARTPutHex16( UARTn_Type* UARTx, uint16_t hexnum );
+void UARTPutHex32( UARTn_Type* UARTx, uint32_t hexnum );
+uint8_t UARTGetChar( UARTn_Type* UARTx );
+uint8_t UARTGetCh( UARTn_Type* UARTx, uint8_t* ch );
+void cprintf( const char* format, ... );
+void debug_frmwrk_init( void );
+uint8_t getstring( void );
+
+#endif   /* _DEBUG_MSG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _DEBUG_FRMWRK_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_fmc.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_fmc.h
new file mode 100644
index 0000000..be3058a
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_fmc.h
@@ -0,0 +1,104 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_fmc.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for fmc firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _FMC_H_
+#define _FMC_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+//----------   Flash Memory Control Constants Definition   ----------
+#define FLASH_ID1                0x08192A3B
+#define FLASH_ID2                0x4C5D6E7F
+#define FLASH_IDXOR              0x9C752FC2
+#define FLASH_ADDR_CD0           0x5FFFFFFF
+#define FLASH_ADDR_CD1           0x5F9A30D7
+#define FLASH_ADDR_CDXOR         0xA498DF92
+#define FLASH_ADDR_INIT          0x5FFFFF80
+#define FLASH_CLR_PAGEBUF        0x6C930001
+#define FLASH_CHIPER_WOPT        0xC1BE0555
+#define FLASH_BULK_CODE          0x6C93A408
+#define FLASH_MEM_PGM_CODE       0x6C93A400
+#define FLASH_OPT_PGM_CODE       0x6C933800
+
+#define FLASH_START_ADDR         (0x10000000)
+#define FLASH_END_ADDR           (0x1000FFFF)
+#define CFG_OPT_SADDR            (0x1FFFF200)
+#define CFG_OPT_EADDR            (0x1FFFF7FF)
+#define SECTOR_SIZE_BYTE         (0x80uL)
+
+//----------   Flash Erase/Write Code Constanst Definition   ----------
+#define FLASH_BULK_ERASE         0x9AB1E0F8
+#define FLASH_PAGE_ERASE         0x190CD5A2
+#define FLASH_PAGE_WRITE         0x54760F54
+
+//----------   Flash Procedure Good/Fail Constant Definition   ----------
+#define FLASH_PGM_GOOD           0x0uL
+#define FLASH_PGM_FAIL           0x9uL
+
+//******************************************************************************
+// Variable
+//******************************************************************************
+
+extern uint32_t      flash_id1_reg;
+extern uint32_t      flash_id2_reg;
+extern uint32_t      flash_addr_code0;
+extern uint32_t      flash_addr_code1;
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+void HAL_FMC_FlashEntry( void );
+void HAL_FMC_FlashExit( void );
+uint32_t HAL_FMC_FlashFunction( uint32_t u32FncSel, uint32_t u32Addr, uint32_t* u32Buf );
+
+uint32_t HAL_FMC_BulkErase( uint32_t u32UserId );
+uint32_t HAL_FMC_PageErase( uint32_t u32UserId, uint32_t u32Addr );
+uint32_t HAL_FMC_PageWrite( uint32_t u32UserId, uint32_t u32Addr, uint32_t* u32Buf );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _FMC_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_i2cn.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_i2cn.h
new file mode 100644
index 0000000..686cdff
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_i2cn.h
@@ -0,0 +1,130 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_i2cn.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for i2cn firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _I2Cn_H_
+#define _I2Cn_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+/**   I2C Slave Address registers bit mask */
+#define I2Cn_SLA_BITMASK      (0xff)
+
+// I2C state handle return values
+#define RECEIVE_MODE          1
+#define TRANS_MODE            2
+#define RECEIVE_DATA          3
+#define TRANS_DATA            4
+#define LOST_BUS              5
+#define STOP_DECT             6
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+/**   Transfer option type definitions */
+typedef enum
+{
+   I2Cn_TRANSFER_POLLING = 0,    /**<  Transfer in polling mode */
+   I2Cn_TRANSFER_INTERRUPT       /**<  Transfer in interrupt mode */
+} I2Cn_TRANSFER_OPT_Type;
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+/**   Master transfer setup data structure definitions */
+typedef struct
+{
+   uint32_t          sl_addr7bit;   /**<  Slave address in 7bit mode */
+   uint8_t*          tx_data;       /**<  Pointer to Transmit data - NULL if data transmit is not used */
+   uint32_t          tx_length;     /**<  Transmit data length - 0 if data transmit is not used */
+   uint32_t          tx_count;      /**<  Current Transmit data counter */
+   uint8_t*          rx_data;       /**<  Pointer to Receive data - NULL if data receive is not used */
+   uint32_t          rx_length;     /**<  Receive data length - 0 if data receive is not used */
+   uint32_t          rx_count;      /**<  Current Receive data counter */
+} I2Cn_M_SETUP_Type;
+
+/**   Slave transfer setup data structure definitions */
+typedef struct
+{
+   uint8_t*          tx_data;       /**<  Pointer to transmit data - NULL if data transmit is not used */
+   uint32_t          tx_length;     /**<  Transmit data length - 0 if data transmit is not used */
+   uint32_t          tx_count;      /**<  Current transmit data counter */
+   uint8_t*          rx_data;       /**<  Pointer to receive data - NULL if data received is not used */
+   uint32_t          rx_length;     /**<  Receive data length - 0 if data receive is not used */
+   uint32_t          rx_count;      /**<  Current receive data counter */
+} I2Cn_S_SETUP_Type;
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_I2C_Init( I2Cn_Type* I2Cx, uint32_t clockrate );
+HAL_Status_Type HAL_I2C_DeInit( I2Cn_Type* I2Cx );
+
+HAL_Status_Type HAL_I2C_ConfigInterrupt( I2Cn_Type* I2Cx, Bool NewState );
+HAL_Status_Type HAL_I2C_Slave_SetAddress1( I2Cn_Type* I2Cx, uint8_t SlaveAddr_7bit, uint8_t GeneralCallState );
+HAL_Status_Type HAL_I2C_Slave_SetAddress2( I2Cn_Type* I2Cx, uint8_t SlaveAddr_7bit, uint8_t GeneralCallState );
+uint32_t HAL_I2C_Master_GetState( I2Cn_Type* I2Cx );
+uint32_t HAL_I2C_Slave_GetState( I2Cn_Type* I2Cx );
+
+HAL_Status_Type HAL_I2C_Master_IRQHandler_IT( I2Cn_Type*  I2Cx );
+HAL_Status_Type HAL_I2C_Slave_IRQHandler_IT( I2Cn_Type*  I2Cx );
+
+Status HAL_I2C_MasterTransferData( I2Cn_Type* I2Cx, I2Cn_M_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt );
+Status HAL_I2C_SlaveTransferData( I2Cn_Type* I2Cx, I2Cn_S_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt );
+
+Status HAL_I2C_Master_Transmit( I2Cn_Type* I2Cx, I2Cn_M_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt );
+Status HAL_I2C_Master_Receive( I2Cn_Type* I2Cx, I2Cn_M_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt );
+Status HAL_I2C_Slave_Receive( I2Cn_Type* I2Cx, I2Cn_S_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _I2Cn_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_intc.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_intc.h
new file mode 100644
index 0000000..acc9db4
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_intc.h
@@ -0,0 +1,411 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_intc.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for intc firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+// External Interrupt Port Number
+// #define PORTA                 (0x0uL)  /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#define PORTB                    (0x1uL)  /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#define PORTC                    (0x2uL)  /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+// #define PORTD                 (0x3uL)  /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#define PORTE                    (0x4uL)  /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+// #define PORTF                 (0x5uL)  /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+
+// External Interrupt Number
+/*
+#define EINT0_SEL                (0x0uL)
+#define EINT1_SEL                (0x1uL)
+#define EINT2_SEL                (0x2uL)
+#define EINT3_SEL                (0x3uL)
+*/
+#define EINT0                    (0x0uL)
+#define EINT1                    (0x1uL)
+#define EINT2                    (0x2uL)
+#define EINT3                    (0x3uL)
+
+// External Interrupt Trigger Selection Control
+/*
+#define TRG_EDGE                 (0x0uL)
+#define TRG_LEVEL                (0x1uL)
+*/
+#define ITRIGx_Edge              INTC_PBTRIG_ITRIG11_Edge
+#define ITRIGx_Level             INTC_PBTRIG_ITRIG11_Level
+
+// External Interrupt Enable Control
+/*
+#define EInt_DISABLE             (0x0uL)
+#define EInt_LOW_LEVEL_INT       (0x1uL)
+#define EInt_HIGH_LEVEL_INT      (0x2uL)
+#define EInt_FALLING_EDGE_INT    (0x1uL)
+#define EInt_RISING_EDGE_INT     (0x2uL)
+#define EInt_BOTH_EDGE_INT       (0x3uL)
+*/
+#define INTCTLx_Disable          INTC_PBCR_INTCTL11_Disable
+#define INTCTLx_LowLevel         INTC_PBCR_INTCTL11_FallingEdgeLowLevel
+#define INTCTLx_HighLevel        INTC_PBCR_INTCTL11_RisingEdgeHighLevel
+#define INTCTLx_FallingEdge      INTC_PBCR_INTCTL11_FallingEdgeLowLevel
+#define INTCTLx_RisingEdge       INTC_PBCR_INTCTL11_RisingEdgeHighLevel
+#define INTCTLx_BothEdge         INTC_PBCR_INTCTL11_BothEdgeNoLevel
+
+// External Interrupt Flag Clear Control
+/*
+#define EFLAG0                   (0x1uL << 0)
+#define EFLAG1                   (0x1uL << 1)
+#define EFLAG2                   (0x1uL << 2)
+#define EFLAG3                   (0x1uL << 3)
+#define EFLAG4                   (0x1uL << 4)
+#define EFLAG5                   (0x1uL << 5)
+#define EFLAG6                   (0x1uL << 6)
+#define EFLAG7                   (0x1uL << 7)
+#define EFLAG8                   (0x1uL << 8)
+#define EFLAG9                   (0x1uL << 9)
+#define EFLAG10                  (0x1uL << 10)
+#define EFLAG11                  (0x1uL << 11)
+*/
+// #define PnFLAG_FLAG15         (0x1uL << INTC_PBFLAG_FLAG15_Pos)
+// #define PnFLAG_FLAG14         (0x1uL << INTC_PBFLAG_FLAG14_Pos)
+// #define PnFLAG_FLAG13         (0x1uL << INTC_PBFLAG_FLAG13_Pos)
+// #define PnFLAG_FLAG12         (0x1uL << INTC_PBFLAG_FLAG12_Pos)
+#define PnFLAG_FLAG11            (0x1uL << INTC_PBFLAG_FLAG11_Pos)
+#define PnFLAG_FLAG10            (0x1uL << INTC_PBFLAG_FLAG10_Pos)
+#define PnFLAG_FLAG9             (0x1uL << INTC_PBFLAG_FLAG9_Pos)
+#define PnFLAG_FLAG8             (0x1uL << INTC_PBFLAG_FLAG8_Pos)
+#define PnFLAG_FLAG7             (0x1uL << INTC_PBFLAG_FLAG7_Pos)
+#define PnFLAG_FLAG6             (0x1uL << INTC_PBFLAG_FLAG6_Pos)
+#define PnFLAG_FLAG5             (0x1uL << INTC_PBFLAG_FLAG5_Pos)
+#define PnFLAG_FLAG4             (0x1uL << INTC_PBFLAG_FLAG4_Pos)
+#define PnFLAG_FLAG3             (0x1uL << INTC_PBFLAG_FLAG3_Pos)
+#define PnFLAG_FLAG2             (0x1uL << INTC_PBFLAG_FLAG2_Pos)
+#define PnFLAG_FLAG1             (0x1uL << INTC_PBFLAG_FLAG1_Pos)
+#define PnFLAG_FLAG0             (0x1uL << INTC_PBFLAG_FLAG0_Pos)
+
+// External Interrupt Configuration Selection Control
+#ifdef PORTA
+#define CONFx_PA                 INTC_EINT0CONF1_CONF0_PA   /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#endif
+#ifdef PORTB
+#define CONFx_PB                 INTC_EINT0CONF1_CONF0_PB   /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#endif
+#ifdef PORTC
+#define CONFx_PC                 INTC_EINT0CONF1_CONF0_PC   /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#endif
+#ifdef PORTD
+#define CONFx_PD                 INTC_EINT0CONF1_CONF0_PD   /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#endif
+#ifdef PORTE
+#define CONFx_PE                 INTC_EINT0CONF1_CONF0_PE   /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#endif
+#ifdef PORTF
+#define CONFx_PF                 INTC_EINT0CONF1_CONF0_PF   /**< Available EINT Pin: PB[11:0], PC[3:0], PE[3:0] */
+#endif
+
+// Interrupt Source Mask Control
+/*
+#define LVI_MASK                 (0x1uL << 0)
+#define WUT_MASK                 (0x1uL << 1)
+#define WDT_MASK                 (0x1uL << 2)
+#define EINT0_MASK               (0x1uL << 3)
+#define EINT1_MASK               (0x1uL << 4)
+#define EINT2_MASK               (0x1uL << 5)
+#define EINT3_MASK               (0x1uL << 6)
+#define TIMER10_MASK             (0x1uL << 7)
+#define TIMER11_MASK             (0x1uL << 8)
+#define TIMER12_MASK             (0x1uL << 9)
+#define I2C0_MASK                (0x1uL << 10)
+#define USART10_MASK             (0x1uL << 11)
+#define WT_MASK                  (0x1uL << 12)
+#define TIMER30_MASK             (0x1uL << 13)
+#define I2C1_MASK                (0x1uL << 14)
+#define TIMER20_MASK             (0x1uL << 15)
+#define TIMER21_MASK             (0x1uL << 16)
+#define USART11_MASK             (0x1uL << 17)
+#define ADC_MASK                 (0x1uL << 18)
+#define UART0_MASK               (0x1uL << 19)
+#define UART1_MASK               (0x1uL << 20)
+#define TIMER13_MASK             (0x1uL << 21)
+#define TIMER14_MASK             (0x1uL << 22)
+#define TIMER15_MASK             (0x1uL << 23)
+#define TIMER16_MASK             (0x1uL << 24)
+#define I2C2_MASK                (0x1uL << 25)
+#define UST12_MASK               (0x1uL << 26)
+#define UST13_MASK               (0x1uL << 27)
+*/
+#define MSK_IMSK31               (0x1uL << INTC_MSK_IMSK31_NULL_Pos)
+#define MSK_IMSK30               (0x1uL << INTC_MSK_IMSK30_NULL_Pos)
+#define MSK_IMSK29               (0x1uL << INTC_MSK_IMSK29_NULL_Pos)
+#define MSK_IMSK28               (0x1uL << INTC_MSK_IMSK28_NULL_Pos)
+#define MSK_USART13              (0x1uL << INTC_MSK_IMSK27_USART13_Pos)
+#define MSK_USART12              (0x1uL << INTC_MSK_IMSK26_USART12_Pos)
+#define MSK_I2C2                 (0x1uL << INTC_MSK_IMSK25_I2C2_Pos)
+#define MSK_TIMER16              (0x1uL << INTC_MSK_IMSK24_TIMER16_Pos)
+#define MSK_TIMER15              (0x1uL << INTC_MSK_IMSK23_TIMER15_Pos)
+#define MSK_TIMER14              (0x1uL << INTC_MSK_IMSK22_TIMER14_Pos)
+#define MSK_TIMER13              (0x1uL << INTC_MSK_IMSK21_TIMER13_Pos)
+#define MSK_UART1                (0x1uL << INTC_MSK_IMSK20_UART1_Pos)
+#define MSK_UART0                (0x1uL << INTC_MSK_IMSK19_UART0_Pos)
+#define MSK_ADC                  (0x1uL << INTC_MSK_IMSK18_ADC_Pos)
+#define MSK_USART11              (0x1uL << INTC_MSK_IMSK17_USART11_Pos)
+#define MSK_TIMER21              (0x1uL << INTC_MSK_IMSK16_TIMER21_Pos)
+#define MSK_TIMER20              (0x1uL << INTC_MSK_IMSK15_TIMER20_Pos)
+#define MSK_I2C1                 (0x1uL << INTC_MSK_IMSK14_I2C1_Pos)
+#define MSK_TIMER30              (0x1uL << INTC_MSK_IMSK13_TIMER30_Pos)
+#define MSK_WT                   (0x1uL << INTC_MSK_IMSK12_WT_Pos)
+#define MSK_USART10              (0x1uL << INTC_MSK_IMSK11_USART10_Pos)
+#define MSK_I2C0                 (0x1uL << INTC_MSK_IMSK10_I2C0_Pos)
+#define MSK_TIMER12              (0x1uL << INTC_MSK_IMSK9_TIMER12_Pos)
+#define MSK_TIMER11              (0x1uL << INTC_MSK_IMSK8_TIMER11_Pos)
+#define MSK_TIMER10              (0x1uL << INTC_MSK_IMSK7_TIMER10_Pos)
+#define MSK_EINT3                (0x1uL << INTC_MSK_IMSK6_EINT3_Pos)
+#define MSK_EINT2                (0x1uL << INTC_MSK_IMSK5_EINT2_Pos)
+#define MSK_EINT1                (0x1uL << INTC_MSK_IMSK4_EINT1_Pos)
+#define MSK_EINT0                (0x1uL << INTC_MSK_IMSK3_EINT0_Pos)
+#define MSK_WDT                  (0x1uL << INTC_MSK_IMSK2_WDT_Pos)
+#define MSK_WUT                  (0x1uL << INTC_MSK_IMSK1_WUT_Pos)
+#define MSK_LVI                  (0x1uL << INTC_MSK_IMSK0_LVI_Pos)
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+#ifdef PORTA
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PA Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPA_GetFg()                 (INTC->PAFLAG)
+#endif
+
+#ifdef PORTB
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PB Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPB_GetFg()                 (INTC->PBFLAG)
+#endif
+
+#ifdef PORTC
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PC Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPC_GetFg()                 (INTC->PCFLAG)
+#endif
+
+#ifdef PORTD
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PD Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPD_GetFg()                 (INTC->PDFLAG)
+#endif
+
+#ifdef PORTE
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PE Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPE_GetFg()                 (INTC->PEFLAG)
+#endif
+
+#ifdef PORTF
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PF Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPF_GetFg()                 (INTC->PFFLAG)
+#endif
+
+#ifdef PORTA
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PA Interrupt Flag
+ * @param[in]     u32Bit
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG0
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPA_ClrFgBits( u32Bit )     (INTC->PAFLAG = u32Bit)
+#endif
+
+#ifdef PORTB
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PB Interrupt Flag
+ * @param[in]     u32Bit
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG11
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPB_ClrFgBits( u32Bit )     (INTC->PBFLAG = u32Bit)
+#endif
+
+#ifdef PORTC
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PC Interrupt Flag
+ * @param[in]     u32Bit
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG3
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPC_ClrFgBits( u32Bit )     (INTC->PCFLAG = u32Bit)
+#endif
+
+#ifdef PORTD
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PD Interrupt Flag
+ * @param[in]     u32Bit
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG0
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPD_ClrFgBits( u32Bit )     (INTC->PDFLAG = u32Bit)
+#endif
+
+#ifdef PORTE
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PE Interrupt Flag
+ * @param[in]     u32Bit
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG3
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPE_ClrFgBits( u32Bit )     (INTC->PEFLAG = u32Bit)
+#endif
+
+#ifdef PORTF
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PF Interrupt Flag
+ * @param[in]     u32Bit
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG0
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+#define EIntPF_ClrFgBits( u32Bit )     (INTC->PFFLAG = u32Bit)
+#endif
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Mask Interrupt Source
+ * @param[in]     u32Msk
+ *                   Interrupt Source Mask
+ *                   -  MSK_LVI, MSK_WUT, MSK_WDT, MSK_EINT0, ...
+ * @return        None
+ * @details       This macro masks an interrupt vector
+ *//*-------------------------------------------------------------------------*/
+#define Int_Mask( u32Msk )             (INTC->MSK = (INTC->MSK) & ~u32Msk)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Unmask Interrupt Source
+ * @param[in]     u32UnMsk
+ *                   Interrupt Source Mask
+ *                   -  MSK_LVI, MSK_WUT, MSK_WDT, MSK_EINT0, ...
+ * @return        None
+ * @details       This macro unmasks an interrupt vector
+ *//*-------------------------------------------------------------------------*/
+#define Int_UnMask( u32UnMsk )         (INTC->MSK = (INTC->MSK) | u32UnMsk)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+void HAL_INT_EIntPx_SetReg( uint32_t u32Px, uint32_t u32pin, uint32_t u32Trig, uint32_t u32Con );
+void HAL_INT_EIntCfg( uint32_t u32TarIntNum, uint32_t u32SrcPort, uint32_t u32SrcPin );
+void HAL_INT_EInt_MaskEnable( uint32_t u32Src );
+void HAL_INT_EInt_MaskDisable( uint32_t u32Src );
+
+#ifdef PORTA
+void HAL_INT_EIntPA_ClearIntStatus( uint32_t u32Value );
+#endif
+#ifdef PORTB
+void HAL_INT_EIntPB_ClearIntStatus( uint32_t u32Value );
+#endif
+#ifdef PORTC
+void HAL_INT_EIntPC_ClearIntStatus( uint32_t u32Value );
+#endif
+#ifdef PORTD
+void HAL_INT_EIntPD_ClearIntStatus( uint32_t u32Value );
+#endif
+#ifdef PORTE
+void HAL_INT_EIntPE_ClearIntStatus( uint32_t u32Value );
+#endif
+#ifdef PORTF
+void HAL_INT_EIntPF_ClearIntStatus( uint32_t u32Value );
+#endif
+
+#ifdef PORTA
+uint32_t HAL_INT_EIntPA_GetIntStatus( void );
+#endif
+#ifdef PORTB
+uint32_t HAL_INT_EIntPB_GetIntStatus( void );
+#endif
+#ifdef PORTC
+uint32_t HAL_INT_EIntPC_GetIntStatus( void );
+#endif
+#ifdef PORTD
+uint32_t HAL_INT_EIntPD_GetIntStatus( void );
+#endif
+#ifdef PORTE
+uint32_t HAL_INT_EIntPE_GetIntStatus( void );
+#endif
+#ifdef PORTF
+uint32_t HAL_INT_EIntPF_GetIntStatus( void );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _INTC_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_lcd.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_lcd.h
new file mode 100644
index 0000000..de1b07c
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_lcd.h
@@ -0,0 +1,165 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_lcd.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for lcd firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _LCD_H_
+#define _LCD_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+//==========   LCD_CR   ========================================
+
+//----------   Internal LCD Bias Dividing Resistor Selection   ----------
+#define LCD_RLCD3       (0x0uL << 6)
+#define LCD_RLCD1       (0x1uL << 6)
+#define LCD_RLCD2       (0x2uL << 6)
+#define LCD_RLCD4       (0x3uL << 6)
+
+//----------   LCD Duty and Bias Selection   ----------
+#define LCD_8D4B        (0x0uL << 3)
+#define LCD_6D4B        (0x1uL << 3)
+#define LCD_5D3B        (0x2uL << 3)
+#define LCD_4D3B        (0x3uL << 3)
+#define LCD_3D3B        (0x4uL << 3)
+#define LCD_3D2B        (0x5uL << 3)
+
+//----------   LCD Clock Selection   ----------
+#define LCD_CLK128      (0x0uL << 1)
+#define LCD_CLK256      (0x1uL << 1)
+#define LCD_CLK512      (0x2uL << 1)
+#define LCD_CLK1024     (0x3uL << 1)
+
+//==========   LCD_BCCR   ========================================
+
+//----------   LCD Automatic Bias Control En/Disable   ----------
+#define LCD_ABCDIS      (0x0uL << 12)
+#define LCD_ABCEN       (0x1uL << 12)
+
+//----------   "Bias Mode A" time Selection   ----------
+#define LCD_BIA1CLK     (0x0uL << 8)
+#define LCD_BIA2CLK     (0x1uL << 8)
+#define LCD_BIA3CLK     (0x2uL << 8)
+#define LCD_BIA4CLK     (0x3uL << 8)
+#define LCD_BIA5CLK     (0x4uL << 8)
+#define LCD_BIA6CLK     (0x5uL << 8)
+#define LCD_BIA7CLK     (0x6uL << 8)
+#define LCD_BIA8CLK     (0x7uL << 8)
+
+//----------   LCD Contrast Control En/Disable   ----------
+#define LCD_CONTDIS     (0x0uL << 5)
+#define LCD_CONTEN      (0x1uL << 5)
+
+//----------   VLC0 Voltage Control   ----------
+#define LCD_VLC31       (0x0uL << 0)
+#define LCD_VLC30       (0x1uL << 0)
+#define LCD_VLC29       (0x2uL << 0)
+#define LCD_VLC28       (0x3uL << 0)
+#define LCD_VLC27       (0x4uL << 0)
+#define LCD_VLC26       (0x5uL << 0)
+#define LCD_VLC25       (0x6uL << 0)
+#define LCD_VLC24       (0x7uL << 0)
+#define LCD_VLC23       (0x8uL << 0)
+#define LCD_VLC22       (0x9uL << 0)
+#define LCD_VLC21       (0xAuL << 0)
+#define LCD_VLC20       (0xBuL << 0)
+#define LCD_VLC19       (0xCuL << 0)
+#define LCD_VLC18       (0xDuL << 0)
+#define LCD_VLC17       (0xEuL << 0)
+#define LCD_VLC16       (0xFuL << 0)
+
+//----------   Constant   ----------
+#define LCDBufSize      28
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+typedef struct
+{
+   /* LCD_CR */
+   uint32_t    Bias;          /**<  RestartEn = ENABLE or DISABLE */
+   uint32_t    Duty;
+   uint32_t    Clk;
+
+   /* LCD_BCCR */
+   uint32_t    AutoBiasEn;
+   uint32_t    BiasTime;
+   uint32_t    Contrast;
+   uint32_t    ContrastStep;
+} LCD_CFG_Type;
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         LCD Enable
+ * @details       This macro Enable LCD Block
+ *//*-------------------------------------------------------------------------*/
+#define LCDON()         (LCD->CR_b.DISP = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         LCD Disable
+ * @details       This macro Disable LCD Block
+ *//*-------------------------------------------------------------------------*/
+#define LCDOFF()        (LCD->CR_b.DISP = 0)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_LCD_Init( LCD_CFG_Type* LCD_Config );
+
+HAL_Status_Type HAL_LCD_SetRegister( uint32_t u32LCD_CR, uint32_t u32LCD_BCCR );
+HAL_Status_Type HAL_LCD_ClearDspRam( void );
+HAL_Status_Type HAL_LCD_WriteDspRam( uint8_t* write_buf, uint32_t u32Index, uint32_t size );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _LCD_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_libcfg.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_libcfg.h
new file mode 100644
index 0000000..1d1a18b
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_libcfg.h
@@ -0,0 +1,85 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_libcfg.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for libcfg firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _A31G12x_LIBCFG_H_
+#define _A31G12x_LIBCFG_H_
+
+/*******************************************************************************
+ * Included File
+ ******************************************************************************/
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
+the "CHECK_PARAM" macro in the FW library code */
+
+#define USE_FULL_ASSERT
+
+/* DEBUG_FRAMWORK ------------------------------ */
+#define _DEBUG_MSG
+
+
+/*******************************************************************************
+ * Public Macro
+ ******************************************************************************/
+
+#ifdef  USE_FULL_ASSERT
+   /*-------------------------------------------------------------------------*//**
+   * @brief         The CHECK_PARAM macro is used for function's parameters check.
+   *                It is used only if the library is compiled in DEBUG mode.
+   * @param         expr
+   *                   -  If expr is false, it calls check_failed() function
+   *                      which reports the name of the source file and the source
+   *                      line number of the call that failed.
+   *                   -  If expr is true, it returns no value.
+   * @return        None
+   *//*-------------------------------------------------------------------------*/
+   #define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+   #define CHECK_PARAM(expr) ((void)0U)
+#endif
+
+
+/*******************************************************************************
+ * Public Typedef
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Exported Public Function
+ ******************************************************************************/
+
+#ifdef  USE_FULL_ASSERT
+   void check_failed( uint8_t* file, uint32_t line );
+#endif
+
+#endif   /* _A31G12x_LIBCFG_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_pcu.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_pcu.h
new file mode 100644
index 0000000..7eac5b3
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_pcu.h
@@ -0,0 +1,267 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_pcu.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for pcu firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _PCU_H_
+#define _PCU_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+// Pin Mode & Pin Alternative Function Mask
+/*
+#define PCU_FUNC_Msk             (0x0FuL)
+#define PCU_MODE_Msk             (0x03uL)
+*/
+#define MODEx_Msk                Pn_MOD_MODE0_Msk
+#define AFSRx_Msk                Pn_AFSR1_AFSR0_Msk
+
+// Pin Alternative Function Selection Control
+/*
+#define FUNC0                    0x0            // Alternative Function 0
+#define FUNC1                    0x1            // Alternative Function 1
+#define FUNC2                    0x2            // Alternative Function 2
+#define FUNC3                    0x3            // Alternative Function 3
+#define FUNC4                    0x4            // Alternative Function 4
+// #define FUNC5                 0x5            // Alternative Function 5
+// #define FUNC6                 0x6            // Alternative Function 6
+// #define FUNC7                 0x7            // Alternative Function 7
+*/
+#define AFSRx_AF0                Pn_AFSR1_AFSR0_AF0
+#define AFSRx_AF1                Pn_AFSR1_AFSR0_AF1
+#define AFSRx_AF2                Pn_AFSR1_AFSR0_AF2
+#define AFSRx_AF3                Pn_AFSR1_AFSR0_AF3
+#define AFSRx_AF4                Pn_AFSR1_AFSR0_AF4
+// #define AFSRx_AF5             Pn_AFSR1_AFSR0_AF5
+// #define AFSRx_AF6             Pn_AFSR1_AFSR0_AF6
+// #define AFSRx_AF7             Pn_AFSR1_AFSR0_AF7
+
+// Pin Pull Up / Pull Down Resistor Enable Control
+/*
+#define DISPUPD                  0x0            // disable pu_pd
+#define ENPU                     0x1            // enable pull up
+#define ENPD                     0x2            // enable pull down
+*/
+#define PUPDx_Disable            Pn_PUPD_PUPD0_Disable
+#define PUPDx_EnablePU           Pn_PUPD_PUPD0_EnablePU
+#define PUPDx_EnablePD           Pn_PUPD_PUPD0_EnablePD
+
+// Debounce Filter Sampling Clock Selection Control
+/*
+#define HCLK_1                   (0x0uL << 16)
+#define HCLK_4                   (0x1uL << 16)
+#define HCLK_16                  (0x2uL << 16)
+#define HCLK_64                  (0x3uL << 16)
+#define HCLK_256                 (0x4uL << 16)
+#define HCLK_1024                (0x5uL << 16)
+*/
+#define DBCLK_HCLK1              (Pn_DBCR_DBCLK_HCLK1    << Pn_DBCR_DBCLK_Pos)   // HCLK/1
+#define DBCLK_HCLK4              (Pn_DBCR_DBCLK_HCLK4    << Pn_DBCR_DBCLK_Pos)   // HCLK/4
+#define DBCLK_HCLK16             (Pn_DBCR_DBCLK_HCLK16   << Pn_DBCR_DBCLK_Pos)   // HCLK/16
+#define DBCLK_HCLK64             (Pn_DBCR_DBCLK_HCLK64   << Pn_DBCR_DBCLK_Pos)   // HCLK/64
+#define DBCLK_HCLK256            (Pn_DBCR_DBCLK_HCLK256  << Pn_DBCR_DBCLK_Pos)   // HCLK/256
+#define DBCLK_HCLK1024           (Pn_DBCR_DBCLK_HCLK1024 << Pn_DBCR_DBCLK_Pos)   // HCLK/1024
+
+// Output Data Mask Control
+#define OUTDMSKx_Unmask          Pn_OUTDMSK_OUTDMSK0_Unmask
+#define OUTDMSKx_Mask            Pn_OUTDMSK_OUTDMSK0_Mask
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+/**   Pin Mode and Pin Type Selection Control */
+typedef enum
+{
+   INPUT = 0,
+   PUSH_PULL_OUTPUT,
+   ALTERN_FUNC,
+   OPEN_DRAIN_OUTPUT
+} PCU_PORT_MODE;
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Port n Input Data
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @return        Current value of GPIO port
+ * @details       This macro gets input data of port n.
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+#define GPIO_GetInData( Px )                 (Px->INDR)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get a bit of Port n
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @return        Current bit value of GPIO port
+ * @details       This macro gets a bit of port n.
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+#define GPIO_GetBit0( Px )                   (Px->INDR_b.INDR0)
+#define GPIO_GetBit1( Px )                   (Px->INDR_b.INDR1)
+#define GPIO_GetBit2( Px )                   (Px->INDR_b.INDR2)
+#define GPIO_GetBit3( Px )                   (Px->INDR_b.INDR3)
+#define GPIO_GetBit4( Px )                   (Px->INDR_b.INDR4)
+#define GPIO_GetBit5( Px )                   (Px->INDR_b.INDR5)
+#define GPIO_GetBit6( Px )                   (Px->INDR_b.INDR6)
+#define GPIO_GetBit7( Px )                   (Px->INDR_b.INDR7)
+#define GPIO_GetBit8( Px )                   (Px->INDR_b.INDR8)
+#define GPIO_GetBit9( Px )                   (Px->INDR_b.INDR9)
+#define GPIO_GetBit10( Px )                  (Px->INDR_b.INDR10)
+#define GPIO_GetBit11( Px )                  (Px->INDR_b.INDR11)
+#define GPIO_GetBit12( Px )                  (Px->INDR_b.INDR12)
+#define GPIO_GetBit13( Px )                  (Px->INDR_b.INDR13)
+#define GPIO_GetBit14( Px )                  (Px->INDR_b.INDR14)
+#define GPIO_GetBit15( Px )                  (Px->INDR_b.INDR15)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Port n Output Data
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     u32OutData
+ *                   Output Data of Port n
+ * @return        None
+ * @details       This macro sets output data of port n.
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+#define GPIO_SetOutData( Px, u32OutData )    (Px->OUTDR = u32OutData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set a bit of Port n
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @return        None
+ * @details       This macro sets a bit of port n.
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+#define GPIO_SetBit0( Px )                   (Px->BSR_b.BSR0 = 1)
+#define GPIO_SetBit1( Px )                   (Px->BSR_b.BSR1 = 1)
+#define GPIO_SetBit2( Px )                   (Px->BSR_b.BSR2 = 1)
+#define GPIO_SetBit3( Px )                   (Px->BSR_b.BSR3 = 1)
+#define GPIO_SetBit4( Px )                   (Px->BSR_b.BSR4 = 1)
+#define GPIO_SetBit5( Px )                   (Px->BSR_b.BSR5 = 1)
+#define GPIO_SetBit6( Px )                   (Px->BSR_b.BSR6 = 1)
+#define GPIO_SetBit7( Px )                   (Px->BSR_b.BSR7 = 1)
+#define GPIO_SetBit8( Px )                   (Px->BSR_b.BSR8 = 1)
+#define GPIO_SetBit9( Px )                   (Px->BSR_b.BSR9 = 1)
+#define GPIO_SetBit10( Px )                  (Px->BSR_b.BSR10 = 1)
+#define GPIO_SetBit11( Px )                  (Px->BSR_b.BSR11 = 1)
+#define GPIO_SetBit12( Px )                  (Px->BSR_b.BSR12 = 1)
+#define GPIO_SetBit13( Px )                  (Px->BSR_b.BSR13 = 1)
+#define GPIO_SetBit14( Px )                  (Px->BSR_b.BSR14 = 1)
+#define GPIO_SetBit15( Px )                  (Px->BSR_b.BSR15 = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear a bit of Port n
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @return        None
+ * @details       This macro clears a bit of port n.
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+#define GPIO_ClrBit0( Px )                   (Px->BCR_b.BCR0 = 1)
+#define GPIO_ClrBit1( Px )                   (Px->BCR_b.BCR1 = 1)
+#define GPIO_ClrBit2( Px )                   (Px->BCR_b.BCR2 = 1)
+#define GPIO_ClrBit3( Px )                   (Px->BCR_b.BCR3 = 1)
+#define GPIO_ClrBit4( Px )                   (Px->BCR_b.BCR4 = 1)
+#define GPIO_ClrBit5( Px )                   (Px->BCR_b.BCR5 = 1)
+#define GPIO_ClrBit6( Px )                   (Px->BCR_b.BCR6 = 1)
+#define GPIO_ClrBit7( Px )                   (Px->BCR_b.BCR7 = 1)
+#define GPIO_ClrBit8( Px )                   (Px->BCR_b.BCR8 = 1)
+#define GPIO_ClrBit9( Px )                   (Px->BCR_b.BCR9 = 1)
+#define GPIO_ClrBit10( Px )                  (Px->BCR_b.BCR10 = 1)
+#define GPIO_ClrBit11( Px )                  (Px->BCR_b.BCR11 = 1)
+#define GPIO_ClrBit12( Px )                  (Px->BCR_b.BCR12 = 1)
+#define GPIO_ClrBit13( Px )                  (Px->BCR_b.BCR13 = 1)
+#define GPIO_ClrBit14( Px )                  (Px->BCR_b.BCR14 = 1)
+#define GPIO_ClrBit15( Px )                  (Px->BCR_b.BCR15 = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Port n Output Data Mask
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     u32Msk
+ *                   Output Data Mask of Port n
+ *                   -  OUTDMSKx_Unmask, OUTDMSKx_Mask
+ * @return        None
+ * @details       This macro sets mask or unmask for output data of port n.
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+#define GPIO_OutMsk( Px, u32Msk )            (Px->OUTDMSK = u32Msk)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+void HAL_GPIO_Init( Pn_Type* Px, uint32_t u32Mode, uint32_t u32Type, uint32_t u32Afsr1, uint32_t u32Afsr2, uint32_t u32PuPd );
+
+void HAL_GPIO_ConfigFunction( Pn_Type* Px, uint8_t pin_no, uint32_t func );
+void HAL_GPIO_ConfigOutput( Pn_Type* Px, uint8_t pin_no, PCU_PORT_MODE dir_type );
+void HAL_GPIO_ConfigOutDataMask( Pn_Type* Px, uint8_t pin_no, FunctionalState maskctrl );
+void HAL_GPIO_ConfigPullup( Pn_Type* Px, uint8_t pin_no, uint8_t pullupdown );
+void HAL_GPIO_SetDebouncePin( Pn_Type* Px, uint32_t u32Pins, uint32_t u32Debnc );
+
+void HAL_GPIO_SetPin( Pn_Type* Px, uint16_t bitValue );
+void HAL_GPIO_ClearPin( Pn_Type* Px, uint16_t bitValue );
+void HAL_GPIO_TogglePin( Pn_Type* Px, uint16_t bitValue );
+void HAL_GPIO_WritePin( Pn_Type* Px, uint16_t Value );
+uint16_t HAL_GPIO_ReadPin( Pn_Type* Px );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _PCU_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_pwr.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_pwr.h
new file mode 100644
index 0000000..9b39b79
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_pwr.h
@@ -0,0 +1,57 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_pwr.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for pwr firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _PWR_H_
+#define _PWR_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+void HAL_PWR_EnterSleepMode( void );
+void HAL_PWR_EnterPowerDownMode( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /*_PWR_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_scu.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_scu.h
new file mode 100644
index 0000000..7b16922
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_scu.h
@@ -0,0 +1,578 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_scu.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for scu firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _SCU_H_
+#define _SCU_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+// Boot Pin Function Selection Control
+/*
+#define B_INCLUDE_RSTB           2
+#define B_POR_ONLY               3
+*/
+#define BFIND_PORorEXTR          SCUCC_BTPSCR_BFIND_PORorEXTR
+#define BFIND_POR                SCUCC_BTPSCR_BFIND_POR
+
+// HIRC Fine Trim One Step Change Control
+#define HIRC_UP_ONESTEP          0
+#define HIRC_DOWN_ONESTEP        1
+
+// WDTRC Fine Trim One Step Change Control
+#define WDTRC_UP_ONESTEP         0
+#define WDTRC_DOWN_ONESTEP       1
+
+
+// MCLK Selection Control
+/*
+#define SCU_HIRC                 (0x0uL << 0)
+#define SCU_XMOSC                (0x1uL << 0)
+#define SCU_XSOSC                (0x2uL << 0)
+#define SCU_WDTRC                (0x3uL << 0)
+*/
+#define MCLKSEL_HIRC             (SCUCG_SCCR_MCLKSEL_HIRC  << SCUCG_SCCR_MCLKSEL_Pos)
+#define MCLKSEL_XMOSC            (SCUCG_SCCR_MCLKSEL_XMOSC << SCUCG_SCCR_MCLKSEL_Pos)
+#define MCLKSEL_XSOSC            (SCUCG_SCCR_MCLKSEL_XSOSC << SCUCG_SCCR_MCLKSEL_Pos)
+#define MCLKSEL_WDTRC            (SCUCG_SCCR_MCLKSEL_WDTRC << SCUCG_SCCR_MCLKSEL_Pos)
+
+// HIRC Selection Control
+/*
+#define HIRC_40M                 (0x0uL << 12)
+#define HIRC_20M                 (0x1uL << 12)
+#define HIRC_10M                 (0x2uL << 12)
+#define HIRC_5M                  (0x3uL << 12)
+*/
+#define HIRCSEL_HIRC1            (SCUCG_CLKSRCR_HIRCSEL_HIRC1 << SCUCG_CLKSRCR_HIRCSEL_Pos)  // 40MHz HIRC
+#define HIRCSEL_HIRC2            (SCUCG_CLKSRCR_HIRCSEL_HIRC2 << SCUCG_CLKSRCR_HIRCSEL_Pos)  // 20MHz HIRC
+#define HIRCSEL_HIRC4            (SCUCG_CLKSRCR_HIRCSEL_HIRC4 << SCUCG_CLKSRCR_HIRCSEL_Pos)  // 10MHz HIRC
+#define HIRCSEL_HIRC8            (SCUCG_CLKSRCR_HIRCSEL_HIRC8 << SCUCG_CLKSRCR_HIRCSEL_Pos)  //  5MHz HIRC 
+
+// XMFRNG Selection Control
+/*
+#define XTAL_XM                  (0x0uL << 8)
+#define EXT_XM                   (0x1uL << 8)
+*/
+#define XMFRNG_Xtal              (SCUCG_CLKSRCR_XMFRNG_Xtal  << SCUCG_CLKSRCR_XMFRNG_Pos)
+#define XMFRNG_Clock             (SCUCG_CLKSRCR_XMFRNG_Clock << SCUCG_CLKSRCR_XMFRNG_Pos)
+
+// System Clock Source Enable Control
+/*
+#define EN_XSOSC                 (0x1uL << 0)
+#define EN_XMOSC                 (0x1uL << 1)
+#define EN_HIRC                  (0x1uL << 2)
+#define EN_WDTRC                 (0x1uL << 3)
+*/
+#define CLKSRCR_WDTRCEN          (0x1uL << SCUCG_CLKSRCR_WDTRCEN_Pos)
+#define CLKSRCR_HIRCEN           (0x1uL << SCUCG_CLKSRCR_HIRCEN_Pos)
+#define CLKSRCR_XMOSCEN          (0x1uL << SCUCG_CLKSRCR_XMOSCEN_Pos)
+#define CLKSRCR_XSOSCEN          (0x1uL << SCUCG_CLKSRCR_XSOSCEN_Pos)
+
+// WT & LCD Clock Divider Selection Control (Divider 2)
+/*
+#define MCLK_64                  0
+#define MCLK_128                 1
+#define MCLK_256                 2
+#define MCLK_512                 3
+#define MCLK_1024                4
+*/
+#define WLDIV_MCLK64             (SCUCG_SCDIVR1_WLDIV_MCLK64   << SCUCG_SCDIVR1_WLDIV_Pos)   // MCLK/64
+#define WLDIV_MCLK128            (SCUCG_SCDIVR1_WLDIV_MCLK128  << SCUCG_SCDIVR1_WLDIV_Pos)   // MCLK/128
+#define WLDIV_MCLK256            (SCUCG_SCDIVR1_WLDIV_MCLK256  << SCUCG_SCDIVR1_WLDIV_Pos)   // MCLK/256
+#define WLDIV_MCLK512            (SCUCG_SCDIVR1_WLDIV_MCLK512  << SCUCG_SCDIVR1_WLDIV_Pos)   // MCLK/512
+#define WLDIV_MCLK1024           (SCUCG_SCDIVR1_WLDIV_MCLK1024 << SCUCG_SCDIVR1_WLDIV_Pos)   // MCLK/1024
+
+// HCLK Divider Selection Control (Divider 0)
+/*
+#define MCLK_16                  0
+#define MCLK_8                   1
+#define MCLK_4                   2
+#define MCLK_2                   3
+#define MCLK_1                   4
+*/
+#define HDIV_MCLK16              (SCUCG_SCDIVR1_HDIV_MCLK16 << SCUCG_SCDIVR1_HDIV_Pos)    // MCLK/16
+#define HDIV_MCLK8               (SCUCG_SCDIVR1_HDIV_MCLK8  << SCUCG_SCDIVR1_HDIV_Pos)    // MCLK/8    
+#define HDIV_MCLK4               (SCUCG_SCDIVR1_HDIV_MCLK4  << SCUCG_SCDIVR1_HDIV_Pos)    // MCLK/4
+#define HDIV_MCLK2               (SCUCG_SCDIVR1_HDIV_MCLK2  << SCUCG_SCDIVR1_HDIV_Pos)    // MCLK/2
+#define HDIV_MCLK1               (SCUCG_SCDIVR1_HDIV_MCLK1  << SCUCG_SCDIVR1_HDIV_Pos)    // MCLK/1
+
+// SysTick Timer Clock Divider Selection Control (Divider 3)
+/*
+#define SCU_HCLK_1               0
+#define SCU_HCLK_2               1
+#define SCU_HCLK_4               2
+#define SCU_HCLK_8               3
+*/
+#define SYSTDIV_HCLK1            (SCUCG_SCDIVR2_SYSTDIV_HCLK1 << SCUCG_SCDIVR2_SYSTDIV_Pos)  // HCLK/1
+#define SYSTDIV_HCLK2            (SCUCG_SCDIVR2_SYSTDIV_HCLK2 << SCUCG_SCDIVR2_SYSTDIV_Pos)  // HCLK/2
+#define SYSTDIV_HCLK4            (SCUCG_SCDIVR2_SYSTDIV_HCLK4 << SCUCG_SCDIVR2_SYSTDIV_Pos)  // HCLK/4
+#define SYSTDIV_HCLK8            (SCUCG_SCDIVR2_SYSTDIV_HCLK8 << SCUCG_SCDIVR2_SYSTDIV_Pos)  // HCLK/8
+
+// PCLK Divider Selection Control (Divider 1)
+#define PDIV_HCLK1               (SCUCG_SCDIVR2_PDIV_HCLK1 << SCUCG_SCDIVR2_PDIV_Pos)  // HCLK/1
+#define PDIV_HCLK2               (SCUCG_SCDIVR2_PDIV_HCLK2 << SCUCG_SCDIVR2_PDIV_Pos)  // HCLK/2
+#define PDIV_HCLK4               (SCUCG_SCDIVR2_PDIV_HCLK4 << SCUCG_SCDIVR2_PDIV_Pos)  // HCLK/4
+#define PDIV_HCLK8               (SCUCG_SCDIVR2_PDIV_HCLK8 << SCUCG_SCDIVR2_PDIV_Pos)  // HCLK/8
+
+// Clock Output Enable/Disable Control
+/*
+#define DIS_CLKOUT               0
+#define EN_CLKOUT                1
+*/
+#define CLKOEN_Disable           SCUCG_CLKOCR_CLKOEN_Disable
+#define CLKOEN_Enable            SCUCG_CLKOCR_CLKOEN_Enable
+
+// Clock Output Polarity Selection Control
+/*
+#define POL_L                    (0x0uL << 6)
+#define POL_H                    (0x1uL << 6)
+*/
+#define POLSEL_Low               (SCUCG_CLKOCR_POLSEL_Low  << SCUCG_CLKOCR_POLSEL_Pos)    // Low level during disable  
+#define POLSEL_High              (SCUCG_CLKOCR_POLSEL_High << SCUCG_CLKOCR_POLSEL_Pos)    // High level during disable
+
+// Clock Output Divider Selection Control
+/*
+#define CLKODIV_1                (0x0uL << 3)
+#define CLKODIV_2                (0x1uL << 3)
+#define CLKODIV_4                (0x2uL << 3)
+#define CLKODIV_8                (0x3uL << 3)
+#define CLKODIV_16               (0x4uL << 3)
+#define CLKODIV_32               (0x5uL << 3)
+#define CLKODIV_64               (0x6uL << 3)
+#define CLKODIV_128              (0x7uL << 3)
+*/
+#define CLKODIV_SelectedClock1   (SCUCG_CLKOCR_CLKODIV_SelectedClock1   << SCUCG_CLKOCR_CLKODIV_Pos)  // Selected Clock/1
+#define CLKODIV_SelectedClock2   (SCUCG_CLKOCR_CLKODIV_SelectedClock2   << SCUCG_CLKOCR_CLKODIV_Pos)  // Selected Clock/2
+#define CLKODIV_SelectedClock4   (SCUCG_CLKOCR_CLKODIV_SelectedClock4   << SCUCG_CLKOCR_CLKODIV_Pos)  // Selected Clock/4
+#define CLKODIV_SelectedClock8   (SCUCG_CLKOCR_CLKODIV_SelectedClock8   << SCUCG_CLKOCR_CLKODIV_Pos)  // Selected Clock/8
+#define CLKODIV_SelectedClock16  (SCUCG_CLKOCR_CLKODIV_SelectedClock16  << SCUCG_CLKOCR_CLKODIV_Pos)  // Selected Clock/16
+#define CLKODIV_SelectedClock32  (SCUCG_CLKOCR_CLKODIV_SelectedClock32  << SCUCG_CLKOCR_CLKODIV_Pos)  // Selected Clock/32
+#define CLKODIV_SelectedClock64  (SCUCG_CLKOCR_CLKODIV_SelectedClock64  << SCUCG_CLKOCR_CLKODIV_Pos)  // Selected Clock/64
+#define CLKODIV_SelectedClock128 (SCUCG_CLKOCR_CLKODIV_SelectedClock128 << SCUCG_CLKOCR_CLKODIV_Pos)  // Selected Clock/128
+
+// Clock Output Target Selection Control
+/*
+#define MCLK_OUT                 (0x0uL << 0)
+#define WDTRC_OUT                (0x1uL << 0)
+#define HIRC_OUT                 (0x2uL << 0)
+#define HCLK_OUT                 (0x3uL << 0)
+#define PCLK_OUT                 (0x4uL << 0)
+*/
+#define CLKOS_MCLK               (SCUCG_CLKOCR_CLKOS_MCLK  << SCUCG_CLKOCR_CLKOS_Pos)
+#define CLKOS_WDTRC              (SCUCG_CLKOCR_CLKOS_WDTRC << SCUCG_CLKOCR_CLKOS_Pos)
+#define CLKOS_HIRC               (SCUCG_CLKOCR_CLKOS_HIRC  << SCUCG_CLKOCR_CLKOS_Pos)
+#define CLKOS_HCLK               (SCUCG_CLKOCR_CLKOS_HCLK  << SCUCG_CLKOCR_CLKOS_Pos)
+#define CLKOS_PCLK               (SCUCG_CLKOCR_CLKOS_PCLK  << SCUCG_CLKOCR_CLKOS_Pos)
+
+// Clock Monitoring Action Selection Control
+/*
+#define FLAG_CHK_M               (0x0uL << 5)
+#define RST_GEN_M                (0x1uL << 5)
+#define SYS_CHG_M                (0x2uL << 5)
+*/
+#define MACTS_FlagChk            (SCUCG_CMONCR_MACTS_FlagChk   << SCUCG_CMONCR_MACTS_Pos)
+#define MACTS_RstGen             (SCUCG_CMONCR_MACTS_RstGen    << SCUCG_CMONCR_MACTS_Pos)
+#define MACTS_SysClkChg          (SCUCG_CMONCR_MACTS_SysClkChg << SCUCG_CMONCR_MACTS_Pos)
+
+// Clock Monitoring Target Selection Control
+/*
+#define MCLK_MON                 (0x0uL << 0)
+#define HIRC_MON                 (0x1uL << 0)
+#define XMOSC_MON                (0x2uL << 0)
+#define XSOSC_MON                (0x3uL << 0)
+*/
+#define MONCS_MCLK               (SCUCG_CMONCR_MONCS_MCLK  << SCUCG_CMONCR_MONCS_Pos)
+#define MONCS_HIRC               (SCUCG_CMONCR_MONCS_HIRC  << SCUCG_CMONCR_MONCS_Pos)
+#define MONCS_XMOSC              (SCUCG_CMONCR_MONCS_XMOSC << SCUCG_CMONCR_MONCS_Pos)
+#define MONCS_XSOSC              (SCUCG_CMONCR_MONCS_XSOSC << SCUCG_CMONCR_MONCS_Pos)
+
+// Peripheral Clock Enable Control 1
+/*
+#define PERI_PA                  (0x1uL << 0)
+#define PERI_PB                  (0x1uL << 1)
+#define PERI_PC                  (0x1uL << 2)
+#define PERI_PD                  (0x1uL << 3)
+#define PERI_PE                  (0x1uL << 4)
+#define PERI_PF                  (0x1uL << 5)
+#define PERI_T13                 (0x1uL << 8)
+#define PERI_T14                 (0x1uL << 9)
+#define PERI_T15                 (0x1uL << 10)
+#define PERI_T16                 (0x1uL << 11)
+#define PERI_T10                 (0x1uL << 16)
+#define PERI_T11                 (0x1uL << 17)
+#define PERI_T12                 (0x1uL << 18)
+#define PERI_T30                 (0x1uL << 19)
+#define PERI_T20                 (0x1uL << 20)
+#define PERI_T21                 (0x1uL << 21)
+*/
+#define PPCLKEN1_T21CLKE         (0x1uL << SCUCG_PPCLKEN1_T21CLKE_Pos)
+#define PPCLKEN1_T20CLKE         (0x1uL << SCUCG_PPCLKEN1_T20CLKE_Pos)
+#define PPCLKEN1_T30CLKE         (0x1uL << SCUCG_PPCLKEN1_T30CLKE_Pos)
+#define PPCLKEN1_T12CLKE         (0x1uL << SCUCG_PPCLKEN1_T12CLKE_Pos)
+#define PPCLKEN1_T11CLKE         (0x1uL << SCUCG_PPCLKEN1_T11CLKE_Pos)
+#define PPCLKEN1_T10CLKE         (0x1uL << SCUCG_PPCLKEN1_T10CLKE_Pos)
+#define PPCLKEN1_T16CLKE         (0x1uL << SCUCG_PPCLKEN1_T16CLKE_Pos)
+#define PPCLKEN1_T15CLKE         (0x1uL << SCUCG_PPCLKEN1_T15CLKE_Pos)
+#define PPCLKEN1_T14CLKE         (0x1uL << SCUCG_PPCLKEN1_T14CLKE_Pos)
+#define PPCLKEN1_T13CLKE         (0x1uL << SCUCG_PPCLKEN1_T13CLKE_Pos)
+#define PPCLKEN1_PFCLKE          (0x1uL << SCUCG_PPCLKEN1_PFCLKE_Pos)
+#define PPCLKEN1_PECLKE          (0x1uL << SCUCG_PPCLKEN1_PECLKE_Pos)
+#define PPCLKEN1_PDCLKE          (0x1uL << SCUCG_PPCLKEN1_PDCLKE_Pos)
+#define PPCLKEN1_PCCLKE          (0x1uL << SCUCG_PPCLKEN1_PCCLKE_Pos)
+#define PPCLKEN1_PBCLKE          (0x1uL << SCUCG_PPCLKEN1_PBCLKE_Pos)
+#define PPCLKEN1_PACLKE          (0x1uL << SCUCG_PPCLKEN1_PACLKE_Pos)
+
+// Peripheral Clock Enable Control 2
+/*
+#define PERI_UST10               (0x1uL << 0)
+#define PERI_UST11               (0x1uL << 1)
+#define PERI_UT0                 (0x1uL << 2)
+#define PERI_UT1                 (0x1uL << 3)
+#define PERI_UST12               (0x1uL << 4)
+#define PERI_UST13               (0x1uL << 5)
+#define PERI_I2C0                (0x1uL << 6)
+#define PERI_I2C1                (0x1uL << 7)
+#define PERI_I2C2                (0x1uL << 8)
+#define PERI_ADC                 (0x1uL << 10)
+#define PERI_CRC                 (0x1uL << 12)
+#define PERI_LCD                 (0x1uL << 13)
+#define PERI_WT                  (0x1uL << 16)
+#define PERI_WDT                 (0x1uL << 17)
+#define PERI_LVI                 (0x1uL << 18)
+#define PERI_FMC                 (0x1uL << 19)
+*/
+#define PPCLKEN2_FMCLKE          (0x1uL << SCUCG_PPCLKEN2_FMCLKE_Pos)
+#define PPCLKEN2_LVICLKE         (0x1uL << SCUCG_PPCLKEN2_LVICLKE_Pos)
+#define PPCLKEN2_WDTCLKE         (0x1uL << SCUCG_PPCLKEN2_WDTCLKE_Pos)
+#define PPCLKEN2_WTCLKE          (0x1uL << SCUCG_PPCLKEN2_WTCLKE_Pos)
+#define PPCLKEN2_LCDCLKE         (0x1uL << SCUCG_PPCLKEN2_LCDCLKE_Pos)
+#define PPCLKEN2_CRCLKE          (0x1uL << SCUCG_PPCLKEN2_CRCLKE_Pos)
+#define PPCLKEN2_ADCLKE          (0x1uL << SCUCG_PPCLKEN2_ADCLKE_Pos)
+#define PPCLKEN2_I2C2CLKE        (0x1uL << SCUCG_PPCLKEN2_I2C2CLKE_Pos)
+#define PPCLKEN2_I2C1CLKE        (0x1uL << SCUCG_PPCLKEN2_I2C1CLKE_Pos)
+#define PPCLKEN2_I2C0CLKE        (0x1uL << SCUCG_PPCLKEN2_I2C0CLKE_Pos)
+#define PPCLKEN2_UST13CLKE       (0x1uL << SCUCG_PPCLKEN2_UST13CLKE_Pos)
+#define PPCLKEN2_UST12CLKE       (0x1uL << SCUCG_PPCLKEN2_UST12CLKE_Pos)
+#define PPCLKEN2_UT1CLKE         (0x1uL << SCUCG_PPCLKEN2_UT1CLKE_Pos)
+#define PPCLKEN2_UT0CLKE         (0x1uL << SCUCG_PPCLKEN2_UT0CLKE_Pos)
+#define PPCLKEN2_UST11CLKE       (0x1uL << SCUCG_PPCLKEN2_UST11CLKE_Pos)
+#define PPCLKEN2_UST10CLKE       (0x1uL << SCUCG_PPCLKEN2_UST10CLKE_Pos)
+
+// Peripheral Clock Enable/Disable Control
+/*
+#define DIS_PERICLK              0
+#define EN_PERICLK               1
+*/
+#define PPxCLKE_Disable          SCUCG_PPCLKEN1_PACLKE_Disable
+#define PPxCLKE_Enable           SCUCG_PPCLKEN1_PACLKE_Enable
+
+// Timer/Counter 20 Clock Selecion Control
+/*
+#define SCUCG_T20CLK             (SCUCG_PPCLKSR_T20CLK_Msk)
+#define SCUCG_T20CLK_XSOSC       (0x0uL << SCUCG_PPCLKSR_T20CLK_Pos)
+#define SCUCG_T20CLK_PCLK        (0x1uL << SCUCG_PPCLKSR_T20CLK_Pos)
+*/
+#define PPCLKSR_T20CLK           (SCUCG_PPCLKSR_T20CLK_Msk)
+#define T20CLK_XSOSC             (SCUCG_PPCLKSR_T20CLK_XSOSC << SCUCG_PPCLKSR_T20CLK_Pos)
+#define T20CLK_PCLK              (SCUCG_PPCLKSR_T20CLK_PCLK  << SCUCG_PPCLKSR_T20CLK_Pos)
+
+// Timer/Counter 30 Clock Selection Control
+/*
+#define SCUCG_T30CLK             (SCUCG_PPCLKSR_T30CLK_Msk)
+#define SCUCG_T30CLK_MCLK        (0x0uL << SCUCG_PPCLKSR_T30CLK_Pos)
+#define SCUCG_T30CLK_PCLK        (0x1uL << SCUCG_PPCLKSR_T30CLK_Pos)
+*/
+#define PPCLKSR_T30CLK           (SCUCG_PPCLKSR_T30CLK_Msk)
+#define T30CLK_MCLK              (SCUCG_PPCLKSR_T30CLK_MCLK << SCUCG_PPCLKSR_T30CLK_Pos)
+#define T30CLK_PCLK              (SCUCG_PPCLKSR_T30CLK_PCLK << SCUCG_PPCLKSR_T30CLK_Pos)
+
+// LCD Driver Clock Selection Control
+/*
+#define SCUCG_LCDCLK             (SCUCG_PPCLKSR_LCDCLK_Msk)
+#define SCUCG_LCDCLK_MCLK        (0x0uL << SCUCG_PPCLKSR_LCDCLK_Pos)
+#define SCUCG_LCDCLK_XSOSC       (0x1uL << SCUCG_PPCLKSR_LCDCLK_Pos)
+#define SCUCG_LCDCLK_WDTRC       (0x2uL << SCUCG_PPCLKSR_LCDCLK_Pos)
+*/
+#define PPCLKSR_LCDCLK           (SCUCG_PPCLKSR_LCDCLK_Msk)
+#define LCDCLK_DividedMCLK       (SCUCG_PPCLKSR_LCDCLK_DividedMCLK << SCUCG_PPCLKSR_LCDCLK_Pos)
+#define LCDCLK_XSOSC             (SCUCG_PPCLKSR_LCDCLK_XSOSC       << SCUCG_PPCLKSR_LCDCLK_Pos)
+#define LCDCLK_WDTRC             (SCUCG_PPCLKSR_LCDCLK_WDTRC       << SCUCG_PPCLKSR_LCDCLK_Pos)
+
+// Watch Timer Clock Selection Control
+/*
+#define SCUCG_WTCLK              (SCUCG_PPCLKSR_WTCLK_Msk)
+#define SCUCG_WTCLK_MCLK         (0x0uL << SCUCG_PPCLKSR_WTCLK_Pos)
+#define SCUCG_WTCLK_XSOSC        (0x1uL << SCUCG_PPCLKSR_WTCLK_Pos)
+#define SCUCG_WTCLK_WDTRC        (0x2uL << SCUCG_PPCLKSR_WTCLK_Pos)
+*/
+#define PPCLKSR_WTCLK            (SCUCG_PPCLKSR_WTCLK_Msk)
+#define WTCLK_DividedMCLK        (SCUCG_PPCLKSR_WTCLK_DividedMCLK << SCUCG_PPCLKSR_WTCLK_Pos)
+#define WTCLK_XSOSC              (SCUCG_PPCLKSR_WTCLK_XSOSC       << SCUCG_PPCLKSR_WTCLK_Pos)
+#define WTCLK_WDTRC              (SCUCG_PPCLKSR_WTCLK_WDTRC       << SCUCG_PPCLKSR_WTCLK_Pos)
+
+// Watch-Dog Timer Clock Selection Control
+/*
+#define SCUCG_WDTCLK             (SCUCG_PPCLKSR_WDTCLK_Msk)
+#define SCUCG_WDTCLK_WDTRC       (0x0uL << SCUCG_PPCLKSR_WDTCLK_Pos)
+#define SCUCG_WDTCLK_PCLK        (0x1uL << SCUCG_PPCLKSR_WDTCLK_Pos)
+*/
+#define PPCLKSR_WDTCLK           (SCUCG_PPCLKSR_WDTCLK_Msk)
+#define WDTCLK_WDTRC             (SCUCG_PPCLKSR_WDTCLK_WDTRC << SCUCG_PPCLKSR_WDTCLK_Pos)
+#define WDTCLK_PCLK              (SCUCG_PPCLKSR_WDTCLK_PCLK  << SCUCG_PPCLKSR_WDTCLK_Pos)
+
+// Peripheral Reset Control 1
+#define PPRST1_T21RST            (0x1uL << SCUCG_PPRST1_T21RST_Pos)
+#define PPRST1_T20RST            (0x1uL << SCUCG_PPRST1_T20RST_Pos)
+#define PPRST1_T30RST            (0x1uL << SCUCG_PPRST1_T30RST_Pos)
+#define PPRST1_T12RST            (0x1uL << SCUCG_PPRST1_T12RST_Pos)
+#define PPRST1_T11RST            (0x1uL << SCUCG_PPRST1_T11RST_Pos)
+#define PPRST1_T10RST            (0x1uL << SCUCG_PPRST1_T10RST_Pos)
+#define PPRST1_T16RST            (0x1uL << SCUCG_PPRST1_T16RST_Pos)
+#define PPRST1_T15RST            (0x1uL << SCUCG_PPRST1_T15RST_Pos)
+#define PPRST1_T14RST            (0x1uL << SCUCG_PPRST1_T14RST_Pos)
+#define PPRST1_T13RST            (0x1uL << SCUCG_PPRST1_T13RST_Pos)
+#define PPRST1_PFRST             (0x1uL << SCUCG_PPRST1_PFRST_Pos)
+#define PPRST1_PERST             (0x1uL << SCUCG_PPRST1_PERST_Pos)
+#define PPRST1_PDRST             (0x1uL << SCUCG_PPRST1_PDRST_Pos)
+#define PPRST1_PCRST             (0x1uL << SCUCG_PPRST1_PCRST_Pos)
+#define PPRST1_PBRST             (0x1uL << SCUCG_PPRST1_PBRST_Pos)
+#define PPRST1_PARST             (0x1uL << SCUCG_PPRST1_PARST_Pos)
+
+// Peripheral Reset Control 2
+#define PPRST2_FMCRST            (0x1uL << SCUCG_PPRST2_FMCRST_Pos)
+#define PPRST2_LVIRST            (0x1uL << SCUCG_PPRST2_LVIRST_Pos)
+#define PPRST2_WTRST             (0x1uL << SCUCG_PPRST2_WTRST_Pos)
+#define PPRST2_LCDRST            (0x1uL << SCUCG_PPRST2_LCDRST_Pos)
+#define PPRST2_CRRST             (0x1uL << SCUCG_PPRST2_CRRST_Pos)
+#define PPRST2_ADRST             (0x1uL << SCUCG_PPRST2_ADRST_Pos)
+#define PPRST2_I2C2RST           (0x1uL << SCUCG_PPRST2_I2C2RST_Pos)
+#define PPRST2_I2C1RST           (0x1uL << SCUCG_PPRST2_I2C1RST_Pos)
+#define PPRST2_I2C0RST           (0x1uL << SCUCG_PPRST2_I2C0RST_Pos)
+#define PPRST2_UST13RST          (0x1uL << SCUCG_PPRST2_UST13RST_Pos)
+#define PPRST2_UST12RST          (0x1uL << SCUCG_PPRST2_UST12RST_Pos)
+#define PPRST2_UT1RST            (0x1uL << SCUCG_PPRST2_UT1RST_Pos)
+#define PPRST2_UT0RST            (0x1uL << SCUCG_PPRST2_UT0RST_Pos)
+#define PPRST2_UST11RST          (0x1uL << SCUCG_PPRST2_UST11RST_Pos)
+#define PPRST2_UST10RST          (0x1uL << SCUCG_PPRST2_UST10RST_Pos)
+
+// External Main Oscillator Filter Selection Control
+/*
+#define XTAL_4DOT5MHZ            (0x0 << 0)
+#define XTAL_6DOT5MHZ            (0x1 << 0)
+#define XTAL_8DOT5MHZ            (0x2 << 0)
+#define XTAL_10DOT5MHZ           (0x3 << 0)
+#define XTAL_12DOT5MHZ           (0x4 << 0)
+#define XTAL_16DOT5MHZ           (0x5 << 0)
+*/
+#define XRNS_LE4p5MHz            (SCUCG_XTFLSR_XRNS_LE4p5MHz  << SCUCG_XTFLSR_XRNS_Pos)   //            x-tal LE 4.5MHz
+#define XRNS_LE6p5MHz            (SCUCG_XTFLSR_XRNS_LE6p5MHz  << SCUCG_XTFLSR_XRNS_Pos)   //  4.5MHz GT x-tal LE 6.5MHz
+#define XRNS_LE8p5MHz            (SCUCG_XTFLSR_XRNS_LE8p5MHz  << SCUCG_XTFLSR_XRNS_Pos)   //  6.5MHz GT x-tal LE 8.5MHz
+#define XRNS_LE10p5MHz           (SCUCG_XTFLSR_XRNS_LE10p5MHz << SCUCG_XTFLSR_XRNS_Pos)   //  8.5MHz GT x-tal LE 10.5MHz
+#define XRNS_LE12p5MHz           (SCUCG_XTFLSR_XRNS_LE12p5MHz << SCUCG_XTFLSR_XRNS_Pos)   // 10.5MHz GT x-tal LE 12.5MHz
+#define XRNS_LE16p5MHz           (SCUCG_XTFLSR_XRNS_LE16p5MHz << SCUCG_XTFLSR_XRNS_Pos)   // 12.5MHz GT x-tal LE 16.5MHz
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get "Vendor ID"/"Chip ID"/Revision Number"
+ * @details       This macro gets vendor ID, chip ID, and revision number.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCC_GetVendorID()         (SCUCC->VENDORID)
+#define SCUCC_GetChipID()           (SCUCC->CHIPID)
+#define SCUCC_GetRevNo()            (SCUCC->REVNR)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Boot Pin Function
+ * @param[in]     rst_src
+ *                   Reset sources to check boot pin
+ *                   -  BFIND_PORorEXTR, BFIND_POR
+ * @details       This macro sets boot pin function to check when reset occurs.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCC_SetBtFnc(rst_src)     (SCUCC->BTPSCR_b.BFIND = rst_src)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Boot Pin Status
+ * @details       This macro gets boot pin status.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCC_GetBtPinSt()          (SCUCC->BTPSCR_b.BTPSTA)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable/Disable NMI Interrupt
+ * @details       This macro sets the NMI interrupt control bit.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCC_EnNMI()               (SCUCC->NMISRCR_b.NMICON = 1)
+#define SCUCC_DisNMI()              (SCUCC->NMISRCR_b.NMICON = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Generate Software Reset
+ * @details       This macro generates software reset.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCC_GenSwRst()            (SCUCC->SWRSTR = ((uint32_t)SCUCC_SWRSTR_WTIDKY_Value << SCUCC_SWRSTR_WTIDKY_Pos) | 0x2DuL)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable/Disable Wake-Up Timer Interrupt
+ * @details       This macro sets the wake-up timer interrupt enable bit.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCC_EnWutInt()            (SCUCC->WUTCR_b.WUTIEN = 1)
+#define SCUCC_DisWutInt()           (SCUCC->WUTCR_b.WUTIEN = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get/Clear Wake-Up Timer Interrupt Flag
+ * @details       This macro gets/clears the wake-up timer interrupt flag.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCC_GetWutFlag()          (SCUCC->WUTCR_b.WUTIFLAG)
+#define SCUCC_ClrWutFlag()          (SCUCC->WUTCR_b.WUTIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Reload Counter of Wake-Up Timer
+ * @details       This macro reloads wake-up timer counter to re-count.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCC_ReloadWut()           (SCUCC->WUTCR_b.CNTRLD = 1)
+
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Divider 0/1/2/3
+ * @param[in]     scu_hdiv
+ *                   -  scu_hdiv:      HDIV_MCLK16, HDIV_MCLK8, HDIV_MCLK4, HDIV_MCLK2, HDIV_MCLK1
+ *                   -  scu_pdiv:      PDIV_HCLK1, PDIV_HCLK2, PDIV_HCLK4, PDIV_HCLK8
+ *                   -  scu_wldiv:     WLDIV_MCLK64, WLDIV_MCLK128, WLDIV_MCLK256, WLDIV_MCLK512, WLDIV_MCLK1024
+ *                   -  scu_systdiv:   SYSTDIV_HCLK1, SYSTDIV_HCLK2, SYSTDIV_HCLK4, SYSTDIV_HCLK8
+ * @details       This macro sets dividers.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCG_SetHCLK( scu_hdiv )            (SCUCG->SCDIVR1_b.HDIV = scu_hdiv)
+#define SCUCG_SetPCLK( scu_pdiv )            (SCUCG->SCDIVR2_b.PDIV = scu_pdiv)
+#define SCUCG_SetWtLcd( scu_wldiv )          (SCUCG->SCDIVR1_b.WLDIV = scu_wldiv)
+#define SCUCG_SetSysTick( scu_systdiv )      (SCUCG->SCDIVR2_b.SYSTDIV = scu_systdiv)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Clock Output Control Register (CLKOCR)
+ * @param[in]     u32Clko
+ *                   Values for CLKO frequency, Polarity, and Divider
+ * @details       This macro sets clock output control register for CLKO.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCG_SetClkOutReg( u32Clko )        (SCUCG->CLKOCR = u32Clko)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get MONFLAG of Clock Monitoring
+ * @details       This macro reads MONFLAG of Clock Monitoring.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCG_GetMonFlag()                   (SCUCG->CMONCR_b.MONFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Timer/Counter 20 Clock
+ * @param[in]     clk
+ *                   -  T20CLK_XSOSC, T20CLK_PCLK
+ * @details       This macro sets Timer/Counter 20 clock.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCG_SetT20ClkSrc( clk )            (SCUCG->PPCLKSR_b.T20CLK = clk)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Timer/Counter 30 Clock
+ * @param[in]     clk
+ *                   -  T30CLK_MCLK, T30CLK_PCLK
+ * @details       This macro sets Timer/Counter 30 clock.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCG_SetT30ClkSrc( clk )            (SCUCG->PPCLKSR_b.T30CLK = clk)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set LCD Driver Clock
+ * @param[in]     clk
+ *                   -  LCDCLK_DividedMCLK, LCDCLK_XSOSC, LCDCLK_WDTRC
+ * @details       This macro sets LCD Driver clock.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCG_SetLcdClk( clk )               (SCUCG->PPCLKSR_b.LCDCLK = clk)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Watch Timer Clock
+ * @param[in]     clk
+ *                   -  WTCLK_DividedMCLK, WTCLK_XSOSC, WTCLK_WDTRC
+ * @details       This macro sets Watch Timer clock.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCG_SetWtClk( clk )                (SCUCG->PPCLKSR_b.WTCLK = clk)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Watch-Dog Timer Clock
+ * @param[in]     clk
+ *                   -  WDTCLK_WDTRC, WDTCLK_PCLK
+ * @details       This macro sets Watch-Dog Timer clock.
+ *//*-------------------------------------------------------------------------*/
+#define SCUCG_SetWdtClk( clk )               (SCUCG->PPCLKSR_b.WDTCLK = clk)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+uint32_t HAL_SCU_ResetSourceStatus( void );
+void HAL_SCU_SetNMI( uint32_t u32NmiCon );
+void HAL_SCU_SoftwareReset_Config( void );
+void HAL_SCU_SetWakupData( uint32_t u32Data );
+void HAL_SCU_HIRCTRM_ClockConfig( uint32_t u32Ind );
+void HAL_SCU_WDTRCTRM_ClockConfig( uint32_t u32Ind );
+
+
+void HAL_SCU_ClockMonitoring( uint32_t u32Acts, uint32_t u32Target );
+void HAL_SCU_ClockMonitoring_Disable( void );
+void HAL_SCU_ClockSource_Config( uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc );
+void HAL_SCU_ClockSource_Enable( uint32_t u32ClkSrc, uint32_t u32HircDiv );
+void HAL_SCU_ClockSource_Disable( uint32_t u32ClkSrc );
+void HAL_SCU_SystemClockChange( uint32_t u32Target );
+void HAL_SCU_MainXtal_PinConfig( uint32_t u32XtalFilter );
+void HAL_SCU_SubXtal_PinConfig( void );
+void HAL_SCU_SystemClockDivider( uint32_t u32Div02, uint32_t u32Div13 );
+void HAL_SCU_CLKO_PinConfig( void );
+void HAL_SCU_ClockOutput( uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div );
+void HAL_SCU_Peripheral_ClockConfig( uint32_t u32PeriClk1, uint32_t u32PeriClk2 );
+void HAL_SCU_Peripheral_EnableClock1( uint32_t u32PeriClk1, uint32_t Ind );
+void HAL_SCU_Peripheral_EnableClock2( uint32_t u32PeriClk2, uint32_t u32Ind );
+void HAL_SCU_Peripheral_ResetConfig( uint32_t u32PeriRst1, uint32_t u32PeriRst2 );
+void HAL_SCU_Peripheral_SetReset1( uint32_t u32EachPeri1 );
+void HAL_SCU_Peripheral_SetReset2( uint32_t u32EachPeri2 );
+void HAL_SCU_Peripheral_ClockSelection( uint32_t u32Peri, uint32_t u32ClkSrc );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _SCU_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_sculv.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_sculv.h
new file mode 100644
index 0000000..5c38380
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_sculv.h
@@ -0,0 +1,130 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_sculv.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for sculv firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _SCULV_H_
+#define _SCULV_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+// LVI Enable/Disable Control
+/*
+#define LVI_DIS                  (0x00uL << 7)
+#define LVI_EN                   (0x01uL << 7)
+*/
+#define LVIEN_Disable            (SCULV_LVICR_LVIEN_Disable << SCULV_LVICR_LVIEN_Pos)
+#define LVIEN_Enable             (SCULV_LVICR_LVIEN_Enable  << SCULV_LVICR_LVIEN_Pos)
+
+// LVI Interrupt Enable/Disable Control
+/*
+#define LVI_INT_DIS              (0x00uL << 5)
+#define LVI_INT_EN               (0x01uL << 5)
+*/
+#define LVINTEN_Disable          (SCULV_LVICR_LVINTEN_Disable << SCULV_LVICR_LVINTEN_Pos)
+#define LVINTEN_Enable           (SCULV_LVICR_LVINTEN_Enable  << SCULV_LVICR_LVINTEN_Pos)
+
+// LVI Voltage Selection Control
+/*
+#define LV_1DOT88                (0x03uL)
+#define LV_2DOT00                (0x04uL)
+#define LV_2DOT13                (0x05uL)
+#define LV_2DOT28                (0x06uL)
+#define LV_2DOT46                (0x07uL)
+#define LV_2DOT67                (0x08uL)
+#define LV_3DOT04                (0x09uL)
+#define LV_3DOT20                (0x0AuL)
+#define LV_3DOT55                (0x0BuL)
+#define LV_3DOT75                (0x0CuL)
+#define LV_3DOT99                (0x0DuL)
+#define LV_4DOT25                (0x0EuL)
+#define LV_4DOT55                (0x0FuL)
+*/
+#define LVIVS_2p00V              (SCULV_LVICR_LVIVS_2p00V << SCULV_LVICR_LVIVS_Pos)    // 2.00V                                                              */
+#define LVIVS_2p13V              (SCULV_LVICR_LVIVS_2p13V << SCULV_LVICR_LVIVS_Pos)    // 2.13V                                                              */
+#define LVIVS_2p28V              (SCULV_LVICR_LVIVS_2p28V << SCULV_LVICR_LVIVS_Pos)    // 2.28V                                                              */
+#define LVIVS_2p46V              (SCULV_LVICR_LVIVS_2p46V << SCULV_LVICR_LVIVS_Pos)    // 2.46V                                                              */
+#define LVIVS_2p67V              (SCULV_LVICR_LVIVS_2p67V << SCULV_LVICR_LVIVS_Pos)    // 2.67V                                                              */
+#define LVIVS_3p04V              (SCULV_LVICR_LVIVS_3p04V << SCULV_LVICR_LVIVS_Pos)    // 3.04V                                                              */
+#define LVIVS_3p20V              (SCULV_LVICR_LVIVS_3p20V << SCULV_LVICR_LVIVS_Pos)    // 3.20V                                                              */
+#define LVIVS_3p55V              (SCULV_LVICR_LVIVS_3p55V << SCULV_LVICR_LVIVS_Pos)    // 3.55V                                                              */
+#define LVIVS_3p75V              (SCULV_LVICR_LVIVS_3p75V << SCULV_LVICR_LVIVS_Pos)    // 3.75V                                                              */
+#define LVIVS_3p99V              (SCULV_LVICR_LVIVS_3p99V << SCULV_LVICR_LVIVS_Pos)    // 3.99V                                                              */
+#define LVIVS_4p25V              (SCULV_LVICR_LVIVS_4p25V << SCULV_LVICR_LVIVS_Pos)    // 4.25V                                                              */
+#define LVIVS_4p55V              (SCULV_LVICR_LVIVS_4p55V << SCULV_LVICR_LVIVS_Pos)    // 4.55V                                                              */
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable/Disable LVR
+ * @details       This macro disables/enables LVR. If any value is written, the LVR register won't be changed until to POR.
+ *//*-------------------------------------------------------------------------*/
+#define SCULV_DisLVR()           (SCULV->LVRCR_b.LVREN = 0x55)
+#define SCULV_EnLVR()            (SCULV->LVRCR_b.LVREN = 0x8A)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable/Disable LVI Interrupt
+ * @details       This macro sets the LVI interrupt enable bit.
+ *//*-------------------------------------------------------------------------*/
+#define SCULV_EnLviInt()         (SCULV->LVICR_b.LVINTEN = 1)
+#define SCULV_DisLviInt()        (SCULV->LVICR_b.LVINTEN = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get/Clear LVI Interrupt Flag
+ * @details       This macro gets/clears the LVI interrupt flag.
+ *//*-------------------------------------------------------------------------*/
+#define SCULV_GetLviFlag()       (SCULV->LVICR_b.LVIFLAG)
+#define SCULV_ClrLviFlag()       (SCULV->LVICR_b.LVIFLAG = 1)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+void HAL_LVI_Init( uint32_t u32LviEnBit, uint32_t u32LviIntEnBit, uint32_t u32LviLevel );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _SCULV_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer1n.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer1n.h
new file mode 100644
index 0000000..8d9cb0e
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer1n.h
@@ -0,0 +1,308 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_timer1n.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for timer1n firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _TIMER1n_H_
+#define _TIMER1n_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+//----------   TIMER1n Enable/Disable Definition   ----------
+#define TIMER1n_DISABLE          (0x0uL << 15)
+#define TIMER1n_ENABLE           (0x1uL << 15)
+
+//----------   TIMER1n Clock Selection Definition   ----------
+#define TIMER1n_CLKINT           (0x0uL << 14)
+#define TIMER1n_CLKEXT           (0x1uL << 14)
+
+//----------   TIMER1n Mode Selection Definition   ----------
+#define TIMER1n_CNTM             (0x0uL << 12)
+#define TIMER1n_CAPM             (0x1uL << 12)
+#define TIMER1n_PPGONEM          (0x2uL << 12)
+#define TIMER1n_PPGREM           (0x3uL << 12)
+
+//----------   TIMER1n External Clock Edge Selection Definition   ----------
+#define TIMER1n_FEDGE            (0x0uL << 11)
+#define TIMER1n_REDGE            (0x1uL << 11)
+
+//----------   TIMER1n OUT Polarity Selection Definition   ----------
+#define TIMER1n_STHIGH           (0x0uL << 8)
+#define TIMER1n_STLOW            (0x1uL << 8)
+
+//----------   TIMER1n Capture Polarity Selection Definition   ----------
+#define TIMER1n_CAPFALL          (0x0uL << 6)
+#define TIMER1n_CAPRISE          (0x1uL << 6)
+#define TIMER1n_CAPBOTH          (0x2uL << 6)
+
+//----------   TIMER1n Match Interrupt Definition   ----------
+#define TIMER1n_MATINTEN         (0x1uL << 5)
+#define TIMER1n_MATINTDIS        (0x0uL << 5)
+
+//----------   TIMER1n Capture Interrupt Definition   ----------
+#define TIMER1n_CAPINTEN         (0x1uL << 4)
+#define TIMER1n_CAPINTDIS        (0x0uL << 4)
+
+#define TIMER1n_PRS_MASK         0x0FFF
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+/**   counter clock source select */
+typedef enum
+{
+   TIMER1n_PCLK = 0,             /**<  clock source from pclk */
+   TIMER1n_ECn = 1               /**<  clock source from ECn pin input. before setting, have to set ECn pin mode */
+} TIMER1n_CKSEL_MODE_OPT;
+
+typedef enum
+{
+   TIMER1n_PERIODIC_MODE = 0,    /**<  PERIODIC mode */
+   TIMER1n_CAPTURE_MODE,         /**<  CAPTURE mode */
+   TIMER1n_ONESHOT_MODE,         /**<  ONE SHOT mode */
+   TIMER1n_PWM_MODE              /**<  PWM mode */
+} TIMER1n_MODE_OPT;
+
+typedef enum
+{
+   TIMER1n_FALLING_EGDE = 0,     /**<  falling edge clear mode */
+   TIMER1n_RISING_EGDE,          /**<  rising edge clear mode */
+   TIMER1n_BOTH_EGDE,            /**<  both edge clear  mode */
+   TIMER1n_NONE                  /**<  none clear mode */
+} TIMER1n_CLR_MODE_OPT;
+
+/**   start default level select: initial output value. */
+typedef enum
+{
+   TIMER1n_START_HIGH = 0,
+   TIMER1n_START_LOW
+} TIMER1n_STARTLVL_OPT;
+
+/**   TIMER Interrupt Type definitions */
+typedef enum
+{
+   TIMER1n_INTCFG_MIE = 0,    /**<  Match Interrupt enable*/
+   TIMER1n_INTCFG_CIE,        /**<  Capture Interrupt enable*/
+} TIMER1n_INT_Type;
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+/**   Configuration structure in TIMER mode */
+typedef struct
+{
+   uint16_t    ADR;
+   uint16_t    BDR;
+   uint16_t    Prescaler;
+   uint8_t     StartLevel;    /**<  set initial output value
+                                    -  TIMER1n_START_LOW, TIMER1n_START_HIGH
+                              */
+   uint8_t     CkSel;         /**<  Counter clock source select
+                                    -  PCLK, ECn
+                              */
+   uint8_t     ECE;
+} TIMER1n_PERIODICCFG_Type;
+
+/**   Configuration structure in COUNTER mode */
+typedef struct
+{
+   uint16_t    ADR;
+   uint16_t    BDR;
+   uint16_t    Prescaler;
+   uint8_t     StartLevel;    /**<  set initial output value
+                                    -  TIMER1n_START_LOW, TIMER1n_START_HIGH
+                              */
+   uint8_t     CkSel;         /**<  Counter clock source select
+                                    -  PCLK, ECn
+                              */
+   uint8_t     ECE;
+} TIMER1n_PWMCFG_Type, TIMER1n_ONESHOTCFG_Type;
+
+/**   Capture Input configuration structure */
+typedef struct
+{
+   uint16_t    ADR;
+   uint16_t    Prescaler;
+   uint8_t     ClrMode;
+   uint8_t     CkSel;
+   uint8_t     ECE;
+} TIMER1n_CAPTURECFG_Type;
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER1n Enable/Disable
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro Enable TIMER1n Block
+ *//*-------------------------------------------------------------------------*/
+#define TIMER1n_EN( TIMER1x )        (TIMER1x->CR_b.T1nEN = 1)
+#define TIMER1n_DIS( TIMER1x )       (TIMER1x->CR_b.T1nEN = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER1n Continue Counting/Temporary Pause
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro select TIMER1n Continue Counting/Temporary Pause
+ *//*-------------------------------------------------------------------------*/
+#define TIMER1n_ConCnt( TIMER1x )       (TIMER1x->CR_b.T1nPAU = 0)
+#define TIMER1n_TempPau( TIMER1x )      (TIMER1x->CR_b.T1nPAU = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER1n Counter and Prescaler clear
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro clears Counter and Prescalrer of TIMER1n
+ *//*-------------------------------------------------------------------------*/
+#define TIMER1n_ClrCnt( TIMER1x )       (TIMER1x->CR_b.T1nCLR = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get TIMER1n Counter Register
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro gets TIMER1n Counter Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER1n_GetCnt( TIMER1x )       (TIMER1x->CNT)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER1n A Data Register
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @param[in]     u32AData
+ *                   A Data of TIMER1n
+ * @details       This macro sets TIMER1n A Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER1n_SetAData( TIMER1x, u32AData )    (TIMER1x->ADR = u32AData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER1n B Data Register
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @param[in]     u32BData
+ *                   B Data of TIMER1n
+ * @details       This macro sets TIMER1n B Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER1n_SetBData( TIMER1x, u32BData )    (TIMER1x->BDR = u32BData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get TIMER1n Capture Data Register
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro gets TIMER1n Capture Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER1n_GetCapData( TIMER1x )      (TIMER1x->CAPDR)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER1n Match Interrupt
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro gets interrupt flag of TIMER1n Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define T1nMaInt_GetFg( TIMER1x )          (TIMER1x->CR_b.T1nMIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER1n Match Interrupt
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro clears interrupt flag of TIMER1n Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define T1nMaInt_ClrFg( TIMER1x )          (TIMER1x->CR_b.T1nMIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER1n Capture Interrupt
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro gets interrupt flag of TIMER1n Capture Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define T1nCapInt_GetFg( TIMER1x )         (TIMER1x->CR_b.T1nCIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER1n Capture Interrupt
+ * @param[in]     TIMER1x
+ *                   -  TIMER10 ~ TIMER16
+ * @details       This macro clears interrupt flag of TIMER1n Capture Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define T1nCapInt_ClrFg( TIMER1x )         (TIMER1x->CR_b.T1nCIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Timer device enumeration
+ *//*-------------------------------------------------------------------------*/
+/* Timer n Control register  */
+#define TIMER1n_CR_CKSEL_MASK          (TIMER1n_CR_T1nCLK_Msk)
+#define TIMER1n_CR_CKSEL_SET( n )      (n << TIMER1n_CR_T1nCLK_Pos)
+
+#define TIMER1n_CR_MODE_MASK           (TIMER1n_CR_T1nMS_Msk)
+#define TIMER1n_CR_MODE_SET( n )       (n << TIMER1n_CR_T1nMS_Pos)
+
+#define TIMER1n_CR_ECE_MASK            (TIMER1n_CR_T1nECE_Msk)
+#define TIMER1n_CR_ECE_SET( n )        (n << TIMER1n_CR_T1nECE_Pos)
+
+#define TIMER1n_CR_STARTLVL_MASK       (TIMER1n_CR_T1nOPOL_Msk)
+#define TIMER1n_CR_STARTLVL_SET( n )   (n << TIMER1n_CR_T1nOPOL_Pos)
+
+#define TIMER1n_CR_CPOL_MASK           (TIMER1n_CR_T1nCPOL_Msk)
+#define TIMER1n_CR_CPOL_SET( n )       (n << TIMER1n_CR_T1nCPOL_Pos)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_TIMER1n_Init( TIMER1n_Type* TIMER1x, TIMER1n_MODE_OPT TimerCounterMode, void* TIMER1n_Config );
+HAL_Status_Type HAL_TIMER1n_DeInit( TIMER1n_Type* TIMER1x );
+
+HAL_Status_Type HAL_TIMER1n_ConfigInterrupt( TIMER1n_Type* TIMER1x, TIMER1n_INT_Type TIMER1n_IntCfg, FunctionalState NewState );
+HAL_Status_Type HAL_TIMER1n_Cmd( TIMER1n_Type* TIMER1x, FunctionalState NewState );
+HAL_Status_Type HAL_TIMER1n_SetRegister( TIMER1n_Type* TIMER1x, uint32_t u32T1nSet, uint32_t u32T1nClk );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _TIMER1n_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer2n.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer2n.h
new file mode 100644
index 0000000..402b6f7
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer2n.h
@@ -0,0 +1,352 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_timer2n.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for timer2n firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _TIMER2n_H_
+#define _TIMER2n_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+//--------------------------------------
+// TIMER2n Control Register definitions
+//--------------------------------------
+
+/**   Counter/timer mode bits */
+#define TIMER2n_CR_MODE_MASK        (0x3)
+
+/**   counter clock select bits */
+#define TIMER2n_CR_CLK_MASK         (TIMER2n_CR_T2nCLK_Msk)
+
+/**   External Clock Edge Selection bit */
+#define TIMER2n_CR_ECE_MASK         (TIMER2n_CR_T2nECE_Msk)
+
+/**   T2nCAP signal selection bit */
+#define TIMER2n_CR_CAPSEL_MASK      (0x03 << 9)
+
+/**   T2nOUT Polarity Selection bit */
+#define TIMER2n_CR_OPOL_MASK        (TIMER2n_CR_T2nOPOL_Msk)
+
+/**   TIMER2n Capture Polarity Selection bit */
+#define TIMER2n_CR_CPOL_MASK        (TIMER2n_CR_T2nCPOL_Msk)
+
+/**   TIMER2n Match Interrupt Enable bit */
+#define TIMER2n_CR_MIEN_MASK        (TIMER2n_CR_T2nMIEN_Msk)
+
+/**   TIMER2n Capture Interrupt Enable bit */
+#define TIMER2n_CR_CIEN_MASK        (TIMER2n_CR_T2nCIEN_Msk)
+
+/**   TIMER2n Counter Temporary Pause Control bit */
+#define TIMER2n_CR_PAU_MASK         (TIMER2n_CR_T2nPAU_Msk)
+
+/**   TIMER2n Match Interrupt Flag */
+#define TIMER2n_CR_MATCH_FLAG       (1 << 3)
+#define TIMER2n_CR_CAPTURE_FLAG     (1 << 2)
+
+/**   Clear Flag */
+#define TIMER2n_CR_CLEAR_MATCHINT      (0x01 << TIMER2n_CR_T2nMIFLAG_Pos)
+#define TIMER2n_CR_CLEAR_CAPTUREINT    (0x01 << TIMER2n_CR_T2nCIFLAG_Pos)
+#define TIMER2n_CR_CLEAR_CNT_PRED      (0x01 << TIMER2n_CR_T2nCLR_Pos)
+
+/**   TIMER2n A Data Register (ADR) */
+#define TIMER2n_ADR_MASK         0xFFFFFFFF
+
+/**   TIMER2n B Data Register (BDR) */
+#define TIMER2n_BDR_MASK         0xFFFFFFFF
+
+/**   TIMER2n Prescaler Data Register (PREDR) */
+#define TIMER2n_PREDR_MASK       (0xFFF << 0)
+
+/**   Timer/counter enable bit */
+#define TIMER2n_ENABLE           (1)
+#define TIMER2n_DISABLE          (0)
+
+/**   Timer/counter reset bit */
+#define TIMER2n_CLEAR            (1)
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+/**   Timer operating mode */
+typedef enum
+{
+   TIMER2n_PERIODIC_MODE = 0,    /**<  PERIODIC mode */
+   TIMER2n_CAPTURE_MODE,         /**<  PWM mode */
+   TIMER2n_ONESHOT_MODE,         /**<  ONE SHOT mode */
+   TIMER2n_PWM_MODE              /**<  CAPTURE mode */
+} TIMER2n_MODE_OPT;
+
+/**   clear select when capture mode */
+typedef enum
+{
+   TIMER2n_FALLING_EGDE = 0,     /**<  rising edge clear mode */
+   TIMER2n_RISING_EGDE,          /**<  falling edge clear mode */
+   TIMER2n_BOTH_EGDE,            /**<  both edge clear  mode */
+   TIMER2n_NONE                  /**<  none clear mode */
+} TIMER2n_CLR_MODE_OPT;
+
+/**   Timer clock source select */
+typedef enum
+{
+   TIMER2n_XSOSC_CLK = 0,        /**<  clock source from Internal */
+   TIMER2n_PCLK_CLK,             /**<  clock source from External */
+} TIMER2n_MASTER_CKSEL_OPT;
+
+/**   counter clock source select */
+typedef enum
+{
+   TIMER2n_INTERNAL_CLK = 0,     /**<  clock source from Internal */
+   TIMER2n_EXTERNAL_CLK,         /**<  clock source from External */
+} TIMER2n_CKSEL_MODE_OPT;
+
+/**   capture clock source select */
+typedef enum
+{
+   TIMER2n_CAP_EXTERNAL_CLK = 0,    /**<  clock source from Externl */
+   TIMER2n_CAP_XSOSC_CLK,           /**<  clock source from XSOSC */
+   TIMER2n_CAP_WDTRC_CLK,           /**<  Clock Source from WDTRC */
+} TIMER2n_CAP_CKSEL_OPT;
+
+/**   start default level select: initial output value. */
+typedef enum
+{
+   TIMER2n_START_HIGH = 0,    /**<  clock source from pclk div 2 */
+   TIMER2n_START_LOW          /**<  clock source from pclk div 4 */
+} TIMER2n_STARTLVL_OPT;
+
+/**   TIMER Interrupt Type definitions */
+typedef enum
+{
+   TIMER2n_CR_MATCH_INTR = 0,    /**<  OVIE Interrupt enable*/
+   TIMER2n_CR_CAPTURE_INTR,      /**<  MBIE Interrupt enable*/
+} TIMER2n_INT_Type;
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+/**   Configuration structure in TIMER mode */
+typedef struct
+{
+   uint32_t    ADR;
+   uint32_t    BDR;
+   uint8_t     TCLK_SEL;         /**<  Timer Clock Source, should be:
+                                       -  XSOSC
+                                       -  PCLK
+                                 */
+   uint16_t    Prescaler;        /**<  Timer Prescaler(TnPRS), should be:
+                                       -  0~4095  value range
+                                 */
+   uint8_t     CkSel;            /**<  Counter clock source select, should be:
+                                       -  Internal
+                                       -  EXT : EXT,  clock source
+                                 */
+   uint8_t     ExtCkEdge;        /**<  Set External Clock Edge Selection bit:
+                                       -  Falling Edge
+                                       -  Rising Edge
+                                 */
+   uint8_t     StartLevel;       /**<  set initial output value, should be:
+                                       -  TIMER2n_START_LOW
+                                       -  TIMER2n_START_HIGH
+                                 */
+   uint8_t     CapEdge;          /**<  Set Capture Edge, should be:
+                                       -  Falling Edge
+                                       -  Rising Edge
+                                       -  Both Edge
+                                 */
+} TIMER2n_PERIODICCFG_Type;
+
+/**   Configuration structure in COUNTER mode */
+typedef struct
+{
+   uint32_t    ADR;
+   uint32_t    BDR;
+   uint8_t     TCLK_SEL;         /**<  Timer Clock Source, should be:
+                                       -  XSOSC
+                                       -  PCLK
+                                 */
+   uint16_t    Prescaler;        /**<  Timer Prescaler(TnPRS), should be:
+                                       -  0~4095  value range
+                                 */
+   uint8_t     CkSel;            /**<  Counter clock source select, should be:
+                                       -  Internal
+                                       -  EXT : EXT,  clock source
+                                 */
+   uint8_t     ExtCkEdge;        /**<  Set External Clock Edge Selection bit:
+                                       -  Falling Edge
+                                       -  Rising Edge
+                                 */
+   uint8_t     StartLevel;       /**<  set initial output value, should be:
+                                       -  TIMER2n_START_LOW
+                                       -  TIMER2n_START_HIGH
+                                 */
+   uint8_t     CapEdge;          /**<  Set Capture Edge, should be:
+                                       -  Falling Edge
+                                       -  Rising Edge
+                                       -  Both Edge
+                                 */
+} TIMER2n_PWMCFG_Type, TIMER2n_ONESHOTCFG_Type;
+
+/**   Capture Input configuration structure */
+typedef struct
+{
+   uint8_t     TCLK_SEL;         /**<  Timer Clock Source, should be:
+                                       -  XSOSC
+                                       -  PCLK
+                                 */
+   uint16_t    Prescaler;        /**<  Timer Prescaler(TnPRS), should be:
+                                       -  0~4095  value range
+                                 */
+   uint8_t     ClrMode;          /**<  clear select when capture, should be:
+                                       -  TIMER2n_RISING_EGDE
+                                       -  TIMER2n_FALLING_EGDE
+                                       -  TIMER2n_BOTH_EGDE
+                                       -  TIMER2n_NONE
+                                 */
+   uint8_t     CkSel;            /**<  Counter clock source select, should be:
+                                       -  PCLK_2:     PCLK / 2
+                                       -  PCLK_4:     PCLK / 4
+                                       -  PCLK_16:    PCLK / 16
+                                       -  PCLK_64:    PCLK / 64
+                                       -  EXT = 4:    EXT, clock source from MCCR3(TEXT) clock
+                                       -  TnC
+                                 */
+   uint8_t     CAPCkSel;         /**<  Capture clock source select, should be:
+                                       -  External Capture Signal
+                                       -  XSOSC
+                                       -  WDTRC
+                                 */
+   uint8_t     Reserved[2];      /**<  Reserved */
+} TIMER2n_CAPTURECFG_Type;
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER2n Counter and Prescaler clear
+ * @param[in]     TIMER2x
+ *                   -  TIMER20 ~ TIMER21
+ * @details       This macro clears Counter and Prescalrer of TIMER2n
+ *//*-------------------------------------------------------------------------*/
+#define TIMER2n_ClrCnt( TIMER2x )       (TIMER2x->CR_b.T2nCLR = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get TIMER2n Counter Register
+ * @param[in]     TIMER2x
+ *                   -  TIMER20 ~ TIMER21
+ * @details       This macro gets TIMER2n Counter Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER2n_GetCnt( TIMER2x )       (TIMER2x->CNT)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER2n A Data Register
+ * @param[in]     TIMER2x
+ *                   -  TIMER20 ~ TIMER21
+ * @param[in]     u32AData
+ *                   A Data of TIMER2n
+ * @details       This macro sets TIMER2n A Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER2n_SetAData( TIMER2x, u32AData )    (TIMER2x->ADR = u32AData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER2n B Data Register
+ * @param[in]     TIMER2x
+ *                   -  TIMER20 ~ TIMER21
+ * @param[in]     u32BData
+ *                   B Data of TIMER2n
+ * @details       This macro sets TIMER2n B Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER2n_SetBData( TIMER2x, u32BData )    (TIMER2x->BDR = u32BData)
+
+/**   counter clock select bits */
+#define TIMER2n_CR_CLK_SET( n )        (n << TIMER2n_CR_T2nCLK_Pos)
+
+/**   External Clock Edge Selection bit */
+#define TIMER2n_CR_ECE_SET( n )        (n << TIMER2n_CR_T2nECE_Pos)
+
+/**   T2nCAP signal selection bit */
+#define TIMER2n_CR_CAPSEL_SET( n )     (n << 9)
+
+/**   T2nOUT Polarity Selection bit */
+#define TIMER2n_CR_OPOL_SET( n )       (n << TIMER2n_CR_T2nOPOL_Pos)
+
+/**   TIMER2n Capture Polarity Selection bit */
+#define TIMER2n_CR_CPOL_SET( n )       (n << TIMER2n_CR_T2nCPOL_Pos)
+
+/**   TIMER2n Match Interrupt Enable bit */
+#define TIMER2n_CR_MIEN_SET( n )       (n << TIMER2n_CR_T2nMIEN_Pos)
+
+/**   TIMER2n Capture Interrupt Enable bit */
+#define TIMER2n_CR_CIEN_SET( n )       (n << TIMER2n_CR_T2nCIEN_Pos)
+
+/**   TIMER2n Counter Temporary Pause Control bit */
+#define TIMER2n_CR_PAU_SET( n )        (n << TIMER2n_CR_T2nPAU_Pos)
+
+#define TIMER2n_PREDR_SET( n )         (n << 0)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_TIMER2n_Init( TIMER2n_Type* TIMER2x, TIMER2n_MODE_OPT TimerCounterMode, void* TIMER2n_Config );
+HAL_Status_Type HAL_TIMER2n_DeInit( TIMER2n_Type* TIMER2x );
+
+HAL_Status_Type HAL_TIMER2n_ConfigInterrupt( TIMER2n_Type* TIMER2x, TIMER2n_INT_Type TIMER2n_IntCfg, FunctionalState NewState );
+HAL_Status_Type HAL_TIMER2n_Cmd( TIMER2n_Type* TIMER2x, FunctionalState NewState );
+HAL_Status_Type HAL_TIMER2n_ClearCounter( TIMER2n_Type* TIMER2x );
+HAL_Status_Type HAL_TIMER2n_UpdateCountValue( TIMER2n_Type* TIMER2x, uint8_t CountCh, uint16_t Value );
+HAL_Status_Type HAL_TIMER2n_ClearStatus( TIMER2n_Type* TIMER2x, uint8_t value );
+uint8_t HAL_TIMER2n_GetStatus( TIMER2n_Type* TIMER2x );
+
+uint32_t HAL_TIMER2n_GetCaptureData( TIMER2n_Type* TIMER2x );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _TIMER2n_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer3n.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer3n.h
new file mode 100644
index 0000000..3a4da8b
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_timer3n.h
@@ -0,0 +1,490 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_timer3n.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for timer3n firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _TIMER3n_H_
+#define _TIMER3n_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+//==========   TIMER3n_CR   ========================================
+
+//----------   TIMER3n Enable/Disable Definition   ----------
+#define TIMER3n_DISABLE       (0x0uL << TIMER3n_CR_T3nEN_Pos)
+#define TIMER3n_ENABLE        (0x1uL << TIMER3n_CR_T3nEN_Pos)
+
+//----------   TIMER3n Clock Selection Definition   ----------
+#define TIMER3n_CLKINT        (0x0uL << TIMER3n_CR_T3nCLK_Pos)
+#define TIMER3n_CLKEXT        (0x1uL << TIMER3n_CR_T3nCLK_Pos)
+
+//----------   TIMER3n Mode Selection Definition   ----------
+#define TIMER3n_INVM          (0x0uL << TIMER3n_CR_T3nMS_Pos)
+#define TIMER3n_CAPM          (0x1uL << TIMER3n_CR_T3nMS_Pos)
+#define TIMER3n_BTOB          (0x2uL << TIMER3n_CR_T3nMS_Pos)
+
+//----------   TIMER3n External Clock Edge Selection Definition   ----------
+#define TIMER3n_FEDGE         (0x0uL << TIMER3n_CR_T3nECE_Pos)
+#define TIMER3n_REDGE         (0x1uL << TIMER3n_CR_T3nECE_Pos)
+
+//----------   TIMER3n Output Mode Selection Definition   ----------
+#define TIMER3n_6CHMOD        (0x0uL << TIMER3n_CR_FORCA_Pos)
+#define TIMER3n_FORAMOD       (0x1uL << TIMER3n_CR_FORCA_Pos)
+
+//----------   TIMER3n Delay Time Insert En/Disable Definition   ----------
+#define TIMER3n_DLYINSDIS     (0x0uL << TIMER3n_CR_DLYEN_Pos)
+#define TIMER3n_DLYINSEN      (0x1uL << TIMER3n_CR_DLYEN_Pos)
+
+//----------   TIMER3n Delay Timer Insertion Position Definition   ----------
+#define TIMER3n_INSFRONT      (0x0uL << TIMER3n_CR_DLYPOS_Pos)
+#define TIMER3n_INSBACK       (0x1uL << TIMER3n_CR_DLYPOS_Pos)
+
+//----------   TIMER3n Capture Polarity Selection Definition   ----------
+#define TIMER3n_CAPFALL       (0x0uL << TIMER3n_CR_T3nCPOL_Pos)
+#define TIMER3n_CAPRISE       (0x1uL << TIMER3n_CR_T3nCPOL_Pos)
+#define TIMER3n_CAPBOTH       (0x2uL << TIMER3n_CR_T3nCPOL_Pos)
+
+//----------   TIMER3n Data Reload Time Selection Definition   ----------
+#define TIMER3n_UPWRITE       (0x0uL << TIMER3n_CR_UPDT_Pos)
+#define TIMER3n_UPMATCH       (0x1uL << TIMER3n_CR_UPDT_Pos)
+#define TIMER3n_UPBOTTOM      (0x2uL << TIMER3n_CR_UPDT_Pos)
+
+//----------   TIMER3n Period Match Interrupt Occurrence Selection Definition   ----------
+#define TIMER3n_E1PERIOD      (0x00uL << TIMER3n_CR_PMOC_Pos)
+#define TIMER3n_E2PERIOD      (0x01uL << TIMER3n_CR_PMOC_Pos)
+#define TIMER3n_E3PERIOD      (0x02uL << TIMER3n_CR_PMOC_Pos)
+#define TIMER3n_E4PERIOD      (0x03uL << TIMER3n_CR_PMOC_Pos)
+#define TIMER3n_E5PERIOD      (0x04uL << TIMER3n_CR_PMOC_Pos)
+#define TIMER3n_E6PERIOD      (0x05uL << TIMER3n_CR_PMOC_Pos)
+#define TIMER3n_E7PERIOD      (0x06uL << TIMER3n_CR_PMOC_Pos)
+#define TIMER3n_E8PERIOD      (0x07uL << TIMER3n_CR_PMOC_Pos)
+
+//==========   TIMER3n_OUTCR   ========================================
+
+//----------   TIMER3n PWM30xB Output Polarity Selection Definition   ----------
+#define TIMER3n_OUT_BPOLOW       (0x0uL << TIMER3n_OUTCR_POLB_Pos)
+#define TIMER3n_OUT_BPOHIGH      (0x1uL << TIMER3n_OUTCR_POLB_Pos)
+
+//----------   TIMER3n PWM30xA Output Polarity Selection Definition   ----------
+#define TIMER3n_OUT_APOLOW       (0x0uL << TIMER3n_OUTCR_POLA_Pos)
+#define TIMER3n_OUT_APOHIGH      (0x1uL << TIMER3n_OUTCR_POLA_Pos)
+
+//----------   TIMER3n PWM30AB Output En/Disable Definition   ----------
+#define TIMER3n_OUT_PWMABDIS     (0x0uL << TIMER3n_OUTCR_PABOE_Pos)
+#define TIMER3n_OUT_PWMABEN      (0x1uL << TIMER3n_OUTCR_PABOE_Pos)
+
+//----------   TIMER3n PWM30BB Output En/Disable Definition   ----------
+#define TIMER3n_OUT_PWMBBDIS     (0x0uL << TIMER3n_OUTCR_PBBOE_Pos)
+#define TIMER3n_OUT_PWMBBEN      (0x1uL << TIMER3n_OUTCR_PBBOE_Pos)
+
+//----------   TIMER3n PWM30CB Output En/Disable Definition   ----------
+#define TIMER3n_OUT_PWMCBDIS     (0x0uL << TIMER3n_OUTCR_PCBOE_Pos)
+#define TIMER3n_OUT_PWMCBEN      (0x1uL << TIMER3n_OUTCR_PCBOE_Pos)
+
+//----------   TIMER3n PWM30AA Output En/Disable Definition   ----------
+#define TIMER3n_OUT_PWMAADIS     (0x0uL << TIMER3n_OUTCR_PAAOE_Pos)
+#define TIMER3n_OUT_PWMAAEN      (0x1uL << TIMER3n_OUTCR_PAAOE_Pos)
+
+//----------   TIMER3n PWM30BA Output En/Disable Definition   ----------
+#define TIMER3n_OUT_PWMBADIS     (0x0uL << TIMER3n_OUTCR_PBAOE_Pos)
+#define TIMER3n_OUT_PWMBAEN      (0x1uL << TIMER3n_OUTCR_PBAOE_Pos)
+
+//----------   TIMER3n PWM30CA Output En/Disable Definition   ----------
+#define TIMER3n_OUT_PWMCADIS     (0x0uL << TIMER3n_OUTCR_PCAOE_Pos)
+#define TIMER3n_OUT_PWMCAEN      (0x1uL << TIMER3n_OUTCR_PCAOE_Pos)
+
+//----------   TIMER3n PWM30AB Output When Disable   ----------
+#define TIMER3n_OUT_ABLOW        (0x0uL << TIMER3n_OUTCR_LVLAB_Pos)
+#define TIMER3n_OUT_ABHIGH       (0x1uL << TIMER3n_OUTCR_LVLAB_Pos)
+
+//----------   TIMER3n PWM30BB Output When Disable   ----------
+#define TIMER3n_OUT_BBLOW        (0x0uL << TIMER3n_OUTCR_LVLBB_Pos)
+#define TIMER3n_OUT_BBHIGH       (0x1uL << TIMER3n_OUTCR_LVLBB_Pos)
+
+//----------   TIMER3n PWM30CB Output When Disable   ----------
+#define TIMER3n_OUT_CBLOW        (0x0uL << TIMER3n_OUTCR_LVLCB_Pos)
+#define TIMER3n_OUT_CBHIGH       (0x1uL << TIMER3n_OUTCR_LVLCB_Pos)
+
+//----------   TIMER3n PWM30AA Output When Disable   ----------
+#define TIMER3n_OUT_AALOW        (0x0uL << TIMER3n_OUTCR_LVLAA_Pos)
+#define TIMER3n_OUT_AAHIGH       (0x1uL << TIMER3n_OUTCR_LVLAA_Pos)
+
+//----------   TIMER3n PWM30BA Output When Disable   ----------
+#define TIMER3n_OUT_BALOW        (0x0uL << TIMER3n_OUTCR_LVLBA_Pos)
+#define TIMER3n_OUT_BAHIGH       (0x1uL << TIMER3n_OUTCR_LVLBA_Pos)
+
+//----------   TIMER3n PWM30CA Output When Disable   ----------
+#define TIMER3n_OUT_CALOW        (0x0uL << TIMER3n_OUTCR_LVLCA_Pos)
+#define TIMER3n_OUT_CAHIGH       (0x1uL << TIMER3n_OUTCR_LVLCA_Pos)
+
+//==========   TIMER3n_INTCR   ========================================
+
+//----------   TIMER3n High-Impedance Interrupt EN/Disable Definition   ----------
+#define TIMER3n_INT_HIZDIS       (0x0uL << TIMER3n_INTCR_HIZIEN_Pos)
+#define TIMER3n_INT_HIZEN        (0x1uL << TIMER3n_INTCR_HIZIEN_Pos)
+
+//----------   TIMER3n Capture Interrupt EN/Disable Definition   ----------
+#define TIMER3n_INT_CAPDIS       (0x0uL << TIMER3n_INTCR_T3nCIEN_Pos)
+#define TIMER3n_INT_CAPEN        (0x1uL << TIMER3n_INTCR_T3nCIEN_Pos)
+
+//----------   TIMER3n Bottom Interrupt EN/Disable Definition   ----------
+#define TIMER3n_INT_BOTDIS       (0x0uL << TIMER3n_INTCR_T3nBTIEN_Pos)
+#define TIMER3n_INT_BOTEN        (0x1uL << TIMER3n_INTCR_T3nBTIEN_Pos)
+
+//----------   TIMER3n Period Match Interrupt EN/Disable Definition   ----------
+#define TIMER3n_INT_PMATDIS      (0x0uL << TIMER3n_INTCR_T3nPMIEN_Pos)
+#define TIMER3n_INT_PMATEN       (0x1uL << TIMER3n_INTCR_T3nPMIEN_Pos)
+
+//----------   TIMER3n A Match Interrupt EN/Disable Definition   ----------
+#define TIMER3n_INT_AMATDIS      (0x0uL << TIMER3n_INTCR_T3nAMIEN_Pos)
+#define TIMER3n_INT_AMATEN       (0x1uL << TIMER3n_INTCR_T3nAMIEN_Pos)
+
+//----------   TIMER3n B Match Interrupt EN/Disable Definition   ----------
+#define TIMER3n_INT_BMATDIS      (0x0uL << TIMER3n_INTCR_T3nBMIEN_Pos)
+#define TIMER3n_INT_BMATEN       (0x1uL << TIMER3n_INTCR_T3nBMIEN_Pos)
+
+//----------   TIMER3n C Match Interrupt EN/Disable Definition   ----------
+#define TIMER3n_INT_CMATDIS      (0x0uL << TIMER3n_INTCR_T3nCMIEN_Pos)
+#define TIMER3n_INT_CMATEN       (0x1uL << TIMER3n_INTCR_T3nCMIEN_Pos)
+
+//==========   TIMER3n_HIZCR   ========================================
+
+//----------   TIMER3n PWM Output High-Impedance En/Disable Definition   ----------
+#define TIMER3n_HIZ_DISABLE      (0x0uL << TIMER3n_HIZCR_HIZEN_Pos)
+#define TIMER3n_HIZ_ENABLE       (0x1uL << TIMER3n_HIZCR_HIZEN_Pos)
+
+//----------   TIMER3n High-Impedance(BLNK) Edge Definition   ----------
+#define TIMER3n_HIZ_BLNKFALL     (0x0uL << TIMER3n_HIZCR_HEDGE_Pos)
+#define TIMER3n_HIZ_BLNKRISE     (0x1uL << TIMER3n_HIZCR_HEDGE_Pos)
+
+//==========   TIMER3n_ADTCR   ========================================
+
+//----------   TIMER3n Bottom for A/DC Trigger Signal Generator EN/Disable Definition   ----------
+#define TIMER3n_ADT_BTTGDIS      (0x0uL << TIMER3n_ADTCR_T3nBTTG_Pos)
+#define TIMER3n_ADT_BTTGEN       (0x1uL << TIMER3n_ADTCR_T3nBTTG_Pos)
+
+//----------   TIMER3n Period Match for A/DC Trigger Signal Generator EN/Disable Definition   ----------
+#define TIMER3n_ADT_PMTGDIS      (0x0uL << TIMER3n_ADTCR_T3nPMTG_Pos)
+#define TIMER3n_ADT_PMTGEN       (0x1uL << TIMER3n_ADTCR_T3nPMTG_Pos)
+
+//----------   TIMER3n A-ch Match for A/DC Trigger Signal Generator EN/Disable Definition   ----------
+#define TIMER3n_ADT_AMTGDIS      (0x0uL << TIMER3n_ADTCR_T3nAMTG_Pos)
+#define TIMER3n_ADT_AMTGEN       (0x1uL << TIMER3n_ADTCR_T3nAMTG_Pos)
+
+//----------   TIMER3n B-ch Match for A/DC Trigger Signal Generator EN/Disable Definition   ----------
+#define TIMER3n_ADT_BMTGDIS      (0x0uL << TIMER3n_ADTCR_T3nBMTG_Pos)
+#define TIMER3n_ADT_BMTGEN       (0x1uL << TIMER3n_ADTCR_T3nBMTG_Pos)
+
+//----------   TIMER3n C-ch Match for A/DC Trigger Signal Generator EN/Disable Definition   ----------
+#define TIMER3n_ADT_CMTGDIS      (0x0uL << TIMER3n_ADTCR_T3nCMTG_Pos)
+#define TIMER3n_ADT_CMTGEN       (0x1uL << TIMER3n_ADTCR_T3nCMTG_Pos)
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+typedef struct
+{
+   // TIMER3n.CR
+   TIMER3n_CR_T3nMS_Enum         T3nMS;      // TIMER3n Operation Mode Selection
+   TIMER3n_CR_T3nCLK_Enum        T3nCLK;     // TIMER3n Clock Selection
+   TIMER3n_CR_T3nECE_Enum        T3nECE;     // TIMER3n External Clock Edge Selection
+   TIMER3n_CR_T3nCPOL_Enum       T3nCPOL;    // TIMER3n Capture Polarity Selection
+
+   // TIMER3n.PDR
+   uint16_t    PDR;
+
+   // TIMER3n.ADR
+   uint16_t    ADR;
+
+   // TIMER3n.BDR
+   uint16_t    BDR;
+
+   // TIMER3n.CDR
+   uint16_t    CDR;
+
+   // TIMER3n.PREDR
+   uint16_t    Prescaler;
+} TIMER3n_CFG_Type;
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+// Control
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER3n Enable/Disable
+ * @details       This macro Enable TIMER3n Block
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_EN()                      (TIMER30->CR_b.T3nEN = 1)
+#define TIMER3n_DIS()                     (TIMER30->CR_b.T3nEN = 0)
+#define TIMER3n_EnableTimer( TIMER3x )    (TIMER3x->CR_b.T3nEN = 1)
+#define TIMER3n_DisableTimer( TIMER3x )   (TIMER3x->CR_b.T3nEN = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER3n Counter and Prescaler clear
+ * @details       This macro clears Counter and Prescalrer of TIMER3n
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_ClrCnt()                  (TIMER30->CR_b.T3nCLR = 1)
+#define TIMER3n_ClearCounter( TIMER3x )   (TIMER3x->CR_b.T3nCLR = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get TIMER3n Counter Register
+ * @details       This macro gets TIMER3n Counter Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_GetCnt()               (TIMER30->CNT)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER3n Period Match Interrupt Occurrence
+ * @details       This macro sets Period Match Interrupt Occurrence
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_SetPMOC( u32PMOC )     (TIMER30->CR_b.PMOC = u32PMOC)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER3n PWM Output High-Impedance Enable/Disable
+ * @details       This macro Enable TIMER3n PWM Output High-Impedance
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_HIZEN()                (TIMER30->HIZCR_b.T3nEN = 1)
+#define TIMER3n_HIZDIS()               (TIMER30->HIZCR_b.T3nEN = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER3n PWM Output High-Impedance by Software
+ * @details       This macro sets TIMER3n PWM Output High-Impedance by Software
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_SetHIZSW()             (TIMER30->HIZCR_b.HIZSW = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER3n High-Impedance Output Clear
+ * @details       This macro clears TIMER3n High-Impedance Output
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_ClrHIZ()               (TIMER30->HIZCR_b.HIZCLR = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get TIMER3n High-Impedance Status
+ * @details       This macro gets TIMER3n High-Impedance Status
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_GetHIZStaus()          (TIMER30->HIZCR_b.HIZSTA)
+
+// Set & Get Data Register
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER3n Period Data Register
+ * @param[in]     u32PData
+ *                   Period Data of TIMER3n
+ * @details       This macro sets TIMER3n Period Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_SetPeData( u32PData )     (TIMER30->PDR = u32PData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER3n A Data Register
+ * @param[in]     u32AData
+ *                   A Data of TIMER3n
+ * @details       This macro sets TIMER3n A Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_SetAData( u32AData )      (TIMER30->ADR = u32AData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER3n B Data Register
+ * @param[in]     u32BData
+ *                   B Data of TIMER3n
+ * @details       This macro sets TIMER3n B Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_SetBData( u32BData )      (TIMER30->BDR = u32BData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER3n C Data Register
+ * @param[in]     u32CData
+ *                   C Data of TIMER3n
+ * @details       This macro sets TIMER3n C Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_SetCData( u32CData )      (TIMER30->CDR = u32CData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get TIMER3n Capture Data Register
+ * @details       This macro gets TIMER3n Capture Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_GetCapData()                 (TIMER30->CAPDR)
+#define TIMER3n_GetCaptureData( TIMER3x )    (TIMER3x->CAPDR)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER3n PWM Output Delay Data Register
+ * @param[in]     u32DelayData
+ *                   PWM Output Delay Data of TIMER3n
+ * @details       This macro sets TIMER3n PWM Output Delay Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_SetDelayData( u32DelayData )    (TIMER30->DLY = u32DelayData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER3n A/DC Trigger Generator Data Register
+ * @param[in]     u32ADTData
+ *                   A/DC Trigger Generator Data of TIMER3n
+ * @details       This macro sets TIMER3n A/DC Trigger Generator Data Register
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_SetADTData( u32ADTData )        (TIMER30->ADTDR = u32ADTData)
+
+// Get & Clear Interrupt Flag
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER3n All Interrupt
+ * @details       This macro gets interrupt flag of TIMER3n All Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_AllInt_GetFg()                  (TIMER30->INTFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER3n C-ch Match Interrupt
+ * @details       This macro gets interrupt flag of TIMER3n C-ch Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_CMaInt_GetFg()         (TIMER30->INTFLAG_b.T30CMIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER3n B-ch Match Interrupt
+ * @details       This macro gets interrupt flag of TIMER3n B-ch Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_BMaInt_GetFg()         (TIMER30->INTFLAG_b.T30BMIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER3n A-ch Match Interrupt
+ * @details       This macro gets interrupt flag of TIMER3n A-ch Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_AchMaInt_GetFg()       (TIMER30->INTFLAG_b.T30AMIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER3n Period Match Interrupt
+ * @details       This macro gets interrupt flag of TIMER3n Period Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_PeMaInt_GetFg()        (TIMER30->INTFLAG_b.T30PMIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER3n Bottom Interrupt
+ * @details       This macro gets interrupt flag of TIMER3n Bottom Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_BotMaInt_GetFg()       (TIMER30->INTFLAG_b.T30BTIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER3n Capture Interrupt
+ * @details       This macro gets interrupt flag of TIMER3n Capture Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_CapInt_GetFg()         (TIMER30->INTFLAG_b.T30CIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of TIMER3n High-Impedance Interrupt
+ * @details       This macro gets interrupt flag of TIMER3n High-Impedance Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_HIZInt_GetFg()         (TIMER30->INTFLAG_b.HIZIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER3n All Interrupt
+ * @details       This macro Clears interrupt flag of TIMER3n All Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_AllInt_ClrFg()         (TIMER30->INTFLAG = 0x7F)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER3n C-ch Match Interrupt
+ * @details       This macro clears interrupt flag of TIMER3n C-ch Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_CchMaInt_ClrFg()       (TIMER30->INTFLAG_b.T30CMIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER3n B-ch Match Interrupt
+ * @details       This macro clears interrupt flag of TIMER3n B-ch Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_BchMaInt_ClrFg()       (TIMER30->INTFLAG_b.T30BMIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER3n A-ch Match Interrupt
+ * @details       This macro clears interrupt flag of TIMER3n A-ch Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_AchMaInt_ClrFg()       (TIMER30->INTFLAG_b.T30AMIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER3n Period Match Interrupt
+ * @details       This macro clears interrupt flag of TIMER3n Period Match Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_PeMaInt_ClrFg()        (TIMER30->INTFLAG_b.T30PMIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER3n Bottom Interrupt
+ * @details       This macro clears interrupt flag of TIMER3n Bottom Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_BotMaInt_ClrFg()       (TIMER30->INTFLAG_b.T30BTIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER3n Capture Interrupt
+ * @details       This macro clears interrupt flag of TIMER3n Capture Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_CapInt_ClrFg()         (TIMER30->INTFLAG_b.T30CIFLAG = 1)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of TIMER3n High-Impedance Interrupt
+ * @details       This macro clears interrupt flag of TIMER3n High-Impedance Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define TIMER3n_HIZInt_ClrFg()         (TIMER30->INTFLAG_b.HIZIFLAG = 1)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_TIMER3n_Init( TIMER3n_Type* TIMER3x, TIMER3n_CFG_Type* TIMER3n_Config );
+HAL_Status_Type HAL_TIMER3n_DeInit( TIMER3n_Type* TIMER3x );
+
+HAL_Status_Type HAL_TIMER3n_ConfigInterrupt( TIMER3n_Type* TIMER3x, uint32_t NewState, uint32_t USART3n_IntCfg );
+HAL_Status_Type HAL_TIMER3n_MPWMCmd( TIMER3n_Type* TIMER3x, uint32_t updatedata, uint32_t intcount );
+HAL_Status_Type HAL_TIMER3n_Start( TIMER3n_Type* TIMER3x, uint32_t NewState );
+HAL_Status_Type HAL_TIMER3n_OutputCtrl( TIMER3n_Type* TIMER3x,  uint32_t NewState, uint32_t pwmApol, uint32_t pwmBpol );
+HAL_Status_Type HAL_TIMER3n_ClockPrescaler( TIMER3n_Type* TIMER3x, uint32_t prescale );
+HAL_Status_Type HAL_TIMER3n_SetPeriod( TIMER3n_Type* TIMER3x, uint32_t period );
+HAL_Status_Type HAL_TIMER3n_SetADuty( TIMER3n_Type* TIMER3x, uint32_t aduty );
+HAL_Status_Type HAL_TIMER3n_SetBDuty( TIMER3n_Type* TIMER3x, uint32_t bduty );
+HAL_Status_Type HAL_TIMER3n_SetCDuty( TIMER3n_Type* TIMER3x, uint32_t cduty );
+HAL_Status_Type HAL_TIMER3n_SetDelayTime( TIMER3n_Type* TIMER3x, uint32_t dten, uint32_t dtpos, uint32_t clkdata );
+HAL_Status_Type HAL_TIMER3n_SetHizReg( TIMER3n_Type* TIMER3x, uint32_t u32T30HizSet );
+HAL_Status_Type HAL_TIMER3n_SetADCTrigger( TIMER3n_Type* TIMER3x, uint32_t u32triggerpoint, uint32_t u32triggertime );
+HAL_Status_Type HAL_TIMER3n_ClearStatus_IT( TIMER3n_Type* TIMER3x, uint32_t USART3n_IntCfg );
+uint32_t HAL_TIMER3n_GetStatus_IT( TIMER3n_Type* TIMER3x );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _TIMER3n_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_uartn.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_uartn.h
new file mode 100644
index 0000000..e314b6a
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_uartn.h
@@ -0,0 +1,223 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_uartn.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for uartn firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _UARTn_H_
+#define _UARTn_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * UARTn time-out definitions in case of using Read() and Write function
+ * with Blocking Flag mode
+ *//*-------------------------------------------------------------------------*/
+#define UARTn_BLOCKING_TIMEOUT   0xffffuL    // (0xFFFFFFFFuL)
+
+//--------------------------------------
+// Macro defines for UARTn interrupt enable register
+//--------------------------------------
+#define UARTn_IER_RBRINT_EN      ((uint8_t)(1 << 0))     /**<  RBR Interrupt enable */
+#define UARTn_IER_THREINT_EN     ((uint8_t)(1 << 1))     /**<  THR Interrupt enable */
+#define UARTn_IER_RLSINT_EN      ((uint8_t)(1 << 2))     /**<  RX line status interrupt enable */
+#define UARTn_IER_TXE_EN         ((uint8_t)(1 << 3))     /**<  TXE interrupt enable */
+#define UARTn_IER_BITMASK        ((uint8_t)(0x0F))       /**<  UART interrupt enable register bit mask */
+
+//--------------------------------------
+// Macro defines for UARTn interrupt identification register
+//--------------------------------------
+#define UARTn_IIR_INTSTAT_PEND   ((uint8_t)(1 << 0))     /**<  Interrupt Status - Active low */
+#define UARTn_IIR_INTID_RLS      ((uint8_t)(3 << 1))     /**<  Interrupt identification: Receive line status */
+#define UARTn_IIR_INTID_RDA      ((uint8_t)(2 << 1))     /**<  Interrupt identification: Receive data available */
+#define UARTn_IIR_INTID_THRE     ((uint8_t)(1 << 1))     /**<  Interrupt identification: THRE interrupt */
+#define UARTn_IIR_INTID_TXE      ((uint8_t)(1 << 4))     /**<  Interrupt identification: TXE interrupt */
+#define UARTn_IIR_INTID_MASK     ((uint8_t)(7 << 1))     /**<  Interrupt identification: Interrupt ID mask */
+#define UARTn_IIR_BITMASK        ((uint8_t)(0x1F))       /**<  UART interrupt identification register bit mask */
+
+//--------------------------------------
+// Macro defines for UARTn line control register
+//--------------------------------------
+#define UARTn_LCR_WLEN5          ((uint8_t)(0))          /**<  UART 5 bit data mode */
+#define UARTn_LCR_WLEN6          ((uint8_t)(1 << 0))     /**<  UART 6 bit data mode */
+#define UARTn_LCR_WLEN7          ((uint8_t)(2 << 0))     /**<  UART 7 bit data mode */
+#define UARTn_LCR_WLEN8          ((uint8_t)(3 << 0))     /**<  UART 8 bit data mode */
+#define UARTn_LCR_STOPBIT_SEL    ((uint8_t)(1 << 2))     /**<  UART Two Stop Bits Select */
+#define UARTn_LCR_PARITY_EN      ((uint8_t)(1 << 3))     /**<  UART Parity Enable */
+#define UARTn_LCR_PARITY_ODD     ((uint8_t)(0 << 4))     /**<  UART Odd Parity Select */
+#define UARTn_LCR_PARITY_EVEN    ((uint8_t)(1 << 4))     /**<  UART Even Parity Select */
+#define UARTn_LCR_PARITY_F_1     ((uint8_t)(2 << 4))     /**<  UART force 1 stick parity */
+#define UARTn_LCR_PARITY_F_0     ((uint8_t)(3 << 4))     /**<  UART force 0 stick parity */
+#define UARTn_LCR_BREAK_EN       ((uint8_t)(1 << 6))     /**<  UART Transmission Break enable */
+#define UARTn_LCR_BITMASK        ((uint8_t)(0x7F))       /**<  UART line control bit mask */
+
+//--------------------------------------
+// Macro defines for UARTn data control register
+//--------------------------------------
+#define UARTn_DCR_TXINV       ((uint8_t)(1 << 2))     /**<  data control register: Tx Data Inversion */
+#define UARTn_DCR_RXINV       ((uint8_t)(1 << 3))     /**<  data control register: Rx Data Inversion */
+#define UARTn_DCR_LBON        ((uint8_t)(1 << 4))     /**<  data control register: Local loopback test mode */
+#define UARTn_DCR_BITMASK     ((uint8_t)(0x7 << 2))   /**<  UART data control bit mask */
+
+//--------------------------------------
+// Macro defines for UARTn line status register
+//--------------------------------------
+#define UARTn_LSR_RDR         ((uint8_t)(1 << 0))     /**<  Line status register: Receive data ready */
+#define UARTn_LSR_OE          ((uint8_t)(1 << 1))     /**<  Line status register: Overrun error */
+#define UARTn_LSR_PE          ((uint8_t)(1 << 2))     /**<  Line status register: Parity error */
+#define UARTn_LSR_FE          ((uint8_t)(1 << 3))     /**<  Line status register: Framing error */
+#define UARTn_LSR_BI          ((uint8_t)(1 << 4))     /**<  Line status register: Break interrupt */
+#define UARTn_LSR_THRE        ((uint8_t)(1 << 5))     /**<  Line status register: Transmit holding register empty */
+#define UARTn_LSR_TEMT        ((uint8_t)(1 << 6))     /**<  Line status register: Transmitter empty */
+#define UARTn_LSR_BITMASK     ((uint8_t)(0x7F))       /**<  UART Line status bit mask */
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+/**   UARTn Data Bit type definitions */
+typedef enum
+{
+   UARTn_DATA_BIT_5 = 0,      /**<  5 Data Bits */
+   UARTn_DATA_BIT_6,          /**<  6 Data Bits */
+   UARTn_DATA_BIT_7,          /**<  7 Data Bits */
+   UARTn_DATA_BIT_8           /**<  8 Data Bits */
+} UARTn_DATA_BIT_Type;
+
+/**   UARTn Stop Bit type definitions */
+typedef enum
+{
+   UARTn_STOP_BIT_1 = 0,      /**<  1 Stop Bits */
+   UARTn_STOP_BIT_2           /**<  2 Stop Bits */
+} UARTn_STOP_BIT_Type;
+
+/**   UARTn Parity Bit type definitions */
+typedef enum
+{
+   UARTn_PARITY_BIT_NONE = 0,    /**<  No parity */
+   UARTn_PARITY_BIT_ODD,         /**<  Odd parity */
+   UARTn_PARITY_BIT_EVEN,        /**<  Even parity */
+   UARTn_PARITY_BIT_SP_1,        /**<  Forced "1" stick parity */
+   UARTn_PARITY_BIT_SP_0         /**<  Forced "0" stick parity */
+} UARTn_PARITY_BIT_Type;
+
+/**   UARTn Interrupt Type definitions */
+typedef enum
+{
+   UARTn_INTCFG_RBR = 0,    /**<  RBR Interrupt enable */
+   UARTn_INTCFG_THRE,       /**<  THR Interrupt enable */
+   UARTn_INTCFG_RLS,        /**<  RX line status interrupt enable */
+   UARTn_INTCFG_TXE         /**<  TXE interrupt */
+} UARTn_INT_Type;
+
+/**   UARTn Data Control type definition */
+typedef enum
+{
+   UARTn_DATA_CONTROL_LOOPBACK = 0,     /**<  Loop back mode select */
+   UARTn_DATA_CONTROL_RXINV,
+   UARTn_DATA_CONTROL_TXINV,
+   UARTn_DATA_CONTROL_RTXINV,
+} UARTn_DATA_CONTROL_Type;
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+/**   UARTn Configuration Structure definition */
+typedef struct
+{
+   uint32_t                Baudrate;     /**<  Baud Rate */
+   UARTn_DATA_BIT_Type     Databits;      /**<  Number of Data Bits, should be:
+                                                -  UARTn_DATA_BIT_5:    5 Data Bits
+                                                -  UARTn_DATA_BIT_6:    6 Data Bits
+                                                -  UARTn_DATA_BIT_7:    7 Data Bits
+                                                -  UARTn_DATA_BIT_8:    8 Data Bits
+                                          */
+   UARTn_PARITY_BIT_Type   Parity;        /**<  Number of Parity Bits, should be:
+                                                -  UARTn_PARITY_BIT_NONE:  No Parity
+                                                -  UARTn_PARITY_BIT_ODD:   Odd Parity
+                                                -  UARTn_PARITY_BIT_EVEN:  Even Parity
+                                                -  UARTn_PARITY_BIT_SP_1:  Forced "1" Stick Parity
+                                                -  UARTn_PARITY_BIT_SP_0:  Forced "0" Stick Parity
+                                          */
+   UARTn_STOP_BIT_Type     Stopbits;      /**<  Number of Stop Bits, should be:
+                                                -  UARTn_STOP_BIT_1:    1 Stop Bits
+                                                -  UARTn_STOP_BIT_2:    2 Stop Bits
+                                          */
+} UARTn_CFG_Type;
+
+//******************************************************************************
+// Variable
+//******************************************************************************
+
+extern char     InData[80];
+extern int      InFlag;
+extern int      InCount;
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_UART_Init( UARTn_Type* UARTx, UARTn_CFG_Type* UARTn_Config );
+HAL_Status_Type HAL_UART_DeInit( UARTn_Type* UARTx );
+
+HAL_Status_Type HAL_UART_ConfigStructInit( UARTn_CFG_Type* UARTn_Config );
+HAL_Status_Type HAL_UART_ConfigInterrupt( UARTn_Type* UARTx, UARTn_INT_Type UARTn_IntCfg, FunctionalState NewState );
+HAL_Status_Type HAL_UART_DataControlConfig( UARTn_Type* UARTx, UARTn_DATA_CONTROL_Type Mode, FunctionalState NewState );
+HAL_Status_Type HAL_UART_IFDelayConfig( UARTn_Type* UARTx, uint8_t waitval );
+HAL_Status_Type HAL_UART_ForceBreak( UARTn_Type* UARTx );
+uint8_t HAL_UART_GetLineStatus( UARTn_Type* UARTx );
+FlagStatus HAL_UART_CheckBusy( UARTn_Type* UARTx );
+
+HAL_Status_Type HAL_UART_TransmitByte( UARTn_Type* UARTx, uint8_t Data );
+uint8_t HAL_UART_ReceiveByte( UARTn_Type* UARTx );
+uint32_t HAL_UART_Transmit( UARTn_Type* UARTx, uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag );
+uint32_t HAL_UART_Receive( UARTn_Type* UARTx, uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _UARTn_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_usart1n.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_usart1n.h
new file mode 100644
index 0000000..a659629
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_usart1n.h
@@ -0,0 +1,241 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_usart1n.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for usart1n firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _USART1n_H_
+#define _USART1n_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * USART1n time-out definitions in case of using Read() and Write function
+ * with Blocking Flag mode
+ *//*-------------------------------------------------------------------------*/
+#define USART1n_BLOCKING_TIMEOUT    (0xFFFFFFFFuL)
+
+//--------------------------------------
+// Macro defines for USART1n interrupt enable register
+//--------------------------------------
+
+#define USART1n_IER_WAKEINT_EN   ((uint16_t)(1 << 2))    /**<  WAKE Interrupt enable */
+#define USART1n_IER_RXCINT_EN    ((uint16_t)(1 << 3))    /**<  RXC Interrupt enable */
+#define USART1n_IER_TXCINT_EN    ((uint16_t)(1 << 4))    /**<  TXC interrupt enable */
+#define USART1n_IER_DR_EN        ((uint16_t)(1 << 5))    /**<  DR interrupt enable */
+#define USART1n_IER_BITMASK      ((uint16_t)(0x3C))      /**<  USART interrupt enable register bit mask */
+
+
+//--------------------------------------
+// Macro defines for USART1n interrupt status register
+//--------------------------------------
+#define USART1n_SR_DRE           ((uint16_t)(1 << 7))    /**<  Interrupt identification: Tx Buffer Busy */
+#define USART1n_SR_TXC           ((uint16_t)(1 << 6))    /**<  Interrupt identification: Tx Complete */
+#define USART1n_SR_RXC           ((uint16_t)(1 << 5))    /**<  Interrupt identification: Rx Complete */
+#define USART1n_SR_WAKE          ((uint16_t)(1 << 4))    /**<  Interrupt identification: Wake */
+#define USART1n_SR_DOR           ((uint16_t)(1 << 2))    /**<  Interrupt identification: Data OverRun */
+#define USART1n_SR_FE            ((uint16_t)(1 << 1))    /**<  Interrupt identification: Frame Error */
+#define USART1n_SR_PE            ((uint16_t)(1 << 0))    /**<  Interrupt identification: Parity Error */
+#define USART1n_SR_BITMASK       ((uint16_t)(0xFF))      /**<  USART interrupt identification register bit mask */
+
+#define USART1n_CR2_USTnRX8      ((uint16_t)(1 << 0))    /**<  */
+#define USART1n_CR2_USTnTX8      ((uint16_t)(1 << 1))    /**<  */
+#define USART1n_CR2_USTnSB       ((uint16_t)(1 << 2))    /**<  */
+#define USART1n_CR2_FXCHn        ((uint16_t)(1 << 3))    /**<  */
+#define USART1n_CR2_USTnSSEN     ((uint16_t)(1 << 4))    /**<  */
+#define USART1n_CR2_DISSCKn      ((uint16_t)(1 << 5))    /**<  */
+#define USART1n_CR2_LOOPSn       ((uint16_t)(1 << 6))    /**<  */
+#define USART1n_CR2_MASTERn      ((uint16_t)(1 << 7))    /**<  */
+#define USART1n_CR2_DBLSn        ((uint16_t)(1 << 8))    /**<  */
+#define USART1n_CR2_USTnEN       ((uint16_t)(1 << 9))    /**<  */
+#define USART1n_CR2_BITMASK      ((uint16_t)(0x3FF))     /**<  */
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+typedef enum
+{
+   USART1n_UART_MODE = 0,     /**<  UART Mode */
+   USART1n_USRT_MODE,         /**<  USRT Mode (Syncronous) */
+   USART1n_SPI_MODE = 3       /**<  SPI Mode */
+} USART1n_OPMODE_Type;
+
+typedef enum
+{
+   USART1n_SPI_LSB = 0,          /**<  SPI LSB First */
+   USART1n_SPI_MSB,              /**<  SPI MSB First */
+} USART1n_SPI_ORDER_Type;
+
+typedef enum
+{
+   USART1n_SPI_TX_RISING = 0,    /**<  Txd Change : Rising / Rxd Change : Falling */
+   USART1n_SPI_TX_FALLING,       /**<  Txd Change : Falling / Rxd Change : Rising */
+} USART1n_ACK_Type;
+
+typedef enum
+{
+   USART1n_SPI_TX_LEADEDGE_SAMPLE = 0,    /**<  Leading edge : Sample / Trailing edge : Setup */
+   USART1n_SPI_TX_LEADEDGE_SETUP,         /**<  Leading edge : Setup / Trailing edge : Sample */
+} USART1n_EDGE_Type;
+
+/**   USART1n Data Bit type definitions */
+typedef enum
+{
+   USART1n_DATA_BIT_5 = 0,       /**<  5 Data Bits */
+   USART1n_DATA_BIT_6,           /**<  6 Data Bits */
+   USART1n_DATA_BIT_7,           /**<  7 Data Bits */
+   USART1n_DATA_BIT_8,           /**<  8 Data Bits */
+   USART1n_DATA_BIT_9 = 7        /**<  9 Data Bits */
+} USART1n_DATA_BIT_Type;
+
+/**   USART1n Stop Bit type definitions */
+typedef enum
+{
+   USART1n_STOP_BIT_1 = 0,       /**<  1 Stop Bits */
+   USART1n_STOP_BIT_2            /**<  2 Stop Bits */
+} USART1n_STOP_BIT_Type;
+
+/**   USART1n Parity Bit type definitions */
+typedef enum
+{
+   USART1n_PARITY_BIT_NONE = 0,     /**<  No parity */
+   USART1n_PARITY_BIT_EVEN = 2,     /**<  Even parity */
+   USART1n_PARITY_BIT_ODD = 3       /**<  Odd parity */
+} USART1n_PARITY_BIT_Type;
+
+/**   USART Data Control type definition */
+typedef enum
+{
+   USART1n_CONTROL_USTRX8 = 0,
+   USART1n_CONTROL_USTTX8,
+   USART1n_CONTROL_USTSB,
+   USART1n_CONTROL_FXCH,
+   USART1n_CONTROL_USTSSEN,
+   USART1n_CONTROL_DISSCK,
+   USART1n_CONTROL_LOOPS,
+   USART1n_CONTROL_MASTER,
+   USART1n_CONTROL_DBLS,
+   USART1n_CONTROL_USTEN
+} USART1n_CONTROL_Type;
+
+typedef enum
+{
+   USART1n_STATUS_PE = 0,
+   USART1n_STATUS_FE,
+   USART1n_STATUS_DOR,
+   USART1n_STATUS_WAKE,
+   USART1n_STATUS_RXC,
+   USART1n_STATUS_TXC,
+   USART1n_STATUS_DRE,
+} USART1n_STATUS_Type;
+
+typedef enum
+{
+   USART1n_INTCFG_WAKE = 0,   /**<  Wake-Up Interrupt enable*/
+   USART1n_INTCFG_RXC,        /**<  Receive Complete Interrupt enable*/
+   USART1n_INTCFG_TXC,        /**<  Transmit Complete line status interrupt enable*/
+   USART1n_INTCFG_DR          /**<  Data Register Empty interrupt */
+} USART1n_INT_Type;
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+typedef struct
+{
+   uint32_t                   Baudrate;
+   USART1n_OPMODE_Type        Mode;
+   USART1n_SPI_ORDER_Type     Order;
+   USART1n_ACK_Type           ACK;
+   USART1n_EDGE_Type          Edge;
+   USART1n_DATA_BIT_Type      Databits;      /**<  Number of Data Bits, should be:
+                                                   -  USART_DATABIT_5:  5 Data Bits
+                                                   -  USART_DATABIT_6:  6 Data Bits
+                                                   -  USART_DATABIT_7:  7 Data Bits
+                                                   -  USART_DATABIT_8:  8 Data Bits
+                                                   -  USART_DATABIT_9:  9 Data Bits
+                                             */
+   USART1n_PARITY_BIT_Type    Parity;        /**<  Number of Parity Bits, should be:
+                                                   -  USART_PARITY_NONE:   No Parity
+                                                   -  USART_PARITY_ODD:    Odd Parity
+                                                   -  USART_PARITY_EVEN:   Even Parity
+                                                   -  USART_PARITY_SP_1:   Forced "1" Stick Parity
+                                                   -  USART_PARITY_SP_0:   Forced "0" Stick Parity
+                                             */
+   USART1n_STOP_BIT_Type      Stopbits;      /**<  Number of Stop Bits, should be:
+                                                   -  USART_STOPBIT_1:  1 Stop Bits
+                                                   -  USART_STOPBIT_2:  2 Stop Bits
+                                             */
+} USART1n_CFG_Type;
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_USART_Init( USART1n_Type* USART1x, USART1n_CFG_Type* USART1n_Config );
+HAL_Status_Type HAL_USART_DeInit( USART1n_Type* USART1x );
+
+HAL_Status_Type HAL_USART_UART_Mode_Config( USART1n_CFG_Type* USART1n_Config );
+HAL_Status_Type HAL_USART_USRT_Mode_Config( USART1n_CFG_Type* USART1n_Config );
+HAL_Status_Type HAL_USART_SPI_Mode_Config( USART1n_CFG_Type* USART1n_Config );
+HAL_Status_Type HAL_USART_ConfigInterrupt( USART1n_Type* USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState );
+HAL_Status_Type HAL_USART_DataControlConfig( USART1n_Type* USART1x, USART1n_CONTROL_Type Mode, FunctionalState NewState );
+HAL_Status_Type HAL_USART_Enable( USART1n_Type* USART1x, FunctionalState state );
+HAL_Status_Type HAL_USART_ClearStatus( USART1n_Type* USART1x, USART1n_STATUS_Type Status );
+uint8_t HAL_USART_GetStatus( USART1n_Type* USART1x );
+
+FlagStatus HAL_USART_CheckBusy( USART1n_Type* USART1x );
+
+HAL_Status_Type HAL_USART_TransmitByte( USART1n_Type* USART1x, uint8_t Data );
+uint8_t HAL_USART_ReceiveByte( USART1n_Type* USART1x );
+uint32_t HAL_USART_Transmit( USART1n_Type* USART1x, uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag );
+uint32_t HAL_USART_Receive( USART1n_Type* USART1x, uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _USART1n_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wdt.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wdt.h
new file mode 100644
index 0000000..5a7d41e
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wdt.h
@@ -0,0 +1,116 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_wdt.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for wdt firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _WDT_H_
+#define _WDT_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+// WDT_CR interrupt enable bit
+/* Deprecated
+#define WDT_CR_UNFIEN            ((uint32_t)(1 << 2))    // WDT Underflow Interrupt Enable bit
+#define WDT_CR_WINMIEN           ((uint32_t)(1 << 3))    // WDT Window Match Interrupt Enable bit
+#define WDT_INTERRUPT_BITMASK    0x000c
+*/
+
+/**   WDT_SR interrupt enable bit */
+#define WDT_SR_UNFIFLAG          ((uint32_t)(1 << 0))    // WDT Underflow Interrupt Flag bit
+#define WDT_SR_WINMIFLAG         ((uint32_t)(1 << 1))    // WDT Window Match Interrupt Flag bit
+
+#define WDT_STATUS_BITMASK       0x0003
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+enum
+{
+   WDT_DIV_4 = 0,
+   WDT_DIV_16,
+   WDT_DIV_64,
+   WDT_DIV_256
+};
+
+typedef enum
+{
+   WDT_INTCFG_UNFIEN = 0,     /**<  UNFIEN Interrupt enable */
+   WDT_INTCFG_WINMIEN,        /**<  WINMIEN Interrupt enable */
+} WDT_INT_Type;
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+typedef struct
+{
+   uint8_t     wdtResetEn;       /**<  if ENABLE -> the Reset bit is enabled */
+   uint16_t    wdtClkDiv;        /**<  wdtClkDiv */
+   uint32_t    wdtTmrConst;      /**<  Set Watch-Dog Timer Data Register */
+   uint32_t    wdtWTmrConst;     /**<  Set Watch-Dog Timer Window Data Register */
+} WDT_CFG_Type;
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_WDT_Init( WDT_CFG_Type* WDT_Config );
+HAL_Status_Type HAL_WDT_DeInit( void );
+
+HAL_Status_Type HAL_WDT_ConfigInterrupt( WDT_INT_Type WDT_IntCfg, FunctionalState NewState );
+HAL_Status_Type HAL_WDT_ReloadTimeCounter( void );
+HAL_Status_Type HAL_WDT_Start( FunctionalState ctrl );
+HAL_Status_Type HAL_WDT_ClearStatus( uint32_t clrbit );
+uint32_t HAL_WDT_GetStatus( void );
+
+uint32_t HAL_WDT_GetCurrentCount( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _WDT_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wt.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wt.h
new file mode 100644
index 0000000..d4117ec
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wt.h
@@ -0,0 +1,154 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_wt.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for wt firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _WT_H_
+#define _WT_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+//==========   WT_CR   ========================================
+
+//----------   WT Interval Selection   ----------
+#define WT_DIV2E7          (0x0uL << 4)
+#define WT_DIV2E13         (0x1uL << 4)
+#define WT_DIV2E14         (0x2uL << 4)
+#define WT_DIV2E14DR       (0x3uL << 4)
+
+//----------   WT Interrupt En/Disable   ----------
+#define WT_INTDIS          (0x0uL << 3)
+#define WT_INTEN           (0x1uL << 3)
+
+/**   WT_CR interrupt enable bit */
+#define WT_CR_WTIEN              ((uint32_t)(1 << 3))    // WT Interrupt Enable bit
+#define WT_INTERRUPT_BITMASK     0x0008
+
+/**   WT_CR interrupt status flag bit */
+#define WT_CR_WTIFLAG            ((uint32_t)(1 << 1))    // WT Interrupt Flag bit
+#define WT_STATUS_BITMASK        0x0002
+
+#define WT_CR_WTCLR              ((uint32_t)(1 << 0))    // WT counter and divider clear bit
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+//==============================================================================
+// Enumeration
+//==============================================================================
+
+enum
+{
+   WT_DIV_2_7 = 0,
+   WT_DIV_2_13,
+   WT_DIV_2_14,
+   WT_DIV_2_14_MUL_DR
+};
+
+//==============================================================================
+// Structure
+//==============================================================================
+
+typedef struct
+{
+   uint32_t    wtClkDiv;      /**<  wtClkDiv */
+   uint32_t    wtTmrConst;    /**<  Set Watch Timer Data Register */
+} WT_CFG_Type;
+
+//******************************************************************************
+// Macro
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Watch Timer Enable/Disable
+ * @details       This macro Enable Watch Timer Block
+ *//*-------------------------------------------------------------------------*/
+#define WT_EN()      (WT->CR_b.WTEN = 1)
+#define WT_DIS()     (WT->CR_b.WTEN = 0)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Watch Timer Counter Register
+ * @details       This macro gets Watch Timer Counter Register
+ *//*-------------------------------------------------------------------------*/
+#define WT_GetCnt()     (WT->CNT)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Watch Timer Data Register
+ * @param[in]     u32WTData
+ *                   Data of WT_DR
+ * @details       This macro sets Watch Timer Data Register
+ *//*-------------------------------------------------------------------------*/
+#define WT_SetWT_DR( u32WTData )    (WT->DR = u32WTData)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get flags of Watch Timer Interrupt
+ * @details       This macro gets interrupt flag of Watch Timer Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define WTInt_GetFg()      (WT->CR_b.WTIFLAG)
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear flags of Watch Timer Interrupt
+ * @details       This macro clears interrupt flag of Watch Timer Interrupt
+ *//*-------------------------------------------------------------------------*/
+#define WTInt_ClrFg()      (WT->CR_b.WTIFLAG = 1)
+
+//******************************************************************************
+// Function
+//******************************************************************************
+
+HAL_Status_Type HAL_WT_Init( WT_CFG_Type* WT_Config );
+HAL_Status_Type HAL_WT_DeInit( void );
+
+HAL_Status_Type HAL_WT_ConfigInterrupt( FunctionalState NewState );
+HAL_Status_Type HAL_WT_Start( FunctionalState ctrl );
+HAL_Status_Type HAL_WT_SetRegister( uint32_t u32WTSet );
+HAL_Status_Type HAL_WT_ClearStatus( void );
+uint32_t HAL_WT_GetStatus( void );
+
+uint32_t HAL_WT_GetCurrentCount( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /*_WT_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wtidky.h b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wtidky.h
new file mode 100644
index 0000000..c1dedf8
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_wtidky.h
@@ -0,0 +1,68 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_wtidky.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for wtidky firmware library on A31G12x
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+#ifndef _WTIDKY_H_
+#define _WTIDKY_H_
+
+#include "A31G12x.h"
+#include "A31G12x_hal_aa_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+// Write ID Key Definition
+#define SCU_SCCRWTIDKY     0x570AuL       // 0     SCUCG_SCCR_WTIDKY_Value
+#define SCU_CLKSRCRWTIDKY  0xA507uL       // 1     SCUCG_CLKSRCR_WTIDKY_Value
+#define XTFWTIDKY          0x9B37uL       // 2     SCUCG_XTFLSR_WTIDKY_Value
+#define HIRCWTIDKY         0xA6B5uL       // 3     SCUCC_HIRCTRM_WTIDKY_Value
+#define WDTRCWTIDKY        0x4C3DuL       // 4     SCUCC_WDTRCTRM_WTIDKY_Value
+#define REMWTIDKY          0xE2F1uL       // 5     SCUCC_PMREMAP_WTIDKY_Value
+#define WDTWTIDKY          0x5A69uL       // 6     WDT_CR_WTIDKY_Value
+#define T30OUTWTIDKY       0xE06CuL       // 7     TIMER30_T30_OUTCR_WTIDKY_Value
+#define FMC_BCRWTIDKY      0xC1BEuL       // 8     FMC_BCR_WTIDKY_Value
+#define FMC_CRWTIDKY       0x6C93uL       // 9     FMC_CR_WTIDKY_Value
+#define SWRSTWTIDKY        0x9EB3uL       // 10    SCUCC_SWRSTR_WTIDKY_Value
+#define VECTWTIDKY         0x05FAuL       // 11
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif   /* _WTIDKY_H_ */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_adc.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_adc.c
new file mode 100644
index 0000000..d7b2921
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_adc.c
@@ -0,0 +1,264 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_adc.c
+* @brief    Contains all functions support for adc firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_adc.h"
+#include "A31G12x_hal_scu.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the ADC peripheral with the specified parameters.
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @param[in]     ADC_Config
+ *                   Pointer to a ADC_CFG_Type structure
+ *                   that contains the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_ADC_Init( ADC_Type* ADCx, ADC_CFG_Type* ADC_Config )
+{
+   uint32_t    tempreg;
+
+   /* Check ADC handle */
+   if( ADCx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_ADCLKE, PPxCLKE_Enable );
+
+   ADCx->CR = ( 1 << ADC_CR_ADCEN_Pos ); // ADCEN;
+
+   tempreg = 0
+             | ( 1 << ADC_CR_ADCEN_Pos ) // ADCEN
+             | ( ( ( ADC_Config->TrgSel ) & 7 ) << ADC_CR_TRIG_Pos ) // TRGSRC
+             | ( ( ( ADC_Config->RefSel ) & 1 ) << ADC_CR_REFSEL_Pos )
+             | ( 1 << ADC_CR_ADCIFLAG_Pos ) // clear flag
+             ;
+   ADCx->CR = tempreg;
+
+   ADCx->PREDR = ( ADC_Config->InClkDiv & ADC_PREDR_PRED_Msk );
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Close ADC
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_ADC_DeInit( ADC_Type* ADCx )
+{
+   /* Check ADC handle */
+   if( ADCx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   ADCx->CR = 0;
+   HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_ADCLKE, PPxCLKE_Disable );
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         ADC interrupt configuration
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_ADC_ConfigInterrupt( ADC_Type* ADCx, FunctionalState NewState )
+{
+   uint32_t    tempreg;
+
+   /* Check ADC handle */
+   if( ADCx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   tempreg = ADCx->CR;
+   tempreg &= ~( 1 << ADC_CR_ADCIEN_Pos );
+
+   if( NewState )
+   {
+      tempreg |= ( 1 << ADC_CR_ADCIEN_Pos );
+   }
+   ADCx->CR = tempreg;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Select ADC Channel Number
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @param[in]     Channel
+ *                   Channel Number
+ *                   -  ADC_CR_ADSEL_AN0 ~ ADC_CR_ADSEL_AN13
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_ADC_ChannelSel( ADC_Type* ADCx, uint32_t Channel )
+{
+   uint32_t    temp_reg;
+
+   /* Check ADC handle */
+   if( ADCx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   temp_reg = ADCx->CR & ( uint32_t )( ~ADC_CR_ADSEL_Msk );
+   temp_reg |= ( uint32_t )( Channel & ADC_CR_ADSEL_Msk );
+   ADCx->CR = temp_reg;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Start A/D conversion
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_ADC_Start( ADC_Type* ADCx )
+{
+   /* Check ADC handle */
+   if( ADCx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   ADCx->CR |= ( 1 << ADC_CR_ADST_Pos );
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Stop A/D conversion
+ *                If this function called after a conversion cycle starts,
+ *                the current conversion is completed
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_ADC_Stop( ADC_Type* ADCx )
+{
+   /* Check ADC handle */
+   if( ADCx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   ADCx->CR &= ~( 1 << ADC_CR_ADST_Pos );
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear ADC channel status
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_ADC_ClearStatus( ADC_Type* ADCx )
+{
+   uint32_t    tempreg;
+
+   /* Check ADC handle */
+   if( ADCx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   tempreg = ADCx->CR;
+   tempreg |= ( 1 << ADC_CR_ADCIFLAG_Pos );
+
+   ADCx->CR = tempreg;  // clear flag;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get ADC channel status
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @return        ADC status register
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_ADC_GetStatus( ADC_Type* ADCx )
+{
+   uint32_t    tempreg;
+
+   tempreg = ADCx->CR;
+   tempreg &= ( 1 << ADC_CR_ADCIFLAG_Pos );
+
+   return tempreg;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Result conversion from A/D data register
+ * @param[in]     ADCx
+ *                   Pointer to the target ADC
+ *                   -  ADC
+ * @return        Result of conversion
+ *//*-------------------------------------------------------------------------*/
+uint16_t HAL_ADC_GetData( ADC_Type* ADCx )
+{
+   uint16_t    adc_value;
+
+   adc_value = ADCx->DR;
+
+   return ADC_DR_RESULT( adc_value );
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_crc.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_crc.c
new file mode 100644
index 0000000..849de94
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_crc.c
@@ -0,0 +1,212 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_crc.c
+* @brief    Contains all functions support for crc firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_crc.h"
+#include "A31G12x_hal_scu.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize CRC/Checksum peripheral
+ * @param         None
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_CRC_Init( void )
+{
+   // enable peripheral clock
+   HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_CRCLKE, PPxCLKE_Enable );
+
+   // return
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         DeInitialize CRC peripheral
+ * @param         None
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_CRC_DeInit( void )
+{
+   // reset peripheral and disable peripheral clock
+   HAL_SCU_Peripheral_SetReset2( PPRST2_CRRST );
+   HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_CRCLKE, PPxCLKE_Disable );
+
+   // return
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set CRC/Checksum Address
+ * @param[in]     u32SAdr
+ *                   CRC/Checksum Start Address
+ *                   -  0x10000000 ~ 0x10007FFF
+ * @param[in]     u32EAdr
+ *                   CRC/Checksum End Address
+ *                   -  0x10000000 ~ 0x10007FFF
+ * @param[in]     u32IniD
+ *                   CRC/Checksum Initial Data
+ * @return        @ref HAL_Status_Type
+ * @details       This function sets the start/end address for range and initial data for calculation
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_CRC_SetAddress( uint32_t u32SAdr, uint32_t u32EAdr, uint32_t u32IniD )
+{
+   SCUCG->PPCLKEN2_b.CRCLKE = 1;    // CRC/Checksum Clock Enable
+
+   CRC->SADR = u32SAdr;             // Set start address
+   CRC->EADR = u32EAdr;             // Set end address
+   CRC->INIT = u32IniD;             // Set initial data for CRC/Checksum
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         CRC/Checksum Auto Mode Start and Result
+ * @param[in]     u32SEL
+ *                   CRC/Checksum Selection
+ *                   -  CRC_CRC
+ *                   -  CRC_CHECKSUM
+ * @param[in]     u32POLY
+ *                   CRC Polynomial Selection
+ *                   -  CRC_CCITT
+ *                   -  CRC_16
+ * @param[in]     u32FirstBit
+ *                   CRC 1st Shifted-in bit
+ *                   -  CRC_MSB
+ *                   -  CRC_LSB
+ * @return        CRC/Checksum Result
+ * @details       This function starts CRC/Checksum calculation and gets result
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_CRC_ConfigAutoMode( uint32_t u32SEL, uint32_t u32POLY, uint32_t u32FirstBit )
+{
+   uint32_t    imgPRIMASK;
+
+   if( SystemCoreClock > 20000000uL )
+   {
+      SCUCG->SCDIVR1_b.HDIV = 3;          // HCLK should be less than or equal to 20MHz during CRC/Checksum auto mode
+   }
+
+   CRC->CR = 0
+             | ( 0x1uL << CRC_CR_RLTCLR_Pos )   // CRC/Checksum Result Data Register (CRC_RLT) Initialization
+             | MODS_AutoMode                    // User/Auto Mode Selection
+             | u32SEL                           // CRC/Checksum Selection
+             | u32POLY                          // Polynomial Selection (CRC only)
+             | CRC_NOINC                        // CRC/Checksum Start Address Auto Increment Control (User mode only)
+             | u32FirstBit;                     // First Shifted-in Selection (CRC only)
+
+   imgPRIMASK = __get_PRIMASK();          // backup PRIMASK (current global interrupt configuration)
+   DI();                                  // disable global interrupt
+   CRCRun();
+   while( ChkCRCFinish() ) {}             // Check if CRC/Checksum finishes or not
+   __set_PRIMASK( imgPRIMASK );           // restore PRIMASK
+
+   SCUCG->PPCLKEN2_b.CRCLKE = 0;          // CRC/Checksum Clock Disable
+
+   if( SystemCoreClock > 20000000uL )
+   {
+      SCUCG->SCDIVR1_b.HDIV = 4;          // HCLK should be set with original frequency
+   }
+
+   return ( CRC->RLT & 0xffff );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         CRC/Checksum User Mode Start
+ * @param[in]     u32SEL
+ *                   CRC/Checksum Selection
+ *                   -  CRC_CRC
+ *                   -  CRC_CHECKSUM
+ * @param[in]     u32POLY
+ *                   CRC Polynomial Selection
+ *                   -  CRC_CCITT
+ *                   -  CRC_16
+ * @param[in]     u32AdrInc
+ *                   Auto Increment of Start Address
+ *                   -  CRC_NOINC
+ *                   -  CRC_AUTOINC
+ * @param[in]     u32FirstBit
+ *                   CRC 1st Shifted-in bit
+ *                   -  CRC_MSB
+ *                   -  CRC_LSB
+ * @return        @ref HAL_Status_Type
+ * @details       This function sets the control register for CRC/Checksum User mode
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_CRC_ConfigUserMode( uint32_t u32SEL, uint32_t u32POLY, uint32_t u32AdrInc, uint32_t u32FirstBit )
+{
+   CRC->CR = 0
+             | ( 0x1uL << CRC_CR_RLTCLR_Pos )   // CRC/Checksum Result Data Register (CRC_RLT) Initialization
+             | MODS_UserMode                       // User/Auto Mode Selection
+             | u32SEL                           // CRC/Checksum Selection
+             | u32POLY                          // Polynomial Selection (CRC only)
+             | u32AdrInc                        // CRC/Checksum Start Address Auto Increment Control (User mode only)
+             | u32FirstBit;                     // First Shifted-in Selection (CRC only)
+   CRCRun();
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         CRC/Checksum Input on User Mode
+ * @param[in]     u32Input
+ *                   CRC/Checksum Input
+ * @return        CRC/Checksum Result with finish Indicator
+ *                   -  0x8a29xxxx if on run
+ *                   -  0x0000xxxx if Finish
+ * @details       This function calculates up to finish.
+ *                The CRC_SADR register should be incremented by 4 every input on CRC_NOINC
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_CRC_UserInput( uint32_t u32Input )
+{
+   uint32_t    u32Result = 0x8a290000uL;
+   uint32_t    CRC_EADR;
+
+   CRC_InData( u32Input );
+   CRC_EADR = CRC->EADR;
+   if( ( !ChkCRCFinish() ) || ( CRC->SADR > CRC_EADR ) )    // "Auto"/"User" Increment of Start Address
+   {
+      CRCStop();                             // Stop forcingly on User Increment of Start Address
+      SCUCG->PPCLKEN2_b.CRCLKE = 0;          // CRC/Checksum Clock Disable
+      u32Result = ( CRC->RLT & 0xffff );
+   }
+
+   return u32Result;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_debug_frmwrk.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_debug_frmwrk.c
new file mode 100644
index 0000000..102740e
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_debug_frmwrk.c
@@ -0,0 +1,438 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_debug_frmwrk.c
+* @brief    Contains all functions support for debug_frmwrk firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include <stdarg.h>
+#include <stdio.h>
+#include "A31G12x_hal_debug_frmwrk.h"
+#include "A31G12x_hal_pcu.h"
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+#define ASCII_BACKSPACE          (0x08)
+#define ASCII_LINEFEED           (0x0A)
+#define ASCII_CARRIAGE_RETURN    (0x0D)
+
+#ifdef _DEBUG_MSG
+
+//******************************************************************************
+// Variable
+//******************************************************************************
+
+void ( *_db_msg )( UARTn_Type* UARTx, const void* s );
+void ( *_db_msg_ )( UARTn_Type* UARTx, const void* s );
+void ( *_db_char )( UARTn_Type* UARTx, uint8_t ch );
+void ( *_db_dec )( UARTn_Type* UARTx, uint8_t decn );
+void ( *_db_dec_16 )( UARTn_Type* UARTx, uint16_t decn );
+void ( *_db_dec_32 )( UARTn_Type* UARTx, uint32_t decn );
+void ( *_db_hex )( UARTn_Type* UARTx, uint8_t hexn );
+void ( *_db_hex_16 )( UARTn_Type* UARTx, uint16_t hexn );
+void ( *_db_hex_32 )( UARTn_Type* UARTx, uint32_t hexn );
+uint8_t ( *_db_get_char )( UARTn_Type* UARTx );
+uint8_t ( *_db_get_ch )( UARTn_Type* UARTx, uint8_t* ch );
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+#if 0
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a character to file
+ * @param[in]     ch
+ *                   Character to put
+ * @param[in]     f
+ *                   Pointer to file
+ * @return        character
+ * @note          if you use IAR EWARM, select Full as Options/General Options/Library Configuration/Library.
+ *//*-------------------------------------------------------------------------*/
+int fputc( int ch, FILE* f )
+{
+   while( HAL_UART_CheckBusy( ( UARTn_Type* )DEBUG_UART_PORT ) );
+   HAL_UART_TransmitByte( ( UARTn_Type* )DEBUG_UART_PORT, ch );
+
+   return( ch );
+}
+#endif
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a character to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     ch
+ *                   Character to put
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPutChar( UARTn_Type* UARTx, uint8_t ch )
+{
+   HAL_UART_Transmit( UARTx, &ch, 1, BLOCKING );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get a character to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @return        character value that returned
+ *//*-------------------------------------------------------------------------*/
+uint8_t UARTGetChar( UARTn_Type* UARTx )
+{
+   uint8_t     tmp = 0;
+
+   HAL_UART_Receive( UARTx, &tmp, 1, BLOCKING );
+
+   return( tmp );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get a character to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     ch
+ *                   Character to get
+ * @return        if getting value, return '1'. if not, return '0'
+ *//*-------------------------------------------------------------------------*/
+uint8_t UARTGetCh( UARTn_Type* UARTx, uint8_t* ch )
+{
+   if( !( UARTx->LSR & UARTn_LSR_RDR ) )
+   {
+      *ch = 0;
+      return( 0 );
+   }
+   else
+   {
+      *ch = HAL_UART_ReceiveByte( UARTx );
+      return( 1 );
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a string to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     str
+ *                   String to put
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPuts( UARTn_Type* UARTx, const void* str )
+{
+   uint8_t*    s = ( uint8_t* )str;
+
+   while( *s )
+   {
+      UARTPutChar( UARTx, *s++ );
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a string to UART port and print new line
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     str
+ *                   String to put
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPuts_( UARTn_Type* UARTx, const void* str )
+{
+   UARTPuts( UARTx, str );
+   UARTPuts( UARTx, "\n\r" );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a decimal number to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     decnum
+ *                   Decimal number (8-bit long)
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPutDec( UARTn_Type* UARTx, uint8_t decnum )
+{
+   uint8_t     c1 = decnum % 10;
+   uint8_t     c2 = ( decnum / 10 ) % 10;
+   uint8_t     c3 = ( decnum / 100 ) % 10;
+
+   UARTPutChar( UARTx, '0' + c3 );
+   UARTPutChar( UARTx, '0' + c2 );
+   UARTPutChar( UARTx, '0' + c1 );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a decimal number to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     decnum
+ *                   Decimal number (8-bit long)
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPutDec16( UARTn_Type* UARTx, uint16_t decnum )
+{
+   uint8_t     c1 = decnum % 10;
+   uint8_t     c2 = ( decnum / 10 ) % 10;
+   uint8_t     c3 = ( decnum / 100 ) % 10;
+   uint8_t     c4 = ( decnum / 1000 ) % 10;
+   uint8_t     c5 = ( decnum / 10000 ) % 10;
+
+   UARTPutChar( UARTx, '0' + c5 );
+   UARTPutChar( UARTx, '0' + c4 );
+   UARTPutChar( UARTx, '0' + c3 );
+   UARTPutChar( UARTx, '0' + c2 );
+   UARTPutChar( UARTx, '0' + c1 );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a decimal number to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     decnum
+ *                   Decimal number (8-bit long)
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPutDec32( UARTn_Type* UARTx, uint32_t decnum )
+{
+   uint8_t     c1 = decnum % 10;
+   uint8_t     c2 = ( decnum / 10 ) % 10;
+   uint8_t     c3 = ( decnum / 100 ) % 10;
+   uint8_t     c4 = ( decnum / 1000 ) % 10;
+   uint8_t     c5 = ( decnum / 10000 ) % 10;
+   uint8_t     c6 = ( decnum / 100000 ) % 10;
+   uint8_t     c7 = ( decnum / 1000000 ) % 10;
+   uint8_t     c8 = ( decnum / 10000000 ) % 10;
+   uint8_t     c9 = ( decnum / 100000000 ) % 10;
+   uint8_t     c10 = ( decnum / 1000000000 ) % 10;
+
+   UARTPutChar( UARTx, '0' + c10 );
+   UARTPutChar( UARTx, '0' + c9 );
+   UARTPutChar( UARTx, '0' + c8 );
+   UARTPutChar( UARTx, '0' + c7 );
+   UARTPutChar( UARTx, '0' + c6 );
+   UARTPutChar( UARTx, '0' + c5 );
+   UARTPutChar( UARTx, '0' + c4 );
+   UARTPutChar( UARTx, '0' + c3 );
+   UARTPutChar( UARTx, '0' + c2 );
+   UARTPutChar( UARTx, '0' + c1 );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a hex number to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     hexnum
+ *                   Hex number (8-bit long)
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPutHex( UARTn_Type* UARTx, uint8_t hexnum )
+{
+   uint8_t     nibble, i;
+
+   i = 1;
+   do
+   {
+      nibble = ( hexnum >> ( 4 * i ) ) & 0x0F;
+      UARTPutChar( UARTx, ( nibble > 9 ) ? ( 'A' + nibble - 10 ) : ( '0' + nibble ) );
+   } while( i-- );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a hex number to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     hexnum
+ *                   Hex number (16-bit long)
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPutHex16( UARTn_Type* UARTx, uint16_t hexnum )
+{
+   uint8_t     nibble, i;
+
+   i = 3;
+   do
+   {
+      nibble = ( hexnum >> ( 4 * i ) ) & 0x0F;
+      UARTPutChar( UARTx, ( nibble > 9 ) ? ( 'A' + nibble - 10 ) : ( '0' + nibble ) );
+   } while( i-- );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Puts a hex number to UART port
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     hexnum
+ *                   Hex number (32-bit long)
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void UARTPutHex32( UARTn_Type* UARTx, uint32_t hexnum )
+{
+   uint8_t     nibble, i;
+
+   i = 7;
+   do
+   {
+      nibble = ( hexnum >> ( 4 * i ) ) & 0x0F;
+      UARTPutChar( UARTx, ( nibble > 9 ) ? ( 'A' + nibble - 10 ) : ( '0' + nibble ) );
+   } while( i-- );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         print function that supports format as same as printf() function of <stdio.h> library
+ * @param[in]     format
+ *                   formatted string to be print
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void cprintf( const char* format, ... )
+{
+   char        buffer[512 + 1];
+   va_list     vArgs;
+
+   va_start( vArgs, format );
+   vsprintf( ( char* )buffer, ( char const* )format, vArgs );
+   va_end( vArgs );
+
+   _DBG( buffer );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initializes Debug Framework through initializing UARTn
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void debug_frmwrk_init( void )
+{
+   UARTn_CFG_Type    UARTn_Config;
+
+#if (USED_UART_DEBUG_PORT == 0)
+
+   // Initialize UART0 pin connect
+   HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 5, ALTERN_FUNC );    // PB5   SWDIO    0: SEG36       1: RXD0        2: SWDIO       3: ----        4: ----
+   HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 5, AFSRx_AF1 );
+
+   HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 4, ALTERN_FUNC );    // PB4   SWCLK    0: SEG37       1: TXD0        2: SWCLK       3: ----        4: ----
+   HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 4, AFSRx_AF1 );
+
+#elif (USED_UART_DEBUG_PORT == 1)
+
+   // Initialize UART1 pin connect
+   HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 7, ALTERN_FUNC );    // PB7            0: SEG34       1: RXD1        2: ----        3: ----        4: ----
+   HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 7, AFSRx_AF1 );
+
+   HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 6, ALTERN_FUNC );    // PB6            0: SEG35       1: TXD1        2: ----        3: ----        4: ----
+   HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 6, AFSRx_AF1 );
+
+#endif
+
+   /* Initialize UART Configuration parameter structure to default state:
+    * Baudrate = 38400bps
+    * 8 data bit
+    * no parity
+    * 1 stop bit
+    */
+   HAL_UART_ConfigStructInit( &UARTn_Config );
+   UARTn_Config.Baudrate = 38400;
+
+   // Initialize DEBUG_UART_PORT peripheral with given to corresponding parameter
+   HAL_UART_Init( ( UARTn_Type* )DEBUG_UART_PORT, &UARTn_Config );
+
+   _db_msg  = UARTPuts;
+   _db_msg_ = UARTPuts_;
+   _db_char = UARTPutChar;
+   _db_hex = UARTPutHex;
+   _db_hex_16 = UARTPutHex16;
+   _db_hex_32 = UARTPutHex32;
+   _db_dec = UARTPutDec;
+   _db_dec_16 = UARTPutDec16;
+   _db_dec_32 = UARTPutDec32;
+   _db_get_char = UARTGetChar;
+   _db_get_ch = UARTGetCh;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get a character to UART port
+ * @param         None
+ * @return        character value that returned
+ *//*-------------------------------------------------------------------------*/
+uint8_t getstring( void )
+{
+   uint8_t     ch;
+
+   ch = UARTGetChar( ( UARTn_Type* )UART1 );
+
+   if( ch > 0 )
+   {
+      if( InCount < 80 )
+      {
+         if( InCount == 0 && ch < 0x20 )
+         {
+            InData[0] = 0;
+            return ch;
+         }
+
+         UARTPutChar( ( UARTn_Type* )UART1, ch );
+         if( ch == ASCII_BACKSPACE )
+         {
+            InCount--;
+            return ch;
+         }
+
+         if( ch == ASCII_CARRIAGE_RETURN )
+         {
+            InData[InCount] = 0;
+            InFlag = 1;
+            return ch;
+         }
+
+         InData[InCount++] = ch;
+      }
+   }
+
+   return 0;
+}
+
+#endif   /* _DEBUG_MSG */
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_fmc.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_fmc.c
new file mode 100644
index 0000000..b0ba493
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_fmc.c
@@ -0,0 +1,320 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_fmc.c
+* @brief    Contains all functions support for fmc firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_fmc.h"
+
+//******************************************************************************
+// Variable
+//******************************************************************************
+
+uint32_t    flash_id1_reg;
+uint32_t    flash_id2_reg;
+uint32_t    flash_addr_code0;
+uint32_t    flash_addr_code1;
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Entry of Flash Memory Control
+ * @return        None
+ * @details       This function sets flash IDs for erase/write
+ *                The HIRC should be enabled before flash functions. So, Do enable the HIRC if disabled
+ *                The LVR should be enabled and set over 2.28V level before flash functions. So, Do enable the LVR and Set 2.28V level over if disabled
+ *                The global interrupt should be diabled by s/w. So, Diable global interrupt
+ *//*-------------------------------------------------------------------------*/
+void HAL_FMC_FlashEntry( void )
+{
+   uint32_t    WDT_WINDR;
+
+   flash_id1_reg = FLASH_ID1 ^ FLASH_IDXOR;
+   flash_id2_reg = FLASH_ID2 ^ FLASH_IDXOR;
+   flash_addr_code0 = FLASH_ADDR_CD0 ^ FLASH_ADDR_CDXOR;
+   SCUCG->PPCLKEN2_b.FMCLKE = 1;       // Enable Flash Memory Control Clock
+#if 0
+   SCUCG->CLKSRCR_b.HIRCEN = 1;        // Enable HIRC
+   NOP();
+   NOP();
+   NOP();
+
+   SCULV->LVRCR_b.LVREN = 0x00;        // Enable LVR, the Level should be set 2.28V over in CONF_LVRCNFIG register of configure option page 1
+   SCUCC->NMISRCR_b.NMICON = 0;        // Disable NMI
+#endif
+   WDT_WINDR = WDT->WINDR;
+   if( WDT->CNT < WDT_WINDR )
+   {
+      WDT->CNTR_b.CNTR = 0x6a;         // Reload WDT Counter if WDT->CNT < WDT_WINDR
+   }
+   DI();                               // Disable global interrupt
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Exit of Flash Memory Control
+ * @return        None
+ * @details       This function clears flash IDs for erase/write
+ *//*-------------------------------------------------------------------------*/
+void HAL_FMC_FlashExit( void )
+{
+   flash_id1_reg = 0;
+   flash_id2_reg = 0;
+   flash_addr_code0 = 0;
+   flash_addr_code1 = 0;
+   SCUCG->PPCLKEN2_b.FMCLKE = 0;       // Disable Flash Memory Control Clock
+   EI();                               // Enable global interrupt
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Flash Page Erase/Write and Bulk(Chip) Erase
+ * @param[in]     u32FncSel
+ *                   Select Flash Function
+ *                   -  FLASH_BULK_ERASE
+ *                   -  FLASH_PAGE_ERASE
+ *                   -  FLASH_PAGE_WRITE
+ * @param[in]     u32Addr
+ *                   Address of erase/write
+ *                   -  Flash Memory:  0x00000000 ~ 0x0000FFFF
+ *                   -  Configuration Option Area Page 1 ~ 3
+ * @param[in]     u32Buf
+ *                   Write Data
+ * @return        None
+ * @details       This function erases/writes flash memory and configure option area 1 to 3
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_FMC_FlashFunction( uint32_t u32FncSel, uint32_t u32Addr, uint32_t* u32Buf )
+{
+   uint32_t                i;
+   volatile uint32_t*      pagebuffer;
+
+   pagebuffer = &FMC->PAGEBUF;
+   FMC->ADR = flash_addr_code0 ^ FLASH_ADDR_CDXOR;    // Write 0x5FFFFFFF to FMC_ADR during the register is equal to 0x5FFFFF80;
+   FMC->IDR1 = flash_id1_reg ^ FLASH_IDXOR;           // Identification Value 0
+   FMC->IDR2 = flash_id2_reg ^ FLASH_IDXOR;           // Identification Value 1
+
+   FMC->CR = FLASH_CLR_PAGEBUF;                       // Clear page buffer
+   for( i = 0 ; i < SECTOR_SIZE_BYTE / 4 ; i++ )
+   {
+      if( u32FncSel == FLASH_PAGE_WRITE )
+      {
+         *pagebuffer++ = *u32Buf++;                   // To page write
+      }
+      else if( ( u32FncSel == FLASH_PAGE_ERASE ) || ( u32FncSel == FLASH_BULK_ERASE ) )
+      {
+         *pagebuffer++ = 0xFFFFFFFF;                  // To page or bulk erase
+      }
+      else
+      {
+         return FLASH_PGM_FAIL;
+      }
+   }
+
+   if( ( u32FncSel == FLASH_PAGE_WRITE ) || ( u32FncSel == FLASH_PAGE_ERASE ) )  // Page Erase/Write
+   {
+      if( u32Addr < FLASH_START_ADDR )
+      {
+         FMC->ADR = u32Addr + FLASH_START_ADDR;          // Flash Page Address to be erased or written
+      }
+      else
+      {
+         FMC->ADR = u32Addr;
+      }
+   }
+   else if( u32FncSel == FLASH_BULK_ERASE )              // Bulk(Chip) Erase
+   {
+      FMC->BCR = FLASH_CHIPER_WOPT;                      // For bulk erase including Configure Option Page 1/2/3
+      FMC->ADR = flash_addr_code1 ^ FLASH_ADDR_CDXOR;    // Identification Address for bulk erase
+   }
+   else
+   {
+      return FLASH_PGM_FAIL;
+   }
+
+   if( FMC->IDR1 != FLASH_ID1 )
+   {
+      return FLASH_PGM_FAIL;        // Check whether ID0 is ok or not
+   }
+   if( FMC->IDR2 != FLASH_ID2 )
+   {
+      return FLASH_PGM_FAIL;        // Check whether ID1 is ok or not
+   }
+
+   if( ( u32FncSel == FLASH_PAGE_WRITE ) || ( u32FncSel == FLASH_PAGE_ERASE ) )     // Page Erase/Write
+   {
+      if( ( FMC->ADR >= FLASH_START_ADDR ) && ( FMC->ADR <= FLASH_END_ADDR ) )
+      {
+         FMC->CR = FLASH_MEM_PGM_CODE | ( u32FncSel & 0x0000000F );     // Start flash page erase/write from here
+      }
+      else if( ( FMC->ADR >= CFG_OPT_SADDR ) && ( FMC->ADR <= CFG_OPT_EADDR ) )
+      {
+         FMC->CR = FLASH_OPT_PGM_CODE | ( u32FncSel & 0x0000000F );     // Start configure page erase/write from here
+      }
+      else
+      {
+         return FLASH_PGM_FAIL;
+      }
+   }
+   else if( u32FncSel == FLASH_BULK_ERASE )  // Bulk(Chip) Erase
+   {
+      if( FMC->ADR != FLASH_ADDR_CD1 )
+      {
+         return FLASH_PGM_FAIL;
+      }
+      FMC->CR = FLASH_BULK_CODE;             // Start bulk(chip) erase from here
+   }
+   else
+   {
+      return FLASH_PGM_FAIL;
+   }
+
+   while( FMC->CR_b.FMBUSY ) {}              // Check whether the busy bit. If time over, goes out with error.
+   if( !FMC->ERFLAG_b.FMOPFLAG )
+   {
+      return FLASH_PGM_GOOD;     // Success
+   }
+
+   return FLASH_PGM_FAIL;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Flash Bulk(Chip) Erase Function
+ * @param[in]     u32UserId
+ *                   Check value for real chip erase       User ID to check flash memory bulk erase
+ * @return        Result of FMC
+ *                   -  Success:    0
+ *                   -  Fail:       9
+ * @details       This function erases flash memory area with configure option area 1 to 3
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_FMC_BulkErase( uint32_t u32UserId )
+{
+   uint32_t    result;
+
+   HAL_FMC_FlashEntry();
+   flash_addr_code1 = FLASH_ADDR_CD1 ^ FLASH_ADDR_CDXOR;
+   if( u32UserId == 0x90E832CF )                         // Ex) 0x90E832CF, The user ID may be changed by programmer
+   {
+      result = HAL_FMC_FlashFunction( FLASH_BULK_ERASE, 0, 0 );
+   }
+   else
+   {
+      result = FLASH_PGM_FAIL;
+   }
+
+   if( result )                  // If fail
+   {
+      FMC->ERFLAG = 0x03uL;      // Clear FMC related flag
+   }
+   HAL_FMC_FlashExit();
+
+   return result;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Flash Page Erase Function
+ * @param[in]     u32UserId
+ *                   Check value for real page erase       User ID to check flash memory page erase
+ * @param[in]     u32Addr
+ *                   Target Address
+ *                   -  Flash Memory:  0x00000000 ~ 0x0000FFFF
+ *                   -  Configuration Option Area Page 1 ~ 3
+ * @return        Result of FMC
+ *                   -  Success:    0
+ *                   -  Fail:       9
+ * @details       This function erases flash memory area and configure option area
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_FMC_PageErase( uint32_t u32UserId, uint32_t u32Addr )
+{
+   uint32_t    result;
+
+   HAL_FMC_FlashEntry();
+   if( u32UserId == 0xA901358F )    // Ex) 0xA901358F, The user ID may be changed by programmer
+   {
+      result = HAL_FMC_FlashFunction( FLASH_PAGE_ERASE, u32Addr, 0 );
+   }
+   else
+   {
+      result = FLASH_PGM_FAIL;
+   }
+
+   if( result )                     // If fail
+   {
+      FMC->ERFLAG = 0x03uL;         // Clear FMC related flag
+   }
+   HAL_FMC_FlashExit();
+
+   return result;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Flash Page Write Function
+ * @param[in]     u32UserId
+ *                   Check value for real page write       User ID to check flash memory page write
+ * @param[in]     u32Addr
+ *                   Target Address
+ *                   -  Flash Memory:  0x00000000 ~ 0x0000FFFF
+ *                   -  Configuration Option Area Page 1 ~ 3
+ * @param[in]     u32Buf
+ *                   Write Data
+ * @return        Result of FMC
+ *                   -  Success:    0
+ *                   -  Fail:       9
+ * @details       This function writes flash memory area and configure option area
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_FMC_PageWrite( uint32_t u32UserId, uint32_t u32Addr, uint32_t* u32Buf )
+{
+   uint32_t    result;
+
+   HAL_FMC_FlashEntry();
+   if( u32UserId == 0x4F17DC86 )       // Ex) 0x4F17DC86, The user ID may be changed by programmer
+   {
+      result = HAL_FMC_FlashFunction( FLASH_PAGE_WRITE, u32Addr, u32Buf );
+   }
+   else
+   {
+      result = FLASH_PGM_FAIL;
+   }
+
+   if( result )                        // If fail
+   {
+      FMC->ERFLAG = 0x03uL;            // Clear FMC related flag
+   }
+   HAL_FMC_FlashExit();
+
+   return result;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_i2cn.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_i2cn.c
new file mode 100644
index 0000000..0af1551
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_i2cn.c
@@ -0,0 +1,1110 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_i2cn.c
+* @brief    Contains all functions support for i2cn firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+
+#include "A31G12x_hal_i2cn.h"
+#include "A31G12x_hal_scu.h"
+
+//******************************************************************************
+// Constant
+//******************************************************************************
+
+#define I2Cn_BLOCKING_TIMEOUT    (0x000FFFFFUL)
+#define I2Cn_MAX                 3
+
+//******************************************************************************
+// Type
+//******************************************************************************
+
+/**   I2Cn device configuration structure type */
+typedef struct
+{
+   union
+   {
+      I2Cn_M_SETUP_Type  txrx_setup_master;      /**<  Transmission setup */
+      I2Cn_S_SETUP_Type  txrx_setup_slave;       /**<  Transmission setup */
+   };
+   int32_t     dir;        /* Current direction phase, 0 - write, 1 - read */
+} I2Cn_CFG_Type;
+
+//******************************************************************************
+// Variable
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         I2Cn driver data
+ *//*-------------------------------------------------------------------------*/
+
+static I2Cn_CFG_Type    i2cdat[I2Cn_MAX];
+static Bool             I2Cn_MasterComplete[I2Cn_MAX];
+static Bool             I2Cn_SlaveComplete[I2Cn_MAX];
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Convert from I2C peripheral to number
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @return        I2C number or error code, could be:
+ *                   -  0:       I2C0
+ *                   -  1:       I2C1
+ *                   -  2:       I2C2
+ *                   -  (-1):    Error
+ *//*-------------------------------------------------------------------------*/
+int32_t I2Cn_getNum( I2Cn_Type* I2Cx )
+{
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C0 )
+   {
+      return 0;
+   }
+#endif
+
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C1 )
+   {
+      return 1;
+   }
+#endif
+
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C2 )
+   {
+      return 2;
+   }
+#endif
+
+   return -1;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         wait and return status in master mode
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @return        Status
+ *//*-------------------------------------------------------------------------*/
+int32_t I2Cn_MWait( I2Cn_Type* I2Cx )
+{
+   uint32_t    tmp;
+   int32_t     ret = 0;
+
+   while( 1 )     // Interrupt Status Check
+   {
+      if( ( I2Cx->CR & I2Cn_CR_I2CnIFLAG_Msk ) != 0 )
+      {
+         break;
+      }
+   }
+
+   tmp = I2Cx->ST;
+   I2Cx->ST = 0xFF;
+
+   switch( tmp )
+   {
+      // Transmitter mode
+      case 0x87:
+         ret = TRANS_MODE;
+         break;
+
+      // Receive mode
+      case 0x85:
+         ret = RECEIVE_MODE;
+         break;
+
+      // Transed Data
+      case 0x47:
+         ret = TRANS_DATA;
+         break;
+
+      // Received Data
+      case 0x44:
+      case 0x45:
+         ret = RECEIVE_DATA;
+         break;
+
+      default:
+         if( ( tmp ) & 0x08 )
+         {
+            ret = LOST_BUS;   // lost
+         }
+         else if( ( tmp ) & 0x20 )
+         {
+            ret = STOP_DECT;   // stop
+         }
+         else
+         {
+            ret = -1;
+         }
+         break;
+   }
+
+   return ret;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         wait and return status in slave mode
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @return        Status
+ *//*-------------------------------------------------------------------------*/
+int32_t I2Cn_SWait( I2Cn_Type* I2Cx )
+{
+   uint32_t    tmp;
+   int32_t     ret = 0;
+
+   while( 1 )     // Interrupt Status Check
+   {
+      if( ( I2Cx->CR & I2Cn_CR_I2CnIFLAG_Msk ) != 0 )
+      {
+         break;
+      }
+   }
+
+   tmp = I2Cx->ST;
+   I2Cx->ST = 0xFF;
+
+   switch( tmp )
+   {
+      // Receive mode
+      case 0x15:
+      case 0x95:
+         ret = RECEIVE_MODE;
+         break;
+
+      // Transmitter mode
+      case 0x17:
+      case 0x97:
+         ret = TRANS_MODE;
+         break;
+
+      // Received Data
+      case 0x45:
+         ret = RECEIVE_DATA;
+         break;
+
+      // Transed Data
+      case 0x47:
+         ret = TRANS_DATA;
+         break;
+      default:
+         if( tmp & 0x08 )
+         {
+            ret = LOST_BUS;   // lost
+         }
+         else if( tmp & 0x20 )
+         {
+            ret = STOP_DECT;   // stop
+         }
+         else
+         {
+            ret = -1;
+         }
+         break;
+   }
+
+   return ret;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the I2Cn peripheral with the specified parameters.
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     clockrate
+ *                   Target Clock Rate (Hz)
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_I2C_Init( I2Cn_Type* I2Cx, uint32_t clockrate )
+{
+   /* Check I2C handle */
+   if( I2Cx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C0 )
+   {
+      /* Set up clock for I2C0 module */
+      SCUCG->PPCLKEN2_b.I2C0CLKE = 1;
+      HAL_SCU_Peripheral_SetReset2( 1 << 6 );
+   }
+#endif
+
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C1 )
+   {
+      /* Set up clock for I2C1 module */
+      SCUCG->PPCLKEN2_b.I2C1CLKE = 1;
+      HAL_SCU_Peripheral_SetReset2( 1 << 7 );
+   }
+#endif
+
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C2 )
+   {
+      /* Set up clock for I2C2 module */
+      SCUCG->PPCLKEN2_b.I2C2CLKE = 1;
+      HAL_SCU_Peripheral_SetReset2( 1 << 8 );
+   }
+#endif
+
+   I2Cx->CR_b.I2CnEN = 1;     // I2C Block Active
+   I2Cx->CR_b.I2CnIEN = 1;    // I2C Interrupt Enable
+
+
+   I2Cx->SCLR = ( SystemPeriClock / clockrate - 4 ) / 8;    // freq = PCLK / ((4*SCLL+2) + (4*SCLH+2))
+   I2Cx->SCHR = ( SystemPeriClock / clockrate - 4 ) / 8;    // ex) 100k = 10M / ((4*12+2) + (4*12+2)), if PCLK : 10MHz
+
+
+
+
+   I2Cx->SDHR = 1;            // default value 1
+
+   I2Cx->CR_b.ACKnEN = 1;     // ACK Signal Enable
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Deinitialize the I2Cn peripheral registers to their default reset values.
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_I2C_DeInit( I2Cn_Type* I2Cx )
+{
+   /* Check I2C handle */
+   if( I2Cx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   /* Disable I2C control */
+   I2Cx->CR = 0;     // I2C Block Disable
+
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C0 )
+   {
+      /* Set up clock for I2C0 module */
+      SCUCG->PPCLKEN2_b.I2C0CLKE = 0;
+   }
+#endif
+
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C1 )
+   {
+      /* Set up clock for I2C1 module */
+      SCUCG->PPCLKEN2_b.I2C1CLKE = 0;
+   }
+#endif
+
+#if 1    // supported
+   if( I2Cx == ( I2Cn_Type* )I2C2 )
+   {
+      /* Set up clock for I2C2 module */
+      SCUCG->PPCLKEN2_b.I2C2CLKE = 0;
+   }
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable/Disable interrupt for I2C peripheral
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_I2C_ConfigInterrupt( I2Cn_Type* I2Cx, Bool NewState )
+{
+   /* Check I2C handle */
+   if( I2Cx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   if( NewState )
+   {
+#if 1    // supported
+      if( I2Cx == ( I2Cn_Type* )I2C0 )
+      {
+         NVIC_ClearPendingIRQ( I2C0_IRQn );
+         NVIC_EnableIRQ( I2C0_IRQn );
+      }
+#endif
+
+#if 1    // supported
+      if( I2Cx == ( I2Cn_Type* )I2C1 )
+      {
+         NVIC_ClearPendingIRQ( I2C1_IRQn );
+         NVIC_EnableIRQ( I2C1_IRQn );
+      }
+#endif
+
+#if 1    // supported
+      if( I2Cx == ( I2Cn_Type* )I2C2 )
+      {
+         NVIC_ClearPendingIRQ( I2C2_IRQn );
+         NVIC_EnableIRQ( I2C2_IRQn );
+      }
+#endif
+   }
+   else
+   {
+#if 1    // supported
+      if( I2Cx == ( I2Cn_Type* )I2C0 )
+      {
+         NVIC_DisableIRQ( I2C0_IRQn );
+      }
+#endif
+
+#if 1    // supported
+      if( I2Cx == ( I2Cn_Type* )I2C1 )
+      {
+         NVIC_DisableIRQ( I2C1_IRQn );
+      }
+#endif
+
+#if 1    // supported
+      if( I2Cx == ( I2Cn_Type* )I2C2 )
+      {
+         NVIC_DisableIRQ( I2C2_IRQn );
+      }
+#endif
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Own slave address in I2C peripheral
+ *                corresponding to parameter specified in OwnSlaveAddrConfigStruct.
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     SlaveAddr_7bit
+ *                   own slave address
+ * @param[in]     GeneralCallState
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_I2C_Slave_SetAddress1( I2Cn_Type* I2Cx, uint8_t SlaveAddr_7bit, uint8_t GeneralCallState )
+{
+   /* Check I2C handle */
+   if( I2Cx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   I2Cx->SAR1 = ( ( ( uint32_t )( SlaveAddr_7bit << 1 ) ) | ( ( GeneralCallState == ENABLE ) ? 0x01 : 0x00 ) ) & I2Cn_SLA_BITMASK;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Own slave address in I2C peripheral
+ *                corresponding to parameter specified in OwnSlaveAddrConfigStruct.
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     SlaveAddr_7bit
+ *                   own slave address
+ * @param[in]     GeneralCallState
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_I2C_Slave_SetAddress2( I2Cn_Type* I2Cx, uint8_t SlaveAddr_7bit, uint8_t GeneralCallState )
+{
+   /* Check I2C handle */
+   if( I2Cx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   I2Cx->SAR2 = ( ( ( uint32_t )( SlaveAddr_7bit << 1 ) ) | ( ( GeneralCallState == ENABLE ) ? 0x01 : 0x00 ) ) & I2Cn_SLA_BITMASK;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Status of Master Transfer
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @return        Status of Master Transfer
+ *                   -  TRUE, FALSE
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_I2C_Master_GetState( I2Cn_Type* I2Cx )
+{
+   uint32_t    retval, tmp;
+
+   tmp = I2Cn_getNum( I2Cx );
+   retval = I2Cn_MasterComplete[tmp];
+   I2Cn_MasterComplete[tmp] = FALSE;
+
+   return retval;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Status of Slave Transfer
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @return        Status of Slave Transfer
+ *                   -  TRUE, FALSE
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_I2C_Slave_GetState( I2Cn_Type* I2Cx )
+{
+   uint32_t    retval, tmp;
+
+   tmp = I2Cn_getNum( I2Cx );
+   retval = I2Cn_SlaveComplete[tmp];
+   I2Cn_SlaveComplete[tmp] = FALSE;
+
+   return retval;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         General Master Interrupt handler for I2C peripheral
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_I2C_Master_IRQHandler_IT( I2Cn_Type* I2Cx )
+{
+   int32_t                 tmp;
+   I2Cn_M_SETUP_Type*      txrx_setup;
+   uint32_t                status;
+
+   /* Check I2C handle */
+   if( I2Cx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   tmp = I2Cn_getNum( I2Cx );
+   txrx_setup = ( I2Cn_M_SETUP_Type* )&i2cdat[tmp].txrx_setup_master;
+
+   status = I2Cx->ST;
+
+   switch( status )
+   {
+      case 0x87: // transmit mode - addr ACK
+         if( txrx_setup->tx_count < txrx_setup->tx_length )
+         {
+            I2Cx->DR = txrx_setup->tx_data[txrx_setup->tx_count];
+            txrx_setup->tx_count++;
+         }
+         else
+         {
+            I2Cx->CR = 0
+                       | ( 1 << 7 )    // Enable I2C Block
+                       | ( 1 << 5 )    // Interrupt Enable
+                       | ( 1 << 1 );   // STOP
+         }
+         break;
+
+      case 0x47: // transmit mode - data ACK
+         if( txrx_setup->tx_count < txrx_setup->tx_length )
+         {
+            I2Cx->DR = txrx_setup->tx_data[txrx_setup->tx_count];
+            txrx_setup->tx_count++;
+         }
+         else
+         {
+            if( txrx_setup->rx_count < txrx_setup->rx_length )
+            {
+               // load slave address and rw flag (SLA+RnW)
+               I2Cx->DR = ( ( txrx_setup->sl_addr7bit << 1 ) | 0x01 );
+
+               // generate start condition
+               I2Cx->CR |= ( 1 << 0 );    // reSTART
+            }
+            else
+            {
+               I2Cx->CR = 0
+                          | ( 1 << 7 )    // Enable I2C Block
+                          | ( 1 << 5 )    // Interrupt Enable
+                          | ( 1 << 1 );   // STOP
+            }
+         }
+         break;
+
+      case 0x85: // receive mode - addr ACK
+         if( txrx_setup->rx_count < txrx_setup->rx_length )
+         {
+            if( ( txrx_setup->rx_length > 1 ) && ( txrx_setup->rx_count < ( txrx_setup->rx_length - 1 ) ) )
+            {
+               NOP();
+            }
+            else
+            {
+               I2Cx->CR_b.ACKnEN = 0;     // disable ACKEN
+            }
+         }
+         else
+         {
+            I2Cx->CR = 0
+                       | ( 1 << 7 )    // Enable I2C Block
+                       | ( 1 << 5 )    // Interrupt Enable
+                       | ( 1 << 1 );   // STOP
+         }
+         break;
+
+      case 0x45: // receive mode - data ACK
+         if( txrx_setup->rx_count < txrx_setup->rx_length )
+         {
+            txrx_setup->rx_data[txrx_setup->rx_count] = I2Cx->DR;
+            txrx_setup->rx_count++;
+
+            if( ( txrx_setup->rx_length > 1 ) && ( txrx_setup->rx_count < ( txrx_setup->rx_length - 1 ) ) )
+            {
+               NOP();
+            }
+            else
+            {
+               I2Cx->CR_b.ACKnEN = 0;     // disable ACKEN
+            }
+         }
+         break;
+
+      case 0x44: // receive mode - data NOACK
+         if( txrx_setup->rx_count < txrx_setup->rx_length )
+         {
+            txrx_setup->rx_data[txrx_setup->rx_count] = I2Cx->DR;
+            txrx_setup->rx_count++;
+
+            I2Cx->CR = 0
+                       | ( 1 << 7 )    // Enable I2C Block
+                       | ( 1 << 5 )    // Interrupt Enable
+                       | ( 1 << 1 );   // STOP
+         }
+         break;
+
+      case 0x20: // receive mode
+      case 0x22: // transmit mode - stop receive
+         I2Cx->CR = 0
+                    | ( 1 << 7 )    // Enable I2C Block
+                    | ( 1 << 5 )    // Interrupt Enable
+                    | ( 1 << 3 );   // ACK Signal Enable
+         goto s_int_end;
+
+      default:
+         if( status & 0x08 )     // mastership lost
+         {
+
+         }
+         break;
+   }
+
+   I2Cx->ST = 0xff;     // flag clear and SCL go to HIGH
+   return HAL_OK;
+
+s_int_end:
+
+   I2Cx->ST = 0xff;     // flag clear and SCL go to HIGH
+
+   // Disable interrupt
+   HAL_I2C_ConfigInterrupt( I2Cx, FALSE );
+
+   I2Cn_MasterComplete[tmp] = TRUE;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         General Slave Interrupt handler for I2C peripheral
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_I2C_Slave_IRQHandler_IT( I2Cn_Type* I2Cx )
+{
+   int32_t                 tmp;
+   I2Cn_S_SETUP_Type*      txrx_setup;
+   uint32_t                status;
+
+   /* Check I2C handle */
+   if( I2Cx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   tmp = I2Cn_getNum( I2Cx );
+   txrx_setup = ( I2Cn_S_SETUP_Type* )&i2cdat[tmp].txrx_setup_slave;
+
+   status = I2Cx->ST;
+   switch( status )
+   {
+      case 0x15: // receive mode - slave select + ACK
+      case 0x45: // receive mode - data ACK
+         if( ( txrx_setup->rx_count < txrx_setup->rx_length ) && ( txrx_setup->rx_data != NULL ) )
+         {
+            txrx_setup->rx_data[txrx_setup->rx_count] = I2Cx->DR;
+            txrx_setup->rx_count++;
+         }
+         break;
+
+      case 0x20: // receive mode
+      case 0x22: // transmit mode - stop receive
+         goto s_int_end;
+
+      case 0x17: // transmit mode - slave select + ACK
+      case 0x46: // transmit mode - data NOACK
+      case 0x47: // transmit mode - data ACK
+         if( ( txrx_setup->tx_count < txrx_setup->tx_length ) && ( txrx_setup->tx_data != NULL ) )
+         {
+            I2Cx->DR = txrx_setup->tx_data[txrx_setup->tx_count];
+            txrx_setup->tx_count++;
+         }
+         break;
+   }
+
+   I2Cx->ST = 0xff;     // flag clear and SCL go to HIGH
+   return HAL_OK;
+
+s_int_end:
+
+   I2Cx->ST = 0xff;     // flag clear and SCL go to HIGH
+
+   // Disable interrupt
+   HAL_I2C_ConfigInterrupt( I2Cx, FALSE );
+
+   I2Cn_SlaveComplete[tmp] = TRUE;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Transmit and Receive data in master mode
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     TransferCfg
+ *                   Pointer to a I2Cn_M_SETUP_Type structure
+ *                   that contains specified information about the configuration for master transfer.
+ * @param[in]     Opt
+ *                   I2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return        Result
+ *                   -  SUCCESS, ERROR
+ *//*-------------------------------------------------------------------------*/
+Status HAL_I2C_MasterTransferData( I2Cn_Type* I2Cx, I2Cn_M_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt )
+{
+   int32_t     tmp;
+   uint32_t    exitflag;
+   int32_t     Ret;
+
+   // Reset I2C setup value to default state
+   TransferCfg->tx_count = 0;
+   TransferCfg->rx_count = 0;
+
+   while( I2Cx->ST & 0x04 );     // busy check
+
+   if( Opt == I2Cn_TRANSFER_POLLING )
+   {
+      // init count
+      TransferCfg->tx_count = 0;
+      TransferCfg->rx_count = 0;
+
+      // tx transfer
+      if( TransferCfg->tx_count < TransferCfg->tx_length )
+      {
+         // generate start condition
+         I2Cx->DR = ( TransferCfg->sl_addr7bit << 1 );      // load slave address and write flag (SLA+RnW)
+         I2Cx->CR |= ( 1 << 0 );    // START
+         Ret = I2Cn_MWait( I2Cx );
+         if( ( Ret != TRANS_MODE ) )
+         {
+            // generate stop condition
+            I2Cx->CR |= ( 1 << 1 );    // STOP
+            I2Cn_MWait( I2Cx );
+            I2Cx->ST = 0xFF;
+            I2Cx->CR = 0
+                       | ( 1 << 7 )    // I2C Block Enable
+                       | ( 1 << 5 )    // Interrupt Enable
+                       | ( 1 << 3 );   // ACK Signal Enable
+
+            // return
+            return ERROR;
+         }
+
+         // tx data
+         exitflag = 1;
+         while( exitflag )
+         {
+            if( TransferCfg->tx_count < TransferCfg->tx_length )
+            {
+               // tx byte
+               I2Cx->DR = TransferCfg->tx_data[TransferCfg->tx_count];
+               TransferCfg->tx_count++;
+               I2Cx->ST = 0xFF;
+               Ret = I2Cn_MWait( I2Cx );
+               if( ( Ret != TRANS_DATA ) )
+               {
+                  // generate stop condition
+                  I2Cx->CR |= ( 1 << 1 );    // STOP
+                  I2Cn_MWait( I2Cx );
+                  I2Cx->ST = 0xFF;
+                  I2Cx->CR = 0
+                             | ( 1 << 7 )    // I2C Block Enable
+                             | ( 1 << 5 )    // Interrupt Enable
+                             | ( 1 << 3 );   // ACK Signal Enable
+
+                  // return
+                  return ERROR;
+               }
+            }
+            else
+            {
+               if( TransferCfg->rx_count >= TransferCfg->rx_length )
+               {
+                  // generate stop condition
+                  I2Cx->CR |= ( 1 << 1 );    // STOP
+                  I2Cx->ST = 0xFF;
+                  I2Cn_MWait( I2Cx );
+                  I2Cx->ST = 0xFF;
+                  I2Cx->CR = 0
+                             | ( 1 << 7 )    // I2C Block Enable
+                             | ( 1 << 5 )    // Interrupt Enable
+                             | ( 1 << 3 );   // ACK Signal Enable
+
+                  // return
+                  return SUCCESS;
+               }
+               else
+               {
+                  exitflag = 0;
+               }
+            }
+         }
+      }
+
+      // rx transfer
+      if( TransferCfg->rx_count < TransferCfg->rx_length )
+      {
+         // generate start condition
+         I2Cx->DR = ( ( TransferCfg->sl_addr7bit << 1 ) | 0x01 );    // load slave address and read flag (SLA+RnW)
+         I2Cx->CR |= ( 1 << 0 );    // START
+         I2Cx->ST = 0xFF;
+         Ret = I2Cn_MWait( I2Cx );
+         if( ( Ret != RECEIVE_MODE ) )
+         {
+            // generate stop condition
+            I2Cx->CR |= ( 1 << 1 );    // STOP
+            I2Cn_MWait( I2Cx );
+            I2Cx->ST = 0xFF;
+            I2Cx->CR = 0
+                       | ( 1 << 7 )    // I2C Block Enable
+                       | ( 1 << 5 )    // Interrupt Enable
+                       | ( 1 << 3 );   // ACK Signal Enable
+
+            // return
+            return ERROR;
+         }
+
+         // rx data
+         exitflag = 1;
+         while( exitflag )
+         {
+            if( ( TransferCfg->rx_length > 1 ) && ( TransferCfg->rx_count < ( TransferCfg->rx_length - 1 ) ) )
+            {
+               // rx byte
+               I2Cx->ST = 0xFF;
+               Ret = I2Cn_MWait( I2Cx );
+               if( ( Ret != RECEIVE_DATA ) )
+               {
+                  // generate stop condition
+                  I2Cx->CR |= ( 1 << 1 );    // STOP
+                  I2Cn_MWait( I2Cx );
+                  I2Cx->ST = 0xFF;
+                  I2Cx->CR = 0
+                             | ( 1 << 7 )    // I2C Block Enable
+                             | ( 1 << 5 )    // Interrupt Enable
+                             | ( 1 << 3 );   // ACK Signal Enable
+
+                  // return
+                  return ERROR;
+               }
+            }
+            else    // the next byte is the last byte, send NACK instead.
+            {
+               // generate nack
+               I2Cx->CR &= ~( 1 << 3 );   // ACK Signal Disable
+
+               // rx byte
+               I2Cx->ST = 0xFF;
+               Ret = I2Cn_MWait( I2Cx );
+               if( ( Ret != RECEIVE_DATA ) )
+               {
+                  // generate stop condition
+                  I2Cx->CR |= ( 1 << 1 );    // STOP
+                  I2Cn_MWait( I2Cx );
+                  I2Cx->CR = 0
+                             | ( 1 << 7 )    // I2C Block Enable
+                             | ( 1 << 5 )    // Interrupt Enable
+                             | ( 1 << 3 );   // ACK Signal Enable
+
+                  // return
+                  return ERROR;
+               }
+            }
+            TransferCfg->rx_data[TransferCfg->rx_count] = I2Cx->DR;
+            TransferCfg->rx_count++;
+            if( TransferCfg->rx_count == TransferCfg->rx_length )
+            {
+               exitflag = 0;
+               // commented by kth  return SUCCESS;
+            }
+         }
+
+         // generate stop condition
+         I2Cx->CR |= ( 1 << 1 );    // STOP
+         I2Cx->ST = 0xFF;
+         I2Cn_MWait( I2Cx );
+         I2Cx->ST = 0xFF;
+         I2Cx->CR = 0
+                    | ( 1 << 7 )    // I2C Block Enable
+                    | ( 1 << 5 )    // Interrupt Enable
+                    | ( 1 << 3 );   // ACK Signal Enable
+
+         // return
+         return SUCCESS;
+      }
+   }
+   else if( Opt == I2Cn_TRANSFER_INTERRUPT )
+   {
+      // clear flag
+      tmp = I2Cn_getNum( I2Cx );
+      I2Cn_MasterComplete[tmp] = FALSE;
+
+      // Setup tx_rx data, callback and interrupt handler
+      i2cdat[tmp].txrx_setup_master = *TransferCfg;
+
+      // Set direction phase, write first
+      i2cdat[tmp].dir = 0;
+
+      // enable interrupt
+      HAL_I2C_ConfigInterrupt( I2Cx, TRUE );
+
+      // generate start condition
+      if( TransferCfg->tx_count < TransferCfg->tx_length )
+      {
+         I2Cx->DR = ( TransferCfg->sl_addr7bit << 1 );               // load slave address and write flag (SLA+RnW)
+      }
+      else if( TransferCfg->rx_count < TransferCfg->rx_length )
+      {
+         I2Cx->DR = ( ( TransferCfg->sl_addr7bit << 1 ) | 0x01 );    // load slave address and read flag (SLA+RnW)
+      }
+      I2Cx->CR |= ( 1 << 0 );    // START
+
+      // return
+      return SUCCESS;
+   }
+
+   // return
+   return ERROR;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Receive and Transmit data in slave mode
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     TransferCfg
+ *                   Pointer to a I2Cn_S_SETUP_Type structure
+ *                   that contains specified information about the configuration for master transfer.
+ * @param[in]     Opt
+ *                   I2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return        Result
+ *                   -  SUCCESS, ERROR
+ *//*-------------------------------------------------------------------------*/
+Status HAL_I2C_SlaveTransferData( I2Cn_Type* I2Cx, I2Cn_S_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt )
+{
+   int32_t     tmp;
+   int32_t     Ret;
+
+   // Reset I2C setup value to default state
+   TransferCfg->tx_count = 0;
+   TransferCfg->rx_count = 0;
+
+   // Polling option
+   if( Opt == I2Cn_TRANSFER_POLLING )
+   {
+      while( 1 )
+      {
+         Ret = I2Cn_SWait( I2Cx );      // Start
+         switch( Ret )
+         {
+            case RECEIVE_MODE:
+            case RECEIVE_DATA:
+               if( ( TransferCfg->rx_count < TransferCfg->rx_length ) && ( TransferCfg->rx_data != NULL ) )
+               {
+                  TransferCfg->rx_data[TransferCfg->rx_count] = I2Cx->DR;
+                  TransferCfg->rx_count++;
+               }
+               break;
+            case TRANS_MODE:
+            case TRANS_DATA:
+               if( ( TransferCfg->tx_count < TransferCfg->tx_length ) && ( TransferCfg->tx_data != NULL ) )
+               {
+                  I2Cx->DR = TransferCfg->tx_data[TransferCfg->tx_count];
+                  TransferCfg->tx_count++;
+               }
+               break;
+            case STOP_DECT:
+               goto s_end_stage;
+            case 0:
+               break;
+            default:
+               goto s_error;
+         }
+      }
+
+s_end_stage:
+      I2Cx->ST = 0xFF;
+      return SUCCESS;
+
+s_error:
+      I2Cx->ST = 0xFF;
+      return ERROR;
+   }
+
+   else if( Opt == I2Cn_TRANSFER_INTERRUPT )
+   {
+      tmp = I2Cn_getNum( I2Cx );
+      I2Cn_SlaveComplete[tmp] = FALSE;
+
+      // Setup tx_rx data, callback and interrupt handler
+      i2cdat[tmp].txrx_setup_slave = *TransferCfg;
+
+      // Set direction phase, read first
+      i2cdat[tmp].dir = 1;
+
+      HAL_I2C_ConfigInterrupt( I2Cx, TRUE );
+
+      return SUCCESS;
+   }
+
+   // return
+   return ERROR;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Transmit an array of bytes in Master mode
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     TransferCfg
+ *                   Pointer to a I2Cn_M_SETUP_Type structure
+ *                   that contains specified information about the configuration for master transfer.
+ * @param[in]     Opt
+ *                   I2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return        Result
+ *                   -  SUCCESS, ERROR
+ *//*-------------------------------------------------------------------------*/
+Status HAL_I2C_Master_Transmit( I2Cn_Type* I2Cx, I2Cn_M_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt )
+{
+   TransferCfg->rx_data = NULL;
+   TransferCfg->rx_length = 0;
+   TransferCfg->tx_count = 0;
+   TransferCfg->rx_count = 0;
+
+   return HAL_I2C_MasterTransferData( I2Cx, TransferCfg, Opt );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Receive an array of bytes in Master mode
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     TransferCfg
+ *                   Pointer to a I2Cn_M_SETUP_Type structure
+ *                   that contains specified information about the configuration for master transfer.
+ * @param[in]     Opt
+ *                   I2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return        Result
+ *                   -  SUCCESS, ERROR
+ *//*-------------------------------------------------------------------------*/
+Status HAL_I2C_Master_Receive( I2Cn_Type* I2Cx, I2Cn_M_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt )
+{
+   TransferCfg->tx_data = NULL;
+   TransferCfg->tx_length = 0;
+   TransferCfg->tx_count = 0;
+   TransferCfg->rx_count = 0;
+
+   return HAL_I2C_MasterTransferData( I2Cx, TransferCfg, Opt );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Receive an array of bytes in Slave mode
+ * @param[in]     I2Cx
+ *                   Pointer to the target I2C
+ *                   -  I2C0 ~ I2C2
+ * @param[in]     TransferCfg
+ *                   Pointer to a I2Cn_S_SETUP_Type structure
+ *                   that contains specified information about the configuration for slave transfer.
+ * @param[in]     Opt
+ *                   I2Cn_TRANSFER_OPT_Type type that selected for interrupt or polling mode.
+ * @return        Result
+ *                   -  SUCCESS, ERROR
+ *//*-------------------------------------------------------------------------*/
+Status HAL_I2C_Slave_Receive( I2Cn_Type* I2Cx, I2Cn_S_SETUP_Type* TransferCfg, I2Cn_TRANSFER_OPT_Type Opt )
+{
+   TransferCfg->tx_data = NULL;
+   TransferCfg->tx_length = 0;
+   TransferCfg->tx_count = 0;
+   TransferCfg->rx_count = 0;
+
+   return HAL_I2C_SlaveTransferData( I2Cx, TransferCfg, Opt );
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_intc.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_intc.c
new file mode 100644
index 0000000..1ac6aeb
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_intc.c
@@ -0,0 +1,461 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_intc.c
+* @brief    Contains all functions support for intc firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_intc.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure External Interrupt Trigger
+ * @param[in]     u32Px
+ *                   Port Number
+ *                   -  PORTB ~ PORTC, PORTE
+ * @param[in]     u32pin
+ *                   Pin Number
+ *                   -  0 ~ 11
+ * @param[in]     u32Trig
+ *                   Trigger Mode
+ *                   -  ITRIGx_Edge, ITRIGx_Level
+ * @param[in]     u32Con
+ *                   Interrupt Mode
+ *                   -  when Trigger Mode is ITRIGx_Edge
+ *                      -  INTCTLx_Disable, INTCTLx_FallingEdge, INTCTLx_RisingEdge, INTCTLx_BothEdge
+ *                   -  when Trigger Mode is ITRIGx_Level
+ *                      -  INTCTLx_Disable, INTCTLx_LowLevel, INTCTLx_HighLevel
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ * @code
+ *                [Example]
+ *
+ *                // configure PB0 as a Falling Edge Trigger
+ *                HAL_INT_EIntPx_SetReg( PORTB, 0, ITRIGx_Edge, INTCTLx_FallingEdge );
+ *
+ *                // configure PB1 as a Falling Edge Trigger
+ *                HAL_INT_EIntPx_SetReg( PORTB, 1, ITRIGx_Edge, INTCTLx_RisingEdge );
+ *
+ *                // configure PB2 as a Falling Edge Trigger
+ *                HAL_INT_EIntPx_SetReg( PORTB, 2, ITRIGx_Edge, INTCTLx_BothEdge );
+ *
+ *                // configure PB3 as a Falling Edge Trigger
+ *                HAL_INT_EIntPx_SetReg( PORTB, 3, ITRIGx_Level, INTCTLx_LowLevel );
+ * @endcode
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EIntPx_SetReg( uint32_t u32Px, uint32_t u32pin, uint32_t u32Trig, uint32_t u32Con )
+{
+   uint32_t    temp_reg;
+
+#ifdef PORTA
+   if( u32Px == PORTA )
+   {
+      temp_reg = INTC->PATRIG;
+      temp_reg &= ~( 1 << u32pin );
+      temp_reg |= ( u32Trig << u32pin );
+      INTC->PATRIG = temp_reg;
+
+      temp_reg = INTC->PACR;
+      temp_reg &= ~( 3 << ( u32pin << 1 ) );
+      temp_reg |= ( u32Con << ( u32pin << 1 ) );
+      INTC->PACR = temp_reg;
+   }
+#endif
+
+#ifdef PORTB
+   if( u32Px == PORTB )
+   {
+      temp_reg = INTC->PBTRIG;
+      temp_reg &= ~( 1 << u32pin );
+      temp_reg |= ( u32Trig << u32pin );
+      INTC->PBTRIG = temp_reg;
+
+      temp_reg = INTC->PBCR;
+      temp_reg &= ~( 3 << ( u32pin << 1 ) );
+      temp_reg |= ( u32Con << ( u32pin << 1 ) );
+      INTC->PBCR = temp_reg;
+   }
+#endif
+
+#ifdef PORTC
+   if( u32Px == PORTC )
+   {
+      temp_reg = INTC->PCTRIG;
+      temp_reg &= ~( 1 << u32pin );
+      temp_reg |= ( u32Trig << u32pin );
+      INTC->PCTRIG = temp_reg;
+
+      temp_reg = INTC->PCCR;
+      temp_reg &= ~( 3 << ( u32pin << 1 ) );
+      temp_reg |= ( u32Con << ( u32pin << 1 ) );
+      INTC->PCCR = temp_reg;
+   }
+#endif
+
+#ifdef PORTD
+   if( u32Px == PORTD )
+   {
+      temp_reg = INTC->PDTRIG;
+      temp_reg &= ~( 1 << u32pin );
+      temp_reg |= ( u32Trig << u32pin );
+      INTC->PDTRIG = temp_reg;
+
+      temp_reg = INTC->PDCR;
+      temp_reg &= ~( 3 << ( u32pin << 1 ) );
+      temp_reg |= ( u32Con << ( u32pin << 1 ) );
+      INTC->PDCR = temp_reg;
+   }
+#endif
+
+#ifdef PORTE
+   if( u32Px == PORTE )
+   {
+      temp_reg = INTC->PETRIG;
+      temp_reg &= ~( 1 << u32pin );
+      temp_reg |= ( u32Trig << u32pin );
+      INTC->PETRIG = temp_reg;
+
+      temp_reg = INTC->PECR;
+      temp_reg &= ~( 3 << ( u32pin << 1 ) );
+      temp_reg |= ( u32Con << ( u32pin << 1 ) );
+      INTC->PECR = temp_reg;
+   }
+#endif
+
+#ifdef PORTF
+   if( u32Px == PORTF )
+   {
+      temp_reg = INTC->PFTRIG;
+      temp_reg &= ~( 1 << u32pin );
+      temp_reg |= ( u32Trig << u32pin );
+      INTC->PFTRIG = temp_reg;
+
+      temp_reg = INTC->PFCR;
+      temp_reg &= ~( 3 << ( u32pin << 1 ) );
+      temp_reg |= ( u32Con << ( u32pin << 1 ) );
+      INTC->PFCR = temp_reg;
+   }
+#endif
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure External Interrupt Group
+ * @param[in]     u32TarIntNum
+ *                   External Interrupt Number
+ *                   -  EINT0 ~ EINT3
+ * @param[in]     u32SrcPort
+ *                   Port Number
+ *                   -  CONFx_PB ~ CONFx_PC, CONFx_PE
+ * @param[in]     u32SrcPin
+ *                   Pin Number
+ *                   -  0 ~ 11
+ * @return        None
+ * @details       This function configures the external interrupt group 0 to 3
+ *                   -  If EINT0CONF1 == 0x01214211, The group 0 interrupts are [None:PB6:None:PB4:PE3:PC2:PB1:PB0]
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EIntCfg( uint32_t u32TarIntNum, uint32_t u32SrcPort, uint32_t u32SrcPin )
+{
+   uint32_t    temp_reg;
+
+   if( u32SrcPin < 8 )
+   {
+      if( u32TarIntNum == EINT0 )
+      {
+         temp_reg = INTC->EINT0CONF1;
+         temp_reg &= ~( 0x0F << ( u32SrcPin * 4 ) );
+         temp_reg |= ( u32SrcPort << ( u32SrcPin * 4 ) );
+         INTC->EINT0CONF1 = temp_reg;
+      }
+      else if( u32TarIntNum == EINT1 )
+      {
+         temp_reg = INTC->EINT1CONF1;
+         temp_reg &= ~( 0x0F << ( u32SrcPin * 4 ) );
+         temp_reg |= ( u32SrcPort << ( u32SrcPin * 4 ) );
+         INTC->EINT1CONF1 = temp_reg;
+      }
+      else if( u32TarIntNum == EINT2 )
+      {
+         temp_reg = INTC->EINT2CONF1;
+         temp_reg &= ~( 0x0F << ( u32SrcPin * 4 ) );
+         temp_reg |= ( u32SrcPort << ( u32SrcPin * 4 ) );
+         INTC->EINT2CONF1 = temp_reg;
+      }
+      else if( u32TarIntNum == EINT3 )
+      {
+         temp_reg = INTC->EINT3CONF1;
+         temp_reg &= ~( 0x0F << ( u32SrcPin * 4 ) );
+         temp_reg |= ( u32SrcPort << ( u32SrcPin * 4 ) );
+         INTC->EINT3CONF1 = temp_reg;
+      }
+   }
+#if 1
+   else
+   {
+      u32SrcPin -= 8;
+      if( u32TarIntNum == EINT0 )
+      {
+         temp_reg = INTC->EINT0CONF2;
+         temp_reg &= ~( 0x0F << ( u32SrcPin * 4 ) );
+         temp_reg |= ( u32SrcPort << ( u32SrcPin * 4 ) );
+         INTC->EINT0CONF2 = temp_reg;
+      }
+      else if( u32TarIntNum == EINT1 )
+      {
+         temp_reg = INTC->EINT1CONF2;
+         temp_reg &= ~( 0x0F << ( u32SrcPin * 4 ) );
+         temp_reg |= ( u32SrcPort << ( u32SrcPin * 4 ) );
+         INTC->EINT1CONF2 = temp_reg;
+      }
+      else if( u32TarIntNum == EINT2 )
+      {
+         temp_reg = INTC->EINT2CONF2;
+         temp_reg &= ~( 0x0F << ( u32SrcPin * 4 ) );
+         temp_reg |= ( u32SrcPort << ( u32SrcPin * 4 ) );
+         INTC->EINT2CONF2 = temp_reg;
+      }
+      else if( u32TarIntNum == EINT3 )
+      {
+         temp_reg = INTC->EINT3CONF2;
+         temp_reg &= ~( 0x0F << ( u32SrcPin * 4 ) );
+         temp_reg |= ( u32SrcPort << ( u32SrcPin * 4 ) );
+         INTC->EINT3CONF2 = temp_reg;
+      }
+   }
+#endif
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable Interrupt Source Mask
+ * @param[in]     u32Src
+ *                   Interrupt Source Mask
+ *                   -  MSK_LVI | MSK_WUT | MSK_WDT | MSK_EINT0 | ...
+ * @return        None
+ * @code
+ *                [Example]
+ *
+ *                // mask LVI, WUT, WDT interrupt
+ *                HAL_INT_EInt_MaskEnable( MSK_LVI | MSK_WUT | MSK_WDT );
+ * @endcode
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EInt_MaskEnable( uint32_t u32Src )
+{
+   INTC->MSK &= ~u32Src;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Disable Interrupt Source Mask
+ * @param[in]     u32Src
+ *                   Interrupt Source Mask
+ *                   -  MSK_LVI | MSK_WUT | MSK_WDT | MSK_EINT0 | ...
+ * @return        None
+ * @code
+ *                [Example]
+ *
+ *                // unmask LVI, WUT, WDT interrupt
+ *                HAL_INT_EInt_MaskDisable( MSK_LVI | MSK_WUT | MSK_WDT );
+ * @endcode
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EInt_MaskDisable( uint32_t u32Src )
+{
+   INTC->MSK |= u32Src;
+}
+
+#ifdef PORTA
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PA Interrupt Flag
+ * @param[in]     u32Value
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG0
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EIntPA_ClearIntStatus( uint32_t u32Value )
+{
+   INTC->PAFLAG = u32Value;
+}
+#endif
+
+#ifdef PORTB
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PB Interrupt Flag
+ * @param[in]     u32Value
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG11
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EIntPB_ClearIntStatus( uint32_t u32Value )
+{
+   INTC->PBFLAG = u32Value;
+}
+#endif
+
+#ifdef PORTC
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PC Interrupt Flag
+ * @param[in]     u32Value
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG3
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EIntPC_ClearIntStatus( uint32_t u32Value )
+{
+   INTC->PCFLAG = u32Value;
+}
+#endif
+
+#ifdef PORTD
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PD Interrupt Flag
+ * @param[in]     u32Value
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG0
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EIntPD_ClearIntStatus( uint32_t u32Value )
+{
+   INTC->PDFLAG = u32Value;
+}
+#endif
+
+#ifdef PORTE
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PE Interrupt Flag
+ * @param[in]     u32Value
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG3
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EIntPE_ClearIntStatus( uint32_t u32Value )
+{
+   INTC->PEFLAG = u32Value;
+}
+#endif
+
+#ifdef PORTF
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear PF Interrupt Flag
+ * @param[in]     u32Value
+ *                   Pn Interrupt Flag Mask
+ *                   -  PnFLAG_FLAG0 ~ PnFLAG_FLAG0
+ * @return        None
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_INT_EIntPF_ClearIntStatus( uint32_t u32Value )
+{
+   INTC->PFFLAG = u32Value;
+}
+#endif
+
+#ifdef PORTA
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PA Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_INT_EIntPA_GetIntStatus( void )
+{
+   return INTC->PAFLAG;
+}
+#endif
+
+#ifdef PORTB
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PB Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_INT_EIntPB_GetIntStatus( void )
+{
+   return INTC->PBFLAG;
+}
+#endif
+
+#ifdef PORTC
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PC Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_INT_EIntPC_GetIntStatus( void )
+{
+   return INTC->PCFLAG;
+}
+#endif
+
+#ifdef PORTD
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PD Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_INT_EIntPD_GetIntStatus( void )
+{
+   return INTC->PDFLAG;
+}
+#endif
+
+#ifdef PORTE
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PE Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_INT_EIntPE_GetIntStatus( void )
+{
+   return INTC->PEFLAG;
+}
+#endif
+
+#ifdef PORTF
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get PF Interrupt Flag
+ * @return        Pn Interrput Flag
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_INT_EIntPF_GetIntStatus( void )
+{
+   return INTC->PFFLAG;
+}
+#endif
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_lcd.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_lcd.c
new file mode 100644
index 0000000..e97a961
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_lcd.c
@@ -0,0 +1,151 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_lcd.c
+* @brief    Contains all functions support for lcd firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_lcd.h"
+#include "A31G12x_hal_scu.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the LCD peripheral with the specified parameters.
+ * @param[in]     LCD_Config
+ *                   Pointer to LCD_CFG_Type
+ *                   that contains the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ * @details       This function sets the LCD Bias Resistor, LCD Duty,
+ *                LCD Clock, Automatic Bias Control, and Contrast Control Data.
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_LCD_Init( LCD_CFG_Type* LCD_Config )
+{
+   /* Check LCD_Config */
+   if( LCD_Config == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   // enable peripheral clock
+   HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_LCDCLKE, PPxCLKE_Enable );
+
+   LCD->CR = 0
+             | LCD_Config->Bias
+             | LCD_Config->Duty
+             | LCD_Config->Clk
+             ;
+
+   LCD->BCCR = 0
+               | LCD_Config->AutoBiasEn
+               | LCD_Config->BiasTime
+               | LCD_Config->Contrast
+               | LCD_Config->ContrastStep
+               ;
+
+   // return
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set LCD LCD_CR/LCD_BCCR Registers
+ * @param[in]     u32LCD_CR
+ *                   LCD Driver Control Register Setting Data
+ * @param[in]     u32LCD_BCCR
+ *                   LCD Automatic bias and Contrast Control Register Setting Data
+ * @return        @ref HAL_Status_Type
+ * @details       This function sets the LCD Bias Resistor, LCD Duty,
+ *                LCD Clock, Automatic Bias Control, and Contrast Control Data.
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_LCD_SetRegister( uint32_t u32LCD_CR, uint32_t u32LCD_BCCR )
+{
+   LCD->CR = u32LCD_CR;       // Set LCD Driver Control Register
+   LCD->BCCR = u32LCD_BCCR;   // Set LCD Driver Automatic Bias and Contrast Control Register
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear LCD Buffer
+ * @return        @ref HAL_Status_Type
+ * @details       This function clear Display Data RAM.
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_LCD_ClearDspRam( void )
+{
+   uint8_t              u32Index;
+   volatile uint8_t*    lcd_dsp_ram;
+
+   lcd_dsp_ram = &LCD->DR0;
+   for( u32Index = 0; u32Index < LCDBufSize; u32Index ++ )
+   {
+      lcd_dsp_ram[u32Index] = 0;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Write LCD Buffer
+ * @param[in]     write_buf
+ *                   Font Data Buffer Address
+ * @param[in]     u32Index
+ *                   Font Data Buffer Index
+ * @param[in]     size
+ *                   Font Data Buffer Size
+ * @return        @ref HAL_Status_Type
+ * @details       This function writes display data to Display Data RAM.
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_LCD_WriteDspRam( uint8_t* write_buf, uint32_t u32Index, uint32_t size )
+{
+   volatile uint8_t*    lcd_dsp_ram;
+   uint32_t             i;
+
+   if( ( u32Index + size ) > LCDBufSize )    // Check Buffer size
+   {
+      size = size - ( ( u32Index + size ) - LCDBufSize );
+   }
+
+   lcd_dsp_ram = &LCD->DR0;
+   for( i = 0; i < size; i ++ )
+   {
+      lcd_dsp_ram[u32Index + i] = write_buf[i];
+   }
+
+   return HAL_OK;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_pcu.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_pcu.c
new file mode 100644
index 0000000..13bc51c
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_pcu.c
@@ -0,0 +1,364 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_pcu.c
+* @brief    Contains all functions support for pcu firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_pcu.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set PCU Pn_MOD/Pn_TYP/Pn_AFSR1/Pn_PUPD Registers
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     u32Mode
+ *                   Values for In/Out/Alternative mode
+ * @param[in]     u32Type
+ *                   Values for Push-pull and Open-drain
+ * @param[in]     u32Afsr1
+ *                   Values for Alternative Function
+ * @param[in]     u32Afsr2
+ *                   Values for Alternative Function
+ * @param[in]     u32PuPd
+ *                   Values for Pull-up/down resistor
+ * @return        None
+ * @details       This function sets the mode, type, alternative function, and pull-up/down resistor of port.
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_Init( Pn_Type* Px, uint32_t u32Mode, uint32_t u32Type, uint32_t u32Afsr1, uint32_t u32Afsr2, uint32_t u32PuPd )
+{
+   Px->MOD   = u32Mode;    // 00/01/10/11: Input/Output/"Alternative Function"/Reserved Mode
+   Px->TYP   = u32Type;    // 0/1:         Push-pull/Open-drain Output
+   Px->AFSR1 = u32Afsr1;   // 0 to 4:      Alternative Function 0 to 4
+   Px->AFSR2 = u32Afsr2;   // 0 to 4:      Alternative Function 0 to 4
+   Px->PUPD  = u32PuPd;    // 00/01/10/11: "Disable Pull-up/down"/"Enable Pull-up"/"Enable Pull-down"/Reserved Resistor
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure pin function
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     pin_no
+ *                   Pin Number
+ *                   -  0 ~ 15
+ * @param[in]     func
+ *                   Alternative Function Number
+ *                   -  AFSRx_AF0 ~ AFSRx_AF4
+ * @return        None
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_ConfigFunction( Pn_Type* Px, uint8_t pin_no, uint32_t func )
+{
+   uint8_t     pin_offset;
+   uint32_t    reg_val;
+
+   if( pin_no < 8 ) // 0~7
+   {
+      //--------------------------------------
+      // pin_offset = pin_no * 4
+      //--------------------------------------
+      pin_offset = ( pin_no * 4 );
+
+      //--------------------------------------
+      // MR
+      //--------------------------------------
+      reg_val = Px->AFSR1;
+      reg_val &= ~( AFSRx_Msk << pin_offset );
+      reg_val |= ( func << pin_offset );
+
+      Px->AFSR1 = reg_val;
+   }
+   else
+   {
+      pin_no -= 8;
+      //--------------------------------------
+      // pin_offset = pin_no * 4
+      //--------------------------------------
+      pin_offset = ( pin_no * 4 );
+
+      //--------------------------------------
+      // MR
+      //--------------------------------------
+      reg_val = Px->AFSR2;
+      reg_val &= ~( AFSRx_Msk << pin_offset );
+      reg_val |= ( func << pin_offset );
+
+      Px->AFSR2 = reg_val;
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure pin mode
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     pin_no
+ *                   Pin Number
+ *                   -  0 ~ 15
+ * @param[in]     dir_type
+ *                   Pin Mode
+ *                   -  INPUT:               0
+ *                   -  PUSH_PULL_OUTPUT:    1
+ *                   -  ALTERN_FUNC:         2
+ *                   -  OPEN_DRAIN_OUTPUT:   3
+ * @return        None
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_ConfigOutput( Pn_Type* Px, uint8_t pin_no, PCU_PORT_MODE dir_type )
+{
+   uint8_t     pin_offset;
+   uint32_t    reg_val;
+   uint32_t    dir_type_temp;
+
+   dir_type_temp = dir_type;
+   if( dir_type_temp == OPEN_DRAIN_OUTPUT )
+   {
+      dir_type = PUSH_PULL_OUTPUT;
+   }
+   //--------------------------------------
+   // pin_offset = pin_no * 2
+   //--------------------------------------
+   pin_offset = ( pin_no << 1 );
+
+   //--------------------------------------
+   // Pn_MOD
+   //--------------------------------------
+   reg_val = Px->MOD;
+   reg_val &= ~( MODEx_Msk << pin_offset );
+   reg_val |= ( dir_type << pin_offset );
+   Px->MOD = reg_val;
+
+   //--------------------------------------
+   // Pn_TYP
+   //--------------------------------------
+   if( ( dir_type_temp == PUSH_PULL_OUTPUT ) || ( dir_type_temp == OPEN_DRAIN_OUTPUT ) )
+   {
+      reg_val = Px->TYP;
+      reg_val &= ~( 1 << pin_no );
+      if( dir_type_temp == OPEN_DRAIN_OUTPUT )
+      {
+         reg_val |= ( 1 << pin_no );
+      }
+      Px->TYP = reg_val;
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure out data Mask
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     pin_no
+ *                   Pin Number
+ *                   -  0 ~ 15
+ * @param[in]     maskctrl
+ *                   state
+ *                   -  OUTDMSKx_Unmask  // The corresponding OUTDRx bit can be changed.
+ *                   -  OUTDMSKx_Mask    // The corresponding OUTDRx bit is protected.
+ * @return        None
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_ConfigOutDataMask( Pn_Type* Px, uint8_t pin_no, FunctionalState maskctrl )
+{
+   uint32_t    reg_val;
+
+   reg_val = Px->OUTDMSK;
+   reg_val &= ~( 1 << pin_no );
+   reg_val |= ( maskctrl << pin_no );
+   Px->OUTDMSK = reg_val;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure Pin Pull-Up & Pull-Down
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     pin_no
+ *                   Pin Number
+ *                   -  0 ~ 15
+ * @param[in]     pullupdown
+ *                   Target Configuration
+ *                   -  PUPDx_Disable
+ *                   -  PUPDx_EnablePU
+ *                   -  PUPDx_EnablePD
+ * @return        None
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_ConfigPullup( Pn_Type* Px, uint8_t pin_no, uint8_t pullupdown )
+{
+   uint32_t    reg_val;
+   uint8_t     pin_offset;
+
+   pin_offset = ( pin_no << 1 );
+
+   reg_val = Px->PUPD;
+   reg_val &= ~( 3 << pin_offset );
+   reg_val |= ( pullupdown << pin_offset );
+   Px->PUPD = reg_val;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set PCU Debounce
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PB ~ PC, PE
+ * @param[in]     u32Pins
+ *                   Pin Number
+ *                   -  0 ~ 11
+ * @param[in]     u32Debnc
+ *                   Sampling Clock Selection
+ *                   -  DBCLK_HCLK1, DBCLK_HCLK4, DBCLK_HCLK16, DBCLK_HCLK64, DBCLK_HCLK256, DBCLK_HCLK1024
+ * @return        None
+ * @details       This function enables the debounce filter for the pin specified by u32Pins
+ *                and selects the debounce filter sampling clock.
+ * @remark        Available EINT Pin: PB[11:0], PC[3:0], PE[3:0]
+ * @code
+ *                [Example]
+ *
+ *                HAL_GPIO_SetDebouncePin( ( Pn_Type* )PB, 0, DBCLK_HCLK1024 );
+ *                HAL_GPIO_SetDebouncePin( ( Pn_Type* )PB, 1, DBCLK_HCLK1024 );
+ * @endcode
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_SetDebouncePin( Pn_Type* Px, uint32_t u32Pins, uint32_t u32Debnc )
+{
+#if 0    // before bug fix
+   uint32_t    reg_val;
+
+   reg_val = ( 0x07ff & Px->DBCR );
+   reg_val |= ( 0x01 << u32Pins );
+   reg_val |= u32Debnc;
+   Px->DBCR = reg_val;
+#else    // after bug fix
+   Px->DBCR = Px->DBCR
+              & ~Pn_DBCR_DBCLK_Msk
+              | ( 1 << u32Pins )
+              | u32Debnc
+              ;
+#endif
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Value for bits that have output direction on GPIO port.
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     bitValue
+ *                   Value that contains all bits on GPIO to set.
+ *                   -  0x0000 ~ 0xffff
+ *                   -  Example: Use the value of 0x0003 to set bit 0 and bit 1.
+ * @return        None
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_SetPin( Pn_Type* Px, uint16_t bitValue )
+{
+   Px->BSR = bitValue;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear Value for bits that have output direction on GPIO port.
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     bitValue
+ *                   Value that contains all bits on GPIO to clear.
+ *                   -  0x0000 ~ 0xffff
+ *                   -  Example: Use the value of 0x0003 to clear bit 0 and bit 1.
+ * @return        None
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_ClearPin( Pn_Type* Px, uint16_t bitValue )
+{
+   Px->BCR = bitValue;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Toggle Value for bits that have output direction on GPIO port.
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     bitValue
+ *                   Value that contains all bits on GPIO to toggle.
+ *                   -  0x00 ~ 0xff 
+ * @return        None
+ * @remark        Available GPIO Pin: PA[7:0], PB[7:0], PC[4:0], PD[7:0], PE[7:0], PF[7:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_TogglePin( Pn_Type* Px, uint16_t bitValue )
+{
+   if((Px->OUTDR & bitValue) != 0)
+   {
+      HAL_GPIO_ClearPin(Px, bitValue);
+   }
+   else
+   {
+      HAL_GPIO_SetPin(Px, bitValue);
+   }
+}
+/*-------------------------------------------------------------------------*//**
+ * @brief         Write Value on port that have output direction of GPIO
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @param[in]     Value
+ *                   Value to write
+ * @return        None
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ *//*-------------------------------------------------------------------------*/
+void HAL_GPIO_WritePin( Pn_Type* Px, uint16_t Value )
+{
+   Px->OUTDR = Value;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Read Current state on port pin that have input direction of GPIO
+ * @param[in]     Px
+ *                   Pointer to the target PORT
+ *                   -  PA ~ PF
+ * @return        Current value of GPIO port.
+ * @remark        Available GPIO Pin: PA[11:0], PB[15:0], PC[12:0], PD[7:0], PE[15:0], PF[11:0]
+ * @note          Return value contain state of each port pin (bit) on that GPIO regardless
+ *                its direction is input or output.
+ *//*-------------------------------------------------------------------------*/
+uint16_t HAL_GPIO_ReadPin( Pn_Type* Px )
+{
+   return Px->INDR;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_pwr.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_pwr.c
new file mode 100644
index 0000000..e5d970f
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_pwr.c
@@ -0,0 +1,82 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_pwr.c
+* @brief    Contains all functions support for pwr firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_pwr.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enter Sleep mode with co-operated instruction by the Cortex-M0+.
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void HAL_PWR_EnterSleepMode( void )
+{
+   // Sleep Mode, clear SLEEPDEEP bit
+   SCB->SCR = 0;
+
+   // Sleep Mode
+   WFI();
+   NOP();
+   NOP();
+   NOP();
+   NOP();
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enter Deep Sleep mode with co-operated instruction by the Cortex-M0+.
+ * @param         None
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+void HAL_PWR_EnterPowerDownMode( void )
+{
+   // Deep-Sleep Mode, set SLEEPDEEP bit
+   SCB->SCR = 0x4;
+
+   // Deep Sleep Mode
+   WFI();
+   NOP();
+   NOP();
+   NOP();
+   NOP();
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_scu.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_scu.c
new file mode 100644
index 0000000..ab27804
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_scu.c
@@ -0,0 +1,582 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_scu.c
+* @brief    Contains all functions support for scu firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_scu.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Reset Source Status
+ * @return        Reset Source
+ * @details       This function gets reset source status and clear the register.
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_SCU_ResetSourceStatus( void )
+{
+   uint32_t    tmp;
+
+   tmp = SCUCC->RSTSSR;       // Get reset source status
+   SCUCC->RSTSSR = 0x3FuL;    // Clear all reset source status
+   return tmp;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Non-Maskable Interrupt(NMI) Source Selection Register
+ * @param[in]     u32NmiCon
+ *                   Values for NMISRCR register
+ * @return        None
+ * @details       This function sets NMISRCR register.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_SetNMI( uint32_t u32NmiCon )
+{
+   SCUCC->NMISRCR = u32NmiCon;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Check whether system reset ok or not. Generate s/w reset if a weak reset
+ * @return        None
+ * @details       This function checks system reset validation and Generate s/w reset if a weak reset.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_SoftwareReset_Config( void )
+{
+   if( SCUCC->SRSTVR_b.VALID != 0x55 )
+   {
+      SCUCC_GenSwRst();    // Generate S/W reset on invalid reset
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Wake-Up Timer Data
+ * @param[in]     u32Data
+ * @return        None
+ * @details       This function sets wake-up timer data to wait for release of deep sleep mode.
+ *                Its value should be set to be at least more than 150usec.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_SetWakupData( uint32_t u32Data )
+{
+   SCUCC->WUTDR = u32Data;    // On HCLK=40MHz, (150us x 40)/32 = 187.5. So, the data should be more than 187
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Change fine trim value of HIRC by one step
+ * @param[in]     u32Ind
+ *                   Indicator for +/- one step
+ *                   -  HIRC_UP_ONESTEP, HIRC_DOWN_ONESTEP
+ * @return        None
+ * @details       This function changes fine trim value by one step.
+ *                If the u32Ind is HIRC_UP_ONESTEP, HIRC frequency is changed up by about 140kHz.
+ *                If the u32Ind is HIRC_DOWN_ONESTEP, HIRC frequency is changed down by about 140kHz.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_HIRCTRM_ClockConfig( uint32_t u32Ind )
+{
+   uint32_t    tmp, ntrim;
+
+   tmp = ( SCUCC->HIRCTRM ) & 0x001fuL;   // Read current fine trim value of HIRC
+   if( u32Ind == HIRC_UP_ONESTEP )        // Increment by one step(about 140kHz)
+   {
+      if( tmp != 0x0f )
+      {
+         tmp++;
+      }
+   }
+   else     // Decrement by one step(about 140kHz)
+   {
+      if( tmp != 0x10 )
+      {
+         tmp--;
+      }
+   }
+   tmp &= 0x1f;                                 // Fine trim value is only 5-bits
+   tmp |= ( ( SCUCC->HIRCTRM ) & 0x00E0uL );    // Read Coarse trim value
+   ntrim = ( tmp << 8 ) ^ 0x0000FF00;           // Make write complement key
+   SCUCC->HIRCTRM = ( ( uint32_t )SCUCC_HIRCTRM_WTIDKY_Value << SCUCC_HIRCTRM_WTIDKY_Pos )   // Write new HIRC trim value with write ID and complement key
+                    | ntrim
+                    | tmp;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Change fine trim value of WDTRC by one step
+ * @param[in]     u32Ind
+ *                   Indicator for +/- one step
+ *                   -  WDTRC_UP_ONESTEP, WDTRC_DOWN_ONESTEP
+ * @return        None
+ * @details       This function changes fine trim value by one step.
+ *                If the u32Ind is WDTRC_UP_ONESTEP, WDTRC frequency is changed up by about 1.1kHz.
+ *                If the u32Ind is WDTRC_DOWN_ONESTEP, WDTRC frequency is changed down by about 1.1kHz.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_WDTRCTRM_ClockConfig( uint32_t u32Ind )
+{
+   uint32_t    ctmp, ftmp, ntrim;
+
+   ftmp = ( SCUCC->WDTRCTRM ) & 0x0007uL;    // Read current fine trim value of WDTRC
+   ctmp = ( SCUCC->WDTRCTRM ) & 0x00F0uL;    // Read current coarse trim value of WDTRC
+   if( u32Ind == WDTRC_UP_ONESTEP )          // Increment by one step(about 1.1kHz)
+   {
+      ftmp++;
+      ftmp &= 0x07uL;                        // Fine trim value is only 3-bits
+      if( ftmp == 0x04 )
+      {
+         if( ctmp != 0x70 )
+         {
+            ctmp += 0x10uL;
+         }
+         else
+         {
+            ftmp = 0x03uL;
+         }
+      }
+   }
+   else     // Decrement by one step(about 1.1kHz)
+   {
+      ftmp--;
+      ftmp &= 0x07uL;      // Fine trim value is only 3-bits
+      if( ftmp == 0x03 )
+      {
+         if( ctmp != 0x80 )
+         {
+            ctmp -= 0x10uL;
+         }
+         else
+         {
+            ftmp = 0x04uL;
+         }
+      }
+   }
+   ctmp &= 0x00f0uL;                      // Coarse trim value is only 4-bits
+   ctmp |= ftmp;
+   ntrim = ( ctmp << 8 ) ^ 0x0000FF00;    // Make write complement key
+   SCUCC->WDTRCTRM   = ( SCUCC_WDTRCTRM_WTIDKY_Value << SCUCC_WDTRCTRM_WTIDKY_Pos )    // Write new WDTRC trim value with write ID and complement key
+                       | ntrim
+                       | ctmp;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure Clock Monitoring
+ * @param[in]     u32Acts
+ *                   Clock Monitoring Action Selection
+ *                   -  MACTS_FlagChk, MACTS_RstGen, MACTS_SysClkChg
+ * @param[in]     u32Target
+ *                   Clock Monitoring Target Selection
+ *                   -  MONCS_MCLK, MONCS_HIRC, MONCS_XMOSC, MONCS_XSOSC
+ * @return        None
+ * @details       This function checks whether the target clock oscillates.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_ClockMonitoring( uint32_t u32Acts, uint32_t u32Target )
+{
+   if( SCUCG->CLKSRCR_b.WDTRCEN == 0 )
+   {
+      SCUCG->CLKSRCR = SCUCG->CLKSRCR
+                       | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )
+                       | CLKSRCR_WDTRCEN;                   // The WDTRC should be enabled to use clock monitoring
+   }
+   SCUCG->CMONCR = ( 0x3uL << 2 ) | u32Acts | u32Target;    // Clear MONFLAG and NMINTFG, Set Monitoring Target and Monitoring Action
+   SCUCG->CMONCR_b.MONEN = 1;                               // Clock Monitoring Enable
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Disable Clock Monitoring
+ * @return        None
+ * @details       This function disables clock monitoring.
+                  Before disabling the ��clock monitoring�� function, you need to take step to clear
+                  the MACTS[1:0] bits of SCU_CMONCR register to ��00b��.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_ClockMonitoring_Disable( void )
+{
+   SCUCG->CMONCR_b.MACTS = 0;    // Clear MACTS bits first
+   SCUCG->CMONCR_b.MONEN = 0;    // Disable clock monitoring function
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Clock Source, HIRC Frequency, and type of XMOSC
+ * @param[in]     u32FreIRC
+ *                   HIRC Frequency Selection
+ *                   -  HIRCSEL_HIRC1, HIRCSEL_HIRC2, HIRCSEL_HIRC4, HIRCSEL_HIRC8
+ * @param[in]     u32TypeXM
+ *                   Main Oscillator Type and Frequency Range Selection
+ *                   -  XMFRNG_Xtal, XMFRNG_Clock
+ * @param[in]     u32ClkSrc
+ *                   Clock Source
+ *                   -  CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
+ * @return        None
+ * @details       This function sets clock source, HIRC frequency, and x-tal type of XMOSC.
+ *                If target clock source is one of XMOSC and XSOSC,
+ *                the x-tal pins should be set as alternative before this function call.
+ *                To set alternative for x-tal, Use HAL_SCU_MainXtal_PinConfig() and HAL_SCU_SubXtal_PinConfig() functions.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_ClockSource_Config( uint32_t u32FreIRC, uint32_t u32TypeXM, uint32_t u32ClkSrc )
+{
+   uint32_t    tmp;
+
+   tmp = SCUCG->CLKSRCR & 0x0000000F;
+   tmp |= ( ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )  // Write ID
+            | u32FreIRC                                                             // HIRC Frequency
+            | u32TypeXM                                                             // XMOSC type: x-tal or external clock
+            | u32ClkSrc );
+   SCUCG->CLKSRCR = tmp;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable Clock Source
+ * @param[in]     u32ClkSrc
+ *                   Clock Source
+ *                   -  CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
+ * @param[in]     u32HircDiv
+ *                   HIRC Frequency Selection
+ *                   -  HIRCSEL_HIRC1, HIRCSEL_HIRC2, HIRCSEL_HIRC4, HIRCSEL_HIRC8
+ * @return        None
+ * @details       This function is used to enable original source after system clock change.
+ * @code
+ *                [Example]
+ *
+ *                // eable HIRC, XMOSC, SXOSC, WDTRC and select HIRCSEL_HIRC1(40MHz HIRC)
+ *                HAL_SCU_ClockSource_Enable( CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN | CLKSRCR_WDTRCEN, HIRCSEL_HIRC1 );
+ * @endcode
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_ClockSource_Enable( uint32_t u32ClkSrc, uint32_t u32HircDiv )
+{
+#if 0    // before bug fix
+   uint32_t    tmp;
+
+   tmp = SCUCG->CLKSRCR & 0x0000FFFF;     // 0x00000fff�� ���� ��...
+   tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos );   // Write ID
+   tmp |= u32ClkSrc;
+   tmp |= u32HircDiv;
+   SCUCG->CLKSRCR = tmp;
+#else    // after bug fix
+   SCUCG->CLKSRCR =  SCUCG->CLKSRCR
+                     & ~( SCUCG_CLKSRCR_WTIDKY_Msk | SCUCG_CLKSRCR_HIRCSEL_Msk )
+                     | ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos )   // Write ID
+                     | u32HircDiv
+                     | u32ClkSrc
+                     ;
+#endif
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Disable Clock Source
+ * @param[in]     u32ClkSrc
+ *                   Clock Source
+ *                   -  CLKSRCR_WDTRCEN | CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN
+ * @return        None
+ * @details       This function is used to disable original source after system clock change.
+ * @code
+ *                [Example]
+ *
+ *                // disable XMOSC, SXOSC
+ *                HAL_SCU_ClockSource_Disable( CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN );
+ * @endcode
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_ClockSource_Disable( uint32_t u32ClkSrc )
+{
+   uint32_t    tmp;
+
+   tmp = SCUCG->CLKSRCR & 0x0000FFFF;
+   tmp |= ( ( uint32_t )SCUCG_CLKSRCR_WTIDKY_Value << SCUCG_CLKSRCR_WTIDKY_Pos );   // Write ID
+   tmp &= ~u32ClkSrc;
+   SCUCG->CLKSRCR = tmp;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set XMOSC Pins for x-tal
+ * @param[in]     u32XtalFilter
+ *                   the filter of x-tal frequency
+ *                   -  XRNS_LE4p5MHz, XRNS_LE6p5MHz, XRNS_LE8p5MHz
+ *                   -  XRNS_LE10p5MHz, XRNS_LE12p5MHz, XRNS_LE16p5MHz
+ * @return        None
+ * @details       This function sets PF[1:0]'s alternative for x-tal of XMOSC.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_MainXtal_PinConfig( uint32_t u32XtalFilter )
+{
+   PF->AFSR1 &= 0xFFFFFF00;      // PF[1:0]: XIN/XOUT
+   PF->PUPD  &= 0xFFFFF0uL;      // PF[1:0]: Pull-up/down resistors Disable
+   PF->MOD   &= 0xFFFFF0uL;
+   PF->MOD   |= 0x000AuL;        // PF[1:0]: Alternative Function
+   SCUCG->XTFLSR = ( ( uint32_t )SCUCG_XTFLSR_WTIDKY_Value << SCUCG_XTFLSR_WTIDKY_Pos )   // Write ID
+                   | u32XtalFilter;                                                       // x-tal filter value
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set XSOSC Pins for x-tal
+ * @return        None
+ * @details       This function sets PF[3:2]'s alternative for x-tal of XSOSC.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_SubXtal_PinConfig( void )
+{
+   PF->AFSR1 &= 0xFFFF00FF;      // PF[3:2]: SXIN/SXOUT
+   PF->PUPD  &= 0xFFFF0FuL;      // PF[3:2]: Pull-up/down resistors Disable
+   PF->MOD   &= 0xFFFF0FuL;
+   PF->MOD   |= 0x00A0uL;        // PF[3:2]: Alternative Function
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Change System Clock
+ * @param[in]     u32Target
+ *                   Target Clock
+ *                   -  MCLKSEL_HIRC, MCLKSEL_XMOSC, MCLKSEL_XSOSC, MCLKSEL_WDTRC
+ * @return        None
+ * @details       This function changes system clock to target source.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_SystemClockChange( uint32_t u32Target )
+{
+   SCUCG->SCCR = ( SCUCG_SCCR_WTIDKY_Value << SCUCG_SCCR_WTIDKY_Pos )   // Write ID
+                 | u32Target;                                           // Target Clock Source
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set System Clock Dividers, SCDIVR1 for WT and LCD Driver in case of using MCLK, SCDIVR2 for SysTick Timer and PCLK
+ * @param[in]     u32Div02
+ *                   Values for Divider 0 and 2
+ *                   -  Clock Divide for HCLK (Divider 0)
+ *                      -  HDIV_MCLK16, HDIV_MCLK8, HDIV_MCLK4, HDIV_MCLK2, HDIV_MCLK1
+ *                   -  Clock Divide for Watch Timer and LCD Driver (Divider 2)
+ *                      -  WLDIV_MCLK64, WLDIV_MCLK128, WLDIV_MCLK256, WLDIV_MCLK512, WLDIV_MCLK1024
+ * @param[in]     u32Div13
+ *                   Values for Divider 1 and 3
+ *                   -  Clock Divide for PCLK (Divider 1)
+ *                      -  PDIV_HCLK1, PDIV_HCLK2, PDIV_HCLK4, PDIV_HCLK8
+ *                   -  Clock Divide for SysTick Timer (Divider 3)
+ *                      -  SYSTDIV_HCLK1, SYSTDIV_HCLK2, SYSTDIV_HCLK4, SYSTDIV_HCLK8
+ * @return        None
+ * @details       This function changes system clock to target source.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_SystemClockDivider( uint32_t u32Div02, uint32_t u32Div13 )
+{
+   // Divider 0 for HCLK:                 000/001/010/011/100: MCLK is divided by 16/8/4/2/1
+   // Divider 2 for WT and LCD Driver:    000/001/010/011/100: MCLK is divided by 64/128/256/512/1024
+   SCUCG->SCDIVR1 = u32Div02;
+
+   // Divider 1 for PCLK:                 00/01/10/11: HCLK is divided by 1/2/4/8
+   // Divider 3 for SysTick Timer:        00/01/10/11: HCLK is divided by 1/2/4/8
+   SCUCG->SCDIVR2 = u32Div13;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set CLKO Pin for Clock Output
+ * @return        None
+ * @details       This function sets selected pin's alternative for CLKO.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_CLKO_PinConfig( void )
+{
+   PF->AFSR1 &= 0xFFF0FFFF;   // PF4   CLKO     0: CLKO        1: ----        2: ----        3: ----        4: ----
+   PF->PUPD  &= 0xFFFCFFuL;   // PF4   CLKO     0: Disable Pull-Up/Down    1: Enable Pull-Up    2: Enable Pull-Down
+   PF->MOD   &= 0xFFFCFFuL;   // PF4   CLKO     0: Input Mode     1: Output Mode    2: Alternative Function Mode
+   PF->MOD   |= 0x0200uL;     // PF4   CLKO     0: Input Mode     1: Output Mode    2: Alternative Function Mode
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Configuration for Clock Output
+ * @param[in]     u32ClkSrc
+ *                   Clock to output
+ *                   -  CLKOS_MCLK, CLKOS_WDTRC, CLKOS_HIRC, CLKOS_HCLK, CLKOS_PCLK
+ * @param[in]     u32Level
+ *                   Clock Output Polarity when Disable
+ *                   -  POLSEL_Low, POLSEL_High
+ * @param[in]     u32Div
+ *                   Output Clock Divide
+ *                   -  CLKODIV_SelectedClock1, CLKODIV_SelectedClock2
+ *                   -  CLKODIV_SelectedClock4, CLKODIV_SelectedClock8
+ *                   -  CLKODIV_SelectedClock16, CLKODIV_SelectedClock32
+ *                   -  CLKODIV_SelectedClock64, CLKODIV_SelectedClock128
+ * @return        None
+ * @details       This function sets clock output related configuration.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_ClockOutput( uint32_t u32ClkSrc, uint32_t u32Level, uint32_t u32Div )
+{
+   SCUCG->CLKOCR = 0
+                   | ( 1 << SCUCG_CLKOCR_CLKOEN_Pos )    // CLKO Enable
+                   | u32Level    // 0: Low Level   1: High Level
+                   | u32Div      // 0: div_1       1: div_2       2: div_4    3: div_8    4: div_16   5: div_32   6: div_64   7: div_128
+                   | u32ClkSrc   // 0: MCLK        1: WDTRC       2: HIRC     3: HCLK     4: PCLK
+                   ;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Peripheral Clock, The peripheral doesn't work if the corresponding bit is "0b".
+ * @param[in]     u32PeriClk1
+ *                   Values for TIMER20 ~ TIMER21, TIMER30, TIMER10 ~ TIMER16, PA ~ PF
+ * @param[in]     u32PeriClk2
+ *                   Values for the Others Peripheral
+ * @return        None
+ * @details       This function sets the peripheral clock.
+ *                A peripheral works properly during the corresponding bit is set to "1b".
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_Peripheral_ClockConfig( uint32_t u32PeriClk1, uint32_t u32PeriClk2 )
+{
+   SCUCG->PPCLKEN1 = u32PeriClk1;   // Set peripheral clock of timers and ports
+   SCUCG->PPCLKEN2 = u32PeriClk2;   // Set peripheral clock of the others
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Each Peripheral Clock
+ * @param[in]     u32PeriClk1
+ *                   PeriClk1
+ *                   -  PPCLKEN1_T20CLKE ~ PPCLKEN1_T21CLKE, PPCLKEN1_T30CLKE
+ *                   -  PPCLKEN1_T10CLKE ~ PPCLKEN1_T16CLKE, PPCLKEN1_PACLKE ~ PPCLKEN1_PFCLKE
+ * @param[in]     Ind
+ *                   Enable/Disable Peripheral Clock.
+ *                   -  PPxCLKE_Disable, PPxCLKE_Enable
+ * @return        None
+ * @details       This function sets each peripheral clock of timers and Ports.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_Peripheral_EnableClock1( uint32_t u32PeriClk1, uint32_t Ind )
+{
+   if( Ind )
+   {
+      SCUCG->PPCLKEN1 |= u32PeriClk1;     // Enable a peripheral clock of timers and ports
+   }
+   else
+   {
+      SCUCG->PPCLKEN1 &= ~u32PeriClk1;    // Disable a peripheral clock of timers and ports
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Each Peripheral Clock
+ * @param[in]     u32PeriClk2
+ *                   PeriClk2
+ *                   -  PPCLKEN2_FMCLKE, PPCLKEN2_LVICLKE, PPCLKEN2_WDTCLKE, PPCLKEN2_WTCLKE
+ *                   -  PPCLKEN2_LCDCLKE, PPCLKEN2_CRCLKE, PPCLKEN2_ADCLKE
+ *                   -  PPCLKEN2_I2C0CLKE ~ PPCLKEN2_I2C2CLKE
+ *                   -  PPCLKEN2_UT0CLKE ~ PPCLKEN2_UT1CLKE, PPCLKEN2_UST10CLKE ~ PPCLKEN2_UST13CLKE
+ * @param[in]     u32Ind
+ *                   Enable/Disable Peripheral Clock.
+ *                   -  PPxCLKE_Disable, PPxCLKE_Enable
+ * @return        None
+ * @details       This function sets each peripheral clock of the others.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_Peripheral_EnableClock2( uint32_t u32PeriClk2, uint32_t u32Ind )
+{
+   if( u32Ind )
+   {
+      SCUCG->PPCLKEN2 |= u32PeriClk2;     // Enable a peripheral clock of others
+   }
+   else
+   {
+      SCUCG->PPCLKEN2 &= ~u32PeriClk2;    // Disable a peripheral clock of others
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Reset Peripheral Block, The peripheral is reset if the corresponding bit is "1b".
+ * @param[in]     u32PeriRst1
+ *                   Values for TIMER20 ~ TIMER21, TIMER30, TIMER10 ~ TIMER16, PA ~ PF
+ * @param[in]     u32PeriRst2
+ *                   Values for the Others Peripheral
+ * @return        None
+ * @details       This function reset peripheral block during the corresponding bit is set to "1b".
+                  After reset of a block, the corresponding bit should be cleared to "0b" for operation.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_Peripheral_ResetConfig( uint32_t u32PeriRst1, uint32_t u32PeriRst2 )
+{
+   uint32_t    i;
+
+   SCUCG->PPRST1 = u32PeriRst1;  // Reset peripheral block of timers and ports if the corresponding bit is "1b"
+   SCUCG->PPRST2 = u32PeriRst2;  // Reset peripheral block of the others
+   for( i = 0 ; i < 10 ; i++ )
+   {
+      NOP();
+   }
+   SCUCG->PPRST1 = 0x0uL;        // Clear the peripheral reset bits
+   SCUCG->PPRST2 = 0x0uL;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set/Reset Each Peripheral Block Reset of PPRST1 Register
+ * @param[in]     u32EachPeri1
+ *                   Peri1
+ *                   -  PPRST1_T20RST ~ PPRST1_T21RST, PPRST1_T30RST
+ *                   -  PPRST1_T10RST ~ PPRST1_T16RST, PPRST1_PARST ~ PPRST1_PFRST
+ * @details       This function resets each peripheral block.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_Peripheral_SetReset1( uint32_t u32EachPeri1 )
+{
+   uint32_t    i;
+
+   SCUCG->PPRST1 = u32EachPeri1;    // Reset a peripheral block
+   for( i = 0 ; i < 10 ; i++ )
+   {
+      NOP();
+   }
+   SCUCG->PPRST1 = 0;               // Clear the peripheral reset bit
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set/Reset Each Peripheral Block Reset of PPRST2 Register
+ * @param[in]     u32EachPeri2
+ *                   Peri2
+ *                   -  PPRST2_FMCRST, PPRST2_LVIRST, PPRST2_WTRST, PPRST2_LCDRST
+ *                   -  PPRST2_CRRST, PPRST2_ADRST, PPRST2_I2C0RST ~ PPRST2_I2C2RST
+ *                   -  PPRST2_UT0RST ~ PPRST2_UT1RST, PPRST2_UST10RST ~ PPRST2_UST13RST
+ * @details       This function resets each peripheral block.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_Peripheral_SetReset2( uint32_t u32EachPeri2 )
+{
+   uint32_t    i;
+
+   SCUCG->PPRST2 = u32EachPeri2;    // Reset a peripheral block
+   for( i = 0 ; i < 10 ; i++ )
+   {
+      NOP();
+   }
+   SCUCG->PPRST2 = 0;               // Clear the peripheral reset bit
+}
+
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Peripheral Clock Selection of PPCLKSR Register
+ * @param[in]     u32Peri
+ *                   Peripheral Selection
+ *                   -  PPCLKSR_T20CLK, PPCLKSR_T30CLK, PPCLKSR_LCDCLK, PPCLKSR_WTCLK, PPCLKSR_WDTCLK
+ * @param[in]     u32ClkSrc
+ *                   Peripheral Clock Selection
+ *                   -  PPCLKSR_T20CLK:   T20CLK_XSOSC, T20CLK_PCLK
+ *                   -  PPCLKSR_T30CLK:   T30CLK_MCLK, T30CLK_PCLK
+ *                   -  PPCLKSR_LCDCLK:   LCDCLK_DividedMCLK, LCDCLK_XSOSC, LCDCLK_WDTRC
+ *                   -  PPCLKSR_WTCLK:    WTCLK_DividedMCLK, WTCLK_XSOSC, WTCLK_WDTRC
+ *                   -  PPCLKSR_WDTCLK:   WDTCLK_WDTRC, WDTCLK_PCLK
+ * @details       This function resets each peripheral block.
+ *//*-------------------------------------------------------------------------*/
+void HAL_SCU_Peripheral_ClockSelection( uint32_t u32Peri, uint32_t u32ClkSrc )
+{
+   SCUCG->PPCLKSR &= ~u32Peri;
+   SCUCG->PPCLKSR |= u32ClkSrc;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_sculv.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_sculv.c
new file mode 100644
index 0000000..513d5f9
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_sculv.c
@@ -0,0 +1,80 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_sculv.c
+* @brief    Contains all functions support for sculv firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_sculv.h"
+#include "A31G12x_hal_scu.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set LVI Block Enable/Disable and Voltage Level
+ * @param[in]     u32LviEnBit
+ *                   LVI Enable/Disable Control
+ *                   -  LVIEN_Disable, LVIEN_Enable
+ * @param[in]     u32LviIntEnBit
+ *                   LVI Interrupt Enable/Disable Control
+ *                   -  LVINTEN_Disable, LVINTEN_Enable
+ * @param[in]     u32LviLevel
+ *                   LVI Voltage Level
+ *                   -  LVIVS_2p00V    // 2.00V
+ *                   -  LVIVS_2p13V    // 2.13V
+ *                   -  LVIVS_2p28V    // 2.28V
+ *                   -  LVIVS_2p46V    // 2.46V
+ *                   -  LVIVS_2p67V    // 2.67V
+ *                   -  LVIVS_3p04V    // 3.04V
+ *                   -  LVIVS_3p20V    // 3.20V
+ *                   -  LVIVS_3p55V    // 3.55V
+ *                   -  LVIVS_3p75V    // 3.75V
+ *                   -  LVIVS_3p99V    // 3.99V
+ *                   -  LVIVS_4p25V    // 4.25V
+ *                   -  LVIVS_4p55V    // 4.55V
+ * @return        None
+ * @details       This function sets LVI voltage level.
+ *//*-------------------------------------------------------------------------*/
+void HAL_LVI_Init( uint32_t u32LviEnBit, uint32_t u32LviIntEnBit, uint32_t u32LviLevel )
+{
+   // enable peripheral clock
+   HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_LVICLKE, PPxCLKE_Enable );
+
+   SCULV->LVICR = ( u32LviEnBit | u32LviIntEnBit | u32LviLevel );
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer1n.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer1n.c
new file mode 100644
index 0000000..09997bf
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer1n.c
@@ -0,0 +1,360 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_timer1n.c
+* @brief    Contains all functions support for timer1n firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_scu.h"
+#include "A31G12x_hal_timer1n.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the TIMER1n peripheral with the specified parameters.
+ *                   -  Set Clock frequency for Timer
+ *                   -  Set initial configuration for Timer
+ * @param[in]     TIMER1x
+ *                   Pointer to the target TIMER1
+ *                   -  TIMER10 ~ TIMER16
+ * @param[in]     TimerCounterMode
+ *                   Timer Counter Mode
+ *                   -  TIMER1n_PERIODIC_MODE:  Timer mode
+ *                   -  TIMER1n_PWM_MODE:       Counter rising mode
+ *                   -  TIMER1n_ONESHOT_MODE:   Counter falling mode
+ *                   -  TIMER1n_CAPTURE_MODE:   Counter on both edges
+ * @param[in]     TIMER1n_Config
+ *                   Pointer to the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER1n_Init( TIMER1n_Type* TIMER1x, TIMER1n_MODE_OPT TimerCounterMode, void* TIMER1n_Config )
+{
+   TIMER1n_PERIODICCFG_Type*     pTimeCfg;
+   TIMER1n_PWMCFG_Type*          pPwmOneshotCfg;
+   TIMER1n_CAPTURECFG_Type*      pCaptureCfg;
+   uint16_t                      reg_val16;
+
+   /* Check TIMER1 handle */
+   if( TIMER1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER10 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T10CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER11 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T11CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER12 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T12CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER13 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T13CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER14 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T14CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER15 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T15CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER16 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T16CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+   if( TimerCounterMode == TIMER1n_PERIODIC_MODE )
+   {
+      pTimeCfg = ( TIMER1n_PERIODICCFG_Type* )TIMER1n_Config;
+
+      reg_val16 = 0
+                  | TIMER1n_CR_CKSEL_SET( pTimeCfg->CkSel )
+                  | TIMER1n_CR_MODE_SET( TimerCounterMode )
+                  | TIMER1n_CR_STARTLVL_SET( pTimeCfg->StartLevel )
+                  ;
+      if( pTimeCfg->CkSel == 1 )
+      {
+         reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pTimeCfg->ECE );
+      }
+      TIMER1x->CR = reg_val16;
+
+      TIMER1x->PREDR = ( ( pTimeCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
+      TIMER1x->ADR = pTimeCfg->ADR;
+   }
+   else if( ( TimerCounterMode == TIMER1n_PWM_MODE ) || ( TimerCounterMode == TIMER1n_ONESHOT_MODE ) )
+   {
+      pPwmOneshotCfg = ( TIMER1n_PWMCFG_Type* )TIMER1n_Config;
+
+      reg_val16 = 0
+                  | TIMER1n_CR_CKSEL_SET( pPwmOneshotCfg->CkSel )
+                  | TIMER1n_CR_MODE_SET( TimerCounterMode )
+                  | TIMER1n_CR_STARTLVL_SET( pPwmOneshotCfg->StartLevel )
+                  ;
+      if( pPwmOneshotCfg->CkSel == 1 )
+      {
+         reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pPwmOneshotCfg->ECE );
+      }
+      TIMER1x->CR = reg_val16;
+
+      TIMER1x->PREDR = ( ( pPwmOneshotCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
+      TIMER1x->ADR = pPwmOneshotCfg->ADR;
+      TIMER1x->BDR = pPwmOneshotCfg->BDR;
+   }
+   else if( TimerCounterMode == TIMER1n_CAPTURE_MODE )
+   {
+      pCaptureCfg = ( TIMER1n_CAPTURECFG_Type* )TIMER1n_Config;
+
+      reg_val16 = 0
+                  | TIMER1n_CR_CKSEL_SET( pCaptureCfg->CkSel )
+                  | TIMER1n_CR_MODE_SET( TimerCounterMode )
+                  | TIMER1n_CR_CPOL_SET( pCaptureCfg->ClrMode )
+                  ;
+      if( pCaptureCfg->CkSel == 1 )
+      {
+         reg_val16 = reg_val16 | TIMER1n_CR_ECE_SET( pCaptureCfg->ECE );
+      }
+      TIMER1x->CR = reg_val16;
+
+      TIMER1x->PREDR = ( ( pCaptureCfg->Prescaler - 1 ) & TIMER1n_PRS_MASK );
+      TIMER1x->ADR = pCaptureCfg->ADR;
+   }
+   TIMER1x->CR |= 0x1; //  timer counter clear
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Close Timer/Counter device
+ * @param[in]     TIMER1x
+ *                   Pointer to the target TIMER1
+ *                   -  TIMER10 ~ TIMER16
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER1n_DeInit( TIMER1n_Type* TIMER1x )
+{
+   /* Check TIMER1 handle */
+   if( TIMER1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   // Disable timer/counter
+   TIMER1x->CR = 0x00;
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER10 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T10CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER11 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T11CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER12 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T12CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER13 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T13CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER14 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T14CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER15 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T15CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER1x == ( TIMER1n_Type* )TIMER16 )
+   {
+      HAL_SCU_Peripheral_EnableClock1( PPCLKEN1_T16CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure the peripheral interrupt.
+ * @param[in]     TIMER1x
+ *                   Pointer to the target TIMER1
+ *                   -  TIMER10 ~ TIMER16
+ * @param[in]     TIMER1n_IntCfg
+ *                   Specifies the interrupt flag
+ *                   -  TIMER1n_INTCFG_MIE:  OVIE Interrupt enable
+ *                   -  TIMER1n_INTCFG_CIE:  MBIE Interrupt enable
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER1n_ConfigInterrupt( TIMER1n_Type* TIMER1x, TIMER1n_INT_Type TIMER1n_IntCfg, FunctionalState NewState )
+{
+   uint8_t     tmp;
+
+   /* Check TIMER1 handle */
+   if( TIMER1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   switch( TIMER1n_IntCfg )
+   {
+      case TIMER1n_INTCFG_MIE:
+         tmp = TIMER1n_MATINTEN;
+         break;
+      case TIMER1n_INTCFG_CIE:
+         tmp = TIMER1n_CAPINTEN;
+         break;
+   }
+
+   if( NewState == ENABLE )
+   {
+      TIMER1x->CR |= tmp;
+   }
+   else
+   {
+      TIMER1x->CR &= ( ~tmp );
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Start/Stop Timer/Counter device
+ * @param[in]     TIMER1x
+ *                   Pointer to the target TIMER1
+ *                   -  TIMER10 ~ TIMER16
+ * @param[in]     NewState
+ *                   Next State of Functional Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER1n_Cmd( TIMER1n_Type* TIMER1x, FunctionalState NewState )
+{
+   /* Check TIMER1 handle */
+   if( TIMER1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   if( NewState == ENABLE )
+   {
+      TIMER1x->CR |=  TIMER1n_ENABLE;
+   }
+   else
+   {
+      TIMER1x->CR &= ~TIMER1n_ENABLE;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set TIMER1n CR/PREDR Registers
+ * @param[in]     TIMER1x
+ *                   Pointer to the target TIMER1
+ *                   -  TIMER10 ~ TIMER16
+ * @param[in]     u32T1nSet
+ *                   TIMER1n Control Register Setting Data
+ * @param[in]     u32T1nClk
+ *                   TIMER1n Prescaler Data
+ * @return        @ref HAL_Status_Type
+ * @details       This function sets the mode, external clock edge, Timer out polarity,
+ *                Capture Polarity and Timer match/capture interrupt.
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER1n_SetRegister( TIMER1n_Type* TIMER1x, uint32_t u32T1nSet, uint32_t u32T1nClk )
+{
+   /* Check TIMER1 handle */
+   if( TIMER1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER1x->CR = u32T1nSet;      // Setting TIMER1n Control Register
+
+   TIMER1x->PREDR = u32T1nClk;   // Setting TIMER1n Prescaler data
+
+   return HAL_OK;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer2n.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer2n.c
new file mode 100644
index 0000000..fad6eea
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer2n.c
@@ -0,0 +1,357 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_timer2n.c
+* @brief    Contains all functions support for timer2n firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_timer2n.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the TIMER2n peripheral with the specified parameters.
+ *                   -  Set Clock frequency for Timer
+ *                   -  Set initial configuration for Timer
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @param[in]     TimerCounterMode
+ *                   Timer Counter Mode
+ *                   -  TIMER2n_PERIODIC_MODE:  Timer mode
+ *                   -  TIMER2n_PWM_MODE:       Counter rising mode
+ *                   -  TIMER2n_ONESHOT_MODE:   Counter falling mode
+ *                   -  TIMER2n_CAPTURE_MODE:   Counter on both edges
+ * @param[in]     TIMER2n_Config
+ *                   Pointer to the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER2n_Init( TIMER2n_Type* TIMER2x, TIMER2n_MODE_OPT TimerCounterMode, void* TIMER2n_Config )
+{
+   TIMER2n_PERIODICCFG_Type*     pTimeCfg;
+   TIMER2n_PWMCFG_Type*          pPwmOneshotCfg;
+   TIMER2n_CAPTURECFG_Type*      pCaptureCfg;
+   uint16_t                      reg_val16;
+
+   /* Check TIMER2 handle */
+   if( TIMER2x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+#if 1    // supported
+   if( TIMER2x == ( TIMER2n_Type* )TIMER20 )
+   {
+      SCUCG->PPCLKEN1_b.T20CLKE = 1;
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER2x == ( TIMER2n_Type* )TIMER21 )
+   {
+      SCUCG->PPCLKEN1_b.T21CLKE = 1;
+   }
+#endif
+
+   if( TimerCounterMode == TIMER2n_PERIODIC_MODE )
+   {
+      pTimeCfg = ( TIMER2n_PERIODICCFG_Type* )TIMER2n_Config;
+
+      SCUCG->PPCLKSR_b.T20CLK = pTimeCfg->TCLK_SEL;
+      reg_val16 = 0
+                  | ( TimerCounterMode << 12 )
+                  | TIMER2n_CR_CLK_SET( pTimeCfg->CkSel )
+                  | TIMER2n_CR_ECE_SET( pTimeCfg->ExtCkEdge )
+                  | TIMER2n_CR_OPOL_SET( pTimeCfg->StartLevel )
+                  | TIMER2n_CR_CPOL_SET( pTimeCfg->CapEdge )
+                  ;
+      TIMER2x->CR = reg_val16;
+      TIMER2x->PREDR = ( ( pTimeCfg->Prescaler - 1 ) & TIMER2n_PREDR_MASK );
+      TIMER2x->ADR = pTimeCfg->ADR;
+      TIMER2x->BDR = pTimeCfg->BDR;
+   }
+   else if( ( TimerCounterMode == TIMER2n_PWM_MODE ) || ( TimerCounterMode == TIMER2n_ONESHOT_MODE ) )
+   {
+      pPwmOneshotCfg = ( TIMER2n_PWMCFG_Type* )TIMER2n_Config;
+
+      SCUCG->PPCLKSR_b.T20CLK = pPwmOneshotCfg->TCLK_SEL;
+      reg_val16 = 0
+                  | ( TimerCounterMode << 12 )
+                  | TIMER2n_CR_CLK_SET( pPwmOneshotCfg->CkSel )
+                  | TIMER2n_CR_ECE_SET( pPwmOneshotCfg->ExtCkEdge )
+                  | TIMER2n_CR_OPOL_SET( pPwmOneshotCfg->StartLevel )
+                  | TIMER2n_CR_CPOL_SET( pPwmOneshotCfg->CapEdge )
+                  ;
+      TIMER2x->CR = reg_val16;
+      TIMER2x->PREDR = ( ( pPwmOneshotCfg->Prescaler - 1 ) & TIMER2n_PREDR_MASK );
+      TIMER2x->ADR = pPwmOneshotCfg->ADR;
+      TIMER2x->BDR = pPwmOneshotCfg->BDR;
+   }
+   else if( TimerCounterMode == TIMER2n_CAPTURE_MODE )
+   {
+      pCaptureCfg = ( TIMER2n_CAPTURECFG_Type* )TIMER2n_Config;
+
+      SCUCG->PPCLKSR_b.T20CLK = pCaptureCfg->TCLK_SEL;
+      reg_val16 = 0
+                  | ( TimerCounterMode << 12 )
+                  | TIMER2n_CR_CLK_SET( pCaptureCfg->CkSel )
+                  | TIMER2n_CR_CPOL_SET( pCaptureCfg->ClrMode )
+                  | TIMER2n_CR_CAPSEL_SET( pCaptureCfg->CAPCkSel )
+                  ;
+      TIMER2x->CR = reg_val16;
+      TIMER2x->PREDR = ( ( pCaptureCfg->Prescaler - 1 ) & TIMER2n_PREDR_MASK );
+   }
+
+   TIMER2x->CR_b.T2nCLR = TIMER2n_CLEAR;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Close Timer/Counter device
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER2n_DeInit( TIMER2n_Type* TIMER2x )
+{
+   /* Check TIMER2 handle */
+   if( TIMER2x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   // Disable timer/counter
+   TIMER2x->CR_b.T2nEN = 0;
+
+#if 1    // supported
+   if( TIMER2x == ( TIMER2n_Type* )TIMER20 )
+   {
+      SCUCG->PPCLKEN1_b.T20CLKE = 0;
+   }
+#endif
+
+#if 1    // supported
+   if( TIMER2x == ( TIMER2n_Type* )TIMER21 )
+   {
+      SCUCG->PPCLKEN1_b.T21CLKE = 0;
+   }
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure the peripheral interrupt.
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @param[in]     TIMER2n_IntCfg
+ *                   Specifies the interrupt flag
+ *                   -  TIMER2n_CR_MATCH_INTR:     Match interrupt enable
+ *                   -  TIMER2n_CR_CAPTURE_INTR:   Capture interrupt enable
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER2n_ConfigInterrupt( TIMER2n_Type* TIMER2x, TIMER2n_INT_Type TIMER2n_IntCfg, FunctionalState NewState )
+{
+   /* Check TIMER2 handle */
+   if( TIMER2x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   switch( TIMER2n_IntCfg )
+   {
+      case TIMER2n_CR_MATCH_INTR:
+         if( NewState == ENABLE )
+         {
+            TIMER2x->CR_b.T2nMIEN = 1;
+         }
+         else if( NewState == DISABLE )
+         {
+            TIMER2x->CR_b.T2nMIEN = 0;
+         }
+         break;
+      case TIMER2n_CR_CAPTURE_INTR:
+         if( NewState == ENABLE )
+         {
+            TIMER2x->CR_b.T2nCIEN = 1;
+         }
+         else if( NewState == DISABLE )
+         {
+            TIMER2x->CR_b.T2nCIEN = 0;
+         }
+         break;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Start/Stop Timer/Counter device
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @param[in]     NewState
+ *                   Next State of Functional Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER2n_Cmd( TIMER2n_Type* TIMER2x, FunctionalState NewState )
+{
+   /* Check TIMER2 handle */
+   if( TIMER2x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   if( NewState == ENABLE )
+   {
+      TIMER2x->CR_b.T2nEN = TIMER2n_ENABLE;
+   }
+   else
+   {
+      TIMER2x->CR_b.T2nEN = TIMER2n_DISABLE;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear Timer/Counter device,
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER2n_ClearCounter( TIMER2n_Type* TIMER2x )
+{
+   /* Check TIMER2 handle */
+   if( TIMER2x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER2x->CR_b.T2nCLR |= TIMER2n_CLEAR;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Update value
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @param[in]     CountCh
+ *                   -  0 = GRA
+ *                   -  1 = GRB
+ * @param[in]     Value
+ *                   updated match value
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER2n_UpdateCountValue( TIMER2n_Type* TIMER2x, uint8_t CountCh, uint16_t Value )
+{
+   /* Check TIMER2 handle */
+   if( TIMER2x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   switch( CountCh )
+   {
+      case 0:
+         TIMER2x->ADR = Value;
+         break;
+      case 1:
+         TIMER2x->BDR = Value;
+         break;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear Timer Status
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @param[in]     value
+ *                   clear value
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER2n_ClearStatus( TIMER2n_Type* TIMER2x, uint8_t value )
+{
+   /* Check TIMER2 handle */
+   if( TIMER2x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER2x->CR |= ( 0xD & value );
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Timer Status
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @return        Value of status register
+ *//*-------------------------------------------------------------------------*/
+uint8_t HAL_TIMER2n_GetStatus( TIMER2n_Type* TIMER2x )
+{
+   return TIMER2x->CR;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Read value of capture register in timer/counter device
+ * @param[in]     TIMER2x
+ *                   Pointer to the target TIMER2
+ *                   -  TIMER20 ~ TIMER21
+ * @return        Value of count register
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_TIMER2n_GetCaptureData( TIMER2n_Type* TIMER2x )
+{
+   return TIMER2x->CAPDR;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer3n.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer3n.c
new file mode 100644
index 0000000..ef073e1
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_timer3n.c
@@ -0,0 +1,498 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_timer3n.c
+* @brief    Contains all functions support for timer3n firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_timer3n.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the TIMER3n peripheral with the specified parameters.
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     TIMER3n_Config
+ *                   Pointer to the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_Init( TIMER3n_Type* TIMER3x, TIMER3n_CFG_Type* TIMER3n_Config )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+#if 1    // supported
+   if( TIMER3x == ( TIMER3n_Type* )TIMER30 )
+   {
+      // enable peripheral clock
+      SCUCG->PPCLKEN1_b.T30CLKE = 1;
+   }
+#endif
+
+#if 0    // not supported
+   if( TIMER3x == ( TIMER3n_Type* )TIMER31 )
+   {
+      // enable peripheral clock
+      SCUCG->PPCLKEN1_b.T31CLKE = 1;
+   }
+#endif
+
+   // CR
+   TIMER3x->CR =  0
+                  | ( TIMER3n_Config->T3nMS  << TIMER3n_CR_T3nMS_Pos )
+                  | ( TIMER3n_Config->T3nCLK << TIMER3n_CR_T3nCLK_Pos )
+                  | ( TIMER3n_Config->T3nECE << TIMER3n_CR_T3nECE_Pos )
+                  | ( TIMER3n_Config->T3nCPOL << TIMER3n_CR_T3nCPOL_Pos )
+                  ;
+
+   // PDR
+   TIMER3x->PDR = TIMER3n_Config->PDR;
+
+   // ADR & BDR & CDR
+   TIMER3x->ADR = TIMER3n_Config->ADR;
+   TIMER3x->BDR = TIMER3n_Config->BDR;
+   TIMER3x->CDR = TIMER3n_Config->CDR;
+
+   // PREDR
+   TIMER3x->PREDR = TIMER3n_Config->Prescaler;
+
+   // clear counter and prescaler
+   TIMER3n_ClearCounter( TIMER3x );
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Close Timer/Counter device
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_DeInit( TIMER3n_Type* TIMER3x )
+{
+   /* Check TIMER2 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   // Disable timer/counter
+   TIMER3x->CR_b.T3nEN = 0;
+
+#if 1    // supported
+   if( TIMER3x == ( TIMER3n_Type* )TIMER30 )
+   {
+      // disable peripheral clock
+      SCUCG->PPCLKEN1_b.T30CLKE = 0;
+   }
+#endif
+
+#if 0    // not supported
+   if( TIMER3x == ( TIMER3n_Type* )TIMER31 )
+   {
+      // disable peripheral clock
+      SCUCG->PPCLKEN1_b.T31CLKE = 0;
+   }
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Interrupt Control Register
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @param[in]     USART3n_IntCfg
+ *                   Interrupt Sourtce Setting
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_ConfigInterrupt( TIMER3n_Type* TIMER3x, uint32_t NewState, uint32_t USART3n_IntCfg )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   if( NewState == ENABLE )
+   {
+      TIMER3x->INTCR |= USART3n_IntCfg;
+   }
+   else
+   {
+      TIMER3x->INTCR &= ( ~USART3n_IntCfg ) & 0x7f;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         TIMER3n PWM Mode Setting (Initial : Back to Back Mode, Internal Clock, 6channel Mode)
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     updatedata
+ *                   PWM Duty Update Timing
+ * @param[in]     intcount
+ *                   Period Match Interrupt Occurence Seletion
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_MPWMCmd( TIMER3n_Type* TIMER3x, uint32_t updatedata, uint32_t intcount )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->CR = 0
+                 | TIMER3n_CLKINT
+                 | TIMER3n_BTOB
+                 | TIMER3n_6CHMOD
+                 | updatedata
+                 | intcount
+                 | 1             // Clear TIMER3n & Precaler
+                 ;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable or Disable PWM start
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     NewState
+ *                   Next State of Functional Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_Start( TIMER3n_Type* TIMER3x, uint32_t NewState )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   if( NewState == TIMER3n_ENABLE )
+   {
+      TIMER3x->CR |= TIMER3n_ENABLE;
+   }
+   else
+   {
+      TIMER3x->CR &= ~TIMER3n_ENABLE;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         PWM Output Port Control Register (Initial : 6channel enable, output low)
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     NewState
+ *                   Next State of Functional Operation
+ *                   -  ENABLE, DISABLE
+ * @param[in]     pwmApol
+ *                   Timer 30xA Output Polarity Selection
+ * @param[in]     pwmBpol
+ *                   Timer 30xB Output Polarity Selection
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_OutputCtrl( TIMER3n_Type* TIMER3x,  uint32_t NewState, uint32_t pwmApol, uint32_t pwmBpol )
+{
+   uint32_t    temp;
+
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   temp = 0
+          | ( ( uint32_t )TIMER30_T30_OUTCR_WTIDKY_Value << TIMER30_OUTCR_WTIDKY_Pos )
+          | ( pwmApol | pwmBpol )
+          ;
+   if( NewState == ENABLE )
+   {
+      temp |= ( 0x3f << 8 );
+   }
+
+   TIMER3x->OUTCR = temp;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set Prescaler data.
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     prescale
+ *                   Timer30 Prescaler Value
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_ClockPrescaler( TIMER3n_Type* TIMER3x, uint32_t prescale )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->PREDR = ( prescale & 0x0fff ); // period. it sould be larger than 0x10
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set period data.
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     period
+ *                   MPWM period data
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_SetPeriod( TIMER3n_Type* TIMER3x, uint32_t period )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->PDR = ( period & 0xffff ); // period. it sould be larger than 0x10
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set duty A data.
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     aduty
+ *                   Timer30 Aduty data
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_SetADuty( TIMER3n_Type* TIMER3x, uint32_t aduty )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->ADR = ( ( aduty ) & 0xffff ); // if using I/O control function, set period data
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set duty B data.
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     bduty
+ *                   Timer30 Bduty data
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_SetBDuty( TIMER3n_Type* TIMER3x, uint32_t bduty )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->BDR = ( ( bduty ) & 0xffff ); // if using I/O control function, set period data
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set duty C data.
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     cduty
+ *                   Timer30 Cduty data
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_SetCDuty( TIMER3n_Type* TIMER3x, uint32_t cduty )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->CDR = ( ( cduty ) & 0xffff ); // if using I/O control function, set period data
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set dead time (delay time)
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     dten
+ *                   dead time enable
+ * @param[in]     dtpos
+ *                   dead timer position (front or back)
+ * @param[in]     clkdata
+ *                   dead time
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_SetDelayTime( TIMER3n_Type* TIMER3x, uint32_t dten, uint32_t dtpos, uint32_t clkdata )
+{
+   uint32_t    temp;
+
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   temp = TIMER3x->CR;
+   temp &= ~( 0x03 << 8 );
+   temp |= dten | dtpos;
+   TIMER3x->CR = temp;
+
+   TIMER3x->DLY = clkdata & 0x03ff;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set HIZCR Register
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     u32T30HizSet
+ *                   Timer 30 Output High-Impedance Setting Data
+ * @return        @ref HAL_Status_Type
+ * @details       This function sets the Timer 30 HIZ/ADT Control Register
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_SetHizReg( TIMER3n_Type* TIMER3x, uint32_t u32T30HizSet )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->HIZCR = u32T30HizSet;  //Setting Timer 30 High-Impedance Control Register
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set ADC Tirgger Source & Timing
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     u32triggerpoint
+ *                   Timer 30 Output High-Impedance Setting Data
+ * @param[in]     u32triggertime
+ *                   Timer 30 A/DC Trigger Setting Data
+ * @return        @ref HAL_Status_Type
+ * @details       This function sets the Timer 30 HIZ/ADT Control Register
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_SetADCTrigger( TIMER3n_Type* TIMER3x, uint32_t u32triggerpoint, uint32_t u32triggertime )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->ADTCR = u32triggerpoint;  //Setting Timer 30 A/DC Trigger Control Register
+   TIMER3x->ADTDR = u32triggertime;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Interrupt Flag Clear
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @param[in]     USART3n_IntCfg
+ *                   Select clear interrupt
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_TIMER3n_ClearStatus_IT( TIMER3n_Type* TIMER3x, uint32_t USART3n_IntCfg )
+{
+   /* Check TIMER3 handle */
+   if( TIMER3x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   TIMER3x->INTFLAG = USART3n_IntCfg;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get Interrupt Flag
+ * @param[in]     TIMER3x
+ *                   Pointer to the target TIMER3
+ *                   -  TIMER30
+ * @return        Interrupt Flag
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_TIMER3n_GetStatus_IT( TIMER3n_Type* TIMER3x )
+{
+   return TIMER3x->INTFLAG;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_uartn.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_uartn.c
new file mode 100644
index 0000000..b9acd64
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_uartn.c
@@ -0,0 +1,671 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_uartn.c
+* @brief    Contains all functions support for uartn firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_scu.h"
+#include "A31G12x_hal_uartn.h"
+
+//******************************************************************************
+// Variable
+//******************************************************************************
+
+static uint32_t      UARTn_BaseClock;
+
+char                 InData[80];
+int                  InFlag;
+int                  InCount;
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Determines best dividers to get a target clock rate
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     baudrate
+ *                   Desired baudrate
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+static void uart_set_divisors( UARTn_Type* UARTx, uint32_t baudrate )
+{
+   uint32_t    numerator;
+   uint32_t    denominator;
+   uint32_t    bdr, bfr;
+   uint32_t    fd;
+
+   //--------------------------------------
+   // bdr = UARTn_BaseClock / (16 * baudrate * 2)
+   //--------------------------------------
+   numerator = UARTn_BaseClock;
+   denominator = 16 * baudrate * 2;
+   bdr = numerator / denominator;
+
+   //--------------------------------------
+   // fd = numerator - bdr * denominator
+   // bfr = (numerator / denominator - bdr) * 256
+   //     = (numerator - bdr * denominator) * 256 / denominator
+   //     = fd * 256 / denominator
+   //--------------------------------------
+   fd = numerator - bdr * denominator;
+   bfr = ( fd * 256 ) / denominator;
+   UARTx->BDR = ( uint16_t )( bdr & 0xffff );
+   UARTx->BFR = ( uint8_t )( bfr & 0xff );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the UARTn peripheral with the specified parameters.
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     UARTn_Config
+ *                   Pointer to a UARTn_CFG_Type structure
+ *                   that contains the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_UART_Init( UARTn_Type* UARTx, UARTn_CFG_Type* UARTn_Config )
+{
+   uint8_t     tmp;
+
+   /* Check UART handle */
+   if( UARTx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+#if 1    // supported
+   if( UARTx == ( UARTn_Type* )UART0 )
+   {
+      /* Set up peripheral clock for UART0 module */
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT0CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+#if 1    // supported
+   if( UARTx == ( UARTn_Type* )UART1 )
+   {
+      /* Set up peripheral clock for UART1 module */
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT1CLKE, PPxCLKE_Enable );
+   }
+#endif
+
+   // Dummy reading
+   while( UARTx->LSR & UARTn_LSR_RDR )
+   {
+      tmp = UARTx->RBR;
+   }
+   // Wait for current transmit complete
+   while( !( UARTx->LSR & UARTn_LSR_THRE ) );
+
+   // Disable interrupt
+   UARTx->IER = 0;
+   // Set LCR, DCR to default state
+   UARTx->LCR = 0;
+   UARTx->DCR = 0;
+   // Dummy reading
+   tmp = UARTx->LSR;
+   tmp = UARTx->IIR;
+
+   // uart clock set
+   // SCU->MCCR7 &=0xffff0000;
+   // SCU->MCCR7 |=((4<<8)|(2)); // MCLK
+   UARTn_BaseClock = SystemPeriClock;
+
+   // Set Line Control register ----------------------------
+   uart_set_divisors( UARTx, ( UARTn_Config->Baudrate ) );
+
+   tmp = ( UARTx->LCR & UARTn_LCR_BREAK_EN ) & UARTn_LCR_BITMASK;
+
+   switch( UARTn_Config->Databits )
+   {
+      case UARTn_DATA_BIT_5:
+         tmp |= UARTn_LCR_WLEN5;
+         break;
+      case UARTn_DATA_BIT_6:
+         tmp |= UARTn_LCR_WLEN6;
+         break;
+      case UARTn_DATA_BIT_7:
+         tmp |= UARTn_LCR_WLEN7;
+         break;
+      case UARTn_DATA_BIT_8:
+      default:
+         tmp |= UARTn_LCR_WLEN8;
+         break;
+   }
+
+   if( UARTn_Config->Parity == UARTn_PARITY_BIT_NONE )
+   {
+      // Do nothing...
+   }
+   else
+   {
+      tmp |= UARTn_LCR_PARITY_EN;
+      switch( UARTn_Config->Parity )
+      {
+         case UARTn_PARITY_BIT_ODD:
+            tmp |= UARTn_LCR_PARITY_ODD;
+            break;
+
+         case UARTn_PARITY_BIT_EVEN:
+            tmp |= UARTn_LCR_PARITY_EVEN;
+            break;
+
+         case UARTn_PARITY_BIT_SP_1:
+            tmp |= UARTn_LCR_PARITY_F_1;
+            break;
+
+         case UARTn_PARITY_BIT_SP_0:
+            tmp |= UARTn_LCR_PARITY_F_0;
+            break;
+         default:
+            break;
+      }
+   }
+
+   switch( UARTn_Config->Stopbits )
+   {
+      case UARTn_STOP_BIT_2:
+         tmp |= UARTn_LCR_STOPBIT_SEL;
+         break;
+      case UARTn_STOP_BIT_1:
+      default:
+         // Do no thing
+         break;
+   }
+
+   UARTx->LCR = ( uint8_t )( tmp & UARTn_LCR_BITMASK );
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Deinitialize the UARTn peripheral registers to their default reset values.
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_UART_DeInit( UARTn_Type* UARTx )
+{
+   /* Check UART handle */
+   if( UARTx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+#if 1    // supported
+   if( UARTx == ( UARTn_Type* )UART0 )
+   {
+      /* Set up peripheral clock for UART0 module */
+      HAL_SCU_Peripheral_SetReset2( 1 << 2 );
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT0CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( UARTx == ( UARTn_Type* )UART1 )
+   {
+      /* Set up peripheral clock for UART1 module */
+      HAL_SCU_Peripheral_SetReset2( 1 << 3 );
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UT1CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Fills each UARTn_Config member with its default value:
+ *                   -  38400 bps
+ *                   -  8 Data Bit
+ *                   -  No Parity Bit
+ *                   -  1 Stop Bit
+ * @param[out]    UARTn_Config
+ *                   Pointer to a UARTn_CFG_Type structure which will be initialized.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_UART_ConfigStructInit( UARTn_CFG_Type* UARTn_Config )
+{
+   /* Check UARTn_Config */
+   if( UARTn_Config == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   UARTn_Config->Baudrate = 38400;
+   UARTn_Config->Databits = UARTn_DATA_BIT_8;
+   UARTn_Config->Parity = UARTn_PARITY_BIT_NONE;
+   UARTn_Config->Stopbits = UARTn_STOP_BIT_1;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure the peripheral interrupt.
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     UARTn_IntCfg
+ *                   Specifies the interrupt flag
+ *                   -  UARTn_INTCFG_RBR:    RBR Interrupt enable
+ *                   -  UARTn_INTCFG_THRE:   THR Interrupt enable
+ *                   -  UARTn_INTCFG_RLS:    RX line status interrupt enable
+ *                   -  UARTn_INTCFG_DRX:    THR Interrupt enable
+ *                   -  UARTn_INTCFG_DTX:    RX line status interrupt enable
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_UART_ConfigInterrupt( UARTn_Type* UARTx, UARTn_INT_Type UARTn_IntCfg, FunctionalState NewState )
+{
+   uint32_t    tmp;
+
+   /* Check UART handle */
+   if( UARTx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   switch( UARTn_IntCfg )
+   {
+      case UARTn_INTCFG_RBR:
+         tmp = UARTn_IER_RBRINT_EN;
+         break;
+      case UARTn_INTCFG_THRE:
+         tmp = UARTn_IER_THREINT_EN;
+         break;
+      case UARTn_INTCFG_RLS:
+         tmp = UARTn_IER_RLSINT_EN;
+         break;
+      case UARTn_INTCFG_TXE:
+         tmp = UARTn_IER_TXE_EN;
+         break;
+   }
+
+   if( NewState == ENABLE )
+   {
+      UARTx->IER |= tmp;
+   }
+   else
+   {
+      UARTx->IER &= ( ~tmp ) & UARTn_IER_BITMASK;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure Data Control mode for UART peripheral
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ * @param[in]     Mode
+ *                   Data Control Mode
+ *                   -  UARTn_DATA_CONTROL_LOOPBACK:  Loop back mode.
+ *                   -  UARTn_DATA_CONTROL_RXINV:     RX Data inversion mode.
+ *                   -  UARTn_DATA_CONTROL_TXINV:     TX Data inversion mode.
+ *                   -  UARTn_DATA_CONTROL_RTXINV:    TX RX Data inversion mode.
+ * @param[in]     NewState
+ *                   Next State of Functional Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_UART_DataControlConfig( UARTn_Type* UARTx, UARTn_DATA_CONTROL_Type Mode, FunctionalState NewState )
+{
+   uint8_t     tmp;
+
+   /* Check UART handle */
+   if( UARTx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   switch( Mode )
+   {
+      case UARTn_DATA_CONTROL_LOOPBACK:
+         tmp = UARTn_DCR_LBON;
+         break;
+      case UARTn_DATA_CONTROL_RXINV:
+         tmp = UARTn_DCR_RXINV;
+         break;
+      case UARTn_DATA_CONTROL_TXINV:
+         tmp = UARTn_DCR_TXINV;
+         break;
+      case UARTn_DATA_CONTROL_RTXINV:
+         tmp = UARTn_DCR_RXINV | UARTn_DCR_TXINV;
+         break;
+      default:
+         break;
+   }
+
+   if( NewState == ENABLE )
+   {
+      UARTx->DCR |= tmp;
+   }
+   else
+   {
+      UARTx->DCR &= ( ~tmp ) & UARTn_DCR_BITMASK;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure inter-frame delay time for UART peripheral
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ * @param[in]     waitval
+ *                   inter-frame delay time: 1 bit time  unit (0~7)
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_UART_IFDelayConfig( UARTn_Type* UARTx, uint8_t waitval )
+{
+   /* Check UART handle */
+   if( UARTx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   if( waitval < 8 )
+   {
+      UARTx->IDTR = waitval;
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Force BREAK character on UART line, output pin UARTn TXD is
+ *                   forced to logic 0.
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_UART_ForceBreak( UARTn_Type* UARTx )
+{
+   /* Check UART handle */
+   if( UARTx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   UARTx->LCR |= UARTn_LCR_BREAK_EN;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         This function returns the current value of Line Status Register.
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @return        Current value of Line Status register in UART peripheral.
+ * @note          The return value of this function must be ANDed with each member in
+ *                UART_LS_Type enumeration to determine current flag status
+ *                corresponding to each Line status type. Because some flags in
+ *                Line Status register will be cleared after reading, the next reading
+ *                Line Status register could not be correct. So this function used to
+ *                read Line status register in one time only, then the return value
+ *                used to check all flags.
+ *//*-------------------------------------------------------------------------*/
+uint8_t HAL_UART_GetLineStatus( UARTn_Type* UARTx )
+{
+   return ( ( UARTx->LSR ) & UARTn_LSR_BITMASK );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Check whether if UART is busy or not
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @return        RESET if UART is not busy, otherwise return SET.
+ *//*-------------------------------------------------------------------------*/
+FlagStatus HAL_UART_CheckBusy( UARTn_Type* UARTx )
+{
+   if( UARTx->LSR & UARTn_LSR_TEMT )
+   {
+      return RESET;
+   }
+   else
+   {
+      return SET;
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Transmit a single data through UART peripheral
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     Data
+ *                   Data to transmit (must be 8-bit long)
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_UART_TransmitByte( UARTn_Type* UARTx, uint8_t Data )
+{
+   /* Check UART handle */
+   if( UARTx == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   UARTx->THR = Data;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Receive a single data from UART peripheral
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @return        Data received
+ *//*-------------------------------------------------------------------------*/
+uint8_t HAL_UART_ReceiveByte( UARTn_Type* UARTx )
+{
+   return UARTx->RBR;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Send a block of data via UART peripheral
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[in]     txbuf
+ *                   Pointer to Transmit buffer
+ * @param[in]     buflen
+ *                   Length of Transmit buffer
+ * @param[in]     flag
+ *                   Flag used in  UART transfer
+ *                   -  NONE_BLOCKING
+ *                   -  BLOCKING
+ * @return        Number of bytes sent.
+ * @note          when using UART in BLOCKING mode,
+ *                a time-out condition is used via defined symbol UARTn_BLOCKING_TIMEOUT.
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_UART_Transmit( UARTn_Type* UARTx, uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
+{
+   uint32_t    bToSend, bSent, timeOut;
+   uint8_t*    pChar = txbuf;
+
+   // init counter
+   bToSend = buflen;
+   bSent = 0;
+
+   // Blocking Mode
+   if( flag == BLOCKING )
+   {
+      while( bToSend )
+      {
+         // wait until tx data register is empty with timeout
+         timeOut = UARTn_BLOCKING_TIMEOUT;
+         while( !( UARTx->LSR & UARTn_LSR_THRE ) )
+         {
+            if( timeOut == 0 )
+            {
+               break;
+            }
+            timeOut--;
+         }
+
+         // if timeout
+         if( timeOut == 0 )
+         {
+            break;
+         }
+
+         // send byte
+         HAL_UART_TransmitByte( UARTx, ( *pChar++ ) );
+
+         // update counter
+         bToSend--;
+         bSent++;
+      }
+
+      // wait until previous transmission is complete
+      while( UARTx->LSR_b.TEMT == 0 );    // Polling Only
+   }
+
+   // Non-Blocking Mode
+   else
+   {
+      while( bToSend )
+      {
+         // if tx data register is not empty
+         if( !( UARTx->LSR & UARTn_LSR_THRE ) )
+         {
+            break;
+         }
+
+         // send byte
+         HAL_UART_TransmitByte( UARTx, ( *pChar++ ) );
+
+         // update counter
+         bToSend--;
+         bSent++;
+      }
+   }
+
+   // return
+   return bSent;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Receive a block of data via UART peripheral
+ * @param[in]     UARTx
+ *                   Pointer to the target UART
+ *                   -  UART0 ~ UART1
+ * @param[out]    rxbuf
+ *                   Pointer to Received buffer
+ * @param[in]     buflen
+ *                   Length of Received buffer
+ * @param[in]     flag
+ *                   Flag mode
+ *                   -  NONE_BLOCKING
+ *                   -  BLOCKING
+ * @return        Number of bytes received
+ * @note          when using UART in BLOCKING mode,
+ *                a time-out condition is used via defined symbol UARTn_BLOCKING_TIMEOUT.
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_UART_Receive( UARTn_Type* UARTx, uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
+{
+   uint32_t    bToRecv, bRecv, timeOut;
+   uint8_t*    pChar = rxbuf;
+
+   // init counter
+   bToRecv = buflen;
+   bRecv = 0;
+
+   // Blocking Mode
+   if( flag == BLOCKING )
+   {
+      while( bToRecv )
+      {
+         // wait until data are received with timeout
+         timeOut = UARTn_BLOCKING_TIMEOUT;
+         while( !( UARTx->LSR & UARTn_LSR_RDR ) )
+         {
+            if( timeOut == 0 )
+            {
+               break;
+            }
+            timeOut--;
+         }
+
+         // if timeout
+         if( timeOut == 0 )
+         {
+            break;
+         }
+
+         // receive byte
+         ( *pChar++ ) = HAL_UART_ReceiveByte( UARTx );
+
+         // update counter
+         bToRecv--;
+         bRecv++;
+      }
+   }
+
+   // Non-Blocking Mode
+   else
+   {
+      while( bToRecv )
+      {
+         // if no data were received
+         if( !( UARTx->LSR & UARTn_LSR_RDR ) )
+         {
+            break;
+         }
+
+         // receive byte
+         ( *pChar++ ) = HAL_UART_ReceiveByte( UARTx );
+
+         // update counter
+         bToRecv--;
+         bRecv++;
+      }
+   }
+
+   // return
+   return bRecv;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_usart1n.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_usart1n.c
new file mode 100644
index 0000000..e44a338
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_usart1n.c
@@ -0,0 +1,781 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_usart1n.c
+* @brief    Contains all functions support for usart1n firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_scu.h"
+#include "A31G12x_hal_usart1n.h"
+
+//******************************************************************************
+// Variable
+//******************************************************************************
+
+uint32_t    USART1n_BaseClock;
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Determines best dividers to get a target clock rate
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[in]     mode
+ *                   -  USART1n_UART_MODE
+ *                   -  USART1n_USRT_MODE
+ *                   -  USART1n_SPI_MODE
+ * @param[in]     baudrate
+ *                   Desired baudrate
+ * @return        None
+ *//*-------------------------------------------------------------------------*/
+static void usart_set_divisors( USART1n_Type* USART1x, uint32_t mode, uint32_t baudrate )
+{
+   uint32_t    numerator;
+   uint32_t    denominator;
+   uint32_t    n;
+   uint32_t    bdr;
+
+   if( mode == USART1n_UART_MODE )
+   {
+      // baudrate = PCLK / (16 * (bdr + 1))
+      // bdr = (PCLK / (16 * baudrate)) - 1
+      n = 16;
+   }
+   else
+   {
+      // baudrate = PCLK / (2 * (bdr + 1))
+      // bdr = (PCLK / (2 * baudrate)) - 1
+      n = 2;
+   }
+
+   //--------------------------------------
+   // numerator & denominator
+   //
+   // bdr = USART1n_BaseClock / n / baudrate  - 1
+   //--------------------------------------
+   numerator = USART1n_BaseClock;
+   denominator = baudrate;
+
+   bdr = numerator / n / denominator - 1;
+
+   USART1x->BDR = ( uint16_t )( bdr & 0xffff );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the USART1n peripheral with the specified parameters.
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[in]     USART1n_Config
+ *                   Pointer to a USART1n_CFG_Type structure
+ *                   that contains the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_Init( USART1n_Type* USART1x, USART1n_CFG_Type* USART1n_Config )
+{
+   uint32_t    tmp;
+
+   /* Check USART handle */
+   if( USART1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+#if 1    // supported
+   if( USART1x == ( USART1n_Type* )USART10 )
+   {
+      /* Set up peripheral clock for USART10 module */
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Enable );
+      HAL_SCU_Peripheral_SetReset2( 1 << 0 );
+   }
+#endif
+
+#if 1    // supported
+   if( USART1x == ( USART1n_Type* )USART11 )
+   {
+      /* Set up peripheral clock for USART11 module */
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Enable );
+      HAL_SCU_Peripheral_SetReset2( 1 << 1 );
+   }
+#endif
+
+#if 1    // supported
+   if( USART1x == ( USART1n_Type* )USART12 )
+   {
+      /* Set up peripheral clock for USART12 module */
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Enable );
+      HAL_SCU_Peripheral_SetReset2( 1 << 4 );
+   }
+#endif
+
+#if 1    // supported
+   if( USART1x == ( USART1n_Type* )USART13 )
+   {
+      /* Set up peripheral clock for USART13 module */
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Enable );
+      HAL_SCU_Peripheral_SetReset2( 1 << 5 );
+   }
+#endif
+
+   USART1n_BaseClock = SystemPeriClock;
+
+   usart_set_divisors( USART1x, USART1n_Config->Mode, USART1n_Config->Baudrate );
+
+   tmp = 0
+         | ( ( USART1n_Config->Mode & 0x3 ) << USART1n_CR1_USTnMS_Pos )
+         | ( ( USART1n_Config->Parity & 0x3 ) << USART1n_CR1_USTnP_Pos )
+         | ( ( USART1n_Config->Databits & 0x7 ) << USART1n_CR1_USTnS_Pos )
+         | ( ( USART1n_Config->Order & 0x1 ) << USART1n_CR1_ORDn_Pos )
+         | ( ( USART1n_Config->ACK & 0x1 ) << USART1n_CR1_CPOLn_Pos )
+         | ( ( USART1n_Config->Edge & 0x3 )  << USART1n_CR1_CPHAn_Pos )
+         | ( 1 << USART1n_CR1_TXEn_Pos )  // Tx Enable
+         | ( 1 << USART1n_CR1_RXEn_Pos )  // Rx Enable
+         ;
+
+   USART1x->CR1 = tmp;
+
+   USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnSB_Pos );     // USTnSB reset
+   USART1x->CR2 |= ( ( USART1n_Config->Stopbits & 0x1 ) << USART1n_CR2_USTnSB_Pos );    // USTnSB
+   USART1x->CR2 &= ~( 1 << USART1n_CR2_FXCHn_Pos );      // FXCHn reset
+   // USART1x->CR2 |= (1<<USART1n_CR2_FXCHn_Pos);        // FXCHn
+
+   HAL_USART_ClearStatus( USART1x, USART1n_STATUS_TXC );
+
+   // Dummy Read
+   tmp = HAL_USART_ReceiveByte( USART1x );
+   tmp = HAL_USART_ReceiveByte( USART1x );
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Deinitialize the USART1n peripheral registers to their default reset values.
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_DeInit( USART1n_Type* USART1x )
+{
+   /* Check USART handle */
+   if( USART1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+#if 1    // supported
+   if( USART1x == ( USART1n_Type* )USART10 )
+   {
+      /* Set up peripheral clock for USART10 module */
+      HAL_SCU_Peripheral_SetReset2( 1 << 0 );
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST10CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( USART1x == ( USART1n_Type* )USART11 )
+   {
+      /* Set up peripheral clock for USART11 module */
+      HAL_SCU_Peripheral_SetReset2( 1 << 1 );
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST11CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( USART1x == ( USART1n_Type* )USART12 )
+   {
+      /* Set up peripheral clock for USART12 module */
+      HAL_SCU_Peripheral_SetReset2( 1 << 4 );
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST12CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+#if 1    // supported
+   if( USART1x == ( USART1n_Type* )USART13 )
+   {
+      /* Set up peripheral clock for USART13 module */
+      HAL_SCU_Peripheral_SetReset2( 1 << 5 );
+      HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_UST13CLKE, PPxCLKE_Disable );
+   }
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Fills each USART_InitStruct member with its default value:
+ *                   -  38400 bps
+ *                   -  8 Data Bit
+ *                   -  No Parity Bit
+ *                   -  1 Stop Bit
+ * @param[out]    USART1n_Config
+ *                   Pointer to a USART1n_CFG_Type structure which will be initialized.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_UART_Mode_Config( USART1n_CFG_Type* USART1n_Config )
+{
+   /* Check USART1n_Config */
+   if( USART1n_Config == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   USART1n_Config->Mode = USART1n_UART_MODE;
+   USART1n_Config->Baudrate = 38400;
+   USART1n_Config->Databits = USART1n_DATA_BIT_8;
+   USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
+   USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Fills each USART_InitStruct member with its default value:
+ *                   -  38400 bps
+ *                   -  8 Data Bit
+ *                   -  No Parity Bit
+ *                   -  1 Stop Bit
+ * @param[out]    USART1n_Config
+ *                   Pointer to a USART1n_CFG_Type structure which will be initialized.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_USRT_Mode_Config( USART1n_CFG_Type* USART1n_Config )
+{
+   /* Check USART1n_Config */
+   if( USART1n_Config == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   USART1n_Config->Mode = USART1n_USRT_MODE;
+   USART1n_Config->Baudrate = 38400;
+   USART1n_Config->Databits = USART1n_DATA_BIT_8;
+   USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
+   USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
+
+   //only SPI & Sync. Mode
+   USART1n_Config->Order = USART1n_SPI_LSB;
+#if 0 // CPOLn : 0, CPHAn : 0 (X)
+   USART1n_Config->ACK = USART1n_SPI_TX_RISING;
+   USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
+#endif
+#if 1 // CPOLn : 0, CPHAn : 1 (O)
+   USART1n_Config->ACK = USART1n_SPI_TX_RISING;
+   USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
+#endif
+
+#if 0 // CPOLn : 1, CPHAn : 0 (X)
+   USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
+   USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
+#endif
+
+#if 0 // CPOLn : 1, CPHAn : 1 (O)
+   USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
+   USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Fills each USART_InitStruct member with its default value:
+ *                   -  38400 bps
+ *                   -  8 Data Bit
+ *                   -  No Parity Bit
+ *                   -  1 Stop Bit
+ * @param[out]    USART1n_Config
+ *                   Pointer to a USART1n_CFG_Type structure which will be initialized.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_SPI_Mode_Config( USART1n_CFG_Type* USART1n_Config )
+{
+   /* Check USART1n_Config */
+   if( USART1n_Config == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   USART1n_Config->Mode = USART1n_SPI_MODE;
+   USART1n_Config->Baudrate = 38400;
+   USART1n_Config->Databits = USART1n_DATA_BIT_8;
+   USART1n_Config->Parity = USART1n_PARITY_BIT_NONE;
+   USART1n_Config->Stopbits = USART1n_STOP_BIT_1;
+
+   //only SPI & Sync. Mode
+   USART1n_Config->Order = USART1n_SPI_LSB;
+#if 1 // CPOLn : 0, CPHAn : 0 (X)
+   USART1n_Config->ACK = USART1n_SPI_TX_RISING;
+   USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
+#endif
+#if 0 // CPOLn : 0, CPHAn : 1 (O)
+   USART1n_Config->ACK = USART1n_SPI_TX_RISING;
+   USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
+#endif
+
+#if 0 // CPOLn : 1, CPHAn : 0 (X)
+   USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
+   USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
+#endif
+
+#if 0 // CPOLn : 1, CPHAn : 1 (O)
+   USART1n_Config->ACK = USART1n_SPI_TX_FALLING;
+   USART1n_Config->Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure the peripheral interrupt.
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[in]     USART1n_IntCfg
+ *                   Specifies the interrupt flag
+ *                   -  USART1n_INTCFG_DR:      DR Interrupt enable
+ *                   -  USART1n_INTCFG_TXC:     TXC Interrupt enable
+ *                   -  USART1n_INTCFG_RXC:     RXC interrupt enable
+ *                   -  USART1n_INTCFG_WAKE:    WAKE Interrupt enable
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_ConfigInterrupt( USART1n_Type* USART1x, USART1n_INT_Type USART1n_IntCfg, FunctionalState NewState )
+{
+   uint32_t    tmp = 0;
+
+   /* Check USART handle */
+   if( USART1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   switch( USART1n_IntCfg )
+   {
+      case USART1n_INTCFG_WAKE :
+         tmp = USART1n_IER_WAKEINT_EN;
+         break;
+      case USART1n_INTCFG_RXC:
+         tmp = USART1n_IER_RXCINT_EN;
+         break;
+      case USART1n_INTCFG_TXC:
+         tmp = USART1n_IER_TXCINT_EN;
+         break;
+      case USART1n_INTCFG_DR:
+         tmp = USART1n_IER_DR_EN;
+         break;
+   }
+
+   if( NewState == ENABLE )
+   {
+      USART1x->CR1 |= tmp;
+   }
+   else
+   {
+      USART1x->CR1 &= ~( tmp & USART1n_IER_BITMASK );
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure Data Control mode for USART peripheral
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[in]     Mode
+ *                   Data Control Mode
+ *                   -  UST_CR_USTEN:     Activate USART1n Block by supplying.
+ *                   -  UST_CR_DBLS:      Selects receiver sampling rate. (only UART mode)
+ *                   -  UST_CR_MASTER:    Selects master or slave in SPIn or Synchronous mode and controls the direction of SCKn pin.
+ *                   -  UST_CR_LOOPS:     Control the Loop Back mode of USART1n for test mode.
+ *                   -  UST_CR_DISSCK:    In synchronous mode operation, selects the waveform of SCKn output.
+ *                   -  UST_CR_USTSSEN:   This bit controls the SSn pin operation. (only SPI mode)
+ *                   -  UST_CR_FXCH:      SPIn port function exchange control bit. (only SPI mode)
+ *                   -  UST_CR_USTSB:     Selects the length of stop bit in Asynchronous or Synchronous mode.
+ *                   -  UST_CR_USTTX8:    The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USART1n_DR register.
+ *                   -  UST_CR_USTRX8:    The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)
+ * @param[in]     NewState
+ *                   Next State of Functional Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_DataControlConfig( USART1n_Type* USART1x, USART1n_CONTROL_Type Mode, FunctionalState NewState )
+{
+   uint16_t    tmp = 0;
+
+   /* Check USART handle */
+   if( USART1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   switch( Mode )
+   {
+      case USART1n_CONTROL_USTRX8:
+         tmp = USART1n_CR2_USTnRX8;
+         break;
+      case USART1n_CONTROL_USTTX8:
+         tmp = USART1n_CR2_USTnTX8;
+         break;
+      case USART1n_CONTROL_USTSB:
+         tmp = USART1n_CR2_USTnSB;
+         break;
+      case USART1n_CONTROL_FXCH:
+         tmp = USART1n_CR2_FXCHn;
+         break;
+      case USART1n_CONTROL_USTSSEN:
+         tmp = USART1n_CR2_USTnSSEN;
+         break;
+      case USART1n_CONTROL_DISSCK:
+         tmp = USART1n_CR2_DISSCKn;
+         break;
+      case USART1n_CONTROL_LOOPS:
+         tmp = USART1n_CR2_LOOPSn;
+         break;
+      case USART1n_CONTROL_MASTER:
+         tmp = USART1n_CR2_MASTERn;
+         break;
+      case USART1n_CONTROL_DBLS:
+         tmp = USART1n_CR2_DBLSn;
+         break;
+      case USART1n_CONTROL_USTEN:
+         tmp = USART1n_CR2_USTnEN;
+         break;
+      default:
+         break;
+   }
+
+   if( NewState == ENABLE )
+   {
+      USART1x->CR2 |= tmp;
+   }
+   else
+   {
+      USART1x->CR2 &= ~( tmp & USART1n_CR2_BITMASK );
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         USART1n enable control
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[in]     state
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_Enable( USART1n_Type* USART1x, FunctionalState state )
+{
+   /* Check USART handle */
+   if( USART1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   if( state == ENABLE )
+   {
+      USART1x->CR2 |= ( 1 << USART1n_CR2_USTnEN_Pos );      // USTnEN
+   }
+   else
+   {
+      USART1x->CR2 &= ~( 1 << USART1n_CR2_USTnEN_Pos );     // USTnEN
+   }
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear Status register in USART peripheral.
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[in]     Status
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_ClearStatus( USART1n_Type* USART1x, USART1n_STATUS_Type Status )
+{
+   uint32_t    tmp;
+
+   /* Check USART handle */
+   if( USART1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   switch( Status )
+   {
+      case USART1n_STATUS_WAKE:
+         tmp = USART1n_SR_WAKE;
+         break;
+      case USART1n_STATUS_RXC:
+         tmp = USART1n_SR_RXC;
+         break;
+      case USART1n_STATUS_TXC:
+         tmp = USART1n_SR_TXC;
+         break;
+      case USART1n_STATUS_DRE:
+         tmp = USART1n_SR_DRE;
+         break;
+      default:
+         return HAL_ERROR;
+   }
+
+   USART1x->ST = tmp;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get current value of Line Status register in USART peripheral.
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @return        Current value of Status register in USART peripheral.
+ *//*-------------------------------------------------------------------------*/
+uint8_t HAL_USART_GetStatus( USART1n_Type* USART1x )
+{
+   return ( ( USART1x->ST ) & USART1n_SR_BITMASK );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Check whether if USART is busy or not
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @return        RESET if USART is not busy, otherwise return SET.
+ *//*-------------------------------------------------------------------------*/
+FlagStatus HAL_USART_CheckBusy( USART1n_Type* USART1x )
+{
+   if( USART1x->ST & USART1n_SR_DRE )
+   {
+      return RESET;
+   }
+   else
+   {
+      return SET;
+   }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Transmit a single data through USART peripheral
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[in]     Data
+ *                   Data to transmit (must be 8-bit long)
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_USART_TransmitByte( USART1n_Type* USART1x, uint8_t Data )
+{
+   /* Check USART handle */
+   if( USART1x == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   USART1x->DR = Data;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Receive a single data from USART peripheral
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @return        Data received
+ *//*-------------------------------------------------------------------------*/
+uint8_t HAL_USART_ReceiveByte( USART1n_Type* USART1x )
+{
+   return USART1x->DR;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Send a block of data via USART peripheral
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[in]     txbuf
+ *                   Pointer to Transmit buffer
+ * @param[in]     buflen
+ *                   Length of Transmit buffer
+ * @param[in]     flag
+ *                   Flag used in  USART transfer
+ *                   -  NONE_BLOCKING
+ *                   -  BLOCKING
+ * @return        Number of bytes sent.
+ * @note          when using USART in BLOCKING mode, a time-out condition is used
+ *                via defined symbol USART_BLOCKING_TIMEOUT.
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_USART_Transmit( USART1n_Type* USART1x, uint8_t* txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
+{
+   uint32_t    bToSend, bSent, timeOut;
+   uint8_t*    pChar = txbuf;
+
+   bToSend = buflen;
+
+   // blocking mode
+
+   if( flag == BLOCKING )
+   {
+      bSent = 0;
+      while( bToSend )
+      {
+
+         HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
+
+         timeOut = USART1n_BLOCKING_TIMEOUT;
+         // Wait for THR empty with timeout
+         while( !( USART1x->ST & USART1n_SR_TXC ) )
+         {
+            if( timeOut == 0 )
+            {
+               break;
+            }
+            timeOut--;
+         }
+         // Time out!
+         if( timeOut == 0 )
+         {
+            break;
+         }
+         HAL_USART_ClearStatus( USART1x, USART1n_STATUS_TXC );
+         bToSend--;
+         bSent++;
+      }
+   }
+
+   // Non-Blocking Mode
+   else
+   {
+      bSent = 0;
+      while( bToSend )
+      {
+         if( !( USART1x->ST & USART1n_SR_DRE ) )
+         {
+            break;
+         }
+         HAL_USART_TransmitByte( USART1x, ( *pChar++ ) );
+         bToSend--;
+         bSent++;
+      }
+   }
+
+   return bSent;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Receive a block of data via USART peripheral
+ * @param[in]     USART1x
+ *                   Pointer to the target USART1
+ *                   -  USART10 ~ USART13
+ * @param[out]    rxbuf
+ *                   Pointer to Received buffer
+ * @param[in]     buflen
+ *                   Length of Received buffer
+ * @param[in]     flag
+ *                   Flag mode
+ *                   -  NONE_BLOCKING
+ *                   -  BLOCKING
+ * @return        Number of bytes received
+ * @note          when using USART in BLOCKING mode, a time-out condition is used
+ *                via defined symbol USART_BLOCKING_TIMEOUT.
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_USART_Receive( USART1n_Type* USART1x, uint8_t* rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag )
+{
+   uint32_t    bToRecv, bRecv, timeOut;
+   uint8_t*    pChar = rxbuf;
+
+   bToRecv = buflen;
+
+   // Blocking Mode
+   if( flag == BLOCKING )
+   {
+      bRecv = 0;
+      while( bToRecv )
+      {
+         timeOut = USART1n_BLOCKING_TIMEOUT;
+         while( !( USART1x->ST & USART1n_SR_RXC ) )
+         {
+            if( timeOut == 0 )
+            {
+               break;
+            }
+            timeOut--;
+         }
+         // Time out!
+
+         if( timeOut == 0 )
+         {
+            break;
+         }
+         // Get data from the buffer
+         ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
+
+         bToRecv--;
+         bRecv++;
+      }
+   }
+
+   // Non-Blocking Mode
+   else
+   {
+      bRecv = 0;
+      while( bToRecv )
+      {
+         if( !( USART1x->ST & USART1n_SR_RXC ) )
+         {
+            break;
+         }
+         else
+         {
+            ( *pChar++ ) = HAL_USART_ReceiveByte( USART1x );
+            bRecv++;
+            bToRecv--;
+         }
+      }
+   }
+
+   return bRecv;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_wdt.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_wdt.c
new file mode 100644
index 0000000..0d5236a
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_wdt.c
@@ -0,0 +1,243 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_wdt.c
+* @brief    Contains all functions support for wdt firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_wdt.h"
+#include "A31G12x_hal_scu.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the WDT peripheral with the specified parameters.
+ * @param[in]     WDT_Config
+ *                   Pointer to a WDT_CFG_Type structure
+ *                   that contains the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WDT_Init( WDT_CFG_Type* WDT_Config )
+{
+   uint32_t    reg_val = 0;
+
+   /* Check WDT_Config */
+   if( WDT_Config == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   // enable peripheral clock
+   HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_WDTCLKE, PPxCLKE_Enable );
+
+   WDT->DR = ( WDT_Config->wdtTmrConst & 0x00FFFFFF );
+   WDT->WINDR = ( WDT_Config->wdtWTmrConst & 0x00FFFFFF );
+   reg_val = WDT_Config->wdtClkDiv;
+   if( WDT_Config->wdtResetEn == ENABLE )
+   {
+      reg_val &= ~( 0x3f << WDT_CR_RSTEN_Pos );
+   }
+   else
+   {
+      reg_val |= ( 0x25 << WDT_CR_RSTEN_Pos );
+   }
+   WDT->CR = ( 0x5A69 << WDT_CR_WTIDKY_Pos ) | ( 0x1a << WDT_CR_CNTEN_Pos ) | reg_val;    // /w Write Identification Key
+
+   // return
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Deinitialize WDT
+ * @param         None
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WDT_DeInit( void )
+{
+   WDT->CR = 0
+             | ( 0x5A69 << WDT_CR_WTIDKY_Pos )  // Write Identification Key
+             | ( 0x25  << WDT_CR_RSTEN_Pos )    // Disable watch-dog timer reset
+             | ( 0x1A << WDT_CR_CNTEN_Pos )     // Disable watch-dog timer counter
+             ;
+
+   // return
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure the peripheral interrupt.
+ * @param[in]     WDT_IntCfg
+ *                   Specifies the interrupt flag
+ *                   -  WDT_INTCFG_UNFIEN:   UNFIEN Interrupt enable
+ *                   -  WDT_INTCFG_WINMIEN:  WINMIEN Interrupt enable
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WDT_ConfigInterrupt( WDT_INT_Type WDT_IntCfg, FunctionalState NewState )
+{
+#if 0    // before bug fix
+   uint32_t    reg_val = 0;
+   uint32_t    tmp = 0;
+
+   reg_val = ( WDT->CR & 0xFFFF );
+
+   switch( WDT_IntCfg )
+   {
+      case WDT_INTCFG_UNFIEN:
+         tmp = WDT_CR_UNFIEN;
+         break;
+      case WDT_INTCFG_WINMIEN:
+         tmp = WDT_CR_WINMIEN;
+         break;
+   }
+
+   if( NewState == ENABLE )
+   {
+      reg_val |= ( tmp & WDT_INTERRUPT_BITMASK );
+   }
+   else
+   {
+      reg_val &= ( ( ~tmp ) & WDT_INTERRUPT_BITMASK );   // reg_val &= ~tmp;�� ���� ��...
+   }
+
+   WDT->CR = ( 0x5A69 << WDT_CR_WTIDKY_Pos ) | reg_val;  // Write Identification Key 0x5A69
+#else    // after bug fix
+   uint32_t    reg_val = 0;
+   uint32_t    mask = 0;
+
+   switch( WDT_IntCfg )
+   {
+      case WDT_INTCFG_UNFIEN:
+         mask = WDT_CR_UNFIEN_Msk;
+         break;
+      case WDT_INTCFG_WINMIEN:
+         mask = WDT_CR_WINMIEN_Msk;
+         break;
+   }
+
+   reg_val =   WDT->CR
+               & ~( WDT_CR_WTIDKY_Msk )
+               | ( ( uint32_t )WDT_CR_WTIDKY_Value << WDT_CR_WTIDKY_Pos )
+               ;
+   if( NewState == ENABLE )
+   {
+      reg_val |= mask;
+   }
+   else
+   {
+      reg_val &= ~mask;
+   }
+
+   WDT->CR = reg_val;
+#endif
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Reload WDT counter
+ * @param         None
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WDT_ReloadTimeCounter( void )
+{
+   WDT->CNTR = 0x6a;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable WDT activity
+ * @param[in]     ctrl
+ *                   -  DISABLE:  wdt enable
+ *                   -  ENABLE:   wdt disable
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WDT_Start( FunctionalState ctrl )
+{
+   uint32_t    tmp_reg;
+
+   tmp_reg = WDT->CR & 0xFFFF;
+   tmp_reg |= ( 0x1a << WDT_CR_CNTEN_Pos );  // Disable watch-dog timer counter
+
+   if( ctrl == ENABLE )
+   {
+      tmp_reg &= ~( 0x3f << WDT_CR_CNTEN_Pos );    // Enable watch-dog timer counter,
+   }
+
+   WDT->CR = ( 0x5A69 << WDT_CR_WTIDKY_Pos ) | tmp_reg;  // Write Identification Key 0x5A69
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear the timer status register of WDT
+ * @param[in]     clrbit
+ *                   -  WDT_SR_UNFIFLAG:     UNFIFLAG Interrupt flag
+ *                   -  WDT_SR_WINMIFLAG:    WINMIFLAG Interrupt flag
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WDT_ClearStatus( uint32_t clrbit )
+{
+   WDT->SR = clrbit;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get the timer status register of WDT
+ * @param         None
+ * @return        the status register of WDT
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_WDT_GetStatus( void )
+{
+   return WDT->SR;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get the current value of WDT
+ * @param         None
+ * @return        current value of WDT
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_WDT_GetCurrentCount( void )
+{
+   return WDT->CNT;
+}
+
diff --git a/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_wt.c b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_wt.c
new file mode 100644
index 0000000..f2aaa41
--- /dev/null
+++ b/Project/SDK_V2_5_0/Drivers/Source/A31G12x_hal_wt.c
@@ -0,0 +1,188 @@
+/***************************************************************************//**
+* @file     A31G12x_hal_wt.c
+* @brief    Contains all functions support for wt firmware library on A31G12x
+*
+*
+*
+* @version  1.00
+* @date     2020-05-29
+* @author   ABOV Application Team
+*
+* Copyright(C) 2019, ABOV Semiconductor
+* All rights reserved.
+*
+********************************************************************************
+* ABOV Disclaimer
+*
+*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
+*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
+*modifications, and improvements to ABOV products and/or to this document at any time without notice.
+*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
+*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
+*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
+*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
+*express or implied, to any intellectual property rights is granted by ABOV herein.
+*ABOV disclaims all express and implied warranties and shall not be responsible or
+*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
+*ABOV and the ABOV logo are trademarks of ABOV.
+*All other product or service names are the property of their respective owners.
+*Information in this document supersedes and replaces the information previously
+*supplied in any former versions of this document.
+*2020 ABOV Semiconductor  All rights reserved
+*
+*//****************************************************************************/
+
+/* Includes ----------------------------------------------------------------- */
+//******************************************************************************
+// Include
+//******************************************************************************
+
+#include "A31G12x_hal_wt.h"
+#include "A31G12x_hal_scu.h"
+
+/* Public Functions --------------------------------------------------------- */
+//******************************************************************************
+// Function
+//******************************************************************************
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Initialize the WT peripheral with the specified parameters.
+ * @param[in]     WT_Config
+ *                   Pointer to a WT_CFG_Type structure
+ *                   that contains the configuration information for the specified peripheral.
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WT_Init( WT_CFG_Type* WT_Config )
+{
+   /* Check WT_Config */
+   if( WT_Config == NULL )
+   {
+      return HAL_ERROR;
+   }
+
+   // enable peripheral clock
+   HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_WTCLKE, PPxCLKE_Enable );
+
+   WT->CR = 0
+            | ( ( WT_Config->wtClkDiv & 0x03 ) << 4 )   // WTINTV[1:0]
+            | WT_CR_WTCLR
+            ;
+   WT->DR = ( WT_Config->wtTmrConst & 0xFFF );
+
+   // return
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         deinit for Watch Timer function
+ * @param         None
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WT_DeInit( void )
+{
+   WT->CR = 0;
+
+   // return
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Configure the peripheral interrupt.
+ * @param[in]     NewState
+ *                   Next State of Interrupt Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WT_ConfigInterrupt( FunctionalState NewState )
+{
+   uint32_t    reg_val = 0;
+
+   reg_val = ( WT->CR & 0xFF );
+
+   if( NewState == ENABLE )
+   {
+      reg_val |= WT_CR_WTIEN;          // WTIEN bit
+   }
+   else
+   {
+      reg_val &= ~WT_CR_WTIEN;
+   }
+
+   WT->CR = reg_val | WT_CR_WTIFLAG;   // (1<<1):  clear for WTIFLAG
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Enable WT activity
+ * @param[in]     ctrl
+ *                   Next State of Functional Operation
+ *                   -  ENABLE, DISABLE
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WT_Start( FunctionalState ctrl )
+{
+   uint32_t    tmp_reg;
+
+   tmp_reg = WT->CR & 0xFF;
+   tmp_reg &= ~( 0x1 << 7 );  // Disable watch-dog timer counter
+
+   if( ctrl == ENABLE )
+   {
+      tmp_reg |= ( 0x1 << 7 );   // Enable watch timer counter
+   }
+
+   tmp_reg |= WT_CR_WTCLR;    // clear the counter and divider
+
+   WT->CR = tmp_reg;
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Set WT CR Register
+ * @param[in]     u32WTSet
+ *                      Watch Timer Control Register Setting Data
+ * @return        @ref HAL_Status_Type
+ * @details       This function sets the mode, external clock edge, Timer out polarity,
+ *                Capture Polarity and Timer match/capture interrupt.
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WT_SetRegister( uint32_t u32WTSet )
+{
+   WT->CR = u32WTSet;      // Setting Timer 1n Control Register
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Clear the timer status register of WT
+ * @param         None
+ * @return        @ref HAL_Status_Type
+ *//*-------------------------------------------------------------------------*/
+HAL_Status_Type HAL_WT_ClearStatus( void )
+{
+   WT->CR |= WT_CR_WTIFLAG;   // (1<<1):  clear for WTIFLAG
+
+   return HAL_OK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get the timer status register of WT
+ * @param         None
+ * @return        the status register of WT
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_WT_GetStatus( void )
+{
+   return ( WT->CR & WT_STATUS_BITMASK );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * @brief         Get the current value of WT
+ * @param         None
+ * @return        current value of WT
+ *//*-------------------------------------------------------------------------*/
+uint32_t HAL_WT_GetCurrentCount( void )
+{
+   return ( WT->CNT & 0xFFF );
+}
+
diff --git a/Project/SDK_V2_5_0/FlashLoader/A31G12x_CFG.FLM b/Project/SDK_V2_5_0/FlashLoader/A31G12x_CFG.FLM
new file mode 100644
index 0000000..16fd340
Binary files /dev/null and b/Project/SDK_V2_5_0/FlashLoader/A31G12x_CFG.FLM differ
diff --git a/Project/SDK_V2_5_0/FlashLoader/A31G12x_FLASH.FLM b/Project/SDK_V2_5_0/FlashLoader/A31G12x_FLASH.FLM
new file mode 100644
index 0000000..46b844b
Binary files /dev/null and b/Project/SDK_V2_5_0/FlashLoader/A31G12x_FLASH.FLM differ
diff --git a/Project/SDK_V2_5_0/INI/RAM.ini b/Project/SDK_V2_5_0/INI/RAM.ini
new file mode 100644
index 0000000..ef0ab99
--- /dev/null
+++ b/Project/SDK_V2_5_0/INI/RAM.ini
@@ -0,0 +1,25 @@
+/***********************************************************************/
+/*  This file is part of the ARM Compiler package                      */
+/*  Copyright KEIL ELEKTRONIK GmbH 1992-2006                           */
+/***********************************************************************/
+/*                                                                     */
+/*  RAM.ini: RAM Initialization File                                   */
+/*                                                                     */
+/***********************************************************************/
+
+
+   //*** <<< Use Configuration Wizard in Context Menu >>> *** 
+
+   FUNC void Setup( void )
+   {
+      SP = _RDWORD( 0x20000000 );               // Setup Stack Pointer
+      PC = _RDWORD( 0x20000004 );               // Setup Program Counter
+   // _WDWORD( 0xE000ED08, 0x20000000 );        // Setup Vector Table Offset Register
+   }
+
+   LOAD %L INCREMENTAL                          // Load The Application
+
+   Setup();                                     // Setup for Running
+
+// g, main
+
diff --git a/Project/SDK_V2_5_0/INI/ROM.ini b/Project/SDK_V2_5_0/INI/ROM.ini
new file mode 100644
index 0000000..224d47e
--- /dev/null
+++ b/Project/SDK_V2_5_0/INI/ROM.ini
@@ -0,0 +1,25 @@
+/***********************************************************************/
+/*  This file is part of the ARM Compiler package                      */
+/*  Copyright KEIL ELEKTRONIK GmbH 1992-2006                           */
+/***********************************************************************/
+/*                                                                     */
+/*  ROM.ini: ROM Initialization File                                   */
+/*                                                                     */
+/***********************************************************************/
+
+
+   //*** <<< Use Configuration Wizard in Context Menu >>> *** 
+
+   FUNC void Setup( void )
+   {
+      SP = _RDWORD( 0x00000000 );               // Setup Stack Pointer
+      PC = _RDWORD( 0x00000004 );               // Setup Program Counter
+   // _WDWORD( 0xE000ED08, 0x00000000 );        // Setup Vector Table Offset Register
+   }
+
+   LOAD %L INCREMENTAL                          // Load The Application
+
+   Setup();                                     // Setup for Running
+
+// g, main
+
diff --git a/Project/SDK_V2_5_0/Option/option_A31G12x.s b/Project/SDK_V2_5_0/Option/option_A31G12x.s
new file mode 100644
index 0000000..b2520cf
--- /dev/null
+++ b/Project/SDK_V2_5_0/Option/option_A31G12x.s
@@ -0,0 +1,268 @@
+;-------------------------------------------------------------------------------
+; This file is used for configure option setting, Area 1/2/3.
+;-------------------------------------------------------------------------------
+;// <<< Use Configuration Wizard in Context Menu >>>
+;/*****************************************************************************/
+;/* This file is part of the uVision/ARM development tools.                   */
+;/* Copyright (c) 2005-2008 Keil Software. All rights reserved.               */
+;/* This software may only be used under the terms of a valid, current,       */
+;/* end user licence from KEIL for a compatible version of KEIL software      */
+;/* development tools. Nothing else gives you the right to use this software. */
+;/*****************************************************************************/
+
+
+;// <e> Configure Option Page 1
+CONFIGURE_OPTION_1         EQU      1
+
+;// <h> Read Protection Configuration
+;//    <o.0..2> Read Protection
+;//       <3=> Level 0 <2=> Level 1 <0=> Level 2
+;// </h>
+RPCNFIG                    EQU      0x69C8A273
+
+;// <h> Extra User Data
+;//   <o0> Word 0 <0x0000-0xFFFF>
+;//   <o1> Word 1 <0x0000-0xFFFF>
+;// </h>
+EX0CNFIG                   EQU      0xFFFF
+EX1CNFIG                   EQU      0xFFFF
+nEX0CNFIG                  EQU      EX0CNFIG:EOR:0xFFFF
+nEX1CNFIG                  EQU      EX1CNFIG:EOR:0xFFFF
+
+;// <h> Watch-Dog Timer Configuration
+;//    <o.4..15> WDTRC Enable Selection
+;//       <0x96D=> By S/W (CLKSRCR Register) <0x2A7=> Enable but disable at deep sleep <0xFFF=> Always Enable
+;//    <o.2> Watch-Dog Timer Clock Selection
+;//       <0=> By S/W (PPCLKSR Register) <1=> WDTRC
+;//    <o.1> Watch-Dog Timer Reset Enable Selection
+;//       <0=> Enable WDT Reset <1=> By S/W (WDTCR Register)
+;//    <o.0> Watch-Dog Timer Counter Enable Selection
+;//       <0=> Enable WDT Counter <1=> By S/W (WDTCR Register)
+;// </h>
+WDTCNFIG                   EQU      0xFFFF96DB
+
+;// <h> Low Voltage Reset Configuration
+;//    <o.8..15> LVR Operation Control Selection
+;//       <0xAA=> By S/W (LVRCR Register) <0xFF=> Always Enable
+;//    <o.0..3> LVR Voltage Selection
+;//       <15=> 1.62V <11=> 2.00V <10=> 2.13V <9=> 2.28V <8=> 2.46V <7=> 2.67V <6=> 3.04V <5=> 3.20V <4=> 3.55V <3=> 3.75V <2=> 3.99V <1=> 4.25V <0=> 4.55V
+;// </h>
+LVRCNFIG                   EQU      0xFFFFAAFF
+
+;// <h> Configure Option Page Erase/Write Protection
+;//    <o.0> Option Page 1, 0x1FFFF200 to 0x1FFFF27F
+;//    <o.1> Option Page 2, 0x1FFFF400 to 0x1FFFF47F
+;//    <o.2> Option Page 3, 0x1FFFF600 to 0x1FFFF67F
+;// </h>
+OPTIONPAGE                 EQU      0x00000000
+CNFIGWTP1                  EQU      ~OPTIONPAGE
+
+;// <h> Flash Memory Erase/Write Protection
+;//    <o.0> Sector 0, 0x10000000 to 0x100007FF
+;//    <o.1> Sector 1, 0x10000800 to 0x10000FFF
+;//    <o.2> Sector 2, 0x10001000 to 0x100017FF
+;//    <o.3> Sector 3, 0x10001800 to 0x10001FFF
+;//    <o.4> Sector 4, 0x10002000 to 0x100027FF
+;//    <o.5> Sector 5, 0x10002800 to 0x10002FFF
+;//    <o.6> Sector 6, 0x10003000 to 0x100037FF
+;//    <o.7> Sector 7, 0x10003800 to 0x10003FFF
+;//    <o.8> Sector 8, 0x10004000 to 0x100047FF
+;//    <o.9> Sector 9, 0x10004800 to 0x10004FFF
+;//    <o.10> Sector 10, 0x10005000 to 0x100057FF
+;//    <o.11> Sector 11, 0x10005800 to 0x10005FFF
+;//    <o.12> Sector 12, 0x10006000 to 0x100067FF
+;//    <o.13> Sector 13, 0x10006800 to 0x10006FFF
+;//    <o.14> Sector 14, 0x10007000 to 0x100077FF
+;//    <o.15> Sector 15, 0x10007800 to 0x10007FFF
+;//    <o.16> Sector 16, 0x10008000 to 0x100087FF
+;//    <o.17> Sector 17, 0x10008800 to 0x10008FFF
+;//    <o.18> Sector 18, 0x10009000 to 0x100097FF
+;//    <o.19> Sector 19, 0x10009800 to 0x10009FFF
+;//    <o.20> Sector 20, 0x1000A000 to 0x1000A7FF
+;//    <o.21> Sector 21, 0x1000A800 to 0x1000AFFF
+;//    <o.22> Sector 22, 0x1000B000 to 0x1000B7FF
+;//    <o.23> Sector 23, 0x1000B800 to 0x1000BFFF
+;//    <o.24> Sector 24, 0x1000C000 to 0x1000C7FF
+;//    <o.25> Sector 25, 0x1000C800 to 0x1000CFFF
+;//    <o.26> Sector 26, 0x1000D000 to 0x1000D7FF
+;//    <o.27> Sector 27, 0x1000D800 to 0x1000DFFF
+;//    <o.28> Sector 28, 0x1000E000 to 0x1000E7FF
+;//    <o.29> Sector 29, 0x1000E800 to 0x1000EFFF
+;//    <o.30> Sector 30, 0x1000F000 to 0x1000F7FF
+;//    <o.31> Sector 31, 0x1000F800 to 0x1000FFFF
+;// </h>
+FLASHSECTOR                EQU      0x00000000
+FMWTP0                     EQU      ~FLASHSECTOR
+;// </e>
+
+;// <e> Configure Option Page 2
+CONFIGURE_OPTION_2         EQU      1
+
+;// <h> User Data Area 0
+;//   <o0> Double 0 <0x00000000-0xFFFFFFFF>
+;//   <o1> Double 1 <0x00000000-0xFFFFFFFF>
+;//   <o2> Double 2 <0x00000000-0xFFFFFFFF>
+;//   <o3> Double 3 <0x00000000-0xFFFFFFFF>
+;//   <o4> Double 4 <0x00000000-0xFFFFFFFF>
+;//   <o5> Double 5 <0x00000000-0xFFFFFFFF>
+;//   <o6> Double 6 <0x00000000-0xFFFFFFFF>
+;//   <o7> Double 7 <0x00000000-0xFFFFFFFF>
+;//   <o8> Double 8 <0x00000000-0xFFFFFFFF>
+;//   <o9> Double 9 <0x00000000-0xFFFFFFFF>
+;//   <o10> Double 10 <0x00000000-0xFFFFFFFF>
+;//   <o11> Double 11 <0x00000000-0xFFFFFFFF>
+;//   <o12> Double 12 <0x00000000-0xFFFFFFFF>
+;//   <o13> Double 13 <0x00000000-0xFFFFFFFF>
+;//   <o14> Double 14 <0x00000000-0xFFFFFFFF>
+;//   <o15> Double 15 <0x00000000-0xFFFFFFFF>
+;//   <o16> Double 16 <0x00000000-0xFFFFFFFF>
+;//   <o17> Double 17 <0x00000000-0xFFFFFFFF>
+;//   <o18> Double 18 <0x00000000-0xFFFFFFFF>
+;//   <o19> Double 19 <0x00000000-0xFFFFFFFF>
+;//   <o20> Double 20 <0x00000000-0xFFFFFFFF>
+;//   <o21> Double 21 <0x00000000-0xFFFFFFFF>
+;//   <o22> Double 22 <0x00000000-0xFFFFFFFF>
+;//   <o23> Double 23 <0x00000000-0xFFFFFFFF>
+;//   <o24> Double 24 <0x00000000-0xFFFFFFFF>
+;//   <o25> Double 25 <0x00000000-0xFFFFFFFF>
+;//   <o26> Double 26 <0x00000000-0xFFFFFFFF>
+;//   <o27> Double 27 <0x00000000-0xFFFFFFFF>
+;//   <o28> Double 28 <0x00000000-0xFFFFFFFF>
+;//   <o29> Double 29 <0x00000000-0xFFFFFFFF>
+;//   <o30> Double 30 <0x00000000-0xFFFFFFFF>
+;//   <o31> Double 31 <0x00000000-0xFFFFFFFF>
+;// </h>
+AREA0_0                    EQU      0xe2e2e2e2
+AREA0_1                    EQU      0xFFFFFFFF
+AREA0_2                    EQU      0xFFFFFFFF
+AREA0_3                    EQU      0xFFFFFFFF
+AREA0_4                    EQU      0xFFFFFFFF
+AREA0_5                    EQU      0xFFFFFFFF
+AREA0_6                    EQU      0xFFFFFFFF
+AREA0_7                    EQU      0xFFFFFFFF
+AREA0_8                    EQU      0xFFFFFFFF
+AREA0_9                    EQU      0xFFFFFFFF
+AREA0_10                   EQU      0xFFFFFFFF
+AREA0_11                   EQU      0xFFFFFFFF
+AREA0_12                   EQU      0xFFFFFFFF
+AREA0_13                   EQU      0xFFFFFFFF
+AREA0_14                   EQU      0xFFFFFFFF
+AREA0_15                   EQU      0xFFFFFFFF
+AREA0_16                   EQU      0xFFFFFFFF
+AREA0_17                   EQU      0xFFFFFFFF
+AREA0_18                   EQU      0xFFFFFFFF
+AREA0_19                   EQU      0xFFFFFFFF
+AREA0_20                   EQU      0xFFFFFFFF
+AREA0_21                   EQU      0xFFFFFFFF
+AREA0_22                   EQU      0xFFFFFFFF
+AREA0_23                   EQU      0xFFFFFFFF
+AREA0_24                   EQU      0xFFFFFFFF
+AREA0_25                   EQU      0xFFFFFFFF
+AREA0_26                   EQU      0xFFFFFFFF
+AREA0_27                   EQU      0xFFFFFFFF
+AREA0_28                   EQU      0xFFFFFFFF
+AREA0_29                   EQU      0xFFFFFFFF
+AREA0_30                   EQU      0xFFFFFFFF
+AREA0_31                   EQU      0xe2e2e2e2
+;// </e>
+
+;// <e> Configure Option Page 3
+CONFIGURE_OPTION_3         EQU      1
+
+;// <h> User Data Area 1
+;//   <o0> Double 0 <0x00000000-0xFFFFFFFF>
+;//   <o1> Double 1 <0x00000000-0xFFFFFFFF>
+;//   <o2> Double 2 <0x00000000-0xFFFFFFFF>
+;//   <o3> Double 3 <0x00000000-0xFFFFFFFF>
+;//   <o4> Double 4 <0x00000000-0xFFFFFFFF>
+;//   <o5> Double 5 <0x00000000-0xFFFFFFFF>
+;//   <o6> Double 6 <0x00000000-0xFFFFFFFF>
+;//   <o7> Double 7 <0x00000000-0xFFFFFFFF>
+;//   <o8> Double 8 <0x00000000-0xFFFFFFFF>
+;//   <o9> Double 9 <0x00000000-0xFFFFFFFF>
+;//   <o10> Double 10 <0x00000000-0xFFFFFFFF>
+;//   <o11> Double 11 <0x00000000-0xFFFFFFFF>
+;//   <o12> Double 12 <0x00000000-0xFFFFFFFF>
+;//   <o13> Double 13 <0x00000000-0xFFFFFFFF>
+;//   <o14> Double 14 <0x00000000-0xFFFFFFFF>
+;//   <o15> Double 15 <0x00000000-0xFFFFFFFF>
+;//   <o16> Double 16 <0x00000000-0xFFFFFFFF>
+;//   <o17> Double 17 <0x00000000-0xFFFFFFFF>
+;//   <o18> Double 18 <0x00000000-0xFFFFFFFF>
+;//   <o19> Double 19 <0x00000000-0xFFFFFFFF>
+;//   <o20> Double 20 <0x00000000-0xFFFFFFFF>
+;//   <o21> Double 21 <0x00000000-0xFFFFFFFF>
+;//   <o22> Double 22 <0x00000000-0xFFFFFFFF>
+;//   <o23> Double 23 <0x00000000-0xFFFFFFFF>
+;//   <o24> Double 24 <0x00000000-0xFFFFFFFF>
+;//   <o25> Double 25 <0x00000000-0xFFFFFFFF>
+;//   <o26> Double 26 <0x00000000-0xFFFFFFFF>
+;//   <o27> Double 27 <0x00000000-0xFFFFFFFF>
+;//   <o28> Double 28 <0x00000000-0xFFFFFFFF>
+;//   <o29> Double 29 <0x00000000-0xFFFFFFFF>
+;//   <o30> Double 30 <0x00000000-0xFFFFFFFF>
+;//   <o31> Double 31 <0x00000000-0xFFFFFFFF>
+;// </h>
+AREA1_0                    EQU      0xe3e3e3e3
+AREA1_1                    EQU      0xFFFFFFFF
+AREA1_2                    EQU      0xFFFFFFFF
+AREA1_3                    EQU      0xFFFFFFFF
+AREA1_4                    EQU      0xFFFFFFFF
+AREA1_5                    EQU      0xFFFFFFFF
+AREA1_6                    EQU      0xFFFFFFFF
+AREA1_7                    EQU      0xFFFFFFFF
+AREA1_8                    EQU      0xFFFFFFFF
+AREA1_9                    EQU      0xFFFFFFFF
+AREA1_10                   EQU      0xFFFFFFFF
+AREA1_11                   EQU      0xFFFFFFFF
+AREA1_12                   EQU      0xFFFFFFFF
+AREA1_13                   EQU      0xFFFFFFFF
+AREA1_14                   EQU      0xFFFFFFFF
+AREA1_15                   EQU      0xFFFFFFFF
+AREA1_16                   EQU      0xFFFFFFFF
+AREA1_17                   EQU      0xFFFFFFFF
+AREA1_18                   EQU      0xFFFFFFFF
+AREA1_19                   EQU      0xFFFFFFFF
+AREA1_20                   EQU      0xFFFFFFFF
+AREA1_21                   EQU      0xFFFFFFFF
+AREA1_22                   EQU      0xFFFFFFFF
+AREA1_23                   EQU      0xFFFFFFFF
+AREA1_24                   EQU      0xFFFFFFFF
+AREA1_25                   EQU      0xFFFFFFFF
+AREA1_26                   EQU      0xFFFFFFFF
+AREA1_27                   EQU      0xFFFFFFFF
+AREA1_28                   EQU      0xFFFFFFFF
+AREA1_29                   EQU      0xFFFFFFFF
+AREA1_30                   EQU      0xFFFFFFFF
+AREA1_31                   EQU      0xe3e3e3e3
+;// </e>
+
+                           IF      CONFIGURE_OPTION_1 <> 0
+                           AREA    |.ARM.__AT_0x1FFFF200|, CODE, READONLY
+                           DCD     RPCNFIG
+                           DCW     EX0CNFIG, nEX0CNFIG, EX1CNFIG, nEX1CNFIG
+                           DCD     WDTCNFIG
+                           DCD     LVRCNFIG
+                           DCD     CNFIGWTP1
+                           FILL    40,0xFF,1
+                           DCD     FMWTP0
+                           ENDIF
+
+                           IF      CONFIGURE_OPTION_2 <> 0
+                           AREA    |.ARM.__AT_0x1FFFF400|, CODE, READONLY
+                           DCD     AREA0_0, AREA0_1, AREA0_2, AREA0_3, AREA0_4, AREA0_5, AREA0_6, AREA0_7
+                           DCD     AREA0_8, AREA0_9, AREA0_10, AREA0_11, AREA0_12, AREA0_13, AREA0_14, AREA0_15
+                           DCD     AREA0_16, AREA0_17, AREA0_18, AREA0_19, AREA0_20, AREA0_21, AREA0_22, AREA0_23
+                           DCD     AREA0_24, AREA0_25, AREA0_26, AREA0_27, AREA0_28, AREA0_29, AREA0_30, AREA0_31
+                           ENDIF
+
+                           IF      CONFIGURE_OPTION_3 <> 0
+                           AREA    |.ARM.__AT_0x1FFFF600|, CODE, READONLY
+                           DCD     AREA1_0, AREA1_1, AREA1_2, AREA1_3, AREA1_4, AREA1_5, AREA1_6, AREA1_7
+                           DCD     AREA1_8, AREA1_9, AREA1_10, AREA1_11, AREA1_12, AREA1_13, AREA1_14, AREA1_15
+                           DCD     AREA1_16, AREA1_17, AREA1_18, AREA1_19, AREA1_20, AREA1_21, AREA1_22, AREA1_23
+                           DCD     AREA1_24, AREA1_25, AREA1_26, AREA1_27, AREA1_28, AREA1_29, AREA1_30, AREA1_31
+                           ENDIF
+
+                           END
+