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S_Co2_Sensor_Logger
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Imbis 6 months ago
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Project/Objects

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Project/A31G12x_Co2_Sensor_Logger.uvoptx
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<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
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<v6LangP>3</v6LangP>
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<vShortWch>1</vShortWch>
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<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>.\Application;.\SDK_V2_5_0\Device\Startup;.\SDK_V2_5_0\Drivers\Include;.\SDK_V2_5_0\Drivers\Source;.\SDK_V2_5_0\FlashLoader;.\SDK_V2_5_0\Option;.\SDK_V2_5_0\INI;.\SDK_V2_5_0\Core;.\Application\FATFS\App;.\Application\FATFS\Target;.\Application\Middlewares\Third_Party\FatFs\src;.\Application\Middlewares\Third_Party\FatFs\src\option</IncludePath>
</VariousControls>
</Cads>
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<interw>1</interw>
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<Rwpi>0</Rwpi>
<thumb>0</thumb>
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<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
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<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Application</GroupName>
<Files>
<File>
<FileName>A31G12x_Interrupt.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\A31G12x_Interrupt.c</FilePath>
</File>
<File>
<FileName>A31G12x_Interrupt.h</FileName>
<FileType>5</FileType>
<FilePath>.\Application\A31G12x_Interrupt.h</FilePath>
</File>
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<FileType>1</FileType>
<FilePath>.\Application\A31G12x_SystemClock.c</FilePath>
</File>
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<FileName>A31G12x_SystemClock.h</FileName>
<FileType>5</FileType>
<FilePath>.\Application\A31G12x_SystemClock.h</FilePath>
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<File>
<FileName>define.h</FileName>
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<FilePath>.\Application\main.c</FilePath>
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<FilePath>.\Application\dbg_printf.c</FilePath>
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<FilePath>.\Application\sw_timer.c</FilePath>
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<FilePath>.\Application\ring_buffer.c</FilePath>
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<FilePath>.\Application\gpio_state_led.c</FilePath>
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<FilePath>.\Application\gpio_switch.c</FilePath>
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<FileName>uart1.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\uart1.c</FilePath>
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<File>
<FileName>segment_74hc595d.c</FileName>
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<FilePath>.\Application\segment_74hc595d.c</FilePath>
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<FileName>timer12.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\timer12.c</FilePath>
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<FileName>gpio_i2c.c</FileName>
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<FilePath>.\Application\gpio_i2c.c</FilePath>
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<FileType>1</FileType>
<FilePath>.\Application\spi10.c</FilePath>
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<FilePath>.\Application\buzzer.c</FilePath>
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<FileName>uart_packet.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\uart_packet.c</FilePath>
</File>
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</Group>
<Group>
<GroupName>Driver</GroupName>
<Files>
<File>
<FileName>A31G12x_hal_adc.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_adc.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_crc.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_crc.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_debug_frmwrk.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_debug_frmwrk.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_fmc.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_fmc.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_i2cn.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_i2cn.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_intc.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_intc.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_lcd.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_lcd.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_pcu.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_pcu.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_pwr.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_scu.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_scu.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_sculv.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_sculv.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_timer1n.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_timer1n.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_timer2n.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_timer2n.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_timer3n.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_timer3n.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_uartn.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_uartn.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_usart1n.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_usart1n.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_wdt.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_wdt.c</FilePath>
</File>
<File>
<FileName>A31G12x_hal_wt.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Drivers\Source\A31G12x_hal_wt.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Startup</GroupName>
<Files>
<File>
<FileName>startup_A31G12x.s</FileName>
<FileType>2</FileType>
<FilePath>.\SDK_V2_5_0\Device\Startup\startup_A31G12x.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Device</GroupName>
<Files>
<File>
<FileName>system_A31G12x.h</FileName>
<FileType>5</FileType>
<FilePath>.\SDK_V2_5_0\Device\Startup\system_A31G12x.h</FilePath>
</File>
<File>
<FileName>system_A31G12x.c</FileName>
<FileType>1</FileType>
<FilePath>.\SDK_V2_5_0\Device\Startup\system_A31G12x.c</FilePath>
</File>
<File>
<FileName>A31G12x.h</FileName>
<FileType>5</FileType>
<FilePath>.\SDK_V2_5_0\Device\Startup\A31G12x.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Option</GroupName>
<Files>
<File>
<FileName>option_A31G12x.s</FileName>
<FileType>2</FileType>
<FilePath>.\SDK_V2_5_0\Option\option_A31G12x.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>FATFS</GroupName>
<Files>
<File>
<FileName>fatfs.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\FATFS\App\fatfs.c</FilePath>
</File>
<File>
<FileName>user_diskio.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\FATFS\Target\user_diskio.c</FilePath>
</File>
<File>
<FileName>user_diskio_spi.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\FATFS\Target\user_diskio_spi.c</FilePath>
</File>
<File>
<FileName>diskio.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\Middlewares\Third_Party\FatFs\src\diskio.c</FilePath>
</File>
<File>
<FileName>ff.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\Middlewares\Third_Party\FatFs\src\ff.c</FilePath>
</File>
<File>
<FileName>ff_gen_drv.c</FileName>
<FileType>1</FileType>
<FilePath>.\Application\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>A31G12x_Project</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

89
Project/Application/A31G12x_Interrupt.c
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/***************************************************************************//**
* @file A31G12x_it.c
* @brief Contains all functions support for Exception & Interrupt Handler on A31G12x
*
*
*
* @version 1.00
* @date 2020-05-29
* @author ABOV Application Team
*
* Copyright(C) 2019, ABOV Semiconductor
* All rights reserved.
*
*//****************************************************************************/
#include "A31G12x_Interrupt.h"
/* Private typedef ---------------------------------------------------------- */
/* Private define ----------------------------------------------------------- */
/* Private macro ------------------------------------------------------------ */
/* Private define ----------------------------------------------------------- */
/* Private function prototypes ---------------------------------------------- */
/* Private variables -------------------------------------------------------- */
/******************************************************************************/
/* Cortex M0+ Processor Exceptions Handlers */
/******************************************************************************/
/*-------------------------------------------------------------------------*//**
* @brief This function handles NMI exception.
* @param None
* @return None
*//*-------------------------------------------------------------------------*/
void NMI_Handler( void )
{
}
/*-------------------------------------------------------------------------*//**
* @brief This function handles Hard Fault exception.
* @param None
* @return None
*//*-------------------------------------------------------------------------*/
void HardFault_Handler( void )
{
/* Go to infinite loop when Hard Fault exception occurs */
while( 1 )
{
}
}
/*-------------------------------------------------------------------------*//**
* @brief This function handles SVCall exception
* @param None
* @return None
*//*-------------------------------------------------------------------------*/
void SVC_Handler( void )
{
}
/*-------------------------------------------------------------------------*//**
* @brief This function handles PendSVC exception
* @param None
* @return None
*//*-------------------------------------------------------------------------*/
void PendSV_Handler( void )
{
}
/******************************************************************************/
/* A31G12x Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_A31G12x.s). */
/******************************************************************************/

52
Project/Application/A31G12x_Interrupt.h
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/** \file A31G12x_Interrupt.h */
/***************************************************************************//**
* @file A31G12x_it.h
* @brief Contains all macro definitions and function prototypes
* support for Exception & Interrupt Handler on A31G12x
*
*
* @version 1.00
* @date 2020-05-29
* @author ABOV Application Team
*
* Copyright(C) 2019, ABOV Semiconductor
* All rights reserved.
*
*//****************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#if !defined(A31G12X_INTERRUPT_H__8AA39883_A129_473E_A344_853E2B3D652F__INCLUDED_)
#define A31G12X_INTERRUPT_H__8AA39883_A129_473E_A344_853E2B3D652F__INCLUDED_
/* Includes ----------------------------------------------------------------- */
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ----------------------------------------------------------- */
/* Exported constants ------------------------------------------------------- */
/* Exported macro ----------------------------------------------------------- */
/* Exported functions ------------------------------------------------------- */
void NMI_Handler( void );
void HardFault_Handler( void );
void MemManage_Handler( void );
void BusFault_Handler( void );
void UsageFault_Handler( void );
void SVC_Handler( void );
void DebugMon_Handler( void );
void PendSV_Handler( void );
void SysTick_Handler( void );
#ifdef __cplusplus
}
#endif
#endif /* __A31G12x_IT_H */

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Project/Application/A31G12x_SystemClock.c
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/***************************************************************************//**
* @file A31G12x_SystemClock.c
* @brief Contains all functions support for Example Code on A31G12x
*
*
*
* @version 1.00
* @date 2020-05-29
* @author ABOV Application Team
*
* Copyright(C) 2019, ABOV Semiconductor
* All rights reserved.
*
*//****************************************************************************/
/*******************************************************************************
* A31G12x Device
*------------------------------------------------------------------------
* System Clock source | High Speend Internal oscillator
*------------------------------------------------------------------------
* SYSCLK(MHz) | 40MHz
*------------------------------------------------------------------------
* HCLK(MHz) - Core Clock | 40MHz
*------------------------------------------------------------------------
* PCLK(MHz) - Peri Clock | 40MHz
*------------------------------------------------------------------------
******************************************************************************/
#include "A31G12x_SystemClock.h"
/* Private typedef ---------------------------------------------------------- */
/* Private define ----------------------------------------------------------- */
/* Private macro ------------------------------------------------------------ */
/* Private variables -------------------------------------------------------- */
/* Private define ----------------------------------------------------------- */
// Main Clock Selection: Select only one of the following.
#define USED_HIRC /* HIRC : 40000000uL */
//#define USED_WDTRC /* WDTRC : 40000uL */
//#define USED_XMOSC /* XMOSC : 16000000uL */
//#define USED_XSOSC /* XSOSC : 32768uL */
/* Clock Out Selection ( Monitoring ) */
/*#define USED_CLKO*/
/* Private function prototypes ---------------------------------------------- */
void SystemClock_Config( void );
/* Private variables -------------------------------------------------------- */
/*-------------------------------------------------------------------------*//**
* @brief Initialize default clock for A31G12x Board
* @param None
* @return None
*//*-------------------------------------------------------------------------*/
void System_Clock_Initialization( void )
{
uint32_t i;
// enable clock source
HAL_SCU_ClockSource_Enable( CLKSRCR_HIRCEN | CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN | CLKSRCR_WDTRCEN, HIRCSEL_HIRC1 );
for( i = 0; i < 1000; i++ ); // Clock Stable Time
// select system clock
#ifdef USED_WDTRC
HAL_SCU_SystemClockDivider( WLDIV_MCLK64 | HDIV_MCLK1, SYSTDIV_HCLK1 | PDIV_HCLK1 ); // WT/LCD | HCLK, SysTick | PCLK
HAL_SCU_SystemClockChange( MCLKSEL_WDTRC );
SystemCoreClock = 40000uL; // HCLK
SystemPeriClock = 40000uL; // PCLK
#endif
#ifdef USED_XSOSC
HAL_SCU_SystemClockDivider( WLDIV_MCLK64 | HDIV_MCLK1, SYSTDIV_HCLK1 | PDIV_HCLK1 ); // WT/LCD | HCLK, SysTick | PCLK
HAL_SCU_SystemClockChange( MCLKSEL_XSOSC );
SystemCoreClock = 32768uL; // HCLK
SystemPeriClock = 32768uL; // PCLK
#endif
#ifdef USED_XMOSC
HAL_SCU_SystemClockChange( MCLKSEL_XMOSC );
HAL_SCU_SystemClockDivider( WLDIV_MCLK64 | HDIV_MCLK1, SYSTDIV_HCLK1 | PDIV_HCLK1 ); // WT/LCD | HCLK, SysTick | PCLK
SystemCoreClock = 16000000uL; // HCLK
SystemPeriClock = 16000000uL; // PCLK
#endif
#ifdef USED_HIRC
HAL_SCU_SystemClockChange( MCLKSEL_HIRC );
HAL_SCU_SystemClockDivider( WLDIV_MCLK64 | HDIV_MCLK1, SYSTDIV_HCLK1 | PDIV_HCLK1 ); // WT/LCD | HCLK, SysTick | PCLK
SystemCoreClock = 40000000uL; // HCLK
SystemPeriClock = 40000000uL; // PCLK
#endif
// disable unused clock source
//HAL_SCU_ClockSource_Disable( CLKSRCR_XMOSCEN | CLKSRCR_XSOSCEN );
// enable clock monitoring
HAL_SCU_ClockMonitoring( MACTS_SysClkChg, MONCS_MCLK );
// enable clock output
#ifdef USED_CLKO
HAL_SCU_CLKO_PinConfig();
HAL_SCU_ClockOutput( CLKOS_MCLK, POLSEL_Low, CLKODIV_SelectedClock1 );
#endif
HAL_SCU_Peripheral_ClockConfig(0x00003FuL, 0x000000L); // Enable All Ports,
}
void Systick_Initialization(uint32_t SysticTime)
{
if(SysticTime > 1000)
{
SysticTime = 1000;
}
SysTick_Config( SystemCoreClock / (1000 / SysticTime) );
}

11
Project/Application/A31G12x_SystemClock.h
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/** \file A31G12x_SystemClock.h */
#if !defined(A31G12X_SYSTEMCLOCK_H__CC394B1C_0861_4187_A351_DE0A4FCEDED0__INCLUDED_)
#define A31G12X_SYSTEMCLOCK_H__CC394B1C_0861_4187_A351_DE0A4FCEDED0__INCLUDED_
#include "define.h"
void System_Clock_Initialization( void );
void Systick_Initialization(uint32_t SysticTime);
#endif

56
Project/Application/FATFS/App/fatfs.c
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/**
******************************************************************************
* @file fatfs.c
* @brief Code for fatfs applications
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
#include "fatfs.h"
uint8_t retUSER; /* Return value for USER */
char USERPath[4]; /* USER logical drive path */
FATFS USERFatFS; /* File system object for USER logical drive */
FIL USERFile; /* File object for USER */
/* USER CODE BEGIN Variables */
/* USER CODE END Variables */
void MX_FATFS_Init(void)
{
/*## FatFS: Link the USER driver ###########################*/
retUSER = FATFS_LinkDriver(&USER_Driver, USERPath);
/* USER CODE BEGIN Init */
/* additional user code for init */
/* USER CODE END Init */
}
/**
* @brief Gets Time from RTC
* @param None
* @retval Time in DWORD
*/
DWORD get_fattime(void)
{
/* USER CODE BEGIN get_fattime */
return 0;
/* USER CODE END get_fattime */
}
/* USER CODE BEGIN Application */
/* USER CODE END Application */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Project/Application/FATFS/App/fatfs.h
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/**
******************************************************************************
* @file fatfs.h
* @brief Header for fatfs applications
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __fatfs_H
#define __fatfs_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ff.h"
#include "ff_gen_drv.h"
#include "user_diskio.h" /* defines USER_Driver as external */
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern uint8_t retUSER; /* Return value for USER */
extern char USERPath[4]; /* USER logical drive path */
extern FATFS USERFatFS; /* File system object for USER logical drive */
extern FIL USERFile; /* File object for USER */
void MX_FATFS_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__fatfs_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* FatFs - FAT file system module configuration file R0.11 (C)ChaN, 2015
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* USER CODE END Header */
#ifndef _FFCONF
#define _FFCONF 32020 /* Revision ID */
/*-----------------------------------------------------------------------------/
/ Additional user header to be used
/-----------------------------------------------------------------------------*/
#include "main.h"
/*-----------------------------------------------------------------------------/
/ Functions and Buffer Configurations
/-----------------------------------------------------------------------------*/
#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of the file object (FIL) is reduced _MAX_SS
/ bytes. Instead of private sector buffer eliminated from the file object,
/ common sector buffer in the file system object (FATFS) is used for the file
/ data transfer. */
#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
/ and optional writing functions as well. */
#define _FS_MINIMIZE 0 /* 0 to 3 */
/* This option defines minimization level to remove some basic API functions.
/
/ 0: All basic functions are enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(),
/ f_truncate() and f_rename() function are removed.
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */
/* This option switches string functions, f_gets(), f_putc(), f_puts() and
/ f_printf().
/
/ 0: Disable string functions.
/ 1: Enable without LF-CRLF conversion.
/ 2: Enable with LF-CRLF conversion. */
#define _USE_FIND 0
/* This option switches filtered directory read feature and related functions,
/ f_findfirst() and f_findnext(). (0:Disable or 1:Enable) */
#define _USE_MKFS 1
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
#define _USE_FASTSEEK 1
/* This option switches fast seek feature. (0:Disable or 1:Enable) */
#define _USE_LABEL 0
/* This option switches volume label functions, f_getlabel() and f_setlabel().
/ (0:Disable or 1:Enable) */
#define _USE_FORWARD 0
/* This option switches f_forward() function. (0:Disable or 1:Enable)
/ To enable it, also _FS_TINY need to be set to 1. */
/*-----------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/-----------------------------------------------------------------------------*/
#define _CODE_PAGE 850
/* This option specifies the OEM code page to be used on the target system.
/ Incorrect setting of the code page can cause a file open failure.
/
/ 932 - Japanese Shift_JIS (DBCS, OEM, Windows)
/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
/ 949 - Korean (DBCS, OEM, Windows)
/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
/ 1250 - Central Europe (Windows)
/ 1251 - Cyrillic (Windows)
/ 1252 - Latin 1 (Windows)
/ 1253 - Greek (Windows)
/ 1254 - Turkish (Windows)
/ 1255 - Hebrew (Windows)
/ 1256 - Arabic (Windows)
/ 1257 - Baltic (Windows)
/ 1258 - Vietnam (OEM, Windows)
/ 437 - U.S. (OEM)
/ 720 - Arabic (OEM)
/ 737 - Greek (OEM)
/ 775 - Baltic (OEM)
/ 850 - Multilingual Latin 1 (OEM)
/ 858 - Multilingual Latin 1 + Euro (OEM)
/ 852 - Latin 2 (OEM)
/ 855 - Cyrillic (OEM)
/ 866 - Russian (OEM)
/ 857 - Turkish (OEM)
/ 862 - Hebrew (OEM)
/ 874 - Thai (OEM, Windows)
/ 1 - ASCII (No extended character. Valid for only non-LFN configuration.) */
#define _USE_LFN 0 /* 0 to 3 */
#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
/* The _USE_LFN option switches the LFN feature.
/
/ 0: Disable LFN feature. _MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ When enable the LFN feature, Unicode handling functions (option/unicode.c) must
/ be added to the project. The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes.
/ When use stack for the working buffer, take care on stack overflow. When use heap
/ memory for the working buffer, memory management functions, ff_memalloc() and
/ ff_memfree(), must be added to the project. */
#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
/* This option switches character encoding on the API. (0:ANSI/OEM or 1:Unicode)
/ To use Unicode string for the path name, enable LFN feature and set _LFN_UNICODE
/ to 1. This option also affects behavior of string I/O functions. */
#define _STRF_ENCODE 3
/* When _LFN_UNICODE is 1, this option selects the character encoding on the file to
/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
/
/ 0: ANSI/OEM
/ 1: UTF-16LE
/ 2: UTF-16BE
/ 3: UTF-8
/
/ When _LFN_UNICODE is 0, this option has no effect. */
#define _FS_RPATH 0 /* 0 to 2 */
/* This option configures relative path feature.
/
/ 0: Disable relative path feature and remove related functions.
/ 1: Enable relative path feature. f_chdir() and f_chdrive() are available.
/ 2: f_getcwd() function is available in addition to 1.
/
/ Note that directory items read via f_readdir() are affected by this option. */
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/----------------------------------------------------------------------------*/
#define _VOLUMES 1
/* Number of volumes (logical drives) to be used. */
/* USER CODE BEGIN Volumes */
#define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
/* _STR_VOLUME_ID option switches string volume ID feature.
/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
/ number in the path name. _VOLUME_STRS defines the drive ID strings for each
/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for
/ the drive ID strings are: A-Z and 0-9. */
/* USER CODE END Volumes */
#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Multiple partition */
/* This option switches multi-partition feature. By default (0), each logical drive
/ number is bound to the same physical drive number and only an FAT volume found on
/ the physical drive will be mounted. When multi-partition feature is enabled (1),
/ each logical drive number is bound to arbitrary physical drive and partition
/ listed in the VolToPart[]. Also f_fdisk() funciton will be available. */
#define _MIN_SS 512 /* 512, 1024, 2048 or 4096 */
#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
/* These options configure the range of sector size to be supported. (512, 1024,
/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and
/ harddisk. But a larger value may be required for on-board flash memory and some
/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the
/ disk_ioctl() function. */
#define _USE_TRIM 0
/* This option switches ATA-TRIM feature. (0:Disable or 1:Enable)
/ To enable Trim feature, also CTRL_TRIM command should be implemented to the
/ disk_ioctl() function. */
#define _FS_NOFSINFO 0 /* 0,1,2 or 3 */
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
/ option, and f_getfree() function at first time after volume mount will force
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
*/
/*---------------------------------------------------------------------------/
/ System Configurations
/----------------------------------------------------------------------------*/
#define _FS_NORTC 0
#define _NORTC_MON 6
#define _NORTC_MDAY 4
#define _NORTC_YEAR 2015
/* The _FS_NORTC option switches timestamp feature. If the system does not have
/ an RTC function or valid timestamp is not needed, set _FS_NORTC to 1 to disable
/ the timestamp feature. All objects modified by FatFs will have a fixed timestamp
/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR.
/ When timestamp feature is enabled (_FS_NORTC == 0), get_fattime() function need
/ to be added to the project to read current time form RTC. _NORTC_MON,
/ _NORTC_MDAY and _NORTC_YEAR have no effect.
/ These options have no effect at read-only configuration (_FS_READONLY == 1). */
#define _FS_LOCK 2 /* 0:Disable or >=1:Enable */
/* The _FS_LOCK option switches file lock feature to control duplicated file open
/ and illegal operation to open objects. This option must be 0 when _FS_READONLY
/ is 1.
/
/ 0: Disable file lock feature. To avoid volume corruption, application program
/ should avoid illegal open, remove and rename to the open objects.
/ >0: Enable file lock feature. The value defines how many files/sub-directories
/ can be opened simultaneously under file lock control. Note that the file
/ lock feature is independent of re-entrancy. */
#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
#define _SYNC_t NULL
/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs
/ module itself. Note that regardless of this option, file access to different
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
/ to the same volume is under control of this feature.
/
/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
/ function, must be added to the project. Samples are available in
/ option/syscall.c.
/
/ The _FS_TIMEOUT defines timeout period in unit of time tick.
/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
/ SemaphoreHandle_t and etc.. */
#define _WORD_ACCESS 0 /* 0 or 1 */
/* The _WORD_ACCESS option is an only platform dependent option. It defines
/ which access method is used to the word data on the FAT volume.
/
/ 0: Byte-by-byte access. Always compatible with all platforms.
/ 1: Word access. Do not choose this unless under both the following conditions.
/
/ * Address misaligned memory access is always allowed to ALL instructions.
/ * Byte order on the memory is little-endian.
/
/ If it is the case, _WORD_ACCESS can also be set to 1 to reduce code size.
/ Following table shows allowable settings of some processor types.
/
/ ARM7TDMI 0 ColdFire 0 V850E 0
/ Cortex-M3 0 Z80 0/1 V850ES 0/1
/ Cortex-M0 0 x86 0/1 TLCS-870 0/1
/ AVR 0/1 RX600(LE) 0/1 TLCS-900 0/1
/ AVR32 0 RL78 0 R32C 0
/ PIC18 0/1 SH-2 0 M16C 0/1
/ PIC24 0 H8S 0 MSP430 0
/ PIC32 0 H8/300H 0 8051 0/1
*/
#endif /* _FFCONF */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file user_diskio.c
* @brief This file includes a diskio driver skeleton to be completed by the user.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* USER CODE END Header */
#ifdef USE_OBSOLETE_USER_CODE_SECTION_0
/*
* Warning: the user section 0 is no more in use (starting from CubeMx version 4.16.0)
* To be suppressed in the future.
* Kept to ensure backward compatibility with previous CubeMx versions when
* migrating projects.
* User code previously added there should be copied in the new user sections before
* the section contents can be deleted.
*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
#endif
/* USER CODE BEGIN DECL */
/* Includes ------------------------------------------------------------------*/
#include <string.h>
#include "ff_gen_drv.h"
#include "user_diskio_spi.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Disk status */
static volatile DSTATUS Stat = STA_NOINIT;
/* USER CODE END DECL */
/* Private function prototypes -----------------------------------------------*/
DSTATUS USER_initialize (BYTE pdrv);
DSTATUS USER_status (BYTE pdrv);
DRESULT USER_read (BYTE pdrv, BYTE *buff, DWORD sector, UINT count);
#if _USE_WRITE == 1
DRESULT USER_write (BYTE pdrv, const BYTE *buff, DWORD sector, UINT count);
#endif /* _USE_WRITE == 1 */
#if _USE_IOCTL == 1
DRESULT USER_ioctl (BYTE pdrv, BYTE cmd, void *buff);
#endif /* _USE_IOCTL == 1 */
Diskio_drvTypeDef USER_Driver =
{
USER_initialize,
USER_status,
USER_read,
#if _USE_WRITE
USER_write,
#endif /* _USE_WRITE == 1 */
#if _USE_IOCTL == 1
USER_ioctl,
#endif /* _USE_IOCTL == 1 */
};
/* Private functions ---------------------------------------------------------*/
/**
* @brief Initializes a Drive
* @param pdrv: Physical drive number (0..)
* @retval DSTATUS: Operation status
*/
DSTATUS USER_initialize (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
/* USER CODE BEGIN INIT */
return USER_SPI_initialize(pdrv);
/* USER CODE END INIT */
}
/**
* @brief Gets Disk Status
* @param pdrv: Physical drive number (0..)
* @retval DSTATUS: Operation status
*/
DSTATUS USER_status (
BYTE pdrv /* Physical drive number to identify the drive */
)
{
/* USER CODE BEGIN STATUS */
return USER_SPI_status(pdrv);
/* USER CODE END STATUS */
}
/**
* @brief Reads Sector(s)
* @param pdrv: Physical drive number (0..)
* @param *buff: Data buffer to store read data
* @param sector: Sector address (LBA)
* @param count: Number of sectors to read (1..128)
* @retval DRESULT: Operation result
*/
DRESULT USER_read (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
BYTE *buff, /* Data buffer to store read data */
DWORD sector, /* Sector address in LBA */
UINT count /* Number of sectors to read */
)
{
/* USER CODE BEGIN READ */
return USER_SPI_read(pdrv, buff, sector, count);
/* USER CODE END READ */
}
/**
* @brief Writes Sector(s)
* @param pdrv: Physical drive number (0..)
* @param *buff: Data to be written
* @param sector: Sector address (LBA)
* @param count: Number of sectors to write (1..128)
* @retval DRESULT: Operation result
*/
#if _USE_WRITE == 1
DRESULT USER_write (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
const BYTE *buff, /* Data to be written */
DWORD sector, /* Sector address in LBA */
UINT count /* Number of sectors to write */
)
{
/* USER CODE BEGIN WRITE */
/* USER CODE HERE */
return USER_SPI_write(pdrv, buff, sector, count);
/* USER CODE END WRITE */
}
#endif /* _USE_WRITE == 1 */
/**
* @brief I/O control operation
* @param pdrv: Physical drive number (0..)
* @param cmd: Control code
* @param *buff: Buffer to send/receive control data
* @retval DRESULT: Operation result
*/
#if _USE_IOCTL == 1
DRESULT USER_ioctl (
BYTE pdrv, /* Physical drive nmuber (0..) */
BYTE cmd, /* Control code */
void *buff /* Buffer to send/receive control data */
)
{
/* USER CODE BEGIN IOCTL */
return USER_SPI_ioctl(pdrv, cmd, buff);
/* USER CODE END IOCTL */
}
#endif /* _USE_IOCTL == 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file user_diskio.h
* @brief This file contains the common defines and functions prototypes for
* the user_diskio driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USER_DISKIO_H
#define __USER_DISKIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE BEGIN 0 */
/* Includes ------------------------------------------------------------------*/
#include "user_diskio_spi.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
extern Diskio_drvTypeDef USER_Driver;
/* USER CODE END 0 */
#ifdef __cplusplus
}
#endif
#endif /* __USER_DISKIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file user_diskio_spi.c
* @brief This file contains the implementation of the user_diskio_spi FatFs
* driver.
******************************************************************************
* Portions copyright (C) 2014, ChaN, all rights reserved.
* Portions copyright (C) 2017, kiwih, all rights reserved.
*
* This software is a free software and there is NO WARRANTY.
* No restriction on use. You can use, modify and redistribute it for
* personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
* Redistributions of source code must retain the above copyright notice.
*
******************************************************************************
*/
//This code was ported by kiwih from a copywrited (C) library written by ChaN
//available at http://elm-chan.org/fsw/ff/ffsample.zip
//(text at http://elm-chan.org/fsw/ff/00index_e.html)
//This file provides the FatFs driver functions and SPI code required to manage
//an SPI-connected MMC or compatible SD card with FAT
//It is designed to be wrapped by a cubemx generated user_diskio.c file.
#include "user_diskio_spi.h"
#include "spi10.h"
//Make sure you set #define SD_SPI_HANDLE as some hspix in main.h
//Make sure you set #define SD_CS_GPIO_Port as some GPIO port in main.h
//Make sure you set #define SD_CS_Pin as some GPIO pin in main.h
/* Function prototypes */
//(Note that the _256 is used as a mask to clear the prescalar bits as it provides binary 111 in the correct position)
#define FCLK_SLOW() { SPI10_Initialization(250000, SPI10_MODE0, false); } /* Set SCLK = slow, approx 280 KBits/s*/
#define FCLK_FAST() { SPI10_Initialization(4500000, SPI10_MODE0, false); } /* Set SCLK = fast, approx 4.5 MBits/s */
#define CS_HIGH() {SPI10_CS_HIGH;}
#define CS_LOW() {SPI10_CS_LOW;}
/*--------------------------------------------------------------------------
Module Private Functions
---------------------------------------------------------------------------*/
/* MMC/SD command */
#define CMD0 (0) /* GO_IDLE_STATE */
#define CMD1 (1) /* SEND_OP_COND (MMC) */
#define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */
#define CMD8 (8) /* SEND_IF_COND */
#define CMD9 (9) /* SEND_CSD */
#define CMD10 (10) /* SEND_CID */
#define CMD12 (12) /* STOP_TRANSMISSION */
#define ACMD13 (0x80+13) /* SD_STATUS (SDC) */
#define CMD16 (16) /* SET_BLOCKLEN */
#define CMD17 (17) /* READ_SINGLE_BLOCK */
#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
#define CMD23 (23) /* SET_BLOCK_COUNT (MMC) */
#define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24 (24) /* WRITE_BLOCK */
#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
#define CMD32 (32) /* ERASE_ER_BLK_START */
#define CMD33 (33) /* ERASE_ER_BLK_END */
#define CMD38 (38) /* ERASE */
#define CMD55 (55) /* APP_CMD */
#define CMD58 (58) /* READ_OCR */
/* MMC card type flags (MMC_GET_TYPE) */
#define CT_MMC 0x01 /* MMC ver 3 */
#define CT_SD1 0x02 /* SD ver 1 */
#define CT_SD2 0x04 /* SD ver 2 */
#define CT_SDC (CT_SD1|CT_SD2) /* SD */
#define CT_BLOCK 0x08 /* Block addressing */
static volatile
DSTATUS Stat = STA_NOINIT; /* Physical drive status */
static
BYTE CardType; /* Card type flags */
uint32_t spiTimerTickStart;
uint32_t spiTimerTickDelay;
void SPI_Timer_On(uint32_t waitTicks) {
spiTimerTickStart = millis();
spiTimerTickDelay = waitTicks;
}
uint8_t SPI_Timer_Status() {
return ((millis() - spiTimerTickStart) < spiTimerTickDelay);
}
/*-----------------------------------------------------------------------*/
/* SPI controls (Platform dependent) */
/*-----------------------------------------------------------------------*/
/* Exchange a byte */
static
BYTE xchg_spi (
BYTE dat /* Data to send */
)
{
BYTE rxDat;
rxDat = SPI10_SendReceiveByte(dat);
return rxDat;
}
/* Receive multiple byte */
static
void rcvr_spi_multi (
BYTE *buff, /* Pointer to data buffer */
UINT btr /* Number of bytes to receive (even number) */
)
{
for(UINT i=0; i<btr; i++) {
*(buff+i) = xchg_spi(0xFF);
}
}
#if _USE_WRITE
/* Send multiple byte */
static
void xmit_spi_multi (
const BYTE *buff, /* Pointer to the data */
UINT btx /* Number of bytes to send (even number) */
)
{
//HAL_SPI_Transmit(&SD_SPI_HANDLE, buff, btx, HAL_MAX_DELAY);
SPI10_Transmit((uint8_t *)buff, btx);
}
#endif
/*-----------------------------------------------------------------------*/
/* Wait for card ready */
/*-----------------------------------------------------------------------*/
static
int wait_ready ( /* 1:Ready, 0:Timeout */
UINT wt /* Timeout [ms] */
)
{
BYTE d;
//wait_ready needs its own timer, unfortunately, so it can't use the
//spi_timer functions
uint32_t waitSpiTimerTickStart;
uint32_t waitSpiTimerTickDelay;
waitSpiTimerTickStart = millis();
waitSpiTimerTickDelay = (uint32_t)wt;
do {
d = xchg_spi(0xFF);
/* This loop takes a time. Insert rot_rdq() here for multitask envilonment. */
} while (d != 0xFF && ((millis() - waitSpiTimerTickStart) < waitSpiTimerTickDelay)); /* Wait for card goes ready or timeout */
return (d == 0xFF) ? 1 : 0;
}
/*-----------------------------------------------------------------------*/
/* Despiselect card and release SPI */
/*-----------------------------------------------------------------------*/
static
void despiselect (void)
{
CS_HIGH(); /* Set CS# high */
xchg_spi(0xFF); /* Dummy clock (force DO hi-z for multiple slave SPI) */
}
/*-----------------------------------------------------------------------*/
/* Select card and wait for ready */
/*-----------------------------------------------------------------------*/
static
int spiselect (void) /* 1:OK, 0:Timeout */
{
CS_LOW(); /* Set CS# low */
xchg_spi(0xFF); /* Dummy clock (force DO enabled) */
if (wait_ready(500)) return 1; /* Wait for card ready */
despiselect();
return 0; /* Timeout */
}
/*-----------------------------------------------------------------------*/
/* Receive a data packet from the MMC */
/*-----------------------------------------------------------------------*/
static
int rcvr_datablock ( /* 1:OK, 0:Error */
BYTE *buff, /* Data buffer */
UINT btr /* Data block length (byte) */
)
{
BYTE token;
SPI_Timer_On(200);
do { /* Wait for DataStart token in timeout of 200ms */
token = xchg_spi(0xFF);
/* This loop will take a time. Insert rot_rdq() here for multitask envilonment. */
} while ((token == 0xFF) && SPI_Timer_Status());
if(token != 0xFE) return 0; /* Function fails if invalid DataStart token or timeout */
rcvr_spi_multi(buff, btr); /* Store trailing data to the buffer */
xchg_spi(0xFF); xchg_spi(0xFF); /* Discard CRC */
return 1; /* Function succeeded */
}
/*-----------------------------------------------------------------------*/
/* Send a data packet to the MMC */
/*-----------------------------------------------------------------------*/
#if _USE_WRITE
static
int xmit_datablock ( /* 1:OK, 0:Failed */
const BYTE *buff, /* Ponter to 512 byte data to be sent */
BYTE token /* Token */
)
{
BYTE resp;
if (!wait_ready(500)) return 0; /* Wait for card ready */
xchg_spi(token); /* Send token */
if (token != 0xFD) { /* Send data if token is other than StopTran */
xmit_spi_multi(buff, 512); /* Data */
xchg_spi(0xFF); xchg_spi(0xFF); /* Dummy CRC */
resp = xchg_spi(0xFF); /* Receive data resp */
if ((resp & 0x1F) != 0x05) return 0; /* Function fails if the data packet was not accepted */
}
return 1;
}
#endif
/*-----------------------------------------------------------------------*/
/* Send a command packet to the MMC */
/*-----------------------------------------------------------------------*/
static
BYTE send_cmd ( /* Return value: R1 resp (bit7==1:Failed to send) */
BYTE cmd, /* Command index */
DWORD arg /* Argument */
)
{
BYTE n, res;
if (cmd & 0x80) { /* Send a CMD55 prior to ACMD<n> */
cmd &= 0x7F;
res = send_cmd(CMD55, 0);
if (res > 1) return res;
}
/* Select the card and wait for ready except to stop multiple block read */
if (cmd != CMD12) {
despiselect();
if (!spiselect()) return 0xFF;
}
/* Send command packet */
xchg_spi(0x40 | cmd); /* Start + command index */
xchg_spi((BYTE)(arg >> 24)); /* Argument[31..24] */
xchg_spi((BYTE)(arg >> 16)); /* Argument[23..16] */
xchg_spi((BYTE)(arg >> 8)); /* Argument[15..8] */
xchg_spi((BYTE)arg); /* Argument[7..0] */
n = 0x01; /* Dummy CRC + Stop */
if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) */
if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) */
xchg_spi(n);
/* Receive command resp */
if (cmd == CMD12) xchg_spi(0xFF); /* Diacard following one byte when CMD12 */
n = 10; /* Wait for response (10 bytes max) */
do {
res = xchg_spi(0xFF);
} while ((res & 0x80) && --n);
return res; /* Return received response */
}
/*--------------------------------------------------------------------------
Public FatFs Functions (wrapped in user_diskio.c)
---------------------------------------------------------------------------*/
//The following functions are defined as inline because they aren't the functions that
//are passed to FatFs - they are wrapped by autogenerated (non-inline) cubemx template
//code.
//If you do not wish to use cubemx, remove the "inline" from these functions here
//and in the associated .h
/*-----------------------------------------------------------------------*/
/* Initialize disk drive */
/*-----------------------------------------------------------------------*/
inline DSTATUS USER_SPI_initialize (
BYTE drv /* Physical drive number (0) */
)
{
BYTE n, cmd, ty, ocr[4];
if (drv != 0) return STA_NOINIT; /* Supports only drive 0 */
//assume SPI already init init_spi(); /* Initialize SPI */
if (Stat & STA_NODISK) return Stat; /* Is card existing in the soket? */
FCLK_SLOW();
for (n = 10; n; n--) xchg_spi(0xFF); /* Send 80 dummy clocks */
ty = 0;
if (send_cmd(CMD0, 0) == 1) { /* Put the card SPI/Idle state */
SPI_Timer_On(1000); /* Initialization timeout = 1 sec */
if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */
for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); /* Get 32 bit return value of R7 resp */
if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* Is the card supports vcc of 2.7-3.6V? */
while (SPI_Timer_Status() && send_cmd(ACMD41, 1UL << 30)) ; /* Wait for end of initialization with ACMD41(HCS) */
if (SPI_Timer_Status() && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */
for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF);
ty = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* Card id SDv2 */
}
}
} else { /* Not SDv2 card */
if (send_cmd(ACMD41, 0) <= 1) { /* SDv1 or MMC? */
ty = CT_SD1; cmd = ACMD41; /* SDv1 (ACMD41(0)) */
} else {
ty = CT_MMC; cmd = CMD1; /* MMCv3 (CMD1(0)) */
}
while (SPI_Timer_Status() && send_cmd(cmd, 0)) ; /* Wait for end of initialization */
if (!SPI_Timer_Status() || send_cmd(CMD16, 512) != 0) /* Set block length: 512 */
ty = 0;
}
}
CardType = ty; /* Card type */
despiselect();
if (ty) { /* OK */
FCLK_FAST(); /* Set fast clock */
Stat &= ~STA_NOINIT; /* Clear STA_NOINIT flag */
} else { /* Failed */
Stat = STA_NOINIT;
}
return Stat;
}
/*-----------------------------------------------------------------------*/
/* Get disk status */
/*-----------------------------------------------------------------------*/
inline DSTATUS USER_SPI_status (
BYTE drv /* Physical drive number (0) */
)
{
if (drv) return STA_NOINIT; /* Supports only drive 0 */
return Stat; /* Return disk status */
}
/*-----------------------------------------------------------------------*/
/* Read sector(s) */
/*-----------------------------------------------------------------------*/
inline DRESULT USER_SPI_read (
BYTE drv, /* Physical drive number (0) */
BYTE *buff, /* Pointer to the data buffer to store read data */
DWORD sector, /* Start sector number (LBA) */
UINT count /* Number of sectors to read (1..128) */
)
{
if (drv || !count) return RES_PARERR; /* Check parameter */
if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check if drive is ready */
if (!(CardType & CT_BLOCK)) sector *= 512; /* LBA ot BA conversion (byte addressing cards) */
if (count == 1) { /* Single sector read */
if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */
&& rcvr_datablock(buff, 512)) {
count = 0;
}
}
else { /* Multiple sector read */
if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */
do {
if (!rcvr_datablock(buff, 512)) break;
buff += 512;
} while (--count);
send_cmd(CMD12, 0); /* STOP_TRANSMISSION */
}
}
despiselect();
return count ? RES_ERROR : RES_OK; /* Return result */
}
/*-----------------------------------------------------------------------*/
/* Write sector(s) */
/*-----------------------------------------------------------------------*/
#if _USE_WRITE
inline DRESULT USER_SPI_write (
BYTE drv, /* Physical drive number (0) */
const BYTE *buff, /* Ponter to the data to write */
DWORD sector, /* Start sector number (LBA) */
UINT count /* Number of sectors to write (1..128) */
)
{
if (drv || !count) return RES_PARERR; /* Check parameter */
if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check drive status */
if (Stat & STA_PROTECT) return RES_WRPRT; /* Check write protect */
if (!(CardType & CT_BLOCK)) sector *= 512; /* LBA ==> BA conversion (byte addressing cards) */
if (count == 1) { /* Single sector write */
if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */
&& xmit_datablock(buff, 0xFE)) {
count = 0;
}
}
else { /* Multiple sector write */
if (CardType & CT_SDC) send_cmd(ACMD23, count); /* Predefine number of sectors */
if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */
do {
if (!xmit_datablock(buff, 0xFC)) break;
buff += 512;
} while (--count);
if (!xmit_datablock(0, 0xFD)) count = 1; /* STOP_TRAN token */
}
}
despiselect();
return count ? RES_ERROR : RES_OK; /* Return result */
}
#endif
/*-----------------------------------------------------------------------*/
/* Miscellaneous drive controls other than data read/write */
/*-----------------------------------------------------------------------*/
#if _USE_IOCTL
inline DRESULT USER_SPI_ioctl (
BYTE drv, /* Physical drive number (0) */
BYTE cmd, /* Control command code */
void *buff /* Pointer to the conrtol data */
)
{
DRESULT res;
BYTE n, csd[16];
DWORD *dp, st, ed, csize;
if (drv) return RES_PARERR; /* Check parameter */
if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check if drive is ready */
res = RES_ERROR;
switch (cmd) {
case CTRL_SYNC : /* Wait for end of internal write process of the drive */
if (spiselect()) res = RES_OK;
break;
case GET_SECTOR_COUNT : /* Get drive capacity in unit of sector (DWORD) */
if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) {
if ((csd[0] >> 6) == 1) { /* SDC ver 2.00 */
csize = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1;
*(DWORD*)buff = csize << 10;
} else { /* SDC ver 1.XX or MMC ver 3 */
n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
csize = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1;
*(DWORD*)buff = csize << (n - 9);
}
res = RES_OK;
}
break;
case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
if (CardType & CT_SD2) { /* SDC ver 2.00 */
if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */
xchg_spi(0xFF);
if (rcvr_datablock(csd, 16)) { /* Read partial block */
for (n = 64 - 16; n; n--) xchg_spi(0xFF); /* Purge trailing data */
*(DWORD*)buff = 16UL << (csd[10] >> 4);
res = RES_OK;
}
}
} else { /* SDC ver 1.XX or MMC */
if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */
if (CardType & CT_SD1) { /* SDC ver 1.XX */
*(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1);
} else { /* MMC */
*(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1);
}
res = RES_OK;
}
}
break;
case CTRL_TRIM : /* Erase a block of sectors (used when _USE_ERASE == 1) */
if (!(CardType & CT_SDC)) break; /* Check if the card is SDC */
if (USER_SPI_ioctl(drv, MMC_GET_CSD, csd)) break; /* Get CSD */
if (!(csd[0] >> 6) && !(csd[10] & 0x40)) break; /* Check if sector erase can be applied to the card */
dp = buff; st = dp[0]; ed = dp[1]; /* Load sector block */
if (!(CardType & CT_BLOCK)) {
st *= 512; ed *= 512;
}
if (send_cmd(CMD32, st) == 0 && send_cmd(CMD33, ed) == 0 && send_cmd(CMD38, 0) == 0 && wait_ready(30000)) { /* Erase sector block */
res = RES_OK; /* FatFs does not check result of this command */
}
break;
default:
res = RES_PARERR;
}
despiselect();
return res;
}
#endif

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/**
******************************************************************************
* @file user_diskio_spi.h
* @brief This file contains the common defines and functions prototypes for
* the user_diskio_spi driver implementation
******************************************************************************
* Portions copyright (C) 2014, ChaN, all rights reserved.
* Portions copyright (C) 2017, kiwih, all rights reserved.
*
* This software is a free software and there is NO WARRANTY.
* No restriction on use. You can use, modify and redistribute it for
* personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
* Redistributions of source code must retain the above copyright notice.
*
******************************************************************************
*/
#ifndef _USER_DISKIO_SPI_H
#define _USER_DISKIO_SPI_H
#include "integer.h" //from FatFs middleware library
#include "diskio.h" //from FatFs middleware library
#include "ff_gen_drv.h" //from FatFs middleware library
//we define these as inline because we don't want them to be actual function calls (they get "called" from the cubemx autogenerated user_diskio file)
//we define them as extern because they are defined in a separate .c file to user_diskio.c (which #includes this .h file)
extern DSTATUS USER_SPI_initialize (BYTE pdrv);
extern DSTATUS USER_SPI_status (BYTE pdrv);
extern DRESULT USER_SPI_read (BYTE pdrv, BYTE *buff, DWORD sector, UINT count);
#if _USE_WRITE == 1
extern DRESULT USER_SPI_write (BYTE pdrv, const BYTE *buff, DWORD sector, UINT count);
#endif /* _USE_WRITE == 1 */
#if _USE_IOCTL == 1
extern DRESULT USER_SPI_ioctl (BYTE pdrv, BYTE cmd, void *buff);
#endif /* _USE_IOCTL == 1 */
#endif

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/*-----------------------------------------------------------------------*/
/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2014 */
/* */
/* Portions COPYRIGHT 2015 STMicroelectronics */
/* Portions Copyright (C) 2014, ChaN, all right reserved */
/*-----------------------------------------------------------------------*/
/* If a working storage control module is available, it should be */
/* attached to the FatFs via a glue function rather than modifying it. */
/* This is an example of glue functions to attach various exsisting */
/* storage control modules to the FatFs module with a defined API. */
/*-----------------------------------------------------------------------*/
/**
******************************************************************************
* @file diskio.c
* @author MCD Application Team
* @version V1.3.0
* @date 08-May-2015
* @brief FatFs low level disk I/O module.
******************************************************************************
* @attention
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "diskio.h"
#include "ff_gen_drv.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
extern Disk_drvTypeDef disk;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief Gets Disk Status
* @param pdrv: Physical drive number (0..)
* @retval DSTATUS: Operation status
*/
DSTATUS disk_status (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
DSTATUS stat;
stat = disk.drv[pdrv]->disk_status(disk.lun[pdrv]);
return stat;
}
/**
* @brief Initializes a Drive
* @param pdrv: Physical drive number (0..)
* @retval DSTATUS: Operation status
*/
DSTATUS disk_initialize (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
DSTATUS stat = RES_OK;
if(disk.is_initialized[pdrv] == 0)
{
disk.is_initialized[pdrv] = 1;
stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]);
}
return stat;
}
/**
* @brief Reads Sector(s)
* @param pdrv: Physical drive number (0..)
* @param *buff: Data buffer to store read data
* @param sector: Sector address (LBA)
* @param count: Number of sectors to read (1..128)
* @retval DRESULT: Operation result
*/
DRESULT disk_read (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
BYTE *buff, /* Data buffer to store read data */
DWORD sector, /* Sector address in LBA */
UINT count /* Number of sectors to read */
)
{
DRESULT res;
res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count);
return res;
}
/**
* @brief Writes Sector(s)
* @param pdrv: Physical drive number (0..)
* @param *buff: Data to be written
* @param sector: Sector address (LBA)
* @param count: Number of sectors to write (1..128)
* @retval DRESULT: Operation result
*/
#if _USE_WRITE == 1
DRESULT disk_write (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
const BYTE *buff, /* Data to be written */
DWORD sector, /* Sector address in LBA */
UINT count /* Number of sectors to write */
)
{
DRESULT res;
res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count);
return res;
}
#endif /* _USE_WRITE == 1 */
/**
* @brief I/O control operation
* @param pdrv: Physical drive number (0..)
* @param cmd: Control code
* @param *buff: Buffer to send/receive control data
* @retval DRESULT: Operation result
*/
#if _USE_IOCTL == 1
DRESULT disk_ioctl (
BYTE pdrv, /* Physical drive nmuber (0..) */
BYTE cmd, /* Control code */
void *buff /* Buffer to send/receive control data */
)
{
DRESULT res;
res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff);
return res;
}
#endif /* _USE_IOCTL == 1 */
/**
* @brief Gets Time from RTC
* @param None
* @retval Time in DWORD
*/
__weak DWORD get_fattime (void)
{
return 0;
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*-----------------------------------------------------------------------/
/ Low level disk interface modlue include file (C)ChaN, 2014 /
/-----------------------------------------------------------------------*/
#ifndef _DISKIO_DEFINED
#define _DISKIO_DEFINED
#ifdef __cplusplus
extern "C" {
#endif
#define _USE_WRITE 1 /* 1: Enable disk_write function */
#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */
#include "integer.h"
/* Status of Disk Functions */
typedef BYTE DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
} DRESULT;
/*---------------------------------------*/
/* Prototypes for disk control functions */
DSTATUS disk_initialize (BYTE pdrv);
DSTATUS disk_status (BYTE pdrv);
DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
DWORD get_fattime (void);
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01 /* Drive not initialized */
#define STA_NODISK 0x02 /* No medium in the drive */
#define STA_PROTECT 0x04 /* Write protected */
/* Command code for disk_ioctrl fucntion */
/* Generic command (Used by FatFs) */
#define CTRL_SYNC 0 /* Complete pending write process (needed at _FS_READONLY == 0) */
#define GET_SECTOR_COUNT 1 /* Get media size (needed at _USE_MKFS == 1) */
#define GET_SECTOR_SIZE 2 /* Get sector size (needed at _MAX_SS != _MIN_SS) */
#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at _USE_MKFS == 1) */
#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
/* Generic command (Not used by FatFs) */
#define CTRL_POWER 5 /* Get/Set power status */
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
#define CTRL_EJECT 7 /* Eject media */
#define CTRL_FORMAT 8 /* Create physical format on the media */
/* MMC/SDC specific ioctl command */
#define MMC_GET_TYPE 10 /* Get card type */
#define MMC_GET_CSD 11 /* Get CSD */
#define MMC_GET_CID 12 /* Get CID */
#define MMC_GET_OCR 13 /* Get OCR */
#define MMC_GET_SDSTAT 14 /* Get SD status */
/* ATA/CF specific ioctl command */
#define ATA_GET_REV 20 /* Get F/W revision */
#define ATA_GET_MODEL 21 /* Get model name */
#define ATA_GET_SN 22 /* Get serial number */
#ifdef __cplusplus
}
#endif
#endif

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/*---------------------------------------------------------------------------/
/ FatFs - FAT file system module include R0.11 (C)ChaN, 2015
/----------------------------------------------------------------------------/
/ FatFs module is a free software that opened under license policy of
/ following conditions.
/
/ Copyright (C) 2015, ChaN, all right reserved.
/
/ 1. Redistributions of source code must retain the above copyright notice,
/ this condition and the following disclaimer.
/
/ This software is provided by the copyright holder and contributors "AS IS"
/ and any warranties related to this software are DISCLAIMED.
/ The copyright owner or contributors be NOT LIABLE for any damages caused
/ by use of this software.
/---------------------------------------------------------------------------*/
#ifndef _FATFS
#define _FATFS 32020 /* Revision ID */
#ifdef __cplusplus
extern "C" {
#endif
#include "integer.h" /* Basic integer types */
#include "ffconf.h" /* FatFs configuration options */
#if _FATFS != _FFCONF
#error Wrong configuration file (ffconf.h).
#endif
/* Definitions of volume management */
#if _MULTI_PARTITION /* Multiple partition configuration */
typedef struct {
BYTE pd; /* Physical drive number */
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
} PARTITION;
extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */
#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */
#else /* Single partition configuration */
#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */
#define LD2PT(vol) 0 /* Find first valid partition or in SFD */
#endif
/* Type of path name strings on FatFs API */
#if _LFN_UNICODE /* Unicode string */
#if !_USE_LFN
#error _LFN_UNICODE must be 0 at non-LFN cfg.
#endif
#ifndef _INC_TCHAR
typedef WCHAR TCHAR;
#define _T(x) L ## x
#define _TEXT(x) L ## x
#endif
#else /* ANSI/OEM string */
#ifndef _INC_TCHAR
typedef char TCHAR;
#define _T(x) x
#define _TEXT(x) x
#endif
#endif
/* File system object structure (FATFS) */
typedef struct {
union{
UINT d32[_MAX_SS/4]; /* Force 32bits alignement */
BYTE d8[_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
}win;
BYTE fs_type; /* FAT sub-type (0:Not mounted) */
BYTE drv; /* Physical drive number */
BYTE csize; /* Sectors per cluster (1,2,4...128) */
BYTE n_fats; /* Number of FAT copies (1 or 2) */
BYTE wflag; /* win[] flag (b0:dirty) */
BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
WORD id; /* File system mount ID */
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
#if _MAX_SS != _MIN_SS
WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */
#endif
#if _FS_REENTRANT
_SYNC_t sobj; /* Identifier of sync object */
#endif
#if !_FS_READONLY
DWORD last_clust; /* Last allocated cluster */
DWORD free_clust; /* Number of free clusters */
#endif
#if _FS_RPATH
DWORD cdir; /* Current directory start cluster (0:root) */
#endif
DWORD n_fatent; /* Number of FAT entries, = number of clusters + 2 */
DWORD fsize; /* Sectors per FAT */
DWORD volbase; /* Volume start sector */
DWORD fatbase; /* FAT start sector */
DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */
DWORD database; /* Data start sector */
DWORD winsect; /* Current sector appearing in the win[] */
} FATFS;
/* File object structure (FIL) */
typedef struct {
#if !_FS_TINY
union{
UINT d32[_MAX_SS/4]; /* Force 32bits alignement */
BYTE d8[_MAX_SS]; /* File data read/write buffer */
}buf;
#endif
FATFS* fs; /* Pointer to the related file system object (**do not change order**) */
WORD id; /* Owner file system mount ID (**do not change order**) */
BYTE flag; /* Status flags */
BYTE err; /* Abort flag (error code) */
DWORD fptr; /* File read/write pointer (Zeroed on file open) */
DWORD fsize; /* File size */
DWORD sclust; /* File start cluster (0:no cluster chain, always 0 when fsize is 0) */
DWORD clust; /* Current cluster of fpter (not valid when fprt is 0) */
DWORD dsect; /* Sector number appearing in buf[] (0:invalid) */
#if !_FS_READONLY
DWORD dir_sect; /* Sector number containing the directory entry */
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] */
#endif
#if _USE_FASTSEEK
DWORD* cltbl; /* Pointer to the cluster link map table (Nulled on file open) */
#endif
#if _FS_LOCK
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
#endif
} FIL;
/* Directory object structure (DIR) */
typedef struct {
#if !_FS_TINY
union{
UINT d32[_MAX_SS/4]; /* Force 32bits alignement */
BYTE d8[_MAX_SS]; /* File data read/write buffer */
}buf;
#endif
FATFS* fs; /* Pointer to the owner file system object (**do not change order**) */
WORD id; /* Owner file system mount ID (**do not change order**) */
WORD index; /* Current read/write index number */
DWORD sclust; /* Table start cluster (0:Root dir) */
DWORD clust; /* Current cluster */
DWORD sect; /* Current sector */
BYTE* dir; /* Pointer to the current SFN entry in the win[] */
BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
#if _FS_LOCK
UINT lockid; /* File lock ID (index of file semaphore table Files[]) */
#endif
#if _USE_LFN
WCHAR* lfn; /* Pointer to the LFN working buffer */
WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
#endif
#if _USE_FIND
const TCHAR* pat; /* Pointer to the name matching pattern */
#endif
} DIR;
/* File information structure (FILINFO) */
typedef struct {
DWORD fsize; /* File size */
WORD fdate; /* Last modified date */
WORD ftime; /* Last modified time */
BYTE fattrib; /* Attribute */
TCHAR fname[13]; /* Short file name (8.3 format) */
#if _USE_LFN
TCHAR* lfname; /* Pointer to the LFN buffer */
UINT lfsize; /* Size of LFN buffer in TCHAR */
#endif
} FILINFO;
/* File function return code (FRESULT) */
typedef enum {
FR_OK = 0, /* (0) Succeeded */
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
FR_INT_ERR, /* (2) Assertion failed */
FR_NOT_READY, /* (3) The physical drive cannot work */
FR_NO_FILE, /* (4) Could not find the file */
FR_NO_PATH, /* (5) Could not find the path */
FR_INVALID_NAME, /* (6) The path name format is invalid */
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
FR_EXIST, /* (8) Access denied due to prohibited access */
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
FR_NOT_ENABLED, /* (12) The volume has no work area */
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
} FRESULT;
/*--------------------------------------------------------------*/
/* FatFs module application interface */
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
FRESULT f_close (FIL* fp); /* Close an open file object */
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from a file */
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to a file */
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
FRESULT f_lseek (FIL* fp, DWORD ofs); /* Move file pointer of a file object */
FRESULT f_truncate (FIL* fp); /* Truncate file */
FRESULT f_sync (FIL* fp); /* Flush cached data of a writing file */
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
FRESULT f_closedir (DIR* dp); /* Close an open directory */
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of the file/dir */
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change times-tamp of the file/dir */
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
FRESULT f_mkfs (const TCHAR* path, BYTE sfd, UINT au); /* Create a file system on the volume */
FRESULT f_fdisk (BYTE pdrv, const DWORD szt[], void* work); /* Divide a physical drive into some partitions */
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
#define f_eof(fp) ((int)((fp)->fptr == (fp)->fsize))
#define f_error(fp) ((fp)->err)
#define f_tell(fp) ((fp)->fptr)
#define f_size(fp) ((fp)->fsize)
#define f_rewind(fp) f_lseek((fp), 0)
#define f_rewinddir(dp) f_readdir((dp), 0)
#ifndef EOF
#define EOF (-1)
#endif
/*--------------------------------------------------------------*/
/* Additional user defined functions */
/* RTC function */
#if !_FS_READONLY && !_FS_NORTC
DWORD get_fattime (void);
#endif
/* Unicode support functions */
#if _USE_LFN /* Unicode - OEM code conversion */
WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */
WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */
#if _USE_LFN == 3 /* Memory functions */
void* ff_memalloc (UINT msize); /* Allocate memory block */
void ff_memfree (void* mblock); /* Free memory block */
#endif
#endif
/* Sync functions */
#if _FS_REENTRANT
int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */
int ff_req_grant (_SYNC_t sobj); /* Lock sync object */
void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */
int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */
#endif
/*--------------------------------------------------------------*/
/* Flags and offset address */
/* File access control and file status flags (FIL.flag) */
#define FA_READ 0x01
#define FA_OPEN_EXISTING 0x00
#if !_FS_READONLY
#define FA_WRITE 0x02
#define FA_CREATE_NEW 0x04
#define FA_CREATE_ALWAYS 0x08
#define FA_OPEN_ALWAYS 0x10
#define FA__WRITTEN 0x20
#define FA__DIRTY 0x40
#endif
/* FAT sub type (FATFS.fs_type) */
#define FS_FAT12 1
#define FS_FAT16 2
#define FS_FAT32 3
/* File attribute bits for directory entry */
#define AM_RDO 0x01 /* Read only */
#define AM_HID 0x02 /* Hidden */
#define AM_SYS 0x04 /* System */
#define AM_VOL 0x08 /* Volume label */
#define AM_LFN 0x0F /* LFN entry */
#define AM_DIR 0x10 /* Directory */
#define AM_ARC 0x20 /* Archive */
#define AM_MASK 0x3F /* Mask of defined bits */
/* Fast seek feature */
#define CREATE_LINKMAP 0xFFFFFFFF
/*--------------------------------*/
/* Multi-byte word access macros */
#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr))
#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr))
#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val)
#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
#else /* Use byte-by-byte access to the FAT structure */
#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
#endif
#ifdef __cplusplus
}
#endif
#endif /* _FATFS */

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/**
******************************************************************************
* @file ff_gen_drv.c
* @author MCD Application Team
* @version V1.3.0
* @date 08-May-2015
* @brief FatFs generic low level driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "ff_gen_drv.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
Disk_drvTypeDef disk = {{0},{0},{0},0};
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief Links a compatible diskio driver/lun id and increments the number of active
* linked drivers.
* @note The number of linked drivers (volumes) is up to 10 due to FatFs limits.
* @param drv: pointer to the disk IO Driver structure
* @param path: pointer to the logical drive path
* @param lun : only used for USB Key Disk to add multi-lun management
else the paramter must be equal to 0
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_LinkDriverEx(Diskio_drvTypeDef *drv, char *path, uint8_t lun)
{
uint8_t ret = 1;
uint8_t DiskNum = 0;
if(disk.nbr <= _VOLUMES)
{
disk.is_initialized[disk.nbr] = 0;
disk.drv[disk.nbr] = drv;
disk.lun[disk.nbr] = lun;
DiskNum = disk.nbr++;
path[0] = DiskNum + '0';
path[1] = ':';
path[2] = '/';
path[3] = 0;
ret = 0;
}
return ret;
}
/**
* @brief Links a compatible diskio driver and increments the number of active
* linked drivers.
* @note The number of linked drivers (volumes) is up to 10 due to FatFs limits
* @param drv: pointer to the disk IO Driver structure
* @param path: pointer to the logical drive path
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_LinkDriver(Diskio_drvTypeDef *drv, char *path)
{
return FATFS_LinkDriverEx(drv, path, 0);
}
/**
* @brief Unlinks a diskio driver and decrements the number of active linked
* drivers.
* @param path: pointer to the logical drive path
* @param lun : not used
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_UnLinkDriverEx(char *path, uint8_t lun)
{
uint8_t DiskNum = 0;
uint8_t ret = 1;
if(disk.nbr >= 1)
{
DiskNum = path[0] - '0';
if(disk.drv[DiskNum] != 0)
{
disk.drv[DiskNum] = 0;
disk.lun[DiskNum] = 0;
disk.nbr--;
ret = 0;
}
}
return ret;
}
/**
* @brief Unlinks a diskio driver and decrements the number of active linked
* drivers.
* @param path: pointer to the logical drive path
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_UnLinkDriver(char *path)
{
return FATFS_UnLinkDriverEx(path, 0);
}
/**
* @brief Gets number of linked drivers to the FatFs module.
* @param None
* @retval Number of attached drivers.
*/
uint8_t FATFS_GetAttachedDriversNbr(void)
{
return disk.nbr;
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file ff_gen_drv.h
* @author MCD Application Team
* @version V1.3.0
* @date 08-May-2015
* @brief Header for ff_gen_drv.c module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __FF_GEN_DRV_H
#define __FF_GEN_DRV_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "diskio.h"
#include "ff.h"
/* Exported types ------------------------------------------------------------*/
/**
* @brief Disk IO Driver structure definition
*/
typedef struct
{
DSTATUS (*disk_initialize) (BYTE); /*!< Initialize Disk Drive */
DSTATUS (*disk_status) (BYTE); /*!< Get Disk Status */
DRESULT (*disk_read) (BYTE, BYTE*, DWORD, UINT); /*!< Read Sector(s) */
#if _USE_WRITE == 1
DRESULT (*disk_write) (BYTE, const BYTE*, DWORD, UINT); /*!< Write Sector(s) when _USE_WRITE = 0 */
#endif /* _USE_WRITE == 1 */
#if _USE_IOCTL == 1
DRESULT (*disk_ioctl) (BYTE, BYTE, void*); /*!< I/O control operation when _USE_IOCTL = 1 */
#endif /* _USE_IOCTL == 1 */
}Diskio_drvTypeDef;
/**
* @brief Global Disk IO Drivers structure definition
*/
typedef struct
{
uint8_t is_initialized[_VOLUMES];
Diskio_drvTypeDef *drv[_VOLUMES];
uint8_t lun[_VOLUMES];
__IO uint8_t nbr;
}Disk_drvTypeDef;
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
uint8_t FATFS_LinkDriverEx(Diskio_drvTypeDef *drv, char *path, uint8_t lun);
uint8_t FATFS_LinkDriver(Diskio_drvTypeDef *drv, char *path);
uint8_t FATFS_UnLinkDriver(char *path);
uint8_t FATFS_LinkDriverEx(Diskio_drvTypeDef *drv, char *path, BYTE lun);
uint8_t FATFS_UnLinkDriverEx(char *path, BYTE lun);
uint8_t FATFS_GetAttachedDriversNbr(void);
#ifdef __cplusplus
}
#endif
#endif /* __FF_GEN_DRV_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*-------------------------------------------*/
/* Integer type definitions for FatFs module */
/*-------------------------------------------*/
#ifndef _FF_INTEGER
#define _FF_INTEGER
#ifdef _WIN32 /* FatFs development platform */
#include <windows.h>
#include <tchar.h>
#else /* Embedded platform */
/* This type MUST be 8 bit */
typedef unsigned char BYTE;
/* These types MUST be 16 bit */
typedef short SHORT;
typedef unsigned short WORD;
typedef unsigned short WCHAR;
/* These types MUST be 16 bit or 32 bit */
typedef int INT;
typedef unsigned int UINT;
/* These types MUST be 32 bit */
typedef long LONG;
typedef unsigned long DWORD;
#endif
#endif

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/*------------------------------------------------------------------------*/
/* Sample code of OS dependent controls for FatFs */
/* (C)ChaN, 2014 */
/*------------------------------------------------------------------------*/
#include <stdlib.h> /* ANSI memory controls */
#include "../ff.h"
#if _FS_REENTRANT
/*-----------------------------------------------------------------------
Create a Synchronization Object
------------------------------------------------------------------------
This function is called in f_mount function to create a new
synchronization object, such as semaphore and mutex. When a zero is
returned, the f_mount function fails with FR_INT_ERR.
*/
int ff_cre_syncobj ( /* TRUE:Function succeeded, FALSE:Could not create due to any error */
BYTE vol, /* Corresponding logical drive being processed */
_SYNC_t *sobj /* Pointer to return the created sync object */
)
{
int ret;
osSemaphoreDef(SEM);
*sobj = osSemaphoreCreate(osSemaphore(SEM), 1);
ret = (*sobj != NULL);
return ret;
}
/*------------------------------------------------------------------------*/
/* Delete a Synchronization Object */
/*------------------------------------------------------------------------*/
/* This function is called in f_mount function to delete a synchronization
/ object that created with ff_cre_syncobj function. When a zero is
/ returned, the f_mount function fails with FR_INT_ERR.
*/
int ff_del_syncobj ( /* TRUE:Function succeeded, FALSE:Could not delete due to any error */
_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
)
{
osSemaphoreDelete (sobj);
return 1;
}
/*------------------------------------------------------------------------*/
/* Request Grant to Access the Volume */
/*------------------------------------------------------------------------*/
/* This function is called on entering file functions to lock the volume.
/ When a zero is returned, the file function fails with FR_TIMEOUT.
*/
int ff_req_grant ( /* TRUE:Got a grant to access the volume, FALSE:Could not get a grant */
_SYNC_t sobj /* Sync object to wait */
)
{
int ret = 0;
if(osSemaphoreWait(sobj, _FS_TIMEOUT) == osOK)
{
ret = 1;
}
return ret;
}
/*------------------------------------------------------------------------*/
/* Release Grant to Access the Volume */
/*------------------------------------------------------------------------*/
/* This function is called on leaving file functions to unlock the volume.
*/
void ff_rel_grant (
_SYNC_t sobj /* Sync object to be signaled */
)
{
osSemaphoreRelease(sobj);
}
#endif
#if _USE_LFN == 3 /* LFN with a working buffer on the heap */
/*------------------------------------------------------------------------*/
/* Allocate a memory block */
/*------------------------------------------------------------------------*/
/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE.
*/
void* ff_memalloc ( /* Returns pointer to the allocated memory block */
UINT msize /* Number of bytes to allocate */
)
{
return malloc(msize); /* Allocate a new memory block with POSIX API */
}
/*------------------------------------------------------------------------*/
/* Free a memory block */
/*------------------------------------------------------------------------*/
void ff_memfree (
void* mblock /* Pointer to the memory block to free */
)
{
free(mblock); /* Discard the memory block with POSIX API */
}
#endif

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#include "action_process.h"
#include "sw_timer.h"
#include "gpio_switch.h"
#include "gpio_state_led.h"
#include "gpio_sensor.h"
#include "eeprom.h"
#include "buzzer.h"
#include "segment.h"
#include "rtc_process.h"
#include "save_file.h"
typedef struct _control_info
{
bool isActionRun;
uint32_t Co2_MaxValue;
uint32_t Co2_MinValue;
}CONTROL_INFO;
static CONTROL_INFO Control_Info;
static void Action_Process(void);
static void Action_PowerKey_Push(void);
static void Action_PowerKey_LongPush(void);
static void Action_Sensor_Read_Process(void);
void Action_Initialization(void)
{
SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1, Action_Process);
}
static void Action_Process(void)
{
}

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/** \file action_process.h */
#if !defined(ACTION_PROCESS_H__793AF4F0_9732_4285_BF6C_F708ACCE969B__INCLUDED_)
#define ACTION_PROCESS_H__793AF4F0_9732_4285_BF6C_F708ACCE969B__INCLUDED_
#include "define.h"
#include "board_config.h"
void Action_Initialization(void);
#endif

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/** \file board_config.h */
#if !defined(BOARD_CONFIG_H__8269C71E_6C81_429B_B9F6_2CA6AC082DCC__INCLUDED_)
#define BOARD_CONFIG_H__8269C71E_6C81_429B_B9F6_2CA6AC082DCC__INCLUDED_
#include "define.h"
#define FW_VERSION_MAJOR 0
#define FW_VERSION_MINOR 1
//////////////////////////////////////////////////////////////
#define FALSE 0
#define TRUE (!FALSE)
//////////////////////////////////////////////////////////////
// dbg_print Config
//////////////////////////////////////////////////////////////
#define DEBUG_PRINT
#if defined(DEBUG_PRINT)
#define dbg_printf(fmt,args...) printf( fmt, ## args )
#if 0
#define SW_TIMER_DBG_PRINT
#endif
#else
#define dbg_printf(fmt,args...)
#endif
#if 0
//////////////////////////////////////////////////////////////
// MODBUS Config
//////////////////////////////////////////////////////////////
#define MODBUS_BAUDRATE 9600
#define MODBUS_DATA_BIT UARTn_DATA_BIT_8
#define MODBUS_STOP_BIT UARTn_STOP_BIT_1
#define MODBUS_PARITY_BIT UARTn_PARITY_BIT_EVEN
#define MODBUS_RX_TIMEOUT 100
#define MODBUS_DEFAULT_ADDRESS 0x01
#define MODBUS_START_REG_ADDRESS 0x0000
#define MODBUS_GET_REG_COUNT 0x0029
#define MODBUS_POLLING_INTERVAL_TIME 1000 //??? ?? ??
#define MODBUS_DATA_INDEX_OUTPUT_COUNT 100 //??? ??? ?? ??? ??
#define MODBUS_DATA_UPDATE_CHECK_INTERVAL_TIME (MODBUS_POLLING_INTERVAL_TIME/2)
#define MODBUS_TX_ERROR_COUNT 10 //?? ?? ?? ?? ???? ??, ??? ???
//////////////////////////////////////////////////////////////
// DATA OUT Uart Config
//////////////////////////////////////////////////////////////
#define DATAOUT_BAUDRATE 115200
#define DATAOUT_DATA_BIT USART1n_DATA_BIT_8
#define DATAOUT_STOP_BIT USART1n_STOP_BIT_1
#define DATAOUT_PARITY_BIT USART1n_PARITY_BIT_NONE
#define DATAOUT_INTERFACE_INIT Usart11_Initialization
#define DATAOUT_TRANSMIT Usart11_Transmit
#endif
#endif

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#include "buzzer.h"
#include "sw_timer.h"
static bool isBuzzerOn;
static uint32_t BuzzerStartTick;
static uint32_t BuzzerOnTimeCount;
static void Buzzer_Output_Process(void);
void Buzzer_Initialization(void)
{
HAL_GPIO_ConfigOutput(GPIO_BUZZER_PORT, GPIO_BUZZER_PIN_NUM, PUSH_PULL_OUTPUT);
HAL_GPIO_ConfigPullup(GPIO_BUZZER_PORT, GPIO_BUZZER_PIN_NUM, PUPDx_EnablePU);
SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1, Buzzer_Output_Process);
}
void Buzzer_On(uint32_t BuzzerOnTime)
{
isBuzzerOn = true;
BuzzerStartTick = millis();
BuzzerOnTimeCount = BuzzerOnTime;
}
static void Buzzer_Output_Process(void)
{
if(isBuzzerOn == true)
{
if((millis() - BuzzerStartTick) <= BuzzerOnTimeCount)
{
GPIO_BUZZER_ON;
}
else
{
isBuzzerOn = false;
GPIO_BUZZER_OFF;
}
}
else
{
GPIO_BUZZER_OFF;;
}
}

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/** \file buzzer.h */
#if !defined(BUZZER_H__4676A357_207F_4D31_A901_C2B23A663560__INCLUDED_)
#define BUZZER_H__4676A357_207F_4D31_A901_C2B23A663560__INCLUDED_
#include "define.h"
#include "board_config.h"
#define GPIO_BUZZER_PORT (Pn_Type*)PD
#define GPIO_BUZZER_PIN_NUM 7
#define GPIO_BUZZER_ON HAL_GPIO_SetPin(GPIO_BUZZER_PORT, _BIT(GPIO_BUZZER_PIN_NUM))
#define GPIO_BUZZER_OFF HAL_GPIO_ClearPin(GPIO_BUZZER_PORT, _BIT(GPIO_BUZZER_PIN_NUM))
#define GPIO_BUZZER_T HAL_GPIO_TogglePin(GPIO_BUZZER_PORT, _BIT(GPIO_BUZZER_PIN_NUM))
void Buzzer_Initialization(void);
void Buzzer_On(uint32_t BuzzerOnTime);
#endif

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#include "dbg_printf.h"
#include "uart1.h"
/*-------------------------------------------------------------------------*//**
* @brief Puts a character to file
* @param[in] ch
* Character to put
* @param[in] f
* Pointer to file
* @return character
* @note if you use IAR EWARM, select Full as Options/General Options/Library Configuration/Library.
*//*-------------------------------------------------------------------------*/
int fputc( int ch, FILE* f )
{
Uart1_Transmit(ch);
return( ch );
}

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/** \file dbg_printf.h */
#if !defined(DBG_PRINTF_H__3735CB34_D9A0_43AC_B22D_005B5B83B450__INCLUDED_)
#define DBG_PRINTF_H__3735CB34_D9A0_43AC_B22D_005B5B83B450__INCLUDED_
#include "define.h"
#include "board_config.h"
#endif

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/** \file define.h */
#if !defined(DEFINE_H__8F668E66_FF75_45CB_850C_2513B033D139__INCLUDED_)
#define DEFINE_H__8F668E66_FF75_45CB_850C_2513B033D139__INCLUDED_
#include <stdio.h>
#include <stdint.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>
#include <math.h>
#include "A31G12x.h"
#include "A31G12x_hal_aa_types.h"
#include "A31G12x_hal_adc.h"
#include "A31G12x_hal_crc.h"
#include "A31G12x_hal_debug_frmwrk.h"
#include "A31G12x_hal_fmc.h"
#include "A31G12x_hal_i2cn.h"
#include "A31G12x_hal_intc.h"
#include "A31G12x_hal_lcd.h"
#include "A31G12x_hal_libcfg.h"
#include "A31G12x_hal_pcu.h"
#include "A31G12x_hal_pwr.h"
#include "A31G12x_hal_scu.h"
#include "A31G12x_hal_sculv.h"
#include "A31G12x_hal_timer1n.h"
#include "A31G12x_hal_timer2n.h"
#include "A31G12x_hal_timer3n.h"
#include "A31G12x_hal_uartn.h"
#include "A31G12x_hal_usart1n.h"
#include "A31G12x_hal_wdt.h"
#include "A31G12x_hal_wt.h"
#include "A31G12x_hal_wtidky.h"
#include "A31G12x_SystemClock.h"
#include "systick_timer.h"
#define SETBIT(ADDRESS,BIT) (ADDRESS |= (1<<BIT))
#define CLEARBIT(ADDRESS,BIT) (ADDRESS &= ~(1<<BIT))
#define TESTBIT(ADDRESS,BIT) ((ADDRESS & (1<<BIT)) ? 1 : 0)
#define TOGGLEBIT(ADDRESS, BIT) (ADDRESS ^= (1<<BIT))
#define VERSION_MAJOR 0 // max 9
#define VERSION_MINOR 0 // max 9
#define VERSION_PATCH 1 // max 99
#define SEGMENT_CHECK_WAIT_TIME 300 //
#define SEGMENT_VERSION_WAIT_TIME 1000
#define DEFAULT_KEY_PUSH_COUNT 50
#define DEFAULT_LONGKEY_PUSH_COUNT 1000
#define DUST_SENSOR_POWER_ON_WAIT_TIME_COUNT 100
#define DUST_SENSOR_POWER_OFF_WAIT_TIME_COUNT 100
#define DUST_SENSOR_PM4P0_VIEW_TIME 5 // sec
#define DUST_SENSOR_PM1P0_VIEW_TIME 5 // sec
#define DUST_SENSOR_MODE_1_TIME 1000
#define DUST_SENSOR_MODE_2_TIME 2000
#define DUST_SENSOR_MODE_3_TIME 3000
#define DUST_SENSOR_MODE_4_TIME 4000
#define DUST_SENSOR_MODE_5_TIME 5000
#define DUST_SENSOR_PM40_SELECT_1 SEGMENT_OUTPUT_F3C1
#define DUST_SENSOR_PM40_SELECT_2 SEGMENT_OUTPUT_F3C2
#define SEGMENT_TOGGLE_TIME 250
#endif

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Project/Application/driver_ds3231.c
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/**
* Copyright (c) 2015 - present LibDriver All rights reserved
*
* The MIT License (MIT)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* @file driver_ds3231.h
* @brief driver ds3231 header file
* @version 2.0.0
* @author Shifeng Li
* @date 2021-03-15
*
* <h3>history</h3>
* <table>
* <tr><th>Date <th>Version <th>Author <th>Description
* <tr><td>2021/03/15 <td>2.0 <td>Shifeng Li <td>format the code
* <tr><td>2020/11/30 <td>1.0 <td>Shifeng Li <td>first upload
* </table>
*/
#ifndef DRIVER_DS3231_H
#define DRIVER_DS3231_H
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#ifdef __cplusplus
extern "C"{
#endif
/**
* @defgroup ds3231_driver ds3231 driver function
* @brief ds3231 driver modules
* @{
*/
/**
* @addtogroup ds3231_base_driver
* @{
*/
/**
* @brief ds3231 bool enumeration definition
*/
typedef enum
{
DS3231_BOOL_FALSE = 0x00, /**< disable function */
DS3231_BOOL_TRUE = 0x01, /**< enable function */
} ds3231_bool_t;
/**
* @brief ds3231 alarm enumeration definition
*/
typedef enum
{
DS3231_ALARM_1 = 0x00, /**< alarm 1 */
DS3231_ALARM_2 = 0x01, /**< alarm 2 */
} ds3231_alarm_t;
/**
* @brief ds3231 am pm enumeration definition
*/
typedef enum
{
DS3231_AM = 0x00, /**< am */
DS3231_PM = 0x01, /**< pm */
} ds3231_am_pm_t;
/**
* @brief ds3231 pin enumeration definition
*/
typedef enum
{
DS3231_PIN_SQUARE_WAVE = 0x00, /**< square wave pin */
DS3231_PIN_INTERRUPT = 0x01, /**< interrupt pin */
} ds3231_pin_t;
/**
* @brief ds3231 format enumeration definition
*/
typedef enum
{
DS3231_FORMAT_12H = 0x01, /**< 12h format */
DS3231_FORMAT_24H = 0x00, /**< 24h format */
} ds3231_format_t;
/**
* @brief ds3231 alarm1 enumeration definition
*/
typedef enum
{
DS3231_STATUS_ALARM_2 = (1 << 1), /**< alarm 2 status */
DS3231_STATUS_ALARM_1 = (1 << 0), /**< alarm 1 status */
} ds3231_status_t;
/**
* @}
*/
/**
* @addtogroup ds3231_alarm_driver
* @{
*/
/**
* @brief ds3231 alarm1 enumeration definition
*/
typedef enum
{
DS3231_ALARM1_MODE_ONCE_A_SECOND = 0x0F, /**< interrupt once a second */
DS3231_ALARM1_MODE_SECOND_MATCH = 0x0E, /**< interrupt second match */
DS3231_ALARM1_MODE_MINUTE_SECOND_MATCH = 0x0C, /**< interrupt minute second match */
DS3231_ALARM1_MODE_HOUR_MINUTE_SECOND_MATCH = 0x08, /**< interrupt hour minute second match */
DS3231_ALARM1_MODE_DATE_HOUR_MINUTE_SECOND_MATCH = 0x00, /**< interrupt date hour minute second match */
DS3231_ALARM1_MODE_WEEK_HOUR_MINUTE_SECOND_MATCH = 0x10, /**< interrupt week hour minute second match */
} ds3231_alarm1_mode_t;
/**
* @brief ds3231 alarm2 enumeration definition
*/
typedef enum
{
DS3231_ALARM2_MODE_ONCE_A_MINUTE = 0x07, /**< interrupt once a minute */
DS3231_ALARM2_MODE_MINUTE_MATCH = 0x06, /**< interrupt minute match */
DS3231_ALARM2_MODE_HOUR_MINUTE_MATCH = 0x04, /**< interrupt hour minute match */
DS3231_ALARM2_MODE_DATE_HOUR_MINUTE_MATCH = 0x00, /**< interrupt data hour minute match */
DS3231_ALARM2_MODE_WEEK_HOUR_MINUTE_MATCH = 0x10, /**< interrupt week hour minute match */
} ds3231_alarm2_mode_t;
/**
* @}
*/
/**
* @addtogroup ds3231_base_driver
* @{
*/
/**
* @brief ds3231 time structure definition
*/
typedef struct ds3231_time_s
{
uint16_t year; /**< year */
uint8_t month; /**< month */
uint8_t week; /**< week */
uint8_t date; /**< date */
uint8_t hour; /**< hour */
uint8_t minute; /**< minute */
uint8_t second; /**< second */
ds3231_format_t format; /**< data format */
ds3231_am_pm_t am_pm; /**< am pm */
} ds3231_time_t;
/**
* @brief ds3231 handle structure definition
*/
typedef struct ds3231_handle_s
{
uint8_t (*iic_init)(void); /**< point to an iic_init function address */
uint8_t (*iic_deinit)(void); /**< point to an iic_deinit function address */
uint8_t (*iic_write)(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len); /**< point to an iic_write function address */
uint8_t (*iic_read)(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len); /**< point to an iic_read function address */
void (*debug_print)(const char *const fmt, ...); /**< point to a debug_print function address */
void (*receive_callback)(uint8_t type); /**< point to a receive_callback function address */
void (*delay_ms)(uint32_t ms); /**< point to a delay_ms function address */
uint8_t inited; /**< inited flag */
} ds3231_handle_t;
/**
* @brief ds3231 information structure definition
*/
typedef struct ds3231_info_s
{
char chip_name[32]; /**< chip name */
char manufacturer_name[32]; /**< manufacturer name */
char interface[8]; /**< chip interface name */
float supply_voltage_min_v; /**< chip min supply voltage */
float supply_voltage_max_v; /**< chip max supply voltage */
float max_current_ma; /**< chip max current */
float temperature_min; /**< chip min operating temperature */
float temperature_max; /**< chip max operating temperature */
uint32_t driver_version; /**< driver version */
} ds3231_info_t;
/**
* @}
*/
/**
* @defgroup ds3231_link_driver ds3231 link driver function
* @brief ds3231 link driver modules
* @ingroup ds3231_driver
* @{
*/
/**
* @brief initialize ds3231_handle_t structure
* @param[in] HANDLE points to a ds3231 handle structure
* @param[in] STRUCTURE is ds3231_handle_t
* @note none
*/
#define DRIVER_DS3231_LINK_INIT(HANDLE, STRUCTURE) memset(HANDLE, 0, sizeof(STRUCTURE))
/**
* @brief link iic_init function
* @param[in] HANDLE points to a ds3231 handle structure
* @param[in] FUC points to an iic_init function address
* @note none
*/
#define DRIVER_DS3231_LINK_IIC_INIT(HANDLE, FUC) (HANDLE)->iic_init = FUC
/**
* @brief link iic_deinit function
* @param[in] HANDLE points to a ds3231 handle structure
* @param[in] FUC points to an iic_deinit function address
* @note none
*/
#define DRIVER_DS3231_LINK_IIC_DEINIT(HANDLE, FUC) (HANDLE)->iic_deinit = FUC
/**
* @brief link iic_read function
* @param[in] HANDLE points to a ds3231 handle structure
* @param[in] FUC points to an iic_read function address
* @note none
*/
#define DRIVER_DS3231_LINK_IIC_READ(HANDLE, FUC) (HANDLE)->iic_read = FUC
/**
* @brief link iic_write function
* @param[in] HANDLE points to a ds3231 handle structure
* @param[in] FUC points to an iic_write function address
* @note none
*/
#define DRIVER_DS3231_LINK_IIC_WRITE(HANDLE, FUC) (HANDLE)->iic_write = FUC
/**
* @brief link delay_ms function
* @param[in] HANDLE points to a ds3231 handle structure
* @param[in] FUC points to a delay_ms function address
* @note none
*/
#define DRIVER_DS3231_LINK_DELAY_MS(HANDLE, FUC) (HANDLE)->delay_ms = FUC
/**
* @brief link debug_print function
* @param[in] HANDLE points to a ds3231 handle structure
* @param[in] FUC points to a debug_print function address
* @note none
*/
#define DRIVER_DS3231_LINK_DEBUG_PRINT(HANDLE, FUC) (HANDLE)->debug_print = FUC
/**
* @brief link receive_callback function
* @param[in] HANDLE points to a ds3231 handle structure
* @param[in] FUC points to a receive_callback function address
* @note none
*/
#define DRIVER_DS3231_LINK_RECEIVE_CALLBACK(HANDLE, FUC) (HANDLE)->receive_callback = FUC
/**
* @}
*/
/**
* @defgroup ds3231_base_driver ds3231 base driver function
* @brief ds3231 base driver modules
* @ingroup ds3231_driver
* @{
*/
/**
* @brief get chip's information
* @param[out] *info points to a ds3231 info structure
* @return status code
* - 0 success
* - 2 handle is NULL
* @note none
*/
uint8_t ds3231_info(ds3231_info_t *info);
/**
* @brief initialize the chip
* @param[in] *handle points to a ds3231 handle structure
* @return status code
* - 0 success
* - 1 iic initialization failed
* - 2 handle is NULL
* - 3 linked functions is NULL
* @note none
*/
uint8_t ds3231_init(ds3231_handle_t *handle);
/**
* @brief close the chip
* @param[in] *handle points to a ds3231 handle structure
* @return status code
* - 0 success
* - 1 iic deinit failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_deinit(ds3231_handle_t *handle);
/**
* @brief irq handler
* @param[in] *handle points to a ds3231 handle structure
* @return status code
* - 0 success
* - 1 run failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_irq_handler(ds3231_handle_t *handle);
/**
* @brief set the current time
* @param[in] *handle points to a ds3231 handle structure
* @param[in] *t points to a time structure
* @return status code
* - 0 success
* - 1 set time failed
* - 2 handle or time is NULL
* - 3 handle is not initialized
* - 4 time is invalid
* @note none
*/
uint8_t ds3231_set_time(ds3231_handle_t *handle, ds3231_time_t *t);
/**
* @brief get the current time
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *t points to a time structure
* @return status code
* - 0 success
* - 1 get time failed
* - 2 handle or time is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_time(ds3231_handle_t *handle, ds3231_time_t *t);
/**
* @brief enable or disable the oscillator
* @param[in] *handle points to a ds3231 handle structure
* @param[in] enable is a bool value
* @return status code
* - 0 success
* - 1 set oscillator failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_oscillator(ds3231_handle_t *handle, ds3231_bool_t enable);
/**
* @brief get the chip oscillator status
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *enable points to a bool value buffer
* @return status code
* - 0 success
* - 1 get oscillator failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_oscillator(ds3231_handle_t *handle, ds3231_bool_t *enable);
/**
* @brief get the chip status
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *status points to a chip status buffer
* @return status code
* - 0 success
* - 1 get status failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_status(ds3231_handle_t *handle, uint8_t *status);
/**
* @}
*/
/**
* @defgroup ds3231_advance_driver ds3231 advance driver function
* @brief ds3231 advance driver modules
* @ingroup ds3231_driver
* @{
*/
/**
* @brief set the chip pin function
* @param[in] *handle points to a ds3231 handle structure
* @param[in] pin is the pin's function
* @return status code
* - 0 success
* - 1 set pin failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_pin(ds3231_handle_t *handle, ds3231_pin_t pin);
/**
* @brief get the chip pin function
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *pin points to a pin's function buffer
* @return status code
* - 0 success
* - 1 get pin failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_pin(ds3231_handle_t *handle, ds3231_pin_t *pin);
/**
* @brief enable or disable the square wave output
* @param[in] *handle points to a ds3231 handle structure
* @param[in] enable is a bool value
* @return status code
* - 0 success
* - 1 set square wave failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_square_wave(ds3231_handle_t *handle, ds3231_bool_t enable);
/**
* @brief get the square wave output status
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *enable points to a bool value buffer
* @return status code
* - 0 success
* - 1 get square wave failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_square_wave(ds3231_handle_t *handle, ds3231_bool_t *enable);
/**
* @brief enable or disable the 32KHz output
* @param[in] *handle points to a ds3231 handle structure
* @param[in] enable is a bool value
* @return status code
* - 0 success
* - 1 set 32khz output failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_32khz_output(ds3231_handle_t *handle, ds3231_bool_t enable);
/**
* @brief get the 32KHz output status
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *enable points to a bool value buffer
* @return status code
* - 0 success
* - 1 get 32khz output failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_32khz_output(ds3231_handle_t *handle, ds3231_bool_t *enable);
/**
* @brief get the chip temperature
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *raw points to a raw temperature buffer
* @param[out] *s points to a converted temperature buffer
* @return status code
* - 0 success
* - 1 get temperature failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_temperature(ds3231_handle_t *handle, int16_t *raw, float *s);
/**
* @brief set the chip aging offset
* @param[in] *handle points to a ds3231 handle structure
* @param[in] offset is time aging offset
* @return status code
* - 0 success
* - 1 set aging offset failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_aging_offset(ds3231_handle_t *handle, int8_t offset);
/**
* @brief get the chip aging offset
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *offset points to a time aging offset buffer
* @return status code
* - 0 success
* - 1 get aging offset failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_aging_offset(ds3231_handle_t *handle, int8_t *offset);
/**
* @brief convert a aging offset value to a register raw data
* @param[in] *handle points to a ds3231 handle structure
* @param[in] offset is a converted aging offset value
* @param[out] *reg points to a register raw buffer
* @return status code
* - 0 success
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_aging_offset_convert_to_register(ds3231_handle_t *handle, float offset, int8_t *reg);
/**
* @brief convert a register raw data to a converted aging offset data
* @param[in] *handle points to a ds3231 handle structure
* @param[in] reg is the register raw data
* @param[out] *offset points to a converted aging offset buffer
* @return status code
* - 0 success
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_aging_offset_convert_to_data(ds3231_handle_t *handle, int8_t reg, float *offset);
/**
* @}
*/
/**
* @defgroup ds3231_alarm_driver ds3231 alarm driver function
* @brief ds3231 alarm driver modules
* @ingroup ds3231_driver
* @{
*/
/**
* @brief enable or disable the alarm interrupt
* @param[in] *handle points to a ds3231 handle structure
* @param[in] alarm is the alarm number
* @param[in] enable is a bool value
* @return status code
* - 0 success
* - 1 set alarm interrupt failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_alarm_interrupt(ds3231_handle_t *handle, ds3231_alarm_t alarm, ds3231_bool_t enable);
/**
* @brief get the alarm interrupt status
* @param[in] *handle points to a ds3231 handle structure
* @param[in] alarm is the alarm number
* @param[out] *enable points to a bool value buffer
* @return status code
* - 0 success
* - 1 get alarm interrupt failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_alarm_interrupt(ds3231_handle_t *handle, ds3231_alarm_t alarm, ds3231_bool_t *enable);
/**
* @brief set the alarm1 time
* @param[in] *handle points to a ds3231 handle structure
* @param[in] *t points to a time structure
* @param[in] mode is the alarm1 interrupt mode
* @return status code
* - 0 success
* - 1 set alarm1 failed
* - 2 handle or time is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_alarm1(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm1_mode_t mode);
/**
* @brief get the alarm1 time
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *t points to a time structure
* @param[out] *mode points to an alarm1 interrupt mode buffer
* @return status code
* - 0 success
* - 1 get alarm1 failed
* - 2 handle or time is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_alarm1(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm1_mode_t *mode);
/**
* @brief set the alarm2 time
* @param[in] *handle points to a ds3231 handle structure
* @param[in] *t points to a time structure
* @param[in] mode is the alarm2 interrupt mode
* @return status code
* - 0 success
* - 1 set alarm2 failed
* - 2 handle or time is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_alarm2(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm2_mode_t mode);
/**
* @brief get the alarm2 time
* @param[in] *handle points to a ds3231 handle structure
* @param[out] *t points to a time structure
* @param[out] *mode points to an alarm2 interrupt mode buffer
* @return status code
* - 0 success
* - 1 get alarm2 failed
* - 2 handle or time is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_alarm2(ds3231_handle_t *handle, ds3231_time_t *t, ds3231_alarm2_mode_t *mode);
/**
* @brief clear the alarm flag
* @param[in] *handle points to a ds3231 handle structure
* @param[in] alarm is the alarm number
* @return status code
* - 0 success
* - 1 alarm clear failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_alarm_clear(ds3231_handle_t *handle, ds3231_alarm_t alarm);
/**
* @}
*/
/**
* @defgroup ds3231_extern_driver ds3231 extern driver function
* @brief ds3231 extern driver modules
* @ingroup ds3231_driver
* @{
*/
/**
* @brief set the chip register
* @param[in] *handle points to a ds3231 handle structure
* @param[in] reg is the iic register address
* @param[in] *buf points to a data buffer
* @param[in] len is the data buffer length
* @return status code
* - 0 success
* - 1 write failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_set_reg(ds3231_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len);
/**
* @brief get the chip register
* @param[in] *handle points to a ds3231 handle structure
* @param[in] reg is the iic register address
* @param[out] *buf points to a data buffer
* @param[in] len is the data buffer length
* @return status code
* - 0 success
* - 1 read failed
* - 2 handle is NULL
* - 3 handle is not initialized
* @note none
*/
uint8_t ds3231_get_reg(ds3231_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
* Copyright (c) 2015 - present LibDriver All rights reserved
*
* The MIT License (MIT)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* @file driver_ds3231_basic.c
* @brief driver ds3231 basic source file
* @version 2.0.0
* @author Shifeng Li
* @date 2021-03-15
*
* <h3>history</h3>
* <table>
* <tr><th>Date <th>Version <th>Author <th>Description
* <tr><td>2021/03/15 <td>2.0 <td>Shifeng Li <td>format the code
* <tr><td>2020/11/30 <td>1.0 <td>Shifeng Li <td>first upload
* </table>
*/
#include "driver_ds3231_basic.h"
static ds3231_handle_t gs_handle; /**< ds3231 handle */
static int8_t gs_time_zone = 0; /**< local zone */
/**
* @brief basic example init
* @return status code
* - 0 success
* - 1 init failed
* @note none
*/
uint8_t ds3231_basic_init(void)
{
uint8_t res;
int8_t reg;
/* link functions */
DRIVER_DS3231_LINK_INIT(&gs_handle, ds3231_handle_t);
DRIVER_DS3231_LINK_IIC_INIT(&gs_handle, ds3231_interface_iic_init);
DRIVER_DS3231_LINK_IIC_DEINIT(&gs_handle, ds3231_interface_iic_deinit);
DRIVER_DS3231_LINK_IIC_READ(&gs_handle, ds3231_interface_iic_read);
DRIVER_DS3231_LINK_IIC_WRITE(&gs_handle, ds3231_interface_iic_write);
DRIVER_DS3231_LINK_DELAY_MS(&gs_handle, ds3231_interface_delay_ms);
DRIVER_DS3231_LINK_DEBUG_PRINT(&gs_handle, ds3231_interface_debug_print);
DRIVER_DS3231_LINK_RECEIVE_CALLBACK(&gs_handle, ds3231_interface_receive_callback);
/* init ds3231 */
res = ds3231_init(&gs_handle);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: init failed.\n");
return 1;
}
/* set oscillator */
res = ds3231_set_oscillator(&gs_handle, DS3231_BOOL_TRUE);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: set oscillator failed.\n");
(void)ds3231_deinit(&gs_handle);
return 1;
}
/* disable alarm1 */
res = ds3231_set_alarm_interrupt(&gs_handle, DS3231_ALARM_1, DS3231_BOOL_FALSE);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: set alarm1 interrupt failed.\n");
(void)ds3231_deinit(&gs_handle);
return 1;
}
/* disable alarm2 */
res = ds3231_set_alarm_interrupt(&gs_handle, DS3231_ALARM_2, DS3231_BOOL_FALSE);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: set alarm2 interrupt failed.\n");
(void)ds3231_deinit(&gs_handle);
return 1;
}
/* set square wave */
res = ds3231_set_pin(&gs_handle, DS3231_PIN_SQUARE_WAVE);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: set pin failed.\n");
(void)ds3231_deinit(&gs_handle);
return 1;
}
/* disable square wave */
res = ds3231_set_square_wave(&gs_handle, DS3231_BOOL_FALSE);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: set square wave failed.\n");
(void)ds3231_deinit(&gs_handle);
return 1;
}
/* disable 32khz output */
res = ds3231_set_32khz_output(&gs_handle, DS3231_BOOL_FALSE);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: set 32khz output failed.\n");
(void)ds3231_deinit(&gs_handle);
return 1;
}
/* convert to register */
res = ds3231_aging_offset_convert_to_register(&gs_handle, DS3231_BASIC_DEFAULT_AGING_OFFSET, (int8_t *)&reg);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: convert to register failed.\n");
(void)ds3231_deinit(&gs_handle);
return 1;
}
/* set aging offset */
res = ds3231_set_aging_offset(&gs_handle, reg);
if (res != 0)
{
ds3231_interface_debug_print("ds3231: set aging offset failed.\n");
(void)ds3231_deinit(&gs_handle);
return 1;
}
return 0;
}
/**
* @brief basic example deinit
* @return status code
* - 0 success
* - 1 deinit failed
* @note none
*/
uint8_t ds3231_basic_deinit(void)
{
if (ds3231_deinit(&gs_handle) != 0)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief basic example set the time
* @param[in] *t points to a time structure
* @return status code
* - 0 success
* - 1 set time failed
* @note none
*/
uint8_t ds3231_basic_set_time(ds3231_time_t *t)
{
/* set time */
if (ds3231_set_time(&gs_handle, t) != 0)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief basic example set the time by a unix timestamp
* @param[in] timestamp is a unix timestamp
* @return status code
* - 0 success
* - 1 set timestamp failed
* @note none
*/
uint8_t ds3231_basic_set_timestamp(time_t timestamp)
{
ds3231_time_t t;
struct tm *timeptr;
/* convert times */
timestamp += (time_t)(gs_time_zone * 3600);
timeptr = localtime(&timestamp);
t.am_pm = DS3231_AM;
t.date = (uint8_t)timeptr->tm_mday;
t.format = DS3231_FORMAT_24H;
t.hour = (uint8_t)timeptr->tm_hour;
t.minute = (uint8_t)timeptr->tm_min;
t.month = (uint8_t)timeptr->tm_mon + 1;
t.second = (uint8_t)timeptr->tm_sec;
if (timeptr->tm_wday == 0)
{
t.week = 7;
}
else
{
t.week = (uint8_t)timeptr->tm_wday;
}
t.year = (uint16_t)(timeptr->tm_year + 1900);
/* set time */
if (ds3231_set_time(&gs_handle, &t) != 0)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief basic example set the local time zone
* @param[in] zone is the local time zone
* @return status code
* - 0 success
* @note none
*/
uint8_t ds3231_basic_set_timestamp_time_zone(int8_t zone)
{
gs_time_zone = zone;
return 0;
}
/**
* @brief basic example get the time
* @param[out] *t points to a time structure
* @return status code
* - 0 success
* - 1 get time failed
* @note none
*/
uint8_t ds3231_basic_get_time(ds3231_time_t *t)
{
/* get time */
if (ds3231_get_time(&gs_handle, t) != 0)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief basic example get the time in a unix timestamp
* @param[out] *timestamp points to a unix timestamp buffer
* @return status code
* - 0 success
* - 1 get timestamp failed
* @note none
*/
uint8_t ds3231_basic_get_timestamp(time_t *timestamp)
{
ds3231_time_t t;
struct tm timeptr;
/* get time */
if (ds3231_get_time(&gs_handle, &t) != 0)
{
return 1;
}
timeptr.tm_year = t.year - 1900;
timeptr.tm_mon = t.month - 1;
timeptr.tm_wday = t.week;
timeptr.tm_mday = t.date;
if (t.format == DS3231_FORMAT_24H)
{
timeptr.tm_hour = t.hour;
}
else
{
timeptr.tm_hour = t.hour % 12 + t.am_pm * 12;
}
timeptr.tm_min = t.minute;
timeptr.tm_sec = t.second;
/* make time */
*timestamp = mktime(&timeptr) - gs_time_zone * 3600;
return 0;
}
/**
* @brief basic example get the local time zone
* @param[out] *zone points to a local time zone buffer
* @return status code
* - 0 success
* @note none
*/
uint8_t ds3231_basic_get_timestamp_time_zone(int8_t *zone)
{
*zone = gs_time_zone;
return 0;
}
/**
* @brief basic example get the current temperature
* @param[out] *raw points to a raw temperature buffer
* @param[out] *s points to a converted temperature buffer
* @return status code
* - 0 success
* - 1 read temperature failed
* @note none
*/
uint8_t ds3231_basic_get_temperature(int16_t *raw, float *s)
{
/* get temperature */
if (ds3231_get_temperature(&gs_handle, raw, s) != 0)
{
return 1;
}
else
{
return 0;
}
}
/**
* @brief basic example get the ascii time
* @param[out] *buf points to an ascii buffer
* @param[in] len is the data length
* @return status code
* - 0 success
* - 1 read failed
* @note none
*/
uint8_t ds3231_basic_get_ascii_time(char *buf, uint8_t len)
{
ds3231_time_t t;
/* get time */
if (ds3231_get_time(&gs_handle, &t) != 0)
{
return 1;
}
if (t.format == DS3231_FORMAT_24H)
{
(void)snprintf(buf, len, "%04d-%02d-%02d %02d:%02d:%02d %d.\n", t.year, t.month, t.date, t.hour, t.minute, t.second, t.week);
}
else
{
(void)snprintf(buf, len, "%04d-%02d-%02d %s %02d:%02d:%02d %d.\n", t.year, t.month, t.date, (t.am_pm == DS3231_AM) ? "AM" : "PM",
t.hour, t.minute, t.second, t.week
);
}
return 0;
}

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/**
* Copyright (c) 2015 - present LibDriver All rights reserved
*
* The MIT License (MIT)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* @file driver_ds3231_basic.h
* @brief driver ds3231 basic header file
* @version 2.0.0
* @author Shifeng Li
* @date 2021-03-15
*
* <h3>history</h3>
* <table>
* <tr><th>Date <th>Version <th>Author <th>Description
* <tr><td>2021/03/15 <td>2.0 <td>Shifeng Li <td>format the code
* <tr><td>2020/11/30 <td>1.0 <td>Shifeng Li <td>first upload
* </table>
*/
#ifndef DRIVER_DS3231_BASIC_H
#define DRIVER_DS3231_BASIC_H
#include "driver_ds3231_interface.h"
#include <time.h>
#ifdef __cplusplus
extern "C"{
#endif
/**
* @defgroup ds3231_example_driver ds3231 example driver function
* @brief ds3231 example driver modules
* @ingroup ds3231_driver
* @{
*/
/**
* @brief ds3231 basic example default definition
*/
#define DS3231_BASIC_DEFAULT_AGING_OFFSET 0 /**< 0 offset */
/**
* @brief basic example init
* @return status code
* - 0 success
* - 1 init failed
* @note none
*/
uint8_t ds3231_basic_init(void);
/**
* @brief basic example deinit
* @return status code
* - 0 success
* - 1 deinit failed
* @note none
*/
uint8_t ds3231_basic_deinit(void);
/**
* @brief basic example set the time
* @param[in] *t points to a time structure
* @return status code
* - 0 success
* - 1 set time failed
* @note none
*/
uint8_t ds3231_basic_set_time(ds3231_time_t *t);
/**
* @brief basic example get the time
* @param[out] *t points to a time structure
* @return status code
* - 0 success
* - 1 get time failed
* @note none
*/
uint8_t ds3231_basic_get_time(ds3231_time_t *t);
/**
* @brief basic example set the time by a unix timestamp
* @param[in] timestamp is a unix timestamp
* @return status code
* - 0 success
* - 1 set timestamp failed
* @note none
*/
uint8_t ds3231_basic_set_timestamp(time_t timestamp);
/**
* @brief basic example get the time in a unix timestamp
* @param[out] *timestamp points to a unix timestamp buffer
* @return status code
* - 0 success
* - 1 get timestamp failed
* @note none
*/
uint8_t ds3231_basic_get_timestamp(time_t *timestamp);
/**
* @brief basic example set the local time zone
* @param[in] zone is the local time zone
* @return status code
* - 0 success
* @note none
*/
uint8_t ds3231_basic_set_timestamp_time_zone(int8_t zone);
/**
* @brief basic example get the local time zone
* @param[out] *zone points to a local time zone buffer
* @return status code
* - 0 success
* @note none
*/
uint8_t ds3231_basic_get_timestamp_time_zone(int8_t *zone);
/**
* @brief basic example get the current temperature
* @param[out] *raw points to a raw temperature buffer
* @param[out] *s points to a converted temperature buffer
* @return status code
* - 0 success
* - 1 read temperature failed
* @note none
*/
uint8_t ds3231_basic_get_temperature(int16_t *raw, float *s);
/**
* @brief basic example get the ascii time
* @param[out] *buf points to an ascii buffer
* @param[in] len is the data length
* @return status code
* - 0 success
* - 1 read failed
* @note none
*/
uint8_t ds3231_basic_get_ascii_time(char *buf, uint8_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
* Copyright (c) 2015 - present LibDriver All rights reserved
*
* The MIT License (MIT)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* @file driver_ds3231_interface.h
* @brief driver ds3231 interface header file
* @version 2.0.0
* @author Shifeng Li
* @date 2021-03-15
*
* <h3>history</h3>
* <table>
* <tr><th>Date <th>Version <th>Author <th>Description
* <tr><td>2021/03/15 <td>2.0 <td>Shifeng Li <td>format the code
* <tr><td>2020/11/30 <td>1.0 <td>Shifeng Li <td>first upload
* </table>
*/
#ifndef DRIVER_DS3231_INTERFACE_H
#define DRIVER_DS3231_INTERFACE_H
#include "driver_ds3231.h"
#ifdef __cplusplus
extern "C"{
#endif
/**
* @defgroup ds3231_interface_driver ds3231 interface driver function
* @brief ds3231 interface driver modules
* @ingroup ds3231_driver
* @{
*/
/**
* @brief interface iic bus init
* @return status code
* - 0 success
* - 1 iic init failed
* @note none
*/
uint8_t ds3231_interface_iic_init(void);
/**
* @brief interface iic bus deinit
* @return status code
* - 0 success
* - 1 iic deinit failed
* @note none
*/
uint8_t ds3231_interface_iic_deinit(void);
/**
* @brief interface iic bus read
* @param[in] addr is the iic device write address
* @param[in] reg is the iic register address
* @param[out] *buf points to a data buffer
* @param[in] len is the length of the data buffer
* @return status code
* - 0 success
* - 1 read failed
* @note none
*/
uint8_t ds3231_interface_iic_read(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len);
/**
* @brief interface iic bus write
* @param[in] addr is the iic device write address
* @param[in] reg is the iic register address
* @param[in] *buf points to a data buffer
* @param[in] len is the length of the data buffer
* @return status code
* - 0 success
* - 1 write failed
* @note none
*/
uint8_t ds3231_interface_iic_write(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len);
/**
* @brief interface delay ms
* @param[in] ms
* @note none
*/
void ds3231_interface_delay_ms(uint32_t ms);
/**
* @brief interface print format data
* @param[in] fmt is the format data
* @note none
*/
void ds3231_interface_debug_print(const char *const fmt, ...);
/**
* @brief interface receive callback
* @param[in] type is the interrupt type
* @note none
*/
void ds3231_interface_receive_callback(uint8_t type);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
* Copyright (c) 2015 - present LibDriver All rights reserved
*
* The MIT License (MIT)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* @file driver_ds3231_interface_template.c
* @brief driver ds3231 interface template source file
* @version 2.0.0
* @author Shifeng Li
* @date 2021-03-15
*
* <h3>history</h3>
* <table>
* <tr><th>Date <th>Version <th>Author <th>Description
* <tr><td>2021/03/15 <td>2.0 <td>Shifeng Li <td>format the code
* <tr><td>2020/11/30 <td>1.0 <td>Shifeng Li <td>first upload
* </table>
*/
#include "driver_ds3231_interface.h"
#include "gpio_i2c.h"
#include "stdarg.h"
/**
* @brief interface iic bus init
* @return status code
* - 0 success
* - 1 iic init failed
* @note none
*/
uint8_t ds3231_interface_iic_init(void)
{
return 0;
}
/**
* @brief interface iic bus deinit
* @return status code
* - 0 success
* - 1 iic deinit failed
* @note none
*/
uint8_t ds3231_interface_iic_deinit(void)
{
return 0;
}
/**
* @brief interface iic bus read
* @param[in] addr is the iic device write address
* @param[in] reg is the iic register address
* @param[out] *buf points to a data buffer
* @param[in] len is the length of the data buffer
* @return status code
* - 0 success
* - 1 read failed
* @note none
*/
uint8_t ds3231_interface_iic_read(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len)
{
I2C2_Write(addr, &reg, 1);
I2C2_Read(addr, buf, len);
return 0;
}
/**
* @brief interface iic bus write
* @param[in] addr is the iic device write address
* @param[in] reg is the iic register address
* @param[in] *buf points to a data buffer
* @param[in] len is the length of the data buffer
* @return status code
* - 0 success
* - 1 write failed
* @note none
*/
uint8_t ds3231_interface_iic_write(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len)
{
uint8_t WriteData[20];
WriteData[0] = reg;
memcpy(&WriteData[1], buf, len);
len += 1;
I2C2_Write(addr, &WriteData[0], len);
return 0;
}
/**
* @brief interface delay ms
* @param[in] ms
* @note none
*/
void ds3231_interface_delay_ms(uint32_t ms)
{
Delay_ms(ms);
}
/**
* @brief interface print format data
* @param[in] fmt is the format data
* @note none
*/
void ds3231_interface_debug_print(const char *const fmt, ...)
{
char str[256];
uint16_t len;
va_list args;
return;
memset((char *)str, 0, sizeof(char) * 256);
va_start(args, fmt);
vsnprintf((char *)str, 255, (char const *)fmt, args);
va_end(args);
len = strlen((char *)str);
//(void)Uart1_TransmitData((uint8_t *)str, len);
}
/**
* @brief interface receive callback
* @param[in] type is the interrupt type
* @note none
*/
void ds3231_interface_receive_callback(uint8_t type)
{
switch (type)
{
case DS3231_STATUS_ALARM_2 :
{
ds3231_interface_debug_print("ds3231: irq alarm2.\n");
break;
}
case DS3231_STATUS_ALARM_1 :
{
ds3231_interface_debug_print("ds3231: irq alarm1.\n");
break;
}
default :
{
break;
}
}
}

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#include "eeprom.h"
typedef union _eeprom_info
{
struct
{
uint8_t isSave;
uint8_t Mode;
uint8_t Reserved[SECTOR_SIZE_BYTE - 3];
uint8_t CheckSum;
}eeprom_data;
uint8_t eeprom_buffer[SECTOR_SIZE_BYTE];
}EEPROM_INFO;
static EEPROM_INFO eeprom_info;
/*-------------------------------------------------------------------------*//**
* @brief FlashMem_Do_PageWt
* @param[in] tPageAddr
* @param[in] tBuf
* @return None
*//*-------------------------------------------------------------------------*/
void FlashMem_Do_PageWt( uint32_t tPageAddr, uint32_t* tBuf )
{
uint32_t UserID_Buf;
UserID_Buf = 0x4F17DC86;
HAL_FMC_PageWrite( UserID_Buf, tPageAddr, tBuf );
}
/*-------------------------------------------------------------------------*//**
* @brief FlashMem_Do_PageEr
* @param[in] tPageAddr
* @return None
*//*-------------------------------------------------------------------------*/
void FlashMem_Do_PageEr( uint32_t tPageAddr )
{
uint32_t UserID_Buf;
UserID_Buf = 0xA901358F;
HAL_FMC_PageErase( UserID_Buf, tPageAddr );
}
void FlashMEM_Clock_Initialization(void)
{
// enable peripheral clock
HAL_SCU_Peripheral_EnableClock2( PPCLKEN2_FMCLKE, PPxCLKE_Enable );
// init crc
HAL_CRC_Init();
}
bool EEPROM_Read_Mode(uint8_t* pMode)
{
uint8_t i;
uint16_t checksum_init = 0x5AA5;
uint16_t checksum_result;
__disable_irq();
memcpy(&eeprom_info.eeprom_buffer[0], (uint32_t *)CONFIG_ADDRESS, SECTOR_SIZE_BYTE);
__enable_irq();
if(eeprom_info.eeprom_data.isSave != true)
{
return false;
}
// CRC Block Calculation
CRC->INIT = checksum_init;
CRC->CR = 0
| MODS_UserMode // Set User Mode
| CRC_RLTCLR // Initialize CRC_RLT Register With CRC_INIT
| CRC_16 // Polynomial Selection bit : CRC-16
| CRC_NOINC // Address Not Auto Increment
;
CRCRun();
for(i = 0 ; i < (SECTOR_SIZE_BYTE-1) ; i++)
{
CRC->IN = eeprom_info.eeprom_buffer[i];
}
CRCStop();
checksum_result = CRC->RLT;
if((checksum_result & 0xFF) == eeprom_info.eeprom_data.CheckSum)
{
*pMode = eeprom_info.eeprom_data.Mode;
return true;
}
return false;
}
bool EEPROM_Write_Mode(uint8_t Mode)
{
uint8_t i;
uint16_t checksum_init = 0x5AA5;
uint16_t checksum_result;
if(eeprom_info.eeprom_data.isSave == true)
{
if(eeprom_info.eeprom_data.Mode == Mode)
return true;
}
memset(&eeprom_info.eeprom_buffer[0], 0, SECTOR_SIZE_BYTE);
eeprom_info.eeprom_data.isSave = true;
eeprom_info.eeprom_data.Mode = Mode;
// CRC Block Calculation
CRC->INIT = checksum_init;
CRC->CR = 0
| MODS_UserMode // Set User Mode
| CRC_RLTCLR // Initialize CRC_RLT Register With CRC_INIT
| CRC_16 // Polynomial Selection bit : CRC-16
| CRC_NOINC // Address Not Auto Increment
;
CRCRun();
for(i = 0 ; i < (SECTOR_SIZE_BYTE-1) ; i++)
{
CRC->IN = eeprom_info.eeprom_buffer[i];
}
CRCStop();
checksum_result = CRC->RLT;
eeprom_info.eeprom_data.CheckSum = checksum_result & 0xFF;
__disable_irq();
FlashMem_Do_PageEr(CONFIG_ADDRESS);
FlashMem_Do_PageWt(CONFIG_ADDRESS, (uint32_t *)&eeprom_info.eeprom_buffer[0]);
__enable_irq();
return true;
}
#if 0
void EEPROM_Read_Setting_Data(void)
{
#if 0
__disable_irq();
memcpy(&Save_control_Info, (uint32_t *)CONFIG_ADDRESS, SECTOR_SIZE_BYTE);
__enable_irq();
if(Save_control_Info.SaveFlag != EEPROM_SAVE_CHECK_FLAG_DATA)
{
Save_control_Info.SaveFlag = EEPROM_SAVE_CHECK_FLAG_DATA; // 1
Save_control_Info.SaveActionMode = ACTION_MODE_ACTION_AUTO_1; // 2
Save_control_Info.isPowerOnReservation = FALSE; // 3
Save_control_Info.isPowerOnSaturDay = FALSE; // 4
Save_control_Info.PowerOn_Hour = 0; // 5
Save_control_Info.PowerOn_Min = 0; // 6
Save_control_Info.isPowerOffReservation = FALSE; // 7
Save_control_Info.PowerOff_Hour = 0; // 8
Save_control_Info.PowerOff_Min = 0; // 9
Save_control_Info.FanActionTime_1 = 0; // 10
Save_control_Info.FanActionTime_2 = 0; // 11
}
#endif
}
void EEPROM_Write_Seting_Data(void)
{
#if 0
if(Control_Info.isEepromSave == TRUE)
{
Control_Info.isEepromSave = FALSE;
__disable_irq();
FlashMem_Do_PageEr(CONFIG_ADDRESS);
FlashMem_Do_PageWt(CONFIG_ADDRESS, (uint32_t *)&Save_control_Info);
__enable_irq();
}
#endif
}
#endif

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/** \file eeprom.h */
#if !defined(EEPROM_H__702B16C6_4AC7_410F_BD32_D5794BFC24E8__INCLUDED_)
#define EEPROM_H__702B16C6_4AC7_410F_BD32_D5794BFC24E8__INCLUDED_
#include "define.h"
#include "board_config.h"
#define CONFIG_ADDRESS 0x1FFFF400
void FlashMEM_Clock_Initialization(void);
bool EEPROM_Read_Mode(uint8_t* pMode);
bool EEPROM_Write_Mode(uint8_t Mode);
#endif

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#include "gpio_i2c.h"
void Delay_I2C_Delay(uint32_t nDelay)
{
uint32_t i;
for(i = 0 ; i < nDelay ; i++)
{
asm("NOP");
}
}
void GPIO_I2C0_Initialization(void)
{
// configure I2C1 SDA as a Output Mode
HAL_GPIO_ConfigOutput((Pn_Type*)I2C0_SDA_PORT, I2C0_SDA_PIN, PUSH_PULL_OUTPUT );
HAL_GPIO_ConfigPullup((Pn_Type*)I2C0_SDA_PORT, I2C0_SDA_PIN, PUPDx_EnablePU );
// configure I2C1 SCL as a Output Mode
HAL_GPIO_ConfigOutput((Pn_Type*)I2C0_SCL_PORT, I2C0_SCL_PIN, PUSH_PULL_OUTPUT );
HAL_GPIO_ConfigPullup((Pn_Type*)I2C0_SCL_PORT, I2C0_SCL_PIN, PUPDx_EnablePU );
I2C0_SDA_HIGH;
I2C0_SCL_HIGH;
}
void GPIO_I2C0_Start(void)
{
I2C0_SDA_OUTPUT;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SDA_HIGH;
I2C0_SCL_HIGH;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SDA_LOW;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SCL_LOW;
Delay_I2C_Delay(I2C0_DELAY);
}
void GPIO_I2C0_Stop(void)
{
I2C0_SDA_LOW;
I2C0_SDA_OUTPUT;
I2C0_SDA_LOW;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SCL_HIGH;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SDA_HIGH;
}
uint8_t GPIO_I2C0_Write(uint8_t data)
{
uint8_t Ret;
unsigned char i;
I2C0_SDA_OUTPUT;
for(i = 0 ; i < 8 ; i++)
{
if((data & 0x80)==0x80)
{
I2C0_SDA_HIGH;
}
else
{
I2C0_SDA_LOW;
}
data<<=1;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SCL_HIGH;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SCL_LOW;
Delay_I2C_Delay(I2C0_DELAY);
}
I2C0_SDA_INPUTS;
I2C0_SCL_HIGH;
Delay_I2C_Delay(I2C0_DELAY);
Ret = I2C0_SDA_READ;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SCL_LOW;
return Ret;
}
uint8_t GPIO_I2C0_Read(uint8_t rs)
{
uint8_t i;
uint8_t Ret = 0x00;
I2C0_SDA_INPUTS;
for(i = 0 ; i < 8 ; i++)
{
I2C0_SCL_HIGH;
Delay_I2C_Delay(I2C0_DELAY);
Ret <<= 1;
if(I2C0_SDA_READ != 0)
{
Ret |= 0x01;
}
I2C0_SCL_LOW;
Delay_I2C_Delay(I2C0_DELAY);
}
I2C0_SDA_OUTPUT;
if(rs == I2C_ACK)
{
I2C0_SDA_LOW;
}
else
{
I2C0_SDA_HIGH;
}
I2C0_SCL_HIGH;
Delay_I2C_Delay(I2C0_DELAY);
I2C0_SCL_LOW;
Delay_I2C_Delay(I2C0_DELAY);
return Ret;
}
uint8_t I2C0_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize)
{
uint16_t i;
GPIO_I2C0_Start();
GPIO_I2C0_Write(Address << 1);
for(i = 0 ; i < WriteDataSize ; i++)
{
GPIO_I2C0_Write(pWriteData[i]);
}
GPIO_I2C0_Stop();
return 0;
}
uint8_t I2C0_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize)
{
uint16_t i;
GPIO_I2C0_Start();
GPIO_I2C0_Write((Address << 1) | 1);
for(i = 0 ; i < ReadDataSize-1 ; i++)
{
pReadData[i] = GPIO_I2C0_Read(I2C_ACK);
}
pReadData[i] = GPIO_I2C0_Read(I2C_NACK);
GPIO_I2C0_Stop();
return 0;
}
/////////////////////////////////////////////////////////////////////////////
void GPIO_I2C1_Initialization(void)
{
// configure I2C1 SDA as a Output Mode
HAL_GPIO_ConfigOutput((Pn_Type*)I2C1_SDA_PORT, I2C1_SDA_PIN, PUSH_PULL_OUTPUT );
HAL_GPIO_ConfigPullup((Pn_Type*)I2C1_SDA_PORT, I2C1_SDA_PIN, PUPDx_EnablePU );
// configure I2C1 SCL as a Output Mode
HAL_GPIO_ConfigOutput((Pn_Type*)I2C1_SCL_PORT, I2C1_SCL_PIN, PUSH_PULL_OUTPUT );
HAL_GPIO_ConfigPullup((Pn_Type*)I2C1_SCL_PORT, I2C1_SCL_PIN, PUPDx_EnablePU );
I2C1_SDA_HIGH;
I2C1_SCL_HIGH;
}
void GPIO_I2C1_Start(void)
{
I2C1_SDA_OUTPUT;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SDA_HIGH;
I2C1_SCL_HIGH;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SDA_LOW;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SCL_LOW;
Delay_I2C_Delay(I2C1_DELAY);
}
void GPIO_I2C1_Stop(void)
{
I2C1_SDA_LOW;
I2C1_SDA_OUTPUT;
I2C1_SDA_LOW;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SCL_HIGH;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SDA_HIGH;
}
uint8_t GPIO_I2C1_Write(uint8_t data)
{
uint8_t Ret;
unsigned char i;
I2C1_SDA_OUTPUT;
for(i = 0 ; i < 8 ; i++)
{
if((data & 0x80)==0x80)
{
I2C1_SDA_HIGH;
}
else
{
I2C1_SDA_LOW;
}
data<<=1;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SCL_HIGH;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SCL_LOW;
Delay_I2C_Delay(I2C1_DELAY);
}
I2C1_SDA_INPUTS;
I2C1_SCL_HIGH;
Delay_I2C_Delay(I2C1_DELAY);
Ret = I2C1_SDA_READ;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SCL_LOW;
return Ret;
}
uint8_t GPIO_I2C1_Read(uint8_t rs)
{
uint8_t i;
uint8_t Ret = 0x00;
I2C1_SDA_INPUTS;
for(i = 0 ; i < 8 ; i++)
{
I2C1_SCL_HIGH;
Delay_I2C_Delay(I2C1_DELAY);
Ret <<= 1;
if(I2C1_SDA_READ != 0)
{
Ret |= 0x01;
}
I2C1_SCL_LOW;
Delay_I2C_Delay(I2C1_DELAY);
}
I2C1_SDA_OUTPUT;
if(rs == I2C_ACK)
{
I2C1_SDA_LOW;
}
else
{
I2C1_SDA_HIGH;
}
I2C1_SCL_HIGH;
Delay_I2C_Delay(I2C1_DELAY);
I2C1_SCL_LOW;
Delay_I2C_Delay(I2C1_DELAY);
return Ret;
}
uint8_t I2C1_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize)
{
uint16_t i;
GPIO_I2C1_Start();
GPIO_I2C1_Write(Address << 1);
for(i = 0 ; i < WriteDataSize ; i++)
{
GPIO_I2C1_Write(pWriteData[i]);
}
GPIO_I2C1_Stop();
return 0;
}
uint8_t I2C1_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize)
{
uint16_t i;
GPIO_I2C1_Start();
GPIO_I2C1_Write((Address << 1) | 1);
for(i = 0 ; i < ReadDataSize-1 ; i++)
{
pReadData[i] = GPIO_I2C1_Read(I2C_ACK);
}
pReadData[i] = GPIO_I2C1_Read(I2C_NACK);
GPIO_I2C1_Stop();
return 0;
}
/////////////////////////////////////////////////////////////////////////////
void GPIO_I2C2_Initialization(void)
{
// configure I2C1 SDA as a Output Mode
HAL_GPIO_ConfigOutput((Pn_Type*)I2C2_SDA_PORT, I2C2_SDA_PIN, PUSH_PULL_OUTPUT );
HAL_GPIO_ConfigPullup((Pn_Type*)I2C2_SDA_PORT, I2C2_SDA_PIN, PUPDx_EnablePU );
// configure I2C2 SCL as a Output Mode
HAL_GPIO_ConfigOutput((Pn_Type*)I2C2_SCL_PORT, I2C2_SCL_PIN, PUSH_PULL_OUTPUT );
HAL_GPIO_ConfigPullup((Pn_Type*)I2C2_SCL_PORT, I2C2_SCL_PIN, PUPDx_EnablePU );
I2C2_SDA_HIGH;
I2C2_SCL_HIGH;
}
void GPIO_I2C2_Start(void)
{
I2C2_SDA_OUTPUT;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SDA_HIGH;
I2C2_SCL_HIGH;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SDA_LOW;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SCL_LOW;
Delay_I2C_Delay(I2C2_DELAY);
}
void GPIO_I2C2_Stop(void)
{
I2C2_SDA_LOW;
I2C2_SDA_OUTPUT;
I2C2_SDA_LOW;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SCL_HIGH;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SDA_HIGH;
}
uint8_t GPIO_I2C2_Write(uint8_t data)
{
uint8_t Ret;
unsigned char i;
I2C2_SDA_OUTPUT;
for(i = 0 ; i < 8 ; i++)
{
if((data & 0x80)==0x80)
{
I2C2_SDA_HIGH;
}
else
{
I2C2_SDA_LOW;
}
data<<=1;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SCL_HIGH;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SCL_LOW;
Delay_I2C_Delay(I2C2_DELAY);
}
I2C2_SDA_INPUTS;
I2C2_SCL_HIGH;
Delay_I2C_Delay(I2C2_DELAY);
Ret = I2C2_SDA_READ;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SCL_LOW;
return Ret;
}
uint8_t GPIO_I2C2_Read(uint8_t rs)
{
uint8_t i;
uint8_t Ret = 0x00;
I2C2_SDA_INPUTS;
for(i = 0 ; i < 8 ; i++)
{
I2C2_SCL_HIGH;
Delay_I2C_Delay(I2C2_DELAY);
Ret <<= 1;
if(I2C2_SDA_READ != 0)
{
Ret |= 0x01;
}
I2C2_SCL_LOW;
Delay_I2C_Delay(I2C2_DELAY);
}
I2C2_SDA_OUTPUT;
if(rs == I2C_ACK)
{
I2C2_SDA_LOW;
}
else
{
I2C2_SDA_HIGH;
}
I2C2_SCL_HIGH;
Delay_I2C_Delay(I2C2_DELAY);
I2C2_SCL_LOW;
Delay_I2C_Delay(I2C2_DELAY);
return Ret;
}
uint8_t I2C2_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize)
{
uint16_t i;
GPIO_I2C2_Start();
GPIO_I2C2_Write(Address << 1);
for(i = 0 ; i < WriteDataSize ; i++)
{
GPIO_I2C2_Write(pWriteData[i]);
}
GPIO_I2C2_Stop();
return 0;
}
uint8_t I2C2_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize)
{
uint16_t i;
GPIO_I2C2_Start();
GPIO_I2C2_Write((Address << 1) | 1);
for(i = 0 ; i < ReadDataSize-1 ; i++)
{
pReadData[i] = GPIO_I2C2_Read(I2C_ACK);
}
pReadData[i] = GPIO_I2C2_Read(I2C_NACK);
GPIO_I2C2_Stop();
return 0;
}

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/** \file gpio_i2c.h */
#if !defined(GPIO_I2C_H__817813DF_FB6D_4121_912A_DD8A262A2476__INCLUDED_)
#define GPIO_I2C_H__817813DF_FB6D_4121_912A_DD8A262A2476__INCLUDED_
#include "define.h"
#include "board_config.h"
#define I2C_ACK 0
#define I2C_NACK 1
#define I2C0_SDA_PORT PD
#define I2C0_SCL_PORT PD
#define I2C0_SDA_PIN 1
#define I2C0_SCL_PIN 0
#define I2C0_DELAY 30
#define I2C0_SCL_HIGH HAL_GPIO_SetPin((Pn_Type*)I2C0_SCL_PORT,_BIT(I2C0_SCL_PIN))
#define I2C0_SCL_LOW HAL_GPIO_ClearPin((Pn_Type*)I2C0_SCL_PORT,_BIT(I2C0_SCL_PIN))
#define I2C0_SDA_HIGH HAL_GPIO_SetPin((Pn_Type*)I2C0_SDA_PORT,_BIT(I2C0_SDA_PIN))
#define I2C0_SDA_LOW HAL_GPIO_ClearPin((Pn_Type*)I2C0_SDA_PORT,_BIT(I2C0_SDA_PIN))
#define I2C0_SDA_OUTPUT HAL_GPIO_ConfigOutput((Pn_Type*)I2C0_SDA_PORT, I2C0_SDA_PIN, PUSH_PULL_OUTPUT)
#define I2C0_SDA_INPUTS HAL_GPIO_ConfigOutput((Pn_Type*)I2C0_SDA_PORT, I2C0_SDA_PIN, INPUT)
#define I2C0_ACK_READ TESTBIT(I2C0_SDA_PORT->INDR, I2C0_SDA_PIN)
#define I2C0_SDA_READ TESTBIT(I2C0_SDA_PORT->INDR, I2C0_SDA_PIN)
#define I2C1_SDA_PORT PF
#define I2C1_SCL_PORT PF
#define I2C1_SDA_PIN 1
#define I2C1_SCL_PIN 0
#define I2C1_DELAY 30
#define I2C1_SCL_HIGH HAL_GPIO_SetPin((Pn_Type*)I2C1_SCL_PORT,_BIT(I2C1_SCL_PIN))
#define I2C1_SCL_LOW HAL_GPIO_ClearPin((Pn_Type*)I2C1_SCL_PORT,_BIT(I2C1_SCL_PIN))
#define I2C1_SDA_HIGH HAL_GPIO_SetPin((Pn_Type*)I2C1_SDA_PORT,_BIT(I2C1_SDA_PIN))
#define I2C1_SDA_LOW HAL_GPIO_ClearPin((Pn_Type*)I2C1_SDA_PORT,_BIT(I2C1_SDA_PIN))
#define I2C1_SDA_OUTPUT HAL_GPIO_ConfigOutput((Pn_Type*)I2C1_SDA_PORT, I2C1_SDA_PIN, PUSH_PULL_OUTPUT)
#define I2C1_SDA_INPUTS HAL_GPIO_ConfigOutput((Pn_Type*)I2C1_SDA_PORT, I2C1_SDA_PIN, INPUT)
#define I2C1_ACK_READ TESTBIT(I2C1_SDA_PORT->INDR, I2C1_SDA_PIN)
#define I2C1_SDA_READ TESTBIT(I2C1_SDA_PORT->INDR, I2C1_SDA_PIN)
#define I2C2_SDA_PORT PC
#define I2C2_SCL_PORT PC
#define I2C2_SDA_PIN 5
#define I2C2_SCL_PIN 6
#define I2C2_DELAY 30
#define I2C2_SCL_HIGH HAL_GPIO_SetPin((Pn_Type*)I2C2_SCL_PORT,_BIT(I2C2_SCL_PIN))
#define I2C2_SCL_LOW HAL_GPIO_ClearPin((Pn_Type*)I2C2_SCL_PORT,_BIT(I2C2_SCL_PIN))
#define I2C2_SDA_HIGH HAL_GPIO_SetPin((Pn_Type*)I2C2_SDA_PORT,_BIT(I2C2_SDA_PIN))
#define I2C2_SDA_LOW HAL_GPIO_ClearPin((Pn_Type*)I2C2_SDA_PORT,_BIT(I2C2_SDA_PIN))
#define I2C2_SDA_OUTPUT HAL_GPIO_ConfigOutput((Pn_Type*)I2C2_SDA_PORT, I2C2_SDA_PIN, PUSH_PULL_OUTPUT)
#define I2C2_SDA_INPUTS HAL_GPIO_ConfigOutput((Pn_Type*)I2C2_SDA_PORT, I2C2_SDA_PIN, INPUT)
#define I2C2_ACK_READ TESTBIT(I2C2_SDA_PORT->INDR, I2C2_SDA_PIN)
#define I2C2_SDA_READ TESTBIT(I2C2_SDA_PORT->INDR, I2C2_SDA_PIN)
void GPIO_I2C0_Initialization(void);
void GPIO_I2C0_Start(void);
void GPIO_I2C0_Stop(void);
uint8_t GPIO_I2C0_Write(uint8_t data);
uint8_t GPIO_I2C0_Read(uint8_t rs);
uint8_t I2C0_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize);
uint8_t I2C0_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize);
void GPIO_I2C1_Initialization(void);
void GPIO_I2C1_Start(void);
void GPIO_I2C1_Stop(void);
uint8_t GPIO_I2C1_Write(uint8_t data);
uint8_t GPIO_I2C1_Read(uint8_t rs);
uint8_t I2C1_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize);
uint8_t I2C1_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize);
void GPIO_I2C2_Initialization(void);
void GPIO_I2C2_Start(void);
void GPIO_I2C2_Stop(void);
uint8_t GPIO_I2C2_Write(uint8_t data);
uint8_t GPIO_I2C2_Read(uint8_t rs);
uint8_t I2C2_Write(uint8_t Address, uint8_t* pWriteData, uint8_t WriteDataSize);
uint8_t I2C2_Read(uint8_t Address, uint8_t *pReadData, uint8_t ReadDataSize);
#endif

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Project/Application/gpio_sensor.c
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#include "gpio_sensor.h"
void Gpio_Sensor_PWR_Initialization(void)
{
HAL_GPIO_ConfigOutput(GPIO_SENSOR_PWR_PORT, GPIO_SENSOR_PWR_PIN_NUM, PUSH_PULL_OUTPUT);
HAL_GPIO_ConfigPullup(GPIO_SENSOR_PWR_PORT, GPIO_SENSOR_PWR_PIN_NUM, PUPDx_EnablePU);
GPIO_SENSOR_PWR_OFF;
}

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/** \file gpio_sensor.h */
#if !defined(GPIO_SENSOR_H__8553E44F_09AC_401C_9FD1_67C4131DD471__INCLUDED_)
#define GPIO_SENSOR_H__8553E44F_09AC_401C_9FD1_67C4131DD471__INCLUDED_
#include "define.h"
#include "board_config.h"
#define GPIO_SENSOR_PWR_PORT (Pn_Type*)PD
#define GPIO_SENSOR_PWR_PIN_NUM 6
#define GPIO_SENSOR_PWR_ON HAL_GPIO_SetPin(GPIO_SENSOR_PWR_PORT, _BIT(GPIO_SENSOR_PWR_PIN_NUM))
#define GPIO_SENSOR_PWR_OFF HAL_GPIO_ClearPin(GPIO_SENSOR_PWR_PORT, _BIT(GPIO_SENSOR_PWR_PIN_NUM))
#define GPIO_SENSOR_PWR_T HAL_GPIO_TogglePin(GPIO_SENSOR_PWR_PORT, _BIT(GPIO_SENSOR_PWR_PIN_NUM))
void Gpio_Sensor_PWR_Initialization(void);
#endif

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Project/Application/gpio_state_led.c
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#include "gpio_state_led.h"
#include "sw_timer.h"
static void State_Led_Output_Process(void);
static STATE_LED_MODE StateLedMode = STATE_LED_MODE_UNKNOW;
static STATE_LED_STEP StateLedStep = STATE_LED_STEP_INIT;
static STATE_LED_ONOFF_TIME StateLedTime;
static uint32_t StateLedCheckTime;
static STATE_LED_ONOFF_TIME StateLedOnOffTime[STATE_LED_MODE_MAX] =
{
{100, 900}, //STATE_LED_MODE_OFF,
{500, 500}, //STATE_LED_MODE_1,
{1000, 1000}, //STATE_LED_MODE_2,
{1500, 1500}, //STATE_LED_MODE_3,
{2000, 2000}, //STATE_LED_MODE_4,
{2500, 2500}, //STATE_LED_MODE_5,
};
void Gpio_StateLed_Initialization(void)
{
HAL_GPIO_ConfigOutput(GPIO_STATE_LED_PORT, GPIO_STATE_LED_PIN_NUM, PUSH_PULL_OUTPUT);
HAL_GPIO_ConfigPullup(GPIO_STATE_LED_PORT, GPIO_STATE_LED_PIN_NUM, PUPDx_EnablePU);
Gpio_StateLed_Set_Mode(STATE_LED_MODE_OFF);
SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1, State_Led_Output_Process);
}
void Gpio_StateLed_Set_Mode(STATE_LED_MODE mode)
{
if(StateLedMode == mode)
return;
StateLedMode = mode;
StateLedStep = STATE_LED_STEP_INIT;
StateLedTime = StateLedOnOffTime[mode];
}
STATE_LED_MODE Gpio_StateLed_Get_Mode(void)
{
return StateLedMode;
}
static void State_Led_Output_Process(void)
{
switch(StateLedStep)
{
case STATE_LED_STEP_INIT:
StateLedCheckTime = millis();
StateLedStep = STATE_LED_STEP_ON_TIME;
break;
case STATE_LED_STEP_ON_TIME:
if((millis() - StateLedCheckTime) <= StateLedTime.onTime)
{
GPIO_STATE_LED_ON;
}
else
{
StateLedCheckTime = millis();
StateLedStep = STATE_LED_STEP_OFF_TIME;
}
break;
case STATE_LED_STEP_OFF_TIME:
if((millis() - StateLedCheckTime) <= StateLedTime.OffTime)
{
GPIO_STATE_LED_OFF;
}
else
{
StateLedCheckTime = millis();
StateLedStep = STATE_LED_STEP_ON_TIME;
}
break;
}
}

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Project/Application/gpio_state_led.h
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/** \file gpio_state_led.h */
#if !defined(GPIO_STATE_LED_H__E29D0861_1041_4928_8D5B_AAD6D1FAD6EB__INCLUDED_)
#define GPIO_STATE_LED_H__E29D0861_1041_4928_8D5B_AAD6D1FAD6EB__INCLUDED_
#include "define.h"
#include "board_config.h"
#define GPIO_STATE_LED_PORT (Pn_Type*)PF
#define GPIO_STATE_LED_PIN_NUM 4
#define GPIO_STATE_LED_ON HAL_GPIO_ClearPin(GPIO_STATE_LED_PORT, _BIT(GPIO_STATE_LED_PIN_NUM))
#define GPIO_STATE_LED_OFF HAL_GPIO_SetPin(GPIO_STATE_LED_PORT, _BIT(GPIO_STATE_LED_PIN_NUM))
#define GPIO_STATE_LED_T HAL_GPIO_TogglePin(GPIO_STATE_LED_PORT, _BIT(GPIO_STATE_LED_PIN_NUM))
typedef enum _state_led_mode
{
STATE_LED_MODE_OFF,
STATE_LED_MODE_1,
STATE_LED_MODE_2,
STATE_LED_MODE_3,
STATE_LED_MODE_4,
STATE_LED_MODE_5,
STATE_LED_MODE_MAX,
STATE_LED_MODE_UNKNOW,
}STATE_LED_MODE;
typedef enum _state_led_step
{
STATE_LED_STEP_INIT,
STATE_LED_STEP_ON_TIME,
STATE_LED_STEP_OFF_TIME,
}STATE_LED_STEP;
typedef struct _state_led_onoff_time
{
uint32_t onTime;
uint32_t OffTime;
}STATE_LED_ONOFF_TIME;
void Gpio_StateLed_Initialization(void);
void Gpio_StateLed_Set_Mode(STATE_LED_MODE mode);
STATE_LED_MODE Gpio_StateLed_Get_Mode(void);
#endif

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Project/Application/gpio_switch.c
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#include "gpio_switch.h"
#include "sw_timer.h"
#include "gpio_state_led.h"
#if 1
#define GPIO_PUSH_SW1_PORT (Pn_Type*)PB
#define GPIO_PUSH_SW1_PIN_NUM 8
#else
#define GPIO_PUSH_SW1_PORT (Pn_Type*)PF
#define GPIO_PUSH_SW1_PIN_NUM 6
#endif
typedef struct
{
Pn_Type* Port;
uint8_t Pin;
uint32_t nPushCount;
uint32_t nLongPushCount;
GPIO_SW_CALLBACK_FN Push_Callback;
GPIO_SW_CALLBACK_FN LongPush_Callback;
GPIO_SW_CALLBACK_FN Release_Callback;
//////////////////////////////////////////////////////////
bool isPush;
bool isLongKeyPush;
uint32_t nCheckCount;
}KEY_CHECK;
static KEY_CHECK KeyCheckInfo[KEY_PUSH_SW_MAX] =
{
{GPIO_PUSH_SW1_PORT, GPIO_PUSH_SW1_PIN_NUM, DEFAULT_KEY_PUSH_COUNT, DEFAULT_LONGKEY_PUSH_COUNT, NULL, NULL, NULL, false, false, 0},
};
static void Gpio_Switch_Check_Process(void);
///////////////////////////////////////////////////////////////////////////////////////////////////////////
void Gpio_Switch_Port_Initialization(void)
{
HAL_GPIO_ConfigOutput((Pn_Type*)GPIO_PUSH_SW1_PORT, GPIO_PUSH_SW1_PIN_NUM, INPUT);
HAL_GPIO_ConfigPullup((Pn_Type*)GPIO_PUSH_SW1_PORT, GPIO_PUSH_SW1_PIN_NUM, PUPDx_EnablePU);
HAL_GPIO_SetDebouncePin((Pn_Type*)GPIO_PUSH_SW1_PORT, GPIO_PUSH_SW1_PIN_NUM, DBCLK_HCLK64);
SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1, Gpio_Switch_Check_Process);
}
void Gpio_Swtich_Set_PushCount(KEY_LIST key, uint32_t Push_Count, uint32_t LongPush_Count)
{
if(key < KEY_PUSH_SW_MAX)
{
KeyCheckInfo[key].nPushCount = Push_Count;
KeyCheckInfo[key].nLongPushCount = LongPush_Count;
}
}
void Gpio_Swtich_Set_Callback(KEY_LIST key, GPIO_SW_CALLBACK_FN Push_Callback, GPIO_SW_CALLBACK_FN LongPush_Callback, GPIO_SW_CALLBACK_FN Release_Callback)
{
if(key < KEY_PUSH_SW_MAX)
{
KeyCheckInfo[key].Push_Callback = Push_Callback;
KeyCheckInfo[key].LongPush_Callback = LongPush_Callback;
KeyCheckInfo[key].Release_Callback = Release_Callback;
}
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////
static void Gpio_Switch_Check_Process(void)
{
uint8_t i;
for(i = 0 ; i < KEY_PUSH_SW_MAX ; i++)
{
if(TESTBIT(HAL_GPIO_ReadPin(KeyCheckInfo[i].Port), KeyCheckInfo[i].Pin) == 0)
{
if(KeyCheckInfo[i].isPush != true)
{
KeyCheckInfo[i].isPush = true;
KeyCheckInfo[i].isLongKeyPush = false;
KeyCheckInfo[i].nCheckCount = 0;
}
else
{
KeyCheckInfo[i].nCheckCount++;
if((KeyCheckInfo[i].nCheckCount >= KeyCheckInfo[i].nLongPushCount) && (KeyCheckInfo[i].isLongKeyPush == false))
{
KeyCheckInfo[i].isLongKeyPush = true;
if(KeyCheckInfo[i].LongPush_Callback != NULL)
{
KeyCheckInfo[i].LongPush_Callback();
}
}
}
}
else
{
if(KeyCheckInfo[i].isLongKeyPush == false)
{
if(KeyCheckInfo[i].nCheckCount >= KeyCheckInfo[i].nPushCount)
{
if(KeyCheckInfo[i].Push_Callback != NULL)
{
KeyCheckInfo[i].Push_Callback();
}
}
}
if(KeyCheckInfo[i].Release_Callback != NULL)
{
KeyCheckInfo[i].Release_Callback();
}
KeyCheckInfo[i].isPush = false;
KeyCheckInfo[i].isLongKeyPush = false;
KeyCheckInfo[i].nCheckCount = 0;
}
}
}

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Project/Application/gpio_switch.h
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/** \file gpio_switch.h */
#if !defined(GPIO_SWITCH_H__7A08A6AB_4529_4D95_A81A_08ECA85DC521__INCLUDED_)
#define GPIO_SWITCH_H__7A08A6AB_4529_4D95_A81A_08ECA85DC521__INCLUDED_
#include "define.h"
#include "board_config.h"
typedef enum
{
KEY_PUSH_SW1,
KEY_PUSH_SW_MAX
}KEY_LIST;
typedef void (*GPIO_SW_CALLBACK_FN) (void);
void Gpio_Switch_Port_Initialization(void);
void Gpio_Swtich_Set_PushCount(KEY_LIST key, uint32_t Push_Count, uint32_t LongPush_Count);
void Gpio_Swtich_Set_Callback(KEY_LIST key, GPIO_SW_CALLBACK_FN Push_Callback, GPIO_SW_CALLBACK_FN LongPush_Callback, GPIO_SW_CALLBACK_FN Release_Callback);
#endif

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Project/Application/main.c
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#include "main.h"
#include "sw_timer.h"
#include "gpio_state_led.h"
#include "gpio_switch.h"
#include "uart1.h"
#include "spi10.h"
#include "spi13.h"
#include "timer12.h"
#include "segment_74hc595d.h"
#include "segment.h"
#include "save_file.h"
#include "driver_ds3231_basic.h"
#include "gpio_i2c.h"
#include "rtc_process.h"
#include "action_process.h"
#include "eeprom.h"
#include "buzzer.h"
#include "uart_packet.h"
void timer_test(void)
{
//Buzzer_On(50);
//Segment_In_Set_Humidity(12);
}
int main(void)
{
System_Clock_Initialization();
Systick_Initialization(1);
FlashMEM_Clock_Initialization();
Timer12_Initialization();
Uart1_Initialization(115200, UARTn_DATA_BIT_8, UARTn_PARITY_BIT_NONE, UARTn_STOP_BIT_1);
SPI10_Initialization(1000000, SPI10_MODE0, false);
Gpio_StateLed_Initialization();
Gpio_Switch_Port_Initialization();
Gpio_Sensor_PWR_Initialization();
GPIO_I2C0_Initialization();
GPIO_I2C1_Initialization();
GPIO_I2C2_Initialization();
Segment_Initialization();
__enable_irq();
RTC_Process_Initialization();
Buzzer_Initialization();
Action_Initialization();
Uart_Packet_Initialization();
//Sensor_Save_SDCard_Process();
SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 500, timer_test);
//Timer12_Set_Match_Interrupt_Callback(timer_test);
while(true)
{
SW_Timer_Callback_Process();
}
}

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Project/Application/main.h
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/** \file main.h */
#if !defined(MAIN_H__5D109DF7_736B_42BD_A8C5_FB39935994BC__INCLUDED_)
#define MAIN_H__5D109DF7_736B_42BD_A8C5_FB39935994BC__INCLUDED_
#include "define.h"
#endif

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Project/Application/ring_buffer.c
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#include "ring_buffer.h"
// 큐 초기화
bool RingBuffer_Initialization(RING_BUFFER* pRingbuffer, bool isOverWrite, uint32_t buffer_size, uint8_t* pBuffer)
{
if(buffer_size == 0 || pRingbuffer == NULL || pBuffer == NULL)
return false;
pRingbuffer->pBuffer = pBuffer;
pRingbuffer->BufferSize = buffer_size;
pRingbuffer->isOverWrite = isOverWrite;
pRingbuffer->front = -1;
pRingbuffer->rear = -1;
return true;
}
bool RingBuffer_Clear(RING_BUFFER* pRingbuffer)
{
if(pRingbuffer == NULL || pRingbuffer->BufferSize == 0 || pRingbuffer->pBuffer == NULL)
return false;
pRingbuffer->front = -1;
pRingbuffer->rear = -1;
return true;
}
bool RingBuffer_isEmpty(RING_BUFFER* pRingbuffer)
{
return (pRingbuffer->front == -1);
}
bool RingBuffer_isFull(RING_BUFFER* pRingbuffer)
{
return ((pRingbuffer->front == 0 && pRingbuffer->rear == (pRingbuffer->BufferSize - 1)) || (pRingbuffer->front == (pRingbuffer->rear + 1)));
}
// 큐에 요소를 추가 (enqueue)
bool RingBuffer_Enqueue(RING_BUFFER* pRingbuffer, uint8_t value)
{
uint8_t temp;
if (RingBuffer_isFull(pRingbuffer))
{
if(pRingbuffer->isOverWrite == false)
return false;
else
RingBuffer_Dequeue(pRingbuffer, &temp);
}
if (pRingbuffer->front == -1)
{
pRingbuffer->front = 0;
}
pRingbuffer->rear = (pRingbuffer->rear + 1) % pRingbuffer->BufferSize;
pRingbuffer->pBuffer[pRingbuffer->rear] = value;
return true;
}
// 큐에서 요소를 제거하고 반환 (dequeue)
bool RingBuffer_Dequeue(RING_BUFFER* pRingbuffer, uint8_t* pRetValue)
{
if (RingBuffer_isEmpty(pRingbuffer))
{
return false;
}
else
{
*pRetValue = pRingbuffer->pBuffer[pRingbuffer->front];
if (pRingbuffer->front == pRingbuffer->rear)
{
pRingbuffer->front = -1;
pRingbuffer->rear = -1;
}
else
{
pRingbuffer->front = (pRingbuffer->front + 1) % pRingbuffer->BufferSize;
}
return true;
}
}
bool RingBuffer_GetData(RING_BUFFER* pRingbuffer, uint8_t* pRetValue)
{
*pRetValue = pRingbuffer->pBuffer[pRingbuffer->front];
return true;
}
bool RingBuffer_PopData(RING_BUFFER* pRingbuffer)
{
if (pRingbuffer->front == pRingbuffer->rear)
{
pRingbuffer->front = -1;
pRingbuffer->rear = -1;
}
else
{
pRingbuffer->front = (pRingbuffer->front + 1) % pRingbuffer->BufferSize;
}
return true;
}
uint32_t RingBuffer_Get_DataSize(RING_BUFFER* pRingbuffer)
{
if (RingBuffer_isEmpty(pRingbuffer))
{
return 0;
}
else if (pRingbuffer->front <= pRingbuffer->rear)
{
return (pRingbuffer->rear - pRingbuffer->front + 1);
}
else
{
return (pRingbuffer->BufferSize - pRingbuffer->front + pRingbuffer->rear + 1);
}
}

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Project/Application/ring_buffer.h
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/** \file ring_buffer.h */
#if !defined(RING_BUFFER_H__002F3B3E_9C40_4947_A8EE_139D5ADFF045__INCLUDED_)
#define RING_BUFFER_H__002F3B3E_9C40_4947_A8EE_139D5ADFF045__INCLUDED_
#include "define.h"
#include "board_config.h"
typedef struct ring_buffer
{
uint8_t* pBuffer;
uint32_t BufferSize;
bool isOverWrite;
int32_t front, rear;
}RING_BUFFER;
bool RingBuffer_Initialization(RING_BUFFER* pRingbuffer, bool isOverWrite, uint32_t buffer_size, uint8_t* pBuffer);
bool RingBuffer_Clear(RING_BUFFER* pRingbuffer);
bool RingBuffer_isEmpty(RING_BUFFER* pRingbuffer);
bool RingBuffer_isFull(RING_BUFFER* pRingbuffer);
bool RingBuffer_Enqueue(RING_BUFFER* pRingbuffer, uint8_t value) ;
bool RingBuffer_Dequeue(RING_BUFFER* pRingbuffer, uint8_t* pRetValue);
bool RingBuffer_GetData(RING_BUFFER* pRingbuffer, uint8_t* pRetValue);
bool RingBuffer_PopData(RING_BUFFER* pRingbuffer);
uint32_t RingBuffer_Get_DataSize(RING_BUFFER* pRingbuffer);
#endif

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Project/Application/rtc_process.c
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#include "rtc_process.h"
#include "sw_timer.h"
#include "driver_ds3231_basic.h"
#include "save_file.h"
static RTC_TIME rtc_Time;
static void RTC_Get_IC_Time_Process(void);
void RTC_Process_Initialization(void)
{
ds3231_basic_init();
SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 1000, RTC_Get_IC_Time_Process);
}
static void RTC_Get_IC_Time_Process(void)
{
ds3231_time_t t;
ds3231_basic_get_time(&t);
rtc_Time.rtc_Year = t.year;
rtc_Time.rtc_Month = t.month;
rtc_Time.rtc_Date = t.date;
if(t.format == DS3231_FORMAT_24H)
rtc_Time.rtc_Hour = t.hour;
else
rtc_Time.rtc_Hour = t.hour % 12 + t.am_pm * 12;
rtc_Time.rtc_Min = t.minute;
rtc_Time.rtc_Sec = t.second;
}
RTC_TIME RTC_Get_Time(void)
{
return rtc_Time;
}

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Project/Application/rtc_process.h
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/** \file rtc_process.h */
#if !defined(RTC_PROCESS_H__D0EA5D23_A0C1_480D_9C2A_A1F6D5C1D9CC__INCLUDED_)
#define RTC_PROCESS_H__D0EA5D23_A0C1_480D_9C2A_A1F6D5C1D9CC__INCLUDED_
#include "define.h"
#include "board_config.h"
typedef struct _rtc_time
{
uint16_t rtc_Year;
uint8_t rtc_Month;
uint8_t rtc_Date;
uint8_t rtc_Hour;
uint8_t rtc_Min;
uint8_t rtc_Sec;
}RTC_TIME;
void RTC_Process_Initialization(void);
RTC_TIME RTC_Get_Time(void);
#endif

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Project/Application/save_file.c
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#include "save_file.h"
#include "fatfs.h"
#include "spi10.h"
#include "rtc_process.h"
#include "action_process.h"
typedef enum
{
SAVE_STEP_INIT,
SAVE_STEP_POWER_ON_WAIT,
SAVE_STEP_SAVE_TIME_CHECK,
SAVE_STEP_SAVE_MOUNT,
SAVE_STEP_SAVE_FILE_OPEN,
SAVE_STEP_SAVE_FILE_LSEEK,
SAVE_STEP_SAVE_FILE_WRITE,
SAVE_STEP_SAVE_FILE_CLOSE,
SAVE_STEP_SAVE_ERROR,
}SAVE_STEP;
static SAVE_STEP SaveStep = SAVE_STEP_INIT;
static uint32_t SaveFileTickCount;
static uint8_t SaveMin;
static FATFS FatFs; //Fatfs handle
static FIL fil; //File handle
static FRESULT fres; //Result after operations
uint8_t FileBuffer[512];
uint32_t WriteDataSize;
static bool isGuidePrint;
static bool isPowerOn;
bool Save_SensorData_SDCard(void)
{
#if 0
RTC_TIME rtc_time;
SENSOR_SAVE_DATA SaveSensorData;
uint32_t writeByte;
rtc_time = RTC_Get_Time();
MX_FATFS_Init();
fres = f_mount(&FatFs, "", 1); //1=mount now
if(fres == FR_DISK_ERR)
{
FATFS_UnLinkDriver("0:/");
MX_FATFS_Init();
fres = f_mount(&FatFs, "", 1); //1=mount now
}
if(fres != FR_OK)
{
return false;
}
sprintf((char *)FileBuffer, "%d_%d_%d.csv", rtc_time.rtc_Year, rtc_time.rtc_Month, rtc_time.rtc_Date);
if(f_open(&fil, FileBuffer, FA_WRITE | FA_READ) != FR_OK)
{
if (f_open(&fil, FileBuffer, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK)
{
return false;
}
else
{
isGuidePrint = true;
}
}
else
{
isGuidePrint = false;
}
fres = f_lseek(&fil, f_size(&fil));
if(fres != FR_OK)
{
f_close(&fil);
return false;
}
if(isGuidePrint == true)
{
sprintf((char *)FileBuffer, "Time,In_PM10.0,In_PM4.0,In_PM2.5,In_PM1.0,In_Humidity,In_Temp,In_Voc,Out_PM10.0,Out_PM4.0,Out_PM2.5,Out_PM1.0,Out_Humidity,Out_Temp,Out_Voc\r\n");
fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
if(fres != FR_OK)
{
f_close(&fil);
return false;
}
}
while(Sensor_RingBuffer_Get_DataSize(&Sensor_RingBuffer_Info) != 0)
{
if(Sensor_RingBuffer_Dequeue(&Sensor_RingBuffer_Info, &SaveSensorData) == true)
{
sprintf((char *)FileBuffer, "%d:%d:%d,", SaveSensorData.rtc_time.rtc_Hour, SaveSensorData.rtc_time.rtc_Min, SaveSensorData.rtc_time.rtc_Sec);
fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
if(fres != FR_OK)
{
f_close(&fil);
return false;
}
if(SaveSensorData.dust_sensor_In_info.isSensorMount == true)
{
sprintf((char *)FileBuffer, "%d,%d,%d,%d,%d,%d,%d,", SaveSensorData.dust_sensor_In_info.Dust_PM10p0,
SaveSensorData.dust_sensor_In_info.Dust_PM4p0,
SaveSensorData.dust_sensor_In_info.Dust_PM2p5,
SaveSensorData.dust_sensor_In_info.Dust_PM1p0,
SaveSensorData.dust_sensor_In_info.Dust_Humidity,
SaveSensorData.dust_sensor_In_info.Dust_Temperature,
SaveSensorData.dust_sensor_In_info.Dust_VOC_Index);
fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
if(fres != FR_OK)
{
f_close(&fil);
return false;
}
#if 0
printf("In,
#endif
}
else
{
sprintf((char *)FileBuffer, "-,-,-,-,-,-,-,");
fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
if(fres != FR_OK)
{
f_close(&fil);
return false;
}
}
if(SaveSensorData.dust_sensor_Out_info.isSensorMount == true)
{
sprintf((char *)FileBuffer, "%d,%d,%d,%d,%d,%d,%d\r\n", SaveSensorData.dust_sensor_Out_info.Dust_PM10p0,
SaveSensorData.dust_sensor_Out_info.Dust_PM4p0,
SaveSensorData.dust_sensor_Out_info.Dust_PM2p5,
SaveSensorData.dust_sensor_Out_info.Dust_PM1p0,
SaveSensorData.dust_sensor_Out_info.Dust_Humidity,
SaveSensorData.dust_sensor_Out_info.Dust_Temperature,
SaveSensorData.dust_sensor_Out_info.Dust_VOC_Index);
fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
if(fres != FR_OK)
{
f_close(&fil);
return false;
}
}
else
{
sprintf((char *)FileBuffer, "-,-,-,-,-,-,-\r\n");
fres = f_write(&fil, FileBuffer, strlen(FileBuffer), &writeByte);
if(fres != FR_OK)
{
f_close(&fil);
return false;
}
}
}
}
f_close(&fil);
#endif
return true;
}

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Project/Application/save_file.h
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/** \file save_file.h */
#if !defined(SAVE_FILE_H__13EABF11_DA2C_4D03_AFD4_9CD0FD384825__INCLUDED_)
#define SAVE_FILE_H__13EABF11_DA2C_4D03_AFD4_9CD0FD384825__INCLUDED_
#include "define.h"
#include "board_config.h"
bool Save_SensorData_SDCard(void);
#endif

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Project/Application/segment.c
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#include "segment.h"
#include "segment_74hc595d.h"
const uint8_t SegmentData[SEG_INDEX_MAX] =
{
0x3F, //SEGMENT_0
0x06, //SEGMENT_1
0x5B, //SEGMENT_2
0x4F, //SEGMENT_3
0x66, //SEGMENT_4
0x6D, //SEGMENT_5
0x7D, //SEGMENT_6
0x07, //SEGMENT_7
0x7F, //SEGMENT_8
0x67, //SEGMENT_9
0x00, //SEGMENT_CLEAR
0x5F, //SEGMENT_A,
0x7C, //SEGMENT_B,
0x58, //SEGMENT_C,
0x5E, //SEGMENT_D,
0x79, //SEGMENT_E,
0x71, //SEGMENT_F,
0x3D, //SEGMENT_G,
0x74, //SEGMENT_H,
0x11, //SEGMENT_I,
0x0D, //SEGMENT_J,
0x75, //SEGMENT_K,
0x38, //SEGMENT_L,
0x55, //SEGMENT_M,
0x54, //SEGMENT_N,
0x5C, //SEGMENT_O,
0x73, //SEGMENT_P,
0x67, //SEGMENT_Q,
0x50, //SEGMENT_R,
0x2D, //SEGMENT_S,
0x78, //SEGMENT_T,
0x1C, //SEGMENT_U,
0x2A, //SEGMENT_V,
0x6A, //SEGMENT_W,
0x14, //SEGMENT_X,
0x6E, //SEGMENT_Y,
0x1B, //SEGMENT_Z,
0x40, //SEGMENT_MINUS
};
uint8_t Segment_OutputBuff[SEGMENT_SELECT_MAX_INDEX][SEGMENT_MAX_DATA_INDEX];
void Segment_In_Set_PM_1p0(uint32_t OutputData)
{
Segment_Toggle_In = false;
if(OutputData >= 9999)
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
}
else if(OutputData >= 1000)
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[OutputData/1000];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 100)
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 10)
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
}
void Segment_In_Set_PM_2p5(uint32_t OutputData)
{
if(OutputData >= 9999)
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
}
else if(OutputData >= 1000)
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[OutputData/1000];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 100)
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 10)
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
}
void Segment_In_Set_PM_4p0(uint32_t OutputData)
{
Segment_Toggle_In = true;
if(OutputData >= 9999)
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[SEG_9];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[SEG_9];
}
else if(OutputData >= 1000)
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[OutputData/1000];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 100)
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 10)
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
}
void Segment_In_Set_PM_10(uint32_t OutputData)
{
if(OutputData >= 9999)
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
}
else if(OutputData >= 1000)
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[OutputData/1000];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 100)
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 10)
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
else
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[(OutputData%10)];
}
}
void Segment_In_Set_Humidity(uint32_t OutputData)
{
if(OutputData >= 99)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_1] = SegmentData[SEG_9];
}
else if(OutputData <= 9)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_1] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_1] = SegmentData[OutputData%10];
}
else
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_1] = SegmentData[OutputData / 10];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_1] = SegmentData[OutputData % 10];
}
}
void Segment_In_Set_Temperature(int32_t OutputData)
{
if(OutputData >= 99)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
}
else if(OutputData <= -10)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[SEG_9];
}
else if(OutputData >= -9 && OutputData <= -1)
{
int32_t temp = OutputData * -1;
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[temp%10];
}
else if(OutputData <= 9 && OutputData >= 0)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[OutputData%10];
}
else
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[OutputData / 10];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[OutputData % 10];
}
}
void Segment_Out_Set_PM_1p0(uint32_t OutputData)
{
Segment_Toggle_Out = false;
if(OutputData >= 9999)
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
}
else if(OutputData >= 1000)
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[OutputData/1000];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 100)
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 10)
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else
{
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
}
void Segment_Out_Set_PM_2p5(uint32_t OutputData)
{
if(OutputData >= 9999)
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
}
else if(OutputData >= 1000)
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[OutputData/1000];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 100)
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 10)
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else
{
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
}
void Segment_Out_Set_PM_4p0(uint32_t OutputData)
{
Segment_Toggle_Out = true;
if(OutputData >= 9999)
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[SEG_9];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[SEG_9];
}
else if(OutputData >= 1000)
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[OutputData/1000];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 100)
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 10)
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else
{
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[DUST_SENSOR_PM40_SELECT_2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
}
void Segment_Out_Set_PM_10(uint32_t OutputData)
{
if(OutputData >= 9999)
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
}
else if(OutputData >= 1000)
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[OutputData/1000];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 100)
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[(OutputData%1000)/100];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else if(OutputData >= 10)
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[(OutputData%100)/10];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
else
{
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[(OutputData%10)];
}
}
void Segment_Out_Set_Humidity(uint32_t OutputData)
{
if(OutputData >= 99)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_3] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_3] = SegmentData[SEG_9];
}
else if(OutputData <= 9)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_3] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_3] = SegmentData[OutputData%10];
}
else
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_3] = SegmentData[OutputData / 10];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_3] = SegmentData[OutputData % 10];
}
}
void Segment_Out_Set_Temperature(int32_t OutputData)
{
if(OutputData >= 99)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
}
else if(OutputData <= -10)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[SEG_9];
}
else if(OutputData >= -9 && OutputData <= -1)
{
int32_t temp = OutputData * -1;
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[temp%10];
}
else if(OutputData <= 9 && OutputData >= 0)
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_CLEAR];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[OutputData%10];
}
else
{
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[OutputData / 10];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[OutputData % 10];
}
}
void Segment_All_Set_Data(uint8_t SegmentData)
{
uint8_t i;
for(i = SEGMENT_F1C1 ; i < SEGMENT_SELECT_MAX_INDEX ; i++)
{
Segment_OutputBuff[i][SEGMENT_DATA_1] = SegmentData;
Segment_OutputBuff[i][SEGMENT_DATA_2] = SegmentData;
Segment_OutputBuff[i][SEGMENT_DATA_3] = SegmentData;
Segment_OutputBuff[i][SEGMENT_DATA_4] = SegmentData;
}
}
void Segment_Show_Version(void)
{
uint8_t i;
uint16_t temp;
for(i = SEGMENT_F1C1 ; i < SEGMENT_SELECT_MAX_INDEX ; i++)
{
Segment_OutputBuff[i][SEGMENT_DATA_1] = 0x00;
Segment_OutputBuff[i][SEGMENT_DATA_2] = 0x00;
Segment_OutputBuff[i][SEGMENT_DATA_3] = 0x00;
Segment_OutputBuff[i][SEGMENT_DATA_4] = 0x00;
}
//Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_9];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_V];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_E];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[SEG_R];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[VERSION_MAJOR] | 0x80;
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[VERSION_MINOR] | 0x80;
temp = VERSION_PATCH;
if(temp >= 99)
{
temp = 99;
}
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[temp/10];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[temp%10];
}
void Segment_Show_Mode(uint8_t Mode)
{
uint8_t i;
uint16_t temp;
for(i = SEGMENT_F1C1 ; i < SEGMENT_SELECT_MAX_INDEX ; i++)
{
Segment_OutputBuff[i][SEGMENT_DATA_1] = 0x00;
Segment_OutputBuff[i][SEGMENT_DATA_2] = 0x00;
Segment_OutputBuff[i][SEGMENT_DATA_3] = 0x00;
Segment_OutputBuff[i][SEGMENT_DATA_4] = 0x00;
}
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_M];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_O];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_D];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[SEG_E];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[Mode];
}
void Segment_In_Sensor_Error(void)
{
Segment_Toggle_In = false;
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_1] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_2] = SegmentData[SEG_MINUS];
}
void Segment_Out_Sensor_Error(void)
{
Segment_Toggle_Out = false;
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F1C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F1C2][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F2C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F2C2][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F3C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F3C2][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_3] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C1][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
Segment_OutputBuff[SEGMENT_F4C2][SEGMENT_DATA_4] = SegmentData[SEG_MINUS];
}

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Project/Application/segment.h
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/** \file segment.h */
#if !defined(SEGMENT_H__CECA83FE_5707_4492_A247_CC6270C87910__INCLUDED_)
#define SEGMENT_H__CECA83FE_5707_4492_A247_CC6270C87910__INCLUDED_
#include "board_config.h"
typedef enum
{
SEG_0,
SEG_1,
SEG_2,
SEG_3,
SEG_4,
SEG_5,
SEG_6,
SEG_7,
SEG_8,
SEG_9,
SEG_CLEAR,
SEG_A,
SEG_B,
SEG_C,
SEG_D,
SEG_E,
SEG_F,
SEG_G,
SEG_H,
SEG_I,
SEG_J,
SEG_K,
SEG_L,
SEG_M,
SEG_N,
SEG_O,
SEG_P,
SEG_Q,
SEG_R,
SEG_S,
SEG_T,
SEG_U,
SEG_V,
SEG_W,
SEG_X,
SEG_Y,
SEG_Z,
SEG_MINUS,
SEG_INDEX_MAX,
}SEGMENT_INDEX;
typedef enum
{
SEGMENT_F1C1,
SEGMENT_F1C2,
SEGMENT_F2C1,
SEGMENT_F2C2,
SEGMENT_F3C1,
SEGMENT_F3C2,
SEGMENT_F4C1,
SEGMENT_F4C2,
SEGMENT_SELECT_MAX_INDEX,
}SEGMENT_SELECT_INDEX;
typedef enum
{
SEGMENT_DATA_1,
SEGMENT_DATA_2,
SEGMENT_DATA_3,
SEGMENT_DATA_4,
SEGMENT_MAX_DATA_INDEX,
}SEGMENT_DATA_INDEX;
extern uint8_t Segment_OutputBuff[SEGMENT_SELECT_MAX_INDEX][SEGMENT_MAX_DATA_INDEX];
extern const uint8_t SegmentData[SEG_INDEX_MAX];
void Segment_In_Set_PM_1p0(uint32_t OutputData);
void Segment_In_Set_PM_2p5(uint32_t OutputData);
void Segment_In_Set_PM_4p0(uint32_t OutputData);
void Segment_In_Set_PM_10(uint32_t OutputData);
void Segment_In_Set_Humidity(uint32_t OutputData);
void Segment_In_Set_Temperature(int32_t OutputData);
void Segment_In_Sensor_Error(void);
void Segment_Out_Set_PM_1p0(uint32_t OutputData);
void Segment_Out_Set_PM_2p5(uint32_t OutputData);
void Segment_Out_Set_PM_4p0(uint32_t OutputData);
void Segment_Out_Set_PM_10(uint32_t OutputData);
void Segment_Out_Set_Humidity(uint32_t OutputData);
void Segment_Out_Set_Temperature(int32_t OutputData);
void Segment_Out_Sensor_Error(void);
void Segment_All_Set_Data(uint8_t SegmentData);
void Segment_Show_Version(void);
void Segment_Show_Mode(uint8_t Mode);
#endif

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Project/Application/segment_74hc595d.c
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#include "segment_74hc595d.h"
#include "segment.h"
#include "timer12.h"
#include "spi13.h"
#include "systick_timer.h"
typedef enum
{
LSB_FIRST,
MSB_FIRST,
}LSB_MSB_MODE;
#define SEGMENT_74HC595D_SDATA_PORT (Pn_Type*)PE
#define SEGMENT_74HC595D_SDATA_PIN 8
#define SEGMENT_74HC595D_SDATA_HIGH HAL_GPIO_SetPin(SEGMENT_74HC595D_SDATA_PORT,_BIT(SEGMENT_74HC595D_SDATA_PIN))
#define SEGMENT_74HC595D_SDATA_LOW HAL_GPIO_ClearPin(SEGMENT_74HC595D_SDATA_PORT,_BIT(SEGMENT_74HC595D_SDATA_PIN))
#define SEGMENT_74HC595D_SCK_PORT (Pn_Type*)PE
#define SEGMENT_74HC595D_SCK_PIN 9
#define SEGMENT_74HC595D_SCK_HIGH HAL_GPIO_SetPin(SEGMENT_74HC595D_SCK_PORT,_BIT(SEGMENT_74HC595D_SCK_PIN))
#define SEGMENT_74HC595D_SCK_LOW HAL_GPIO_ClearPin(SEGMENT_74HC595D_SCK_PORT,_BIT(SEGMENT_74HC595D_SCK_PIN))
#define SEGMENT_74HC595D_LATCH_PORT (Pn_Type*)PE
#define SEGMENT_74HC595D_LATCH_PIN_NUM 10
#define SEGMENT_74HC595D_LATCH_H HAL_GPIO_SetPin(SEGMENT_74HC595D_LATCH_PORT, _BIT(SEGMENT_74HC595D_LATCH_PIN_NUM))
#define SEGMENT_74HC595D_LATCH_L HAL_GPIO_ClearPin(SEGMENT_74HC595D_LATCH_PORT, _BIT(SEGMENT_74HC595D_LATCH_PIN_NUM))
#define SEGMENT_74HC595D_LATCH_T HAL_GPIO_TogglePin(SEGMENT_74HC595D_LATCH_PORT, _BIT(SEGMENT_74HC595D_LATCH_PIN_NUM))
typedef union
{
struct
{
uint8_t HC595_4;
uint8_t HC595_3;
uint8_t HC595_5_F1C1 : 1;
uint8_t HC595_5_F1C2 : 1;
uint8_t HC595_5_F2C1 : 1;
uint8_t HC595_5_F2C2 : 1;
uint8_t HC595_5_F3C1 : 1;
uint8_t HC595_5_F3C2 : 1;
uint8_t HC595_5_F4C1 : 1;
uint8_t HC595_5_F4C2 : 1;
uint8_t HC595_2;
uint8_t HC595_1;
}HC595_Data;
uint8_t HC595_TxBuff[SEGMENT_74HC595D_IC_TOTAL_NUM];
}HC595_OUTPUT_DATA;
static SEGMENT_OUTPUT_STEP SegmentOutputStep;
static HC595_OUTPUT_DATA HC595_OutputData;
static LSB_MSB_MODE HC595_OutputMode = MSB_FIRST;
static uint32_t ToggleTickCount;
static bool isToggle = false;
uint8_t Segment_Buff[SEGMENT_OUTPUT_MAX][SEGMENT_74HC595D_IC_DATA_NUM];
bool Segment_Toggle_In;
bool Segment_Toggle_Out;
static void Segemet_Output_Process(void);
static void Segment_Output_Data(uint8_t* pTxData, uint8_t TxSize);
void Segment_Initialization(void)
{
HAL_GPIO_ConfigOutput(SEGMENT_74HC595D_SDATA_PORT, SEGMENT_74HC595D_SDATA_PIN, PUSH_PULL_OUTPUT);
HAL_GPIO_ConfigPullup(SEGMENT_74HC595D_SDATA_PORT, SEGMENT_74HC595D_SDATA_PIN, PUPDx_EnablePU);
HAL_GPIO_ConfigOutput(SEGMENT_74HC595D_SCK_PORT, SEGMENT_74HC595D_SCK_PIN, PUSH_PULL_OUTPUT);
HAL_GPIO_ConfigPullup(SEGMENT_74HC595D_SCK_PORT, SEGMENT_74HC595D_SCK_PIN, PUPDx_EnablePU);
HAL_GPIO_ConfigOutput(SEGMENT_74HC595D_LATCH_PORT, SEGMENT_74HC595D_LATCH_PIN_NUM, PUSH_PULL_OUTPUT);
HAL_GPIO_ConfigPullup(SEGMENT_74HC595D_LATCH_PORT, SEGMENT_74HC595D_LATCH_PIN_NUM, PUPDx_EnablePU);
SEGMENT_74HC595D_LATCH_H;
SEGMENT_74HC595D_SCK_LOW;
SEGMENT_74HC595D_SDATA_HIGH;
//Segmet_Output_Process();
ToggleTickCount = millis();
isToggle = false;
Timer12_Set_Match_Interrupt_Callback(Segemet_Output_Process);
}
static void Segemet_Output_Process(void)
{
static uint8_t temp = 0;
memset(HC595_OutputData.HC595_TxBuff, 0, SEGMENT_74HC595D_IC_TOTAL_NUM);
if((millis() - ToggleTickCount) >= SEGMENT_TOGGLE_TIME)
{
ToggleTickCount = millis();
isToggle = !isToggle;
}
switch(SegmentOutputStep)
{
case SEGMENT_OUTPUT_F1C1:
HC595_OutputData.HC595_Data.HC595_5_F1C1 = true;
break;
case SEGMENT_OUTPUT_F1C2:
HC595_OutputData.HC595_Data.HC595_5_F1C2 = true;
break;
case SEGMENT_OUTPUT_F2C1:
HC595_OutputData.HC595_Data.HC595_5_F2C1 = true;
break;
case SEGMENT_OUTPUT_F2C2:
HC595_OutputData.HC595_Data.HC595_5_F2C2 = true;
break;
case SEGMENT_OUTPUT_F3C1:
HC595_OutputData.HC595_Data.HC595_5_F3C1 = true;
break;
case SEGMENT_OUTPUT_F3C2:
HC595_OutputData.HC595_Data.HC595_5_F3C2 = true;
break;
case SEGMENT_OUTPUT_F4C1:
HC595_OutputData.HC595_Data.HC595_5_F4C1 = true;
break;
case SEGMENT_OUTPUT_F4C2:
HC595_OutputData.HC595_Data.HC595_5_F4C2 = true;
break;
}
HC595_OutputData.HC595_Data.HC595_1 = Segment_OutputBuff[SegmentOutputStep][0];
HC595_OutputData.HC595_Data.HC595_2 = Segment_OutputBuff[SegmentOutputStep][1];
HC595_OutputData.HC595_Data.HC595_3 = Segment_OutputBuff[SegmentOutputStep][2];
HC595_OutputData.HC595_Data.HC595_4 = Segment_OutputBuff[SegmentOutputStep][3];
if(Segment_Toggle_In == true && isToggle == true)
{
if(SegmentOutputStep == DUST_SENSOR_PM40_SELECT_1 || SegmentOutputStep == DUST_SENSOR_PM40_SELECT_2)
{
HC595_OutputData.HC595_Data.HC595_1 = 0x00;
HC595_OutputData.HC595_Data.HC595_2 = 0x00;
}
}
if(Segment_Toggle_Out == true && isToggle == true)
{
if(SegmentOutputStep == DUST_SENSOR_PM40_SELECT_1 || SegmentOutputStep == DUST_SENSOR_PM40_SELECT_2)
{
HC595_OutputData.HC595_Data.HC595_3 = 0x00;
HC595_OutputData.HC595_Data.HC595_4 = 0x00;
}
}
SEGMENT_74HC595D_LATCH_L;
Segment_Output_Data(HC595_OutputData.HC595_TxBuff, SEGMENT_74HC595D_IC_TOTAL_NUM);
SEGMENT_74HC595D_LATCH_H;
SegmentOutputStep++;
if(SegmentOutputStep >= SEGMENT_OUTPUT_MAX)
{
SegmentOutputStep = SEGMENT_OUTPUT_F1C1;
}
}
static void Segment_Output_Data(uint8_t* pTxData, uint8_t TxSize)
{
uint8_t Temp;
uint8_t i, j;
if(HC595_OutputMode == LSB_FIRST)
{
for(i = 0 ; i < TxSize ; i++)
{
Temp = pTxData[i];
for(j = 0 ; j < 8 ; j++)
{
if((Temp & 0x01))
{
SEGMENT_74HC595D_SDATA_HIGH;
}
else
{
SEGMENT_74HC595D_SDATA_LOW;
}
SEGMENT_74HC595D_SCK_HIGH;
SEGMENT_74HC595D_SCK_LOW;
Temp = Temp >> 1;
}
}
}
else
{
for(i = 0 ; i < TxSize ; i++)
{
Temp = pTxData[i];
for(j = 0 ; j < 8 ; j++)
{
if((Temp & 0x80))
{
SEGMENT_74HC595D_SDATA_HIGH;
}
else
{
SEGMENT_74HC595D_SDATA_LOW;
}
SEGMENT_74HC595D_SCK_HIGH;
SEGMENT_74HC595D_SCK_LOW;
Temp = Temp << 1;
}
}
}
SEGMENT_74HC595D_SDATA_HIGH;
}

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Project/Application/segment_74hc595d.h
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/** \file segment_74hc595d.h */
#if !defined(SEGMENT_74HC595D_H__80B128A2_DCE6_4A8C_812C_0CCA0173ECA2__INCLUDED_)
#define SEGMENT_74HC595D_H__80B128A2_DCE6_4A8C_812C_0CCA0173ECA2__INCLUDED_
#include "define.h"
#include "board_config.h"
#define SEGMENT_74HC595D_IC_DATA_NUM 4
#define SEGMENT_74HC595D_IC_SELECT_NUM 1
#define SEGMENT_74HC595D_IC_TOTAL_NUM (SEGMENT_74HC595D_IC_DATA_NUM + SEGMENT_74HC595D_IC_SELECT_NUM)
typedef enum
{
SEGMENT_OUTPUT_F1C1,
SEGMENT_OUTPUT_F1C2,
SEGMENT_OUTPUT_F2C1,
SEGMENT_OUTPUT_F2C2,
SEGMENT_OUTPUT_F3C1,
SEGMENT_OUTPUT_F3C2,
SEGMENT_OUTPUT_F4C1,
SEGMENT_OUTPUT_F4C2,
SEGMENT_OUTPUT_MAX,
}SEGMENT_OUTPUT_STEP;
void Segment_Initialization(void);
extern uint8_t Segment_Buff[SEGMENT_OUTPUT_MAX][SEGMENT_74HC595D_IC_DATA_NUM];
extern bool Segment_Toggle_In;
extern bool Segment_Toggle_Out;
#endif

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#include "spi10.h"
void SPI10_Initialization(uint32_t speed, SPI10_MODE mode, bool lsbFirst)
{
USART1n_CFG_Type USART1n_Config;
/*
* Initialize USART10
*/
HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 0, ALTERN_FUNC );
HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 0, AFSRx_AF2 );
HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 1, ALTERN_FUNC );
HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 1, AFSRx_AF2 );
HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 2, ALTERN_FUNC );
HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 2, AFSRx_AF2 );
HAL_GPIO_ConfigOutput((Pn_Type*)SPI10_CS_PORT, SPI10_CS_PIN, PUSH_PULL_OUTPUT );
HAL_GPIO_ConfigPullup((Pn_Type*)SPI10_CS_PORT, SPI10_CS_PIN, PUPDx_EnablePU );
SPI10_CS_HIGH;
// default: 38400-8-N-1
HAL_USART_SPI_Mode_Config( &USART1n_Config );
USART1n_Config.Mode = USART1n_SPI_MODE;
USART1n_Config.Baudrate = speed;
USART1n_Config.Databits = USART1n_DATA_BIT_8;
USART1n_Config.Parity = USART1n_PARITY_BIT_NONE;
USART1n_Config.Stopbits = USART1n_STOP_BIT_1;
if(lsbFirst == true)
USART1n_Config.Order = USART1n_SPI_LSB;
else
USART1n_Config.Order = USART1n_SPI_MSB;
switch(mode)
{
case SPI10_MODE0:
USART1n_Config.ACK = USART1n_SPI_TX_RISING;
USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
break;
case SPI10_MODE1:
USART1n_Config.ACK = USART1n_SPI_TX_RISING;
USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
break;
case SPI10_MODE2:
USART1n_Config.ACK = USART1n_SPI_TX_FALLING;
USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
break;
case SPI10_MODE3:
USART1n_Config.ACK = USART1n_SPI_TX_FALLING;
USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
break;
}
HAL_USART_Init( ( USART1n_Type* )USART10, &USART1n_Config );
// SPI Master
HAL_USART_DataControlConfig( ( USART1n_Type* )USART10, USART1n_CONTROL_MASTER, ENABLE );
// ENABLE
HAL_USART_Enable( ( USART1n_Type* )USART10, ENABLE );
}
void SPI10_Transmit(uint8_t* pTxData, uint32_t Tx_Len)
{
uint32_t i;
for(i = 0 ; i < Tx_Len ; i++)
{
USART10->DR = pTxData[i];
while((USART10->ST & 0x40)==0x00){} // transmit complete flag wait
while((USART10->ST & 0x20)==0x00){} // receive complete flag wait
uint8_t temp = USART10->DR;
}
}
void SPI10_SendRecv(uint8_t* pTxByte, uint8_t* pRxByte, uint32_t TRx_Len)
{
uint32_t i;
for(i = 0 ; i < TRx_Len ; i++)
{
USART10->DR = pTxByte[i];
while((USART10->ST & 0x40)==0x00){} // transmit complete flag wait
while((USART10->ST & 0x20)==0x00){} // receive complete flag wait
pRxByte[i] = USART10->DR;
}
}
uint8_t SPI10_SendReceiveByte(uint8_t SendByte)
{
uint8_t recvByte;
USART10->DR = SendByte;
while((USART10->ST & 0x40)==0x00){} // transmit complete flag wait
while((USART10->ST & 0x20)==0x00){} // receive complete flag wait
recvByte = USART10->DR;
return recvByte;
}

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/** \file spi11.h */
#if !defined(SPI10_H__30436C8B_DA45_4E91_95E0_C40C4C083867__INCLUDED_)
#define SPI10_H__30436C8B_DA45_4E91_95E0_C40C4C083867__INCLUDED_
#include "define.h"
#include "board_config.h"
typedef enum
{
SPI10_MODE0,
SPI10_MODE1,
SPI10_MODE2,
SPI10_MODE3,
}SPI10_MODE;
#define SPI10_CS_PORT PA
#define SPI10_CS_PIN 7
#define SPI10_CS_LOW HAL_GPIO_ClearPin((Pn_Type*)SPI10_CS_PORT, _BIT(SPI10_CS_PIN))
#define SPI10_CS_HIGH HAL_GPIO_SetPin((Pn_Type*)SPI10_CS_PORT, _BIT(SPI10_CS_PIN))
void SPI10_Initialization(uint32_t speed, SPI10_MODE mode, bool lsbFirst);
void SPI10_Transmit(uint8_t* pTxData, uint32_t Tx_Len);
void SPI10_SendRecv(uint8_t* pTxByte, uint8_t* pRxByte, uint32_t TRx_Len);
uint8_t SPI10_SendReceiveByte(uint8_t SendByte);
#endif

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#include "spi13.h"
void SPI13_Initialization(uint32_t speed, SPI13_MODE mode, bool lsbFirst)
{
USART1n_CFG_Type USART1n_Config;
/*
* Initialize USART13
*/
// MOSI
HAL_GPIO_ConfigOutput( ( Pn_Type* )PE, 8, ALTERN_FUNC );
HAL_GPIO_ConfigFunction( ( Pn_Type* )PE, 8, AFSRx_AF2 );
// MISO
//HAL_GPIO_ConfigOutput( ( Pn_Type* )PB, 1, ALTERN_FUNC );
//HAL_GPIO_ConfigFunction( ( Pn_Type* )PB, 1, AFSRx_AF2 );
// SCK
HAL_GPIO_ConfigOutput( ( Pn_Type* )PE, 10, ALTERN_FUNC );
HAL_GPIO_ConfigFunction( ( Pn_Type* )PE, 10, AFSRx_AF2 );
// default: 38400-8-N-1
HAL_USART_SPI_Mode_Config( &USART1n_Config );
USART1n_Config.Mode = USART1n_SPI_MODE;
USART1n_Config.Baudrate = speed;
USART1n_Config.Databits = USART1n_DATA_BIT_8;
USART1n_Config.Parity = USART1n_PARITY_BIT_NONE;
USART1n_Config.Stopbits = USART1n_STOP_BIT_1;
if(lsbFirst == true)
USART1n_Config.Order = USART1n_SPI_LSB;
else
USART1n_Config.Order = USART1n_SPI_MSB;
switch(mode)
{
case SPI13_MODE0:
USART1n_Config.ACK = USART1n_SPI_TX_RISING;
USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
break;
case SPI13_MODE1:
USART1n_Config.ACK = USART1n_SPI_TX_RISING;
USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
break;
case SPI13_MODE2:
USART1n_Config.ACK = USART1n_SPI_TX_FALLING;
USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SAMPLE;
break;
case SPI13_MODE3:
USART1n_Config.ACK = USART1n_SPI_TX_FALLING;
USART1n_Config.Edge = USART1n_SPI_TX_LEADEDGE_SETUP;
break;
}
HAL_USART_Init( ( USART1n_Type* )USART13, &USART1n_Config );
// SPI Master
HAL_USART_DataControlConfig( ( USART1n_Type* )USART13, USART1n_CONTROL_MASTER, ENABLE );
// ENABLE
HAL_USART_Enable( ( USART1n_Type* )USART13, ENABLE );
}
void SPI13_Transmit(uint8_t* pTxData, uint32_t Tx_Len)
{
uint32_t i;
for(i = 0 ; i < Tx_Len ; i++)
{
USART13->DR = pTxData[i];
while((USART13->ST & 0x40)==0x00){} // transmit complete flag wait
while((USART13->ST & 0x20)==0x00){} // receive complete flag wait
uint8_t temp = USART13->DR;
}
}
void SPI13_SendRecv(uint8_t* pTxByte, uint8_t* pRxByte, uint32_t TRx_Len)
{
uint32_t i;
for(i = 0 ; i < TRx_Len ; i++)
{
USART13->DR = pTxByte[i];
while((USART13->ST & 0x40)==0x00){} // transmit complete flag wait
while((USART13->ST & 0x20)==0x00){} // receive complete flag wait
pRxByte[i] = USART13->DR;
}
}
uint8_t SPI13_SendReceiveByte(uint8_t SendByte)
{
uint8_t recvByte;
USART13->DR = SendByte;
while((USART13->ST & 0x40)==0x00){} // transmit complete flag wait
while((USART13->ST & 0x20)==0x00){} // receive complete flag wait
recvByte = USART13->DR;
return recvByte;
}

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/** \file spi13.h */
#if !defined(SPI13_H__30436C8B_DA45_4E91_95E0_C40C4C083867__INCLUDED_)
#define SPI10_H__30436C8B_DA45_4E91_95E0_C40C4C083867__INCLUDED_
#include "define.h"
#include "board_config.h"
typedef enum
{
SPI13_MODE0,
SPI13_MODE1,
SPI13_MODE2,
SPI13_MODE3,
}SPI13_MODE;
void SPI13_Initialization(uint32_t speed, SPI13_MODE mode, bool lsbFirst);
void SPI13_Transmit(uint8_t* pTxData, uint32_t Tx_Len);
void SPI13_SendRecv(uint8_t* pTxByte, uint8_t* pRxByte, uint32_t TRx_Len);
uint8_t SPI13_SendReceiveByte(uint8_t SendByte);
#endif

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#include "sw_timer.h"
#include "systick_timer.h"
typedef struct _timer_callback_info
{
SW_TIMER_CALLBACK_TYPE SW_Callback_Type;
uint32_t SW_Timer_StartTick;
uint32_t SW_Timer_PeriodCount;
SW_TIMER_CALLBACK_FN SW_Timer_CallbackFunction;
}SW_TIMER_INFO;
static SW_TIMER_INFO SW_Timer_Info[MAX_SW_TIMER_REGISTER_COUNT];
bool SW_Timer_Callback_Register(SW_TIMER_CALLBACK_TYPE type, uint32_t PeriodTime, SW_TIMER_CALLBACK_FN pTimerCallback)
{
uint8_t i;
bool ret = false;
for(i = 0 ; i < MAX_SW_TIMER_REGISTER_COUNT ; i++)
{
if(SW_Timer_Info[i].SW_Timer_CallbackFunction == NULL)
{
SW_Timer_Info[i].SW_Callback_Type = type;
SW_Timer_Info[i].SW_Timer_StartTick = millis();
SW_Timer_Info[i].SW_Timer_PeriodCount = PeriodTime;
SW_Timer_Info[i].SW_Timer_CallbackFunction = pTimerCallback;
ret = true;
break;
}
}
return ret;
}
bool SW_Timer_Callback_UnRegister(SW_TIMER_CALLBACK_FN pSwTimerCallbackFunc)
{
uint8_t i;
bool ret = false;
for(i = 0 ; i < MAX_SW_TIMER_REGISTER_COUNT ; i++)
{
if(SW_Timer_Info[i].SW_Timer_CallbackFunction == pSwTimerCallbackFunc)
{
SW_Timer_Info[i].SW_Callback_Type = SW_TIMER_RUN_NONE;
SW_Timer_Info[i].SW_Timer_CallbackFunction = NULL;
ret = true;
}
}
return ret;
}
void SW_Timer_Callback_Process(void)
{
uint8_t i;
uint32_t nowTickCount = millis();
for(i = 0 ; i < MAX_SW_TIMER_REGISTER_COUNT ; i++)
{
if(SW_Timer_Info[i].SW_Timer_CallbackFunction != NULL &&
SW_Timer_Info[i].SW_Callback_Type != SW_TIMER_RUN_NONE)
{
if((nowTickCount - SW_Timer_Info[i].SW_Timer_StartTick) >= SW_Timer_Info[i].SW_Timer_PeriodCount)
{
if(SW_Timer_Info[i].SW_Callback_Type == SW_TIMER_RUN_ONNY_ONCE)
{
SW_Timer_Info[i].SW_Timer_StartTick = 0xFFFFFFFF;
SW_Timer_Info[i].SW_Callback_Type = SW_TIMER_RUN_NONE;
SW_Timer_Info[i].SW_Timer_CallbackFunction();
SW_Timer_Info[i].SW_Timer_CallbackFunction = NULL;
}
else
{
SW_Timer_Info[i].SW_Timer_CallbackFunction();
SW_Timer_Info[i].SW_Timer_StartTick = nowTickCount;
}
}
}
}
}

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/** \file sw_timer.h */
#if !defined(SW_TIMER_H__8AF06FDD_AC0A_4693_88C3_8ACCF1AB4372__INCLUDED_)
#define SW_TIMER_H__8AF06FDD_AC0A_4693_88C3_8ACCF1AB4372__INCLUDED_
#include "define.h"
#include "board_config.h"
#define MAX_SW_TIMER_REGISTER_COUNT 10
typedef enum
{
SW_TIMER_RUN_NONE,
SW_TIMER_RUN_ONNY_ONCE,
SW_TIMER_RUN_CONTINUE,
}SW_TIMER_CALLBACK_TYPE;
typedef void (*SW_TIMER_CALLBACK_FN) (void);
bool SW_Timer_Callback_Register(SW_TIMER_CALLBACK_TYPE type, uint32_t PeriodTime, SW_TIMER_CALLBACK_FN pTimerCallback);
bool SW_Timer_Callback_UnRegister(SW_TIMER_CALLBACK_FN pSwTimerCallbackFunc);
void SW_Timer_Callback_Process(void);
#endif

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#include "systick_timer.h"
static uint32_t tick_count;
volatile uint32_t nDelayCount;
/*-------------------------------------------------------------------------*//**
* @brief This function handles SysTick Handler.
* @param None
* @return None
*//*-------------------------------------------------------------------------*/
void SysTick_Handler( void )
{
tick_count++;
if(nDelayCount != 0)
{
nDelayCount--;
}
}
uint32_t millis(void)
{
return tick_count;
}
void Delay_ms(uint32_t nDelay)
{
nDelayCount = nDelay;
while(nDelayCount != 0);
}

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/** \file systick_timer.h */
#if !defined(SYSTICK_TIMER_H__5F17ECEC_79B1_4DE4_9B38_A54E0782477E__INCLUDED_)
#define SYSTICK_TIMER_H__5F17ECEC_79B1_4DE4_9B38_A54E0782477E__INCLUDED_
#include "define.h"
uint32_t millis(void);
void Delay_ms(uint32_t nDelay);
#endif

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#include "timer12.h"
#include "gpio_state_led.h"
#define TIMER1n_PERIPHERAL TIMER12
#define TIMER1n_IRQ_TYPE TIMER12_IRQn
#define TIMER1n_INTERRUPT_MASK MSK_TIMER12
static TIMER_CALLBACK Timer12_Match_Callback = NULL;
void Timer12_Initialization(void)
{
TIMER1n_PERIODICCFG_Type TIMER1n_Config;
TIMER1n_Config.CkSel = TIMER1n_PCLK; // PCLK = 40MHz
TIMER1n_Config.Prescaler = 40; // fTIMER = PCLK / 40 = 1MHz
TIMER1n_Config.ADR = ( 1000 ); // Period = ADR / fTIMER = 1000us
TIMER1n_Config.StartLevel = TIMER1n_START_LOW;
TIMER1n_Config.BDR = 0; // Duty(B) = BDR / fTIMER = 0us // dummy parameter
TIMER1n_Config.ECE = TIMER1n_FALLING_EGDE; // dummy parameter
HAL_TIMER1n_Init((TIMER1n_Type*)TIMER1n_PERIPHERAL, TIMER1n_PERIODIC_MODE, &TIMER1n_Config);
HAL_TIMER1n_ConfigInterrupt((TIMER1n_Type*)TIMER1n_PERIPHERAL, TIMER1n_INTCFG_MIE, ENABLE);
NVIC_SetPriority(TIMER1n_IRQ_TYPE, 3);
NVIC_EnableIRQ(TIMER1n_IRQ_TYPE);
HAL_INT_EInt_MaskDisable(TIMER1n_INTERRUPT_MASK);
HAL_TIMER1n_Cmd((TIMER1n_Type*)TIMER1n_PERIPHERAL, ENABLE ); // timer start & clear
}
void Timer12_Set_Match_Interrupt_Callback(TIMER_CALLBACK Callback)
{
Timer12_Match_Callback = Callback;
}
/*----------------- INTERRUPT SERVICE ROUTINES --------------------------*/
/*********************************************************************//**
* @brief Timer12 interrupt handler sub-routine
* @param[in] None
* @return None
**********************************************************************/
void TIMER12_Handler(void)
{
// TODO : Type your code here
uint32_t status;
status = T1nMaInt_GetFg(TIMER1n_PERIPHERAL);
if (status == 1)
{
T1nMaInt_ClrFg(TIMER1n_PERIPHERAL);
if(Timer12_Match_Callback != NULL)
Timer12_Match_Callback();
}
}

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/** \file timer12.h */
#if !defined(TIMER12_H__2923006F_3CBC_45ED_8A7D_C04AC01E9281__INCLUDED_)
#define TIMER12_H__2923006F_3CBC_45ED_8A7D_C04AC01E9281__INCLUDED_
#include "define.h"
#include "board_config.h"
typedef void (*TIMER_CALLBACK)(void);
void Timer12_Initialization(void);
void Timer12_Set_Match_Interrupt_Callback(TIMER_CALLBACK Callback);
#endif

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/** \file uart.h */
#if !defined(UART_H__06447B60_D695_412E_90C8_93147FA649B9__INCLUDED_)
#define UART_H__06447B60_D695_412E_90C8_93147FA649B9__INCLUDED_
#include "define.h"
#include "struct.h"
#include "ringbuffer.h"
void Uart1_Initialization(uint32_t Baudrate);
void Uart1_Receive_Process(void);
void Uart1_Transmit(uint8_t TxData);
void Usart10_Initialization(uint32_t Baudrate);
void Usart10_Receive_Process(void);
void Usart10_Transmit(uint8_t TxData);
void Usart10_Transmit_Process(void);
void Usart10_Transmit_DataPush(uint8_t TxData);
void Usart10_Recv_Complete_TimeCheck_Process(void);
void Usart10_Transmit_Check_Process(void);
void Usart11_Initialization(uint32_t Baudrate);
void Usart11_Receive_Process(void);
void Usart11_Transmit(uint8_t TxData);
void Usart13_Initialization(uint32_t Baudrate);
void Usart13_Receive_Process(void);
void Usart13_Transmit(uint8_t TxData);
#endif

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#include "uart1.h"
#include "sw_timer.h"
#include "ring_buffer.h"
#define UARTn_TX_INTERRUTP_ENABLE FALSE
#define UARTn_PERIPHERAL UART1
#define UARTn_INTERRUPT_HANDLER UART1_IRQn
#define UARTn_INTERRUPT_MASK MSK_UART1
#define UARTn_INTERRUPT_PRIORITY 3
#define UARTn_TX_PORT PB
#define UARTn_TX_PIN_NUM 6
#define UARTn_RX_PORT PB
#define UARTn_RX_PIN_NUM 7
#define UARTn_TX_BUFFER_SIZE 200
#define UARTn_RX_BUFFER_SIZE 100
static uint8_t Tx_Buffer[UARTn_TX_BUFFER_SIZE];
static uint8_t Rx_Buffer[UARTn_RX_BUFFER_SIZE];
static RING_BUFFER RingBuffer_Tx;
static RING_BUFFER RingBuffer_Rx;
#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
static volatile uint8_t Uartn_TxIntEnable = FALSE;
static void Uart1_Init_TransmitSet(void);
#else
static void Uart1_Transmit_Process(void);
#endif
static void Uart1_Receive_Handler(void);
void Uart1_Initialization(uint32_t Baudrate, UARTn_DATA_BIT_Type Databit, UARTn_PARITY_BIT_Type Paritybit, UARTn_STOP_BIT_Type Stopbit)
{
UARTn_CFG_Type UARTn_Config;
/*
* Initialize UART0 pin connect
*/
HAL_GPIO_ConfigOutput((Pn_Type*)UARTn_RX_PORT, UARTn_RX_PIN_NUM, ALTERN_FUNC );
HAL_GPIO_ConfigFunction((Pn_Type*)UARTn_RX_PORT, UARTn_RX_PIN_NUM, AFSRx_AF1 );
HAL_GPIO_ConfigPullup((Pn_Type*)UARTn_RX_PORT, UARTn_RX_PIN_NUM, PUPDx_EnablePU );
HAL_GPIO_ConfigOutput((Pn_Type*)UARTn_TX_PORT, UARTn_TX_PIN_NUM, ALTERN_FUNC );
HAL_GPIO_ConfigFunction((Pn_Type*)UARTn_TX_PORT, UARTn_TX_PIN_NUM, AFSRx_AF1 );
// default: 38400-8-N-1
HAL_UART_ConfigStructInit(&UARTn_Config);
UARTn_Config.Baudrate = Baudrate;
UARTn_Config.Databits = Databit;
UARTn_Config.Parity = Paritybit;
UARTn_Config.Stopbits = Stopbit;
HAL_UART_Init((UARTn_Type*)UARTn_PERIPHERAL, &UARTn_Config);
/* Enable UART Rx interrupt */
HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_RBR, ENABLE );
#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
// Reset Tx Interrupt state
Uartn_TxIntEnable = RESET;
#else
SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 0, Uart1_Transmit_Process);
#endif
RingBuffer_Initialization(&RingBuffer_Rx, false, UARTn_RX_BUFFER_SIZE, &Rx_Buffer[0]);
RingBuffer_Initialization(&RingBuffer_Tx, false, UARTn_TX_BUFFER_SIZE, &Tx_Buffer[0]);
NVIC_SetPriority(UARTn_INTERRUPT_HANDLER, UARTn_INTERRUPT_PRIORITY);
NVIC_EnableIRQ(UARTn_INTERRUPT_HANDLER );
HAL_INT_EInt_MaskDisable(UARTn_INTERRUPT_MASK);
}
void Uart1_Transmit(uint8_t TxData)
{
#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
/* Temporarily lock out UART transmit interrupts during this read so the UART transmit interrupt won't cause problems with the index values */
HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_THRE, DISABLE );
RingBuffer_Enqueue(&RingBuffer_Tx, TxData);
/*
* Check if current Tx interrupt enable is reset,
* that means the Tx interrupt must be re-enabled
* due to call IntTransmit() function to trigger
* this interrupt type
*/
if(Uartn_TxIntEnable == RESET)
{
Uart1_Init_TransmitSet();
}
/*
* Otherwise, re-enables Tx Interrupt
*/
else
{
HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_THRE, ENABLE );
}
#else
RingBuffer_Enqueue(&RingBuffer_Tx, TxData);
#endif
}
void Uart1_TransmitData(uint8_t* pTxData, uint32_t TxLen)
{
uint32_t i;
#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
HAL_UART_ConfigInterrupt( ( UARTn_Type* )UARTn_PERIPHERAL, UARTn_INTCFG_THRE, DISABLE );
for(i = 0 ; i < TxLen ; i++)
RingBuffer_Enqueue(&RingBuffer_Tx, pTxData[i]);
if(Uartn_TxIntEnable == RESET)
{
Uart1_Init_TransmitSet();
}
else
{
HAL_UART_ConfigInterrupt( ( UARTn_Type* )UARTn_PERIPHERAL, UARTn_INTCFG_THRE, ENABLE );
}
#else
for(i = 0 ; i < TxLen ; i++)
RingBuffer_Enqueue(&RingBuffer_Tx, pTxData[i]);
#endif
}
#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
static void Uart1_Init_TransmitSet(void)
{
// Disable THRE interrupt
HAL_UART_ConfigInterrupt( ( UARTn_Type* )UARTn_PERIPHERAL, UARTn_INTCFG_THRE, DISABLE );
/* Wait until THR empty */
while( HAL_UART_CheckBusy( ( UARTn_Type* )UARTn_PERIPHERAL ) == SET );
while(RingBuffer_Get_DataSize(&RingBuffer_Tx) != 0)
{
uint8_t TxData;
RingBuffer_GetData(&RingBuffer_Tx, &TxData);
if(HAL_UART_Transmit( ( UARTn_Type* )UARTn_PERIPHERAL, &TxData, 1, NONE_BLOCKING ) )
{
/* Update transmit ring FIFO tail pointer */
RingBuffer_PopData(&RingBuffer_Tx);
break;
}
else
{
break;
}
}
/* If there is no more data to send, disable the transmit interrupt - else enable it or keep it enabled */
if(RingBuffer_Get_DataSize(&RingBuffer_Tx) == 0)
{
HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_THRE, DISABLE );
// Reset Tx Interrupt state
Uartn_TxIntEnable = RESET;
}
else
{
// Set Tx Interrupt state
Uartn_TxIntEnable = SET;
HAL_UART_ConfigInterrupt((UARTn_Type*)UARTn_PERIPHERAL, UARTn_INTCFG_THRE, ENABLE );
}
}
#else
static void Uart1_Transmit_Process(void)
{
if(RingBuffer_Get_DataSize(&RingBuffer_Tx) != 0)
{
uint8_t TxData;
RingBuffer_GetData(&RingBuffer_Tx, &TxData);
if(HAL_UART_Transmit((UARTn_Type*)UARTn_PERIPHERAL, &TxData, 1, NONE_BLOCKING))
{
/* Update transmit ring FIFO tail pointer */
RingBuffer_PopData(&RingBuffer_Tx);
}
}
}
#endif
static void Uart1_Receive_Handler(void)
{
uint8_t tmpc;
uint32_t rLen;
while(1)
{
rLen = HAL_UART_Receive((UARTn_Type*)UARTn_PERIPHERAL, &tmpc, 1, NONE_BLOCKING );
if (rLen)
{
RingBuffer_Enqueue(&RingBuffer_Rx, tmpc);
}
else
{
break;
}
}
}
/*********************************************************************//**
* @brief UART1 interrupt handler sub-routine
* @param[in] None
* @return None
**********************************************************************/
void UART1_Handler(void)
{
uint32_t intsrc, tmp;
/* Determine the interrupt source */
intsrc = UARTn_PERIPHERAL->IIR;
tmp = intsrc & UARTn_IIR_INTID_MASK;
// Receiver Line Status
if(tmp == UARTn_IIR_INTID_RLS) // error(Overrun, Parity, Framing or Break Error)
{
}
else if(tmp == UARTn_IIR_INTID_RDA) // Receiver Data Available
{
Uart1_Receive_Handler();
}
else if(tmp == UARTn_IIR_INTID_THRE) // Transmitter Holding Register Empty
{
#if (UARTn_TX_INTERRUTP_ENABLE == TRUE)
Uart1_Init_TransmitSet();
#endif
}
else if(tmp == UARTn_IIR_INTID_TXE) // Transmitter Register Empty
{
}
}
uint32_t Uart1_Get_RecvDataCount(void)
{
return RingBuffer_Get_DataSize(&RingBuffer_Rx);
}
uint8_t Uart1_Get_RecvData(void)
{
uint8_t retData;
RingBuffer_Dequeue(&RingBuffer_Rx, &retData);
return retData;
}

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/** \file uart1.h */
#if !defined(UART1_H__A3672F4B_1033_433E_A296_1444C586906C__INCLUDED_)
#define UART1_H__A3672F4B_1033_433E_A296_1444C586906C__INCLUDED_
#include "board_config.h"
#include "define.h"
void Uart1_Initialization(uint32_t Baudrate, UARTn_DATA_BIT_Type Databit, UARTn_PARITY_BIT_Type Paritybit, UARTn_STOP_BIT_Type Stopbit);
void Uart1_Transmit(uint8_t TxData);
void Uart1_TransmitData(uint8_t* pTxData, uint32_t TxLen);
uint32_t Uart1_Get_RecvDataCount(void);
uint8_t Uart1_Get_RecvData(void);
#endif

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#include "uart_packet.h"
#include "sw_timer.h"
#include "uart1.h"
#include "driver_ds3231_basic.h"
#include "buzzer.h"
#define PACKET_BUFF_SIZE 100
static void Uart_Packet_Make_Process(void);
static void Uart_Packet_Process(uint8_t* pRxBuff);
static uint8_t Pack_Buff[PACKET_BUFF_SIZE];
static uint8_t Pack_Index;
static uint8_t Pack_CheckSum;
static uint8_t Pack_DataLen;
void Uart_Packet_Initialization(void)
{
Pack_Index = 0;
SW_Timer_Callback_Register(SW_TIMER_RUN_CONTINUE, 0, Uart_Packet_Make_Process);
}
static void Uart_Packet_Make_Process(void)
{
if(Uart1_Get_RecvDataCount() != 0)
{
uint8_t RxData = Uart1_Get_RecvData();
if(Pack_Index == PACK_INDEX_STX && RxData == STX)
{
Pack_Buff[Pack_Index++] = RxData;
Pack_CheckSum = RxData;
Pack_DataLen = 0;
}
else if(Pack_Index == PACK_INDEX_CMD && (RxData >= UART_CMD_SET_TIME && RxData < UART_CMD_MAX))
{
Pack_Buff[Pack_Index++] = RxData;
Pack_CheckSum += RxData;
}
else if(Pack_Index == PACK_INDEX_LEN && RxData < (PACKET_BUFF_SIZE - PACK_INDEX_ETX))
{
Pack_Buff[Pack_Index++] = RxData;
Pack_CheckSum += RxData;
Pack_DataLen = RxData;
}
else if(Pack_Index == (PACK_INDEX_CHECKSUM + Pack_DataLen))
{
if(RxData != Pack_CheckSum)
{
Pack_Index = 0;
}
else
{
Pack_Buff[Pack_Index++] = RxData;
}
}
else if(Pack_Index == (PACK_INDEX_ETX + Pack_DataLen))
{
if(RxData != ETX)
{
Pack_Index = 0;
}
else
{
Pack_Buff[Pack_Index++] = RxData;
Uart_Packet_Process(Pack_Buff);
Pack_Index = 0;
}
}
else if(Pack_Index >= PACK_INDEX_DATA && Pack_Index < (PACK_INDEX_DATA + Pack_DataLen))
{
Pack_Buff[Pack_Index++] = RxData;
Pack_CheckSum += RxData;
}
else
{
Pack_Index = 0;
}
}
}
static void Uart_Packet_Process(uint8_t* pRxBuff)
{
UART_CMD cmd = pRxBuff[PACK_INDEX_CMD];
uint8_t DataLen = pRxBuff[PACK_INDEX_LEN];
if(cmd == UART_CMD_SET_TIME && DataLen == 7)
{
uint16_t Year;
uint8_t Month;
uint8_t Date;
uint8_t Hour;
uint8_t Min;
uint8_t Sec;
uint8_t index = 0;
ds3231_time_t set_time;
ds3231_basic_get_time(&set_time);
Year = pRxBuff[PACK_INDEX_DATA + index++] << 8;
Year += pRxBuff[PACK_INDEX_DATA + index++];
Month = pRxBuff[PACK_INDEX_DATA + index++];
Date = pRxBuff[PACK_INDEX_DATA + index++];
Hour = pRxBuff[PACK_INDEX_DATA + index++];
Min = pRxBuff[PACK_INDEX_DATA + index++];
Sec = pRxBuff[PACK_INDEX_DATA + index++];
set_time.format = DS3231_FORMAT_24H;
set_time.year = Year;
set_time.month = Month;
set_time.date = Date;
set_time.hour = Hour;
set_time.minute = Min;
set_time.second = Sec;
// year 2, mon 1, da 1 , h 1, m1, s 1
ds3231_basic_set_time(&set_time);
Buzzer_On(100);
}
}

32
Project/Application/uart_packet.h
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/** \file uart_packet.h */
#if !defined(UART_PACKET_H__4C114ACB_4130_48D0_A3D5_EF34FC3189D2__INCLUDED_)
#define UART_PACKET_H__4C114ACB_4130_48D0_A3D5_EF34FC3189D2__INCLUDED_
#include "define.h"
#include "board_config.h"
#define STX 0x02
#define ETX 0x03
typedef enum
{
PACK_INDEX_STX = 0x00,
PACK_INDEX_CMD = 0x01,
PACK_INDEX_LEN = 0x02,
PACK_INDEX_DATA = 0x03,
PACK_INDEX_CHECKSUM = 0x03,
PACK_INDEX_ETX = 0x04,
}PACKET_INDEX;
typedef enum
{
UART_CMD_SET_TIME = 0x00,
UART_CMD_MAX,
}UART_CMD;
void Uart_Packet_Initialization(void);
#endif

9
Project/EventRecorderStub.scvd
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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

2476
Project/Listings/S_DustSensorView.map
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1299
Project/Listings/option_a31g12x.lst
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866
Project/Listings/startup_a31g12x.lst
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ARM Macro Assembler Page 1
1 00000000 ;/******************************************************
********************//**
2 00000000 ; * @file startup_A31G12x.s
3 00000000 ; * @brief CMSIS Core Device Startup File for
4 00000000 ; * A31G12x Device Series
5 00000000 ; * @version V5.00
6 00000000 ; * @date 02. March 2016
7 00000000 ; ******************************************************
************************/
8 00000000 ;/*
9 00000000 ; * Copyright (c) 2009-2016 ARM Limited. All rights rese
rved.
10 00000000 ; *
11 00000000 ; * SPDX-License-Identifier: Apache-2.0
12 00000000 ; *
13 00000000 ; * Licensed under the Apache License, Version 2.0 (the
License); you may
14 00000000 ; * not use this file except in compliance with the Lice
nse.
15 00000000 ; * You may obtain a copy of the License at
16 00000000 ; *
17 00000000 ; * www.apache.org/licenses/LICENSE-2.0
18 00000000 ; *
19 00000000 ; * Unless required by applicable law or agreed to in wr
iting, software
20 00000000 ; * distributed under the License is distributed on an A
S IS BASIS, WITHOUT
21 00000000 ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express
or implied.
22 00000000 ; * See the License for the specific language governing
permissions and
23 00000000 ; * limitations under the License.
24 00000000 ; */
25 00000000
26 00000000 ;/*
27 00000000 ;//-------- <<< Use Configuration Wizard in Context Menu
>>> ------------------
28 00000000 ;*/
29 00000000
30 00000000
31 00000000 ; <h> Stack Configuration
32 00000000 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
33 00000000 ; </h>
34 00000000
35 00000000 00000500
Stack_Size
EQU 0x00000500
36 00000000
37 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
=3
38 00000000 Stack_Mem
SPACE Stack_Size
39 00000500 __initial_sp
40 00000500
41 00000500
42 00000500 ; <h> Heap Configuration
43 00000500 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
44 00000500 ; </h>
45 00000500
ARM Macro Assembler Page 2
46 00000500 00000080
Heap_Size
EQU 0x00000080
47 00000500
48 00000500 AREA HEAP, NOINIT, READWRITE, ALIGN=
3
49 00000000 __heap_base
50 00000000 Heap_Mem
SPACE Heap_Size
51 00000080 __heap_limit
52 00000080
53 00000080
54 00000080 PRESERVE8
55 00000080 THUMB
56 00000080
57 00000080
58 00000080 ; Vector Table Mapped to Address 0 at Reset
59 00000080
60 00000080 AREA RESET, DATA, READONLY
61 00000000 EXPORT __Vectors
62 00000000 EXPORT __Vectors_End
63 00000000 EXPORT __Vectors_Size
64 00000000
65 00000000 00000000
__Vectors
DCD __initial_sp ; Top of Stack
66 00000004 00000000 DCD Reset_Handler ; Reset Handler
67 00000008 00000000 DCD NMI_Handler ; NMI Handler
68 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
Handler
69 00000010 00000000 DCD 0 ; Reserved
70 00000014 00000000 DCD 0 ; Reserved
71 00000018 00000000 DCD 0 ; Reserved
72 0000001C 00000000 DCD 0 ; Reserved
73 00000020 00000000 DCD 0 ; Reserved
74 00000024 00000000 DCD 0 ; Reserved
75 00000028 00000000 DCD 0 ; Reserved
76 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
77 00000030 00000000 DCD 0 ; Reserved
78 00000034 00000000 DCD 0 ; Reserved
79 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
80 0000003C 00000000 DCD SysTick_Handler
; SysTick Handler
81 00000040
82 00000040 ; External Interrupts
83 00000040 00000000 DCD LVI_Handler ; IRQ 0
84 00000044 00000000 DCD WUT_Handler ; IRQ 1
85 00000048 00000000 DCD WDT_Handler ; IRQ 2
86 0000004C 00000000 DCD EINT0_Handler ; IRQ 3
87 00000050 00000000 DCD EINT1_Handler ; IRQ 4
88 00000054 00000000 DCD EINT2_Handler ; IRQ 5
89 00000058 00000000 DCD EINT3_Handler ; IRQ 6
90 0000005C 00000000 DCD TIMER10_Handler ; IRQ 7
91 00000060 00000000 DCD TIMER11_Handler ; IRQ 8
92 00000064 00000000 DCD TIMER12_Handler ; IRQ 9
93 00000068 00000000 DCD I2C0_Handler ; IRQ 10
94 0000006C 00000000 DCD USART10_Handler ; IRQ 11
95 00000070 00000000 DCD WT_Handler ; IRQ 12
ARM Macro Assembler Page 3
96 00000074 00000000 DCD TIMER30_Handler ; IRQ 13
97 00000078 00000000 DCD I2C1_Handler ; IRQ 14
98 0000007C 00000000 DCD TIMER20_Handler ; IRQ 15
99 00000080 00000000 DCD TIMER21_Handler ; IRQ 16
100 00000084 00000000 DCD USART11_Handler ; IRQ 17
101 00000088 00000000 DCD ADC_Handler ; IRQ 18
102 0000008C 00000000 DCD UART0_Handler ; IRQ 19
103 00000090 00000000 DCD UART1_Handler ; IRQ 20
104 00000094 00000000 DCD TIMER13_Handler ; IRQ 21
105 00000098 00000000 DCD TIMER14_Handler ; IRQ 22
106 0000009C 00000000 DCD TIMER15_Handler ; IRQ 23
107 000000A0 00000000 DCD TIMER16_Handler ; IRQ 24
108 000000A4 00000000 DCD I2C2_Handler ; IRQ 25
109 000000A8 00000000 DCD USART12_Handler ; IRQ 26
110 000000AC 00000000 DCD USART13_Handler ; IRQ 27
111 000000B0 ;DCD RESERVED_Handler ; IRQ 28
112 000000B0 ;DCD RESERVED_Handler ; IRQ 29
113 000000B0 ;DCD RESERVED_Handler ; IRQ 30
114 000000B0 ;DCD RESERVED_Handler ; IRQ 31
115 000000B0 __Vectors_End
116 000000B0
117 000000B0 000000B0
__Vectors_Size
EQU __Vectors_End - __Vectors
118 000000B0
119 000000B0 AREA |.text|, CODE, READONLY
120 00000000
121 00000000
122 00000000 ; Reset Handler
123 00000000
124 00000000 Reset_Handler
PROC
125 00000000 EXPORT Reset_Handler [WEAK
]
126 00000000 IMPORT SystemInit
127 00000000 IMPORT __main
128 00000000 4804 LDR R0, =SystemInit
129 00000002 4780 BLX R0
130 00000004 4804 LDR R0, =__main
131 00000006 4700 BX R0
132 00000008 ENDP
133 00000008
134 00000008
135 00000008 ; Dummy Exception Handlers (infinite loops which can be
modified)
136 00000008
137 00000008 NMI_Handler
PROC
138 00000008 EXPORT NMI_Handler [WEAK
]
139 00000008 E7FE B .
140 0000000A ENDP
142 0000000A HardFault_Handler
PROC
143 0000000A EXPORT HardFault_Handler [WEAK
]
144 0000000A E7FE B .
145 0000000C ENDP
146 0000000C SVC_Handler
ARM Macro Assembler Page 4
PROC
147 0000000C EXPORT SVC_Handler [WEAK
]
148 0000000C E7FE B .
149 0000000E ENDP
150 0000000E PendSV_Handler
PROC
151 0000000E EXPORT PendSV_Handler [WEAK
]
152 0000000E E7FE B .
153 00000010 ENDP
154 00000010 SysTick_Handler
PROC
155 00000010 EXPORT SysTick_Handler [WEAK
]
156 00000010 E7FE B .
157 00000012 ENDP
158 00000012
159 00000012 DEVICE_Handler
PROC
160 00000012
161 00000012 EXPORT LVI_Handler [WEAK
]
162 00000012 EXPORT WUT_Handler [WEAK
]
163 00000012 EXPORT WDT_Handler [WEAK
]
164 00000012 EXPORT EINT0_Handler [WEAK
]
165 00000012 EXPORT EINT1_Handler [WEAK
]
166 00000012 EXPORT EINT2_Handler [WEAK
]
167 00000012 EXPORT EINT3_Handler [WEAK
]
168 00000012 EXPORT TIMER10_Handler [WEAK
]
169 00000012 EXPORT TIMER11_Handler [WEAK
]
170 00000012 EXPORT TIMER12_Handler [WEAK
]
171 00000012 EXPORT I2C0_Handler [WEAK
]
172 00000012 EXPORT USART10_Handler [WEAK
]
173 00000012 EXPORT WT_Handler [WEAK
]
174 00000012 EXPORT TIMER30_Handler [WEAK
]
175 00000012 EXPORT I2C1_Handler [WEAK
]
176 00000012 EXPORT TIMER20_Handler [WEAK
]
177 00000012 EXPORT TIMER21_Handler [WEAK
]
178 00000012 EXPORT USART11_Handler [WEAK
]
179 00000012 EXPORT ADC_Handler [WEAK
]
ARM Macro Assembler Page 5
180 00000012 EXPORT UART0_Handler [WEAK
]
181 00000012 EXPORT UART1_Handler [WEAK
]
182 00000012 EXPORT TIMER13_Handler [WEAK
]
183 00000012 EXPORT TIMER14_Handler [WEAK
]
184 00000012 EXPORT TIMER15_Handler [WEAK
]
185 00000012 EXPORT TIMER16_Handler [WEAK
]
186 00000012 EXPORT I2C2_Handler [WEAK
]
187 00000012 EXPORT USART12_Handler [WEAK
]
188 00000012 EXPORT USART13_Handler [WEAK
]
189 00000012
190 00000012 LVI_Handler
191 00000012 WUT_Handler
192 00000012 WDT_Handler
193 00000012 EINT0_Handler
194 00000012 EINT1_Handler
195 00000012 EINT2_Handler
196 00000012 EINT3_Handler
197 00000012 TIMER10_Handler
198 00000012 TIMER11_Handler
199 00000012 TIMER12_Handler
200 00000012 I2C0_Handler
201 00000012 USART10_Handler
202 00000012 WT_Handler
203 00000012 TIMER30_Handler
204 00000012 I2C1_Handler
205 00000012 TIMER20_Handler
206 00000012 TIMER21_Handler
207 00000012 USART11_Handler
208 00000012 ADC_Handler
209 00000012 UART0_Handler
210 00000012 UART1_Handler
211 00000012 TIMER13_Handler
212 00000012 TIMER14_Handler
213 00000012 TIMER15_Handler
214 00000012 TIMER16_Handler
215 00000012 I2C2_Handler
216 00000012 USART12_Handler
217 00000012 USART13_Handler
218 00000012 E7FE B .
219 00000014
220 00000014 ENDP
221 00000014
222 00000014
223 00000014 ALIGN
224 00000014
225 00000014
226 00000014 ; User Initial Stack & Heap
227 00000014
228 00000014 IF :DEF:__MICROLIB
229 00000014
ARM Macro Assembler Page 6
230 00000014 EXPORT __initial_sp
231 00000014 EXPORT __heap_base
232 00000014 EXPORT __heap_limit
233 00000014
234 00000014 ELSE
249 ENDIF
250 00000014
251 00000014
252 00000014 END
00000000
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw
ork --depend=.\objects\startup_a31g12x.d -o.\objects\startup_a31g12x.o -IC:\Use
rs\Imbis\AppData\Local\Arm\Packs\ABOV\CM0_DFP\1.0.4\A31G12x\Core\include -I"C:\
Program Files (x86)\Keil_v5\ARM\CMSIS\Include" --predefine="__MICROLIB SETA 1"
--predefine="__UVISION_VERSION SETA 533" --list=.\listings\startup_a31g12x.lst
SDK_V2_5_0\Device\Startup\startup_A31G12x.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
STACK 00000000
Symbol: STACK
Definitions
At line 37 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
None
Comment: STACK unused
Stack_Mem 00000000
Symbol: Stack_Mem
Definitions
At line 38 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
None
Comment: Stack_Mem unused
__initial_sp 00000500
Symbol: __initial_sp
Definitions
At line 39 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 65 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 230 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
HEAP 00000000
Symbol: HEAP
Definitions
At line 48 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
None
Comment: HEAP unused
Heap_Mem 00000000
Symbol: Heap_Mem
Definitions
At line 50 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
None
Comment: Heap_Mem unused
__heap_base 00000000
Symbol: __heap_base
Definitions
At line 49 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 231 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Comment: __heap_base used once
__heap_limit 00000080
Symbol: __heap_limit
Definitions
At line 51 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 232 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Comment: __heap_limit used once
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
RESET 00000000
Symbol: RESET
Definitions
At line 60 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
None
Comment: RESET unused
__Vectors 00000000
Symbol: __Vectors
Definitions
At line 65 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 61 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 117 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
__Vectors_End 000000B0
Symbol: __Vectors_End
Definitions
At line 115 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 62 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 117 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 119 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
None
Comment: .text unused
ADC_Handler 00000012
Symbol: ADC_Handler
Definitions
At line 208 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 101 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 179 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
DEVICE_Handler 00000012
Symbol: DEVICE_Handler
Definitions
At line 159 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
None
Comment: DEVICE_Handler unused
EINT0_Handler 00000012
Symbol: EINT0_Handler
Definitions
At line 193 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 86 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 164 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
EINT1_Handler 00000012
Symbol: EINT1_Handler
Definitions
At line 194 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 87 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 165 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
EINT2_Handler 00000012
Symbol: EINT2_Handler
Definitions
At line 195 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 88 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 166 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
EINT3_Handler 00000012
Symbol: EINT3_Handler
Definitions
At line 196 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 89 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
At line 167 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
HardFault_Handler 0000000A
Symbol: HardFault_Handler
Definitions
At line 142 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 68 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 143 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
I2C0_Handler 00000012
Symbol: I2C0_Handler
Definitions
At line 200 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 93 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 171 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
I2C1_Handler 00000012
Symbol: I2C1_Handler
Definitions
At line 204 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 97 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 175 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
I2C2_Handler 00000012
Symbol: I2C2_Handler
Definitions
At line 215 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 108 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 186 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
LVI_Handler 00000012
Symbol: LVI_Handler
Definitions
At line 190 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 83 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 161 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
NMI_Handler 00000008
Symbol: NMI_Handler
Definitions
At line 137 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 67 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 138 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
PendSV_Handler 0000000E
Symbol: PendSV_Handler
ARM Macro Assembler Page 3 Alphabetic symbol ordering
Relocatable symbols
Definitions
At line 150 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 79 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 151 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Reset_Handler 00000000
Symbol: Reset_Handler
Definitions
At line 124 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 66 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 125 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
SVC_Handler 0000000C
Symbol: SVC_Handler
Definitions
At line 146 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 76 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 147 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
SysTick_Handler 00000010
Symbol: SysTick_Handler
Definitions
At line 154 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 80 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 155 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
TIMER10_Handler 00000012
Symbol: TIMER10_Handler
Definitions
At line 197 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 90 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 168 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
TIMER11_Handler 00000012
Symbol: TIMER11_Handler
Definitions
At line 198 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 91 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 169 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
TIMER12_Handler 00000012
Symbol: TIMER12_Handler
Definitions
At line 199 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 92 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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TIMER13_Handler 00000012
Symbol: TIMER13_Handler
Definitions
At line 211 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
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TIMER14_Handler 00000012
Symbol: TIMER14_Handler
Definitions
At line 212 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
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TIMER15_Handler 00000012
Symbol: TIMER15_Handler
Definitions
At line 213 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 106 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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TIMER16_Handler 00000012
Symbol: TIMER16_Handler
Definitions
At line 214 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
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TIMER20_Handler 00000012
Symbol: TIMER20_Handler
Definitions
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Uses
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TIMER21_Handler 00000012
Symbol: TIMER21_Handler
Definitions
At line 206 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 99 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
At line 177 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
TIMER30_Handler 00000012
Symbol: TIMER30_Handler
Definitions
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At line 203 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
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UART0_Handler 00000012
Symbol: UART0_Handler
Definitions
At line 209 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 102 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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UART1_Handler 00000012
Symbol: UART1_Handler
Definitions
At line 210 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
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USART10_Handler 00000012
Symbol: USART10_Handler
Definitions
At line 201 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 94 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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USART11_Handler 00000012
Symbol: USART11_Handler
Definitions
At line 207 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 100 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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USART12_Handler 00000012
Symbol: USART12_Handler
Definitions
At line 216 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 109 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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USART13_Handler 00000012
Symbol: USART13_Handler
Definitions
At line 217 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 110 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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WDT_Handler 00000012
Symbol: WDT_Handler
Definitions
At line 192 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 85 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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WT_Handler 00000012
Symbol: WT_Handler
Definitions
At line 202 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 95 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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WUT_Handler 00000012
Symbol: WUT_Handler
Definitions
At line 191 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 84 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
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Heap_Size 00000080
Symbol: Heap_Size
Definitions
At line 46 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 50 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Comment: Heap_Size used once
Stack_Size 00000500
Symbol: Stack_Size
Definitions
At line 35 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 38 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Comment: Stack_Size used once
__Vectors_Size 000000B0
Symbol: __Vectors_Size
Definitions
At line 117 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 63 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Comment: __Vectors_Size used once
3 symbols
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SystemInit 00000000
Symbol: SystemInit
Definitions
At line 126 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 128 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Comment: SystemInit used once
__main 00000000
Symbol: __main
Definitions
At line 127 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Uses
At line 130 in file SDK_V2_5_0\Device\Startup\startup_A31G12x.s
Comment: __main used once
2 symbols
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Project/SDK_V2_5_0/Core/cmsis_armcc.h
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@ -0,0 +1,734 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return(result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex-M0+
@{
*/
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0+ header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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;/**************************************************************************//**
; * @file startup_A31G12x.s
; * @brief CMSIS Core Device Startup File for
; * A31G12x Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000500
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000080
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD LVI_Handler ; IRQ 0
DCD WUT_Handler ; IRQ 1
DCD WDT_Handler ; IRQ 2
DCD EINT0_Handler ; IRQ 3
DCD EINT1_Handler ; IRQ 4
DCD EINT2_Handler ; IRQ 5
DCD EINT3_Handler ; IRQ 6
DCD TIMER10_Handler ; IRQ 7
DCD TIMER11_Handler ; IRQ 8
DCD TIMER12_Handler ; IRQ 9
DCD I2C0_Handler ; IRQ 10
DCD USART10_Handler ; IRQ 11
DCD WT_Handler ; IRQ 12
DCD TIMER30_Handler ; IRQ 13
DCD I2C1_Handler ; IRQ 14
DCD TIMER20_Handler ; IRQ 15
DCD TIMER21_Handler ; IRQ 16
DCD USART11_Handler ; IRQ 17
DCD ADC_Handler ; IRQ 18
DCD UART0_Handler ; IRQ 19
DCD UART1_Handler ; IRQ 20
DCD TIMER13_Handler ; IRQ 21
DCD TIMER14_Handler ; IRQ 22
DCD TIMER15_Handler ; IRQ 23
DCD TIMER16_Handler ; IRQ 24
DCD I2C2_Handler ; IRQ 25
DCD USART12_Handler ; IRQ 26
DCD USART13_Handler ; IRQ 27
;DCD RESERVED_Handler ; IRQ 28
;DCD RESERVED_Handler ; IRQ 29
;DCD RESERVED_Handler ; IRQ 30
;DCD RESERVED_Handler ; IRQ 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
DEVICE_Handler PROC
EXPORT LVI_Handler [WEAK]
EXPORT WUT_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT EINT0_Handler [WEAK]
EXPORT EINT1_Handler [WEAK]
EXPORT EINT2_Handler [WEAK]
EXPORT EINT3_Handler [WEAK]
EXPORT TIMER10_Handler [WEAK]
EXPORT TIMER11_Handler [WEAK]
EXPORT TIMER12_Handler [WEAK]
EXPORT I2C0_Handler [WEAK]
EXPORT USART10_Handler [WEAK]
EXPORT WT_Handler [WEAK]
EXPORT TIMER30_Handler [WEAK]
EXPORT I2C1_Handler [WEAK]
EXPORT TIMER20_Handler [WEAK]
EXPORT TIMER21_Handler [WEAK]
EXPORT USART11_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT TIMER13_Handler [WEAK]
EXPORT TIMER14_Handler [WEAK]
EXPORT TIMER15_Handler [WEAK]
EXPORT TIMER16_Handler [WEAK]
EXPORT I2C2_Handler [WEAK]
EXPORT USART12_Handler [WEAK]
EXPORT USART13_Handler [WEAK]
LVI_Handler
WUT_Handler
WDT_Handler
EINT0_Handler
EINT1_Handler
EINT2_Handler
EINT3_Handler
TIMER10_Handler
TIMER11_Handler
TIMER12_Handler
I2C0_Handler
USART10_Handler
WT_Handler
TIMER30_Handler
I2C1_Handler
TIMER20_Handler
TIMER21_Handler
USART11_Handler
ADC_Handler
UART0_Handler
UART1_Handler
TIMER13_Handler
TIMER14_Handler
TIMER15_Handler
TIMER16_Handler
I2C2_Handler
USART12_Handler
USART13_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

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Project/SDK_V2_5_0/Device/Startup/system_A31G12x.c
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/***************************************************************************//**
* @file system_A31G12x.c
* @brief CMSIS Device System Source File for
* A31G12x Device Series
* @version V5.00
* @date 10. January 2018
*//***************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "A31G12x.h"
//==============================================================================
// System Core Clock Variable
//==============================================================================
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t mclk; /**< Main Clock Frequency (MCLK) */
uint32_t SystemCoreClock; /**< System Core Clock Frequency (Core Clock & HCLK) */
uint32_t SystemPeriClock; /**< System Peripheral Clock Frequency (PCLK) */
uint32_t ClkSrcTbl[] = { __HIRC, __XMOSC, __XSOSC, __WDTRC };
/*-------------------------------------------------------------------------*//**
* @brief Update SystemCoreClock variable.
* @return None
* @details Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
* @note This function should be executed whenever the clock is changed.
*//*-------------------------------------------------------------------------*/
void SystemCoreClockUpdate( void ) /* Get Core Clock Frequency */
{
mclk = ClkSrcTbl[SCUCG->SCCR_b.MCLKSEL];
if( SCUCG->SCCR_b.MCLKSEL == 0 ) mclk >>= SCUCG->CLKSRCR_b.HIRCSEL; // MCLK
if( SCUCG->SCDIVR1_b.HDIV > 4 ) SCUCG->SCDIVR1_b.HDIV = 4;
SystemCoreClock = mclk >> (4 - SCUCG->SCDIVR1_b.HDIV); // HCLK
SystemPeriClock = SystemCoreClock >> SCUCG->SCDIVR2_b.PDIV; // PCLK
}
/*-------------------------------------------------------------------------*//**
* @brief Setup the microcontroller system.
* @return None
* @details Initialize the System and update the SystemCoreClock variable.
*//*-------------------------------------------------------------------------*/
void SystemInit( void )
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
while( SCUCC->SRSTVR_b.VALID != 0x55 ) {}
// disable interrupt
__disable_irq();
// disable WDT
WDT->CR = 0
| ( 0x5A69uL << WDT_CR_WTIDKY_Pos )
| ( WDT_CR_RSTEN_Disable << WDT_CR_RSTEN_Pos ) // added by lms
| ( WDT_CR_CNTEN_Disable << WDT_CR_CNTEN_Pos )
;
#ifndef __ON_DEBUG__
WDT->SR_b.DBGCNTEN = 0 << WDT_SR_DBGCNTEN_Pos;
#endif
}

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Project/SDK_V2_5_0/Device/Startup/system_A31G12x.h
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/***************************************************************************//**
* @file system_A31G12x.h
* @brief CMSIS Device System Header File for
* A31G12x Device Series
* @version V5.00
* @date 10. January 2018
*//***************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_A31G12x_H
#define SYSTEM_A31G12x_H
#ifdef __cplusplus
extern "C" {
#endif
//==============================================================================
// Define Debug mode or not
//==============================================================================
#define __ON_DEBUG__ // This line should be defined on debug mode only.
//==============================================================================
// Define clocks
//==============================================================================
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define __HIRC (40000000uL) /**< Internal RC Oscillator Frequency */
#define __XMOSC (16000000uL) /**< External Main Crystal Oscillator Frequency */
#define __XSOSC (32768uL) /**< External Sub Crystal Oscillator Frequency */
#define __WDTRC (40000uL) /**< Watch-Dog Timer RC Oscillator Frequency */
extern uint32_t mclk; /**< Main Clock Frequency (MCLK) */
extern uint32_t SystemCoreClock; /**< System Core Clock Frequency (Core Clock & HCLK) */
extern uint32_t SystemPeriClock; /**< System Peripheral Clock Frequency (PCLK) */
/*-------------------------------------------------------------------------*//**
* @brief Setup the microcontroller system.
* @return None
* @details Initialize the System and update the SystemCoreClock variable.
*//*-------------------------------------------------------------------------*/
extern void SystemInit( void );
/*-------------------------------------------------------------------------*//**
* @brief Update SystemCoreClock variable.
* @return None
* @details Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*//*-------------------------------------------------------------------------*/
extern void SystemCoreClockUpdate( void );
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_A31G12x_H */

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Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_aa_types.h
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/***************************************************************************//**
* @file A31G12x_hal_aa_types.h
* @brief Contains the ABOV typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.00
* @date 2020-05-29
* @author ABOV Application Team
*
* Copyright(C) 2019, ABOV Semiconductor
* All rights reserved.
*
********************************************************************************
* ABOV Disclaimer
*
*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
*modifications, and improvements to ABOV products and/or to this document at any time without notice.
*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
*express or implied, to any intellectual property rights is granted by ABOV herein.
*ABOV disclaims all express and implied warranties and shall not be responsible or
*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
*ABOV and the ABOV logo are trademarks of ABOV.
*All other product or service names are the property of their respective owners.
*Information in this document supersedes and replaces the information previously
*supplied in any former versions of this document.
*2020 ABOV Semiconductor All rights reserved
*
*//****************************************************************************/
#ifndef AA_TYPES_H
#define AA_TYPES_H
#ifdef __cplusplus
extern "C" {
#endif
//******************************************************************************
// Constant
//******************************************************************************
/* NULL pointer */
#ifndef NULL
#define NULL ((void*) 0)
#endif
//******************************************************************************
// Type
//******************************************************************************
//==============================================================================
// Enumeration
//==============================================================================
/** HAL Status Type Definition */
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_Status_Type;
/** Boolean Type Definition */
typedef enum
{
FALSE = 0,
TRUE = !FALSE
} Bool;
/** Flag Status and Interrupt Flag Status Type Definition */
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, IntStatus, SetState;
/** Functional State Definition */
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
/** Status Type Definition */
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
} Status;
/** Read/Write Transfer Mode Type */
typedef enum
{
NONE_BLOCKING = 0, /**< Non-Blocking Mode */
BLOCKING, /**< Blocking Mode */
} TRANSFER_BLOCK_Type;
//==============================================================================
// Generic
//==============================================================================
typedef unsigned char b8; // boolean type
typedef char c8; // character type
typedef unsigned char u8; // 8-bit unsigned integer type
typedef signed char s8; // 8-bit signed integer type
typedef unsigned short int u16; // 16-bit unsigned integer type
typedef signed short int s16; // 16-bit signed integer type
// typedef unsigned int u32; // 32-bit unsigned integer type
// typedef signed int s32; // 32-bit signed integer type
typedef unsigned long int u32; // 32-bit unsigned integer type
typedef signed long int s32; // 32-bit signed integer type
typedef unsigned long long int u64; // 64-bit unsigned integer type
typedef signed long long int s64; // 64-bit signed integer type
typedef float f32; // 32-bit floating point type
typedef double f64; // 64-bit floating point type
typedef volatile unsigned char vb8; // boolean type
typedef volatile char vc8; // character type
typedef volatile unsigned char vu8; // 8-bit unsigned integer type
typedef volatile signed char vs8; // 8-bit signed integer type
typedef volatile unsigned short int vu16; // 16-bit unsigned integer type
typedef volatile signed short int vs16; // 16-bit signed integer type
// typedef volatile unsigned int vu32; // 32-bit unsigned integer type
// typedef volatile signed int vs32; // 32-bit signed integer type
typedef volatile unsigned long int vu32; // 32-bit unsigned integer type
typedef volatile signed long int vs32; // 32-bit signed integer type
typedef volatile unsigned long long int vu64; // 64-bit unsigned integer type
typedef volatile signed long long int vs64; // 64-bit signed integer type
typedef volatile float vf32; // 32-bit floating point type
typedef volatile double vf64; // 64-bit floating point type
//******************************************************************************
// Macro
//******************************************************************************
//==============================================================================
// bit operation
//==============================================================================
#define bitm( p ) ((u32)1<<(p))
#define bitp( r, p, v ) { \
r &= ~bitm( p ); \
r |= (((v) & bitm(0)) << (p)); \
}
#define bits( r, p ) r |= bitm( p )
#define bitr( r, p ) r &= ~bitm( p )
#define bitc( r, p ) r ^= bitm( p )
#define bitg( r, p ) ((r&bitm( p )) >> (p))
#define bitt( r, p, v ) ((r&bitm( p )) == ((v)<<(p)))
#define bitsm( p, s ) ((((u64)1<<(s))-1) << (p))
#define bitsp( r, p, s, v ) { \
r &= ~bitsm( p, s ); \
r |= (((v) & bitsm(0,s)) << (p)); \
}
#define bitss( r, p, s ) r |= bitsm( p, s )
#define bitsr( r, p, s ) r &= ~bitsm( p, s )
#define bitsc( r, p, s ) r ^= bitsm( p, s )
#define bitsg( r, p, s ) ((r&bitsm( p, s )) >> (p))
#define bitst( r, p, s, v ) ((r&bitsm( p, s )) == ((v)<<(p)))
//==============================================================================
// bit operation
//==============================================================================
/*-------------------------------------------------------------------------*//**
* _BIT( n ) sets the bit at position "n"
* _BIT( n ) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*//*-------------------------------------------------------------------------*/
#undef _BIT
// Set bit macro
#define _BIT( n ) (1 << (n))
/*-------------------------------------------------------------------------*//**
* _SBF( f, v ) sets the bit field starting at position "f" to value "v".
* _SBF( f, v ) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*//*-------------------------------------------------------------------------*/
#undef _SBF
// Set bit field macro
#define _SBF( f, v ) ((v) << (f))
/*-------------------------------------------------------------------------*//**
* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*//*-------------------------------------------------------------------------*/
#undef _BITMASK
// Bitmask creation macro
#define _BITMASK( field_width ) (_BIT(field_width) - 1)
//==============================================================================
// array
//==============================================================================
// Number of elements in an array
#define NELEMENTS( array ) (sizeof (array) / sizeof (array[0]))
//==============================================================================
// max/min
//==============================================================================
// max
#if !defined( MAX )
#define MAX( a, b ) (((a) > (b)) ? (a) : (b))
#endif
// min
#if !defined( MIN )
#define MIN( a, b ) (((a) < (b)) ? (a) : (b))
#endif
//==============================================================================
// instruction
//==============================================================================
#define SYS_RESET() NVIC_SystemReset()
#define NOP() __NOP()
#define WFI() __WFI()
#define WFE() __WFE()
#define DI() __disable_irq() // reset value is "interrupt enable".
#define EI() __enable_irq() // reset value is "interrupt enable".
#define APB_NOP {unsigned long tmp = CIDR;}
//==============================================================================
// directive
//==============================================================================
// Static data/function define
#define STATIC static
// External data/function define
#define EXTERN extern
// inline function
#ifdef __CC_ARM
#define INLINE __inline
#else
#define INLINE inline
#endif
#ifdef __cplusplus
}
#endif
#endif /* AA_TYPES_H */

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Project/SDK_V2_5_0/Drivers/Include/A31G12x_hal_adc.h
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/***************************************************************************//**
* @file A31G12x_hal_adc.h
* @brief Contains all macro definitions and function prototypes
* support for adc firmware library on A31G12x
*
*
* @version 1.00
* @date 2020-05-29
* @author ABOV Application Team
*
* Copyright(C) 2019, ABOV Semiconductor
* All rights reserved.
*
********************************************************************************
* ABOV Disclaimer
*
*IMPORTANT NOTICE ? PLEASE READ CAREFULLY
*ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements,
*modifications, and improvements to ABOV products and/or to this document at any time without notice.
*ABOV does not give warranties as to the accuracy or completeness of the information included herein.
*Purchasers should obtain the latest relevant information of ABOV products before placing orders.
*Purchasers are entirely responsible for the choice, selection, and use of ABOV products and
*ABOV assumes no liability for application assistance or the design of purchasers' products. No license,
*express or implied, to any intellectual property rights is granted by ABOV herein.
*ABOV disclaims all express and implied warranties and shall not be responsible or
*liable for any injuries or damages related to use of ABOV products in such unauthorized applications.
*ABOV and the ABOV logo are trademarks of ABOV.
*All other product or service names are the property of their respective owners.
*Information in this document supersedes and replaces the information previously
*supplied in any former versions of this document.
*2020 ABOV Semiconductor All rights reserved
*
*//****************************************************************************/
#ifndef _ADC_H_
#define _ADC_H_
#include "A31G12x.h"
#include "A31G12x_hal_aa_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//******************************************************************************
// Constant
//******************************************************************************
//---------- ADC Trigger Signal Definition ----------
#define ADC_ADST (0x0uL << 11)
#define ADC_T10M (0x1uL << 11)
#define ADC_T11M (0x2uL << 11)
#define ADC_T12M (0x3uL << 11)
#define ADC_T30 (0x4uL << 11)
//---------- ADC Reference Selection Definition ----------
#define ADC_VDD (0x0uL << 10)
#define ADC_AVREF (0x1uL << 10)
//---------- ADC Convesion Start Definition ----------
//#define ADC_ADST (0x1uL << 8)
//---------- ADC Interrupt Enable/Disable Definition ----------
#define ADC_INTDIS (0x0uL << 5)
#define ADC_INTEN (0x1uL << 5)
//---------- ADC Channel Selection Definition ----------
#define ADC_AN0 (0x00uL << 0)
#define ADC_AN1 (0x01uL << 0)
#define ADC_AN2 (0x02uL << 0)
#define ADC_AN3 (0x03uL << 0)
#define ADC_AN4 (0x04uL << 0)
#define ADC_AN5 (0x05uL << 0)
#define ADC_AN6 (0x06uL << 0)
#define ADC_AN7 (0x07uL << 0)
#define ADC_AN8 (0x08uL << 0)
#define ADC_AN9 (0x09uL << 0)
#define ADC_AN10 (0x0auL << 0)
/*-------------------------------------------------------------------------*//**
* Macro defines for ADC Status register
*//*-------------------------------------------------------------------------*/
#define ADC_STAT_END ((1uL << 4))
#define ADC_REF_VDD 0 /**< ADC ref source VDD */
#define ADC_REF_AVREF 1 /**< ADC ref source AVREF */
#define ADC_TRIGGER_DISABLE 0 /**< Event Trigger Disabled/Soft-Trigger Only */
#define ADC_TRIGGER_TIMER10 1 /**< Timer10 Event Trigger */
#define ADC_TRIGGER_TIMER11 2 /**< Timer11 Event Trigger */
#define ADC_TRIGGER_TIMER12 3 /**< Timer12 Event Trigger */
#define ADC_TRIGGER_TIMER30 4 /**< Timer30 Event Trigger */
//******************************************************************************
// Type
//******************************************************************************
//==============================================================================
// Structure
//==============================================================================
typedef struct
{
/* ADC_CR */
uint32_t RefSel; /**< RestartEn = ENABLE or DISABLE */
uint32_t TrgSel;
/* ADC_PREDR */
uint32_t InClkDiv;
} ADC_CFG_Type;
//******************************************************************************
// Macro
//******************************************************************************
/*-------------------------------------------------------------------------*//**
* @brief ADC Enable
* @details This macro Enable ADC Block
*//*-------------------------------------------------------------------------*/
#define ADCEN() (ADC->CR_b.ADCEN = 1)
/*-------------------------------------------------------------------------*//**
* @brief ADC Disable
* @details This macro Disable ADC Block
*//*-------------------------------------------------------------------------*/
#define ADCDIS() (ADC->CR_b.ADCEN = 0)
/*-------------------------------------------------------------------------*//**
* @brief ADC Start bit set
* @details This macro starts ADC conversion
*//*-------------------------------------------------------------------------*/
#define ADCADST_Set() (ADC->CR_b.ADST = 1)
/*-------------------------------------------------------------------------*//**
* @brief ADC Start bit get
* @details This macro gets ADST bit
*//*-------------------------------------------------------------------------*/
#define ADCADST_Get() (ADC->CR_b.ADST)
/*-------------------------------------------------------------------------*//**
* @brief Get flags of ADC Interrupt
* @details This macro gets interrupt flag of ADC
*//*-------------------------------------------------------------------------*/
#define ADCInt_GetFg() (ADC->CR_b.ADCIFLAG)
/*-------------------------------------------------------------------------*//**
* @brief Clear flags of ADC Interrupt
* @details This macro gets interrupt flag of ADC
*//*-------------------------------------------------------------------------*/
#define ADCInt_ClrFg() (ADC->CR_b.ADCIFLAG = 1)
/*-------------------------------------------------------------------------*//**
* @brief Get data of ADC Conversion
* @details This macro gets data of ADC Conversion
*//*-------------------------------------------------------------------------*/
#define ADCData_Get() (ADC->DR)
/*-------------------------------------------------------------------------*//**
* Macro defines for ADC Data register
*//*-------------------------------------------------------------------------*/
/** When DONE is 1, this field contains result value of ADC conversion */
#define ADC_DR_RESULT( n ) ((n) & ADC_DR_ADDATA_Msk)
//******************************************************************************
// Function
//******************************************************************************
HAL_Status_Type HAL_ADC_Init( ADC_Type* ADCx, ADC_CFG_Type* ADC_Config );
HAL_Status_Type HAL_ADC_DeInit( ADC_Type* ADCx );
HAL_Status_Type HAL_ADC_ConfigInterrupt( ADC_Type* ADCx, FunctionalState NewState );
HAL_Status_Type HAL_ADC_ChannelSel( ADC_Type* ADCx, uint32_t Channel );
HAL_Status_Type HAL_ADC_Start( ADC_Type* ADCx );
HAL_Status_Type HAL_ADC_Stop( ADC_Type* ADCx );
HAL_Status_Type HAL_ADC_ClearStatus( ADC_Type* ADCx );
uint32_t HAL_ADC_GetStatus( ADC_Type* ADCx );
uint16_t HAL_ADC_GetData( ADC_Type* ADCx );
#ifdef __cplusplus
}
#endif
#endif /* _ADC_H_ */

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