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168 lines
7.1 KiB
168 lines
7.1 KiB
/**
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* @file icc_regs.h
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* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
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*/
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/* ****************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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*
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*************************************************************************** */
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#ifndef _ICC_REGS_H_
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#define _ICC_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined (__ICCARM__)
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#pragma system_include
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#endif
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#if defined (__CC_ARM)
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#pragma anon_unions
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#endif
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/// @cond
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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/**
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* @ingroup icc
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* @defgroup icc_registers ICC_Registers
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* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
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* @details Instruction Cache Controller Registers
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*/
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/**
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* @ingroup icc_registers
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* Structure type to access the ICC Registers.
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*/
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typedef struct {
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__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
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__I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> ICC MEMCFG Register */
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__R uint32_t rsv_0x8_0xff[62];
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__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
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__R uint32_t rsv_0x104_0x6ff[383];
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__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
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} mxc_icc_regs_t;
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/* Register offsets for module ICC */
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/**
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* @ingroup icc_registers
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* @defgroup ICC_Register_Offsets Register Offsets
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* @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address.
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* @{
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*/
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#define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */
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#define MXC_R_ICC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */
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#define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */
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#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */
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/**@} end of group icc_registers */
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/**
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* @ingroup icc_registers
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* @defgroup ICC_CACHE_ID ICC_CACHE_ID
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* @brief Cache ID Register.
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* @{
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*/
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#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
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#define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
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#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
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#define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
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#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
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#define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
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/**@} end of group ICC_CACHE_ID_Register */
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/**
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* @ingroup icc_registers
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* @defgroup ICC_MEMCFG ICC_MEMCFG
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* @brief Memory Configuration Register.
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* @{
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*/
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#define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
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#define MXC_F_ICC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
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#define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
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#define MXC_F_ICC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
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/**@} end of group ICC_MEMCFG_Register */
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/**
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* @ingroup icc_registers
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* @defgroup ICC_CACHE_CTRL ICC_CACHE_CTRL
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* @brief Cache Control and Status Register.
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* @{
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*/
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#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */
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#define MXC_F_ICC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */
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#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
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#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS Setting */
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#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
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#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN Setting */
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#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */
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#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */
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#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
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#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Setting */
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#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
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#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_READY Setting */
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/**@} end of group ICC_CACHE_CTRL_Register */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ICC_REGS_H_ */
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