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256 lines
15 KiB
256 lines
15 KiB
4 months ago
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/**
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* @file sir_regs.h
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* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
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*/
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/* ****************************************************************************
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* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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*
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*************************************************************************** */
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#ifndef _SIR_REGS_H_
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#define _SIR_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined (__ICCARM__)
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#pragma system_include
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#endif
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#if defined (__CC_ARM)
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#pragma anon_unions
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#endif
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/// @cond
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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/**
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* @ingroup sir
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* @defgroup sir_registers SIR_Registers
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* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
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* @details System Initialization Registers.
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*/
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/**
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* @ingroup sir_registers
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* Structure type to access the SIR Registers.
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*/
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typedef struct {
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__I uint32_t sistat; /**< <tt>\b 0x00:</tt> SIR SISTAT Register */
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__I uint32_t erraddr; /**< <tt>\b 0x04:</tt> SIR ERRADDR Register */
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__R uint32_t rsv_0x8_0xff[62];
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__I uint32_t fstat; /**< <tt>\b 0x100:</tt> SIR FSTAT Register */
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__I uint32_t sfstat; /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */
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} mxc_sir_regs_t;
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/* Register offsets for module SIR */
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/**
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* @ingroup sir_registers
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* @defgroup SIR_Register_Offsets Register Offsets
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* @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address.
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* @{
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*/
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#define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */
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#define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */
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#define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */
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#define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */
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/**@} end of group sir_registers */
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/**
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* @ingroup sir_registers
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* @defgroup SIR_SISTAT SIR_SISTAT
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* @brief System Initialization Status Register.
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* @{
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*/
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#define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */
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#define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */
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#define MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET ((uint32_t)0x0UL) /**< SISTAT_MAGIC_MAGICNOTSET Value */
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#define MXC_S_SIR_SISTAT_MAGIC_MAGICNOTSET (MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICNOTSET Setting */
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#define MXC_V_SIR_SISTAT_MAGIC_MAGICSET ((uint32_t)0x1UL) /**< SISTAT_MAGIC_MAGICSET Value */
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#define MXC_S_SIR_SISTAT_MAGIC_MAGICSET (MXC_V_SIR_SISTAT_MAGIC_MAGICSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICSET Setting */
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#define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */
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#define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */
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#define MXC_V_SIR_SISTAT_CRCERR_NOERROR ((uint32_t)0x0UL) /**< SISTAT_CRCERR_NOERROR Value */
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#define MXC_S_SIR_SISTAT_CRCERR_NOERROR (MXC_V_SIR_SISTAT_CRCERR_NOERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_NOERROR Setting */
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#define MXC_V_SIR_SISTAT_CRCERR_ERROR ((uint32_t)0x1UL) /**< SISTAT_CRCERR_ERROR Value */
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#define MXC_S_SIR_SISTAT_CRCERR_ERROR (MXC_V_SIR_SISTAT_CRCERR_ERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_ERROR Setting */
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/**@} end of group SIR_SISTAT_Register */
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/**
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* @ingroup sir_registers
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* @defgroup SIR_ERRADDR SIR_ERRADDR
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* @brief Read-only field set by the SIB block if a CRC error occurs during the read of
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* the OTP memory. Contains the failing address in OTP memory (when CRCERR equals
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* 1).
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* @{
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*/
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#define MXC_F_SIR_ERRADDR_ERRADDR_POS 0 /**< ERRADDR_ERRADDR Position */
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#define MXC_F_SIR_ERRADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ERRADDR_ERRADDR_POS)) /**< ERRADDR_ERRADDR Mask */
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/**@} end of group SIR_ERRADDR_Register */
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/**
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* @ingroup sir_registers
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* @defgroup SIR_FSTAT SIR_FSTAT
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* @brief funcstat register.
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* @{
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*/
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#define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */
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#define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */
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#define MXC_V_SIR_FSTAT_FPU_NO ((uint32_t)0x0UL) /**< FSTAT_FPU_NO Value */
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#define MXC_S_SIR_FSTAT_FPU_NO (MXC_V_SIR_FSTAT_FPU_NO << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_NO Setting */
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#define MXC_V_SIR_FSTAT_FPU_YES ((uint32_t)0x1UL) /**< FSTAT_FPU_YES Value */
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#define MXC_S_SIR_FSTAT_FPU_YES (MXC_V_SIR_FSTAT_FPU_YES << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_YES Setting */
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#define MXC_F_SIR_FSTAT_USB_POS 1 /**< FSTAT_USB Position */
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#define MXC_F_SIR_FSTAT_USB ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */
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#define MXC_V_SIR_FSTAT_USB_NO ((uint32_t)0x0UL) /**< FSTAT_USB_NO Value */
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#define MXC_S_SIR_FSTAT_USB_NO (MXC_V_SIR_FSTAT_USB_NO << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_NO Setting */
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#define MXC_V_SIR_FSTAT_USB_YES ((uint32_t)0x1UL) /**< FSTAT_USB_YES Value */
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#define MXC_S_SIR_FSTAT_USB_YES (MXC_V_SIR_FSTAT_USB_YES << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_YES Setting */
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#define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */
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#define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */
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#define MXC_V_SIR_FSTAT_ADC_NO ((uint32_t)0x0UL) /**< FSTAT_ADC_NO Value */
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#define MXC_S_SIR_FSTAT_ADC_NO (MXC_V_SIR_FSTAT_ADC_NO << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_NO Setting */
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#define MXC_V_SIR_FSTAT_ADC_YES ((uint32_t)0x1UL) /**< FSTAT_ADC_YES Value */
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#define MXC_S_SIR_FSTAT_ADC_YES (MXC_V_SIR_FSTAT_ADC_YES << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_YES Setting */
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#define MXC_F_SIR_FSTAT_XIP_POS 3 /**< FSTAT_XIP Position */
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#define MXC_F_SIR_FSTAT_XIP ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_XIP_POS)) /**< FSTAT_XIP Mask */
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#define MXC_V_SIR_FSTAT_XIP_NO ((uint32_t)0x0UL) /**< FSTAT_XIP_NO Value */
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#define MXC_S_SIR_FSTAT_XIP_NO (MXC_V_SIR_FSTAT_XIP_NO << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_NO Setting */
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#define MXC_V_SIR_FSTAT_XIP_YES ((uint32_t)0x1UL) /**< FSTAT_XIP_YES Value */
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#define MXC_S_SIR_FSTAT_XIP_YES (MXC_V_SIR_FSTAT_XIP_YES << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_YES Setting */
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#define MXC_F_SIR_FSTAT_PBM_POS 4 /**< FSTAT_PBM Position */
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#define MXC_F_SIR_FSTAT_PBM ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_PBM_POS)) /**< FSTAT_PBM Mask */
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#define MXC_V_SIR_FSTAT_PBM_NO ((uint32_t)0x0UL) /**< FSTAT_PBM_NO Value */
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#define MXC_S_SIR_FSTAT_PBM_NO (MXC_V_SIR_FSTAT_PBM_NO << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_NO Setting */
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#define MXC_V_SIR_FSTAT_PBM_YES ((uint32_t)0x1UL) /**< FSTAT_PBM_YES Value */
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#define MXC_S_SIR_FSTAT_PBM_YES (MXC_V_SIR_FSTAT_PBM_YES << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_YES Setting */
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#define MXC_F_SIR_FSTAT_HBC_POS 5 /**< FSTAT_HBC Position */
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#define MXC_F_SIR_FSTAT_HBC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_HBC_POS)) /**< FSTAT_HBC Mask */
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#define MXC_V_SIR_FSTAT_HBC_NO ((uint32_t)0x0UL) /**< FSTAT_HBC_NO Value */
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#define MXC_S_SIR_FSTAT_HBC_NO (MXC_V_SIR_FSTAT_HBC_NO << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_NO Setting */
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#define MXC_V_SIR_FSTAT_HBC_YES ((uint32_t)0x1UL) /**< FSTAT_HBC_YES Value */
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#define MXC_S_SIR_FSTAT_HBC_YES (MXC_V_SIR_FSTAT_HBC_YES << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_YES Setting */
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#define MXC_F_SIR_FSTAT_SDHC_POS 6 /**< FSTAT_SDHC Position */
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#define MXC_F_SIR_FSTAT_SDHC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SDHC_POS)) /**< FSTAT_SDHC Mask */
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#define MXC_V_SIR_FSTAT_SDHC_NO ((uint32_t)0x0UL) /**< FSTAT_SDHC_NO Value */
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#define MXC_S_SIR_FSTAT_SDHC_NO (MXC_V_SIR_FSTAT_SDHC_NO << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_NO Setting */
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#define MXC_V_SIR_FSTAT_SDHC_YES ((uint32_t)0x1UL) /**< FSTAT_SDHC_YES Value */
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#define MXC_S_SIR_FSTAT_SDHC_YES (MXC_V_SIR_FSTAT_SDHC_YES << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_YES Setting */
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#define MXC_F_SIR_FSTAT_SMPHR_POS 7 /**< FSTAT_SMPHR Position */
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#define MXC_F_SIR_FSTAT_SMPHR ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */
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#define MXC_V_SIR_FSTAT_SMPHR_NO ((uint32_t)0x0UL) /**< FSTAT_SMPHR_NO Value */
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#define MXC_S_SIR_FSTAT_SMPHR_NO (MXC_V_SIR_FSTAT_SMPHR_NO << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_NO Setting */
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#define MXC_V_SIR_FSTAT_SMPHR_YES ((uint32_t)0x1UL) /**< FSTAT_SMPHR_YES Value */
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#define MXC_S_SIR_FSTAT_SMPHR_YES (MXC_V_SIR_FSTAT_SMPHR_YES << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_YES Setting */
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#define MXC_F_SIR_FSTAT_SCACHE_POS 8 /**< FSTAT_SCACHE Position */
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#define MXC_F_SIR_FSTAT_SCACHE ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SCACHE_POS)) /**< FSTAT_SCACHE Mask */
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#define MXC_V_SIR_FSTAT_SCACHE_NO ((uint32_t)0x0UL) /**< FSTAT_SCACHE_NO Value */
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#define MXC_S_SIR_FSTAT_SCACHE_NO (MXC_V_SIR_FSTAT_SCACHE_NO << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_NO Setting */
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#define MXC_V_SIR_FSTAT_SCACHE_YES ((uint32_t)0x1UL) /**< FSTAT_SCACHE_YES Value */
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#define MXC_S_SIR_FSTAT_SCACHE_YES (MXC_V_SIR_FSTAT_SCACHE_YES << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_YES Setting */
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/**@} end of group SIR_FSTAT_Register */
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/**
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* @ingroup sir_registers
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* @defgroup SIR_SFSTAT SIR_SFSTAT
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* @brief secfuncstat register.
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* @{
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*/
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#define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */
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#define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */
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#define MXC_V_SIR_SFSTAT_TRNG_NO ((uint32_t)0x0UL) /**< SFSTAT_TRNG_NO Value */
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#define MXC_S_SIR_SFSTAT_TRNG_NO (MXC_V_SIR_SFSTAT_TRNG_NO << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_NO Setting */
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#define MXC_V_SIR_SFSTAT_TRNG_YES ((uint32_t)0x1UL) /**< SFSTAT_TRNG_YES Value */
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#define MXC_S_SIR_SFSTAT_TRNG_YES (MXC_V_SIR_SFSTAT_TRNG_YES << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_YES Setting */
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#define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */
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#define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */
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#define MXC_V_SIR_SFSTAT_AES_NO ((uint32_t)0x0UL) /**< SFSTAT_AES_NO Value */
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#define MXC_S_SIR_SFSTAT_AES_NO (MXC_V_SIR_SFSTAT_AES_NO << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_NO Setting */
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#define MXC_V_SIR_SFSTAT_AES_YES ((uint32_t)0x1UL) /**< SFSTAT_AES_YES Value */
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#define MXC_S_SIR_SFSTAT_AES_YES (MXC_V_SIR_SFSTAT_AES_YES << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_YES Setting */
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#define MXC_F_SIR_SFSTAT_SHA_POS 4 /**< SFSTAT_SHA Position */
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#define MXC_F_SIR_SFSTAT_SHA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHA_POS)) /**< SFSTAT_SHA Mask */
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#define MXC_V_SIR_SFSTAT_SHA_NO ((uint32_t)0x0UL) /**< SFSTAT_SHA_NO Value */
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#define MXC_S_SIR_SFSTAT_SHA_NO (MXC_V_SIR_SFSTAT_SHA_NO << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_NO Setting */
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#define MXC_V_SIR_SFSTAT_SHA_YES ((uint32_t)0x1UL) /**< SFSTAT_SHA_YES Value */
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#define MXC_S_SIR_SFSTAT_SHA_YES (MXC_V_SIR_SFSTAT_SHA_YES << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_YES Setting */
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#define MXC_F_SIR_SFSTAT_MAA_POS 5 /**< SFSTAT_MAA Position */
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#define MXC_F_SIR_SFSTAT_MAA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_MAA_POS)) /**< SFSTAT_MAA Mask */
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#define MXC_V_SIR_SFSTAT_MAA_NO ((uint32_t)0x0UL) /**< SFSTAT_MAA_NO Value */
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#define MXC_S_SIR_SFSTAT_MAA_NO (MXC_V_SIR_SFSTAT_MAA_NO << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_NO Setting */
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#define MXC_V_SIR_SFSTAT_MAA_YES ((uint32_t)0x1UL) /**< SFSTAT_MAA_YES Value */
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#define MXC_S_SIR_SFSTAT_MAA_YES (MXC_V_SIR_SFSTAT_MAA_YES << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_YES Setting */
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/**@} end of group SIR_SFSTAT_Register */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SIR_REGS_H_ */
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